diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch b/common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch new file mode 100644 index 00000000..2e49f7d3 --- /dev/null +++ b/common/recipes-kernel/linux/files/0494-drm-amdgpu-gfx-adjust-gfx_v8_0_send_serdes_cmd-for-S.patch @@ -0,0 +1,58 @@ +From 136df7832570112848b7c6f406a7a95f85180d5b Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 7 Apr 2016 23:16:00 -0400 +Subject: [PATCH 0494/1110] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for + ST + +Acked-by: Tom St Denis <tom.stdenis@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 +++++++++++++++++------ + 1 file changed, 17 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index edd63e7..14c75fe 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -4292,7 +4292,8 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev, + WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); + + data = RREG32(mmRLC_SERDES_WR_CTRL); +- data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | ++ if (adev->asic_type == CHIP_STONEY) ++ data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | + RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | + RLC_SERDES_WR_CTRL__P1_SELECT_MASK | + RLC_SERDES_WR_CTRL__P2_SELECT_MASK | +@@ -4300,13 +4301,23 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev, + RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | + RLC_SERDES_WR_CTRL__POWER_UP_MASK | + RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | +- RLC_SERDES_WR_CTRL__BPM_DATA_MASK | +- RLC_SERDES_WR_CTRL__REG_ADDR_MASK | + RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); ++ else ++ data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | ++ RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | ++ RLC_SERDES_WR_CTRL__P1_SELECT_MASK | ++ RLC_SERDES_WR_CTRL__P2_SELECT_MASK | ++ RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK | ++ RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | ++ RLC_SERDES_WR_CTRL__POWER_UP_MASK | ++ RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | ++ RLC_SERDES_WR_CTRL__BPM_DATA_MASK | ++ RLC_SERDES_WR_CTRL__REG_ADDR_MASK | ++ RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); + data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK | +- (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) | +- (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) | +- (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); ++ (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) | ++ (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) | ++ (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); + + WREG32(mmRLC_SERDES_WR_CTRL, data); + } +-- +2.7.4 + |