diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch b/common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch new file mode 100644 index 00000000..e373d350 --- /dev/null +++ b/common/recipes-kernel/linux/files/0491-drm-amdgpu-common-add-proper-CG-flags-for-fiji.patch @@ -0,0 +1,100 @@ +From bd0f234e6e86704d66c4719d7c1273a1feb01c6e Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 8 Apr 2016 00:52:58 -0400 +Subject: [PATCH 0491/1110] drm/amdgpu/common: add proper CG flags for fiji + +We were already enabling these CG features, this uses +the standard interface for doing so. + +Acked-by: Tom St Denis <tom.stdenis@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vi.c | 22 +++++++++++++--------- + 1 file changed, 13 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c +index 5759504..ea9edf4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/vi.c +@@ -1085,7 +1085,11 @@ static int vi_common_early_init(void *handle) + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_SDMA_MGCG | +- AMD_CG_SUPPORT_SDMA_LS; ++ AMD_CG_SUPPORT_SDMA_LS | ++ AMD_CG_SUPPORT_BIF_LS | ++ AMD_CG_SUPPORT_HDP_MGCG | ++ AMD_CG_SUPPORT_HDP_LS | ++ AMD_CG_SUPPORT_ROM_MGCG; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x3c; + break; +@@ -1188,13 +1192,13 @@ static int vi_common_soft_reset(void *handle) + } + + static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, +- bool enable) ++ bool enable) + { + uint32_t temp, data; + + temp = data = RREG32_PCIE(ixPCIE_CNTL2); + +- if (enable) ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) + data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; +@@ -1208,13 +1212,13 @@ static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, + } + + static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, +- bool enable) ++ bool enable) + { + uint32_t temp, data; + + temp = data = RREG32(mmHDP_HOST_PATH_CNTL); + +- if (enable) ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) + data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; + else + data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; +@@ -1230,7 +1234,7 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev, + + temp = data = RREG32(mmHDP_MEM_POWER_LS); + +- if (enable) ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) + data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; + else + data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; +@@ -1240,13 +1244,13 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev, + } + + static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, +- bool enable) ++ bool enable) + { + uint32_t temp, data; + + temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); + +- if (enable) ++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) + data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | + CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); + else +@@ -1258,7 +1262,7 @@ static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev + } + + static int vi_common_set_clockgating_state(void *handle, +- enum amd_clockgating_state state) ++ enum amd_clockgating_state state) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +-- +2.7.4 + |