diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch | 840 |
1 files changed, 840 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch b/common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch new file mode 100644 index 00000000..09a41286 --- /dev/null +++ b/common/recipes-kernel/linux/files/0478-drm-amd-make-a-type-safe-cgs_device-struct.-v2.patch @@ -0,0 +1,840 @@ +From 674cd6d2ced8478f7ed20d5f15c621cc649cf7b1 Mon Sep 17 00:00:00 2001 +From: Dave Airlie <airlied@redhat.com> +Date: Tue, 12 Apr 2016 13:25:48 +1000 +Subject: [PATCH 0478/1110] drm/amd: make a type-safe cgs_device struct. (v2) + +This is just a type-safety things to avoid everyone taking void *, +it doesn't change anything. + +v2: agd5f: split out the dal changes into a separate patch. + +Signed-off-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/acp/acp_hw.c | 2 +- + drivers/gpu/drm/amd/acp/include/acp_gfx_if.h | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 92 ++++++++++++++-------------- + drivers/gpu/drm/amd/include/cgs_common.h | 76 ++++++++++++----------- + drivers/gpu/drm/amd/include/cgs_linux.h | 6 +- + 7 files changed, 93 insertions(+), 98 deletions(-) + +diff --git a/drivers/gpu/drm/amd/acp/acp_hw.c b/drivers/gpu/drm/amd/acp/acp_hw.c +index 7af83f1..c7d7205 100644 +--- a/drivers/gpu/drm/amd/acp/acp_hw.c ++++ b/drivers/gpu/drm/amd/acp/acp_hw.c +@@ -34,7 +34,7 @@ + + #define mmACP_AZALIA_I2S_SELECT 0x51d4 + +-int amd_acp_hw_init(void *cgs_device, ++int amd_acp_hw_init(struct cgs_device *cgs_device, + unsigned acp_version_major, unsigned acp_version_minor) + { + unsigned int acp_mode = ACP_MODE_I2S; +diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h +index bccf47b..a72ddb2 100644 +--- a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h ++++ b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h +@@ -28,7 +28,7 @@ + #include "cgs_linux.h" + #include "cgs_common.h" + +-int amd_acp_hw_init(void *cgs_device, ++int amd_acp_hw_init(struct cgs_device *cgs_device, + unsigned acp_version_major, unsigned acp_version_minor); + + #endif /* _ACP_GFX_IF_H */ +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index bd80ea5..47a3c8f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1872,15 +1872,8 @@ struct amdgpu_atcs { + /* + * CGS + */ +-void *amdgpu_cgs_create_device(struct amdgpu_device *adev); +-void amdgpu_cgs_destroy_device(void *cgs_device); +- +- +-/* +- * CGS +- */ +-void *amdgpu_cgs_create_device(struct amdgpu_device *adev); +-void amdgpu_cgs_destroy_device(void *cgs_device); ++struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); ++void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); + + + /* GPU virtualization */ +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h +index f6e32a6..8a39631 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h +@@ -30,7 +30,7 @@ + + struct amdgpu_acp { + struct device *parent; +- void *cgs_device; ++ struct cgs_device *cgs_device; + struct amd_acp_private *private; + struct mfd_cell *acp_cell; + struct resource *acp_res; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +index 6043dc7..8b653f2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +@@ -42,7 +42,7 @@ struct amdgpu_cgs_device { + struct amdgpu_device *adev = \ + ((struct amdgpu_cgs_device *)cgs_device)->adev + +-static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type, ++static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, + uint64_t *mc_start, uint64_t *mc_size, + uint64_t *mem_size) + { +@@ -73,7 +73,7 @@ static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type, + return 0; + } + +-static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem, ++static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem, + uint64_t size, + uint64_t min_offset, uint64_t max_offset, + cgs_handle_t *kmem_handle, uint64_t *mcaddr) +@@ -102,7 +102,7 @@ static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem, + return ret; + } + +-static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle) ++static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle) + { + struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle; + +@@ -118,7 +118,7 @@ static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle) + return 0; + } + +-static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, ++static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, + enum cgs_gpu_mem_type type, + uint64_t size, uint64_t align, + uint64_t min_offset, uint64_t max_offset, +@@ -208,7 +208,7 @@ static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, + return ret; + } + +-static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) ++static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle) + { + struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; + +@@ -225,7 +225,7 @@ static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) + return 0; + } + +-static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle, ++static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle, + uint64_t *mcaddr) + { + int r; +@@ -246,7 +246,7 @@ static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle, + return r; + } + +-static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) ++static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle) + { + int r; + struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; +@@ -258,7 +258,7 @@ static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) + return r; + } + +-static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle, ++static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle, + void **map) + { + int r; +@@ -271,7 +271,7 @@ static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle, + return r; + } + +-static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) ++static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle) + { + int r; + struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; +@@ -283,20 +283,20 @@ static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) + return r; + } + +-static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset) ++static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset) + { + CGS_FUNC_ADEV; + return RREG32(offset); + } + +-static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset, ++static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset, + uint32_t value) + { + CGS_FUNC_ADEV; + WREG32(offset, value); + } + +-static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device, ++static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device, + enum cgs_ind_reg space, + unsigned index) + { +@@ -320,7 +320,7 @@ static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device, + return 0; + } + +-static void amdgpu_cgs_write_ind_register(void *cgs_device, ++static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, + enum cgs_ind_reg space, + unsigned index, uint32_t value) + { +@@ -343,7 +343,7 @@ static void amdgpu_cgs_write_ind_register(void *cgs_device, + WARN(1, "Invalid indirect register space"); + } + +-static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr) ++static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr) + { + CGS_FUNC_ADEV; + uint8_t val; +@@ -353,7 +353,7 @@ static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr) + return val; + } + +-static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr) ++static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr) + { + CGS_FUNC_ADEV; + uint16_t val; +@@ -363,7 +363,7 @@ static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr) + return val; + } + +-static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device, ++static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device, + unsigned addr) + { + CGS_FUNC_ADEV; +@@ -374,7 +374,7 @@ static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device, + return val; + } + +-static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr, ++static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr, + uint8_t value) + { + CGS_FUNC_ADEV; +@@ -382,7 +382,7 @@ static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr, + WARN(ret, "pci_write_config_byte error"); + } + +-static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr, ++static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr, + uint16_t value) + { + CGS_FUNC_ADEV; +@@ -390,7 +390,7 @@ static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr, + WARN(ret, "pci_write_config_word error"); + } + +-static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, ++static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr, + uint32_t value) + { + CGS_FUNC_ADEV; +@@ -399,7 +399,7 @@ static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, + } + + +-static int amdgpu_cgs_get_pci_resource(void *cgs_device, ++static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device, + enum cgs_resource_type resource_type, + uint64_t size, + uint64_t offset, +@@ -433,7 +433,7 @@ static int amdgpu_cgs_get_pci_resource(void *cgs_device, + } + } + +-static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, ++static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device, + unsigned table, uint16_t *size, + uint8_t *frev, uint8_t *crev) + { +@@ -449,7 +449,7 @@ static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, + return NULL; + } + +-static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table, ++static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table, + uint8_t *frev, uint8_t *crev) + { + CGS_FUNC_ADEV; +@@ -462,7 +462,7 @@ static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table, + return -EINVAL; + } + +-static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table, ++static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table, + void *args) + { + CGS_FUNC_ADEV; +@@ -471,33 +471,33 @@ static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table, + adev->mode_info.atom_context, table, args); + } + +-static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request) ++static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request) + { + /* TODO */ + return 0; + } + +-static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request) ++static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request) + { + /* TODO */ + return 0; + } + +-static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request, ++static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request, + int active) + { + /* TODO */ + return 0; + } + +-static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request, ++static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request, + enum cgs_clock clock, unsigned freq) + { + /* TODO */ + return 0; + } + +-static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request, ++static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request, + enum cgs_engine engine, int powered) + { + /* TODO */ +@@ -506,7 +506,7 @@ static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request, + + + +-static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device, ++static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device, + enum cgs_clock clock, + struct cgs_clock_limits *limits) + { +@@ -514,7 +514,7 @@ static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device, + return 0; + } + +-static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask, ++static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask, + const uint32_t *voltages) + { + DRM_ERROR("not implemented"); +@@ -565,7 +565,7 @@ static const struct amdgpu_irq_src_funcs cgs_irq_funcs = { + .process = cgs_process_irq, + }; + +-static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id, ++static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id, + unsigned num_types, + cgs_irq_source_set_func_t set, + cgs_irq_handler_func_t handler, +@@ -600,19 +600,19 @@ static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id, + return ret; + } + +-static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type) ++static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type) + { + CGS_FUNC_ADEV; + return amdgpu_irq_get(adev, adev->irq.sources[src_id], type); + } + +-static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type) ++static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type) + { + CGS_FUNC_ADEV; + return amdgpu_irq_put(adev, adev->irq.sources[src_id], type); + } + +-int amdgpu_cgs_set_clockgating_state(void *cgs_device, ++int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state) + { +@@ -633,7 +633,7 @@ int amdgpu_cgs_set_clockgating_state(void *cgs_device, + return r; + } + +-int amdgpu_cgs_set_powergating_state(void *cgs_device, ++int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device, + enum amd_ip_block_type block_type, + enum amd_powergating_state state) + { +@@ -655,7 +655,7 @@ int amdgpu_cgs_set_powergating_state(void *cgs_device, + } + + +-static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type) ++static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) + { + CGS_FUNC_ADEV; + enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM; +@@ -695,7 +695,7 @@ static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type) + return result; + } + +-static int amdgpu_cgs_get_firmware_info(void *cgs_device, ++static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, + enum cgs_ucode_id type, + struct cgs_firmware_info *info) + { +@@ -774,7 +774,7 @@ static int amdgpu_cgs_get_firmware_info(void *cgs_device, + return 0; + } + +-static int amdgpu_cgs_query_system_info(void *cgs_device, ++static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, + struct cgs_system_info *sys_info) + { + CGS_FUNC_ADEV; +@@ -808,7 +808,7 @@ static int amdgpu_cgs_query_system_info(void *cgs_device, + return 0; + } + +-static int amdgpu_cgs_get_active_displays_info(void *cgs_device, ++static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, + struct cgs_display_info *info) + { + CGS_FUNC_ADEV; +@@ -851,7 +851,7 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device, + } + + +-static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled) ++static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled) + { + CGS_FUNC_ADEV; + +@@ -867,7 +867,7 @@ static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled) + */ + + #if defined(CONFIG_ACPI) +-static int amdgpu_cgs_acpi_eval_object(void *cgs_device, ++static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device, + struct cgs_acpi_method_info *info) + { + CGS_FUNC_ADEV; +@@ -1030,14 +1030,14 @@ error: + return result; + } + #else +-static int amdgpu_cgs_acpi_eval_object(void *cgs_device, ++static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device, + struct cgs_acpi_method_info *info) + { + return -EIO; + } + #endif + +-int amdgpu_cgs_call_acpi_method(void *cgs_device, ++int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device, + uint32_t acpi_method, + uint32_t acpi_function, + void *pinput, void *poutput, +@@ -1121,7 +1121,7 @@ static const struct cgs_os_ops amdgpu_cgs_os_ops = { + amdgpu_cgs_irq_put + }; + +-void *amdgpu_cgs_create_device(struct amdgpu_device *adev) ++struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) + { + struct amdgpu_cgs_device *cgs_device = + kmalloc(sizeof(*cgs_device), GFP_KERNEL); +@@ -1135,10 +1135,10 @@ void *amdgpu_cgs_create_device(struct amdgpu_device *adev) + cgs_device->base.os_ops = &amdgpu_cgs_os_ops; + cgs_device->adev = adev; + +- return cgs_device; ++ return (struct cgs_device *)cgs_device; + } + +-void amdgpu_cgs_destroy_device(void *cgs_device) ++void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device) + { + kfree(cgs_device); + } +diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h +index ab84d49..ca1e229 100644 +--- a/drivers/gpu/drm/amd/include/cgs_common.h ++++ b/drivers/gpu/drm/amd/include/cgs_common.h +@@ -26,6 +26,8 @@ + + #include "amd_shared.h" + ++struct cgs_device; ++ + /** + * enum cgs_gpu_mem_type - GPU memory types + */ +@@ -223,7 +225,7 @@ struct cgs_acpi_method_info { + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type, ++typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, + uint64_t *mc_start, uint64_t *mc_size, + uint64_t *mem_size); + +@@ -239,7 +241,7 @@ typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size, ++typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size, + uint64_t min_offset, uint64_t max_offset, + cgs_handle_t *kmem_handle, uint64_t *mcaddr); + +@@ -250,7 +252,7 @@ typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle); ++typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle); + + /** + * cgs_alloc_gpu_mem() - Allocate GPU memory +@@ -279,7 +281,7 @@ typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle); + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type, ++typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, + uint64_t size, uint64_t align, + uint64_t min_offset, uint64_t max_offset, + cgs_handle_t *handle); +@@ -291,7 +293,7 @@ typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); ++typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); + + /** + * cgs_gmap_gpu_mem() - GPU-map GPU memory +@@ -303,7 +305,7 @@ typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, ++typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, + uint64_t *mcaddr); + + /** +@@ -315,7 +317,7 @@ typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); ++typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); + + /** + * cgs_kmap_gpu_mem() - Kernel-map GPU memory +@@ -326,7 +328,7 @@ typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, ++typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, + void **map); + + /** +@@ -336,7 +338,7 @@ typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); ++typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); + + /** + * cgs_read_register() - Read an MMIO register +@@ -345,7 +347,7 @@ typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); + * + * Return: register value + */ +-typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset); ++typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); + + /** + * cgs_write_register() - Write an MMIO register +@@ -353,7 +355,7 @@ typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset); + * @offset: register offset + * @value: register value + */ +-typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset, ++typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, + uint32_t value); + + /** +@@ -363,7 +365,7 @@ typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset, + * + * Return: register value + */ +-typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, ++typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, + unsigned index); + + /** +@@ -372,7 +374,7 @@ typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg s + * @offset: register offset + * @value: register value + */ +-typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, ++typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, + unsigned index, uint32_t value); + + /** +@@ -382,7 +384,7 @@ typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg spac + * + * Return: Value read + */ +-typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr); ++typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr); + + /** + * cgs_read_pci_config_word() - Read word from PCI configuration space +@@ -391,7 +393,7 @@ typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr); + * + * Return: Value read + */ +-typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr); ++typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr); + + /** + * cgs_read_pci_config_dword() - Read dword from PCI configuration space +@@ -400,7 +402,7 @@ typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr); + * + * Return: Value read + */ +-typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device, ++typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device, + unsigned addr); + + /** +@@ -409,7 +411,7 @@ typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device, + * @addr: address + * @value: value to write + */ +-typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr, ++typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr, + uint8_t value); + + /** +@@ -418,7 +420,7 @@ typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr, + * @addr: address, must be word-aligned + * @value: value to write + */ +-typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, ++typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr, + uint16_t value); + + /** +@@ -427,7 +429,7 @@ typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, + * @addr: address, must be dword-aligned + * @value: value to write + */ +-typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, ++typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr, + uint32_t value); + + +@@ -441,7 +443,7 @@ typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_get_pci_resource_t)(void *cgs_device, ++typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, + enum cgs_resource_type resource_type, + uint64_t size, + uint64_t offset, +@@ -458,7 +460,7 @@ typedef int (*cgs_get_pci_resource_t)(void *cgs_device, + * Return: Pointer to start of the table, or NULL on failure + */ + typedef const void *(*cgs_atom_get_data_table_t)( +- void *cgs_device, unsigned table, ++ struct cgs_device *cgs_device, unsigned table, + uint16_t *size, uint8_t *frev, uint8_t *crev); + + /** +@@ -470,7 +472,7 @@ typedef const void *(*cgs_atom_get_data_table_t)( + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table, ++typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, + uint8_t *frev, uint8_t *crev); + + /** +@@ -481,7 +483,7 @@ typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device, ++typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, + unsigned table, void *args); + + /** +@@ -491,7 +493,7 @@ typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request); ++typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request); + + /** + * cgs_destroy_pm_request() - Destroy a power management request +@@ -500,7 +502,7 @@ typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request); + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request); ++typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request); + + /** + * cgs_set_pm_request() - Activate or deactiveate a PM request +@@ -516,7 +518,7 @@ typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request); + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request, ++typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request, + int active); + + /** +@@ -528,7 +530,7 @@ typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request, ++typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request, + enum cgs_clock clock, unsigned freq); + + /** +@@ -540,7 +542,7 @@ typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request, ++typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request, + enum cgs_engine engine, int powered); + + /** +@@ -551,7 +553,7 @@ typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device, ++typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device, + enum cgs_clock clock, + struct cgs_clock_limits *limits); + +@@ -563,7 +565,7 @@ typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask, ++typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask, + const uint32_t *voltages); + /** + * cgs_get_firmware_info - Get the firmware information from core driver +@@ -573,25 +575,25 @@ typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_get_firmware_info)(void *cgs_device, ++typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, + enum cgs_ucode_id type, + struct cgs_firmware_info *info); + +-typedef int(*cgs_set_powergating_state)(void *cgs_device, ++typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, + enum amd_ip_block_type block_type, + enum amd_powergating_state state); + +-typedef int(*cgs_set_clockgating_state)(void *cgs_device, ++typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state); + + typedef int(*cgs_get_active_displays_info)( +- void *cgs_device, ++ struct cgs_device *cgs_device, + struct cgs_display_info *info); + +-typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled); ++typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); + +-typedef int (*cgs_call_acpi_method)(void *cgs_device, ++typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, + uint32_t acpi_method, + uint32_t acpi_function, + void *pinput, void *poutput, +@@ -599,7 +601,7 @@ typedef int (*cgs_call_acpi_method)(void *cgs_device, + uint32_t input_size, + uint32_t output_size); + +-typedef int (*cgs_query_system_info)(void *cgs_device, ++typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, + struct cgs_system_info *sys_info); + + struct cgs_ops { +diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h +index 3b47ae3..ca4f600 100644 +--- a/drivers/gpu/drm/amd/include/cgs_linux.h ++++ b/drivers/gpu/drm/amd/include/cgs_linux.h +@@ -66,7 +66,7 @@ typedef int (*cgs_irq_handler_func_t)(void *private_data, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned src_id, ++typedef int (*cgs_add_irq_source_t)(struct cgs_device *cgs_device, unsigned src_id, + unsigned num_types, + cgs_irq_source_set_func_t set, + cgs_irq_handler_func_t handler, +@@ -83,7 +83,7 @@ typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned src_id, + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type); ++typedef int (*cgs_irq_get_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type); + + /** + * cgs_irq_put() - Indicate IRQ source is no longer needed +@@ -98,7 +98,7 @@ typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type); + * + * Return: 0 on success, -errno otherwise + */ +-typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned src_id, unsigned type); ++typedef int (*cgs_irq_put_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type); + + struct cgs_os_ops { + /* IRQ handling */ +-- +2.7.4 + |