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-rw-r--r--common/recipes-kernel/linux/files/0465-drm-amd-powerplay-add-deep-sleep-divider-id-into-DPM.patch62
1 files changed, 0 insertions, 62 deletions
diff --git a/common/recipes-kernel/linux/files/0465-drm-amd-powerplay-add-deep-sleep-divider-id-into-DPM.patch b/common/recipes-kernel/linux/files/0465-drm-amd-powerplay-add-deep-sleep-divider-id-into-DPM.patch
deleted file mode 100644
index 43fed0b3..00000000
--- a/common/recipes-kernel/linux/files/0465-drm-amd-powerplay-add-deep-sleep-divider-id-into-DPM.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 9fedb3f1bb29f2572495d469a6cc7500d91c9c81 Mon Sep 17 00:00:00 2001
-From: Eric Huang <JinHuiEric.Huang@amd.com>
-Date: Wed, 30 Mar 2016 16:30:12 -0400
-Subject: [PATCH 0465/1110] drm/amd/powerplay: add deep sleep divider id into
- DPM table on Tonga
-
-Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
----
- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 29 +++++++++++++++++++----
- 1 file changed, 24 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-index 0d5d837..fee7835 100644
---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
-@@ -2415,6 +2415,25 @@ int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
- return 0;
- }
-
-+static uint8_t tonga_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
-+ uint32_t engine_clock, uint32_t min_engine_clock_in_sr)
-+{
-+ uint32_t i, temp;
-+ uint32_t min = (min_engine_clock_in_sr > TONGA_MINIMUM_ENGINE_CLOCK) ?
-+ min_engine_clock_in_sr : TONGA_MINIMUM_ENGINE_CLOCK;
-+
-+ PP_ASSERT_WITH_CODE((engine_clock >= min),
-+ "Engine clock can't satisfy stutter requirement!", return 0);
-+
-+ for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
-+ temp = engine_clock / (1 << i);
-+
-+ if(temp >= min || i == 0)
-+ break;
-+ }
-+ return (uint8_t)i;
-+}
-+
- /**
- * Populates single SMC SCLK structure using the provided engine clock
- *
-@@ -2463,12 +2482,12 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t
- *get the DAL clock. do it in funture.
- PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
- data->display_timing.min_clock_insr = minClocks.engineClockInSR;
--
-- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-- {
-- graphic_level->DeepSleepDivId = PhwTonga_GetSleepDividerIdFromClock(hwmgr, engine_clock, minClocks.engineClockInSR);
-- }
- */
-+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+ PHM_PlatformCaps_SclkDeepSleep))
-+ graphic_level->DeepSleepDivId =
-+ tonga_get_sleep_divider_id_from_clock(hwmgr, engine_clock,
-+ data->display_timing.min_clock_insr);
-
- /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
- graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
---
-2.7.4
-