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-rw-r--r--common/recipes-kernel/linux/files/0448-drm-amdgpu-remove-VI-hw-bug-workaround-v3.patch64
1 files changed, 0 insertions, 64 deletions
diff --git a/common/recipes-kernel/linux/files/0448-drm-amdgpu-remove-VI-hw-bug-workaround-v3.patch b/common/recipes-kernel/linux/files/0448-drm-amdgpu-remove-VI-hw-bug-workaround-v3.patch
deleted file mode 100644
index 610688f7..00000000
--- a/common/recipes-kernel/linux/files/0448-drm-amdgpu-remove-VI-hw-bug-workaround-v3.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From c548b345d15092bf46469a0339d41ae3e106987d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 7 Aug 2015 20:22:40 +0200
-Subject: [PATCH 0448/1050] drm/amdgpu: remove VI hw bug workaround v3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The workaround simply doesn't work because VM mappings
-are controlled by userspace not the kernel.
-
-Additional to that this is just a performance problem
-which happens if you have holes in your VM mapping.
-
-v2: adjust virtual addr alignment as well.
-v3: fix trivial warning
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com> (v1)
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> (v2)
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 ------------
- 2 files changed, 1 insertion(+), 13 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index 7226def..87da6b1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -455,7 +455,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
- dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
- dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
- dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
-- dev_info.virtual_address_alignment = max(PAGE_SIZE, 0x10000UL);
-+ dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
- dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
- AMDGPU_GPU_PAGE_SIZE;
- dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-index 87d67f8..f1f1b67 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
-@@ -223,18 +223,6 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
- size_t acc_size;
- int r;
-
-- /* VI has a hw bug where VM PTEs have to be allocated in groups of 8.
-- * do this as a temporary workaround
-- */
-- if (!(domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
-- if ((adev->asic_type >= CHIP_TOPAZ) && (adev->asic_type != CHIP_FIJI)) {
-- if (byte_align & 0x7fff)
-- byte_align = ALIGN(byte_align, 0x8000);
-- if (size & 0x7fff)
-- size = ALIGN(size, 0x8000);
-- }
-- }
--
- page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
- size = ALIGN(size, PAGE_SIZE);
-
---
-1.9.1
-