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-rw-r--r--common/recipes-kernel/linux/files/0441-drm-amdgpu-mark-amdgpu_allowed_register_entry-tables.patch70
1 files changed, 70 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0441-drm-amdgpu-mark-amdgpu_allowed_register_entry-tables.patch b/common/recipes-kernel/linux/files/0441-drm-amdgpu-mark-amdgpu_allowed_register_entry-tables.patch
new file mode 100644
index 00000000..f4b70578
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0441-drm-amdgpu-mark-amdgpu_allowed_register_entry-tables.patch
@@ -0,0 +1,70 @@
+From 245ca0d50e4ab1bca452b406249e09dd5f845cb7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Nils=20Wallm=C3=A9nius?= <nils.wallmenius@gmail.com>
+Date: Sat, 19 Mar 2016 16:12:17 +0100
+Subject: [PATCH 0441/1110] drm/amdgpu: mark amdgpu_allowed_register_entry
+ tables as 'const'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/vi.c | 10 +++++-----
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index bddc9ba..009598b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -962,7 +962,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
+ return true;
+ }
+
+-static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
++static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
+ {mmGRBM_STATUS, false},
+ {mmGB_ADDR_CONFIG, false},
+ {mmMC_ARB_RAMCFG, false},
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 1c120ef..a145556 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -414,11 +414,11 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
+ return true;
+ }
+
+-static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
++static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
+ {mmGB_MACROTILE_MODE7, true},
+ };
+
+-static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
++static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
+ {mmGB_TILE_MODE7, true},
+ {mmGB_TILE_MODE12, true},
+ {mmGB_TILE_MODE17, true},
+@@ -426,7 +426,7 @@ static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
+ {mmGB_MACROTILE_MODE7, true},
+ };
+
+-static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
++static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
+ {mmGRBM_STATUS, false},
+ {mmGRBM_STATUS2, false},
+ {mmGRBM_STATUS_SE0, false},
+@@ -525,8 +525,8 @@ static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
+ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
+ u32 sh_num, u32 reg_offset, u32 *value)
+ {
+- struct amdgpu_allowed_register_entry *asic_register_table = NULL;
+- struct amdgpu_allowed_register_entry *asic_register_entry;
++ const struct amdgpu_allowed_register_entry *asic_register_table = NULL;
++ const struct amdgpu_allowed_register_entry *asic_register_entry;
+ uint32_t size, i;
+
+ *value = 0;
+--
+2.7.4
+