diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch | 187 |
1 files changed, 187 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch b/common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch new file mode 100644 index 00000000..4d51f448 --- /dev/null +++ b/common/recipes-kernel/linux/files/0382-drm-amdgpu-split-pipeline-sync-out-of-SDMA-vm_flush-.patch @@ -0,0 +1,187 @@ +From 0303a1a0480622a5fc8496ff28e442b339c8fca5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Tue, 8 Mar 2016 14:11:00 +0100 +Subject: [PATCH 0382/1110] drm/amdgpu: split pipeline sync out of SDMA + vm_flush() as well +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Code it similar to how we did it for the gfx and compute engines. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 27 +++++++++++++++++++-------- + drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 23 +++++++++++++++++------ + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 23 +++++++++++++++++------ + 3 files changed, 53 insertions(+), 20 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +index 481f22b..363d4f6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +@@ -822,19 +822,14 @@ static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) + } + + /** +- * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA ++ * cik_sdma_ring_emit_pipeline_sync - sync the pipeline + * + * @ring: amdgpu_ring pointer +- * @vm: amdgpu_vm pointer + * +- * Update the page table base and flush the VM TLB +- * using sDMA (CIK). ++ * Make sure all previous operations are completed (CIK). + */ +-static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, +- unsigned vm_id, uint64_t pd_addr) ++static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) + { +- u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | +- SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; + +@@ -848,7 +843,22 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, seq); /* reference */ + amdgpu_ring_write(ring, 0xfffffff); /* mask */ + amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ ++} + ++/** ++ * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA ++ * ++ * @ring: amdgpu_ring pointer ++ * @vm: amdgpu_vm pointer ++ * ++ * Update the page table base and flush the VM TLB ++ * using sDMA (CIK). ++ */ ++static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, ++ unsigned vm_id, uint64_t pd_addr) ++{ ++ u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | ++ SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + if (vm_id < 8) { +@@ -1290,6 +1300,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .parse_cs = NULL, + .emit_ib = cik_sdma_ring_emit_ib, + .emit_fence = cik_sdma_ring_emit_fence, ++ .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, + .emit_vm_flush = cik_sdma_ring_emit_vm_flush, + .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, + .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +index 4abfd11..b96ec4e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +@@ -880,16 +880,13 @@ static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib + } + + /** +- * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA ++ * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline + * + * @ring: amdgpu_ring pointer +- * @vm: amdgpu_vm pointer + * +- * Update the page table base and flush the VM TLB +- * using sDMA (VI). ++ * Make sure all previous operations are completed (CIK). + */ +-static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, +- unsigned vm_id, uint64_t pd_addr) ++static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) + { + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; +@@ -905,7 +902,20 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, 0xfffffff); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ ++} + ++/** ++ * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA ++ * ++ * @ring: amdgpu_ring pointer ++ * @vm: amdgpu_vm pointer ++ * ++ * Update the page table base and flush the VM TLB ++ * using sDMA (VI). ++ */ ++static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, ++ unsigned vm_id, uint64_t pd_addr) ++{ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + if (vm_id < 8) { +@@ -1295,6 +1305,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .parse_cs = NULL, + .emit_ib = sdma_v2_4_ring_emit_ib, + .emit_fence = sdma_v2_4_ring_emit_fence, ++ .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, + .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index 9a51233..4d1c0a3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -1031,16 +1031,13 @@ static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib + } + + /** +- * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA ++ * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline + * + * @ring: amdgpu_ring pointer +- * @vm: amdgpu_vm pointer + * +- * Update the page table base and flush the VM TLB +- * using sDMA (VI). ++ * Make sure all previous operations are completed (CIK). + */ +-static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, +- unsigned vm_id, uint64_t pd_addr) ++static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) + { + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; +@@ -1056,7 +1053,20 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, 0xfffffff); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ ++} + ++/** ++ * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA ++ * ++ * @ring: amdgpu_ring pointer ++ * @vm: amdgpu_vm pointer ++ * ++ * Update the page table base and flush the VM TLB ++ * using sDMA (VI). ++ */ ++static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, ++ unsigned vm_id, uint64_t pd_addr) ++{ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + if (vm_id < 8) { +@@ -1563,6 +1573,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .parse_cs = NULL, + .emit_ib = sdma_v3_0_ring_emit_ib, + .emit_fence = sdma_v3_0_ring_emit_fence, ++ .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, + .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, +-- +2.7.4 + |