diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch b/common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch new file mode 100644 index 00000000..27394a5e --- /dev/null +++ b/common/recipes-kernel/linux/files/0362-drm-amdgpu-if-a-GDS-switch-is-needed-emit-a-pipeline.patch @@ -0,0 +1,61 @@ +From e4c5273b33bfe7303ea03aa50f9fad2b3ef32980 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Tue, 1 Mar 2016 15:51:53 +0100 +Subject: [PATCH 0362/1110] drm/amdgpu: if a GDS switch is needed emit a + pipeline sync as well +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Otherwise we might change the GDS settings while they are still in use. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Chunming Zhou <david1.zhou@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 ++++++++++++---------- + 1 file changed, 12 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index 25469bf..f139cea 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -261,22 +261,24 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring, + { + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; ++ bool gds_switch_needed = ring->funcs->emit_gds_switch && ( ++ mgr_id->gds_base != gds_base || ++ mgr_id->gds_size != gds_size || ++ mgr_id->gws_base != gws_base || ++ mgr_id->gws_size != gws_size || ++ mgr_id->oa_base != oa_base || ++ mgr_id->oa_size != oa_size); ++ ++ if (ring->funcs->emit_pipeline_sync && ( ++ pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) ++ amdgpu_ring_emit_pipeline_sync(ring); + + if (pd_addr != AMDGPU_VM_NO_FLUSH) { + trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); +- if (ring->funcs->emit_pipeline_sync) +- amdgpu_ring_emit_pipeline_sync(ring); + amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); + } + +- if (ring->funcs->emit_gds_switch && ( +- mgr_id->gds_base != gds_base || +- mgr_id->gds_size != gds_size || +- mgr_id->gws_base != gws_base || +- mgr_id->gws_size != gws_size || +- mgr_id->oa_base != oa_base || +- mgr_id->oa_size != oa_size)) { +- ++ if (gds_switch_needed) { + mgr_id->gds_base = gds_base; + mgr_id->gds_size = gds_size; + mgr_id->gws_base = gws_base; +-- +2.7.4 + |