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-rw-r--r--common/recipes-kernel/linux/files/0361-drm-amdgpu-split-pipeline-sync-and-vm-flush.patch161
1 files changed, 161 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0361-drm-amdgpu-split-pipeline-sync-and-vm-flush.patch b/common/recipes-kernel/linux/files/0361-drm-amdgpu-split-pipeline-sync-and-vm-flush.patch
new file mode 100644
index 00000000..b0c4797f
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0361-drm-amdgpu-split-pipeline-sync-and-vm-flush.patch
@@ -0,0 +1,161 @@
+From cf95fdb7c71fe682fe165553dc210d04889bcdc8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 15 Apr 2016 16:45:49 -0400
+Subject: [PATCH 0361/1110] drm/amdgpu: split pipeline sync and vm flush
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This allows us to use the pipeline sync for other tasks as well.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++++++++++++++++++++++--------
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +++++++++--
+ 4 files changed, 35 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index a1a10fa..0bc033e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -287,6 +287,7 @@ struct amdgpu_ring_funcs {
+ struct amdgpu_ib *ib);
+ void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
+ uint64_t seq, unsigned flags);
++ void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
+ void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
+ uint64_t pd_addr);
+ void (*emit_hdp_flush)(struct amdgpu_ring *ring);
+@@ -2198,6 +2199,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
+ #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
+ #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
+ #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
++#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
+ #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
+ #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
+ #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index abf0d44..25469bf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -264,6 +264,8 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring,
+
+ if (pd_addr != AMDGPU_VM_NO_FLUSH) {
+ trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
++ if (ring->funcs->emit_pipeline_sync)
++ amdgpu_ring_emit_pipeline_sync(ring);
+ amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 5e9af0b..87d439a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -3041,6 +3041,26 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
+ return 0;
+ }
+
++/**
++ * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
++ *
++ * @ring: the ring to emmit the commands to
++ *
++ * Sync the command pipeline with the PFP. E.g. wait for everything
++ * to be completed.
++ */
++static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
++{
++ int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
++ if (usepfp) {
++ /* synce CE with ME to prevent CE fetch CEIB before context switch done */
++ amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
++ amdgpu_ring_write(ring, 0);
++ amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
++ amdgpu_ring_write(ring, 0);
++ }
++}
++
+ /*
+ * vm
+ * VMID 0 is the physical GPU addresses as used by the kernel.
+@@ -3072,14 +3092,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ amdgpu_ring_write(ring, 0xffffffff);
+ amdgpu_ring_write(ring, 4); /* poll interval */
+
+- if (usepfp) {
+- /* synce CE with ME to prevent CE fetch CEIB before context switch done */
+- amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+- amdgpu_ring_write(ring, 0);
+- }
+-
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+ WRITE_DATA_DST_SEL(0)));
+@@ -5160,6 +5172,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
+ .parse_cs = NULL,
+ .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
+ .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
++ .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
+ .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
+ .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
+ .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
+@@ -5177,6 +5190,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
+ .parse_cs = NULL,
+ .emit_ib = gfx_v7_0_ring_emit_ib_compute,
+ .emit_fence = gfx_v7_0_ring_emit_fence_compute,
++ .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
+ .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
+ .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
+ .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index d6d2453..56dd745 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -4692,8 +4692,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
+
+ }
+
+-static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vm_id, uint64_t pd_addr)
++static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ {
+ int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
+ uint32_t seq = ring->fence_drv.sync_seq;
+@@ -4716,6 +4715,12 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+ amdgpu_ring_write(ring, 0);
+ }
++}
++
++static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
++ unsigned vm_id, uint64_t pd_addr)
++{
++ int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
+
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+@@ -5038,6 +5043,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
+ .parse_cs = NULL,
+ .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
+ .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
++ .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
+ .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
+ .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
+ .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
+@@ -5055,6 +5061,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
+ .parse_cs = NULL,
+ .emit_ib = gfx_v8_0_ring_emit_ib_compute,
+ .emit_fence = gfx_v8_0_ring_emit_fence_compute,
++ .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
+ .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
+ .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
+ .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-26 16:54:58 +0000