diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch b/common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch new file mode 100644 index 00000000..38a34a1e --- /dev/null +++ b/common/recipes-kernel/linux/files/0360-drm-amdgpu-switch-the-GDS-only-on-demand-v2.patch @@ -0,0 +1,148 @@ +From dec35381ca2378fe439abde710d26a641683e63b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Tue, 1 Mar 2016 15:09:25 +0100 +Subject: [PATCH 0360/1110] drm/amdgpu: switch the GDS only on demand v2 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Switching the GDS space to often seems to be problematic. + +This patch together with the following can avoid VM faults on context switch. + +v2: extend commit message a bit + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) +Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1) +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +++ + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 +++++++++++++++++++++++++++++++--- + 3 files changed, 54 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 394122e..a1a10fa 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -881,6 +881,13 @@ struct amdgpu_vm_manager_id { + struct list_head list; + struct fence *active; + atomic_long_t owner; ++ ++ uint32_t gds_base; ++ uint32_t gds_size; ++ uint32_t gws_base; ++ uint32_t gws_size; ++ uint32_t oa_base; ++ uint32_t oa_size; + }; + + struct amdgpu_vm_manager { +@@ -927,6 +934,7 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size); ++void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); + uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); + int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, + struct amdgpu_vm *vm); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +index 4aedfe4..ddaffa4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +@@ -164,6 +164,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, + + if (ib->ctx != ctx || ib->vm != vm) { + ring->current_ctx = old_ctx; ++ if (ib->vm_id) ++ amdgpu_vm_reset_id(adev, ib->vm_id); + amdgpu_ring_undo(ring); + return -EINVAL; + } +@@ -180,6 +182,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, + if (r) { + dev_err(adev->dev, "failed to emit fence (%d)\n", r); + ring->current_ctx = old_ctx; ++ if (ib->vm_id) ++ amdgpu_vm_reset_id(adev, ib->vm_id); + amdgpu_ring_undo(ring); + return r; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index 3e1c8cf..abf0d44 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -259,16 +259,53 @@ void amdgpu_vm_flush(struct amdgpu_ring *ring, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size) + { ++ struct amdgpu_device *adev = ring->adev; ++ struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; ++ + if (pd_addr != AMDGPU_VM_NO_FLUSH) { + trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); + amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); + } + +- if (ring->funcs->emit_gds_switch) +- amdgpu_ring_emit_gds_switch(ring, vm_id, ++ if (ring->funcs->emit_gds_switch && ( ++ mgr_id->gds_base != gds_base || ++ mgr_id->gds_size != gds_size || ++ mgr_id->gws_base != gws_base || ++ mgr_id->gws_size != gws_size || ++ mgr_id->oa_base != oa_base || ++ mgr_id->oa_size != oa_size)) { ++ ++ mgr_id->gds_base = gds_base; ++ mgr_id->gds_size = gds_size; ++ mgr_id->gws_base = gws_base; ++ mgr_id->gws_size = gws_size; ++ mgr_id->oa_base = oa_base; ++ mgr_id->oa_size = oa_size; ++ amdgpu_ring_emit_gds_switch(ring, vm_id, + gds_base, gds_size, + gws_base, gws_size, + oa_base, oa_size); ++ } ++} ++ ++/** ++ * amdgpu_vm_reset_id - reset VMID to zero ++ * ++ * @adev: amdgpu device structure ++ * @vm_id: vmid number to use ++ * ++ * Reset saved GDW, GWS and OA to force switch on next flush. ++ */ ++void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) ++{ ++ struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; ++ ++ mgr_id->gds_base = 0; ++ mgr_id->gds_size = 0; ++ mgr_id->gws_base = 0; ++ mgr_id->gws_size = 0; ++ mgr_id->oa_base = 0; ++ mgr_id->oa_size = 0; + } + + /** +@@ -1429,9 +1466,11 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) + INIT_LIST_HEAD(&adev->vm_manager.ids_lru); + + /* skip over VMID 0, since it is the system VM */ +- for (i = 1; i < adev->vm_manager.num_ids; ++i) ++ for (i = 1; i < adev->vm_manager.num_ids; ++i) { ++ amdgpu_vm_reset_id(adev, i); + list_add_tail(&adev->vm_manager.ids[i].list, + &adev->vm_manager.ids_lru); ++ } + + atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); + +-- +2.7.4 + |