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-rw-r--r--common/recipes-kernel/linux/files/0356-drm-amdgpu-remove-HW-fence-owner.patch292
1 files changed, 292 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0356-drm-amdgpu-remove-HW-fence-owner.patch b/common/recipes-kernel/linux/files/0356-drm-amdgpu-remove-HW-fence-owner.patch
new file mode 100644
index 00000000..3328fe59
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0356-drm-amdgpu-remove-HW-fence-owner.patch
@@ -0,0 +1,292 @@
+From b113c3ab8ac34ccfd88675b75bcc47ef412ed45d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Tue, 16 Feb 2016 10:57:10 +0100
+Subject: [PATCH 0356/1110] drm/amdgpu: remove HW fence owner
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Not used any more since we now always use the sheduler.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 9 ++-------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 ++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 8 +-------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 7 ++-----
+ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++----
+ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 +--
+ 12 files changed, 16 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 1269e3e..27b1dc3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -370,9 +370,6 @@ struct amdgpu_fence {
+ struct amdgpu_ring *ring;
+ uint64_t seq;
+
+- /* filp or special value for fence creator */
+- void *owner;
+-
+ wait_queue_t fence_wake;
+ };
+
+@@ -393,8 +390,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
+ unsigned irq_type);
+ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
+ void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
+-int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
+- struct amdgpu_fence **fence);
++int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence **fence);
+ void amdgpu_fence_process(struct amdgpu_ring *ring);
+ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
+ int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
+@@ -1141,8 +1137,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ unsigned size, struct amdgpu_ib *ib);
+ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
+ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+- struct amdgpu_ib *ib, void *owner);
+- struct fence *last_vm_update,
++ struct amdgpu_ib *ib, struct fence *last_vm_update,
+ int amdgpu_ib_pool_init(struct amdgpu_device *adev);
+ void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
+ int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+index 97db196..d94b13a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+@@ -91,25 +91,21 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
+ * amdgpu_fence_emit - emit a fence on the requested ring
+ *
+ * @ring: ring the fence is associated with
+- * @owner: creator of the fence
+ * @fence: amdgpu fence object
+ *
+ * Emits a fence command on the requested ring (all asics).
+ * Returns 0 on success, -ENOMEM on failure.
+ */
+-int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
+- struct amdgpu_fence **fence)
++int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence **fence)
+ {
+ struct amdgpu_device *adev = ring->adev;
+
+- /* we are protected by the ring emission mutex */
+ *fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
+ if ((*fence) == NULL) {
+ return -ENOMEM;
+ }
+ (*fence)->seq = ++ring->fence_drv.sync_seq;
+ (*fence)->ring = ring;
+- (*fence)->owner = owner;
+ fence_init(&(*fence)->base, &amdgpu_fence_ops,
+ &ring->fence_drv.fence_queue.lock,
+ adev->fence_context + ring->idx,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+index 1966d66..dc5683c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+@@ -101,7 +101,6 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
+ * @adev: amdgpu_device pointer
+ * @num_ibs: number of IBs to schedule
+ * @ibs: IB objects to schedule
+- * @owner: owner for creating the fences
+ *
+ * Schedule an IB on the associated ring (all asics).
+ * Returns 0 on success, error on failure.
+@@ -117,8 +116,7 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
+ * to SI there was just a DE IB.
+ */
+ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+- struct amdgpu_ib *ibs, void *owner,
+- struct fence *last_vm_update,
++ struct amdgpu_ib *ibs, struct fence *last_vm_update,
+ struct fence **f)
+ {
+ struct amdgpu_device *adev = ring->adev;
+@@ -182,7 +180,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+ amdgpu_ring_emit_hdp_invalidate(ring);
+ }
+
+- r = amdgpu_fence_emit(ring, owner, &ib->fence);
++ r = amdgpu_fence_emit(ring, &ib->fence);
+ if (r) {
+ dev_err(adev->dev, "failed to emit fence (%d)\n", r);
+ ring->current_ctx = old_ctx;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+index af9bae6..a3baec9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -148,7 +148,7 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
+ }
+
+ trace_amdgpu_sched_run_job(job);
+- r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job->owner,
++ r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
+ job->sync.last_vm_update, &fence);
+ if (r) {
+ DRM_ERROR("Error scheduling IBs (%d)\n", r);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+index 87690cc..e367342 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+@@ -60,12 +60,8 @@ void amdgpu_sync_create(struct amdgpu_sync *sync)
+ */
+ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
+ {
+- struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
+ struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
+
+- if (a_fence)
+- return a_fence->ring->adev == adev;
+-
+ if (s_fence) {
+ struct amdgpu_ring *ring;
+
+@@ -85,13 +81,11 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
+ */
+ static void *amdgpu_sync_get_owner(struct fence *f)
+ {
+- struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
+ struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
+
+ if (s_fence)
+ return s_fence->owner;
+- else if (a_fence)
+- return a_fence->owner;
++
+ return AMDGPU_FENCE_OWNER_UNDEFINED;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index 726f0cb..c00df2f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -905,8 +905,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
+ AMDGPU_FENCE_OWNER_UNDEFINED,
+ &f);
+ if (direct) {
+- r = amdgpu_ib_schedule(ring, 1, ib,
+- AMDGPU_FENCE_OWNER_UNDEFINED, NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ if (r)
+ goto err_free;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index 547e084..125dba2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -442,8 +442,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+ &amdgpu_vce_free_job,
+ AMDGPU_FENCE_OWNER_UNDEFINED,
+ &f);
+- r = amdgpu_ib_schedule(ring, 1, ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ if (r)
+ goto err;
+
+@@ -514,9 +513,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+ &f);
+
+ if (direct) {
+- r = amdgpu_ib_schedule(ring, 1, ib,
+- AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ if (r)
+ goto err;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+index f94d707..481f22b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+@@ -643,8 +643,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
+ ib.ptr[3] = 1;
+ ib.ptr[4] = 0xDEADBEEF;
+ ib.length_dw = 5;
+- r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ if (r)
+ goto err1;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index e1140a4..5e9af0b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -2136,8 +2136,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
+ ib.ptr[2] = 0xDEADBEEF;
+ ib.length_dw = 3;
+
+- r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ if (r)
+ goto err2;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index fbe148d..d6d2453 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -706,8 +706,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
+ ib.ptr[2] = 0xDEADBEEF;
+ ib.length_dw = 3;
+
+- r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ if (r)
+ goto err2;
+
+@@ -1262,8 +1261,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+
+ /* shedule the ib on the ring */
+- r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ if (r) {
+ DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
+ goto fail;
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+index 602a467..4abfd11 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+@@ -701,8 +701,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
+ ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
+ ib.length_dw = 8;
+
+- r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ if (r)
+ goto err1;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+index e56020e..9a51233 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -853,8 +853,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
+ ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib.length_dw = 8;
+
+- r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
+- NULL, &f);
++ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ if (r)
+ goto err1;
+
+--
+2.7.4
+