diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch b/common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch new file mode 100644 index 00000000..79bb0909 --- /dev/null +++ b/common/recipes-kernel/linux/files/0341-drm-amdgpu-ci-sync-up-with-dpm-changes-from-radeon.patch @@ -0,0 +1,60 @@ +From dd69ad41ab1d50b183a110a9974faefc71a6fc52 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 3 Mar 2016 12:27:46 -0500 +Subject: [PATCH 0341/1110] drm/amdgpu/ci: sync up with dpm changes from radeon +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Looks like radeon commit: +d3052b8ce8a308d2086519fa5f7c4966257ea184 +was missed. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> +Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +index 2a51bc7..1f9109d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +@@ -3017,7 +3017,6 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev, + &memory_level->MinVddcPhases); + + memory_level->EnabledForThrottle = 1; +- memory_level->EnabledForActivity = 1; + memory_level->UpH = 0; + memory_level->DownH = 100; + memory_level->VoltageDownH = 0; +@@ -3376,7 +3375,6 @@ static int ci_populate_single_graphic_level(struct amdgpu_device *adev, + graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); + graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); + graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); +- graphic_level->EnabledForActivity = 1; + + return 0; + } +@@ -3407,6 +3405,7 @@ static int ci_populate_all_graphic_levels(struct amdgpu_device *adev) + pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = + PPSMC_DISPLAY_WATERMARK_HIGH; + } ++ pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; + + pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; + pi->dpm_level_enable_mask.sclk_dpm_enable_mask = +@@ -3450,6 +3449,8 @@ static int ci_populate_all_memory_levels(struct amdgpu_device *adev) + return ret; + } + ++ pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; ++ + if ((dpm_table->mclk_table.count >= 2) && + ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) { + pi->smc_state_table.MemoryLevel[1].MinVddc = +-- +2.7.4 + |