diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0315-drm-amdkfd-Add-support-for-VI-in-DQM.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0315-drm-amdkfd-Add-support-for-VI-in-DQM.patch | 164 |
1 files changed, 0 insertions, 164 deletions
diff --git a/common/recipes-kernel/linux/files/0315-drm-amdkfd-Add-support-for-VI-in-DQM.patch b/common/recipes-kernel/linux/files/0315-drm-amdkfd-Add-support-for-VI-in-DQM.patch deleted file mode 100644 index aab2d9aa..00000000 --- a/common/recipes-kernel/linux/files/0315-drm-amdkfd-Add-support-for-VI-in-DQM.patch +++ /dev/null @@ -1,164 +0,0 @@ -From 914bea6329b2cbbb3586a11f90ddf026bef44348 Mon Sep 17 00:00:00 2001 -From: Ben Goz <ben.goz@amd.com> -Date: Mon, 12 Jan 2015 14:28:46 +0200 -Subject: [PATCH 0315/1050] drm/amdkfd: Add support for VI in DQM - -This patch adds support for the VI APU in the DQM module. - -Most of the functionality of DQM is shared between CI and VI. Therefore, -only a handful of functions are required to be in the -H/W-specific part of DQM. - -Signed-off-by: Ben Goz <ben.goz@amd.com> -Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> ---- - .../drm/amd/amdkfd/kfd_device_queue_manager_vi.c | 103 ++++++++++++++++++++- - 1 file changed, 99 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c -index 4c15212..44c38e8 100644 ---- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c -+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c -@@ -22,6 +22,10 @@ - */ - - #include "kfd_device_queue_manager.h" -+#include "gca/gfx_8_0_enum.h" -+#include "gca/gfx_8_0_sh_mask.h" -+#include "gca/gfx_8_0_enum.h" -+#include "oss/oss_3_0_sh_mask.h" - - static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, - struct qcm_process_device *qpd, -@@ -37,14 +41,40 @@ static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, - - void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops) - { -- pr_warn("amdkfd: VI DQM is not currently supported\n"); -- - ops->set_cache_memory_policy = set_cache_memory_policy_vi; - ops->register_process = register_process_vi; - ops->initialize = initialize_cpsch_vi; - ops->init_sdma_vm = init_sdma_vm; - } - -+static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) -+{ -+ /* In 64-bit mode, we can only control the top 3 bits of the LDS, -+ * scratch and GPUVM apertures. -+ * The hardware fills in the remaining 59 bits according to the -+ * following pattern: -+ * LDS: X0000000'00000000 - X0000001'00000000 (4GB) -+ * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) -+ * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB) -+ * -+ * (where X/Y is the configurable nybble with the low-bit 0) -+ * -+ * LDS and scratch will have the same top nybble programmed in the -+ * top 3 bits of SH_MEM_BASES.PRIVATE_BASE. -+ * GPUVM can have a different top nybble programmed in the -+ * top 3 bits of SH_MEM_BASES.SHARED_BASE. -+ * We don't bother to support different top nybbles -+ * for LDS/Scratch and GPUVM. -+ */ -+ -+ BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || -+ top_address_nybble == 0); -+ -+ return top_address_nybble << 12 | -+ (top_address_nybble << 12) << -+ SH_MEM_BASES__SHARED_BASE__SHIFT; -+} -+ - static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, - struct qcm_process_device *qpd, - enum cache_policy default_policy, -@@ -52,18 +82,83 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, - void __user *alternate_aperture_base, - uint64_t alternate_aperture_size) - { -- return false; -+ uint32_t default_mtype; -+ uint32_t ape1_mtype; -+ -+ default_mtype = (default_policy == cache_policy_coherent) ? -+ MTYPE_CC : -+ MTYPE_NC; -+ -+ ape1_mtype = (alternate_policy == cache_policy_coherent) ? -+ MTYPE_CC : -+ MTYPE_NC; -+ -+ qpd->sh_mem_config = (qpd->sh_mem_config & -+ SH_MEM_CONFIG__ADDRESS_MODE_MASK) | -+ SH_MEM_ALIGNMENT_MODE_UNALIGNED << -+ SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | -+ default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | -+ ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT | -+ SH_MEM_CONFIG__PRIVATE_ATC_MASK; -+ -+ return true; - } - - static int register_process_vi(struct device_queue_manager *dqm, - struct qcm_process_device *qpd) - { -- return -1; -+ struct kfd_process_device *pdd; -+ unsigned int temp; -+ -+ BUG_ON(!dqm || !qpd); -+ -+ pdd = qpd_to_pdd(qpd); -+ -+ /* check if sh_mem_config register already configured */ -+ if (qpd->sh_mem_config == 0) { -+ qpd->sh_mem_config = -+ SH_MEM_ALIGNMENT_MODE_UNALIGNED << -+ SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | -+ MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | -+ MTYPE_CC << SH_MEM_CONFIG__APE1_MTYPE__SHIFT | -+ SH_MEM_CONFIG__PRIVATE_ATC_MASK; -+ -+ qpd->sh_mem_ape1_limit = 0; -+ qpd->sh_mem_ape1_base = 0; -+ } -+ -+ if (qpd->pqm->process->is_32bit_user_mode) { -+ temp = get_sh_mem_bases_32(pdd); -+ qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT; -+ qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA32 << -+ SH_MEM_CONFIG__ADDRESS_MODE__SHIFT; -+ } else { -+ temp = get_sh_mem_bases_nybble_64(pdd); -+ qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); -+ qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA64 << -+ SH_MEM_CONFIG__ADDRESS_MODE__SHIFT; -+ } -+ -+ pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", -+ qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); -+ -+ return 0; - } - - static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, - struct qcm_process_device *qpd) - { -+ uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT); -+ -+ if (q->process->is_32bit_user_mode) -+ value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) | -+ get_sh_mem_bases_32(qpd_to_pdd(qpd)); -+ else -+ value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) << -+ SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) && -+ SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK; -+ -+ q->properties.sdma_vm_addr = value; - } - - static int initialize_cpsch_vi(struct device_queue_manager *dqm) --- -1.9.1 - |