diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch b/common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch new file mode 100644 index 00000000..ac169bc4 --- /dev/null +++ b/common/recipes-kernel/linux/files/0314-drm-amdgpu-vi-move-sdma-tiling-config-setup-into-sdm.patch @@ -0,0 +1,94 @@ +From 7b6b27de3068199ec3d9784c061c80e7e01b1f9e Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 12 Feb 2016 03:19:14 -0500 +Subject: [PATCH 0314/1110] drm/amdgpu/vi: move sdma tiling config setup into + sdma code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Split sdma and gfx programming. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 -------- + drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 +++++ + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++++ + 3 files changed, 10 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 5e04140..13eb40f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -2695,10 +2695,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) + WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); +- WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, +- adev->gfx.config.gb_addr_config & 0x70); +- WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, +- adev->gfx.config.gb_addr_config & 0x70); + WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); +@@ -3959,10 +3955,6 @@ static void gfx_v8_0_print_status(void *handle) + RREG32(mmHDP_ADDR_CONFIG)); + dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", + RREG32(mmDMIF_ADDR_CALC)); +- dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", +- RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); +- dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", +- RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); + dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +index 1f9ba74..1f70d83 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +@@ -434,6 +434,9 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + ++ WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], ++ adev->gfx.config.gb_addr_config & 0x70); ++ + WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); + + /* Set ring buffer size in dwords */ +@@ -1078,6 +1081,8 @@ static void sdma_v2_4_print_status(void *handle) + i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); ++ dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", ++ i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + vi_srbm_select(adev, 0, 0, 0, j); +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index f0943bb..2389bdb 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -570,6 +570,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + ++ WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], ++ adev->gfx.config.gb_addr_config & 0x70); ++ + WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); + + /* Set ring buffer size in dwords */ +@@ -1241,6 +1244,8 @@ static void sdma_v3_0_print_status(void *handle) + i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); ++ dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n", ++ i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i])); + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + vi_srbm_select(adev, 0, 0, 0, j); +-- +2.7.4 + |