diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch b/common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch new file mode 100644 index 00000000..0c09e7b2 --- /dev/null +++ b/common/recipes-kernel/linux/files/0300-drm-amd-include-Update-dce-8-headers-for-dal.patch @@ -0,0 +1,50 @@ +From 72968d3982b7af284da849909f4023432ba74a3f Mon Sep 17 00:00:00 2001 +From: Harry Wentland <harry.wentland@amd.com> +Date: Wed, 10 Feb 2016 20:01:39 -0500 +Subject: [PATCH 0300/1110] drm/amd/include: Update dce 8 headers for dal + +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h | 12 ++++++++++++ + 2 files changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h +index dc52ea0..d3ccf5a 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h +@@ -1379,6 +1379,7 @@ + #define mmDC_GPIO_PAD_STRENGTH_1 0x1978 + #define mmDC_GPIO_PAD_STRENGTH_2 0x1979 + #define mmPHY_AUX_CNTL 0x197f ++#define mmDC_GPIO_I2CPAD_MASK 0x1974 + #define mmDC_GPIO_I2CPAD_A 0x1975 + #define mmDC_GPIO_I2CPAD_EN 0x1976 + #define mmDC_GPIO_I2CPAD_Y 0x1977 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h +index 8a29307..c331c9f 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h +@@ -4130,6 +4130,18 @@ + #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe + #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 + #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x1 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x2 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x4 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x10 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x20 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x40 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6 + #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 + #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 + #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 +-- +2.7.4 + |