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-rw-r--r--common/recipes-kernel/linux/files/0259-drm-amdgpu-fix-the-build-on-big-endian.patch59
1 files changed, 0 insertions, 59 deletions
diff --git a/common/recipes-kernel/linux/files/0259-drm-amdgpu-fix-the-build-on-big-endian.patch b/common/recipes-kernel/linux/files/0259-drm-amdgpu-fix-the-build-on-big-endian.patch
deleted file mode 100644
index 928c7322..00000000
--- a/common/recipes-kernel/linux/files/0259-drm-amdgpu-fix-the-build-on-big-endian.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 454fc95e84a20024eb5d6c0fbc5ab648bae2a56f Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 9 Jun 2015 09:58:23 -0400
-Subject: [PATCH 0259/1050] drm/amdgpu: fix the build on big endian
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Some leftover copy and pastes from radeon that never
-got updated.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 ++-
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +++--
- 2 files changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index fb93163..ab83cc1 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -411,7 +411,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
- rb_bufsz = order_base_2(ring->ring_size / 4);
- rb_cntl = rb_bufsz << 1;
- #ifdef __BIG_ENDIAN
-- rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
-+ rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
-+ SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
- #endif
- WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index afa703c..cb790744 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -2881,7 +2881,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
- rb_bufsz = order_base_2(ring->ring_size / 8);
- tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
- #ifdef __BIG_ENDIAN
-- tmp |= BUF_SWAP_32BIT;
-+ tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
- #endif
- WREG32(mmCP_RB0_CNTL, tmp);
-
-@@ -3400,7 +3400,8 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
- mqd->queue_state.cp_hqd_pq_control |=
- (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
- #ifdef __BIG_ENDIAN
-- mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
-+ mqd->queue_state.cp_hqd_pq_control |=
-+ 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
- #endif
- mqd->queue_state.cp_hqd_pq_control &=
- ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
---
-1.9.1
-