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-rw-r--r--common/recipes-kernel/linux/files/0232-drm-amdgpu-remove-all-sh-mem-register-modification-i.patch270
1 files changed, 0 insertions, 270 deletions
diff --git a/common/recipes-kernel/linux/files/0232-drm-amdgpu-remove-all-sh-mem-register-modification-i.patch b/common/recipes-kernel/linux/files/0232-drm-amdgpu-remove-all-sh-mem-register-modification-i.patch
deleted file mode 100644
index 4e4dc493..00000000
--- a/common/recipes-kernel/linux/files/0232-drm-amdgpu-remove-all-sh-mem-register-modification-i.patch
+++ /dev/null
@@ -1,270 +0,0 @@
-From b9a7faaeb2b0271ca9a7d8436a055da219a35ec8 Mon Sep 17 00:00:00 2001
-From: "monk.liu" <monk.liu@amd.com>
-Date: Wed, 27 May 2015 14:03:22 +0800
-Subject: [PATCH 0232/1050] drm/amdgpu: remove all sh mem register modification
- in vm flush
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Leave that at the values set during init. No need to update
-them repeatedly.
-
-Signed-off-by: monk.liu <monk.liu@amd.com>
-Signed-off-by: David Zhang <david1.zhang@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 27 ------------------------
- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 27 ------------------------
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 30 ---------------------------
- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 38 ----------------------------------
- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 38 ----------------------------------
- 5 files changed, 160 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-index 7c816b5..ef5e9f9 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
-@@ -829,8 +829,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
- {
- u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
- SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
-- u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
-- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-
- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
- if (vm_id < 8) {
-@@ -840,31 +838,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
- }
- amdgpu_ring_write(ring, pd_addr >> 12);
-
-- /* update SH_MEM_* regs */
-- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, VMID(vm_id));
--
-- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-- amdgpu_ring_write(ring, mmSH_MEM_BASES);
-- amdgpu_ring_write(ring, 0);
--
-- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-- amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
-- amdgpu_ring_write(ring, sh_mem_cfg);
--
-- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-- amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
-- amdgpu_ring_write(ring, 1);
--
-- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-- amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
-- amdgpu_ring_write(ring, 0);
--
-- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, VMID(0));
--
- /* flush TLB */
- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
- amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-index 0057699..58a20be 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
-@@ -3593,33 +3593,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, pd_addr >> 12);
-
-- /* update SH_MEM_* regs */
-- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-- WRITE_DATA_DST_SEL(0)));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, 0);
-- amdgpu_ring_write(ring, VMID(vm_id));
--
-- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
-- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-- WRITE_DATA_DST_SEL(0)));
-- amdgpu_ring_write(ring, mmSH_MEM_BASES);
-- amdgpu_ring_write(ring, 0);
--
-- amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
-- amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
-- amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
-- amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
--
-- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-- WRITE_DATA_DST_SEL(0)));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, 0);
-- amdgpu_ring_write(ring, VMID(0));
--
--
- /* bits 0-15 are the VM contexts0-15 */
- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index a7d687d..c3aebdf 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -3800,7 +3800,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
- {
- int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
-- u32 srbm_gfx_cntl = 0;
-
- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-@@ -3815,35 +3814,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, pd_addr >> 12);
-
-- /* update SH_MEM_* regs */
-- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
-- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-- WRITE_DATA_DST_SEL(0)));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, 0);
-- amdgpu_ring_write(ring, srbm_gfx_cntl);
--
-- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
-- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-- WRITE_DATA_DST_SEL(0)));
-- amdgpu_ring_write(ring, mmSH_MEM_BASES);
-- amdgpu_ring_write(ring, 0);
--
-- amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
-- amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
-- amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
-- amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
--
-- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
-- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-- WRITE_DATA_DST_SEL(0)));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, 0);
-- amdgpu_ring_write(ring, srbm_gfx_cntl);
--
--
- /* bits 0-15 are the VM contexts0-15 */
- /* invalidate the cache */
- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-index 64de8f6..d09aa7e 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
-@@ -890,10 +890,6 @@ static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
- static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
- {
-- u32 srbm_gfx_cntl = 0;
-- u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
-- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
--
- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- if (vm_id < 8) {
-@@ -903,40 +899,6 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
- }
- amdgpu_ring_write(ring, pd_addr >> 12);
-
-- /* update SH_MEM_* regs */
-- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, srbm_gfx_cntl);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_BASES);
-- amdgpu_ring_write(ring, 0);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
-- amdgpu_ring_write(ring, sh_mem_cfg);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
-- amdgpu_ring_write(ring, 1);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
-- amdgpu_ring_write(ring, 0);
--
-- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, srbm_gfx_cntl);
--
--
- /* flush TLB */
- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-index bf3cefc..555c0e1 100644
---- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
-@@ -953,10 +953,6 @@ static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
- static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- unsigned vm_id, uint64_t pd_addr)
- {
-- u32 srbm_gfx_cntl = 0;
-- u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
-- SH_MEM_ALIGNMENT_MODE_UNALIGNED);
--
- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
- if (vm_id < 8) {
-@@ -966,40 +962,6 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- }
- amdgpu_ring_write(ring, pd_addr >> 12);
-
-- /* update SH_MEM_* regs */
-- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, srbm_gfx_cntl);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_BASES);
-- amdgpu_ring_write(ring, 0);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
-- amdgpu_ring_write(ring, sh_mem_cfg);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
-- amdgpu_ring_write(ring, 1);
--
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
-- amdgpu_ring_write(ring, 0);
--
-- srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
-- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-- amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-- amdgpu_ring_write(ring, srbm_gfx_cntl);
--
--
- /* flush TLB */
- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
---
-1.9.1
-
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