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-rw-r--r--common/recipes-kernel/linux/files/0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch233
1 files changed, 0 insertions, 233 deletions
diff --git a/common/recipes-kernel/linux/files/0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch b/common/recipes-kernel/linux/files/0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch
deleted file mode 100644
index f859c7f0..00000000
--- a/common/recipes-kernel/linux/files/0188-drm-amdgpu-add-pcie-cap-module-parameters-v2.patch
+++ /dev/null
@@ -1,233 +0,0 @@
-From 0ce33e777dc9d6bee8b6d5039838966eab6bf4a3 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Thu, 4 Feb 2016 10:21:23 -0500
-Subject: [PATCH 0188/1110] drm/amdgpu: add pcie cap module parameters (v2)
-
-Allows the user to force the supported pcie gen and lane
-config on both the asic and the chipset.
-Useful for debugging pcie problems and for virtualization
-where we may not be able to query the pcie bridge caps.
-
-Default to:
-gen: chipset 1/2, asic 1/2/3
-lanes: 1/2/4/8/16
-
-v2: fix bare metal case
-
-Reviewed-by: monk liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 147 ++++++++++++++++-------------
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++
- 3 files changed, 92 insertions(+), 65 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 06a46f5..cb51310 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -87,6 +87,8 @@ extern int amdgpu_sched_jobs;
- extern int amdgpu_sched_hw_submission;
- extern int amdgpu_enable_semaphores;
- extern int amdgpu_powerplay;
-+extern unsigned amdgpu_pcie_gen_cap;
-+extern unsigned amdgpu_pcie_lane_cap;
-
- #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
- #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index e8905be..51bfc11 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1938,80 +1938,97 @@ retry:
- return r;
- }
-
-+#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
-+#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
-+
- void amdgpu_get_pcie_info(struct amdgpu_device *adev)
- {
- u32 mask;
- int ret;
-
-- if (pci_is_root_bus(adev->pdev->bus))
-- return;
-+ if (amdgpu_pcie_gen_cap)
-+ adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
-
-- if (amdgpu_pcie_gen2 == 0)
-- return;
-+ if (amdgpu_pcie_lane_cap)
-+ adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
-
-- if (adev->flags & AMD_IS_APU)
-+ /* covers APUs as well */
-+ if (pci_is_root_bus(adev->pdev->bus)) {
-+ if (adev->pm.pcie_gen_mask == 0)
-+ adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
-+ if (adev->pm.pcie_mlw_mask == 0)
-+ adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
- return;
-+ }
-
-- ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-- if (!ret) {
-- adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
-- CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-- CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
--
-- if (mask & DRM_PCIE_SPEED_25)
-- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
-- if (mask & DRM_PCIE_SPEED_50)
-- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
-- if (mask & DRM_PCIE_SPEED_80)
-- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
-- }
-- ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
-- if (!ret) {
-- switch (mask) {
-- case 32:
-- adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-- break;
-- case 16:
-- adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-- break;
-- case 12:
-- adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-- break;
-- case 8:
-- adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-- break;
-- case 4:
-- adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-- break;
-- case 2:
-- adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-- CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-- break;
-- case 1:
-- adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
-- break;
-- default:
-- break;
-+ if (adev->pm.pcie_gen_mask == 0) {
-+ ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-+ if (!ret) {
-+ adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
-+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
-+
-+ if (mask & DRM_PCIE_SPEED_25)
-+ adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
-+ if (mask & DRM_PCIE_SPEED_50)
-+ adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
-+ if (mask & DRM_PCIE_SPEED_80)
-+ adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
-+ } else {
-+ adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
-+ }
-+ }
-+ if (adev->pm.pcie_mlw_mask == 0) {
-+ ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
-+ if (!ret) {
-+ switch (mask) {
-+ case 32:
-+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+ break;
-+ case 16:
-+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+ break;
-+ case 12:
-+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+ break;
-+ case 8:
-+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+ break;
-+ case 4:
-+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+ break;
-+ case 2:
-+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
-+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
-+ break;
-+ case 1:
-+ adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
-+ break;
-+ default:
-+ break;
-+ }
-+ } else {
-+ adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
- }
- }
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 9c1af89..9ef1db8 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -83,6 +83,8 @@ int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_enable_semaphores = 0;
- int amdgpu_powerplay = -1;
-+unsigned amdgpu_pcie_gen_cap = 0;
-+unsigned amdgpu_pcie_lane_cap = 0;
-
- MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
- module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
-@@ -170,6 +172,12 @@ MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 =
- module_param_named(powerplay, amdgpu_powerplay, int, 0444);
- #endif
-
-+MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
-+module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
-+
-+MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
-+module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
-+
- static struct pci_device_id pciidlist[] = {
- #ifdef CONFIG_DRM_AMDGPU_CIK
- /* Kaveri */
---
-2.7.4
-