diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch b/common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch new file mode 100644 index 00000000..96c94b43 --- /dev/null +++ b/common/recipes-kernel/linux/files/0184-drm-amdgpu-gfx8-enable-cp-inst-reg-error-interrupts.patch @@ -0,0 +1,49 @@ +From 2cc9910bbf39e0c79338cfb57d0d575d57eddb14 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 2 Feb 2016 14:42:28 -0500 +Subject: [PATCH 0184/1110] drm/amdgpu/gfx8: enable cp inst/reg error + interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enable CP register/instruction error interrupts. Useful +for debugging command stream problems. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index ba3d11a..64a070e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -3901,6 +3901,8 @@ static int gfx_v8_0_hw_fini(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + ++ amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); ++ amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + gfx_v8_0_cp_enable(adev, false); + gfx_v8_0_rlc_stop(adev); + gfx_v8_0_cp_compute_fini(adev); +@@ -4329,6 +4331,14 @@ static int gfx_v8_0_late_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; + ++ r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); ++ if (r) ++ return r; ++ ++ r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); ++ if (r) ++ return r; ++ + /* requires IBs so do in late init after IB pool is initialized */ + r = gfx_v8_0_do_edc_gpr_workarounds(adev); + if (r) +-- +2.7.4 + |