diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0144-drm-amdgpu-add-DCE-8.0-register-headers.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0144-drm-amdgpu-add-DCE-8.0-register-headers.patch | 18848 |
1 files changed, 0 insertions, 18848 deletions
diff --git a/common/recipes-kernel/linux/files/0144-drm-amdgpu-add-DCE-8.0-register-headers.patch b/common/recipes-kernel/linux/files/0144-drm-amdgpu-add-DCE-8.0-register-headers.patch deleted file mode 100644 index db05967b..00000000 --- a/common/recipes-kernel/linux/files/0144-drm-amdgpu-add-DCE-8.0-register-headers.patch +++ /dev/null @@ -1,18848 +0,0 @@ -From 26159c86dd004ef1295da9f68439ae50f3e8e60a Mon Sep 17 00:00:00 2001 -From: Alex Deucher <alexander.deucher@amd.com> -Date: Thu, 16 Apr 2015 15:17:19 -0400 -Subject: [PATCH 0144/1050] drm/amdgpu: add DCE 8.0 register headers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -These are register headers for the DCE (Display and Composition Engine) -block on the GPU. - -Acked-by: Christian König <christian.koenig@amd.com> -Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - .../gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h | 5703 ++++++++ - .../drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h | 13109 +++++++++++++++++++ - 2 files changed, 18812 insertions(+) - create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h - create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h - -diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h -new file mode 100644 -index 0000000..dc52ea0 ---- /dev/null -+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h -@@ -0,0 +1,5703 @@ -+/* -+ * DCE_8_0 Register documentation -+ * -+ * Copyright (C) 2014 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included -+ * in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN -+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#ifndef DCE_8_0_D_H -+#define DCE_8_0_D_H -+ -+#define mmPIPE0_PG_CONFIG 0x1760 -+#define mmPIPE0_PG_ENABLE 0x1761 -+#define mmPIPE0_PG_STATUS 0x1762 -+#define mmPIPE1_PG_CONFIG 0x1764 -+#define mmPIPE1_PG_ENABLE 0x1765 -+#define mmPIPE1_PG_STATUS 0x1766 -+#define mmPIPE2_PG_CONFIG 0x1768 -+#define mmPIPE2_PG_ENABLE 0x1769 -+#define mmPIPE2_PG_STATUS 0x176a -+#define mmPIPE3_PG_CONFIG 0x176c -+#define mmPIPE3_PG_ENABLE 0x176d -+#define mmPIPE3_PG_STATUS 0x176e -+#define mmPIPE4_PG_CONFIG 0x1770 -+#define mmPIPE4_PG_ENABLE 0x1771 -+#define mmPIPE4_PG_STATUS 0x1772 -+#define mmPIPE5_PG_CONFIG 0x1774 -+#define mmPIPE5_PG_ENABLE 0x1775 -+#define mmPIPE5_PG_STATUS 0x1776 -+#define mmDC_IP_REQUEST_CNTL 0x1778 -+#define mmDC_PGFSM_CONFIG_REG 0x177c -+#define mmDC_PGFSM_WRITE_REG 0x177d -+#define mmDC_PGCNTL_STATUS_REG 0x177e -+#define mmDCPG_TEST_DEBUG_INDEX 0x1779 -+#define mmDCPG_TEST_DEBUG_DATA 0x177b -+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 -+#define mmBL1_PWM_USER_LEVEL 0x1629 -+#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a -+#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b -+#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c -+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d -+#define mmBL1_PWM_ABM_CNTL 0x162e -+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f -+#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 -+#define mmDC_ABM1_CNTL 0x1638 -+#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 -+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a -+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b -+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c -+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d -+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e -+#define mmDC_ABM1_ACE_THRES_12 0x163f -+#define mmDC_ABM1_ACE_THRES_34 0x1640 -+#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 -+#define mmDC_ABM1_DEBUG_MISC 0x1649 -+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a -+#define mmDC_ABM1_HG_MISC_CTRL 0x164b -+#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c -+#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d -+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e -+#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f -+#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 -+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 -+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 -+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 -+#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 -+#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 -+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 -+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 -+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 -+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 -+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a -+#define mmDC_ABM1_HG_RESULT_1 0x165b -+#define mmDC_ABM1_HG_RESULT_2 0x165c -+#define mmDC_ABM1_HG_RESULT_3 0x165d -+#define mmDC_ABM1_HG_RESULT_4 0x165e -+#define mmDC_ABM1_HG_RESULT_5 0x165f -+#define mmDC_ABM1_HG_RESULT_6 0x1660 -+#define mmDC_ABM1_HG_RESULT_7 0x1661 -+#define mmDC_ABM1_HG_RESULT_8 0x1662 -+#define mmDC_ABM1_HG_RESULT_9 0x1663 -+#define mmDC_ABM1_HG_RESULT_10 0x1664 -+#define mmDC_ABM1_HG_RESULT_11 0x1665 -+#define mmDC_ABM1_HG_RESULT_12 0x1666 -+#define mmDC_ABM1_HG_RESULT_13 0x1667 -+#define mmDC_ABM1_HG_RESULT_14 0x1668 -+#define mmDC_ABM1_HG_RESULT_15 0x1669 -+#define mmDC_ABM1_HG_RESULT_16 0x166a -+#define mmDC_ABM1_HG_RESULT_17 0x166b -+#define mmDC_ABM1_HG_RESULT_18 0x166c -+#define mmDC_ABM1_HG_RESULT_19 0x166d -+#define mmDC_ABM1_HG_RESULT_20 0x166e -+#define mmDC_ABM1_HG_RESULT_21 0x166f -+#define mmDC_ABM1_HG_RESULT_22 0x1670 -+#define mmDC_ABM1_HG_RESULT_23 0x1671 -+#define mmDC_ABM1_HG_RESULT_24 0x1672 -+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b -+#define mmDC_ABM1_BL_MASTER_LOCK 0x169c -+#define mmABM_TEST_DEBUG_INDEX 0x169e -+#define mmABM_TEST_DEBUG_DATA 0x169f -+#define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c -+#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c -+#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c -+#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c -+#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c -+#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c -+#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c -+#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d -+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d -+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d -+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d -+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d -+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d -+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d -+#define mmDCFE_DBG_SEL 0x1b7e -+#define mmCRTC0_DCFE_DBG_SEL 0x1b7e -+#define mmCRTC1_DCFE_DBG_SEL 0x1e7e -+#define mmCRTC2_DCFE_DBG_SEL 0x417e -+#define mmCRTC3_DCFE_DBG_SEL 0x447e -+#define mmCRTC4_DCFE_DBG_SEL 0x477e -+#define mmCRTC5_DCFE_DBG_SEL 0x4a7e -+#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f -+#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f -+#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f -+#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f -+#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f -+#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f -+#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f -+#define mmCRTC_H_TOTAL 0x1b80 -+#define mmCRTC0_CRTC_H_TOTAL 0x1b80 -+#define mmCRTC1_CRTC_H_TOTAL 0x1e80 -+#define mmCRTC2_CRTC_H_TOTAL 0x4180 -+#define mmCRTC3_CRTC_H_TOTAL 0x4480 -+#define mmCRTC4_CRTC_H_TOTAL 0x4780 -+#define mmCRTC5_CRTC_H_TOTAL 0x4a80 -+#define mmCRTC_H_BLANK_START_END 0x1b81 -+#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 -+#define mmCRTC1_CRTC_H_BLANK_START_END 0x1e81 -+#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 -+#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 -+#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 -+#define mmCRTC5_CRTC_H_BLANK_START_END 0x4a81 -+#define mmCRTC_H_SYNC_A 0x1b82 -+#define mmCRTC0_CRTC_H_SYNC_A 0x1b82 -+#define mmCRTC1_CRTC_H_SYNC_A 0x1e82 -+#define mmCRTC2_CRTC_H_SYNC_A 0x4182 -+#define mmCRTC3_CRTC_H_SYNC_A 0x4482 -+#define mmCRTC4_CRTC_H_SYNC_A 0x4782 -+#define mmCRTC5_CRTC_H_SYNC_A 0x4a82 -+#define mmCRTC_H_SYNC_A_CNTL 0x1b83 -+#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 -+#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83 -+#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 -+#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 -+#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 -+#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83 -+#define mmCRTC_H_SYNC_B 0x1b84 -+#define mmCRTC0_CRTC_H_SYNC_B 0x1b84 -+#define mmCRTC1_CRTC_H_SYNC_B 0x1e84 -+#define mmCRTC2_CRTC_H_SYNC_B 0x4184 -+#define mmCRTC3_CRTC_H_SYNC_B 0x4484 -+#define mmCRTC4_CRTC_H_SYNC_B 0x4784 -+#define mmCRTC5_CRTC_H_SYNC_B 0x4a84 -+#define mmCRTC_H_SYNC_B_CNTL 0x1b85 -+#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 -+#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85 -+#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 -+#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 -+#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 -+#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85 -+#define mmCRTC_VBI_END 0x1b86 -+#define mmCRTC0_CRTC_VBI_END 0x1b86 -+#define mmCRTC1_CRTC_VBI_END 0x1e86 -+#define mmCRTC2_CRTC_VBI_END 0x4186 -+#define mmCRTC3_CRTC_VBI_END 0x4486 -+#define mmCRTC4_CRTC_VBI_END 0x4786 -+#define mmCRTC5_CRTC_VBI_END 0x4a86 -+#define mmCRTC_V_TOTAL 0x1b87 -+#define mmCRTC0_CRTC_V_TOTAL 0x1b87 -+#define mmCRTC1_CRTC_V_TOTAL 0x1e87 -+#define mmCRTC2_CRTC_V_TOTAL 0x4187 -+#define mmCRTC3_CRTC_V_TOTAL 0x4487 -+#define mmCRTC4_CRTC_V_TOTAL 0x4787 -+#define mmCRTC5_CRTC_V_TOTAL 0x4a87 -+#define mmCRTC_V_TOTAL_MIN 0x1b88 -+#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 -+#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88 -+#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 -+#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 -+#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 -+#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88 -+#define mmCRTC_V_TOTAL_MAX 0x1b89 -+#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 -+#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89 -+#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 -+#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 -+#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 -+#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89 -+#define mmCRTC_V_TOTAL_CONTROL 0x1b8a -+#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a -+#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a -+#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a -+#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a -+#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a -+#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a -+#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b -+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b -+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b -+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b -+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b -+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b -+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b -+#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c -+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c -+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c -+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c -+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c -+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c -+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c -+#define mmCRTC_V_BLANK_START_END 0x1b8d -+#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d -+#define mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d -+#define mmCRTC2_CRTC_V_BLANK_START_END 0x418d -+#define mmCRTC3_CRTC_V_BLANK_START_END 0x448d -+#define mmCRTC4_CRTC_V_BLANK_START_END 0x478d -+#define mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d -+#define mmCRTC_V_SYNC_A 0x1b8e -+#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e -+#define mmCRTC1_CRTC_V_SYNC_A 0x1e8e -+#define mmCRTC2_CRTC_V_SYNC_A 0x418e -+#define mmCRTC3_CRTC_V_SYNC_A 0x448e -+#define mmCRTC4_CRTC_V_SYNC_A 0x478e -+#define mmCRTC5_CRTC_V_SYNC_A 0x4a8e -+#define mmCRTC_V_SYNC_A_CNTL 0x1b8f -+#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f -+#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f -+#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f -+#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f -+#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f -+#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f -+#define mmCRTC_V_SYNC_B 0x1b90 -+#define mmCRTC0_CRTC_V_SYNC_B 0x1b90 -+#define mmCRTC1_CRTC_V_SYNC_B 0x1e90 -+#define mmCRTC2_CRTC_V_SYNC_B 0x4190 -+#define mmCRTC3_CRTC_V_SYNC_B 0x4490 -+#define mmCRTC4_CRTC_V_SYNC_B 0x4790 -+#define mmCRTC5_CRTC_V_SYNC_B 0x4a90 -+#define mmCRTC_V_SYNC_B_CNTL 0x1b91 -+#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 -+#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91 -+#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 -+#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 -+#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 -+#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91 -+#define mmCRTC_DTMTEST_CNTL 0x1b92 -+#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 -+#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92 -+#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 -+#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 -+#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 -+#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92 -+#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 -+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 -+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93 -+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 -+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 -+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 -+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93 -+#define mmCRTC_TRIGA_CNTL 0x1b94 -+#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 -+#define mmCRTC1_CRTC_TRIGA_CNTL 0x1e94 -+#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 -+#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 -+#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 -+#define mmCRTC5_CRTC_TRIGA_CNTL 0x4a94 -+#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 -+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 -+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95 -+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 -+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 -+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 -+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95 -+#define mmCRTC_TRIGB_CNTL 0x1b96 -+#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 -+#define mmCRTC1_CRTC_TRIGB_CNTL 0x1e96 -+#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 -+#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 -+#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 -+#define mmCRTC5_CRTC_TRIGB_CNTL 0x4a96 -+#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 -+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 -+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97 -+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 -+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 -+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 -+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97 -+#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 -+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98 -+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 -+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 -+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 -+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98 -+#define mmCRTC_FLOW_CONTROL 0x1b99 -+#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 -+#define mmCRTC1_CRTC_FLOW_CONTROL 0x1e99 -+#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 -+#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 -+#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 -+#define mmCRTC5_CRTC_FLOW_CONTROL 0x4a99 -+#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b -+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b -+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b -+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b -+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b -+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b -+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b -+#define mmCRTC_CONTROL 0x1b9c -+#define mmCRTC0_CRTC_CONTROL 0x1b9c -+#define mmCRTC1_CRTC_CONTROL 0x1e9c -+#define mmCRTC2_CRTC_CONTROL 0x419c -+#define mmCRTC3_CRTC_CONTROL 0x449c -+#define mmCRTC4_CRTC_CONTROL 0x479c -+#define mmCRTC5_CRTC_CONTROL 0x4a9c -+#define mmCRTC_BLANK_CONTROL 0x1b9d -+#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d -+#define mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d -+#define mmCRTC2_CRTC_BLANK_CONTROL 0x419d -+#define mmCRTC3_CRTC_BLANK_CONTROL 0x449d -+#define mmCRTC4_CRTC_BLANK_CONTROL 0x479d -+#define mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d -+#define mmCRTC_INTERLACE_CONTROL 0x1b9e -+#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e -+#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e -+#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e -+#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e -+#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e -+#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e -+#define mmCRTC_INTERLACE_STATUS 0x1b9f -+#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f -+#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f -+#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419f -+#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449f -+#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479f -+#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f -+#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 -+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 -+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0 -+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0 -+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0 -+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0 -+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0 -+#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 -+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 -+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1 -+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1 -+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1 -+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1 -+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1 -+#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 -+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 -+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2 -+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2 -+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2 -+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2 -+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2 -+#define mmCRTC_STATUS 0x1ba3 -+#define mmCRTC0_CRTC_STATUS 0x1ba3 -+#define mmCRTC1_CRTC_STATUS 0x1ea3 -+#define mmCRTC2_CRTC_STATUS 0x41a3 -+#define mmCRTC3_CRTC_STATUS 0x44a3 -+#define mmCRTC4_CRTC_STATUS 0x47a3 -+#define mmCRTC5_CRTC_STATUS 0x4aa3 -+#define mmCRTC_STATUS_POSITION 0x1ba4 -+#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 -+#define mmCRTC1_CRTC_STATUS_POSITION 0x1ea4 -+#define mmCRTC2_CRTC_STATUS_POSITION 0x41a4 -+#define mmCRTC3_CRTC_STATUS_POSITION 0x44a4 -+#define mmCRTC4_CRTC_STATUS_POSITION 0x47a4 -+#define mmCRTC5_CRTC_STATUS_POSITION 0x4aa4 -+#define mmCRTC_NOM_VERT_POSITION 0x1ba5 -+#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 -+#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5 -+#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5 -+#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5 -+#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5 -+#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5 -+#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 -+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 -+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6 -+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6 -+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6 -+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6 -+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6 -+#define mmCRTC_STATUS_VF_COUNT 0x1ba7 -+#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 -+#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7 -+#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7 -+#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7 -+#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7 -+#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7 -+#define mmCRTC_STATUS_HV_COUNT 0x1ba8 -+#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 -+#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8 -+#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8 -+#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8 -+#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8 -+#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8 -+#define mmCRTC_COUNT_CONTROL 0x1ba9 -+#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 -+#define mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9 -+#define mmCRTC2_CRTC_COUNT_CONTROL 0x41a9 -+#define mmCRTC3_CRTC_COUNT_CONTROL 0x44a9 -+#define mmCRTC4_CRTC_COUNT_CONTROL 0x47a9 -+#define mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9 -+#define mmCRTC_COUNT_RESET 0x1baa -+#define mmCRTC0_CRTC_COUNT_RESET 0x1baa -+#define mmCRTC1_CRTC_COUNT_RESET 0x1eaa -+#define mmCRTC2_CRTC_COUNT_RESET 0x41aa -+#define mmCRTC3_CRTC_COUNT_RESET 0x44aa -+#define mmCRTC4_CRTC_COUNT_RESET 0x47aa -+#define mmCRTC5_CRTC_COUNT_RESET 0x4aaa -+#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab -+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab -+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab -+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab -+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab -+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab -+#define mmCRTC_VERT_SYNC_CONTROL 0x1bac -+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac -+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac -+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac -+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac -+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac -+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac -+#define mmCRTC_STEREO_STATUS 0x1bad -+#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad -+#define mmCRTC1_CRTC_STEREO_STATUS 0x1ead -+#define mmCRTC2_CRTC_STEREO_STATUS 0x41ad -+#define mmCRTC3_CRTC_STEREO_STATUS 0x44ad -+#define mmCRTC4_CRTC_STEREO_STATUS 0x47ad -+#define mmCRTC5_CRTC_STEREO_STATUS 0x4aad -+#define mmCRTC_STEREO_CONTROL 0x1bae -+#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae -+#define mmCRTC1_CRTC_STEREO_CONTROL 0x1eae -+#define mmCRTC2_CRTC_STEREO_CONTROL 0x41ae -+#define mmCRTC3_CRTC_STEREO_CONTROL 0x44ae -+#define mmCRTC4_CRTC_STEREO_CONTROL 0x47ae -+#define mmCRTC5_CRTC_STEREO_CONTROL 0x4aae -+#define mmCRTC_SNAPSHOT_STATUS 0x1baf -+#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf -+#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf -+#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af -+#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af -+#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af -+#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf -+#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 -+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 -+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0 -+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0 -+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0 -+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0 -+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0 -+#define mmCRTC_SNAPSHOT_POSITION 0x1bb1 -+#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 -+#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1 -+#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1 -+#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1 -+#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1 -+#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1 -+#define mmCRTC_SNAPSHOT_FRAME 0x1bb2 -+#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 -+#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2 -+#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2 -+#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2 -+#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2 -+#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2 -+#define mmCRTC_START_LINE_CONTROL 0x1bb3 -+#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 -+#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3 -+#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3 -+#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3 -+#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3 -+#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3 -+#define mmCRTC_INTERRUPT_CONTROL 0x1bb4 -+#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 -+#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4 -+#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4 -+#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4 -+#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4 -+#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4 -+#define mmCRTC_UPDATE_LOCK 0x1bb5 -+#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 -+#define mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5 -+#define mmCRTC2_CRTC_UPDATE_LOCK 0x41b5 -+#define mmCRTC3_CRTC_UPDATE_LOCK 0x44b5 -+#define mmCRTC4_CRTC_UPDATE_LOCK 0x47b5 -+#define mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5 -+#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 -+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6 -+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 -+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6 -+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 -+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6 -+#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 -+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7 -+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 -+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7 -+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 -+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7 -+#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba -+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba -+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba -+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba -+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba -+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba -+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba -+#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb -+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb -+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb -+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb -+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb -+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb -+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb -+#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc -+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc -+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc -+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc -+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc -+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc -+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc -+#define mmMASTER_UPDATE_LOCK 0x1bbd -+#define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd -+#define mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd -+#define mmCRTC2_MASTER_UPDATE_LOCK 0x41bd -+#define mmCRTC3_MASTER_UPDATE_LOCK 0x44bd -+#define mmCRTC4_MASTER_UPDATE_LOCK 0x47bd -+#define mmCRTC5_MASTER_UPDATE_LOCK 0x4abd -+#define mmMASTER_UPDATE_MODE 0x1bbe -+#define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe -+#define mmCRTC1_MASTER_UPDATE_MODE 0x1ebe -+#define mmCRTC2_MASTER_UPDATE_MODE 0x41be -+#define mmCRTC3_MASTER_UPDATE_MODE 0x44be -+#define mmCRTC4_MASTER_UPDATE_MODE 0x47be -+#define mmCRTC5_MASTER_UPDATE_MODE 0x4abe -+#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf -+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf -+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf -+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf -+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf -+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf -+#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 -+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0 -+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 -+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0 -+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 -+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0 -+#define mmCRTC_MVP_STATUS 0x1bc1 -+#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 -+#define mmCRTC1_CRTC_MVP_STATUS 0x1ec1 -+#define mmCRTC2_CRTC_MVP_STATUS 0x41c1 -+#define mmCRTC3_CRTC_MVP_STATUS 0x44c1 -+#define mmCRTC4_CRTC_MVP_STATUS 0x47c1 -+#define mmCRTC5_CRTC_MVP_STATUS 0x4ac1 -+#define mmCRTC_MASTER_EN 0x1bc2 -+#define mmCRTC0_CRTC_MASTER_EN 0x1bc2 -+#define mmCRTC1_CRTC_MASTER_EN 0x1ec2 -+#define mmCRTC2_CRTC_MASTER_EN 0x41c2 -+#define mmCRTC3_CRTC_MASTER_EN 0x44c2 -+#define mmCRTC4_CRTC_MASTER_EN 0x47c2 -+#define mmCRTC5_CRTC_MASTER_EN 0x4ac2 -+#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 -+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3 -+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 -+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3 -+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 -+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3 -+#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 -+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 -+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4 -+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4 -+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4 -+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4 -+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4 -+#define mmCRTC_OVERSCAN_COLOR 0x1bc8 -+#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 -+#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8 -+#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8 -+#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8 -+#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8 -+#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8 -+#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 -+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 -+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9 -+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9 -+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9 -+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9 -+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9 -+#define mmCRTC_BLANK_DATA_COLOR 0x1bca -+#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca -+#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca -+#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca -+#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca -+#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca -+#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca -+#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb -+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb -+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb -+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb -+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb -+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb -+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb -+#define mmCRTC_BLACK_COLOR 0x1bcc -+#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc -+#define mmCRTC1_CRTC_BLACK_COLOR 0x1ecc -+#define mmCRTC2_CRTC_BLACK_COLOR 0x41cc -+#define mmCRTC3_CRTC_BLACK_COLOR 0x44cc -+#define mmCRTC4_CRTC_BLACK_COLOR 0x47cc -+#define mmCRTC5_CRTC_BLACK_COLOR 0x4acc -+#define mmCRTC_BLACK_COLOR_EXT 0x1bcd -+#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd -+#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd -+#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd -+#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd -+#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd -+#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd -+#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce -+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece -+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce -+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce -+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce -+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace -+#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf -+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf -+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf -+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf -+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf -+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf -+#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 -+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0 -+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 -+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0 -+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 -+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0 -+#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 -+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1 -+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 -+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1 -+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 -+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1 -+#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 -+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2 -+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 -+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2 -+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 -+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2 -+#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 -+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3 -+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 -+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3 -+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 -+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3 -+#define mmCRTC_CRC_CNTL 0x1bd4 -+#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 -+#define mmCRTC1_CRTC_CRC_CNTL 0x1ed4 -+#define mmCRTC2_CRTC_CRC_CNTL 0x41d4 -+#define mmCRTC3_CRTC_CRC_CNTL 0x44d4 -+#define mmCRTC4_CRTC_CRC_CNTL 0x47d4 -+#define mmCRTC5_CRTC_CRC_CNTL 0x4ad4 -+#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 -+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5 -+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 -+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5 -+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 -+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5 -+#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 -+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6 -+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 -+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6 -+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 -+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6 -+#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 -+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7 -+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 -+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7 -+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 -+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7 -+#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 -+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8 -+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 -+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8 -+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 -+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8 -+#define mmCRTC_CRC0_DATA_RG 0x1bd9 -+#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 -+#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9 -+#define mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9 -+#define mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9 -+#define mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9 -+#define mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9 -+#define mmCRTC_CRC0_DATA_B 0x1bda -+#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda -+#define mmCRTC1_CRTC_CRC0_DATA_B 0x1eda -+#define mmCRTC2_CRTC_CRC0_DATA_B 0x41da -+#define mmCRTC3_CRTC_CRC0_DATA_B 0x44da -+#define mmCRTC4_CRTC_CRC0_DATA_B 0x47da -+#define mmCRTC5_CRTC_CRC0_DATA_B 0x4ada -+#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb -+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb -+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db -+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db -+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db -+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb -+#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc -+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc -+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc -+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc -+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc -+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc -+#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd -+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd -+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd -+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd -+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd -+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add -+#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde -+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede -+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de -+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de -+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de -+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade -+#define mmCRTC_CRC1_DATA_RG 0x1bdf -+#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf -+#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf -+#define mmCRTC2_CRTC_CRC1_DATA_RG 0x41df -+#define mmCRTC3_CRTC_CRC1_DATA_RG 0x44df -+#define mmCRTC4_CRTC_CRC1_DATA_RG 0x47df -+#define mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf -+#define mmCRTC_CRC1_DATA_B 0x1be0 -+#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 -+#define mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0 -+#define mmCRTC2_CRTC_CRC1_DATA_B 0x41e0 -+#define mmCRTC3_CRTC_CRC1_DATA_B 0x44e0 -+#define mmCRTC4_CRTC_CRC1_DATA_B 0x47e0 -+#define mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0 -+#define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 -+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 -+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1 -+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 -+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1 -+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 -+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1 -+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 -+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 -+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2 -+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 -+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2 -+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 -+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2 -+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 -+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 -+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3 -+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 -+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3 -+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 -+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3 -+#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 -+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 -+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4 -+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 -+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4 -+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 -+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4 -+#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 -+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 -+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5 -+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 -+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5 -+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 -+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5 -+#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 -+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 -+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6 -+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 -+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6 -+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 -+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6 -+#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 -+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 -+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7 -+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7 -+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7 -+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7 -+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7 -+#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 -+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 -+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78 -+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 -+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 -+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 -+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78 -+#define mmCRTC_GSL_VSYNC_GAP 0x1b79 -+#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 -+#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79 -+#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 -+#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 -+#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 -+#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79 -+#define mmCRTC_GSL_WINDOW 0x1b7a -+#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a -+#define mmCRTC1_CRTC_GSL_WINDOW 0x1e7a -+#define mmCRTC2_CRTC_GSL_WINDOW 0x417a -+#define mmCRTC3_CRTC_GSL_WINDOW 0x447a -+#define mmCRTC4_CRTC_GSL_WINDOW 0x477a -+#define mmCRTC5_CRTC_GSL_WINDOW 0x4a7a -+#define mmCRTC_GSL_CONTROL 0x1b7b -+#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b -+#define mmCRTC1_CRTC_GSL_CONTROL 0x1e7b -+#define mmCRTC2_CRTC_GSL_CONTROL 0x417b -+#define mmCRTC3_CRTC_GSL_CONTROL 0x447b -+#define mmCRTC4_CRTC_GSL_CONTROL 0x477b -+#define mmCRTC5_CRTC_GSL_CONTROL 0x4a7b -+#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 -+#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 -+#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6 -+#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6 -+#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6 -+#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6 -+#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6 -+#define mmCRTC_TEST_DEBUG_DATA 0x1bc7 -+#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 -+#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7 -+#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7 -+#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7 -+#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7 -+#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7 -+#define mmDAC_ENABLE 0x19e4 -+#define mmDAC_SOURCE_SELECT 0x19e5 -+#define mmDAC_CRC_EN 0x19e6 -+#define mmDAC_CRC_CONTROL 0x19e7 -+#define mmDAC_CRC_SIG_RGB_MASK 0x19e8 -+#define mmDAC_CRC_SIG_CONTROL_MASK 0x19e9 -+#define mmDAC_CRC_SIG_RGB 0x19ea -+#define mmDAC_CRC_SIG_CONTROL 0x19eb -+#define mmDAC_SYNC_TRISTATE_CONTROL 0x19ec -+#define mmDAC_STEREOSYNC_SELECT 0x19ed -+#define mmDAC_AUTODETECT_CONTROL 0x19ee -+#define mmDAC_AUTODETECT_CONTROL2 0x19ef -+#define mmDAC_AUTODETECT_CONTROL3 0x19f0 -+#define mmDAC_AUTODETECT_STATUS 0x19f1 -+#define mmDAC_AUTODETECT_INT_CONTROL 0x19f2 -+#define mmDAC_FORCE_OUTPUT_CNTL 0x19f3 -+#define mmDAC_FORCE_DATA 0x19f4 -+#define mmDAC_POWERDOWN 0x19f5 -+#define mmDAC_CONTROL 0x19f6 -+#define mmDAC_COMPARATOR_ENABLE 0x19f7 -+#define mmDAC_COMPARATOR_OUTPUT 0x19f8 -+#define mmDAC_PWR_CNTL 0x19f9 -+#define mmDAC_DFT_CONFIG 0x19fa -+#define mmDAC_FIFO_STATUS 0x19fb -+#define mmPERFCOUNTER_CNTL 0x170 -+#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 -+#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870 -+#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24 -+#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24 -+#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124 -+#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424 -+#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724 -+#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24 -+#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40 -+#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14 -+#define mmPERFCOUNTER_STATE 0x171 -+#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 -+#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871 -+#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25 -+#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25 -+#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125 -+#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425 -+#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725 -+#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25 -+#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41 -+#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15 -+#define mmPERFMON_CNTL 0x173 -+#define mmDC_PERFMON0_PERFMON_CNTL 0x173 -+#define mmDC_PERFMON1_PERFMON_CNTL 0x1873 -+#define mmDC_PERFMON2_PERFMON_CNTL 0x1b27 -+#define mmDC_PERFMON3_PERFMON_CNTL 0x1e27 -+#define mmDC_PERFMON4_PERFMON_CNTL 0x4127 -+#define mmDC_PERFMON5_PERFMON_CNTL 0x4427 -+#define mmDC_PERFMON6_PERFMON_CNTL 0x4727 -+#define mmDC_PERFMON7_PERFMON_CNTL 0x4a27 -+#define mmDC_PERFMON8_PERFMON_CNTL 0x4c43 -+#define mmDC_PERFMON9_PERFMON_CNTL 0x4d17 -+#define mmPERFMON_CVALUE_INT_MISC 0x172 -+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 -+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872 -+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26 -+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26 -+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126 -+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426 -+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726 -+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26 -+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42 -+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16 -+#define mmPERFMON_CVALUE_LOW 0x174 -+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 -+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874 -+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28 -+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28 -+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128 -+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428 -+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728 -+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28 -+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44 -+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18 -+#define mmPERFMON_HI 0x175 -+#define mmDC_PERFMON0_PERFMON_HI 0x175 -+#define mmDC_PERFMON1_PERFMON_HI 0x1875 -+#define mmDC_PERFMON2_PERFMON_HI 0x1b29 -+#define mmDC_PERFMON3_PERFMON_HI 0x1e29 -+#define mmDC_PERFMON4_PERFMON_HI 0x4129 -+#define mmDC_PERFMON5_PERFMON_HI 0x4429 -+#define mmDC_PERFMON6_PERFMON_HI 0x4729 -+#define mmDC_PERFMON7_PERFMON_HI 0x4a29 -+#define mmDC_PERFMON8_PERFMON_HI 0x4c45 -+#define mmDC_PERFMON9_PERFMON_HI 0x4d19 -+#define mmPERFMON_LOW 0x176 -+#define mmDC_PERFMON0_PERFMON_LOW 0x176 -+#define mmDC_PERFMON1_PERFMON_LOW 0x1876 -+#define mmDC_PERFMON2_PERFMON_LOW 0x1b2a -+#define mmDC_PERFMON3_PERFMON_LOW 0x1e2a -+#define mmDC_PERFMON4_PERFMON_LOW 0x412a -+#define mmDC_PERFMON5_PERFMON_LOW 0x442a -+#define mmDC_PERFMON6_PERFMON_LOW 0x472a -+#define mmDC_PERFMON7_PERFMON_LOW 0x4a2a -+#define mmDC_PERFMON8_PERFMON_LOW 0x4c46 -+#define mmDC_PERFMON9_PERFMON_LOW 0x4d1a -+#define mmPERFMON_TEST_DEBUG_INDEX 0x177 -+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 -+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877 -+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b -+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b -+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b -+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b -+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b -+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b -+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47 -+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b -+#define mmPERFMON_TEST_DEBUG_DATA 0x178 -+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 -+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878 -+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c -+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c -+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c -+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c -+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c -+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c -+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48 -+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c -+#define mmVGA25_PPLL_REF_DIV 0xd8 -+#define mmVGA28_PPLL_REF_DIV 0xd9 -+#define mmVGA41_PPLL_REF_DIV 0xda -+#define mmVGA25_PPLL_FB_DIV 0xdc -+#define mmVGA28_PPLL_FB_DIV 0xdd -+#define mmVGA41_PPLL_FB_DIV 0xde -+#define mmVGA25_PPLL_POST_DIV 0xe0 -+#define mmVGA28_PPLL_POST_DIV 0xe1 -+#define mmVGA41_PPLL_POST_DIV 0xe2 -+#define mmVGA25_PPLL_ANALOG 0xe4 -+#define mmVGA28_PPLL_ANALOG 0xe5 -+#define mmVGA41_PPLL_ANALOG 0xe6 -+#define mmDPREFCLK_CNTL 0x118 -+#define mmSCANIN_SOFT_RESET 0x11e -+#define mmDCCG_GTC_CNTL 0x120 -+#define mmDCCG_GTC_DTO_INCR 0x121 -+#define mmDCCG_GTC_DTO_MODULO 0x122 -+#define mmDCCG_GTC_CURRENT 0x123 -+#define mmDCCG_DS_DTO_INCR 0x113 -+#define mmDCCG_DS_DTO_MODULO 0x114 -+#define mmDCCG_DS_CNTL 0x115 -+#define mmDCCG_DS_HW_CAL_INTERVAL 0x116 -+#define mmDCCG_DS_DEBUG_CNTL 0x112 -+#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c -+#define mmSMU_CONTROL 0x12d -+#define mmSMU_INTERRUPT_CONTROL 0x12e -+#define mmDAC_CLK_ENABLE 0x128 -+#define mmDVO_CLK_ENABLE 0x129 -+#define mmDCCG_GATE_DISABLE_CNTL 0x134 -+#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 -+#define mmSCLK_CGTT_BLK_CTRL_REG 0x136 -+#define mmDCCG_CAC_STATUS 0x137 -+#define mmPIXCLK1_RESYNC_CNTL 0x138 -+#define mmPIXCLK2_RESYNC_CNTL 0x139 -+#define mmPIXCLK0_RESYNC_CNTL 0x13a -+#define mmMICROSECOND_TIME_BASE_DIV 0x13b -+#define mmDCCG_DISP_CNTL_REG 0x13f -+#define mmDISPPLL_BG_CNTL 0x13c -+#define mmDIG_SOFT_RESET 0x13d -+#define mmMILLISECOND_TIME_BASE_DIV 0x130 -+#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 -+#define mmLIGHT_SLEEP_CNTL 0x132 -+#define mmDCCG_PERFMON_CNTL 0x133 -+#define mmCRTC0_PIXEL_RATE_CNTL 0x140 -+#define mmDP_DTO0_PHASE 0x141 -+#define mmDP_DTO0_MODULO 0x142 -+#define mmCRTC1_PIXEL_RATE_CNTL 0x144 -+#define mmDP_DTO1_PHASE 0x145 -+#define mmDP_DTO1_MODULO 0x146 -+#define mmCRTC2_PIXEL_RATE_CNTL 0x148 -+#define mmDP_DTO2_PHASE 0x149 -+#define mmDP_DTO2_MODULO 0x14a -+#define mmCRTC3_PIXEL_RATE_CNTL 0x14c -+#define mmDP_DTO3_PHASE 0x14d -+#define mmDP_DTO3_MODULO 0x14e -+#define mmCRTC4_PIXEL_RATE_CNTL 0x150 -+#define mmDP_DTO4_PHASE 0x151 -+#define mmDP_DTO4_MODULO 0x152 -+#define mmCRTC5_PIXEL_RATE_CNTL 0x154 -+#define mmDP_DTO5_PHASE 0x155 -+#define mmDP_DTO5_MODULO 0x156 -+#define mmDCFE0_SOFT_RESET 0x158 -+#define mmDCFE1_SOFT_RESET 0x159 -+#define mmDCFE2_SOFT_RESET 0x15a -+#define mmDCFE3_SOFT_RESET 0x15b -+#define mmDCFE4_SOFT_RESET 0x15c -+#define mmDCFE5_SOFT_RESET 0x15d -+#define mmDCI_SOFT_RESET 0x15e -+#define mmDCCG_SOFT_RESET 0x15f -+#define mmSYMCLKA_CLOCK_ENABLE 0x160 -+#define mmSYMCLKB_CLOCK_ENABLE 0x161 -+#define mmSYMCLKC_CLOCK_ENABLE 0x162 -+#define mmSYMCLKD_CLOCK_ENABLE 0x163 -+#define mmSYMCLKE_CLOCK_ENABLE 0x164 -+#define mmSYMCLKF_CLOCK_ENABLE 0x165 -+#define mmSYMCLKG_CLOCK_ENABLE 0x117 -+#define mmUNIPHY_SOFT_RESET 0x166 -+#define mmDCO_SOFT_RESET 0x167 -+#define mmDVOACLKD_CNTL 0x168 -+#define mmDVOACLKC_MVP_CNTL 0x169 -+#define mmDVOACLKC_CNTL 0x16a -+#define mmDCCG_AUDIO_DTO_SOURCE 0x16b -+#define mmDCCG_AUDIO_DTO0_PHASE 0x16c -+#define mmDCCG_AUDIO_DTO0_MODULE 0x16d -+#define mmDCCG_AUDIO_DTO1_PHASE 0x16e -+#define mmDCCG_AUDIO_DTO1_MODULE 0x16f -+#define mmDCCG_TEST_DEBUG_INDEX 0x17c -+#define mmDCCG_TEST_DEBUG_DATA 0x17d -+#define mmDCCG_TEST_CLK_SEL 0x17e -+#define mmPLL_REF_DIV 0x1700 -+#define mmDCCG_PLL0_PLL_REF_DIV 0x1700 -+#define mmDCCG_PLL1_PLL_REF_DIV 0x1714 -+#define mmDCCG_PLL2_PLL_REF_DIV 0x1728 -+#define mmDCCG_PLL3_PLL_REF_DIV 0x173c -+#define mmPLL_FB_DIV 0x1701 -+#define mmDCCG_PLL0_PLL_FB_DIV 0x1701 -+#define mmDCCG_PLL1_PLL_FB_DIV 0x1715 -+#define mmDCCG_PLL2_PLL_FB_DIV 0x1729 -+#define mmDCCG_PLL3_PLL_FB_DIV 0x173d -+#define mmPLL_POST_DIV 0x1702 -+#define mmDCCG_PLL0_PLL_POST_DIV 0x1702 -+#define mmDCCG_PLL1_PLL_POST_DIV 0x1716 -+#define mmDCCG_PLL2_PLL_POST_DIV 0x172a -+#define mmDCCG_PLL3_PLL_POST_DIV 0x173e -+#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 -+#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 -+#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717 -+#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b -+#define mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f -+#define mmPLL_SS_CNTL 0x1704 -+#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 -+#define mmDCCG_PLL1_PLL_SS_CNTL 0x1718 -+#define mmDCCG_PLL2_PLL_SS_CNTL 0x172c -+#define mmDCCG_PLL3_PLL_SS_CNTL 0x1740 -+#define mmPLL_DS_CNTL 0x1705 -+#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 -+#define mmDCCG_PLL1_PLL_DS_CNTL 0x1719 -+#define mmDCCG_PLL2_PLL_DS_CNTL 0x172d -+#define mmDCCG_PLL3_PLL_DS_CNTL 0x1741 -+#define mmPLL_IDCLK_CNTL 0x1706 -+#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 -+#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a -+#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e -+#define mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742 -+#define mmPLL_CNTL 0x1707 -+#define mmDCCG_PLL0_PLL_CNTL 0x1707 -+#define mmDCCG_PLL1_PLL_CNTL 0x171b -+#define mmDCCG_PLL2_PLL_CNTL 0x172f -+#define mmDCCG_PLL3_PLL_CNTL 0x1743 -+#define mmPLL_ANALOG 0x1708 -+#define mmDCCG_PLL0_PLL_ANALOG 0x1708 -+#define mmDCCG_PLL1_PLL_ANALOG 0x171c -+#define mmDCCG_PLL2_PLL_ANALOG 0x1730 -+#define mmDCCG_PLL3_PLL_ANALOG 0x1744 -+#define mmPLL_ANALOG_CNTL 0x1711 -+#define mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711 -+#define mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725 -+#define mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739 -+#define mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d -+#define mmPLL_VREG_CNTL 0x1709 -+#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 -+#define mmDCCG_PLL1_PLL_VREG_CNTL 0x171d -+#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1731 -+#define mmDCCG_PLL3_PLL_VREG_CNTL 0x1745 -+#define mmPLL_XOR_LOCK 0x1710 -+#define mmDCCG_PLL0_PLL_XOR_LOCK 0x1710 -+#define mmDCCG_PLL1_PLL_XOR_LOCK 0x1724 -+#define mmDCCG_PLL2_PLL_XOR_LOCK 0x1738 -+#define mmDCCG_PLL3_PLL_XOR_LOCK 0x174c -+#define mmPLL_UNLOCK_DETECT_CNTL 0x170a -+#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a -+#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e -+#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732 -+#define mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746 -+#define mmPLL_DEBUG_CNTL 0x170b -+#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b -+#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f -+#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733 -+#define mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747 -+#define mmPLL_UPDATE_LOCK 0x170c -+#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c -+#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720 -+#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734 -+#define mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748 -+#define mmPLL_UPDATE_CNTL 0x170d -+#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d -+#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721 -+#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735 -+#define mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749 -+#define mmPLL_DISPCLK_DTO_CNTL 0x170e -+#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e -+#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722 -+#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736 -+#define mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a -+#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f -+#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f -+#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723 -+#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737 -+#define mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b -+#define mmDENTIST_DISPCLK_CNTL 0x124 -+#define mmDCDEBUG_BUS_CLK1_SEL 0x1860 -+#define mmDCDEBUG_BUS_CLK2_SEL 0x1861 -+#define mmDCDEBUG_BUS_CLK3_SEL 0x1862 -+#define mmDCDEBUG_BUS_CLK4_SEL 0x1863 -+#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a -+#define mmDCDEBUG_OUT_CNTL 0x186b -+#define mmDCDEBUG_OUT_DATA 0x186e -+#define mmDMIF_ADDR_CONFIG 0x2f5 -+#define mmDMIF_CONTROL 0x2f6 -+#define mmDMIF_STATUS 0x2f7 -+#define mmDMIF_HW_DEBUG 0x2f8 -+#define mmDMIF_ARBITRATION_CONTROL 0x2f9 -+#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa -+#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb -+#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc -+#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd -+#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe -+#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff -+#define mmDMIF_TEST_DEBUG_INDEX 0x312 -+#define mmDMIF_TEST_DEBUG_DATA 0x313 -+#define ixDMIF_DEBUG02_CORE0 0x2 -+#define ixDMIF_DEBUG02_CORE1 0xa -+#define mmDMIF_ADDR_CALC 0x300 -+#define mmDMIF_STATUS2 0x301 -+#define mmPIPE0_MAX_REQUESTS 0x302 -+#define mmPIPE1_MAX_REQUESTS 0x303 -+#define mmPIPE2_MAX_REQUESTS 0x304 -+#define mmPIPE3_MAX_REQUESTS 0x305 -+#define mmPIPE4_MAX_REQUESTS 0x306 -+#define mmPIPE5_MAX_REQUESTS 0x307 -+#define mmLOW_POWER_TILING_CONTROL 0x325 -+#define mmMCIF_CONTROL 0x314 -+#define mmMCIF_WRITE_COMBINE_CONTROL 0x315 -+#define mmMCIF_TEST_DEBUG_INDEX 0x316 -+#define mmMCIF_TEST_DEBUG_DATA 0x317 -+#define ixIDDCCIF02_DBG_DCCIF_C 0x9 -+#define ixIDDCCIF04_DBG_DCCIF_E 0xb -+#define ixIDDCCIF05_DBG_DCCIF_F 0xc -+#define mmMCIF_VMID 0x318 -+#define mmMCIF_MEM_CONTROL 0x319 -+#define mmCC_DC_PIPE_DIS 0x177f -+#define mmMC_DC_INTERFACE_NACK_STATUS 0x31c -+#define mmDC_RBBMIF_RDWR_CNTL1 0x31a -+#define mmDC_RBBMIF_RDWR_CNTL2 0x31d -+#define mmDC_RBBMIF_RDWR_CNTL3 0x311 -+#define mmDCI_MEM_PWR_STATE 0x31b -+#define mmDCI_MEM_PWR_STATE2 0x322 -+#define mmDCI_CLK_CNTL 0x31e -+#define mmDCCG_VPCLK_CNTL 0x31f -+#define mmDCI_MEM_PWR_CNTL 0x326 -+#define mmDC_XDMA_INTERFACE_CNTL 0x327 -+#define mmDCI_TEST_DEBUG_INDEX 0x320 -+#define mmDCI_TEST_DEBUG_DATA 0x321 -+#define mmDCI_DEBUG_CONFIG 0x323 -+#define mmPIPE0_DMIF_BUFFER_CONTROL 0x328 -+#define mmPIPE1_DMIF_BUFFER_CONTROL 0x330 -+#define mmPIPE2_DMIF_BUFFER_CONTROL 0x338 -+#define mmPIPE3_DMIF_BUFFER_CONTROL 0x340 -+#define mmPIPE4_DMIF_BUFFER_CONTROL 0x348 -+#define mmPIPE5_DMIF_BUFFER_CONTROL 0x350 -+#define mmMCIF_BUFMGR_SW_CONTROL 0x358 -+#define mmMCIF_BUFMGR_STATUS 0x35a -+#define mmMCIF_BUF_PITCH 0x35b -+#define mmMCIF_BUF_1_ADDR_Y_LOW 0x35c -+#define mmMCIF_BUF_2_ADDR_Y_LOW 0x360 -+#define mmMCIF_BUF_3_ADDR_Y_LOW 0x364 -+#define mmMCIF_BUF_4_ADDR_Y_LOW 0x368 -+#define mmMCIF_BUF_1_ADDR_UP 0x35d -+#define mmMCIF_BUF_2_ADDR_UP 0x361 -+#define mmMCIF_BUF_3_ADDR_UP 0x365 -+#define mmMCIF_BUF_4_ADDR_UP 0x369 -+#define mmMCIF_BUF_1_ADDR_C_LOW 0x35e -+#define mmMCIF_BUF_2_ADDR_C_LOW 0x362 -+#define mmMCIF_BUF_3_ADDR_C_LOW 0x366 -+#define mmMCIF_BUF_4_ADDR_C_LOW 0x36a -+#define mmMCIF_BUF_1_STATUS 0x35f -+#define mmMCIF_BUF_2_STATUS 0x363 -+#define mmMCIF_BUF_3_STATUS 0x367 -+#define mmMCIF_BUF_4_STATUS 0x36b -+#define mmMCIF_SI_ARBITRATION_CONTROL 0x36c -+#define mmMCIF_URGENCY_WATERMARK 0x36d -+#define mmDC_GENERICA 0x1900 -+#define mmDC_GENERICB 0x1901 -+#define mmDC_PAD_EXTERN_SIG 0x1902 -+#define mmDC_REF_CLK_CNTL 0x1903 -+#define mmDC_GPIO_DEBUG 0x1904 -+#define mmDCO_MEM_POWER_STATE 0x1906 -+#define mmDCO_MEM_POWER_STATE_2 0x193a -+#define mmDCO_LIGHT_SLEEP_DIS 0x1907 -+#define mmUNIPHY_IMPCAL_LINKA 0x1908 -+#define mmUNIPHY_IMPCAL_LINKB 0x1909 -+#define mmUNIPHY_IMPCAL_PERIOD 0x190a -+#define mmAUXP_IMPCAL 0x190b -+#define mmAUXN_IMPCAL 0x190c -+#define mmDCIO_IMPCAL_CNTL_AB 0x190d -+#define mmUNIPHY_IMPCAL_PSW_AB 0x190e -+#define mmUNIPHY_IMPCAL_LINKC 0x190f -+#define mmUNIPHY_IMPCAL_LINKD 0x1910 -+#define mmDCIO_IMPCAL_CNTL_CD 0x1911 -+#define mmUNIPHY_IMPCAL_PSW_CD 0x1912 -+#define mmUNIPHY_IMPCAL_LINKE 0x1913 -+#define mmUNIPHY_IMPCAL_LINKF 0x1914 -+#define mmDCIO_IMPCAL_CNTL_EF 0x1915 -+#define mmUNIPHY_IMPCAL_PSW_EF 0x1916 -+#define mmDC_PINSTRAPS 0x1917 -+#define mmDC_DVODATA_CONFIG 0x1905 -+#define mmLVTMA_PWRSEQ_CNTL 0x1919 -+#define mmLVTMA_PWRSEQ_STATE 0x191a -+#define mmLVTMA_PWRSEQ_REF_DIV 0x191b -+#define mmLVTMA_PWRSEQ_DELAY1 0x191c -+#define mmLVTMA_PWRSEQ_DELAY2 0x191d -+#define mmBL_PWM_CNTL 0x191e -+#define mmBL_PWM_CNTL2 0x191f -+#define mmBL_PWM_PERIOD_CNTL 0x1920 -+#define mmBL_PWM_GRP1_REG_LOCK 0x1921 -+#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 -+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 -+#define mmDCIO_GSL0_CNTL 0x1924 -+#define mmDCIO_GSL1_CNTL 0x1925 -+#define mmDCIO_GSL2_CNTL 0x1926 -+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 -+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 -+#define mmDC_GPU_TIMER_READ 0x1929 -+#define mmDC_GPU_TIMER_READ_CNTL 0x192a -+#define mmDCO_CLK_CNTL 0x192b -+#define mmDCO_CLK_RAMP_CNTL 0x192c -+#define mmDCIO_DEBUG 0x192e -+#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937 -+#define mmDCIO_TEST_DEBUG_INDEX 0x192f -+#define mmDCIO_TEST_DEBUG_DATA 0x1930 -+#define ixDCIO_DEBUG1 0x1 -+#define ixDCIO_DEBUG2 0x2 -+#define ixDCIO_DEBUG3 0x3 -+#define ixDCIO_DEBUG4 0x4 -+#define ixDCIO_DEBUG5 0x5 -+#define ixDCIO_DEBUG6 0x6 -+#define ixDCIO_DEBUG7 0x7 -+#define ixDCIO_DEBUG8 0x8 -+#define ixDCIO_DEBUG9 0x9 -+#define ixDCIO_DEBUGA 0xa -+#define ixDCIO_DEBUGB 0xb -+#define ixDCIO_DEBUGC 0xc -+#define ixDCIO_DEBUGD 0xd -+#define ixDCIO_DEBUGE 0xe -+#define ixDCIO_DEBUGF 0xf -+#define ixDCIO_DEBUG10 0x10 -+#define ixDCIO_DEBUG11 0x11 -+#define ixDCIO_DEBUG12 0x12 -+#define ixDCIO_DEBUG13 0x13 -+#define ixDCIO_DEBUG14 0x14 -+#define ixDCIO_DEBUG15 0x15 -+#define ixDCIO_DEBUG_ID 0x0 -+#define mmDC_GPIO_GENERIC_MASK 0x1944 -+#define mmDC_GPIO_GENERIC_A 0x1945 -+#define mmDC_GPIO_GENERIC_EN 0x1946 -+#define mmDC_GPIO_GENERIC_Y 0x1947 -+#define mmDC_GPIO_DVODATA_MASK 0x1948 -+#define mmDC_GPIO_DVODATA_A 0x1949 -+#define mmDC_GPIO_DVODATA_EN 0x194a -+#define mmDC_GPIO_DVODATA_Y 0x194b -+#define mmDC_GPIO_DDC1_MASK 0x194c -+#define mmDC_GPIO_DDC1_A 0x194d -+#define mmDC_GPIO_DDC1_EN 0x194e -+#define mmDC_GPIO_DDC1_Y 0x194f -+#define mmDC_GPIO_DDC2_MASK 0x1950 -+#define mmDC_GPIO_DDC2_A 0x1951 -+#define mmDC_GPIO_DDC2_EN 0x1952 -+#define mmDC_GPIO_DDC2_Y 0x1953 -+#define mmDC_GPIO_DDC3_MASK 0x1954 -+#define mmDC_GPIO_DDC3_A 0x1955 -+#define mmDC_GPIO_DDC3_EN 0x1956 -+#define mmDC_GPIO_DDC3_Y 0x1957 -+#define mmDC_GPIO_DDC4_MASK 0x1958 -+#define mmDC_GPIO_DDC4_A 0x1959 -+#define mmDC_GPIO_DDC4_EN 0x195a -+#define mmDC_GPIO_DDC4_Y 0x195b -+#define mmDC_GPIO_DDC5_MASK 0x195c -+#define mmDC_GPIO_DDC5_A 0x195d -+#define mmDC_GPIO_DDC5_EN 0x195e -+#define mmDC_GPIO_DDC5_Y 0x195f -+#define mmDC_GPIO_DDC6_MASK 0x1960 -+#define mmDC_GPIO_DDC6_A 0x1961 -+#define mmDC_GPIO_DDC6_EN 0x1962 -+#define mmDC_GPIO_DDC6_Y 0x1963 -+#define mmDC_GPIO_DDCVGA_MASK 0x1970 -+#define mmDC_GPIO_DDCVGA_A 0x1971 -+#define mmDC_GPIO_DDCVGA_EN 0x1972 -+#define mmDC_GPIO_DDCVGA_Y 0x1973 -+#define mmDC_GPIO_SYNCA_MASK 0x1964 -+#define mmDC_GPIO_SYNCA_A 0x1965 -+#define mmDC_GPIO_SYNCA_EN 0x1966 -+#define mmDC_GPIO_SYNCA_Y 0x1967 -+#define mmDC_GPIO_GENLK_MASK 0x1968 -+#define mmDC_GPIO_GENLK_A 0x1969 -+#define mmDC_GPIO_GENLK_EN 0x196a -+#define mmDC_GPIO_GENLK_Y 0x196b -+#define mmDC_GPIO_HPD_MASK 0x196c -+#define mmDC_GPIO_HPD_A 0x196d -+#define mmDC_GPIO_HPD_EN 0x196e -+#define mmDC_GPIO_HPD_Y 0x196f -+#define mmDC_GPIO_PWRSEQ_MASK 0x1940 -+#define mmDC_GPIO_PWRSEQ_A 0x1941 -+#define mmDC_GPIO_PWRSEQ_EN 0x1942 -+#define mmDC_GPIO_PWRSEQ_Y 0x1943 -+#define mmDC_GPIO_PAD_STRENGTH_1 0x1978 -+#define mmDC_GPIO_PAD_STRENGTH_2 0x1979 -+#define mmPHY_AUX_CNTL 0x197f -+#define mmDC_GPIO_I2CPAD_A 0x1975 -+#define mmDC_GPIO_I2CPAD_EN 0x1976 -+#define mmDC_GPIO_I2CPAD_Y 0x1977 -+#define mmDC_GPIO_I2CPAD_STRENGTH 0x197a -+#define mmDVO_STRENGTH_CONTROL 0x197b -+#define mmDVO_VREF_CONTROL 0x197c -+#define mmDVO_SKEW_ADJUST 0x197d -+#define mmUNIPHYAB_TPG_CONTROL 0x1931 -+#define mmUNIPHYAB_TPG_SEED 0x1932 -+#define mmUNIPHYCD_TPG_CONTROL 0x1933 -+#define mmUNIPHYCD_TPG_SEED 0x1934 -+#define mmUNIPHYEF_TPG_CONTROL 0x1935 -+#define mmUNIPHYEF_TPG_SEED 0x1936 -+#define mmUNIPHYGH_TPG_CONTROL 0x1938 -+#define mmUNIPHYGH_TPG_SEED 0x1939 -+#define mmDC_GPIO_I2S_SPDIF_MASK 0x193c -+#define mmDC_GPIO_I2S_SPDIF_A 0x193d -+#define mmDC_GPIO_I2S_SPDIF_EN 0x193e -+#define mmDC_GPIO_I2S_SPDIF_Y 0x193f -+#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b -+#define mmDAC_MACRO_CNTL_RESERVED0 0x19fc -+#define mmDAC_MACRO_CNTL_RESERVED1 0x19fd -+#define mmDAC_MACRO_CNTL_RESERVED2 0x19fe -+#define mmDAC_MACRO_CNTL_RESERVED3 0x19ff -+#define mmUNIPHY_TX_CONTROL1 0x1980 -+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 -+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 -+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0 -+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0 -+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0 -+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0 -+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0 -+#define mmUNIPHY_TX_CONTROL2 0x1981 -+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 -+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 -+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1 -+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1 -+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1 -+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1 -+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1 -+#define mmUNIPHY_TX_CONTROL3 0x1982 -+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 -+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 -+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2 -+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2 -+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2 -+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2 -+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2 -+#define mmUNIPHY_TX_CONTROL4 0x1983 -+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 -+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 -+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3 -+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3 -+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3 -+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3 -+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3 -+#define mmUNIPHY_POWER_CONTROL 0x1984 -+#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 -+#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 -+#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4 -+#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4 -+#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4 -+#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4 -+#define mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4 -+#define mmUNIPHY_PLL_FBDIV 0x1985 -+#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 -+#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 -+#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5 -+#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5 -+#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5 -+#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5 -+#define mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5 -+#define mmUNIPHY_PLL_CONTROL1 0x1986 -+#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 -+#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 -+#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6 -+#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6 -+#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6 -+#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6 -+#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6 -+#define mmUNIPHY_PLL_CONTROL2 0x1987 -+#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 -+#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 -+#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7 -+#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7 -+#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7 -+#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7 -+#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7 -+#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 -+#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 -+#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 -+#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8 -+#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8 -+#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8 -+#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8 -+#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8 -+#define mmUNIPHY_PLL_SS_CNTL 0x1989 -+#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 -+#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 -+#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9 -+#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9 -+#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9 -+#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9 -+#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9 -+#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198a -+#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a -+#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a -+#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa -+#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba -+#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca -+#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da -+#define mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa -+#define mmUNIPHY_REG_TEST_OUTPUT 0x198b -+#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b -+#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b -+#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab -+#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb -+#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb -+#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db -+#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb -+#define mmUNIPHY_ANG_BIST_CNTL 0x198c -+#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c -+#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c -+#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac -+#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc -+#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc -+#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc -+#define mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc -+#define mmUNIPHY_LINK_CNTL 0x198d -+#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d -+#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d -+#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad -+#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd -+#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd -+#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd -+#define mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd -+#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e -+#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e -+#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e -+#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae -+#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be -+#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce -+#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de -+#define mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe -+#define mmUNIPHY_REG_TEST_OUTPUT2 0x198f -+#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f -+#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f -+#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af -+#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf -+#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf -+#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df -+#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff -+#define mmGRPH_ENABLE 0x1a00 -+#define mmDCP0_GRPH_ENABLE 0x1a00 -+#define mmDCP1_GRPH_ENABLE 0x1d00 -+#define mmDCP2_GRPH_ENABLE 0x4000 -+#define mmDCP3_GRPH_ENABLE 0x4300 -+#define mmDCP4_GRPH_ENABLE 0x4600 -+#define mmDCP5_GRPH_ENABLE 0x4900 -+#define mmGRPH_CONTROL 0x1a01 -+#define mmDCP0_GRPH_CONTROL 0x1a01 -+#define mmDCP1_GRPH_CONTROL 0x1d01 -+#define mmDCP2_GRPH_CONTROL 0x4001 -+#define mmDCP3_GRPH_CONTROL 0x4301 -+#define mmDCP4_GRPH_CONTROL 0x4601 -+#define mmDCP5_GRPH_CONTROL 0x4901 -+#define mmGRPH_LUT_10BIT_BYPASS 0x1a02 -+#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 -+#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02 -+#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 -+#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 -+#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 -+#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 -+#define mmGRPH_SWAP_CNTL 0x1a03 -+#define mmDCP0_GRPH_SWAP_CNTL 0x1a03 -+#define mmDCP1_GRPH_SWAP_CNTL 0x1d03 -+#define mmDCP2_GRPH_SWAP_CNTL 0x4003 -+#define mmDCP3_GRPH_SWAP_CNTL 0x4303 -+#define mmDCP4_GRPH_SWAP_CNTL 0x4603 -+#define mmDCP5_GRPH_SWAP_CNTL 0x4903 -+#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 -+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04 -+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 -+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 -+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 -+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 -+#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 -+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05 -+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 -+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 -+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 -+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 -+#define mmGRPH_PITCH 0x1a06 -+#define mmDCP0_GRPH_PITCH 0x1a06 -+#define mmDCP1_GRPH_PITCH 0x1d06 -+#define mmDCP2_GRPH_PITCH 0x4006 -+#define mmDCP3_GRPH_PITCH 0x4306 -+#define mmDCP4_GRPH_PITCH 0x4606 -+#define mmDCP5_GRPH_PITCH 0x4906 -+#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 -+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07 -+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 -+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 -+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 -+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 -+#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 -+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08 -+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 -+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 -+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 -+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 -+#define mmGRPH_SURFACE_OFFSET_X 0x1a09 -+#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 -+#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09 -+#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 -+#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 -+#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 -+#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 -+#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a -+#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a -+#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a -+#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a -+#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a -+#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a -+#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a -+#define mmGRPH_X_START 0x1a0b -+#define mmDCP0_GRPH_X_START 0x1a0b -+#define mmDCP1_GRPH_X_START 0x1d0b -+#define mmDCP2_GRPH_X_START 0x400b -+#define mmDCP3_GRPH_X_START 0x430b -+#define mmDCP4_GRPH_X_START 0x460b -+#define mmDCP5_GRPH_X_START 0x490b -+#define mmGRPH_Y_START 0x1a0c -+#define mmDCP0_GRPH_Y_START 0x1a0c -+#define mmDCP1_GRPH_Y_START 0x1d0c -+#define mmDCP2_GRPH_Y_START 0x400c -+#define mmDCP3_GRPH_Y_START 0x430c -+#define mmDCP4_GRPH_Y_START 0x460c -+#define mmDCP5_GRPH_Y_START 0x490c -+#define mmGRPH_X_END 0x1a0d -+#define mmDCP0_GRPH_X_END 0x1a0d -+#define mmDCP1_GRPH_X_END 0x1d0d -+#define mmDCP2_GRPH_X_END 0x400d -+#define mmDCP3_GRPH_X_END 0x430d -+#define mmDCP4_GRPH_X_END 0x460d -+#define mmDCP5_GRPH_X_END 0x490d -+#define mmGRPH_Y_END 0x1a0e -+#define mmDCP0_GRPH_Y_END 0x1a0e -+#define mmDCP1_GRPH_Y_END 0x1d0e -+#define mmDCP2_GRPH_Y_END 0x400e -+#define mmDCP3_GRPH_Y_END 0x430e -+#define mmDCP4_GRPH_Y_END 0x460e -+#define mmDCP5_GRPH_Y_END 0x490e -+#define mmINPUT_GAMMA_CONTROL 0x1a10 -+#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 -+#define mmDCP1_INPUT_GAMMA_CONTROL 0x1d10 -+#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 -+#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 -+#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 -+#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 -+#define mmGRPH_UPDATE 0x1a11 -+#define mmDCP0_GRPH_UPDATE 0x1a11 -+#define mmDCP1_GRPH_UPDATE 0x1d11 -+#define mmDCP2_GRPH_UPDATE 0x4011 -+#define mmDCP3_GRPH_UPDATE 0x4311 -+#define mmDCP4_GRPH_UPDATE 0x4611 -+#define mmDCP5_GRPH_UPDATE 0x4911 -+#define mmGRPH_FLIP_CONTROL 0x1a12 -+#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 -+#define mmDCP1_GRPH_FLIP_CONTROL 0x1d12 -+#define mmDCP2_GRPH_FLIP_CONTROL 0x4012 -+#define mmDCP3_GRPH_FLIP_CONTROL 0x4312 -+#define mmDCP4_GRPH_FLIP_CONTROL 0x4612 -+#define mmDCP5_GRPH_FLIP_CONTROL 0x4912 -+#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 -+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 -+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13 -+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 -+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 -+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 -+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 -+#define mmGRPH_DFQ_CONTROL 0x1a14 -+#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 -+#define mmDCP1_GRPH_DFQ_CONTROL 0x1d14 -+#define mmDCP2_GRPH_DFQ_CONTROL 0x4014 -+#define mmDCP3_GRPH_DFQ_CONTROL 0x4314 -+#define mmDCP4_GRPH_DFQ_CONTROL 0x4614 -+#define mmDCP5_GRPH_DFQ_CONTROL 0x4914 -+#define mmGRPH_DFQ_STATUS 0x1a15 -+#define mmDCP0_GRPH_DFQ_STATUS 0x1a15 -+#define mmDCP1_GRPH_DFQ_STATUS 0x1d15 -+#define mmDCP2_GRPH_DFQ_STATUS 0x4015 -+#define mmDCP3_GRPH_DFQ_STATUS 0x4315 -+#define mmDCP4_GRPH_DFQ_STATUS 0x4615 -+#define mmDCP5_GRPH_DFQ_STATUS 0x4915 -+#define mmGRPH_INTERRUPT_STATUS 0x1a16 -+#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 -+#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16 -+#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 -+#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 -+#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 -+#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 -+#define mmGRPH_INTERRUPT_CONTROL 0x1a17 -+#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 -+#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17 -+#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 -+#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 -+#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 -+#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 -+#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 -+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18 -+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 -+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 -+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 -+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 -+#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 -+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19 -+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 -+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 -+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 -+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 -+#define mmGRPH_COMPRESS_PITCH 0x1a1a -+#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a -+#define mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a -+#define mmDCP2_GRPH_COMPRESS_PITCH 0x401a -+#define mmDCP3_GRPH_COMPRESS_PITCH 0x431a -+#define mmDCP4_GRPH_COMPRESS_PITCH 0x461a -+#define mmDCP5_GRPH_COMPRESS_PITCH 0x491a -+#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b -+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b -+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b -+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b -+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b -+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b -+#define mmOVL_ENABLE 0x1a1c -+#define mmDCP0_OVL_ENABLE 0x1a1c -+#define mmDCP1_OVL_ENABLE 0x1d1c -+#define mmDCP2_OVL_ENABLE 0x401c -+#define mmDCP3_OVL_ENABLE 0x431c -+#define mmDCP4_OVL_ENABLE 0x461c -+#define mmDCP5_OVL_ENABLE 0x491c -+#define mmOVL_CONTROL1 0x1a1d -+#define mmDCP0_OVL_CONTROL1 0x1a1d -+#define mmDCP1_OVL_CONTROL1 0x1d1d -+#define mmDCP2_OVL_CONTROL1 0x401d -+#define mmDCP3_OVL_CONTROL1 0x431d -+#define mmDCP4_OVL_CONTROL1 0x461d -+#define mmDCP5_OVL_CONTROL1 0x491d -+#define mmOVL_CONTROL2 0x1a1e -+#define mmDCP0_OVL_CONTROL2 0x1a1e -+#define mmDCP1_OVL_CONTROL2 0x1d1e -+#define mmDCP2_OVL_CONTROL2 0x401e -+#define mmDCP3_OVL_CONTROL2 0x431e -+#define mmDCP4_OVL_CONTROL2 0x461e -+#define mmDCP5_OVL_CONTROL2 0x491e -+#define mmOVL_SWAP_CNTL 0x1a1f -+#define mmDCP0_OVL_SWAP_CNTL 0x1a1f -+#define mmDCP1_OVL_SWAP_CNTL 0x1d1f -+#define mmDCP2_OVL_SWAP_CNTL 0x401f -+#define mmDCP3_OVL_SWAP_CNTL 0x431f -+#define mmDCP4_OVL_SWAP_CNTL 0x461f -+#define mmDCP5_OVL_SWAP_CNTL 0x491f -+#define mmOVL_SURFACE_ADDRESS 0x1a20 -+#define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 -+#define mmDCP1_OVL_SURFACE_ADDRESS 0x1d20 -+#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 -+#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 -+#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 -+#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 -+#define mmOVL_PITCH 0x1a21 -+#define mmDCP0_OVL_PITCH 0x1a21 -+#define mmDCP1_OVL_PITCH 0x1d21 -+#define mmDCP2_OVL_PITCH 0x4021 -+#define mmDCP3_OVL_PITCH 0x4321 -+#define mmDCP4_OVL_PITCH 0x4621 -+#define mmDCP5_OVL_PITCH 0x4921 -+#define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 -+#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 -+#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22 -+#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 -+#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 -+#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 -+#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 -+#define mmOVL_SURFACE_OFFSET_X 0x1a23 -+#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 -+#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23 -+#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 -+#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 -+#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 -+#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 -+#define mmOVL_SURFACE_OFFSET_Y 0x1a24 -+#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 -+#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24 -+#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 -+#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 -+#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 -+#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 -+#define mmOVL_START 0x1a25 -+#define mmDCP0_OVL_START 0x1a25 -+#define mmDCP1_OVL_START 0x1d25 -+#define mmDCP2_OVL_START 0x4025 -+#define mmDCP3_OVL_START 0x4325 -+#define mmDCP4_OVL_START 0x4625 -+#define mmDCP5_OVL_START 0x4925 -+#define mmOVL_END 0x1a26 -+#define mmDCP0_OVL_END 0x1a26 -+#define mmDCP1_OVL_END 0x1d26 -+#define mmDCP2_OVL_END 0x4026 -+#define mmDCP3_OVL_END 0x4326 -+#define mmDCP4_OVL_END 0x4626 -+#define mmDCP5_OVL_END 0x4926 -+#define mmOVL_UPDATE 0x1a27 -+#define mmDCP0_OVL_UPDATE 0x1a27 -+#define mmDCP1_OVL_UPDATE 0x1d27 -+#define mmDCP2_OVL_UPDATE 0x4027 -+#define mmDCP3_OVL_UPDATE 0x4327 -+#define mmDCP4_OVL_UPDATE 0x4627 -+#define mmDCP5_OVL_UPDATE 0x4927 -+#define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 -+#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 -+#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28 -+#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 -+#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 -+#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 -+#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 -+#define mmOVL_DFQ_CONTROL 0x1a29 -+#define mmDCP0_OVL_DFQ_CONTROL 0x1a29 -+#define mmDCP1_OVL_DFQ_CONTROL 0x1d29 -+#define mmDCP2_OVL_DFQ_CONTROL 0x4029 -+#define mmDCP3_OVL_DFQ_CONTROL 0x4329 -+#define mmDCP4_OVL_DFQ_CONTROL 0x4629 -+#define mmDCP5_OVL_DFQ_CONTROL 0x4929 -+#define mmOVL_DFQ_STATUS 0x1a2a -+#define mmDCP0_OVL_DFQ_STATUS 0x1a2a -+#define mmDCP1_OVL_DFQ_STATUS 0x1d2a -+#define mmDCP2_OVL_DFQ_STATUS 0x402a -+#define mmDCP3_OVL_DFQ_STATUS 0x432a -+#define mmDCP4_OVL_DFQ_STATUS 0x462a -+#define mmDCP5_OVL_DFQ_STATUS 0x492a -+#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b -+#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b -+#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b -+#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b -+#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b -+#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b -+#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b -+#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c -+#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c -+#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c -+#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c -+#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c -+#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c -+#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c -+#define mmPRESCALE_GRPH_CONTROL 0x1a2d -+#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d -+#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d -+#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402d -+#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432d -+#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462d -+#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492d -+#define mmPRESCALE_VALUES_GRPH_R 0x1a2e -+#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e -+#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e -+#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e -+#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e -+#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e -+#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e -+#define mmPRESCALE_VALUES_GRPH_G 0x1a2f -+#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f -+#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f -+#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f -+#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f -+#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f -+#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f -+#define mmPRESCALE_VALUES_GRPH_B 0x1a30 -+#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 -+#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30 -+#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 -+#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 -+#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 -+#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 -+#define mmPRESCALE_OVL_CONTROL 0x1a31 -+#define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 -+#define mmDCP1_PRESCALE_OVL_CONTROL 0x1d31 -+#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 -+#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 -+#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 -+#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 -+#define mmPRESCALE_VALUES_OVL_CB 0x1a32 -+#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 -+#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32 -+#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 -+#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 -+#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 -+#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 -+#define mmPRESCALE_VALUES_OVL_Y 0x1a33 -+#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 -+#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33 -+#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 -+#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 -+#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 -+#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 -+#define mmPRESCALE_VALUES_OVL_CR 0x1a34 -+#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 -+#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34 -+#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 -+#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 -+#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 -+#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 -+#define mmINPUT_CSC_CONTROL 0x1a35 -+#define mmDCP0_INPUT_CSC_CONTROL 0x1a35 -+#define mmDCP1_INPUT_CSC_CONTROL 0x1d35 -+#define mmDCP2_INPUT_CSC_CONTROL 0x4035 -+#define mmDCP3_INPUT_CSC_CONTROL 0x4335 -+#define mmDCP4_INPUT_CSC_CONTROL 0x4635 -+#define mmDCP5_INPUT_CSC_CONTROL 0x4935 -+#define mmINPUT_CSC_C11_C12 0x1a36 -+#define mmDCP0_INPUT_CSC_C11_C12 0x1a36 -+#define mmDCP1_INPUT_CSC_C11_C12 0x1d36 -+#define mmDCP2_INPUT_CSC_C11_C12 0x4036 -+#define mmDCP3_INPUT_CSC_C11_C12 0x4336 -+#define mmDCP4_INPUT_CSC_C11_C12 0x4636 -+#define mmDCP5_INPUT_CSC_C11_C12 0x4936 -+#define mmINPUT_CSC_C13_C14 0x1a37 -+#define mmDCP0_INPUT_CSC_C13_C14 0x1a37 -+#define mmDCP1_INPUT_CSC_C13_C14 0x1d37 -+#define mmDCP2_INPUT_CSC_C13_C14 0x4037 -+#define mmDCP3_INPUT_CSC_C13_C14 0x4337 -+#define mmDCP4_INPUT_CSC_C13_C14 0x4637 -+#define mmDCP5_INPUT_CSC_C13_C14 0x4937 -+#define mmINPUT_CSC_C21_C22 0x1a38 -+#define mmDCP0_INPUT_CSC_C21_C22 0x1a38 -+#define mmDCP1_INPUT_CSC_C21_C22 0x1d38 -+#define mmDCP2_INPUT_CSC_C21_C22 0x4038 -+#define mmDCP3_INPUT_CSC_C21_C22 0x4338 -+#define mmDCP4_INPUT_CSC_C21_C22 0x4638 -+#define mmDCP5_INPUT_CSC_C21_C22 0x4938 -+#define mmINPUT_CSC_C23_C24 0x1a39 -+#define mmDCP0_INPUT_CSC_C23_C24 0x1a39 -+#define mmDCP1_INPUT_CSC_C23_C24 0x1d39 -+#define mmDCP2_INPUT_CSC_C23_C24 0x4039 -+#define mmDCP3_INPUT_CSC_C23_C24 0x4339 -+#define mmDCP4_INPUT_CSC_C23_C24 0x4639 -+#define mmDCP5_INPUT_CSC_C23_C24 0x4939 -+#define mmINPUT_CSC_C31_C32 0x1a3a -+#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a -+#define mmDCP1_INPUT_CSC_C31_C32 0x1d3a -+#define mmDCP2_INPUT_CSC_C31_C32 0x403a -+#define mmDCP3_INPUT_CSC_C31_C32 0x433a -+#define mmDCP4_INPUT_CSC_C31_C32 0x463a -+#define mmDCP5_INPUT_CSC_C31_C32 0x493a -+#define mmINPUT_CSC_C33_C34 0x1a3b -+#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b -+#define mmDCP1_INPUT_CSC_C33_C34 0x1d3b -+#define mmDCP2_INPUT_CSC_C33_C34 0x403b -+#define mmDCP3_INPUT_CSC_C33_C34 0x433b -+#define mmDCP4_INPUT_CSC_C33_C34 0x463b -+#define mmDCP5_INPUT_CSC_C33_C34 0x493b -+#define mmOUTPUT_CSC_CONTROL 0x1a3c -+#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c -+#define mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c -+#define mmDCP2_OUTPUT_CSC_CONTROL 0x403c -+#define mmDCP3_OUTPUT_CSC_CONTROL 0x433c -+#define mmDCP4_OUTPUT_CSC_CONTROL 0x463c -+#define mmDCP5_OUTPUT_CSC_CONTROL 0x493c -+#define mmOUTPUT_CSC_C11_C12 0x1a3d -+#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d -+#define mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d -+#define mmDCP2_OUTPUT_CSC_C11_C12 0x403d -+#define mmDCP3_OUTPUT_CSC_C11_C12 0x433d -+#define mmDCP4_OUTPUT_CSC_C11_C12 0x463d -+#define mmDCP5_OUTPUT_CSC_C11_C12 0x493d -+#define mmOUTPUT_CSC_C13_C14 0x1a3e -+#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e -+#define mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e -+#define mmDCP2_OUTPUT_CSC_C13_C14 0x403e -+#define mmDCP3_OUTPUT_CSC_C13_C14 0x433e -+#define mmDCP4_OUTPUT_CSC_C13_C14 0x463e -+#define mmDCP5_OUTPUT_CSC_C13_C14 0x493e -+#define mmOUTPUT_CSC_C21_C22 0x1a3f -+#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f -+#define mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f -+#define mmDCP2_OUTPUT_CSC_C21_C22 0x403f -+#define mmDCP3_OUTPUT_CSC_C21_C22 0x433f -+#define mmDCP4_OUTPUT_CSC_C21_C22 0x463f -+#define mmDCP5_OUTPUT_CSC_C21_C22 0x493f -+#define mmOUTPUT_CSC_C23_C24 0x1a40 -+#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 -+#define mmDCP1_OUTPUT_CSC_C23_C24 0x1d40 -+#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 -+#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 -+#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 -+#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 -+#define mmOUTPUT_CSC_C31_C32 0x1a41 -+#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 -+#define mmDCP1_OUTPUT_CSC_C31_C32 0x1d41 -+#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 -+#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 -+#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 -+#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 -+#define mmOUTPUT_CSC_C33_C34 0x1a42 -+#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 -+#define mmDCP1_OUTPUT_CSC_C33_C34 0x1d42 -+#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 -+#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 -+#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 -+#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 -+#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 -+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 -+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43 -+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 -+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 -+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 -+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 -+#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 -+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 -+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44 -+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 -+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 -+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 -+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 -+#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 -+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 -+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45 -+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 -+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 -+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 -+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 -+#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 -+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 -+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46 -+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 -+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 -+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 -+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 -+#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 -+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 -+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47 -+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 -+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 -+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 -+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 -+#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 -+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 -+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48 -+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 -+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 -+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 -+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 -+#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 -+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 -+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49 -+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 -+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 -+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 -+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 -+#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a -+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a -+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a -+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a -+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a -+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a -+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a -+#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b -+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b -+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b -+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b -+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b -+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b -+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b -+#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c -+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c -+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c -+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c -+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c -+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c -+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c -+#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d -+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d -+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d -+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d -+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d -+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d -+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d -+#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e -+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e -+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e -+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e -+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e -+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e -+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e -+#define mmDENORM_CONTROL 0x1a50 -+#define mmDCP0_DENORM_CONTROL 0x1a50 -+#define mmDCP1_DENORM_CONTROL 0x1d50 -+#define mmDCP2_DENORM_CONTROL 0x4050 -+#define mmDCP3_DENORM_CONTROL 0x4350 -+#define mmDCP4_DENORM_CONTROL 0x4650 -+#define mmDCP5_DENORM_CONTROL 0x4950 -+#define mmOUT_ROUND_CONTROL 0x1a51 -+#define mmDCP0_OUT_ROUND_CONTROL 0x1a51 -+#define mmDCP1_OUT_ROUND_CONTROL 0x1d51 -+#define mmDCP2_OUT_ROUND_CONTROL 0x4051 -+#define mmDCP3_OUT_ROUND_CONTROL 0x4351 -+#define mmDCP4_OUT_ROUND_CONTROL 0x4651 -+#define mmDCP5_OUT_ROUND_CONTROL 0x4951 -+#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 -+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 -+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52 -+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052 -+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352 -+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652 -+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952 -+#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c -+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c -+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c -+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c -+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c -+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c -+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c -+#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d -+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d -+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d -+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d -+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d -+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d -+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d -+#define mmKEY_CONTROL 0x1a53 -+#define mmDCP0_KEY_CONTROL 0x1a53 -+#define mmDCP1_KEY_CONTROL 0x1d53 -+#define mmDCP2_KEY_CONTROL 0x4053 -+#define mmDCP3_KEY_CONTROL 0x4353 -+#define mmDCP4_KEY_CONTROL 0x4653 -+#define mmDCP5_KEY_CONTROL 0x4953 -+#define mmKEY_RANGE_ALPHA 0x1a54 -+#define mmDCP0_KEY_RANGE_ALPHA 0x1a54 -+#define mmDCP1_KEY_RANGE_ALPHA 0x1d54 -+#define mmDCP2_KEY_RANGE_ALPHA 0x4054 -+#define mmDCP3_KEY_RANGE_ALPHA 0x4354 -+#define mmDCP4_KEY_RANGE_ALPHA 0x4654 -+#define mmDCP5_KEY_RANGE_ALPHA 0x4954 -+#define mmKEY_RANGE_RED 0x1a55 -+#define mmDCP0_KEY_RANGE_RED 0x1a55 -+#define mmDCP1_KEY_RANGE_RED 0x1d55 -+#define mmDCP2_KEY_RANGE_RED 0x4055 -+#define mmDCP3_KEY_RANGE_RED 0x4355 -+#define mmDCP4_KEY_RANGE_RED 0x4655 -+#define mmDCP5_KEY_RANGE_RED 0x4955 -+#define mmKEY_RANGE_GREEN 0x1a56 -+#define mmDCP0_KEY_RANGE_GREEN 0x1a56 -+#define mmDCP1_KEY_RANGE_GREEN 0x1d56 -+#define mmDCP2_KEY_RANGE_GREEN 0x4056 -+#define mmDCP3_KEY_RANGE_GREEN 0x4356 -+#define mmDCP4_KEY_RANGE_GREEN 0x4656 -+#define mmDCP5_KEY_RANGE_GREEN 0x4956 -+#define mmKEY_RANGE_BLUE 0x1a57 -+#define mmDCP0_KEY_RANGE_BLUE 0x1a57 -+#define mmDCP1_KEY_RANGE_BLUE 0x1d57 -+#define mmDCP2_KEY_RANGE_BLUE 0x4057 -+#define mmDCP3_KEY_RANGE_BLUE 0x4357 -+#define mmDCP4_KEY_RANGE_BLUE 0x4657 -+#define mmDCP5_KEY_RANGE_BLUE 0x4957 -+#define mmDEGAMMA_CONTROL 0x1a58 -+#define mmDCP0_DEGAMMA_CONTROL 0x1a58 -+#define mmDCP1_DEGAMMA_CONTROL 0x1d58 -+#define mmDCP2_DEGAMMA_CONTROL 0x4058 -+#define mmDCP3_DEGAMMA_CONTROL 0x4358 -+#define mmDCP4_DEGAMMA_CONTROL 0x4658 -+#define mmDCP5_DEGAMMA_CONTROL 0x4958 -+#define mmGAMUT_REMAP_CONTROL 0x1a59 -+#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 -+#define mmDCP1_GAMUT_REMAP_CONTROL 0x1d59 -+#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 -+#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 -+#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 -+#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 -+#define mmGAMUT_REMAP_C11_C12 0x1a5a -+#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a -+#define mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a -+#define mmDCP2_GAMUT_REMAP_C11_C12 0x405a -+#define mmDCP3_GAMUT_REMAP_C11_C12 0x435a -+#define mmDCP4_GAMUT_REMAP_C11_C12 0x465a -+#define mmDCP5_GAMUT_REMAP_C11_C12 0x495a -+#define mmGAMUT_REMAP_C13_C14 0x1a5b -+#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b -+#define mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b -+#define mmDCP2_GAMUT_REMAP_C13_C14 0x405b -+#define mmDCP3_GAMUT_REMAP_C13_C14 0x435b -+#define mmDCP4_GAMUT_REMAP_C13_C14 0x465b -+#define mmDCP5_GAMUT_REMAP_C13_C14 0x495b -+#define mmGAMUT_REMAP_C21_C22 0x1a5c -+#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c -+#define mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c -+#define mmDCP2_GAMUT_REMAP_C21_C22 0x405c -+#define mmDCP3_GAMUT_REMAP_C21_C22 0x435c -+#define mmDCP4_GAMUT_REMAP_C21_C22 0x465c -+#define mmDCP5_GAMUT_REMAP_C21_C22 0x495c -+#define mmGAMUT_REMAP_C23_C24 0x1a5d -+#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d -+#define mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d -+#define mmDCP2_GAMUT_REMAP_C23_C24 0x405d -+#define mmDCP3_GAMUT_REMAP_C23_C24 0x435d -+#define mmDCP4_GAMUT_REMAP_C23_C24 0x465d -+#define mmDCP5_GAMUT_REMAP_C23_C24 0x495d -+#define mmGAMUT_REMAP_C31_C32 0x1a5e -+#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e -+#define mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e -+#define mmDCP2_GAMUT_REMAP_C31_C32 0x405e -+#define mmDCP3_GAMUT_REMAP_C31_C32 0x435e -+#define mmDCP4_GAMUT_REMAP_C31_C32 0x465e -+#define mmDCP5_GAMUT_REMAP_C31_C32 0x495e -+#define mmGAMUT_REMAP_C33_C34 0x1a5f -+#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f -+#define mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f -+#define mmDCP2_GAMUT_REMAP_C33_C34 0x405f -+#define mmDCP3_GAMUT_REMAP_C33_C34 0x435f -+#define mmDCP4_GAMUT_REMAP_C33_C34 0x465f -+#define mmDCP5_GAMUT_REMAP_C33_C34 0x495f -+#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 -+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 -+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60 -+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 -+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 -+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 -+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 -+#define mmDCP_RANDOM_SEEDS 0x1a61 -+#define mmDCP0_DCP_RANDOM_SEEDS 0x1a61 -+#define mmDCP1_DCP_RANDOM_SEEDS 0x1d61 -+#define mmDCP2_DCP_RANDOM_SEEDS 0x4061 -+#define mmDCP3_DCP_RANDOM_SEEDS 0x4361 -+#define mmDCP4_DCP_RANDOM_SEEDS 0x4661 -+#define mmDCP5_DCP_RANDOM_SEEDS 0x4961 -+#define mmDCP_FP_CONVERTED_FIELD 0x1a65 -+#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 -+#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65 -+#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 -+#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 -+#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 -+#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 -+#define mmCUR_CONTROL 0x1a66 -+#define mmDCP0_CUR_CONTROL 0x1a66 -+#define mmDCP1_CUR_CONTROL 0x1d66 -+#define mmDCP2_CUR_CONTROL 0x4066 -+#define mmDCP3_CUR_CONTROL 0x4366 -+#define mmDCP4_CUR_CONTROL 0x4666 -+#define mmDCP5_CUR_CONTROL 0x4966 -+#define mmCUR_SURFACE_ADDRESS 0x1a67 -+#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 -+#define mmDCP1_CUR_SURFACE_ADDRESS 0x1d67 -+#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 -+#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 -+#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 -+#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 -+#define mmCUR_SIZE 0x1a68 -+#define mmDCP0_CUR_SIZE 0x1a68 -+#define mmDCP1_CUR_SIZE 0x1d68 -+#define mmDCP2_CUR_SIZE 0x4068 -+#define mmDCP3_CUR_SIZE 0x4368 -+#define mmDCP4_CUR_SIZE 0x4668 -+#define mmDCP5_CUR_SIZE 0x4968 -+#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 -+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 -+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69 -+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 -+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 -+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 -+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 -+#define mmCUR_POSITION 0x1a6a -+#define mmDCP0_CUR_POSITION 0x1a6a -+#define mmDCP1_CUR_POSITION 0x1d6a -+#define mmDCP2_CUR_POSITION 0x406a -+#define mmDCP3_CUR_POSITION 0x436a -+#define mmDCP4_CUR_POSITION 0x466a -+#define mmDCP5_CUR_POSITION 0x496a -+#define mmCUR_HOT_SPOT 0x1a6b -+#define mmDCP0_CUR_HOT_SPOT 0x1a6b -+#define mmDCP1_CUR_HOT_SPOT 0x1d6b -+#define mmDCP2_CUR_HOT_SPOT 0x406b -+#define mmDCP3_CUR_HOT_SPOT 0x436b -+#define mmDCP4_CUR_HOT_SPOT 0x466b -+#define mmDCP5_CUR_HOT_SPOT 0x496b -+#define mmCUR_COLOR1 0x1a6c -+#define mmDCP0_CUR_COLOR1 0x1a6c -+#define mmDCP1_CUR_COLOR1 0x1d6c -+#define mmDCP2_CUR_COLOR1 0x406c -+#define mmDCP3_CUR_COLOR1 0x436c -+#define mmDCP4_CUR_COLOR1 0x466c -+#define mmDCP5_CUR_COLOR1 0x496c -+#define mmCUR_COLOR2 0x1a6d -+#define mmDCP0_CUR_COLOR2 0x1a6d -+#define mmDCP1_CUR_COLOR2 0x1d6d -+#define mmDCP2_CUR_COLOR2 0x406d -+#define mmDCP3_CUR_COLOR2 0x436d -+#define mmDCP4_CUR_COLOR2 0x466d -+#define mmDCP5_CUR_COLOR2 0x496d -+#define mmCUR_UPDATE 0x1a6e -+#define mmDCP0_CUR_UPDATE 0x1a6e -+#define mmDCP1_CUR_UPDATE 0x1d6e -+#define mmDCP2_CUR_UPDATE 0x406e -+#define mmDCP3_CUR_UPDATE 0x436e -+#define mmDCP4_CUR_UPDATE 0x466e -+#define mmDCP5_CUR_UPDATE 0x496e -+#define mmCUR2_CONTROL 0x1a6f -+#define mmDCP0_CUR2_CONTROL 0x1a6f -+#define mmDCP1_CUR2_CONTROL 0x1d6f -+#define mmDCP2_CUR2_CONTROL 0x406f -+#define mmDCP3_CUR2_CONTROL 0x436f -+#define mmDCP4_CUR2_CONTROL 0x466f -+#define mmDCP5_CUR2_CONTROL 0x496f -+#define mmCUR2_SURFACE_ADDRESS 0x1a70 -+#define mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70 -+#define mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70 -+#define mmDCP2_CUR2_SURFACE_ADDRESS 0x4070 -+#define mmDCP3_CUR2_SURFACE_ADDRESS 0x4370 -+#define mmDCP4_CUR2_SURFACE_ADDRESS 0x4670 -+#define mmDCP5_CUR2_SURFACE_ADDRESS 0x4970 -+#define mmCUR2_SIZE 0x1a71 -+#define mmDCP0_CUR2_SIZE 0x1a71 -+#define mmDCP1_CUR2_SIZE 0x1d71 -+#define mmDCP2_CUR2_SIZE 0x4071 -+#define mmDCP3_CUR2_SIZE 0x4371 -+#define mmDCP4_CUR2_SIZE 0x4671 -+#define mmDCP5_CUR2_SIZE 0x4971 -+#define mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72 -+#define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72 -+#define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72 -+#define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072 -+#define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372 -+#define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672 -+#define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972 -+#define mmCUR2_POSITION 0x1a73 -+#define mmDCP0_CUR2_POSITION 0x1a73 -+#define mmDCP1_CUR2_POSITION 0x1d73 -+#define mmDCP2_CUR2_POSITION 0x4073 -+#define mmDCP3_CUR2_POSITION 0x4373 -+#define mmDCP4_CUR2_POSITION 0x4673 -+#define mmDCP5_CUR2_POSITION 0x4973 -+#define mmCUR2_HOT_SPOT 0x1a74 -+#define mmDCP0_CUR2_HOT_SPOT 0x1a74 -+#define mmDCP1_CUR2_HOT_SPOT 0x1d74 -+#define mmDCP2_CUR2_HOT_SPOT 0x4074 -+#define mmDCP3_CUR2_HOT_SPOT 0x4374 -+#define mmDCP4_CUR2_HOT_SPOT 0x4674 -+#define mmDCP5_CUR2_HOT_SPOT 0x4974 -+#define mmCUR2_COLOR1 0x1a75 -+#define mmDCP0_CUR2_COLOR1 0x1a75 -+#define mmDCP1_CUR2_COLOR1 0x1d75 -+#define mmDCP2_CUR2_COLOR1 0x4075 -+#define mmDCP3_CUR2_COLOR1 0x4375 -+#define mmDCP4_CUR2_COLOR1 0x4675 -+#define mmDCP5_CUR2_COLOR1 0x4975 -+#define mmCUR2_COLOR2 0x1a76 -+#define mmDCP0_CUR2_COLOR2 0x1a76 -+#define mmDCP1_CUR2_COLOR2 0x1d76 -+#define mmDCP2_CUR2_COLOR2 0x4076 -+#define mmDCP3_CUR2_COLOR2 0x4376 -+#define mmDCP4_CUR2_COLOR2 0x4676 -+#define mmDCP5_CUR2_COLOR2 0x4976 -+#define mmCUR2_UPDATE 0x1a77 -+#define mmDCP0_CUR2_UPDATE 0x1a77 -+#define mmDCP1_CUR2_UPDATE 0x1d77 -+#define mmDCP2_CUR2_UPDATE 0x4077 -+#define mmDCP3_CUR2_UPDATE 0x4377 -+#define mmDCP4_CUR2_UPDATE 0x4677 -+#define mmDCP5_CUR2_UPDATE 0x4977 -+#define mmCUR_REQUEST_FILTER_CNTL 0x1a99 -+#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 -+#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99 -+#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 -+#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 -+#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 -+#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 -+#define mmCUR_STEREO_CONTROL 0x1a9a -+#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a -+#define mmDCP1_CUR_STEREO_CONTROL 0x1d9a -+#define mmDCP2_CUR_STEREO_CONTROL 0x409a -+#define mmDCP3_CUR_STEREO_CONTROL 0x439a -+#define mmDCP4_CUR_STEREO_CONTROL 0x469a -+#define mmDCP5_CUR_STEREO_CONTROL 0x499a -+#define mmCUR2_STEREO_CONTROL 0x1a9b -+#define mmDCP0_CUR2_STEREO_CONTROL 0x1a9b -+#define mmDCP1_CUR2_STEREO_CONTROL 0x1d9b -+#define mmDCP2_CUR2_STEREO_CONTROL 0x409b -+#define mmDCP3_CUR2_STEREO_CONTROL 0x439b -+#define mmDCP4_CUR2_STEREO_CONTROL 0x469b -+#define mmDCP5_CUR2_STEREO_CONTROL 0x499b -+#define mmDC_LUT_RW_MODE 0x1a78 -+#define mmDCP0_DC_LUT_RW_MODE 0x1a78 -+#define mmDCP1_DC_LUT_RW_MODE 0x1d78 -+#define mmDCP2_DC_LUT_RW_MODE 0x4078 -+#define mmDCP3_DC_LUT_RW_MODE 0x4378 -+#define mmDCP4_DC_LUT_RW_MODE 0x4678 -+#define mmDCP5_DC_LUT_RW_MODE 0x4978 -+#define mmDC_LUT_RW_INDEX 0x1a79 -+#define mmDCP0_DC_LUT_RW_INDEX 0x1a79 -+#define mmDCP1_DC_LUT_RW_INDEX 0x1d79 -+#define mmDCP2_DC_LUT_RW_INDEX 0x4079 -+#define mmDCP3_DC_LUT_RW_INDEX 0x4379 -+#define mmDCP4_DC_LUT_RW_INDEX 0x4679 -+#define mmDCP5_DC_LUT_RW_INDEX 0x4979 -+#define mmDC_LUT_SEQ_COLOR 0x1a7a -+#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a -+#define mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a -+#define mmDCP2_DC_LUT_SEQ_COLOR 0x407a -+#define mmDCP3_DC_LUT_SEQ_COLOR 0x437a -+#define mmDCP4_DC_LUT_SEQ_COLOR 0x467a -+#define mmDCP5_DC_LUT_SEQ_COLOR 0x497a -+#define mmDC_LUT_PWL_DATA 0x1a7b -+#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b -+#define mmDCP1_DC_LUT_PWL_DATA 0x1d7b -+#define mmDCP2_DC_LUT_PWL_DATA 0x407b -+#define mmDCP3_DC_LUT_PWL_DATA 0x437b -+#define mmDCP4_DC_LUT_PWL_DATA 0x467b -+#define mmDCP5_DC_LUT_PWL_DATA 0x497b -+#define mmDC_LUT_30_COLOR 0x1a7c -+#define mmDCP0_DC_LUT_30_COLOR 0x1a7c -+#define mmDCP1_DC_LUT_30_COLOR 0x1d7c -+#define mmDCP2_DC_LUT_30_COLOR 0x407c -+#define mmDCP3_DC_LUT_30_COLOR 0x437c -+#define mmDCP4_DC_LUT_30_COLOR 0x467c -+#define mmDCP5_DC_LUT_30_COLOR 0x497c -+#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d -+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d -+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d -+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d -+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d -+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d -+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d -+#define mmDC_LUT_WRITE_EN_MASK 0x1a7e -+#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e -+#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e -+#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e -+#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e -+#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e -+#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e -+#define mmDC_LUT_AUTOFILL 0x1a7f -+#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f -+#define mmDCP1_DC_LUT_AUTOFILL 0x1d7f -+#define mmDCP2_DC_LUT_AUTOFILL 0x407f -+#define mmDCP3_DC_LUT_AUTOFILL 0x437f -+#define mmDCP4_DC_LUT_AUTOFILL 0x467f -+#define mmDCP5_DC_LUT_AUTOFILL 0x497f -+#define mmDC_LUT_CONTROL 0x1a80 -+#define mmDCP0_DC_LUT_CONTROL 0x1a80 -+#define mmDCP1_DC_LUT_CONTROL 0x1d80 -+#define mmDCP2_DC_LUT_CONTROL 0x4080 -+#define mmDCP3_DC_LUT_CONTROL 0x4380 -+#define mmDCP4_DC_LUT_CONTROL 0x4680 -+#define mmDCP5_DC_LUT_CONTROL 0x4980 -+#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 -+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 -+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81 -+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 -+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 -+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 -+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 -+#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 -+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 -+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82 -+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 -+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 -+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 -+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 -+#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 -+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 -+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83 -+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 -+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 -+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 -+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 -+#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 -+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 -+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84 -+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 -+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 -+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 -+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 -+#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 -+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 -+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85 -+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 -+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 -+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 -+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 -+#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 -+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 -+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86 -+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 -+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 -+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 -+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 -+#define mmDCP_CRC_CONTROL 0x1a87 -+#define mmDCP0_DCP_CRC_CONTROL 0x1a87 -+#define mmDCP1_DCP_CRC_CONTROL 0x1d87 -+#define mmDCP2_DCP_CRC_CONTROL 0x4087 -+#define mmDCP3_DCP_CRC_CONTROL 0x4387 -+#define mmDCP4_DCP_CRC_CONTROL 0x4687 -+#define mmDCP5_DCP_CRC_CONTROL 0x4987 -+#define mmDCP_CRC_MASK 0x1a88 -+#define mmDCP0_DCP_CRC_MASK 0x1a88 -+#define mmDCP1_DCP_CRC_MASK 0x1d88 -+#define mmDCP2_DCP_CRC_MASK 0x4088 -+#define mmDCP3_DCP_CRC_MASK 0x4388 -+#define mmDCP4_DCP_CRC_MASK 0x4688 -+#define mmDCP5_DCP_CRC_MASK 0x4988 -+#define mmDCP_CRC_CURRENT 0x1a89 -+#define mmDCP0_DCP_CRC_CURRENT 0x1a89 -+#define mmDCP1_DCP_CRC_CURRENT 0x1d89 -+#define mmDCP2_DCP_CRC_CURRENT 0x4089 -+#define mmDCP3_DCP_CRC_CURRENT 0x4389 -+#define mmDCP4_DCP_CRC_CURRENT 0x4689 -+#define mmDCP5_DCP_CRC_CURRENT 0x4989 -+#define mmDCP_CRC_LAST 0x1a8b -+#define mmDCP0_DCP_CRC_LAST 0x1a8b -+#define mmDCP1_DCP_CRC_LAST 0x1d8b -+#define mmDCP2_DCP_CRC_LAST 0x408b -+#define mmDCP3_DCP_CRC_LAST 0x438b -+#define mmDCP4_DCP_CRC_LAST 0x468b -+#define mmDCP5_DCP_CRC_LAST 0x498b -+#define mmDCP_DEBUG 0x1a8d -+#define mmDCP0_DCP_DEBUG 0x1a8d -+#define mmDCP1_DCP_DEBUG 0x1d8d -+#define mmDCP2_DCP_DEBUG 0x408d -+#define mmDCP3_DCP_DEBUG 0x438d -+#define mmDCP4_DCP_DEBUG 0x468d -+#define mmDCP5_DCP_DEBUG 0x498d -+#define mmGRPH_FLIP_RATE_CNTL 0x1a8e -+#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e -+#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e -+#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e -+#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e -+#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e -+#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e -+#define mmDCP_GSL_CONTROL 0x1a90 -+#define mmDCP0_DCP_GSL_CONTROL 0x1a90 -+#define mmDCP1_DCP_GSL_CONTROL 0x1d90 -+#define mmDCP2_DCP_GSL_CONTROL 0x4090 -+#define mmDCP3_DCP_GSL_CONTROL 0x4390 -+#define mmDCP4_DCP_GSL_CONTROL 0x4690 -+#define mmDCP5_DCP_GSL_CONTROL 0x4990 -+#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 -+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91 -+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 -+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 -+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 -+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 -+#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 -+#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 -+#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92 -+#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 -+#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 -+#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 -+#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 -+#define mmOVL_STEREOSYNC_FLIP 0x1a93 -+#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 -+#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93 -+#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 -+#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 -+#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 -+#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 -+#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 -+#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 -+#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94 -+#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 -+#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 -+#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 -+#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 -+#define mmDCP_TEST_DEBUG_INDEX 0x1a95 -+#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 -+#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95 -+#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 -+#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 -+#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 -+#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 -+#define mmDCP_TEST_DEBUG_DATA 0x1a96 -+#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 -+#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96 -+#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 -+#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 -+#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 -+#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 -+#define mmGRPH_STEREOSYNC_FLIP 0x1a97 -+#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 -+#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97 -+#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 -+#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 -+#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 -+#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 -+#define mmDCP_DEBUG2 0x1a98 -+#define mmDCP0_DCP_DEBUG2 0x1a98 -+#define mmDCP1_DCP_DEBUG2 0x1d98 -+#define mmDCP2_DCP_DEBUG2 0x4098 -+#define mmDCP3_DCP_DEBUG2 0x4398 -+#define mmDCP4_DCP_DEBUG2 0x4698 -+#define mmDCP5_DCP_DEBUG2 0x4998 -+#define mmHW_ROTATION 0x1a9e -+#define mmDCP0_HW_ROTATION 0x1a9e -+#define mmDCP1_HW_ROTATION 0x1d9e -+#define mmDCP2_HW_ROTATION 0x409e -+#define mmDCP3_HW_ROTATION 0x439e -+#define mmDCP4_HW_ROTATION 0x469e -+#define mmDCP5_HW_ROTATION 0x499e -+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f -+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f -+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f -+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f -+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f -+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f -+#define mmREGAMMA_CONTROL 0x1aa0 -+#define mmDCP0_REGAMMA_CONTROL 0x1aa0 -+#define mmDCP1_REGAMMA_CONTROL 0x1da0 -+#define mmDCP2_REGAMMA_CONTROL 0x40a0 -+#define mmDCP3_REGAMMA_CONTROL 0x43a0 -+#define mmDCP4_REGAMMA_CONTROL 0x46a0 -+#define mmDCP5_REGAMMA_CONTROL 0x49a0 -+#define mmREGAMMA_LUT_INDEX 0x1aa1 -+#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 -+#define mmDCP1_REGAMMA_LUT_INDEX 0x1da1 -+#define mmDCP2_REGAMMA_LUT_INDEX 0x40a1 -+#define mmDCP3_REGAMMA_LUT_INDEX 0x43a1 -+#define mmDCP4_REGAMMA_LUT_INDEX 0x46a1 -+#define mmDCP5_REGAMMA_LUT_INDEX 0x49a1 -+#define mmREGAMMA_LUT_DATA 0x1aa2 -+#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 -+#define mmDCP1_REGAMMA_LUT_DATA 0x1da2 -+#define mmDCP2_REGAMMA_LUT_DATA 0x40a2 -+#define mmDCP3_REGAMMA_LUT_DATA 0x43a2 -+#define mmDCP4_REGAMMA_LUT_DATA 0x46a2 -+#define mmDCP5_REGAMMA_LUT_DATA 0x49a2 -+#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 -+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3 -+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 -+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3 -+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3 -+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3 -+#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 -+#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 -+#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4 -+#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4 -+#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4 -+#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4 -+#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4 -+#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 -+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5 -+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 -+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5 -+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5 -+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5 -+#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 -+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 -+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6 -+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6 -+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6 -+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6 -+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6 -+#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 -+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 -+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7 -+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7 -+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7 -+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7 -+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7 -+#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 -+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 -+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8 -+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8 -+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8 -+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8 -+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8 -+#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 -+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 -+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9 -+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9 -+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9 -+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9 -+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9 -+#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa -+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa -+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa -+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa -+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa -+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa -+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa -+#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab -+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab -+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab -+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab -+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab -+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab -+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab -+#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac -+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac -+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac -+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac -+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac -+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac -+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac -+#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad -+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad -+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad -+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad -+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad -+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad -+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad -+#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae -+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae -+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae -+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae -+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae -+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae -+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae -+#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf -+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf -+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf -+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af -+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af -+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af -+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af -+#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 -+#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 -+#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0 -+#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0 -+#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0 -+#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0 -+#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0 -+#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 -+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1 -+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 -+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1 -+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1 -+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1 -+#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 -+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 -+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2 -+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2 -+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2 -+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2 -+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2 -+#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 -+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 -+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3 -+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3 -+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3 -+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3 -+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3 -+#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 -+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 -+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4 -+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4 -+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4 -+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4 -+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4 -+#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 -+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 -+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5 -+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5 -+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5 -+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5 -+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5 -+#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 -+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 -+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6 -+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6 -+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6 -+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6 -+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6 -+#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 -+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 -+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7 -+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7 -+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7 -+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7 -+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7 -+#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 -+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 -+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8 -+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8 -+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8 -+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8 -+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8 -+#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 -+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 -+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9 -+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9 -+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9 -+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9 -+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9 -+#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba -+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba -+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba -+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba -+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba -+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba -+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba -+#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb -+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb -+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb -+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb -+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb -+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb -+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb -+#define mmALPHA_CONTROL 0x1abc -+#define mmDCP0_ALPHA_CONTROL 0x1abc -+#define mmDCP1_ALPHA_CONTROL 0x1dbc -+#define mmDCP2_ALPHA_CONTROL 0x40bc -+#define mmDCP3_ALPHA_CONTROL 0x43bc -+#define mmDCP4_ALPHA_CONTROL 0x46bc -+#define mmDCP5_ALPHA_CONTROL 0x49bc -+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd -+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd -+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd -+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd -+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd -+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd -+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe -+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe -+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be -+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be -+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be -+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be -+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf -+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf -+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf -+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf -+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf -+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf -+#define mmDIG_FE_CNTL 0x1c00 -+#define mmDIG0_DIG_FE_CNTL 0x1c00 -+#define mmDIG1_DIG_FE_CNTL 0x1f00 -+#define mmDIG2_DIG_FE_CNTL 0x4200 -+#define mmDIG3_DIG_FE_CNTL 0x4500 -+#define mmDIG4_DIG_FE_CNTL 0x4800 -+#define mmDIG5_DIG_FE_CNTL 0x4b00 -+#define mmDIG6_DIG_FE_CNTL 0x4e00 -+#define mmDIG_OUTPUT_CRC_CNTL 0x1c01 -+#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01 -+#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01 -+#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 -+#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 -+#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 -+#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01 -+#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01 -+#define mmDIG_OUTPUT_CRC_RESULT 0x1c02 -+#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02 -+#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02 -+#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 -+#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 -+#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 -+#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02 -+#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02 -+#define mmDIG_CLOCK_PATTERN 0x1c03 -+#define mmDIG0_DIG_CLOCK_PATTERN 0x1c03 -+#define mmDIG1_DIG_CLOCK_PATTERN 0x1f03 -+#define mmDIG2_DIG_CLOCK_PATTERN 0x4203 -+#define mmDIG3_DIG_CLOCK_PATTERN 0x4503 -+#define mmDIG4_DIG_CLOCK_PATTERN 0x4803 -+#define mmDIG5_DIG_CLOCK_PATTERN 0x4b03 -+#define mmDIG6_DIG_CLOCK_PATTERN 0x4e03 -+#define mmDIG_TEST_PATTERN 0x1c04 -+#define mmDIG0_DIG_TEST_PATTERN 0x1c04 -+#define mmDIG1_DIG_TEST_PATTERN 0x1f04 -+#define mmDIG2_DIG_TEST_PATTERN 0x4204 -+#define mmDIG3_DIG_TEST_PATTERN 0x4504 -+#define mmDIG4_DIG_TEST_PATTERN 0x4804 -+#define mmDIG5_DIG_TEST_PATTERN 0x4b04 -+#define mmDIG6_DIG_TEST_PATTERN 0x4e04 -+#define mmDIG_RANDOM_PATTERN_SEED 0x1c05 -+#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05 -+#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05 -+#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 -+#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 -+#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 -+#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05 -+#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05 -+#define mmDIG_FIFO_STATUS 0x1c0a -+#define mmDIG0_DIG_FIFO_STATUS 0x1c0a -+#define mmDIG1_DIG_FIFO_STATUS 0x1f0a -+#define mmDIG2_DIG_FIFO_STATUS 0x420a -+#define mmDIG3_DIG_FIFO_STATUS 0x450a -+#define mmDIG4_DIG_FIFO_STATUS 0x480a -+#define mmDIG5_DIG_FIFO_STATUS 0x4b0a -+#define mmDIG6_DIG_FIFO_STATUS 0x4e0a -+#define mmDIG_DISPCLK_SWITCH_CNTL 0x1c08 -+#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08 -+#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08 -+#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 -+#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 -+#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 -+#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08 -+#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08 -+#define mmDIG_DISPCLK_SWITCH_STATUS 0x1c09 -+#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09 -+#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09 -+#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 -+#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 -+#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 -+#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09 -+#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09 -+#define mmHDMI_CONTROL 0x1c0c -+#define mmDIG0_HDMI_CONTROL 0x1c0c -+#define mmDIG1_HDMI_CONTROL 0x1f0c -+#define mmDIG2_HDMI_CONTROL 0x420c -+#define mmDIG3_HDMI_CONTROL 0x450c -+#define mmDIG4_HDMI_CONTROL 0x480c -+#define mmDIG5_HDMI_CONTROL 0x4b0c -+#define mmDIG6_HDMI_CONTROL 0x4e0c -+#define mmHDMI_STATUS 0x1c0d -+#define mmDIG0_HDMI_STATUS 0x1c0d -+#define mmDIG1_HDMI_STATUS 0x1f0d -+#define mmDIG2_HDMI_STATUS 0x420d -+#define mmDIG3_HDMI_STATUS 0x450d -+#define mmDIG4_HDMI_STATUS 0x480d -+#define mmDIG5_HDMI_STATUS 0x4b0d -+#define mmDIG6_HDMI_STATUS 0x4e0d -+#define mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e -+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e -+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e -+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e -+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e -+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e -+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e -+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e -+#define mmHDMI_ACR_PACKET_CONTROL 0x1c0f -+#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f -+#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f -+#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f -+#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f -+#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f -+#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f -+#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f -+#define mmHDMI_VBI_PACKET_CONTROL 0x1c10 -+#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10 -+#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10 -+#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 -+#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 -+#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 -+#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10 -+#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10 -+#define mmHDMI_INFOFRAME_CONTROL0 0x1c11 -+#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11 -+#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11 -+#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 -+#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 -+#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 -+#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11 -+#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11 -+#define mmHDMI_INFOFRAME_CONTROL1 0x1c12 -+#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12 -+#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12 -+#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 -+#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 -+#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 -+#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12 -+#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12 -+#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13 -+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13 -+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13 -+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 -+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 -+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 -+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13 -+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13 -+#define mmAFMT_INTERRUPT_STATUS 0x1c14 -+#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14 -+#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14 -+#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 -+#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 -+#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 -+#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14 -+#define mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14 -+#define mmHDMI_GC 0x1c16 -+#define mmDIG0_HDMI_GC 0x1c16 -+#define mmDIG1_HDMI_GC 0x1f16 -+#define mmDIG2_HDMI_GC 0x4216 -+#define mmDIG3_HDMI_GC 0x4516 -+#define mmDIG4_HDMI_GC 0x4816 -+#define mmDIG5_HDMI_GC 0x4b16 -+#define mmDIG6_HDMI_GC 0x4e16 -+#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17 -+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17 -+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17 -+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 -+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 -+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 -+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17 -+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17 -+#define mmAFMT_ISRC1_0 0x1c18 -+#define mmDIG0_AFMT_ISRC1_0 0x1c18 -+#define mmDIG1_AFMT_ISRC1_0 0x1f18 -+#define mmDIG2_AFMT_ISRC1_0 0x4218 -+#define mmDIG3_AFMT_ISRC1_0 0x4518 -+#define mmDIG4_AFMT_ISRC1_0 0x4818 -+#define mmDIG5_AFMT_ISRC1_0 0x4b18 -+#define mmDIG6_AFMT_ISRC1_0 0x4e18 -+#define mmAFMT_ISRC1_1 0x1c19 -+#define mmDIG0_AFMT_ISRC1_1 0x1c19 -+#define mmDIG1_AFMT_ISRC1_1 0x1f19 -+#define mmDIG2_AFMT_ISRC1_1 0x4219 -+#define mmDIG3_AFMT_ISRC1_1 0x4519 -+#define mmDIG4_AFMT_ISRC1_1 0x4819 -+#define mmDIG5_AFMT_ISRC1_1 0x4b19 -+#define mmDIG6_AFMT_ISRC1_1 0x4e19 -+#define mmAFMT_ISRC1_2 0x1c1a -+#define mmDIG0_AFMT_ISRC1_2 0x1c1a -+#define mmDIG1_AFMT_ISRC1_2 0x1f1a -+#define mmDIG2_AFMT_ISRC1_2 0x421a -+#define mmDIG3_AFMT_ISRC1_2 0x451a -+#define mmDIG4_AFMT_ISRC1_2 0x481a -+#define mmDIG5_AFMT_ISRC1_2 0x4b1a -+#define mmDIG6_AFMT_ISRC1_2 0x4e1a -+#define mmAFMT_ISRC1_3 0x1c1b -+#define mmDIG0_AFMT_ISRC1_3 0x1c1b -+#define mmDIG1_AFMT_ISRC1_3 0x1f1b -+#define mmDIG2_AFMT_ISRC1_3 0x421b -+#define mmDIG3_AFMT_ISRC1_3 0x451b -+#define mmDIG4_AFMT_ISRC1_3 0x481b -+#define mmDIG5_AFMT_ISRC1_3 0x4b1b -+#define mmDIG6_AFMT_ISRC1_3 0x4e1b -+#define mmAFMT_ISRC1_4 0x1c1c -+#define mmDIG0_AFMT_ISRC1_4 0x1c1c -+#define mmDIG1_AFMT_ISRC1_4 0x1f1c -+#define mmDIG2_AFMT_ISRC1_4 0x421c -+#define mmDIG3_AFMT_ISRC1_4 0x451c -+#define mmDIG4_AFMT_ISRC1_4 0x481c -+#define mmDIG5_AFMT_ISRC1_4 0x4b1c -+#define mmDIG6_AFMT_ISRC1_4 0x4e1c -+#define mmAFMT_ISRC2_0 0x1c1d -+#define mmDIG0_AFMT_ISRC2_0 0x1c1d -+#define mmDIG1_AFMT_ISRC2_0 0x1f1d -+#define mmDIG2_AFMT_ISRC2_0 0x421d -+#define mmDIG3_AFMT_ISRC2_0 0x451d -+#define mmDIG4_AFMT_ISRC2_0 0x481d -+#define mmDIG5_AFMT_ISRC2_0 0x4b1d -+#define mmDIG6_AFMT_ISRC2_0 0x4e1d -+#define mmAFMT_ISRC2_1 0x1c1e -+#define mmDIG0_AFMT_ISRC2_1 0x1c1e -+#define mmDIG1_AFMT_ISRC2_1 0x1f1e -+#define mmDIG2_AFMT_ISRC2_1 0x421e -+#define mmDIG3_AFMT_ISRC2_1 0x451e -+#define mmDIG4_AFMT_ISRC2_1 0x481e -+#define mmDIG5_AFMT_ISRC2_1 0x4b1e -+#define mmDIG6_AFMT_ISRC2_1 0x4e1e -+#define mmAFMT_ISRC2_2 0x1c1f -+#define mmDIG0_AFMT_ISRC2_2 0x1c1f -+#define mmDIG1_AFMT_ISRC2_2 0x1f1f -+#define mmDIG2_AFMT_ISRC2_2 0x421f -+#define mmDIG3_AFMT_ISRC2_2 0x451f -+#define mmDIG4_AFMT_ISRC2_2 0x481f -+#define mmDIG5_AFMT_ISRC2_2 0x4b1f -+#define mmDIG6_AFMT_ISRC2_2 0x4e1f -+#define mmAFMT_ISRC2_3 0x1c20 -+#define mmDIG0_AFMT_ISRC2_3 0x1c20 -+#define mmDIG1_AFMT_ISRC2_3 0x1f20 -+#define mmDIG2_AFMT_ISRC2_3 0x4220 -+#define mmDIG3_AFMT_ISRC2_3 0x4520 -+#define mmDIG4_AFMT_ISRC2_3 0x4820 -+#define mmDIG5_AFMT_ISRC2_3 0x4b20 -+#define mmDIG6_AFMT_ISRC2_3 0x4e20 -+#define mmAFMT_AVI_INFO0 0x1c21 -+#define mmDIG0_AFMT_AVI_INFO0 0x1c21 -+#define mmDIG1_AFMT_AVI_INFO0 0x1f21 -+#define mmDIG2_AFMT_AVI_INFO0 0x4221 -+#define mmDIG3_AFMT_AVI_INFO0 0x4521 -+#define mmDIG4_AFMT_AVI_INFO0 0x4821 -+#define mmDIG5_AFMT_AVI_INFO0 0x4b21 -+#define mmDIG6_AFMT_AVI_INFO0 0x4e21 -+#define mmAFMT_AVI_INFO1 0x1c22 -+#define mmDIG0_AFMT_AVI_INFO1 0x1c22 -+#define mmDIG1_AFMT_AVI_INFO1 0x1f22 -+#define mmDIG2_AFMT_AVI_INFO1 0x4222 -+#define mmDIG3_AFMT_AVI_INFO1 0x4522 -+#define mmDIG4_AFMT_AVI_INFO1 0x4822 -+#define mmDIG5_AFMT_AVI_INFO1 0x4b22 -+#define mmDIG6_AFMT_AVI_INFO1 0x4e22 -+#define mmAFMT_AVI_INFO2 0x1c23 -+#define mmDIG0_AFMT_AVI_INFO2 0x1c23 -+#define mmDIG1_AFMT_AVI_INFO2 0x1f23 -+#define mmDIG2_AFMT_AVI_INFO2 0x4223 -+#define mmDIG3_AFMT_AVI_INFO2 0x4523 -+#define mmDIG4_AFMT_AVI_INFO2 0x4823 -+#define mmDIG5_AFMT_AVI_INFO2 0x4b23 -+#define mmDIG6_AFMT_AVI_INFO2 0x4e23 -+#define mmAFMT_AVI_INFO3 0x1c24 -+#define mmDIG0_AFMT_AVI_INFO3 0x1c24 -+#define mmDIG1_AFMT_AVI_INFO3 0x1f24 -+#define mmDIG2_AFMT_AVI_INFO3 0x4224 -+#define mmDIG3_AFMT_AVI_INFO3 0x4524 -+#define mmDIG4_AFMT_AVI_INFO3 0x4824 -+#define mmDIG5_AFMT_AVI_INFO3 0x4b24 -+#define mmDIG6_AFMT_AVI_INFO3 0x4e24 -+#define mmAFMT_MPEG_INFO0 0x1c25 -+#define mmDIG0_AFMT_MPEG_INFO0 0x1c25 -+#define mmDIG1_AFMT_MPEG_INFO0 0x1f25 -+#define mmDIG2_AFMT_MPEG_INFO0 0x4225 -+#define mmDIG3_AFMT_MPEG_INFO0 0x4525 -+#define mmDIG4_AFMT_MPEG_INFO0 0x4825 -+#define mmDIG5_AFMT_MPEG_INFO0 0x4b25 -+#define mmDIG6_AFMT_MPEG_INFO0 0x4e25 -+#define mmAFMT_MPEG_INFO1 0x1c26 -+#define mmDIG0_AFMT_MPEG_INFO1 0x1c26 -+#define mmDIG1_AFMT_MPEG_INFO1 0x1f26 -+#define mmDIG2_AFMT_MPEG_INFO1 0x4226 -+#define mmDIG3_AFMT_MPEG_INFO1 0x4526 -+#define mmDIG4_AFMT_MPEG_INFO1 0x4826 -+#define mmDIG5_AFMT_MPEG_INFO1 0x4b26 -+#define mmDIG6_AFMT_MPEG_INFO1 0x4e26 -+#define mmAFMT_GENERIC_HDR 0x1c27 -+#define mmDIG0_AFMT_GENERIC_HDR 0x1c27 -+#define mmDIG1_AFMT_GENERIC_HDR 0x1f27 -+#define mmDIG2_AFMT_GENERIC_HDR 0x4227 -+#define mmDIG3_AFMT_GENERIC_HDR 0x4527 -+#define mmDIG4_AFMT_GENERIC_HDR 0x4827 -+#define mmDIG5_AFMT_GENERIC_HDR 0x4b27 -+#define mmDIG6_AFMT_GENERIC_HDR 0x4e27 -+#define mmAFMT_GENERIC_0 0x1c28 -+#define mmDIG0_AFMT_GENERIC_0 0x1c28 -+#define mmDIG1_AFMT_GENERIC_0 0x1f28 -+#define mmDIG2_AFMT_GENERIC_0 0x4228 -+#define mmDIG3_AFMT_GENERIC_0 0x4528 -+#define mmDIG4_AFMT_GENERIC_0 0x4828 -+#define mmDIG5_AFMT_GENERIC_0 0x4b28 -+#define mmDIG6_AFMT_GENERIC_0 0x4e28 -+#define mmAFMT_GENERIC_1 0x1c29 -+#define mmDIG0_AFMT_GENERIC_1 0x1c29 -+#define mmDIG1_AFMT_GENERIC_1 0x1f29 -+#define mmDIG2_AFMT_GENERIC_1 0x4229 -+#define mmDIG3_AFMT_GENERIC_1 0x4529 -+#define mmDIG4_AFMT_GENERIC_1 0x4829 -+#define mmDIG5_AFMT_GENERIC_1 0x4b29 -+#define mmDIG6_AFMT_GENERIC_1 0x4e29 -+#define mmAFMT_GENERIC_2 0x1c2a -+#define mmDIG0_AFMT_GENERIC_2 0x1c2a -+#define mmDIG1_AFMT_GENERIC_2 0x1f2a -+#define mmDIG2_AFMT_GENERIC_2 0x422a -+#define mmDIG3_AFMT_GENERIC_2 0x452a -+#define mmDIG4_AFMT_GENERIC_2 0x482a -+#define mmDIG5_AFMT_GENERIC_2 0x4b2a -+#define mmDIG6_AFMT_GENERIC_2 0x4e2a -+#define mmAFMT_GENERIC_3 0x1c2b -+#define mmDIG0_AFMT_GENERIC_3 0x1c2b -+#define mmDIG1_AFMT_GENERIC_3 0x1f2b -+#define mmDIG2_AFMT_GENERIC_3 0x422b -+#define mmDIG3_AFMT_GENERIC_3 0x452b -+#define mmDIG4_AFMT_GENERIC_3 0x482b -+#define mmDIG5_AFMT_GENERIC_3 0x4b2b -+#define mmDIG6_AFMT_GENERIC_3 0x4e2b -+#define mmAFMT_GENERIC_4 0x1c2c -+#define mmDIG0_AFMT_GENERIC_4 0x1c2c -+#define mmDIG1_AFMT_GENERIC_4 0x1f2c -+#define mmDIG2_AFMT_GENERIC_4 0x422c -+#define mmDIG3_AFMT_GENERIC_4 0x452c -+#define mmDIG4_AFMT_GENERIC_4 0x482c -+#define mmDIG5_AFMT_GENERIC_4 0x4b2c -+#define mmDIG6_AFMT_GENERIC_4 0x4e2c -+#define mmAFMT_GENERIC_5 0x1c2d -+#define mmDIG0_AFMT_GENERIC_5 0x1c2d -+#define mmDIG1_AFMT_GENERIC_5 0x1f2d -+#define mmDIG2_AFMT_GENERIC_5 0x422d -+#define mmDIG3_AFMT_GENERIC_5 0x452d -+#define mmDIG4_AFMT_GENERIC_5 0x482d -+#define mmDIG5_AFMT_GENERIC_5 0x4b2d -+#define mmDIG6_AFMT_GENERIC_5 0x4e2d -+#define mmAFMT_GENERIC_6 0x1c2e -+#define mmDIG0_AFMT_GENERIC_6 0x1c2e -+#define mmDIG1_AFMT_GENERIC_6 0x1f2e -+#define mmDIG2_AFMT_GENERIC_6 0x422e -+#define mmDIG3_AFMT_GENERIC_6 0x452e -+#define mmDIG4_AFMT_GENERIC_6 0x482e -+#define mmDIG5_AFMT_GENERIC_6 0x4b2e -+#define mmDIG6_AFMT_GENERIC_6 0x4e2e -+#define mmAFMT_GENERIC_7 0x1c2f -+#define mmDIG0_AFMT_GENERIC_7 0x1c2f -+#define mmDIG1_AFMT_GENERIC_7 0x1f2f -+#define mmDIG2_AFMT_GENERIC_7 0x422f -+#define mmDIG3_AFMT_GENERIC_7 0x452f -+#define mmDIG4_AFMT_GENERIC_7 0x482f -+#define mmDIG5_AFMT_GENERIC_7 0x4b2f -+#define mmDIG6_AFMT_GENERIC_7 0x4e2f -+#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30 -+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30 -+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30 -+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 -+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 -+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 -+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30 -+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30 -+#define mmHDMI_ACR_32_0 0x1c37 -+#define mmDIG0_HDMI_ACR_32_0 0x1c37 -+#define mmDIG1_HDMI_ACR_32_0 0x1f37 -+#define mmDIG2_HDMI_ACR_32_0 0x4237 -+#define mmDIG3_HDMI_ACR_32_0 0x4537 -+#define mmDIG4_HDMI_ACR_32_0 0x4837 -+#define mmDIG5_HDMI_ACR_32_0 0x4b37 -+#define mmDIG6_HDMI_ACR_32_0 0x4e37 -+#define mmHDMI_ACR_32_1 0x1c38 -+#define mmDIG0_HDMI_ACR_32_1 0x1c38 -+#define mmDIG1_HDMI_ACR_32_1 0x1f38 -+#define mmDIG2_HDMI_ACR_32_1 0x4238 -+#define mmDIG3_HDMI_ACR_32_1 0x4538 -+#define mmDIG4_HDMI_ACR_32_1 0x4838 -+#define mmDIG5_HDMI_ACR_32_1 0x4b38 -+#define mmDIG6_HDMI_ACR_32_1 0x4e38 -+#define mmHDMI_ACR_44_0 0x1c39 -+#define mmDIG0_HDMI_ACR_44_0 0x1c39 -+#define mmDIG1_HDMI_ACR_44_0 0x1f39 -+#define mmDIG2_HDMI_ACR_44_0 0x4239 -+#define mmDIG3_HDMI_ACR_44_0 0x4539 -+#define mmDIG4_HDMI_ACR_44_0 0x4839 -+#define mmDIG5_HDMI_ACR_44_0 0x4b39 -+#define mmDIG6_HDMI_ACR_44_0 0x4e39 -+#define mmHDMI_ACR_44_1 0x1c3a -+#define mmDIG0_HDMI_ACR_44_1 0x1c3a -+#define mmDIG1_HDMI_ACR_44_1 0x1f3a -+#define mmDIG2_HDMI_ACR_44_1 0x423a -+#define mmDIG3_HDMI_ACR_44_1 0x453a -+#define mmDIG4_HDMI_ACR_44_1 0x483a -+#define mmDIG5_HDMI_ACR_44_1 0x4b3a -+#define mmDIG6_HDMI_ACR_44_1 0x4e3a -+#define mmHDMI_ACR_48_0 0x1c3b -+#define mmDIG0_HDMI_ACR_48_0 0x1c3b -+#define mmDIG1_HDMI_ACR_48_0 0x1f3b -+#define mmDIG2_HDMI_ACR_48_0 0x423b -+#define mmDIG3_HDMI_ACR_48_0 0x453b -+#define mmDIG4_HDMI_ACR_48_0 0x483b -+#define mmDIG5_HDMI_ACR_48_0 0x4b3b -+#define mmDIG6_HDMI_ACR_48_0 0x4e3b -+#define mmHDMI_ACR_48_1 0x1c3c -+#define mmDIG0_HDMI_ACR_48_1 0x1c3c -+#define mmDIG1_HDMI_ACR_48_1 0x1f3c -+#define mmDIG2_HDMI_ACR_48_1 0x423c -+#define mmDIG3_HDMI_ACR_48_1 0x453c -+#define mmDIG4_HDMI_ACR_48_1 0x483c -+#define mmDIG5_HDMI_ACR_48_1 0x4b3c -+#define mmDIG6_HDMI_ACR_48_1 0x4e3c -+#define mmHDMI_ACR_STATUS_0 0x1c3d -+#define mmDIG0_HDMI_ACR_STATUS_0 0x1c3d -+#define mmDIG1_HDMI_ACR_STATUS_0 0x1f3d -+#define mmDIG2_HDMI_ACR_STATUS_0 0x423d -+#define mmDIG3_HDMI_ACR_STATUS_0 0x453d -+#define mmDIG4_HDMI_ACR_STATUS_0 0x483d -+#define mmDIG5_HDMI_ACR_STATUS_0 0x4b3d -+#define mmDIG6_HDMI_ACR_STATUS_0 0x4e3d -+#define mmHDMI_ACR_STATUS_1 0x1c3e -+#define mmDIG0_HDMI_ACR_STATUS_1 0x1c3e -+#define mmDIG1_HDMI_ACR_STATUS_1 0x1f3e -+#define mmDIG2_HDMI_ACR_STATUS_1 0x423e -+#define mmDIG3_HDMI_ACR_STATUS_1 0x453e -+#define mmDIG4_HDMI_ACR_STATUS_1 0x483e -+#define mmDIG5_HDMI_ACR_STATUS_1 0x4b3e -+#define mmDIG6_HDMI_ACR_STATUS_1 0x4e3e -+#define mmAFMT_AUDIO_INFO0 0x1c3f -+#define mmDIG0_AFMT_AUDIO_INFO0 0x1c3f -+#define mmDIG1_AFMT_AUDIO_INFO0 0x1f3f -+#define mmDIG2_AFMT_AUDIO_INFO0 0x423f -+#define mmDIG3_AFMT_AUDIO_INFO0 0x453f -+#define mmDIG4_AFMT_AUDIO_INFO0 0x483f -+#define mmDIG5_AFMT_AUDIO_INFO0 0x4b3f -+#define mmDIG6_AFMT_AUDIO_INFO0 0x4e3f -+#define mmAFMT_AUDIO_INFO1 0x1c40 -+#define mmDIG0_AFMT_AUDIO_INFO1 0x1c40 -+#define mmDIG1_AFMT_AUDIO_INFO1 0x1f40 -+#define mmDIG2_AFMT_AUDIO_INFO1 0x4240 -+#define mmDIG3_AFMT_AUDIO_INFO1 0x4540 -+#define mmDIG4_AFMT_AUDIO_INFO1 0x4840 -+#define mmDIG5_AFMT_AUDIO_INFO1 0x4b40 -+#define mmDIG6_AFMT_AUDIO_INFO1 0x4e40 -+#define mmAFMT_60958_0 0x1c41 -+#define mmDIG0_AFMT_60958_0 0x1c41 -+#define mmDIG1_AFMT_60958_0 0x1f41 -+#define mmDIG2_AFMT_60958_0 0x4241 -+#define mmDIG3_AFMT_60958_0 0x4541 -+#define mmDIG4_AFMT_60958_0 0x4841 -+#define mmDIG5_AFMT_60958_0 0x4b41 -+#define mmDIG6_AFMT_60958_0 0x4e41 -+#define mmAFMT_60958_1 0x1c42 -+#define mmDIG0_AFMT_60958_1 0x1c42 -+#define mmDIG1_AFMT_60958_1 0x1f42 -+#define mmDIG2_AFMT_60958_1 0x4242 -+#define mmDIG3_AFMT_60958_1 0x4542 -+#define mmDIG4_AFMT_60958_1 0x4842 -+#define mmDIG5_AFMT_60958_1 0x4b42 -+#define mmDIG6_AFMT_60958_1 0x4e42 -+#define mmAFMT_AUDIO_CRC_CONTROL 0x1c43 -+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43 -+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43 -+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 -+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 -+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 -+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43 -+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43 -+#define mmAFMT_RAMP_CONTROL0 0x1c44 -+#define mmDIG0_AFMT_RAMP_CONTROL0 0x1c44 -+#define mmDIG1_AFMT_RAMP_CONTROL0 0x1f44 -+#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 -+#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 -+#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 -+#define mmDIG5_AFMT_RAMP_CONTROL0 0x4b44 -+#define mmDIG6_AFMT_RAMP_CONTROL0 0x4e44 -+#define mmAFMT_RAMP_CONTROL1 0x1c45 -+#define mmDIG0_AFMT_RAMP_CONTROL1 0x1c45 -+#define mmDIG1_AFMT_RAMP_CONTROL1 0x1f45 -+#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 -+#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 -+#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 -+#define mmDIG5_AFMT_RAMP_CONTROL1 0x4b45 -+#define mmDIG6_AFMT_RAMP_CONTROL1 0x4e45 -+#define mmAFMT_RAMP_CONTROL2 0x1c46 -+#define mmDIG0_AFMT_RAMP_CONTROL2 0x1c46 -+#define mmDIG1_AFMT_RAMP_CONTROL2 0x1f46 -+#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 -+#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 -+#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 -+#define mmDIG5_AFMT_RAMP_CONTROL2 0x4b46 -+#define mmDIG6_AFMT_RAMP_CONTROL2 0x4e46 -+#define mmAFMT_RAMP_CONTROL3 0x1c47 -+#define mmDIG0_AFMT_RAMP_CONTROL3 0x1c47 -+#define mmDIG1_AFMT_RAMP_CONTROL3 0x1f47 -+#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 -+#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 -+#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 -+#define mmDIG5_AFMT_RAMP_CONTROL3 0x4b47 -+#define mmDIG6_AFMT_RAMP_CONTROL3 0x4e47 -+#define mmAFMT_60958_2 0x1c48 -+#define mmDIG0_AFMT_60958_2 0x1c48 -+#define mmDIG1_AFMT_60958_2 0x1f48 -+#define mmDIG2_AFMT_60958_2 0x4248 -+#define mmDIG3_AFMT_60958_2 0x4548 -+#define mmDIG4_AFMT_60958_2 0x4848 -+#define mmDIG5_AFMT_60958_2 0x4b48 -+#define mmDIG6_AFMT_60958_2 0x4e48 -+#define mmAFMT_AUDIO_CRC_RESULT 0x1c49 -+#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49 -+#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49 -+#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 -+#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 -+#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 -+#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49 -+#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49 -+#define mmAFMT_STATUS 0x1c4a -+#define mmDIG0_AFMT_STATUS 0x1c4a -+#define mmDIG1_AFMT_STATUS 0x1f4a -+#define mmDIG2_AFMT_STATUS 0x424a -+#define mmDIG3_AFMT_STATUS 0x454a -+#define mmDIG4_AFMT_STATUS 0x484a -+#define mmDIG5_AFMT_STATUS 0x4b4a -+#define mmDIG6_AFMT_STATUS 0x4e4a -+#define mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b -+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b -+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b -+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b -+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b -+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b -+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b -+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b -+#define mmAFMT_VBI_PACKET_CONTROL 0x1c4c -+#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c -+#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c -+#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c -+#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c -+#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c -+#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c -+#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c -+#define mmAFMT_INFOFRAME_CONTROL0 0x1c4d -+#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d -+#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d -+#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d -+#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d -+#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d -+#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d -+#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d -+#define mmAFMT_AUDIO_SRC_CONTROL 0x1c4f -+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f -+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f -+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f -+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f -+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f -+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f -+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f -+#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52 -+#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52 -+#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52 -+#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 -+#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 -+#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 -+#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52 -+#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52 -+#define mmDIG_BE_CNTL 0x1c50 -+#define mmDIG0_DIG_BE_CNTL 0x1c50 -+#define mmDIG1_DIG_BE_CNTL 0x1f50 -+#define mmDIG2_DIG_BE_CNTL 0x4250 -+#define mmDIG3_DIG_BE_CNTL 0x4550 -+#define mmDIG4_DIG_BE_CNTL 0x4850 -+#define mmDIG5_DIG_BE_CNTL 0x4b50 -+#define mmDIG6_DIG_BE_CNTL 0x4e50 -+#define mmDIG_BE_EN_CNTL 0x1c51 -+#define mmDIG0_DIG_BE_EN_CNTL 0x1c51 -+#define mmDIG1_DIG_BE_EN_CNTL 0x1f51 -+#define mmDIG2_DIG_BE_EN_CNTL 0x4251 -+#define mmDIG3_DIG_BE_EN_CNTL 0x4551 -+#define mmDIG4_DIG_BE_EN_CNTL 0x4851 -+#define mmDIG5_DIG_BE_EN_CNTL 0x4b51 -+#define mmDIG6_DIG_BE_EN_CNTL 0x4e51 -+#define mmTMDS_CNTL 0x1c7c -+#define mmDIG0_TMDS_CNTL 0x1c7c -+#define mmDIG1_TMDS_CNTL 0x1f7c -+#define mmDIG2_TMDS_CNTL 0x427c -+#define mmDIG3_TMDS_CNTL 0x457c -+#define mmDIG4_TMDS_CNTL 0x487c -+#define mmDIG5_TMDS_CNTL 0x4b7c -+#define mmDIG6_TMDS_CNTL 0x4e7c -+#define mmTMDS_CONTROL_CHAR 0x1c7d -+#define mmDIG0_TMDS_CONTROL_CHAR 0x1c7d -+#define mmDIG1_TMDS_CONTROL_CHAR 0x1f7d -+#define mmDIG2_TMDS_CONTROL_CHAR 0x427d -+#define mmDIG3_TMDS_CONTROL_CHAR 0x457d -+#define mmDIG4_TMDS_CONTROL_CHAR 0x487d -+#define mmDIG5_TMDS_CONTROL_CHAR 0x4b7d -+#define mmDIG6_TMDS_CONTROL_CHAR 0x4e7d -+#define mmTMDS_CONTROL0_FEEDBACK 0x1c7e -+#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e -+#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e -+#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e -+#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e -+#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e -+#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e -+#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e -+#define mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f -+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f -+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f -+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f -+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f -+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f -+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f -+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f -+#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 -+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 -+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80 -+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 -+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 -+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 -+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80 -+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80 -+#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 -+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 -+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81 -+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 -+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 -+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 -+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81 -+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81 -+#define mmTMDS_DEBUG 0x1c82 -+#define mmDIG0_TMDS_DEBUG 0x1c82 -+#define mmDIG1_TMDS_DEBUG 0x1f82 -+#define mmDIG2_TMDS_DEBUG 0x4282 -+#define mmDIG3_TMDS_DEBUG 0x4582 -+#define mmDIG4_TMDS_DEBUG 0x4882 -+#define mmDIG5_TMDS_DEBUG 0x4b82 -+#define mmDIG6_TMDS_DEBUG 0x4e82 -+#define mmTMDS_CTL_BITS 0x1c83 -+#define mmDIG0_TMDS_CTL_BITS 0x1c83 -+#define mmDIG1_TMDS_CTL_BITS 0x1f83 -+#define mmDIG2_TMDS_CTL_BITS 0x4283 -+#define mmDIG3_TMDS_CTL_BITS 0x4583 -+#define mmDIG4_TMDS_CTL_BITS 0x4883 -+#define mmDIG5_TMDS_CTL_BITS 0x4b83 -+#define mmDIG6_TMDS_CTL_BITS 0x4e83 -+#define mmTMDS_DCBALANCER_CONTROL 0x1c84 -+#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84 -+#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84 -+#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 -+#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 -+#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 -+#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84 -+#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84 -+#define mmTMDS_CTL0_1_GEN_CNTL 0x1c86 -+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86 -+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86 -+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 -+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 -+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 -+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86 -+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86 -+#define mmTMDS_CTL2_3_GEN_CNTL 0x1c87 -+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87 -+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87 -+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 -+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 -+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 -+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87 -+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87 -+#define mmLVDS_DATA_CNTL 0x1c8c -+#define mmDIG0_LVDS_DATA_CNTL 0x1c8c -+#define mmDIG1_LVDS_DATA_CNTL 0x1f8c -+#define mmDIG2_LVDS_DATA_CNTL 0x428c -+#define mmDIG3_LVDS_DATA_CNTL 0x458c -+#define mmDIG4_LVDS_DATA_CNTL 0x488c -+#define mmDIG5_LVDS_DATA_CNTL 0x4b8c -+#define mmDIG6_LVDS_DATA_CNTL 0x4e8c -+#define mmDIG_LANE_ENABLE 0x1c8d -+#define mmDIG0_DIG_LANE_ENABLE 0x1c8d -+#define mmDIG1_DIG_LANE_ENABLE 0x1f8d -+#define mmDIG2_DIG_LANE_ENABLE 0x428d -+#define mmDIG3_DIG_LANE_ENABLE 0x458d -+#define mmDIG4_DIG_LANE_ENABLE 0x488d -+#define mmDIG5_DIG_LANE_ENABLE 0x4b8d -+#define mmDIG6_DIG_LANE_ENABLE 0x4e8d -+#define mmDOUT_SCRATCH0 0x1844 -+#define mmDOUT_SCRATCH1 0x1845 -+#define mmDOUT_SCRATCH2 0x1846 -+#define mmDOUT_SCRATCH3 0x1847 -+#define mmDOUT_SCRATCH4 0x1848 -+#define mmDOUT_SCRATCH5 0x1849 -+#define mmDOUT_SCRATCH6 0x184a -+#define mmDOUT_SCRATCH7 0x184b -+#define mmDOUT_DCE_VCE_CONTROL 0x18ff -+#define mmDC_HPD1_INT_STATUS 0x1807 -+#define mmDC_HPD1_INT_CONTROL 0x1808 -+#define mmDC_HPD1_CONTROL 0x1809 -+#define mmDC_HPD2_INT_STATUS 0x180a -+#define mmDC_HPD2_INT_CONTROL 0x180b -+#define mmDC_HPD2_CONTROL 0x180c -+#define mmDC_HPD3_INT_STATUS 0x180d -+#define mmDC_HPD3_INT_CONTROL 0x180e -+#define mmDC_HPD3_CONTROL 0x180f -+#define mmDC_HPD4_INT_STATUS 0x1810 -+#define mmDC_HPD4_INT_CONTROL 0x1811 -+#define mmDC_HPD4_CONTROL 0x1812 -+#define mmDC_HPD5_INT_STATUS 0x1813 -+#define mmDC_HPD5_INT_CONTROL 0x1814 -+#define mmDC_HPD5_CONTROL 0x1815 -+#define mmDC_HPD6_INT_STATUS 0x1816 -+#define mmDC_HPD6_INT_CONTROL 0x1817 -+#define mmDC_HPD6_CONTROL 0x1818 -+#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 -+#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 -+#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 -+#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 -+#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 -+#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 -+#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc -+#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd -+#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be -+#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc -+#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd -+#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe -+#define mmDC_I2C_CONTROL 0x1819 -+#define mmDC_I2C_ARBITRATION 0x181a -+#define mmDC_I2C_INTERRUPT_CONTROL 0x181b -+#define mmDC_I2C_SW_STATUS 0x181c -+#define mmDC_I2C_DDC1_HW_STATUS 0x181d -+#define mmDC_I2C_DDC2_HW_STATUS 0x181e -+#define mmDC_I2C_DDC3_HW_STATUS 0x181f -+#define mmDC_I2C_DDC4_HW_STATUS 0x1820 -+#define mmDC_I2C_DDC5_HW_STATUS 0x1821 -+#define mmDC_I2C_DDC6_HW_STATUS 0x1822 -+#define mmDC_I2C_DDC1_SPEED 0x1823 -+#define mmDC_I2C_DDC1_SETUP 0x1824 -+#define mmDC_I2C_DDC2_SPEED 0x1825 -+#define mmDC_I2C_DDC2_SETUP 0x1826 -+#define mmDC_I2C_DDC3_SPEED 0x1827 -+#define mmDC_I2C_DDC3_SETUP 0x1828 -+#define mmDC_I2C_DDC4_SPEED 0x1829 -+#define mmDC_I2C_DDC4_SETUP 0x182a -+#define mmDC_I2C_DDC5_SPEED 0x182b -+#define mmDC_I2C_DDC5_SETUP 0x182c -+#define mmDC_I2C_DDC6_SPEED 0x182d -+#define mmDC_I2C_DDC6_SETUP 0x182e -+#define mmDC_I2C_TRANSACTION0 0x182f -+#define mmDC_I2C_TRANSACTION1 0x1830 -+#define mmDC_I2C_TRANSACTION2 0x1831 -+#define mmDC_I2C_TRANSACTION3 0x1832 -+#define mmDC_I2C_DATA 0x1833 -+#define mmGENERIC_I2C_CONTROL 0x1834 -+#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 -+#define mmGENERIC_I2C_STATUS 0x1836 -+#define mmGENERIC_I2C_SPEED 0x1837 -+#define mmGENERIC_I2C_SETUP 0x1838 -+#define mmGENERIC_I2C_TRANSACTION 0x1839 -+#define mmGENERIC_I2C_DATA 0x183a -+#define mmGENERIC_I2C_PIN_SELECTION 0x183b -+#define mmGENERIC_I2C_PIN_DEBUG 0x183c -+#define mmDISP_INTERRUPT_STATUS 0x183d -+#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e -+#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f -+#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 -+#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 -+#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 -+#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0 -+#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1 -+#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2 -+#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3 -+#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 -+#define mmDISP_TIMER_CONTROL 0x1842 -+#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 -+#define mmDC_I2C_DDCVGA_SPEED 0x1856 -+#define mmDC_I2C_DDCVGA_SETUP 0x1857 -+#define mmDC_I2C_EDID_DETECT_CTRL 0x186f -+#define mmDISPOUT_STEREOSYNC_SEL 0x18bf -+#define mmDOUT_TEST_DEBUG_INDEX 0x184d -+#define mmDOUT_TEST_DEBUG_DATA 0x184e -+#define ixDP_AUX1_DEBUG_A 0x10 -+#define ixDP_AUX1_DEBUG_B 0x11 -+#define ixDP_AUX1_DEBUG_C 0x12 -+#define ixDP_AUX1_DEBUG_D 0x13 -+#define ixDP_AUX1_DEBUG_E 0x14 -+#define ixDP_AUX1_DEBUG_F 0x15 -+#define ixDP_AUX1_DEBUG_G 0x16 -+#define ixDP_AUX1_DEBUG_H 0x17 -+#define ixDP_AUX1_DEBUG_I 0x18 -+#define ixDP_AUX1_DEBUG_J 0x19 -+#define ixDP_AUX1_DEBUG_K 0x1a -+#define ixDP_AUX1_DEBUG_L 0x1b -+#define ixDP_AUX1_DEBUG_M 0x1c -+#define ixDP_AUX1_DEBUG_N 0x1d -+#define ixDP_AUX1_DEBUG_O 0x1e -+#define ixDP_AUX1_DEBUG_P 0x1f -+#define ixDP_AUX1_DEBUG_Q 0x90 -+#define ixDP_AUX2_DEBUG_A 0x20 -+#define ixDP_AUX2_DEBUG_B 0x21 -+#define ixDP_AUX2_DEBUG_C 0x22 -+#define ixDP_AUX2_DEBUG_D 0x23 -+#define ixDP_AUX2_DEBUG_E 0x24 -+#define ixDP_AUX2_DEBUG_F 0x25 -+#define ixDP_AUX2_DEBUG_G 0x26 -+#define ixDP_AUX2_DEBUG_H 0x27 -+#define ixDP_AUX2_DEBUG_I 0x28 -+#define ixDP_AUX2_DEBUG_J 0x29 -+#define ixDP_AUX2_DEBUG_K 0x2a -+#define ixDP_AUX2_DEBUG_L 0x2b -+#define ixDP_AUX2_DEBUG_M 0x2c -+#define ixDP_AUX2_DEBUG_N 0x2d -+#define ixDP_AUX2_DEBUG_O 0x2e -+#define ixDP_AUX2_DEBUG_P 0x2f -+#define ixDP_AUX2_DEBUG_Q 0x91 -+#define ixDP_AUX3_DEBUG_A 0x30 -+#define ixDP_AUX3_DEBUG_B 0x31 -+#define ixDP_AUX3_DEBUG_C 0x32 -+#define ixDP_AUX3_DEBUG_D 0x33 -+#define ixDP_AUX3_DEBUG_E 0x34 -+#define ixDP_AUX3_DEBUG_F 0x35 -+#define ixDP_AUX3_DEBUG_G 0x36 -+#define ixDP_AUX3_DEBUG_H 0x37 -+#define ixDP_AUX3_DEBUG_I 0x38 -+#define ixDP_AUX3_DEBUG_J 0x39 -+#define ixDP_AUX3_DEBUG_K 0x3a -+#define ixDP_AUX3_DEBUG_L 0x3b -+#define ixDP_AUX3_DEBUG_M 0x3c -+#define ixDP_AUX3_DEBUG_N 0x3d -+#define ixDP_AUX3_DEBUG_O 0x3e -+#define ixDP_AUX3_DEBUG_P 0x3f -+#define ixDP_AUX3_DEBUG_Q 0x92 -+#define ixDP_AUX4_DEBUG_A 0x40 -+#define ixDP_AUX4_DEBUG_B 0x41 -+#define ixDP_AUX4_DEBUG_C 0x42 -+#define ixDP_AUX4_DEBUG_D 0x43 -+#define ixDP_AUX4_DEBUG_E 0x44 -+#define ixDP_AUX4_DEBUG_F 0x45 -+#define ixDP_AUX4_DEBUG_G 0x46 -+#define ixDP_AUX4_DEBUG_H 0x47 -+#define ixDP_AUX4_DEBUG_I 0x48 -+#define ixDP_AUX4_DEBUG_J 0x49 -+#define ixDP_AUX4_DEBUG_K 0x4a -+#define ixDP_AUX4_DEBUG_L 0x4b -+#define ixDP_AUX4_DEBUG_M 0x4c -+#define ixDP_AUX4_DEBUG_N 0x4d -+#define ixDP_AUX4_DEBUG_O 0x4e -+#define ixDP_AUX4_DEBUG_P 0x4f -+#define ixDP_AUX4_DEBUG_Q 0x93 -+#define ixDP_AUX5_DEBUG_A 0x70 -+#define ixDP_AUX5_DEBUG_B 0x71 -+#define ixDP_AUX5_DEBUG_C 0x72 -+#define ixDP_AUX5_DEBUG_D 0x73 -+#define ixDP_AUX5_DEBUG_E 0x74 -+#define ixDP_AUX5_DEBUG_F 0x75 -+#define ixDP_AUX5_DEBUG_G 0x76 -+#define ixDP_AUX5_DEBUG_H 0x77 -+#define ixDP_AUX5_DEBUG_I 0x78 -+#define ixDP_AUX5_DEBUG_J 0x79 -+#define ixDP_AUX5_DEBUG_K 0x7a -+#define ixDP_AUX5_DEBUG_L 0x7b -+#define ixDP_AUX5_DEBUG_M 0x7c -+#define ixDP_AUX5_DEBUG_N 0x7d -+#define ixDP_AUX5_DEBUG_O 0x7f -+#define ixDP_AUX5_DEBUG_P 0x94 -+#define ixDP_AUX5_DEBUG_Q 0x95 -+#define ixDP_AUX6_DEBUG_A 0x80 -+#define ixDP_AUX6_DEBUG_B 0x81 -+#define ixDP_AUX6_DEBUG_C 0x82 -+#define ixDP_AUX6_DEBUG_D 0x83 -+#define ixDP_AUX6_DEBUG_E 0x84 -+#define ixDP_AUX6_DEBUG_F 0x85 -+#define ixDP_AUX6_DEBUG_G 0x86 -+#define ixDP_AUX6_DEBUG_H 0x87 -+#define ixDP_AUX6_DEBUG_I 0x88 -+#define ixDP_AUX6_DEBUG_J 0x89 -+#define ixDP_AUX6_DEBUG_K 0x8a -+#define ixDP_AUX6_DEBUG_L 0x8b -+#define ixDP_AUX6_DEBUG_M 0x8c -+#define ixDP_AUX6_DEBUG_N 0x8d -+#define ixDP_AUX6_DEBUG_O 0x8f -+#define ixDP_AUX6_DEBUG_P 0x96 -+#define ixDP_AUX6_DEBUG_Q 0x97 -+#define mmDMCU_CTRL 0x1600 -+#define mmDMCU_STATUS 0x1601 -+#define mmDMCU_PC_START_ADDR 0x1602 -+#define mmDMCU_FW_START_ADDR 0x1603 -+#define mmDMCU_FW_END_ADDR 0x1604 -+#define mmDMCU_FW_ISR_START_ADDR 0x1605 -+#define mmDMCU_FW_CS_HI 0x1606 -+#define mmDMCU_FW_CS_LO 0x1607 -+#define mmDMCU_RAM_ACCESS_CTRL 0x1608 -+#define mmDMCU_ERAM_WR_CTRL 0x1609 -+#define mmDMCU_ERAM_WR_DATA 0x160a -+#define mmDMCU_ERAM_RD_CTRL 0x160b -+#define mmDMCU_ERAM_RD_DATA 0x160c -+#define mmDMCU_IRAM_WR_CTRL 0x160d -+#define mmDMCU_IRAM_WR_DATA 0x160e -+#define mmDMCU_IRAM_RD_CTRL 0x160f -+#define mmDMCU_IRAM_RD_DATA 0x1610 -+#define mmDMCU_EVENT_TRIGGER 0x1611 -+#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 -+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 -+#define mmDMCU_INTERRUPT_STATUS 0x1614 -+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 -+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 -+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 -+#define mmDC_DMCU_SCRATCH 0x1618 -+#define mmDMCU_INT_CNT 0x1619 -+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a -+#define mmDMCU_UC_CLK_GATING_CNTL 0x161b -+#define mmMASTER_COMM_DATA_REG1 0x161c -+#define mmMASTER_COMM_DATA_REG2 0x161d -+#define mmMASTER_COMM_DATA_REG3 0x161e -+#define mmMASTER_COMM_CMD_REG 0x161f -+#define mmMASTER_COMM_CNTL_REG 0x1620 -+#define mmSLAVE_COMM_DATA_REG1 0x1621 -+#define mmSLAVE_COMM_DATA_REG2 0x1622 -+#define mmSLAVE_COMM_DATA_REG3 0x1623 -+#define mmSLAVE_COMM_CMD_REG 0x1624 -+#define mmSLAVE_COMM_CNTL_REG 0x1625 -+#define mmDMCU_TEST_DEBUG_INDEX 0x1626 -+#define mmDMCU_TEST_DEBUG_DATA 0x1627 -+#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750 -+#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751 -+#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752 -+#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753 -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754 -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755 -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756 -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757 -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758 -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759 -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a -+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b -+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c -+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d -+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e -+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f -+#define mmDP_LINK_CNTL 0x1cc0 -+#define mmDP0_DP_LINK_CNTL 0x1cc0 -+#define mmDP1_DP_LINK_CNTL 0x1fc0 -+#define mmDP2_DP_LINK_CNTL 0x42c0 -+#define mmDP3_DP_LINK_CNTL 0x45c0 -+#define mmDP4_DP_LINK_CNTL 0x48c0 -+#define mmDP5_DP_LINK_CNTL 0x4bc0 -+#define mmDP6_DP_LINK_CNTL 0x4ec0 -+#define mmDP_PIXEL_FORMAT 0x1cc1 -+#define mmDP0_DP_PIXEL_FORMAT 0x1cc1 -+#define mmDP1_DP_PIXEL_FORMAT 0x1fc1 -+#define mmDP2_DP_PIXEL_FORMAT 0x42c1 -+#define mmDP3_DP_PIXEL_FORMAT 0x45c1 -+#define mmDP4_DP_PIXEL_FORMAT 0x48c1 -+#define mmDP5_DP_PIXEL_FORMAT 0x4bc1 -+#define mmDP6_DP_PIXEL_FORMAT 0x4ec1 -+#define mmDP_MSA_COLORIMETRY 0x1cda -+#define mmDP0_DP_MSA_COLORIMETRY 0x1cda -+#define mmDP1_DP_MSA_COLORIMETRY 0x1fda -+#define mmDP2_DP_MSA_COLORIMETRY 0x42da -+#define mmDP3_DP_MSA_COLORIMETRY 0x45da -+#define mmDP4_DP_MSA_COLORIMETRY 0x48da -+#define mmDP5_DP_MSA_COLORIMETRY 0x4bda -+#define mmDP6_DP_MSA_COLORIMETRY 0x4eda -+#define mmDP_CONFIG 0x1cc2 -+#define mmDP0_DP_CONFIG 0x1cc2 -+#define mmDP1_DP_CONFIG 0x1fc2 -+#define mmDP2_DP_CONFIG 0x42c2 -+#define mmDP3_DP_CONFIG 0x45c2 -+#define mmDP4_DP_CONFIG 0x48c2 -+#define mmDP5_DP_CONFIG 0x4bc2 -+#define mmDP6_DP_CONFIG 0x4ec2 -+#define mmDP_VID_STREAM_CNTL 0x1cc3 -+#define mmDP0_DP_VID_STREAM_CNTL 0x1cc3 -+#define mmDP1_DP_VID_STREAM_CNTL 0x1fc3 -+#define mmDP2_DP_VID_STREAM_CNTL 0x42c3 -+#define mmDP3_DP_VID_STREAM_CNTL 0x45c3 -+#define mmDP4_DP_VID_STREAM_CNTL 0x48c3 -+#define mmDP5_DP_VID_STREAM_CNTL 0x4bc3 -+#define mmDP6_DP_VID_STREAM_CNTL 0x4ec3 -+#define mmDP_STEER_FIFO 0x1cc4 -+#define mmDP0_DP_STEER_FIFO 0x1cc4 -+#define mmDP1_DP_STEER_FIFO 0x1fc4 -+#define mmDP2_DP_STEER_FIFO 0x42c4 -+#define mmDP3_DP_STEER_FIFO 0x45c4 -+#define mmDP4_DP_STEER_FIFO 0x48c4 -+#define mmDP5_DP_STEER_FIFO 0x4bc4 -+#define mmDP6_DP_STEER_FIFO 0x4ec4 -+#define mmDP_MSA_MISC 0x1cc5 -+#define mmDP0_DP_MSA_MISC 0x1cc5 -+#define mmDP1_DP_MSA_MISC 0x1fc5 -+#define mmDP2_DP_MSA_MISC 0x42c5 -+#define mmDP3_DP_MSA_MISC 0x45c5 -+#define mmDP4_DP_MSA_MISC 0x48c5 -+#define mmDP5_DP_MSA_MISC 0x4bc5 -+#define mmDP6_DP_MSA_MISC 0x4ec5 -+#define mmDP_VID_TIMING 0x1cc9 -+#define mmDP0_DP_VID_TIMING 0x1cc9 -+#define mmDP1_DP_VID_TIMING 0x1fc9 -+#define mmDP2_DP_VID_TIMING 0x42c9 -+#define mmDP3_DP_VID_TIMING 0x45c9 -+#define mmDP4_DP_VID_TIMING 0x48c9 -+#define mmDP5_DP_VID_TIMING 0x4bc9 -+#define mmDP6_DP_VID_TIMING 0x4ec9 -+#define mmDP_VID_N 0x1cca -+#define mmDP0_DP_VID_N 0x1cca -+#define mmDP1_DP_VID_N 0x1fca -+#define mmDP2_DP_VID_N 0x42ca -+#define mmDP3_DP_VID_N 0x45ca -+#define mmDP4_DP_VID_N 0x48ca -+#define mmDP5_DP_VID_N 0x4bca -+#define mmDP6_DP_VID_N 0x4eca -+#define mmDP_VID_M 0x1ccb -+#define mmDP0_DP_VID_M 0x1ccb -+#define mmDP1_DP_VID_M 0x1fcb -+#define mmDP2_DP_VID_M 0x42cb -+#define mmDP3_DP_VID_M 0x45cb -+#define mmDP4_DP_VID_M 0x48cb -+#define mmDP5_DP_VID_M 0x4bcb -+#define mmDP6_DP_VID_M 0x4ecb -+#define mmDP_LINK_FRAMING_CNTL 0x1ccc -+#define mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc -+#define mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc -+#define mmDP2_DP_LINK_FRAMING_CNTL 0x42cc -+#define mmDP3_DP_LINK_FRAMING_CNTL 0x45cc -+#define mmDP4_DP_LINK_FRAMING_CNTL 0x48cc -+#define mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc -+#define mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc -+#define mmDP_HBR2_EYE_PATTERN 0x1cc8 -+#define mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8 -+#define mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8 -+#define mmDP2_DP_HBR2_EYE_PATTERN 0x42c8 -+#define mmDP3_DP_HBR2_EYE_PATTERN 0x45c8 -+#define mmDP4_DP_HBR2_EYE_PATTERN 0x48c8 -+#define mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8 -+#define mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8 -+#define mmDP_VID_MSA_VBID 0x1ccd -+#define mmDP0_DP_VID_MSA_VBID 0x1ccd -+#define mmDP1_DP_VID_MSA_VBID 0x1fcd -+#define mmDP2_DP_VID_MSA_VBID 0x42cd -+#define mmDP3_DP_VID_MSA_VBID 0x45cd -+#define mmDP4_DP_VID_MSA_VBID 0x48cd -+#define mmDP5_DP_VID_MSA_VBID 0x4bcd -+#define mmDP6_DP_VID_MSA_VBID 0x4ecd -+#define mmDP_VID_INTERRUPT_CNTL 0x1ccf -+#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf -+#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf -+#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf -+#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf -+#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf -+#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf -+#define mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf -+#define mmDP_DPHY_CNTL 0x1cd0 -+#define mmDP0_DP_DPHY_CNTL 0x1cd0 -+#define mmDP1_DP_DPHY_CNTL 0x1fd0 -+#define mmDP2_DP_DPHY_CNTL 0x42d0 -+#define mmDP3_DP_DPHY_CNTL 0x45d0 -+#define mmDP4_DP_DPHY_CNTL 0x48d0 -+#define mmDP5_DP_DPHY_CNTL 0x4bd0 -+#define mmDP6_DP_DPHY_CNTL 0x4ed0 -+#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 -+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 -+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1 -+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1 -+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1 -+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1 -+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1 -+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1 -+#define mmDP_DPHY_SYM0 0x1cd2 -+#define mmDP0_DP_DPHY_SYM0 0x1cd2 -+#define mmDP1_DP_DPHY_SYM0 0x1fd2 -+#define mmDP2_DP_DPHY_SYM0 0x42d2 -+#define mmDP3_DP_DPHY_SYM0 0x45d2 -+#define mmDP4_DP_DPHY_SYM0 0x48d2 -+#define mmDP5_DP_DPHY_SYM0 0x4bd2 -+#define mmDP6_DP_DPHY_SYM0 0x4ed2 -+#define mmDP_DPHY_SYM1 0x1ce0 -+#define mmDP0_DP_DPHY_SYM1 0x1ce0 -+#define mmDP1_DP_DPHY_SYM1 0x1fe0 -+#define mmDP2_DP_DPHY_SYM1 0x42e0 -+#define mmDP3_DP_DPHY_SYM1 0x45e0 -+#define mmDP4_DP_DPHY_SYM1 0x48e0 -+#define mmDP5_DP_DPHY_SYM1 0x4be0 -+#define mmDP6_DP_DPHY_SYM1 0x4ee0 -+#define mmDP_DPHY_SYM2 0x1cdf -+#define mmDP0_DP_DPHY_SYM2 0x1cdf -+#define mmDP1_DP_DPHY_SYM2 0x1fdf -+#define mmDP2_DP_DPHY_SYM2 0x42df -+#define mmDP3_DP_DPHY_SYM2 0x45df -+#define mmDP4_DP_DPHY_SYM2 0x48df -+#define mmDP5_DP_DPHY_SYM2 0x4bdf -+#define mmDP6_DP_DPHY_SYM2 0x4edf -+#define mmDP_DPHY_8B10B_CNTL 0x1cd3 -+#define mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3 -+#define mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3 -+#define mmDP2_DP_DPHY_8B10B_CNTL 0x42d3 -+#define mmDP3_DP_DPHY_8B10B_CNTL 0x45d3 -+#define mmDP4_DP_DPHY_8B10B_CNTL 0x48d3 -+#define mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3 -+#define mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3 -+#define mmDP_DPHY_PRBS_CNTL 0x1cd4 -+#define mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4 -+#define mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4 -+#define mmDP2_DP_DPHY_PRBS_CNTL 0x42d4 -+#define mmDP3_DP_DPHY_PRBS_CNTL 0x45d4 -+#define mmDP4_DP_DPHY_PRBS_CNTL 0x48d4 -+#define mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4 -+#define mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4 -+#define mmDP_DPHY_CRC_EN 0x1cd6 -+#define mmDP0_DP_DPHY_CRC_EN 0x1cd6 -+#define mmDP1_DP_DPHY_CRC_EN 0x1fd6 -+#define mmDP2_DP_DPHY_CRC_EN 0x42d6 -+#define mmDP3_DP_DPHY_CRC_EN 0x45d6 -+#define mmDP4_DP_DPHY_CRC_EN 0x48d6 -+#define mmDP5_DP_DPHY_CRC_EN 0x4bd6 -+#define mmDP6_DP_DPHY_CRC_EN 0x4ed6 -+#define mmDP_DPHY_CRC_CNTL 0x1cd7 -+#define mmDP0_DP_DPHY_CRC_CNTL 0x1cd7 -+#define mmDP1_DP_DPHY_CRC_CNTL 0x1fd7 -+#define mmDP2_DP_DPHY_CRC_CNTL 0x42d7 -+#define mmDP3_DP_DPHY_CRC_CNTL 0x45d7 -+#define mmDP4_DP_DPHY_CRC_CNTL 0x48d7 -+#define mmDP5_DP_DPHY_CRC_CNTL 0x4bd7 -+#define mmDP6_DP_DPHY_CRC_CNTL 0x4ed7 -+#define mmDP_DPHY_CRC_RESULT 0x1cd8 -+#define mmDP0_DP_DPHY_CRC_RESULT 0x1cd8 -+#define mmDP1_DP_DPHY_CRC_RESULT 0x1fd8 -+#define mmDP2_DP_DPHY_CRC_RESULT 0x42d8 -+#define mmDP3_DP_DPHY_CRC_RESULT 0x45d8 -+#define mmDP4_DP_DPHY_CRC_RESULT 0x48d8 -+#define mmDP5_DP_DPHY_CRC_RESULT 0x4bd8 -+#define mmDP6_DP_DPHY_CRC_RESULT 0x4ed8 -+#define mmDP_DPHY_CRC_MST_CNTL 0x1cc6 -+#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6 -+#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6 -+#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6 -+#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6 -+#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6 -+#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6 -+#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6 -+#define mmDP_DPHY_CRC_MST_STATUS 0x1cc7 -+#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7 -+#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7 -+#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7 -+#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7 -+#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7 -+#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7 -+#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7 -+#define mmDP_DPHY_FAST_TRAINING 0x1cce -+#define mmDP0_DP_DPHY_FAST_TRAINING 0x1cce -+#define mmDP1_DP_DPHY_FAST_TRAINING 0x1fce -+#define mmDP2_DP_DPHY_FAST_TRAINING 0x42ce -+#define mmDP3_DP_DPHY_FAST_TRAINING 0x45ce -+#define mmDP4_DP_DPHY_FAST_TRAINING 0x48ce -+#define mmDP5_DP_DPHY_FAST_TRAINING 0x4bce -+#define mmDP6_DP_DPHY_FAST_TRAINING 0x4ece -+#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9 -+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9 -+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9 -+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9 -+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9 -+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9 -+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9 -+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9 -+#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea -+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea -+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea -+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea -+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea -+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea -+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea -+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea -+#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb -+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb -+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb -+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb -+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb -+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb -+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb -+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb -+#define mmDP_SEC_CNTL 0x1ca0 -+#define mmDP0_DP_SEC_CNTL 0x1ca0 -+#define mmDP1_DP_SEC_CNTL 0x1fa0 -+#define mmDP2_DP_SEC_CNTL 0x42a0 -+#define mmDP3_DP_SEC_CNTL 0x45a0 -+#define mmDP4_DP_SEC_CNTL 0x48a0 -+#define mmDP5_DP_SEC_CNTL 0x4ba0 -+#define mmDP6_DP_SEC_CNTL 0x4ea0 -+#define mmDP_SEC_CNTL1 0x1cab -+#define mmDP0_DP_SEC_CNTL1 0x1cab -+#define mmDP1_DP_SEC_CNTL1 0x1fab -+#define mmDP2_DP_SEC_CNTL1 0x42ab -+#define mmDP3_DP_SEC_CNTL1 0x45ab -+#define mmDP4_DP_SEC_CNTL1 0x48ab -+#define mmDP5_DP_SEC_CNTL1 0x4bab -+#define mmDP6_DP_SEC_CNTL1 0x4eab -+#define mmDP_SEC_FRAMING1 0x1ca1 -+#define mmDP0_DP_SEC_FRAMING1 0x1ca1 -+#define mmDP1_DP_SEC_FRAMING1 0x1fa1 -+#define mmDP2_DP_SEC_FRAMING1 0x42a1 -+#define mmDP3_DP_SEC_FRAMING1 0x45a1 -+#define mmDP4_DP_SEC_FRAMING1 0x48a1 -+#define mmDP5_DP_SEC_FRAMING1 0x4ba1 -+#define mmDP6_DP_SEC_FRAMING1 0x4ea1 -+#define mmDP_SEC_FRAMING2 0x1ca2 -+#define mmDP0_DP_SEC_FRAMING2 0x1ca2 -+#define mmDP1_DP_SEC_FRAMING2 0x1fa2 -+#define mmDP2_DP_SEC_FRAMING2 0x42a2 -+#define mmDP3_DP_SEC_FRAMING2 0x45a2 -+#define mmDP4_DP_SEC_FRAMING2 0x48a2 -+#define mmDP5_DP_SEC_FRAMING2 0x4ba2 -+#define mmDP6_DP_SEC_FRAMING2 0x4ea2 -+#define mmDP_SEC_FRAMING3 0x1ca3 -+#define mmDP0_DP_SEC_FRAMING3 0x1ca3 -+#define mmDP1_DP_SEC_FRAMING3 0x1fa3 -+#define mmDP2_DP_SEC_FRAMING3 0x42a3 -+#define mmDP3_DP_SEC_FRAMING3 0x45a3 -+#define mmDP4_DP_SEC_FRAMING3 0x48a3 -+#define mmDP5_DP_SEC_FRAMING3 0x4ba3 -+#define mmDP6_DP_SEC_FRAMING3 0x4ea3 -+#define mmDP_SEC_FRAMING4 0x1ca4 -+#define mmDP0_DP_SEC_FRAMING4 0x1ca4 -+#define mmDP1_DP_SEC_FRAMING4 0x1fa4 -+#define mmDP2_DP_SEC_FRAMING4 0x42a4 -+#define mmDP3_DP_SEC_FRAMING4 0x45a4 -+#define mmDP4_DP_SEC_FRAMING4 0x48a4 -+#define mmDP5_DP_SEC_FRAMING4 0x4ba4 -+#define mmDP6_DP_SEC_FRAMING4 0x4ea4 -+#define mmDP_SEC_AUD_N 0x1ca5 -+#define mmDP0_DP_SEC_AUD_N 0x1ca5 -+#define mmDP1_DP_SEC_AUD_N 0x1fa5 -+#define mmDP2_DP_SEC_AUD_N 0x42a5 -+#define mmDP3_DP_SEC_AUD_N 0x45a5 -+#define mmDP4_DP_SEC_AUD_N 0x48a5 -+#define mmDP5_DP_SEC_AUD_N 0x4ba5 -+#define mmDP6_DP_SEC_AUD_N 0x4ea5 -+#define mmDP_SEC_AUD_N_READBACK 0x1ca6 -+#define mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6 -+#define mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6 -+#define mmDP2_DP_SEC_AUD_N_READBACK 0x42a6 -+#define mmDP3_DP_SEC_AUD_N_READBACK 0x45a6 -+#define mmDP4_DP_SEC_AUD_N_READBACK 0x48a6 -+#define mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6 -+#define mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6 -+#define mmDP_SEC_AUD_M 0x1ca7 -+#define mmDP0_DP_SEC_AUD_M 0x1ca7 -+#define mmDP1_DP_SEC_AUD_M 0x1fa7 -+#define mmDP2_DP_SEC_AUD_M 0x42a7 -+#define mmDP3_DP_SEC_AUD_M 0x45a7 -+#define mmDP4_DP_SEC_AUD_M 0x48a7 -+#define mmDP5_DP_SEC_AUD_M 0x4ba7 -+#define mmDP6_DP_SEC_AUD_M 0x4ea7 -+#define mmDP_SEC_AUD_M_READBACK 0x1ca8 -+#define mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8 -+#define mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8 -+#define mmDP2_DP_SEC_AUD_M_READBACK 0x42a8 -+#define mmDP3_DP_SEC_AUD_M_READBACK 0x45a8 -+#define mmDP4_DP_SEC_AUD_M_READBACK 0x48a8 -+#define mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8 -+#define mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8 -+#define mmDP_SEC_TIMESTAMP 0x1ca9 -+#define mmDP0_DP_SEC_TIMESTAMP 0x1ca9 -+#define mmDP1_DP_SEC_TIMESTAMP 0x1fa9 -+#define mmDP2_DP_SEC_TIMESTAMP 0x42a9 -+#define mmDP3_DP_SEC_TIMESTAMP 0x45a9 -+#define mmDP4_DP_SEC_TIMESTAMP 0x48a9 -+#define mmDP5_DP_SEC_TIMESTAMP 0x4ba9 -+#define mmDP6_DP_SEC_TIMESTAMP 0x4ea9 -+#define mmDP_SEC_PACKET_CNTL 0x1caa -+#define mmDP0_DP_SEC_PACKET_CNTL 0x1caa -+#define mmDP1_DP_SEC_PACKET_CNTL 0x1faa -+#define mmDP2_DP_SEC_PACKET_CNTL 0x42aa -+#define mmDP3_DP_SEC_PACKET_CNTL 0x45aa -+#define mmDP4_DP_SEC_PACKET_CNTL 0x48aa -+#define mmDP5_DP_SEC_PACKET_CNTL 0x4baa -+#define mmDP6_DP_SEC_PACKET_CNTL 0x4eaa -+#define mmDP_MSE_RATE_CNTL 0x1ce1 -+#define mmDP0_DP_MSE_RATE_CNTL 0x1ce1 -+#define mmDP1_DP_MSE_RATE_CNTL 0x1fe1 -+#define mmDP2_DP_MSE_RATE_CNTL 0x42e1 -+#define mmDP3_DP_MSE_RATE_CNTL 0x45e1 -+#define mmDP4_DP_MSE_RATE_CNTL 0x48e1 -+#define mmDP5_DP_MSE_RATE_CNTL 0x4be1 -+#define mmDP6_DP_MSE_RATE_CNTL 0x4ee1 -+#define mmDP_MSE_RATE_UPDATE 0x1ce3 -+#define mmDP0_DP_MSE_RATE_UPDATE 0x1ce3 -+#define mmDP1_DP_MSE_RATE_UPDATE 0x1fe3 -+#define mmDP2_DP_MSE_RATE_UPDATE 0x42e3 -+#define mmDP3_DP_MSE_RATE_UPDATE 0x45e3 -+#define mmDP4_DP_MSE_RATE_UPDATE 0x48e3 -+#define mmDP5_DP_MSE_RATE_UPDATE 0x4be3 -+#define mmDP6_DP_MSE_RATE_UPDATE 0x4ee3 -+#define mmDP_MSE_SAT0 0x1ce4 -+#define mmDP0_DP_MSE_SAT0 0x1ce4 -+#define mmDP1_DP_MSE_SAT0 0x1fe4 -+#define mmDP2_DP_MSE_SAT0 0x42e4 -+#define mmDP3_DP_MSE_SAT0 0x45e4 -+#define mmDP4_DP_MSE_SAT0 0x48e4 -+#define mmDP5_DP_MSE_SAT0 0x4be4 -+#define mmDP6_DP_MSE_SAT0 0x4ee4 -+#define mmDP_MSE_SAT1 0x1ce5 -+#define mmDP0_DP_MSE_SAT1 0x1ce5 -+#define mmDP1_DP_MSE_SAT1 0x1fe5 -+#define mmDP2_DP_MSE_SAT1 0x42e5 -+#define mmDP3_DP_MSE_SAT1 0x45e5 -+#define mmDP4_DP_MSE_SAT1 0x48e5 -+#define mmDP5_DP_MSE_SAT1 0x4be5 -+#define mmDP6_DP_MSE_SAT1 0x4ee5 -+#define mmDP_MSE_SAT2 0x1ce6 -+#define mmDP0_DP_MSE_SAT2 0x1ce6 -+#define mmDP1_DP_MSE_SAT2 0x1fe6 -+#define mmDP2_DP_MSE_SAT2 0x42e6 -+#define mmDP3_DP_MSE_SAT2 0x45e6 -+#define mmDP4_DP_MSE_SAT2 0x48e6 -+#define mmDP5_DP_MSE_SAT2 0x4be6 -+#define mmDP6_DP_MSE_SAT2 0x4ee6 -+#define mmDP_MSE_SAT_UPDATE 0x1ce7 -+#define mmDP0_DP_MSE_SAT_UPDATE 0x1ce7 -+#define mmDP1_DP_MSE_SAT_UPDATE 0x1fe7 -+#define mmDP2_DP_MSE_SAT_UPDATE 0x42e7 -+#define mmDP3_DP_MSE_SAT_UPDATE 0x45e7 -+#define mmDP4_DP_MSE_SAT_UPDATE 0x48e7 -+#define mmDP5_DP_MSE_SAT_UPDATE 0x4be7 -+#define mmDP6_DP_MSE_SAT_UPDATE 0x4ee7 -+#define mmDP_MSE_LINK_TIMING 0x1ce8 -+#define mmDP0_DP_MSE_LINK_TIMING 0x1ce8 -+#define mmDP1_DP_MSE_LINK_TIMING 0x1fe8 -+#define mmDP2_DP_MSE_LINK_TIMING 0x42e8 -+#define mmDP3_DP_MSE_LINK_TIMING 0x45e8 -+#define mmDP4_DP_MSE_LINK_TIMING 0x48e8 -+#define mmDP5_DP_MSE_LINK_TIMING 0x4be8 -+#define mmDP6_DP_MSE_LINK_TIMING 0x4ee8 -+#define mmDP_MSE_MISC_CNTL 0x1cdb -+#define mmDP0_DP_MSE_MISC_CNTL 0x1cdb -+#define mmDP1_DP_MSE_MISC_CNTL 0x1fdb -+#define mmDP2_DP_MSE_MISC_CNTL 0x42db -+#define mmDP3_DP_MSE_MISC_CNTL 0x45db -+#define mmDP4_DP_MSE_MISC_CNTL 0x48db -+#define mmDP5_DP_MSE_MISC_CNTL 0x4bdb -+#define mmDP6_DP_MSE_MISC_CNTL 0x4edb -+#define mmDP_TEST_DEBUG_INDEX 0x1cfc -+#define mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc -+#define mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc -+#define mmDP2_DP_TEST_DEBUG_INDEX 0x42fc -+#define mmDP3_DP_TEST_DEBUG_INDEX 0x45fc -+#define mmDP4_DP_TEST_DEBUG_INDEX 0x48fc -+#define mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc -+#define mmDP6_DP_TEST_DEBUG_INDEX 0x4efc -+#define mmDP_TEST_DEBUG_DATA 0x1cfd -+#define mmDP0_DP_TEST_DEBUG_DATA 0x1cfd -+#define mmDP1_DP_TEST_DEBUG_DATA 0x1ffd -+#define mmDP2_DP_TEST_DEBUG_DATA 0x42fd -+#define mmDP3_DP_TEST_DEBUG_DATA 0x45fd -+#define mmDP4_DP_TEST_DEBUG_DATA 0x48fd -+#define mmDP5_DP_TEST_DEBUG_DATA 0x4bfd -+#define mmDP6_DP_TEST_DEBUG_DATA 0x4efd -+#define mmAUX_CONTROL 0x1880 -+#define mmDP_AUX0_AUX_CONTROL 0x1880 -+#define mmDP_AUX1_AUX_CONTROL 0x1894 -+#define mmDP_AUX2_AUX_CONTROL 0x18a8 -+#define mmDP_AUX3_AUX_CONTROL 0x18c0 -+#define mmDP_AUX4_AUX_CONTROL 0x18d4 -+#define mmDP_AUX5_AUX_CONTROL 0x18e8 -+#define mmAUX_SW_CONTROL 0x1881 -+#define mmDP_AUX0_AUX_SW_CONTROL 0x1881 -+#define mmDP_AUX1_AUX_SW_CONTROL 0x1895 -+#define mmDP_AUX2_AUX_SW_CONTROL 0x18a9 -+#define mmDP_AUX3_AUX_SW_CONTROL 0x18c1 -+#define mmDP_AUX4_AUX_SW_CONTROL 0x18d5 -+#define mmDP_AUX5_AUX_SW_CONTROL 0x18e9 -+#define mmAUX_ARB_CONTROL 0x1882 -+#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 -+#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 -+#define mmDP_AUX2_AUX_ARB_CONTROL 0x18aa -+#define mmDP_AUX3_AUX_ARB_CONTROL 0x18c2 -+#define mmDP_AUX4_AUX_ARB_CONTROL 0x18d6 -+#define mmDP_AUX5_AUX_ARB_CONTROL 0x18ea -+#define mmAUX_INTERRUPT_CONTROL 0x1883 -+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 -+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 -+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab -+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3 -+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7 -+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb -+#define mmAUX_SW_STATUS 0x1884 -+#define mmDP_AUX0_AUX_SW_STATUS 0x1884 -+#define mmDP_AUX1_AUX_SW_STATUS 0x1898 -+#define mmDP_AUX2_AUX_SW_STATUS 0x18ac -+#define mmDP_AUX3_AUX_SW_STATUS 0x18c4 -+#define mmDP_AUX4_AUX_SW_STATUS 0x18d8 -+#define mmDP_AUX5_AUX_SW_STATUS 0x18ec -+#define mmAUX_LS_STATUS 0x1885 -+#define mmDP_AUX0_AUX_LS_STATUS 0x1885 -+#define mmDP_AUX1_AUX_LS_STATUS 0x1899 -+#define mmDP_AUX2_AUX_LS_STATUS 0x18ad -+#define mmDP_AUX3_AUX_LS_STATUS 0x18c5 -+#define mmDP_AUX4_AUX_LS_STATUS 0x18d9 -+#define mmDP_AUX5_AUX_LS_STATUS 0x18ed -+#define mmAUX_SW_DATA 0x1886 -+#define mmDP_AUX0_AUX_SW_DATA 0x1886 -+#define mmDP_AUX1_AUX_SW_DATA 0x189a -+#define mmDP_AUX2_AUX_SW_DATA 0x18ae -+#define mmDP_AUX3_AUX_SW_DATA 0x18c6 -+#define mmDP_AUX4_AUX_SW_DATA 0x18da -+#define mmDP_AUX5_AUX_SW_DATA 0x18ee -+#define mmAUX_LS_DATA 0x1887 -+#define mmDP_AUX0_AUX_LS_DATA 0x1887 -+#define mmDP_AUX1_AUX_LS_DATA 0x189b -+#define mmDP_AUX2_AUX_LS_DATA 0x18af -+#define mmDP_AUX3_AUX_LS_DATA 0x18c7 -+#define mmDP_AUX4_AUX_LS_DATA 0x18db -+#define mmDP_AUX5_AUX_LS_DATA 0x18ef -+#define mmAUX_DPHY_TX_REF_CONTROL 0x1888 -+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 -+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c -+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0 -+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8 -+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc -+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0 -+#define mmAUX_DPHY_TX_CONTROL 0x1889 -+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 -+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d -+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1 -+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9 -+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd -+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1 -+#define mmAUX_DPHY_RX_CONTROL0 0x188a -+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a -+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e -+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2 -+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca -+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de -+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2 -+#define mmAUX_DPHY_RX_CONTROL1 0x188b -+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b -+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f -+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3 -+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb -+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df -+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3 -+#define mmAUX_DPHY_TX_STATUS 0x188c -+#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c -+#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0 -+#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4 -+#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc -+#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0 -+#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4 -+#define mmAUX_DPHY_RX_STATUS 0x188d -+#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d -+#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1 -+#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5 -+#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd -+#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1 -+#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5 -+#define mmAUX_GTC_SYNC_CONTROL 0x188e -+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e -+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2 -+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6 -+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce -+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2 -+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6 -+#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f -+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f -+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3 -+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7 -+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf -+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3 -+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7 -+#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 -+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 -+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4 -+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8 -+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0 -+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4 -+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8 -+#define mmAUX_GTC_SYNC_STATUS 0x1891 -+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891 -+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5 -+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9 -+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1 -+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5 -+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9 -+#define mmAUX_GTC_SYNC_DATA 0x1892 -+#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892 -+#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6 -+#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba -+#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2 -+#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6 -+#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa -+#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 -+#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 -+#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7 -+#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb -+#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3 -+#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7 -+#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb -+#define mmDVO_ENABLE 0x1858 -+#define mmDVO_SOURCE_SELECT 0x1859 -+#define mmDVO_OUTPUT 0x185a -+#define mmDVO_CONTROL 0x185b -+#define mmDVO_CRC_EN 0x185c -+#define mmDVO_CRC2_SIG_MASK 0x185d -+#define mmDVO_CRC2_SIG_RESULT 0x185e -+#define mmDVO_FIFO_ERROR_STATUS 0x185f -+#define mmFBC_CNTL 0x16d0 -+#define mmFBC_IDLE_MASK 0x16d1 -+#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2 -+#define mmFBC_START_STOP_DELAY 0x16d3 -+#define mmFBC_COMP_CNTL 0x16d4 -+#define mmFBC_COMP_MODE 0x16d5 -+#define mmFBC_DEBUG0 0x16d6 -+#define mmFBC_DEBUG1 0x16d7 -+#define mmFBC_DEBUG2 0x16d8 -+#define mmFBC_IND_LUT0 0x16d9 -+#define mmFBC_IND_LUT1 0x16da -+#define mmFBC_IND_LUT2 0x16db -+#define mmFBC_IND_LUT3 0x16dc -+#define mmFBC_IND_LUT4 0x16dd -+#define mmFBC_IND_LUT5 0x16de -+#define mmFBC_IND_LUT6 0x16df -+#define mmFBC_IND_LUT7 0x16e0 -+#define mmFBC_IND_LUT8 0x16e1 -+#define mmFBC_IND_LUT9 0x16e2 -+#define mmFBC_IND_LUT10 0x16e3 -+#define mmFBC_IND_LUT11 0x16e4 -+#define mmFBC_IND_LUT12 0x16e5 -+#define mmFBC_IND_LUT13 0x16e6 -+#define mmFBC_IND_LUT14 0x16e7 -+#define mmFBC_IND_LUT15 0x16e8 -+#define mmFBC_CSM_REGION_OFFSET_01 0x16e9 -+#define mmFBC_CSM_REGION_OFFSET_23 0x16ea -+#define mmFBC_CLIENT_REGION_MASK 0x16eb -+#define mmFBC_DEBUG_COMP 0x16ec -+#define mmFBC_DEBUG_CSR 0x16ed -+#define mmFBC_DEBUG_CSR_RDATA 0x16ee -+#define mmFBC_DEBUG_CSR_WDATA 0x16ef -+#define mmFBC_DEBUG_CSR_RDATA_HI 0x16f6 -+#define mmFBC_DEBUG_CSR_WDATA_HI 0x16f7 -+#define mmFBC_MISC 0x16f0 -+#define mmFBC_STATUS 0x16f1 -+#define mmFBC_TEST_DEBUG_INDEX 0x16f4 -+#define mmFBC_TEST_DEBUG_DATA 0x16f5 -+#define mmFMT_CLAMP_COMPONENT_R 0x1be8 -+#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 -+#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8 -+#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8 -+#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8 -+#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8 -+#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8 -+#define mmFMT_CLAMP_COMPONENT_G 0x1be9 -+#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 -+#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9 -+#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9 -+#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9 -+#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9 -+#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9 -+#define mmFMT_CLAMP_COMPONENT_B 0x1bea -+#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea -+#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea -+#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea -+#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea -+#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea -+#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea -+#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed -+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed -+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed -+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed -+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed -+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed -+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed -+#define mmFMT_CONTROL 0x1bee -+#define mmFMT0_FMT_CONTROL 0x1bee -+#define mmFMT1_FMT_CONTROL 0x1eee -+#define mmFMT2_FMT_CONTROL 0x41ee -+#define mmFMT3_FMT_CONTROL 0x44ee -+#define mmFMT4_FMT_CONTROL 0x47ee -+#define mmFMT5_FMT_CONTROL 0x4aee -+#define mmFMT_FORCE_OUTPUT_CNTL 0x1bef -+#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef -+#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef -+#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef -+#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef -+#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef -+#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef -+#define mmFMT_FORCE_DATA_0_1 0x1bf0 -+#define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 -+#define mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0 -+#define mmFMT2_FMT_FORCE_DATA_0_1 0x41f0 -+#define mmFMT3_FMT_FORCE_DATA_0_1 0x44f0 -+#define mmFMT4_FMT_FORCE_DATA_0_1 0x47f0 -+#define mmFMT5_FMT_FORCE_DATA_0_1 0x4af0 -+#define mmFMT_FORCE_DATA_2_3 0x1bf1 -+#define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 -+#define mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1 -+#define mmFMT2_FMT_FORCE_DATA_2_3 0x41f1 -+#define mmFMT3_FMT_FORCE_DATA_2_3 0x44f1 -+#define mmFMT4_FMT_FORCE_DATA_2_3 0x47f1 -+#define mmFMT5_FMT_FORCE_DATA_2_3 0x4af1 -+#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 -+#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 -+#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2 -+#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2 -+#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2 -+#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2 -+#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2 -+#define mmFMT_DITHER_RAND_R_SEED 0x1bf3 -+#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 -+#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3 -+#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3 -+#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3 -+#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3 -+#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3 -+#define mmFMT_DITHER_RAND_G_SEED 0x1bf4 -+#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 -+#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4 -+#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4 -+#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4 -+#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4 -+#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4 -+#define mmFMT_DITHER_RAND_B_SEED 0x1bf5 -+#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 -+#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5 -+#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5 -+#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5 -+#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5 -+#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5 -+#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -+#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 -+#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6 -+#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 -+#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6 -+#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6 -+#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6 -+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 -+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7 -+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 -+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7 -+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7 -+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7 -+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 -+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8 -+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 -+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8 -+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8 -+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8 -+#define mmFMT_CLAMP_CNTL 0x1bf9 -+#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 -+#define mmFMT1_FMT_CLAMP_CNTL 0x1ef9 -+#define mmFMT2_FMT_CLAMP_CNTL 0x41f9 -+#define mmFMT3_FMT_CLAMP_CNTL 0x44f9 -+#define mmFMT4_FMT_CLAMP_CNTL 0x47f9 -+#define mmFMT5_FMT_CLAMP_CNTL 0x4af9 -+#define mmFMT_CRC_CNTL 0x1bfa -+#define mmFMT0_FMT_CRC_CNTL 0x1bfa -+#define mmFMT1_FMT_CRC_CNTL 0x1efa -+#define mmFMT2_FMT_CRC_CNTL 0x41fa -+#define mmFMT3_FMT_CRC_CNTL 0x44fa -+#define mmFMT4_FMT_CRC_CNTL 0x47fa -+#define mmFMT5_FMT_CRC_CNTL 0x4afa -+#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb -+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb -+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb -+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb -+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb -+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb -+#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc -+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc -+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc -+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc -+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc -+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc -+#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd -+#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd -+#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd -+#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd -+#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd -+#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd -+#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd -+#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe -+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe -+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe -+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe -+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe -+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe -+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe -+#define mmFMT_DEBUG_CNTL 0x1bff -+#define mmFMT0_FMT_DEBUG_CNTL 0x1bff -+#define mmFMT1_FMT_DEBUG_CNTL 0x1eff -+#define mmFMT2_FMT_DEBUG_CNTL 0x41ff -+#define mmFMT3_FMT_DEBUG_CNTL 0x44ff -+#define mmFMT4_FMT_DEBUG_CNTL 0x47ff -+#define mmFMT5_FMT_DEBUG_CNTL 0x4aff -+#define mmFMT_TEST_DEBUG_INDEX 0x1beb -+#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb -+#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb -+#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb -+#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb -+#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb -+#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb -+#define mmFMT_TEST_DEBUG_DATA 0x1bec -+#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec -+#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec -+#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec -+#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec -+#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec -+#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec -+#define ixFMT_DEBUG0 0x1 -+#define ixFMT_DEBUG1 0x2 -+#define ixFMT_DEBUG2 0x3 -+#define ixFMT_DEBUG_ID 0x0 -+#define mmLB_DATA_FORMAT 0x1ac0 -+#define mmLB0_LB_DATA_FORMAT 0x1ac0 -+#define mmLB1_LB_DATA_FORMAT 0x1dc0 -+#define mmLB2_LB_DATA_FORMAT 0x40c0 -+#define mmLB3_LB_DATA_FORMAT 0x43c0 -+#define mmLB4_LB_DATA_FORMAT 0x46c0 -+#define mmLB5_LB_DATA_FORMAT 0x49c0 -+#define mmLB_MEMORY_CTRL 0x1ac1 -+#define mmLB0_LB_MEMORY_CTRL 0x1ac1 -+#define mmLB1_LB_MEMORY_CTRL 0x1dc1 -+#define mmLB2_LB_MEMORY_CTRL 0x40c1 -+#define mmLB3_LB_MEMORY_CTRL 0x43c1 -+#define mmLB4_LB_MEMORY_CTRL 0x46c1 -+#define mmLB5_LB_MEMORY_CTRL 0x49c1 -+#define mmLB_MEMORY_SIZE_STATUS 0x1ac2 -+#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 -+#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2 -+#define mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2 -+#define mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2 -+#define mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2 -+#define mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2 -+#define mmLB_DESKTOP_HEIGHT 0x1ac3 -+#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 -+#define mmLB1_LB_DESKTOP_HEIGHT 0x1dc3 -+#define mmLB2_LB_DESKTOP_HEIGHT 0x40c3 -+#define mmLB3_LB_DESKTOP_HEIGHT 0x43c3 -+#define mmLB4_LB_DESKTOP_HEIGHT 0x46c3 -+#define mmLB5_LB_DESKTOP_HEIGHT 0x49c3 -+#define mmLB_VLINE_START_END 0x1ac4 -+#define mmLB0_LB_VLINE_START_END 0x1ac4 -+#define mmLB1_LB_VLINE_START_END 0x1dc4 -+#define mmLB2_LB_VLINE_START_END 0x40c4 -+#define mmLB3_LB_VLINE_START_END 0x43c4 -+#define mmLB4_LB_VLINE_START_END 0x46c4 -+#define mmLB5_LB_VLINE_START_END 0x49c4 -+#define mmLB_VLINE2_START_END 0x1ac5 -+#define mmLB0_LB_VLINE2_START_END 0x1ac5 -+#define mmLB1_LB_VLINE2_START_END 0x1dc5 -+#define mmLB2_LB_VLINE2_START_END 0x40c5 -+#define mmLB3_LB_VLINE2_START_END 0x43c5 -+#define mmLB4_LB_VLINE2_START_END 0x46c5 -+#define mmLB5_LB_VLINE2_START_END 0x49c5 -+#define mmLB_V_COUNTER 0x1ac6 -+#define mmLB0_LB_V_COUNTER 0x1ac6 -+#define mmLB1_LB_V_COUNTER 0x1dc6 -+#define mmLB2_LB_V_COUNTER 0x40c6 -+#define mmLB3_LB_V_COUNTER 0x43c6 -+#define mmLB4_LB_V_COUNTER 0x46c6 -+#define mmLB5_LB_V_COUNTER 0x49c6 -+#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 -+#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 -+#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7 -+#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7 -+#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7 -+#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7 -+#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7 -+#define mmLB_INTERRUPT_MASK 0x1ac8 -+#define mmLB0_LB_INTERRUPT_MASK 0x1ac8 -+#define mmLB1_LB_INTERRUPT_MASK 0x1dc8 -+#define mmLB2_LB_INTERRUPT_MASK 0x40c8 -+#define mmLB3_LB_INTERRUPT_MASK 0x43c8 -+#define mmLB4_LB_INTERRUPT_MASK 0x46c8 -+#define mmLB5_LB_INTERRUPT_MASK 0x49c8 -+#define mmLB_VLINE_STATUS 0x1ac9 -+#define mmLB0_LB_VLINE_STATUS 0x1ac9 -+#define mmLB1_LB_VLINE_STATUS 0x1dc9 -+#define mmLB2_LB_VLINE_STATUS 0x40c9 -+#define mmLB3_LB_VLINE_STATUS 0x43c9 -+#define mmLB4_LB_VLINE_STATUS 0x46c9 -+#define mmLB5_LB_VLINE_STATUS 0x49c9 -+#define mmLB_VLINE2_STATUS 0x1aca -+#define mmLB0_LB_VLINE2_STATUS 0x1aca -+#define mmLB1_LB_VLINE2_STATUS 0x1dca -+#define mmLB2_LB_VLINE2_STATUS 0x40ca -+#define mmLB3_LB_VLINE2_STATUS 0x43ca -+#define mmLB4_LB_VLINE2_STATUS 0x46ca -+#define mmLB5_LB_VLINE2_STATUS 0x49ca -+#define mmLB_VBLANK_STATUS 0x1acb -+#define mmLB0_LB_VBLANK_STATUS 0x1acb -+#define mmLB1_LB_VBLANK_STATUS 0x1dcb -+#define mmLB2_LB_VBLANK_STATUS 0x40cb -+#define mmLB3_LB_VBLANK_STATUS 0x43cb -+#define mmLB4_LB_VBLANK_STATUS 0x46cb -+#define mmLB5_LB_VBLANK_STATUS 0x49cb -+#define mmLB_SYNC_RESET_SEL 0x1acc -+#define mmLB0_LB_SYNC_RESET_SEL 0x1acc -+#define mmLB1_LB_SYNC_RESET_SEL 0x1dcc -+#define mmLB2_LB_SYNC_RESET_SEL 0x40cc -+#define mmLB3_LB_SYNC_RESET_SEL 0x43cc -+#define mmLB4_LB_SYNC_RESET_SEL 0x46cc -+#define mmLB5_LB_SYNC_RESET_SEL 0x49cc -+#define mmLB_BLACK_KEYER_R_CR 0x1acd -+#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd -+#define mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd -+#define mmLB2_LB_BLACK_KEYER_R_CR 0x40cd -+#define mmLB3_LB_BLACK_KEYER_R_CR 0x43cd -+#define mmLB4_LB_BLACK_KEYER_R_CR 0x46cd -+#define mmLB5_LB_BLACK_KEYER_R_CR 0x49cd -+#define mmLB_BLACK_KEYER_G_Y 0x1ace -+#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace -+#define mmLB1_LB_BLACK_KEYER_G_Y 0x1dce -+#define mmLB2_LB_BLACK_KEYER_G_Y 0x40ce -+#define mmLB3_LB_BLACK_KEYER_G_Y 0x43ce -+#define mmLB4_LB_BLACK_KEYER_G_Y 0x46ce -+#define mmLB5_LB_BLACK_KEYER_G_Y 0x49ce -+#define mmLB_BLACK_KEYER_B_CB 0x1acf -+#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf -+#define mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf -+#define mmLB2_LB_BLACK_KEYER_B_CB 0x40cf -+#define mmLB3_LB_BLACK_KEYER_B_CB 0x43cf -+#define mmLB4_LB_BLACK_KEYER_B_CB 0x46cf -+#define mmLB5_LB_BLACK_KEYER_B_CB 0x49cf -+#define mmLB_KEYER_COLOR_CTRL 0x1ad0 -+#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 -+#define mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0 -+#define mmLB2_LB_KEYER_COLOR_CTRL 0x40d0 -+#define mmLB3_LB_KEYER_COLOR_CTRL 0x43d0 -+#define mmLB4_LB_KEYER_COLOR_CTRL 0x46d0 -+#define mmLB5_LB_KEYER_COLOR_CTRL 0x49d0 -+#define mmLB_KEYER_COLOR_R_CR 0x1ad1 -+#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 -+#define mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1 -+#define mmLB2_LB_KEYER_COLOR_R_CR 0x40d1 -+#define mmLB3_LB_KEYER_COLOR_R_CR 0x43d1 -+#define mmLB4_LB_KEYER_COLOR_R_CR 0x46d1 -+#define mmLB5_LB_KEYER_COLOR_R_CR 0x49d1 -+#define mmLB_KEYER_COLOR_G_Y 0x1ad2 -+#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 -+#define mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2 -+#define mmLB2_LB_KEYER_COLOR_G_Y 0x40d2 -+#define mmLB3_LB_KEYER_COLOR_G_Y 0x43d2 -+#define mmLB4_LB_KEYER_COLOR_G_Y 0x46d2 -+#define mmLB5_LB_KEYER_COLOR_G_Y 0x49d2 -+#define mmLB_KEYER_COLOR_B_CB 0x1ad3 -+#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 -+#define mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3 -+#define mmLB2_LB_KEYER_COLOR_B_CB 0x40d3 -+#define mmLB3_LB_KEYER_COLOR_B_CB 0x43d3 -+#define mmLB4_LB_KEYER_COLOR_B_CB 0x46d3 -+#define mmLB5_LB_KEYER_COLOR_B_CB 0x49d3 -+#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 -+#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 -+#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4 -+#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4 -+#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4 -+#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4 -+#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4 -+#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 -+#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 -+#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5 -+#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5 -+#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5 -+#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5 -+#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5 -+#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 -+#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 -+#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6 -+#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6 -+#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6 -+#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6 -+#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6 -+#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 -+#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 -+#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7 -+#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7 -+#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7 -+#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7 -+#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7 -+#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 -+#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 -+#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8 -+#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8 -+#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8 -+#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8 -+#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8 -+#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 -+#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 -+#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9 -+#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9 -+#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9 -+#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9 -+#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9 -+#define mmLB_BUFFER_STATUS 0x1ada -+#define mmLB0_LB_BUFFER_STATUS 0x1ada -+#define mmLB1_LB_BUFFER_STATUS 0x1dda -+#define mmLB2_LB_BUFFER_STATUS 0x40da -+#define mmLB3_LB_BUFFER_STATUS 0x43da -+#define mmLB4_LB_BUFFER_STATUS 0x46da -+#define mmLB5_LB_BUFFER_STATUS 0x49da -+#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc -+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc -+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc -+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc -+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc -+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc -+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc -+#define mmMVP_AFR_FLIP_MODE 0x1ae0 -+#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 -+#define mmLB1_MVP_AFR_FLIP_MODE 0x1de0 -+#define mmLB2_MVP_AFR_FLIP_MODE 0x40e0 -+#define mmLB3_MVP_AFR_FLIP_MODE 0x43e0 -+#define mmLB4_MVP_AFR_FLIP_MODE 0x46e0 -+#define mmLB5_MVP_AFR_FLIP_MODE 0x49e0 -+#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 -+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1 -+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 -+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1 -+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1 -+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1 -+#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 -+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 -+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2 -+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2 -+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2 -+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2 -+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2 -+#define mmDC_MVP_LB_CONTROL 0x1ae3 -+#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 -+#define mmLB1_DC_MVP_LB_CONTROL 0x1de3 -+#define mmLB2_DC_MVP_LB_CONTROL 0x40e3 -+#define mmLB3_DC_MVP_LB_CONTROL 0x43e3 -+#define mmLB4_DC_MVP_LB_CONTROL 0x46e3 -+#define mmLB5_DC_MVP_LB_CONTROL 0x49e3 -+#define mmLB_DEBUG 0x1ae4 -+#define mmLB0_LB_DEBUG 0x1ae4 -+#define mmLB1_LB_DEBUG 0x1de4 -+#define mmLB2_LB_DEBUG 0x40e4 -+#define mmLB3_LB_DEBUG 0x43e4 -+#define mmLB4_LB_DEBUG 0x46e4 -+#define mmLB5_LB_DEBUG 0x49e4 -+#define mmLB_DEBUG2 0x1ae5 -+#define mmLB0_LB_DEBUG2 0x1ae5 -+#define mmLB1_LB_DEBUG2 0x1de5 -+#define mmLB2_LB_DEBUG2 0x40e5 -+#define mmLB3_LB_DEBUG2 0x43e5 -+#define mmLB4_LB_DEBUG2 0x46e5 -+#define mmLB5_LB_DEBUG2 0x49e5 -+#define mmLB_DEBUG3 0x1ae6 -+#define mmLB0_LB_DEBUG3 0x1ae6 -+#define mmLB1_LB_DEBUG3 0x1de6 -+#define mmLB2_LB_DEBUG3 0x40e6 -+#define mmLB3_LB_DEBUG3 0x43e6 -+#define mmLB4_LB_DEBUG3 0x46e6 -+#define mmLB5_LB_DEBUG3 0x49e6 -+#define mmLB_TEST_DEBUG_INDEX 0x1afe -+#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe -+#define mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe -+#define mmLB2_LB_TEST_DEBUG_INDEX 0x40fe -+#define mmLB3_LB_TEST_DEBUG_INDEX 0x43fe -+#define mmLB4_LB_TEST_DEBUG_INDEX 0x46fe -+#define mmLB5_LB_TEST_DEBUG_INDEX 0x49fe -+#define mmLB_TEST_DEBUG_DATA 0x1aff -+#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff -+#define mmLB1_LB_TEST_DEBUG_DATA 0x1dff -+#define mmLB2_LB_TEST_DEBUG_DATA 0x40ff -+#define mmLB3_LB_TEST_DEBUG_DATA 0x43ff -+#define mmLB4_LB_TEST_DEBUG_DATA 0x46ff -+#define mmLB5_LB_TEST_DEBUG_DATA 0x49ff -+#define mmMVP_CONTROL1 0x1680 -+#define mmMVP_CONTROL2 0x1681 -+#define mmMVP_FIFO_CONTROL 0x1682 -+#define mmMVP_FIFO_STATUS 0x1683 -+#define mmMVP_SLAVE_STATUS 0x1684 -+#define mmMVP_INBAND_CNTL_CAP 0x1685 -+#define mmMVP_BLACK_KEYER 0x1686 -+#define mmMVP_CRC_CNTL 0x1687 -+#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 -+#define mmMVP_CRC_RESULT_RED 0x1689 -+#define mmMVP_CONTROL3 0x168a -+#define mmMVP_RECEIVE_CNT_CNTL1 0x168b -+#define mmMVP_RECEIVE_CNT_CNTL2 0x168c -+#define mmMVP_DEBUG 0x168f -+#define mmMVP_TEST_DEBUG_INDEX 0x168d -+#define mmMVP_TEST_DEBUG_DATA 0x168e -+#define ixMVP_DEBUG_12 0xc -+#define ixMVP_DEBUG_13 0xd -+#define ixMVP_DEBUG_14 0xe -+#define ixMVP_DEBUG_15 0xf -+#define ixMVP_DEBUG_16 0x10 -+#define ixMVP_DEBUG_17 0x11 -+#define mmSCL_COEF_RAM_SELECT 0x1b40 -+#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 -+#define mmSCL1_SCL_COEF_RAM_SELECT 0x1e40 -+#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 -+#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 -+#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 -+#define mmSCL5_SCL_COEF_RAM_SELECT 0x4a40 -+#define mmSCL_COEF_RAM_TAP_DATA 0x1b41 -+#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 -+#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41 -+#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 -+#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 -+#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 -+#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41 -+#define mmSCL_MODE 0x1b42 -+#define mmSCL0_SCL_MODE 0x1b42 -+#define mmSCL1_SCL_MODE 0x1e42 -+#define mmSCL2_SCL_MODE 0x4142 -+#define mmSCL3_SCL_MODE 0x4442 -+#define mmSCL4_SCL_MODE 0x4742 -+#define mmSCL5_SCL_MODE 0x4a42 -+#define mmSCL_TAP_CONTROL 0x1b43 -+#define mmSCL0_SCL_TAP_CONTROL 0x1b43 -+#define mmSCL1_SCL_TAP_CONTROL 0x1e43 -+#define mmSCL2_SCL_TAP_CONTROL 0x4143 -+#define mmSCL3_SCL_TAP_CONTROL 0x4443 -+#define mmSCL4_SCL_TAP_CONTROL 0x4743 -+#define mmSCL5_SCL_TAP_CONTROL 0x4a43 -+#define mmSCL_CONTROL 0x1b44 -+#define mmSCL0_SCL_CONTROL 0x1b44 -+#define mmSCL1_SCL_CONTROL 0x1e44 -+#define mmSCL2_SCL_CONTROL 0x4144 -+#define mmSCL3_SCL_CONTROL 0x4444 -+#define mmSCL4_SCL_CONTROL 0x4744 -+#define mmSCL5_SCL_CONTROL 0x4a44 -+#define mmSCL_BYPASS_CONTROL 0x1b45 -+#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 -+#define mmSCL1_SCL_BYPASS_CONTROL 0x1e45 -+#define mmSCL2_SCL_BYPASS_CONTROL 0x4145 -+#define mmSCL3_SCL_BYPASS_CONTROL 0x4445 -+#define mmSCL4_SCL_BYPASS_CONTROL 0x4745 -+#define mmSCL5_SCL_BYPASS_CONTROL 0x4a45 -+#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 -+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 -+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46 -+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 -+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 -+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 -+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46 -+#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 -+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 -+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47 -+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 -+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 -+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 -+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47 -+#define mmSCL_HORZ_FILTER_CONTROL 0x1b48 -+#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 -+#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48 -+#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148 -+#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448 -+#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748 -+#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48 -+#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 -+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49 -+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 -+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449 -+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749 -+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49 -+#define mmSCL_HORZ_FILTER_INIT 0x1b4a -+#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a -+#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a -+#define mmSCL2_SCL_HORZ_FILTER_INIT 0x414a -+#define mmSCL3_SCL_HORZ_FILTER_INIT 0x444a -+#define mmSCL4_SCL_HORZ_FILTER_INIT 0x474a -+#define mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a -+#define mmSCL_VERT_FILTER_CONTROL 0x1b4b -+#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b -+#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b -+#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b -+#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b -+#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b -+#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b -+#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c -+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c -+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c -+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c -+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c -+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c -+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c -+#define mmSCL_VERT_FILTER_INIT 0x1b4d -+#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d -+#define mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d -+#define mmSCL2_SCL_VERT_FILTER_INIT 0x414d -+#define mmSCL3_SCL_VERT_FILTER_INIT 0x444d -+#define mmSCL4_SCL_VERT_FILTER_INIT 0x474d -+#define mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d -+#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e -+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e -+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e -+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e -+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e -+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e -+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e -+#define mmSCL_ROUND_OFFSET 0x1b4f -+#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f -+#define mmSCL1_SCL_ROUND_OFFSET 0x1e4f -+#define mmSCL2_SCL_ROUND_OFFSET 0x414f -+#define mmSCL3_SCL_ROUND_OFFSET 0x444f -+#define mmSCL4_SCL_ROUND_OFFSET 0x474f -+#define mmSCL5_SCL_ROUND_OFFSET 0x4a4f -+#define mmSCL_UPDATE 0x1b51 -+#define mmSCL0_SCL_UPDATE 0x1b51 -+#define mmSCL1_SCL_UPDATE 0x1e51 -+#define mmSCL2_SCL_UPDATE 0x4151 -+#define mmSCL3_SCL_UPDATE 0x4451 -+#define mmSCL4_SCL_UPDATE 0x4751 -+#define mmSCL5_SCL_UPDATE 0x4a51 -+#define mmSCL_F_SHARP_CONTROL 0x1b53 -+#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 -+#define mmSCL1_SCL_F_SHARP_CONTROL 0x1e53 -+#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 -+#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 -+#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 -+#define mmSCL5_SCL_F_SHARP_CONTROL 0x4a53 -+#define mmSCL_ALU_CONTROL 0x1b54 -+#define mmSCL0_SCL_ALU_CONTROL 0x1b54 -+#define mmSCL1_SCL_ALU_CONTROL 0x1e54 -+#define mmSCL2_SCL_ALU_CONTROL 0x4154 -+#define mmSCL3_SCL_ALU_CONTROL 0x4454 -+#define mmSCL4_SCL_ALU_CONTROL 0x4754 -+#define mmSCL5_SCL_ALU_CONTROL 0x4a54 -+#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 -+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55 -+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 -+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 -+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 -+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55 -+#define mmVIEWPORT_START 0x1b5c -+#define mmSCL0_VIEWPORT_START 0x1b5c -+#define mmSCL1_VIEWPORT_START 0x1e5c -+#define mmSCL2_VIEWPORT_START 0x415c -+#define mmSCL3_VIEWPORT_START 0x445c -+#define mmSCL4_VIEWPORT_START 0x475c -+#define mmSCL5_VIEWPORT_START 0x4a5c -+#define mmVIEWPORT_SIZE 0x1b5d -+#define mmSCL0_VIEWPORT_SIZE 0x1b5d -+#define mmSCL1_VIEWPORT_SIZE 0x1e5d -+#define mmSCL2_VIEWPORT_SIZE 0x415d -+#define mmSCL3_VIEWPORT_SIZE 0x445d -+#define mmSCL4_VIEWPORT_SIZE 0x475d -+#define mmSCL5_VIEWPORT_SIZE 0x4a5d -+#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e -+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e -+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e -+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e -+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e -+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e -+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e -+#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f -+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f -+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f -+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f -+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f -+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f -+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f -+#define mmSCL_MODE_CHANGE_DET1 0x1b60 -+#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 -+#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60 -+#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 -+#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 -+#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 -+#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60 -+#define mmSCL_MODE_CHANGE_DET2 0x1b61 -+#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 -+#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61 -+#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 -+#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 -+#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 -+#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61 -+#define mmSCL_MODE_CHANGE_DET3 0x1b62 -+#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 -+#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62 -+#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 -+#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 -+#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 -+#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62 -+#define mmSCL_MODE_CHANGE_MASK 0x1b63 -+#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 -+#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63 -+#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 -+#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 -+#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 -+#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63 -+#define mmSCL_DEBUG2 0x1b69 -+#define mmSCL0_SCL_DEBUG2 0x1b69 -+#define mmSCL1_SCL_DEBUG2 0x1e69 -+#define mmSCL2_SCL_DEBUG2 0x4169 -+#define mmSCL3_SCL_DEBUG2 0x4469 -+#define mmSCL4_SCL_DEBUG2 0x4769 -+#define mmSCL5_SCL_DEBUG2 0x4a69 -+#define mmSCL_DEBUG 0x1b6a -+#define mmSCL0_SCL_DEBUG 0x1b6a -+#define mmSCL1_SCL_DEBUG 0x1e6a -+#define mmSCL2_SCL_DEBUG 0x416a -+#define mmSCL3_SCL_DEBUG 0x446a -+#define mmSCL4_SCL_DEBUG 0x476a -+#define mmSCL5_SCL_DEBUG 0x4a6a -+#define mmSCL_TEST_DEBUG_INDEX 0x1b6b -+#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b -+#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b -+#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b -+#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b -+#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b -+#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b -+#define mmSCL_TEST_DEBUG_DATA 0x1b6c -+#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c -+#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c -+#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416c -+#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446c -+#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476c -+#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c -+#define mmGENMO_WT 0xf0 -+#define mmGENMO_RD 0xf3 -+#define mmGENENB 0xf0 -+#define mmGENFC_WT 0xee -+#define mmVGA0_GENFC_WT 0xee -+#define mmVGA1_GENFC_WT 0xf6 -+#define mmGENFC_RD 0xf2 -+#define mmGENS0 0xf0 -+#define mmGENS1 0xee -+#define mmVGA0_GENS1 0xee -+#define mmVGA1_GENS1 0xf6 -+#define mmDAC_DATA 0xf2 -+#define mmDAC_MASK 0xf1 -+#define mmDAC_R_INDEX 0xf1 -+#define mmDAC_W_INDEX 0xf2 -+#define mmSEQ8_IDX 0xf1 -+#define mmSEQ8_DATA 0xf1 -+#define ixSEQ00 0x0 -+#define ixSEQ01 0x1 -+#define ixSEQ02 0x2 -+#define ixSEQ03 0x3 -+#define ixSEQ04 0x4 -+#define mmCRTC8_IDX 0xed -+#define mmVGA0_CRTC8_IDX 0xed -+#define mmVGA1_CRTC8_IDX 0xf5 -+#define mmCRTC8_DATA 0xed -+#define mmVGA0_CRTC8_DATA 0xed -+#define mmVGA1_CRTC8_DATA 0xf5 -+#define ixCRT00 0x0 -+#define ixCRT01 0x1 -+#define ixCRT02 0x2 -+#define ixCRT03 0x3 -+#define ixCRT04 0x4 -+#define ixCRT05 0x5 -+#define ixCRT06 0x6 -+#define ixCRT07 0x7 -+#define ixCRT08 0x8 -+#define ixCRT09 0x9 -+#define ixCRT0A 0xa -+#define ixCRT0B 0xb -+#define ixCRT0C 0xc -+#define ixCRT0D 0xd -+#define ixCRT0E 0xe -+#define ixCRT0F 0xf -+#define ixCRT10 0x10 -+#define ixCRT11 0x11 -+#define ixCRT12 0x12 -+#define ixCRT13 0x13 -+#define ixCRT14 0x14 -+#define ixCRT15 0x15 -+#define ixCRT16 0x16 -+#define ixCRT17 0x17 -+#define ixCRT18 0x18 -+#define ixCRT1E 0x1e -+#define ixCRT1F 0x1f -+#define ixCRT22 0x22 -+#define mmGRPH8_IDX 0xf3 -+#define mmGRPH8_DATA 0xf3 -+#define ixGRA00 0x0 -+#define ixGRA01 0x1 -+#define ixGRA02 0x2 -+#define ixGRA03 0x3 -+#define ixGRA04 0x4 -+#define ixGRA05 0x5 -+#define ixGRA06 0x6 -+#define ixGRA07 0x7 -+#define ixGRA08 0x8 -+#define mmATTRX 0xf0 -+#define mmATTRDW 0xf0 -+#define mmATTRDR 0xf0 -+#define ixATTR00 0x0 -+#define ixATTR01 0x1 -+#define ixATTR02 0x2 -+#define ixATTR03 0x3 -+#define ixATTR04 0x4 -+#define ixATTR05 0x5 -+#define ixATTR06 0x6 -+#define ixATTR07 0x7 -+#define ixATTR08 0x8 -+#define ixATTR09 0x9 -+#define ixATTR0A 0xa -+#define ixATTR0B 0xb -+#define ixATTR0C 0xc -+#define ixATTR0D 0xd -+#define ixATTR0E 0xe -+#define ixATTR0F 0xf -+#define ixATTR10 0x10 -+#define ixATTR11 0x11 -+#define ixATTR12 0x12 -+#define ixATTR13 0x13 -+#define ixATTR14 0x14 -+#define mmVGA_RENDER_CONTROL 0xc0 -+#define mmVGA_SOURCE_SELECT 0xfc -+#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 -+#define mmVGA_MODE_CONTROL 0xc2 -+#define mmVGA_SURFACE_PITCH_SELECT 0xc3 -+#define mmVGA_MEMORY_BASE_ADDRESS 0xc4 -+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 -+#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 -+#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 -+#define mmVGA_HDP_CONTROL 0xca -+#define mmVGA_CACHE_CONTROL 0xcb -+#define mmD1VGA_CONTROL 0xcc -+#define mmD2VGA_CONTROL 0xce -+#define mmD3VGA_CONTROL 0xf8 -+#define mmD4VGA_CONTROL 0xf9 -+#define mmD5VGA_CONTROL 0xfa -+#define mmD6VGA_CONTROL 0xfb -+#define mmVGA_HW_DEBUG 0xcf -+#define mmVGA_STATUS 0xd0 -+#define mmVGA_INTERRUPT_CONTROL 0xd1 -+#define mmVGA_STATUS_CLEAR 0xd2 -+#define mmVGA_INTERRUPT_STATUS 0xd3 -+#define mmVGA_MAIN_CONTROL 0xd4 -+#define mmVGA_TEST_CONTROL 0xd5 -+#define mmVGA_DEBUG_READBACK_INDEX 0xd6 -+#define mmVGA_DEBUG_READBACK_DATA 0xd7 -+#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 -+#define mmVGA_MEM_READ_PAGE_ADDR 0x13 -+#define mmVGA_TEST_DEBUG_INDEX 0xc5 -+#define mmVGA_TEST_DEBUG_DATA 0xc7 -+#define ixVGADCC_DBG_DCCIF_C 0x7e -+#define mmBPHYC_DAC_MACRO_CNTL 0x19fd -+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe -+#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 -+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30 -+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 -+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 -+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 -+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30 -+#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 -+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31 -+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 -+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 -+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 -+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31 -+#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 -+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 -+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32 -+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132 -+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432 -+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732 -+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32 -+#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 -+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 -+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33 -+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 -+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 -+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 -+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33 -+#define mmDPG_PIPE_DPM_CONTROL 0x1b34 -+#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 -+#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34 -+#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 -+#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 -+#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 -+#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34 -+#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 -+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 -+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35 -+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 -+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 -+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 -+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35 -+#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -+#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 -+#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36 -+#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 -+#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 -+#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 -+#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36 -+#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 -+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37 -+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 -+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 -+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 -+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37 -+#define mmDPG_REPEATER_PROGRAM 0x1b3a -+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a -+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a -+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a -+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a -+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a -+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a -+#define mmDPG_HW_DEBUG_A 0x1b3b -+#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b -+#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b -+#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b -+#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b -+#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b -+#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b -+#define mmDPG_HW_DEBUG_B 0x1b3c -+#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c -+#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c -+#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c -+#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c -+#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c -+#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c -+#define mmDPG_TEST_DEBUG_INDEX 0x1b38 -+#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 -+#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38 -+#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 -+#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 -+#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 -+#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38 -+#define mmDPG_TEST_DEBUG_DATA 0x1b39 -+#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 -+#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39 -+#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 -+#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 -+#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 -+#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39 -+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 -+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 -+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 -+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 -+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 -+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a -+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b -+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f -+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 -+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff -+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 -+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 -+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 -+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 -+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 -+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2 -+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3 -+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5 -+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6 -+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7 -+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8 -+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9 -+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da -+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db -+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc -+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd -+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de -+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4 -+#define mmAZALIA_F0_CODEC_DEBUG 0x17df -+#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1 -+#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2 -+#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3 -+#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4 -+#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5 -+#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6 -+#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7 -+#define mmGLOBAL_CAPABILITIES 0x0 -+#define mmMINOR_VERSION 0x0 -+#define mmMAJOR_VERSION 0x0 -+#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 -+#define mmINPUT_PAYLOAD_CAPABILITY 0x1 -+#define mmGLOBAL_CONTROL 0x2 -+#define mmWAKE_ENABLE 0x3 -+#define mmSTATE_CHANGE_STATUS 0x3 -+#define mmGLOBAL_STATUS 0x4 -+#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 -+#define mmINTERRUPT_CONTROL 0x8 -+#define mmINTERRUPT_STATUS 0x9 -+#define mmWALL_CLOCK_COUNTER 0xc -+#define mmSTREAM_SYNCHRONIZATION 0xe -+#define mmCORB_LOWER_BASE_ADDRESS 0x10 -+#define mmCORB_UPPER_BASE_ADDRESS 0x11 -+#define mmCORB_WRITE_POINTER 0x12 -+#define mmCORB_READ_POINTER 0x12 -+#define mmCORB_CONTROL 0x13 -+#define mmCORB_STATUS 0x13 -+#define mmCORB_SIZE 0x13 -+#define mmRIRB_LOWER_BASE_ADDRESS 0x14 -+#define mmRIRB_UPPER_BASE_ADDRESS 0x15 -+#define mmRIRB_WRITE_POINTER 0x16 -+#define mmRESPONSE_INTERRUPT_COUNT 0x16 -+#define mmRIRB_CONTROL 0x17 -+#define mmRIRB_STATUS 0x17 -+#define mmRIRB_SIZE 0x17 -+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 -+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 -+#define mmIMMEDIATE_COMMAND_STATUS 0x1a -+#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c -+#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d -+#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c -+#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 -+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 -+#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 -+#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 -+#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 -+#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 -+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 -+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 -+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 -+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 -+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 -+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 -+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a -+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b -+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 -+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 -+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d -+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e -+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e -+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 -+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 -+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 -+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 -+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c -+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 -+#define ixAUDIO_DESCRIPTOR0 0x1 -+#define ixAUDIO_DESCRIPTOR1 0x2 -+#define ixAUDIO_DESCRIPTOR2 0x3 -+#define ixAUDIO_DESCRIPTOR3 0x4 -+#define ixAUDIO_DESCRIPTOR4 0x5 -+#define ixAUDIO_DESCRIPTOR5 0x6 -+#define ixAUDIO_DESCRIPTOR6 0x7 -+#define ixAUDIO_DESCRIPTOR7 0x8 -+#define ixAUDIO_DESCRIPTOR8 0x9 -+#define ixAUDIO_DESCRIPTOR9 0xa -+#define ixAUDIO_DESCRIPTOR10 0xb -+#define ixAUDIO_DESCRIPTOR11 0xc -+#define ixAUDIO_DESCRIPTOR12 0xd -+#define ixAUDIO_DESCRIPTOR13 0xe -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 -+#define ixSINK_DESCRIPTION0 0x5 -+#define ixSINK_DESCRIPTION1 0x6 -+#define ixSINK_DESCRIPTION2 0x7 -+#define ixSINK_DESCRIPTION3 0x8 -+#define ixSINK_DESCRIPTION4 0x9 -+#define ixSINK_DESCRIPTION5 0xa -+#define ixSINK_DESCRIPTION6 0xb -+#define ixSINK_DESCRIPTION7 0xc -+#define ixSINK_DESCRIPTION8 0xd -+#define ixSINK_DESCRIPTION9 0xe -+#define ixSINK_DESCRIPTION10 0xf -+#define ixSINK_DESCRIPTION11 0x10 -+#define ixSINK_DESCRIPTION12 0x11 -+#define ixSINK_DESCRIPTION13 0x12 -+#define ixSINK_DESCRIPTION14 0x13 -+#define ixSINK_DESCRIPTION15 0x14 -+#define ixSINK_DESCRIPTION16 0x15 -+#define ixSINK_DESCRIPTION17 0x16 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 -+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 -+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 -+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 -+#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9 -+#define mmAZALIA_AUDIO_DTO 0x17ba -+#define mmAZALIA_AUDIO_DTO_CONTROL 0x17bb -+#define mmAZALIA_SCLK_CONTROL 0x17bc -+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd -+#define mmAZALIA_DATA_DMA_CONTROL 0x17be -+#define mmAZALIA_BDL_DMA_CONTROL 0x17bf -+#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0 -+#define mmAZALIA_CORB_DMA_CONTROL 0x17c1 -+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9 -+#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca -+#define mmAZALIA_GLOBAL_CAPABILITIES 0x17cb -+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc -+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd -+#define mmAZALIA_CONTROLLER_DEBUG 0x17cf -+#define mmAZALIA_CRC0_CONTROL0 0x17ae -+#define mmAZALIA_CRC0_CONTROL1 0x17af -+#define mmAZALIA_CRC0_CONTROL2 0x17b0 -+#define mmAZALIA_CRC0_CONTROL3 0x17b1 -+#define mmAZALIA_CRC0_RESULT 0x17b2 -+#define ixAZALIA_CRC0_CHANNEL0 0x0 -+#define ixAZALIA_CRC0_CHANNEL1 0x1 -+#define ixAZALIA_CRC0_CHANNEL2 0x2 -+#define ixAZALIA_CRC0_CHANNEL3 0x3 -+#define ixAZALIA_CRC0_CHANNEL4 0x4 -+#define ixAZALIA_CRC0_CHANNEL5 0x5 -+#define ixAZALIA_CRC0_CHANNEL6 0x6 -+#define ixAZALIA_CRC0_CHANNEL7 0x7 -+#define mmAZALIA_CRC1_CONTROL0 0x17b3 -+#define mmAZALIA_CRC1_CONTROL1 0x17b4 -+#define mmAZALIA_CRC1_CONTROL2 0x17b5 -+#define mmAZALIA_CRC1_CONTROL3 0x17b6 -+#define mmAZALIA_CRC1_RESULT 0x17b7 -+#define ixAZALIA_CRC1_CHANNEL0 0x0 -+#define ixAZALIA_CRC1_CHANNEL1 0x1 -+#define ixAZALIA_CRC1_CHANNEL2 0x2 -+#define ixAZALIA_CRC1_CHANNEL3 0x3 -+#define ixAZALIA_CRC1_CHANNEL4 0x4 -+#define ixAZALIA_CRC1_CHANNEL5 0x5 -+#define ixAZALIA_CRC1_CHANNEL6 0x6 -+#define ixAZALIA_CRC1_CHANNEL7 0x7 -+#define mmAZ_TEST_DEBUG_INDEX 0x17d0 -+#define mmAZ_TEST_DEBUG_DATA 0x17d1 -+#define mmAZALIA_STREAM_INDEX 0x17e8 -+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8 -+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec -+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0 -+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4 -+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8 -+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc -+#define mmAZALIA_STREAM_DATA 0x17e9 -+#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9 -+#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed -+#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1 -+#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5 -+#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9 -+#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd -+#define ixAZALIA_FIFO_SIZE_CONTROL 0x0 -+#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 -+#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 -+#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 -+#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 -+#define ixAZALIA_STREAM_DEBUG 0x5 -+#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 -+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 -+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 -+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c -+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 -+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 -+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e -+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4 -+#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 -+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 -+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 -+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d -+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 -+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 -+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f -+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5 -+#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 -+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 -+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 -+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 -+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 -+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 -+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 -+#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 -+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 -+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 -+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa -+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc -+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd -+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe -+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 -+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 -+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 -+#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 -+#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 -+#define mmBLND_CONTROL 0x1b6d -+#define mmBLND0_BLND_CONTROL 0x1b6d -+#define mmBLND1_BLND_CONTROL 0x1e6d -+#define mmBLND2_BLND_CONTROL 0x416d -+#define mmBLND3_BLND_CONTROL 0x446d -+#define mmBLND4_BLND_CONTROL 0x476d -+#define mmBLND5_BLND_CONTROL 0x4a6d -+#define mmSM_CONTROL2 0x1b6e -+#define mmBLND0_SM_CONTROL2 0x1b6e -+#define mmBLND1_SM_CONTROL2 0x1e6e -+#define mmBLND2_SM_CONTROL2 0x416e -+#define mmBLND3_SM_CONTROL2 0x446e -+#define mmBLND4_SM_CONTROL2 0x476e -+#define mmBLND5_SM_CONTROL2 0x4a6e -+#define mmPTI_CONTROL 0x1b6f -+#define mmBLND0_PTI_CONTROL 0x1b6f -+#define mmBLND1_PTI_CONTROL 0x1e6f -+#define mmBLND2_PTI_CONTROL 0x416f -+#define mmBLND3_PTI_CONTROL 0x446f -+#define mmBLND4_PTI_CONTROL 0x476f -+#define mmBLND5_PTI_CONTROL 0x4a6f -+#define mmBLND_UPDATE 0x1b70 -+#define mmBLND0_BLND_UPDATE 0x1b70 -+#define mmBLND1_BLND_UPDATE 0x1e70 -+#define mmBLND2_BLND_UPDATE 0x4170 -+#define mmBLND3_BLND_UPDATE 0x4470 -+#define mmBLND4_BLND_UPDATE 0x4770 -+#define mmBLND5_BLND_UPDATE 0x4a70 -+#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 -+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 -+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71 -+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171 -+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471 -+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771 -+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71 -+#define mmBLND_V_UPDATE_LOCK 0x1b73 -+#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 -+#define mmBLND1_BLND_V_UPDATE_LOCK 0x1e73 -+#define mmBLND2_BLND_V_UPDATE_LOCK 0x4173 -+#define mmBLND3_BLND_V_UPDATE_LOCK 0x4473 -+#define mmBLND4_BLND_V_UPDATE_LOCK 0x4773 -+#define mmBLND5_BLND_V_UPDATE_LOCK 0x4a73 -+#define mmBLND_REG_UPDATE_STATUS 0x1b77 -+#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 -+#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77 -+#define mmBLND2_BLND_REG_UPDATE_STATUS 0x4177 -+#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4477 -+#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4777 -+#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77 -+#define mmBLND_DEBUG 0x1b74 -+#define mmBLND0_BLND_DEBUG 0x1b74 -+#define mmBLND1_BLND_DEBUG 0x1e74 -+#define mmBLND2_BLND_DEBUG 0x4174 -+#define mmBLND3_BLND_DEBUG 0x4474 -+#define mmBLND4_BLND_DEBUG 0x4774 -+#define mmBLND5_BLND_DEBUG 0x4a74 -+#define mmBLND_TEST_DEBUG_INDEX 0x1b75 -+#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 -+#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75 -+#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175 -+#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475 -+#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775 -+#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75 -+#define mmBLND_TEST_DEBUG_DATA 0x1b76 -+#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 -+#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76 -+#define mmBLND2_BLND_TEST_DEBUG_DATA 0x4176 -+#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4476 -+#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4776 -+#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76 -+#define mmSI_ENABLE 0x4c00 -+#define mmSI_EC_CONFIG 0x4c01 -+#define mmCNV_MODE 0x4c02 -+#define mmCNV_WINDOW_START 0x4c03 -+#define mmCNV_WINDOW_SIZE 0x4c04 -+#define mmCNV_UPDATE 0x4c05 -+#define mmCNV_SOURCE_SIZE 0x4c06 -+#define mmCNV_CSC_CONTROL 0x4c07 -+#define mmCNV_CSC_C11_C12 0x4c08 -+#define mmCNV_CSC_C13_C14 0x4c09 -+#define mmCNV_CSC_C21_C22 0x4c0a -+#define mmCNV_CSC_C23_C24 0x4c0b -+#define mmCNV_CSC_C31_C32 0x4c0c -+#define mmCNV_CSC_C33_C34 0x4c0d -+#define mmCNV_CSC_ROUND_OFFSET_R 0x4c0e -+#define mmCNV_CSC_ROUND_OFFSET_G 0x4c0f -+#define mmCNV_CSC_ROUND_OFFSET_B 0x4c10 -+#define mmCNV_CSC_CLAMP_R 0x4c11 -+#define mmCNV_CSC_CLAMP_G 0x4c12 -+#define mmCNV_CSC_CLAMP_B 0x4c13 -+#define mmCNV_TEST_CNTL 0x4c14 -+#define mmCNV_TEST_CRC_RED 0x4c15 -+#define mmCNV_TEST_CRC_GREEN 0x4c16 -+#define mmCNV_TEST_CRC_BLUE 0x4c17 -+#define mmSI_DEBUG_CTRL 0x4c18 -+#define mmSI_DBG_MODE 0x4c1b -+#define mmSI_HARD_DEBUG 0x4c1c -+#define mmCNV_TEST_DEBUG_INDEX 0x4c19 -+#define mmCNV_TEST_DEBUG_DATA 0x4c1a -+#define mmSISCL_COEF_RAM_SELECT 0x4c20 -+#define mmSISCL_COEF_RAM_TAP_DATA 0x4c21 -+#define mmSISCL_MODE 0x4c22 -+#define mmSISCL_TAP_CONTROL 0x4c23 -+#define mmSISCL_DEST_SIZE 0x4c24 -+#define mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25 -+#define mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26 -+#define mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27 -+#define mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28 -+#define mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29 -+#define mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a -+#define mmSISCL_ROUND_OFFSET 0x4c2b -+#define mmSISCL_CLAMP 0x4c2c -+#define mmSISCL_OVERFLOW_STATUS 0x4c2d -+#define mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e -+#define mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f -+#define mmSISCL_TEST_CNTL 0x4c30 -+#define mmSISCL_TEST_CRC_RED 0x4c31 -+#define mmSISCL_TEST_CRC_GREEN 0x4c32 -+#define mmSISCL_TEST_CRC_BLUE 0x4c33 -+#define mmSISCL_BACKPRESSURE_CNT_EN 0x4c36 -+#define mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37 -+#define mmSISCL_TEST_DEBUG_INDEX 0x4c34 -+#define mmSISCL_TEST_DEBUG_DATA 0x4c35 -+#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 -+#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 -+#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 -+#define mmXDMA_INTERRUPT 0x3e3 -+#define mmXDMA_CLOCK_GATING_CNTL 0x3e4 -+#define mmXDMA_MEM_POWER_CNTL 0x3e6 -+#define mmXDMA_IF_BIF_STATUS 0x3e7 -+#define mmXDMA_PERF_MEAS_STATUS 0x3e8 -+#define mmXDMA_IF_STATUS 0x3e9 -+#define mmXDMA_TEST_DEBUG_INDEX 0x3ea -+#define mmXDMA_TEST_DEBUG_DATA 0x3eb -+#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 -+#define mmXDMA_PG_CONTROL 0x3f9 -+#define mmXDMA_PG_WDATA 0x3fa -+#define mmXDMA_PG_STATUS 0x3fb -+#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc -+#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd -+ -+#endif /* DCE_8_0_D_H */ -diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h -new file mode 100644 -index 0000000..8a29307 ---- /dev/null -+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h -@@ -0,0 +1,13109 @@ -+/* -+ * DCE_8_0 Register documentation -+ * -+ * Copyright (C) 2014 Advanced Micro Devices, Inc. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included -+ * in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN -+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#ifndef DCE_8_0_SH_MASK_H -+#define DCE_8_0_SH_MASK_H -+ -+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 -+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 -+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 -+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 -+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff -+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 -+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 -+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 -+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 -+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c -+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 -+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d -+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 -+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e -+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 -+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 -+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 -+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 -+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff -+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 -+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 -+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 -+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 -+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c -+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 -+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d -+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 -+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e -+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 -+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 -+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 -+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 -+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff -+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 -+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 -+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 -+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 -+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c -+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 -+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d -+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 -+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e -+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1 -+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0 -+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1 -+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0 -+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff -+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0 -+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000 -+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18 -+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000 -+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c -+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000 -+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d -+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000 -+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e -+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1 -+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0 -+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1 -+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0 -+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff -+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0 -+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000 -+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18 -+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000 -+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c -+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000 -+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d -+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000 -+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e -+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1 -+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0 -+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1 -+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0 -+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff -+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0 -+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000 -+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18 -+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 -+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c -+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000 -+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d -+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 -+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e -+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 -+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 -+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff -+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 -+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff -+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 -+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 -+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 -+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 -+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 -+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 -+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 -+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 -+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 -+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff -+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 -+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff -+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 -+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff -+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 -+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff -+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 -+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff -+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 -+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff -+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 -+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff -+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 -+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 -+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 -+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f -+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 -+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 -+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 -+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 -+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 -+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 -+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff -+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 -+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 -+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff -+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 -+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 -+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff -+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 -+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 -+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff -+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 -+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 -+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff -+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 -+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 -+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 -+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff -+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 -+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 -+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 -+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 -+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 -+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f -+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 -+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 -+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 -+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 -+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 -+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 -+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 -+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 -+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 -+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 -+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 -+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f -+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff -+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 -+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff -+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 -+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 -+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 -+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff -+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 -+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 -+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 -+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff -+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 -+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff -+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 -+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff -+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 -+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 -+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 -+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 -+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f -+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff -+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 -+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff -+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 -+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 -+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f -+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff -+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 -+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff -+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 -+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff -+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 -+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff -+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 -+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff -+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 -+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff -+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 -+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff -+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 -+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 -+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa -+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 -+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 -+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 -+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f -+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff -+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff -+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000 -+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f -+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff -+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 -+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 -+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 -+#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf -+#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x1 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x0 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS_MASK 0x2 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS__SHIFT 0x1 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x4 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x2 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x8 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x3 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x10 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x4 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x20 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x5 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x40 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x6 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x300 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x8 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE_MASK 0xc00 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0xa -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x3000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0xc -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0xc000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0xe -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x30000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x10 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0xc0000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x12 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x300000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x14 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0xc00000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x16 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x3000000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x18 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x1c -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x1d -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000 -+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x1e -+#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x1fff -+#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 -+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x1fff -+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 -+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000 -+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 -+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x1fff -+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 -+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000 -+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 -+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 -+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 -+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 -+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 -+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 -+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 -+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x1fff -+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 -+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000 -+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 -+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 -+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 -+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 -+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 -+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 -+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 -+#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x1fff -+#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 -+#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000 -+#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 -+#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x1fff -+#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 -+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x1fff -+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 -+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x1fff -+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 -+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 -+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 -+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 -+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 -+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 -+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 -+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 -+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 -+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 -+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc -+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 -+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf -+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 -+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 -+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc -+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 -+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 -+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 -+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 -+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x1fff -+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 -+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000 -+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 -+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x1fff -+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 -+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000 -+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 -+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 -+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 -+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x1fff -+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 -+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000 -+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 -+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 -+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 -+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 -+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 -+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e -+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 -+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x1fff -+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 -+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000 -+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 -+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f -+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 -+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 -+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f -+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 -+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 -+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 -+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 -+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 -+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 -+#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 -+#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 -+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 -+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 -+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 -+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 -+#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 -+#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc -+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 -+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd -+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 -+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe -+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 -+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 -+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 -+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 -+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 -+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 -+#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 -+#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d -+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 -+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 -+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 -+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 -+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 -+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 -+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 -+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 -+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 -+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 -+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 -+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 -+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 -+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 -+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 -+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 -+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 -+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 -+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff -+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 -+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 -+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 -+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff -+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 -+#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 -+#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 -+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 -+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 -+#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 -+#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 -+#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 -+#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 -+#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 -+#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 -+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 -+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 -+#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 -+#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 -+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 -+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 -+#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 -+#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 -+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x1fff -+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 -+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000 -+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 -+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x1fff -+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 -+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff -+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 -+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffff -+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 -+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffff -+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 -+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 -+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 -+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e -+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 -+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 -+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 -+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 -+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 -+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 -+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 -+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 -+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 -+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 -+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 -+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x1fff -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 -+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 -+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 -+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 -+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 -+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 -+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 -+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 -+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 -+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 -+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x1fff -+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 -+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000 -+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 -+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff -+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 -+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 -+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 -+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100 -+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8 -+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xf0000 -+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x10 -+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000 -+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14 -+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000 -+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c -+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 -+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 -+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 -+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 -+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 -+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 -+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 -+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b -+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c -+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d -+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e -+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 -+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f -+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 -+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 -+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 -+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 -+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 -+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 -+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 -+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 -+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 -+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 -+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 -+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 -+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff -+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 -+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 -+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 -+#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 -+#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 -+#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 -+#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 -+#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 -+#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 -+#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 -+#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 -+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 -+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 -+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 -+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 -+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff -+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 -+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 -+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 -+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 -+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 -+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 -+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 -+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 -+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 -+#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 -+#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 -+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff -+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 -+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 -+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 -+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 -+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 -+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 -+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 -+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff -+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 -+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 -+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa -+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 -+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 -+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 -+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 -+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 -+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 -+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 -+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 -+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff -+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 -+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 -+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa -+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 -+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 -+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 -+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 -+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 -+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 -+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 -+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 -+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff -+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 -+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 -+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa -+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 -+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 -+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 -+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 -+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 -+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 -+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 -+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 -+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x1fff -+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 -+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x1fff0000 -+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 -+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 -+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x1fff -+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 -+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 -+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x1fff -+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 -+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 -+#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 -+#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 -+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 -+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 -+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 -+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 -+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 -+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc -+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 -+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 -+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 -+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 -+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 -+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 -+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x1fff -+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 -+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x1fff0000 -+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 -+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x1fff -+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 -+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x1fff0000 -+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 -+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x1fff -+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 -+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x1fff0000 -+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 -+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x1fff -+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 -+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x1fff0000 -+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 -+#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff -+#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 -+#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 -+#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 -+#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff -+#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 -+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x1fff -+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 -+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x1fff0000 -+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 -+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x1fff -+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 -+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x1fff0000 -+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 -+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x1fff -+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 -+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x1fff0000 -+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 -+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x1fff -+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 -+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x1fff0000 -+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 -+#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff -+#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 -+#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 -+#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 -+#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff -+#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000 -+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c -+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x1fff -+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0 -+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x1fff0000 -+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10 -+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x1fff -+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0 -+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x1fff0000 -+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000 -+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000 -+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000 -+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 -+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 -+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 -+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 -+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x1fff -+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 -+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000 -+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 -+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x1fff -+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 -+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 -+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 -+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 -+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c -+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff -+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff -+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 -+#define DAC_ENABLE__DAC_ENABLE_MASK 0x1 -+#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc -+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 -+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 -+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 -+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 -+#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 -+#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 -+#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 -+#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 -+#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 -+#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 -+#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 -+#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 -+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x100 -+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x8 -+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff -+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 -+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 -+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa -+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 -+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 -+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f -+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 -+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff -+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 -+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 -+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa -+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 -+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 -+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f -+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 -+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 -+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 -+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 -+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 -+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 -+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 -+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 -+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 -+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 -+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 -+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 -+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 -+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 -+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 -+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff -+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 -+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 -+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 -+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff -+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 -+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 -+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 -+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 -+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 -+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 -+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 -+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 -+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 -+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 -+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 -+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 -+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x1000000 -+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x18 -+#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff -+#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 -+#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 -+#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 -+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 -+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 -+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 -+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 -+#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 -+#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 -+#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 -+#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 -+#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 -+#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 -+#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 -+#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 -+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 -+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 -+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 -+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 -+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 -+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 -+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 -+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 -+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 -+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 -+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 -+#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 -+#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 -+#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 -+#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 -+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff -+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 -+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 -+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 -+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc -+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 -+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 -+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa -+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 -+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 -+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 -+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 -+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 -+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d -+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 -+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e -+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 -+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f -+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff -+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc -+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe -+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf -+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 -+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 -+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e -+#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 -+#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 -+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xf0 -+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x4 -+#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 -+#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 -+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 -+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c -+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 -+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d -+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 -+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e -+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 -+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 -+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf -+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 -+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 -+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff -+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 -+#define PERFMON_HI__PERFMON_HI_MASK 0xffff -+#define PERFMON_HI__PERFMON_HI__SHIFT 0x0 -+#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 -+#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d -+#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff -+#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 -+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff -+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff -+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 -+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff -+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0 -+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff -+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0 -+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff -+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0 -+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf -+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0 -+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 -+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 -+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000 -+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10 -+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf -+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0 -+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 -+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 -+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000 -+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10 -+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf -+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0 -+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 -+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 -+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000 -+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10 -+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f -+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 -+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 -+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 -+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 -+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10 -+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f -+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 -+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 -+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 -+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 -+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10 -+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f -+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 -+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 -+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 -+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 -+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10 -+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f -+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0 -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60 -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5 -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00 -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8 -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000 -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000 -+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18 -+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f -+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0 -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60 -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5 -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00 -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8 -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000 -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000 -+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18 -+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f -+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0 -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60 -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5 -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00 -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8 -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000 -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000 -+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18 -+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 -+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 -+#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN_MASK 0x10 -+#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN__SHIFT 0x4 -+#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET_MASK 0x1 -+#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET__SHIFT 0x0 -+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 -+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 -+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff -+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 -+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff -+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 -+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff -+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 -+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff -+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 -+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff -+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 -+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 -+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 -+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 -+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 -+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 -+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 -+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 -+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 -+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 -+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 -+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 -+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 -+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff -+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 -+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 -+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 -+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 -+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 -+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 -+#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 -+#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 -+#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 -+#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 -+#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 -+#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 -+#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 -+#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 -+#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 -+#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 -+#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 -+#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 -+#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 -+#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 -+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 -+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 -+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 -+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 -+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 -+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 -+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 -+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 -+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 -+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 -+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 -+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 -+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 -+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 -+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 -+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 -+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 -+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 -+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 -+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 -+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 -+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x100 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x8 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x200 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x9 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x400 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0xa -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x800 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0xb -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x1000 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0xc -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x2000 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0xd -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE_MASK 0x4000 -+#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE__SHIFT 0xe -+#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000 -+#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10 -+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 -+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 -+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 -+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 -+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 -+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14 -+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 -+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 -+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 -+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x7000000 -+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x18 -+#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000 -+#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x1c -+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf -+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 -+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 -+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 -+#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000 -+#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc -+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf -+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 -+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 -+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 -+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 -+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc -+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff -+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 -+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 -+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 -+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 -+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 -+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 -+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 -+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 -+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 -+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 -+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 -+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 -+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 -+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f -+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 -+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 -+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 -+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 -+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 -+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 -+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 -+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 -+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 -+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 -+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 -+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1 -+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0 -+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0 -+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4 -+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 -+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 -+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 -+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 -+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 -+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 -+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 -+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 -+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 -+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 -+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 -+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 -+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 -+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc -+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 -+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd -+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 -+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 -+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 -+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 -+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 -+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 -+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 -+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 -+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 -+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 -+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 -+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 -+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff -+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 -+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 -+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 -+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 -+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c -+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 -+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d -+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 -+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 -+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f -+#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x1 -+#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x0 -+#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x100 -+#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x8 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 -+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 -+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 -+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 -+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 -+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 -+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 -+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff -+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 -+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff -+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 -+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 -+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 -+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 -+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 -+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 -+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff -+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 -+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff -+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 -+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 -+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 -+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 -+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 -+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 -+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff -+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 -+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff -+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 -+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 -+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 -+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 -+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 -+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 -+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff -+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 -+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff -+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 -+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 -+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 -+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 -+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 -+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 -+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff -+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 -+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff -+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 -+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 -+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 -+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 -+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 -+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 -+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff -+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 -+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff -+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 -+#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x1 -+#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x0 -+#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x2 -+#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x1 -+#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x4 -+#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x2 -+#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x8 -+#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x3 -+#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x10 -+#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x4 -+#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x1 -+#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x0 -+#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x2 -+#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x1 -+#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x4 -+#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x2 -+#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x8 -+#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x3 -+#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x10 -+#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x4 -+#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x1 -+#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x0 -+#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x2 -+#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x1 -+#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x4 -+#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x2 -+#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x8 -+#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x3 -+#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x10 -+#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x4 -+#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x1 -+#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x0 -+#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x2 -+#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x1 -+#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x4 -+#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x2 -+#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x8 -+#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x3 -+#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x10 -+#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x4 -+#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x1 -+#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x0 -+#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x2 -+#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x1 -+#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x4 -+#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x2 -+#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x8 -+#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x3 -+#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x10 -+#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x4 -+#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x1 -+#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x0 -+#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x2 -+#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x1 -+#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x4 -+#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x2 -+#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x8 -+#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x3 -+#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x10 -+#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x4 -+#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 -+#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 -+#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 -+#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 -+#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 -+#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 -+#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 -+#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 -+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 -+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 -+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 -+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 -+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 -+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 -+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 -+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 -+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 -+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 -+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 -+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 -+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 -+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc -+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 -+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 -+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 -+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 -+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 -+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 -+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 -+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc -+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 -+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd -+#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET_MASK 0x4000 -+#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET__SHIFT 0xe -+#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET_MASK 0x8000 -+#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET__SHIFT 0xf -+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 -+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 -+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 -+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 -+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 -+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 -+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 -+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 -+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 -+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 -+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 -+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 -+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 -+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 -+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 -+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 -+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 -+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 -+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 -+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 -+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 -+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 -+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 -+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 -+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 -+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 -+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 -+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 -+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 -+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 -+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 -+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 -+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 -+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 -+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 -+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 -+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1 -+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0 -+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10 -+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4 -+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700 -+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8 -+#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x1 -+#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x0 -+#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x2 -+#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x1 -+#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x4 -+#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x2 -+#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x8 -+#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x3 -+#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x10 -+#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x4 -+#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x20 -+#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x5 -+#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x40 -+#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0x6 -+#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 -+#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 -+#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x2 -+#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x1 -+#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 -+#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 -+#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 -+#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 -+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 -+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 -+#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 -+#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 -+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 -+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 -+#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 -+#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 -+#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 -+#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 -+#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 -+#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 -+#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 -+#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 -+#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 -+#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 -+#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 -+#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 -+#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 -+#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 -+#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 -+#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 -+#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x4000000 -+#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x1a -+#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 -+#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b -+#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000 -+#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x1c -+#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000 -+#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x1d -+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7 -+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 -+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00 -+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 -+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000 -+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 -+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000 -+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 -+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000 -+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000 -+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 -+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000 -+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18 -+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000 -+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c -+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7 -+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 -+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00 -+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 -+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000 -+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 -+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000 -+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 -+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000 -+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 -+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c -+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff -+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 -+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff -+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 -+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff -+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 -+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff -+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 -+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff -+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x1000 -+#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0xc -+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 -+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c -+#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff -+#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0 -+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000 -+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc -+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf -+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0 -+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30 -+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 -+#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000 -+#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10 -+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f -+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0 -+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80 -+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 -+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00 -+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8 -+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000 -+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf -+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000 -+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10 -+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff -+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0 -+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff -+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0 -+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00 -+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8 -+#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000 -+#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc -+#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000 -+#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd -+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000 -+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10 -+#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff -+#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0 -+#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000 -+#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10 -+#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000 -+#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12 -+#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000 -+#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13 -+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1 -+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0 -+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2 -+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1 -+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4 -+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2 -+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8 -+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3 -+#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x10 -+#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x4 -+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100 -+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8 -+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000 -+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc -+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000 -+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10 -+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000 -+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14 -+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000 -+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16 -+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000 -+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18 -+#define PLL_CNTL__PLL_RESET_MASK 0x1 -+#define PLL_CNTL__PLL_RESET__SHIFT 0x0 -+#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2 -+#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1 -+#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4 -+#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2 -+#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8 -+#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 -+#define PLL_CNTL__PLL_VCOREF_MASK 0x30 -+#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4 -+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40 -+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6 -+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80 -+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7 -+#define PLL_CNTL__PLL_CALREF_MASK 0x300 -+#define PLL_CNTL__PLL_CALREF__SHIFT 0x8 -+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400 -+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa -+#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800 -+#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb -+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000 -+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd -+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000 -+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe -+#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000 -+#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10 -+#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000 -+#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13 -+#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000 -+#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14 -+#define PLL_CNTL__PLL_LOCKED_MASK 0x200000 -+#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15 -+#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000 -+#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18 -+#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000 -+#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a -+#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f -+#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0 -+#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60 -+#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5 -+#define PLL_ANALOG__PLL_CP_MASK 0xf00 -+#define PLL_ANALOG__PLL_CP__SHIFT 0x8 -+#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000 -+#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc -+#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000 -+#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15 -+#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000 -+#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18 -+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1 -+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0 -+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e -+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1 -+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0 -+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5 -+#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff -+#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0 -+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000 -+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14 -+#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000 -+#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a -+#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000 -+#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c -+#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1 -+#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0 -+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2 -+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1 -+#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00 -+#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x8 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x3 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100 -+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000 -+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b -+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1 -+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0 -+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1 -+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0 -+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100 -+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8 -+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000 -+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x1ff -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x0 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x10000 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x10 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x60000 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x11 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x100000 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x14 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x200000 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x15 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x400000 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x16 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000 -+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x18 -+#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x1ff -+#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x0 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 -+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 -+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff -+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 -+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff -+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 -+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff -+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 -+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff -+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0xf -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x1f0 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x4 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf0000 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x10 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 -+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c -+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f -+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x20 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x5 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x40 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x6 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x80 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x7 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0xfff00 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x8 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x300000 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x14 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x400000 -+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x16 -+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff -+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 -+#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 -+#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 -+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 -+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 -+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 -+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc -+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 -+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 -+#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 -+#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c -+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 -+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e -+#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 -+#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 -+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 -+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 -+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 -+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 -+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 -+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 -+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 -+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc -+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 -+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 -+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 -+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 -+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 -+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d -+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x3f -+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 -+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x3f00 -+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 -+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 -+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 -+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 -+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 -+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000 -+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 -+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000 -+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 -+#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 -+#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c -+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff -+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 -+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff -+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 -+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 -+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 -+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff -+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 -+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff -+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 -+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff -+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 -+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff -+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 -+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff -+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 -+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff -+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 -+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff -+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 -+#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff -+#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 -+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 -+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 -+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 -+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 -+#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff -+#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 -+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 -+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 -+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 -+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 -+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 -+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 -+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 -+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c -+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 -+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 -+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 -+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 -+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 -+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 -+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 -+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 -+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 -+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 -+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 -+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 -+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 -+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 -+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 -+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 -+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff -+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 -+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff -+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 -+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff -+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 -+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff -+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 -+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff -+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 -+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff -+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 -+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 -+#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 -+#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 -+#define MCIF_CONTROL__MCIF_SCANIN_DISABLE_MASK 0x8 -+#define MCIF_CONTROL__MCIF_SCANIN_DISABLE__SHIFT 0x3 -+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 -+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 -+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 -+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 -+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 -+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc -+#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 -+#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 -+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 -+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 -+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 -+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e -+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 -+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f -+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff -+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 -+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 -+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 -+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff -+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff -+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 -+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff -+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 -+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff -+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 -+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff -+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 -+#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf -+#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 -+#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 -+#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 -+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 -+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e -+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 -+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 -+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 -+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 -+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 -+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 -+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 -+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 -+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 -+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0xf -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x0 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x20 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x5 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x3c0 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x6 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x800 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0xb -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0xf000 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0xc -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x20000 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x11 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x3c0000 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x12 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x800000 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x17 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0xf000000 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x18 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x20000000 -+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x1d -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY_MASK 0xf -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY__SHIFT 0x0 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS_MASK 0x20 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS__SHIFT 0x5 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY_MASK 0x3c0 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY__SHIFT 0x6 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK 0x800 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS__SHIFT 0xb -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY_MASK 0xf000 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY__SHIFT 0xc -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS_MASK 0x20000 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS__SHIFT 0x11 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x3c0000 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x12 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x800000 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x17 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0xf000000 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x18 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x20000000 -+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x1d -+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY_MASK 0xf -+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY__SHIFT 0x0 -+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS_MASK 0x20 -+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS__SHIFT 0x5 -+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY_MASK 0x1ffff000 -+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY__SHIFT 0xc -+#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x3 -+#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x0 -+#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0xc -+#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x2 -+#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x30 -+#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x4 -+#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0xc0 -+#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x6 -+#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x300 -+#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x8 -+#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0xc00 -+#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0xa -+#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x3000 -+#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0xc -+#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0xc000 -+#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0xe -+#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x30000 -+#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x10 -+#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0xc0000 -+#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x12 -+#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x300000 -+#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x14 -+#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0xc00000 -+#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x16 -+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x3000000 -+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x18 -+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0xc000000 -+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x1a -+#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000 -+#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x1c -+#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE_MASK 0xc0000000 -+#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE__SHIFT 0x1e -+#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x3 -+#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x0 -+#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0xc -+#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x2 -+#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x30 -+#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x4 -+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f -+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 -+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 -+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 -+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 -+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 -+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 -+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 -+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 -+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 -+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 -+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 -+#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x400 -+#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0xa -+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 -+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb -+#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x1000 -+#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0xc -+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 -+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd -+#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x4000 -+#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0xe -+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 -+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 -+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 -+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 -+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 -+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 -+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 -+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 -+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 -+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 -+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b -+#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x1 -+#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x0 -+#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x2 -+#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1 -+#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x4 -+#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x2 -+#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x8 -+#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x3 -+#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x10 -+#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x4 -+#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x20 -+#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x5 -+#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x100 -+#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x8 -+#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x200 -+#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x9 -+#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x400 -+#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0xa -+#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x800 -+#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0xb -+#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x1000 -+#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0xc -+#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x2000 -+#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0xd -+#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x4000 -+#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0xe -+#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x8000 -+#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0xf -+#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x10000 -+#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x10 -+#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x20000 -+#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x11 -+#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x40000 -+#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x12 -+#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x80000 -+#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x13 -+#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x100000 -+#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x14 -+#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x200000 -+#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x15 -+#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x400000 -+#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x16 -+#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x800000 -+#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x17 -+#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x1000000 -+#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x18 -+#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x2000000 -+#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x19 -+#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x4000000 -+#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x1a -+#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE_MASK 0x8000000 -+#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1b -+#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE_MASK 0x10000000 -+#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x1c -+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x1 -+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x0 -+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x2 -+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x1 -+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x4 -+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x2 -+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x8 -+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x3 -+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x10 -+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x4 -+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x20 -+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x5 -+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x40 -+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x6 -+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x80 -+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x7 -+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x100 -+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x8 -+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x200 -+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x9 -+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x400 -+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xa -+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x800 -+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xb -+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000 -+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0xc -+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0xc000 -+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0xe -+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x30000 -+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x10 -+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc0000 -+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x12 -+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x300000 -+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x14 -+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0xc00000 -+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x16 -+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x3f -+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x0 -+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x700 -+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x8 -+#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x10000 -+#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x10 -+#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x100000 -+#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x14 -+#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x200000 -+#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x15 -+#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x400000 -+#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x16 -+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff -+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 -+#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0xf -+#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x0 -+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 -+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 -+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 -+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 -+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 -+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 -+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 -+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 -+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 -+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 -+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 -+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 -+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 -+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 -+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 -+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 -+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 -+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 -+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 -+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 -+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 -+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 -+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 -+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE_MASK 0x1 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE__SHIFT 0x0 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN_MASK 0x10 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN__SHIFT 0x4 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK_MASK 0x20 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK__SHIFT 0x5 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN_MASK 0x40 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK_MASK 0xf00 -+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK__SHIFT 0x8 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS_MASK 0x2 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS__SHIFT 0x1 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF_MASK 0x70 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF__SHIFT 0x4 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG_MASK 0xf00 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG__SHIFT 0x8 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE_MASK 0x1fff000 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE__SHIFT 0xc -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF_MASK 0x70000000 -+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF__SHIFT 0x1c -+#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH_MASK 0xffff -+#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH__SHIFT 0x0 -+#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH_MASK 0xffff0000 -+#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH__SHIFT 0x10 -+#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff -+#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 -+#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff -+#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 -+#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff -+#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 -+#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff -+#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 -+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff -+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 -+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 -+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 -+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff -+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 -+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 -+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 -+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff -+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 -+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 -+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 -+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff -+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 -+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 -+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 -+#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff -+#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 -+#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff -+#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 -+#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff -+#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 -+#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff -+#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE_MASK 0x10 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE_MASK 0x80 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE__SHIFT 0x7 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc -+#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 -+#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE_MASK 0x10 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE_MASK 0x80 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE__SHIFT 0x7 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc -+#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 -+#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE_MASK 0x10 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE_MASK 0x80 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE__SHIFT 0x7 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc -+#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 -+#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE_MASK 0x10 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE_MASK 0x80 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE__SHIFT 0x7 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc -+#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 -+#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 -+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE_MASK 0x3 -+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE__SHIFT 0x0 -+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE_MASK 0x30 -+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE__SHIFT 0x4 -+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK_MASK 0xffff -+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0 -+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000 -+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10 -+#define DC_GENERICA__GENERICA_EN_MASK 0x1 -+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 -+#define DC_GENERICA__GENERICA_SEL_MASK 0xf00 -+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x8 -+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 -+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc -+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 -+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 -+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 -+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 -+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 -+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 -+#define DC_GENERICB__GENERICB_EN_MASK 0x1 -+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 -+#define DC_GENERICB__GENERICB_SEL_MASK 0xf00 -+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 -+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 -+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc -+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 -+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 -+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 -+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 -+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 -+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 -+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf -+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 -+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 -+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 -+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 -+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 -+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 -+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 -+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 -+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 -+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 -+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 -+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 -+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 -+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 -+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 -+#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x3 -+#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x0 -+#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0xc -+#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x2 -+#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x30 -+#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x4 -+#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0xc0 -+#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x6 -+#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x300 -+#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x8 -+#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0xc00 -+#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0xa -+#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x3000 -+#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0xc -+#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0xc000 -+#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0xe -+#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x30000 -+#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x10 -+#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0xc0000 -+#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x12 -+#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x300000 -+#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x14 -+#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0xc00000 -+#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x16 -+#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x3000000 -+#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x18 -+#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0xc000000 -+#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x1a -+#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000 -+#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x1c -+#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE_MASK 0x3 -+#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE__SHIFT 0x0 -+#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE_MASK 0xc -+#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE__SHIFT 0x2 -+#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x1 -+#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x0 -+#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x2 -+#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x1 -+#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x4 -+#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x2 -+#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x8 -+#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x3 -+#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x10 -+#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x4 -+#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x20 -+#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x5 -+#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x40 -+#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x6 -+#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x80 -+#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x7 -+#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x100 -+#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x8 -+#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x200 -+#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x9 -+#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x400 -+#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0xa -+#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x800 -+#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0xb -+#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x1000 -+#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0xc -+#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x2000 -+#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0xd -+#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x4000 -+#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0xe -+#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS_MASK 0x8000 -+#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS__SHIFT 0xf -+#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x10000 -+#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x10 -+#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x20000 -+#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x11 -+#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x40000 -+#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x12 -+#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x80000 -+#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x13 -+#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x100000 -+#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x14 -+#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x200000 -+#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x15 -+#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x400000 -+#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x16 -+#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS_MASK 0x800000 -+#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS__SHIFT 0x17 -+#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS_MASK 0x1000000 -+#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS__SHIFT 0x18 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 -+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 -+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e -+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff -+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 -+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 -+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 -+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 -+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 -+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 -+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 -+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 -+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa -+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 -+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 -+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 -+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 -+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 -+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 -+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 -+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c -+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 -+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 -+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 -+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 -+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 -+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 -+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 -+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa -+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 -+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 -+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 -+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 -+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 -+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 -+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 -+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c -+#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0xf -+#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x0 -+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x20 -+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x5 -+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x300 -+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x8 -+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x7000 -+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0xc -+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff -+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 -+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 -+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 -+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 -+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e -+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf -+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 -+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 -+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 -+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 -+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 -+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 -+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc -+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff -+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 -+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 -+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 -+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 -+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e -+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf -+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 -+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 -+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 -+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 -+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 -+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 -+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc -+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff -+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 -+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 -+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 -+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 -+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa -+#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x800 -+#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0xb -+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 -+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd -+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 -+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe -+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 -+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 -+#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 -+#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 -+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 -+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 -+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 -+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa -+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 -+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 -+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 -+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff -+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 -+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 -+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 -+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 -+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 -+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff -+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 -+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 -+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e -+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 -+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f -+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff -+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 -+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 -+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c -+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 -+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e -+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 -+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f -+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff -+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 -+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 -+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 -+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 -+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 -+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 -+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 -+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 -+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 -+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 -+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 -+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 -+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 -+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 -+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 -+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 -+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 -+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 -+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 -+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 -+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 -+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 -+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 -+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 -+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 -+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 -+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff -+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 -+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 -+#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f -+#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0 -+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 -+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 -+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 -+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 -+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 -+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 -+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 -+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 -+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 -+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 -+#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x1000 -+#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0xc -+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 -+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a -+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b -+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c -+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d -+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 -+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e -+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x1000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0xc -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000 -+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e -+#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 -+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f -+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff -+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x1000 -+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0xc -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x8000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0xf -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x100000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x14 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x200000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x15 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x800000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x17 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x2000000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x19 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 -+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b -+#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff -+#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 -+#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff -+#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 -+#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff -+#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 -+#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff -+#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 -+#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff -+#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 -+#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff -+#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 -+#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff -+#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 -+#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff -+#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 -+#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff -+#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 -+#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff -+#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 -+#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff -+#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 -+#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff -+#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 -+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 -+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 -+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 -+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 -+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 -+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 -+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff -+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 -+#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff -+#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 -+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff -+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 -+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 -+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 -+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 -+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 -+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e -+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff -+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 -+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 -+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 -+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 -+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d -+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 -+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e -+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff -+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 -+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 -+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 -+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 -+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d -+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 -+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e -+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff -+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 -+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 -+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 -+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 -+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d -+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 -+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe -+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 -+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 -+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 -+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 -+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 -+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 -+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c -+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 -+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 -+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 -+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 -+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 -+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 -+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 -+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 -+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 -+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 -+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 -+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe -+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 -+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 -+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 -+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 -+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 -+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 -+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c -+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 -+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 -+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 -+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 -+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 -+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 -+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 -+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 -+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 -+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 -+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 -+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe -+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 -+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 -+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 -+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 -+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 -+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 -+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c -+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 -+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 -+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 -+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 -+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 -+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 -+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 -+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 -+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 -+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 -+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 -+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe -+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 -+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 -+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 -+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 -+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 -+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 -+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c -+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 -+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 -+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 -+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 -+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 -+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 -+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 -+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 -+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 -+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 -+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 -+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe -+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 -+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 -+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 -+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 -+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 -+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 -+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c -+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 -+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 -+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 -+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 -+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 -+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 -+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 -+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 -+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 -+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 -+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 -+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe -+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 -+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 -+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 -+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 -+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 -+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 -+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c -+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 -+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 -+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 -+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 -+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 -+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 -+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 -+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 -+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 -+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 -+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 -+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe -+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 -+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 -+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 -+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 -+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 -+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 -+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c -+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 -+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 -+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 -+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 -+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 -+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 -+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 -+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 -+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 -+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 -+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 -+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 -+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c -+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 -+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 -+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 -+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 -+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 -+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 -+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 -+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 -+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 -+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 -+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 -+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 -+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b -+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 -+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 -+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 -+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 -+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 -+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 -+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 -+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 -+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 -+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 -+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 -+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 -+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 -+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 -+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 -+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 -+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 -+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 -+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 -+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 -+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 -+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 -+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 -+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 -+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e -+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a -+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 -+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 -+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 -+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 -+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 -+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 -+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 -+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f -+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf -+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 -+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 -+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 -+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 -+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 -+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 -+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c -+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf -+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 -+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 -+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 -+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 -+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 -+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 -+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc -+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 -+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 -+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 -+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 -+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 -+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e -+#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 -+#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc -+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 -+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe -+#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 -+#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 -+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 -+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 -+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 -+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 -+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 -+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 -+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 -+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 -+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 -+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 -+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 -+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 -+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf -+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 -+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 -+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 -+#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf -+#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0 -+#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0 -+#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4 -+#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00 -+#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8 -+#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000 -+#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc -+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000 -+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10 -+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000 -+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14 -+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000 -+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18 -+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000 -+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c -+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000 -+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d -+#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 -+#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 -+#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 -+#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 -+#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 -+#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 -+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff -+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 -+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x3ff -+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x0 -+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x10000 -+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x10 -+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0xe0000 -+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x11 -+#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x7fffff -+#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x0 -+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x3ff -+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x0 -+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x10000 -+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x10 -+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0xe0000 -+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x11 -+#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x7fffff -+#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x0 -+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x3ff -+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x0 -+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x10000 -+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x10 -+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0xe0000 -+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x11 -+#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x7fffff -+#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x0 -+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN_MASK 0x3ff -+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN__SHIFT 0x0 -+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN_MASK 0x10000 -+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN__SHIFT 0x10 -+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL_MASK 0xe0000 -+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL__SHIFT 0x11 -+#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED_MASK 0x7fffff -+#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED__SHIFT 0x0 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0xf -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x10 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x20 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x40 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x80 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x100 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x200 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x400 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x800 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x1000 -+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0xf -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x10 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x20 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x40 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x80 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x100 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x200 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x400 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x800 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x1000 -+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0xf -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x10 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x20 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x40 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x80 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x100 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x200 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x400 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x800 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x1000 -+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0xf -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x10 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x20 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x40 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x80 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x100 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x200 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x400 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x800 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x1000 -+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc -+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x7 -+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0 -+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_MASK 0x700 -+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH__SHIFT 0x8 -+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x70000 -+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10 -+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_MASK 0x7000000 -+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH__SHIFT 0x18 -+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff -+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 -+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff -+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 -+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff -+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 -+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff -+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000 -+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000 -+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000 -+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x7000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x70000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17 -+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18 -+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000 -+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000 -+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0 -+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2 -+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x4 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000 -+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10 -+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc -+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2 -+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000 -+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a -+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000 -+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc -+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc -+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000 -+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d -+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff -+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0 -+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff -+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0 -+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000 -+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc -+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000 -+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x1000 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0xc -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000 -+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x1c -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000 -+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000 -+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a -+#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 -+#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 -+#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 -+#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 -+#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 -+#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 -+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf -+#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x30000 -+#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x10 -+#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 -+#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 -+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 -+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff -+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0 -+#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 -+#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 -+#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 -+#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 -+#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc -+#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 -+#define GRPH_CONTROL__GRPH_Z_MASK 0x30 -+#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 -+#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 -+#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 -+#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 -+#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 -+#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 -+#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb -+#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 -+#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd -+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 -+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 -+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 -+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 -+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 -+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 -+#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 -+#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 -+#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 -+#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 -+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 -+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d -+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 -+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f -+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 -+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 -+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 -+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 -+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 -+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 -+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 -+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 -+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 -+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 -+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 -+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 -+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 -+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa -+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 -+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 -+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 -+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 -+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 -+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 -+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 -+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 -+#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff -+#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 -+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff -+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 -+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff -+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 -+#define GRPH_X_START__GRPH_X_START_MASK 0x3fff -+#define GRPH_X_START__GRPH_X_START__SHIFT 0x0 -+#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff -+#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 -+#define GRPH_X_END__GRPH_X_END_MASK 0x7fff -+#define GRPH_X_END__GRPH_X_END__SHIFT 0x0 -+#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff -+#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 -+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3 -+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 -+#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30 -+#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4 -+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 -+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 -+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 -+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 -+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 -+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 -+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 -+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 -+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 -+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 -+#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 -+#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 -+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 -+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 -+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 -+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 -+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 -+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c -+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 -+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 -+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 -+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 -+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 -+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 -+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 -+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 -+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 -+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 -+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf -+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 -+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 -+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 -+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 -+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 -+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 -+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 -+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 -+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 -+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 -+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 -+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 -+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 -+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 -+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 -+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff -+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 -+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 -+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 -+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 -+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 -+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define OVL_ENABLE__OVL_ENABLE_MASK 0x1 -+#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0 -+#define OVL_ENABLE__OVLSCL_EN_MASK 0x100 -+#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8 -+#define OVL_CONTROL1__OVL_DEPTH_MASK 0x3 -+#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0 -+#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc -+#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2 -+#define OVL_CONTROL1__OVL_Z_MASK 0x30 -+#define OVL_CONTROL1__OVL_Z__SHIFT 0x4 -+#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0 -+#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6 -+#define OVL_CONTROL1__OVL_FORMAT_MASK 0x700 -+#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8 -+#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800 -+#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb -+#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000 -+#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd -+#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 -+#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 -+#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 -+#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 -+#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000 -+#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12 -+#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000 -+#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14 -+#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000 -+#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18 -+#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000 -+#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19 -+#define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000 -+#define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e -+#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1 -+#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0 -+#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3 -+#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0 -+#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30 -+#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4 -+#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0 -+#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6 -+#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300 -+#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8 -+#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00 -+#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa -+#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1 -+#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0 -+#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00 -+#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8 -+#define OVL_PITCH__OVL_PITCH_MASK 0x7fff -+#define OVL_PITCH__OVL_PITCH__SHIFT 0x0 -+#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff -+#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0 -+#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff -+#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0 -+#define OVL_START__OVL_Y_START_MASK 0x3fff -+#define OVL_START__OVL_Y_START__SHIFT 0x0 -+#define OVL_START__OVL_X_START_MASK 0x3fff0000 -+#define OVL_START__OVL_X_START__SHIFT 0x10 -+#define OVL_END__OVL_Y_END_MASK 0x7fff -+#define OVL_END__OVL_Y_END__SHIFT 0x0 -+#define OVL_END__OVL_X_END_MASK 0x7fff0000 -+#define OVL_END__OVL_X_END__SHIFT 0x10 -+#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1 -+#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0 -+#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2 -+#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1 -+#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000 -+#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10 -+#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 -+#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 -+#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 -+#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8 -+#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1 -+#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0 -+#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70 -+#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4 -+#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700 -+#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 -+#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf -+#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0 -+#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 -+#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 -+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100 -+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8 -+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200 -+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9 -+#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff -+#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0 -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00 -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000 -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14 -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000 -+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 -+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 -+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff -+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 -+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 -+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 -+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff -+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 -+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 -+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 -+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff -+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 -+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 -+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10 -+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4 -+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff -+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0 -+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000 -+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10 -+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff -+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0 -+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000 -+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10 -+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff -+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0 -+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000 -+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10 -+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 -+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 -+#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30 -+#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4 -+#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff -+#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 -+#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 -+#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 -+#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff -+#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 -+#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 -+#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 -+#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff -+#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 -+#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 -+#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 -+#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff -+#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 -+#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 -+#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 -+#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff -+#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 -+#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 -+#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 -+#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff -+#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 -+#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 -+#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 -+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 -+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 -+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70 -+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4 -+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff -+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 -+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 -+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 -+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff -+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 -+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 -+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 -+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff -+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 -+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 -+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 -+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff -+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 -+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 -+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 -+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff -+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 -+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 -+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 -+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff -+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 -+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 -+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 -+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff -+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 -+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 -+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 -+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff -+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 -+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 -+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 -+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff -+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 -+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 -+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 -+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff -+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 -+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 -+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 -+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff -+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 -+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 -+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 -+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff -+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 -+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 -+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 -+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff -+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 -+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 -+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 -+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff -+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 -+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 -+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 -+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff -+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 -+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 -+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 -+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff -+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 -+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 -+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 -+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff -+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 -+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 -+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 -+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff -+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 -+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 -+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 -+#define DENORM_CONTROL__DENORM_MODE_MASK 0x7 -+#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 -+#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 -+#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 -+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf -+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 -+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff -+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 -+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 -+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 -+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff -+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 -+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 -+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 -+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff -+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 -+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 -+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 -+#define KEY_CONTROL__KEY_SELECT_MASK 0x1 -+#define KEY_CONTROL__KEY_SELECT__SHIFT 0x0 -+#define KEY_CONTROL__KEY_MODE_MASK 0x6 -+#define KEY_CONTROL__KEY_MODE__SHIFT 0x1 -+#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000 -+#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c -+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff -+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 -+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 -+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 -+#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff -+#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 -+#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 -+#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 -+#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff -+#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 -+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 -+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 -+#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff -+#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 -+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 -+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 -+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 -+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 -+#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30 -+#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4 -+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 -+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 -+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 -+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc -+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 -+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 -+#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30 -+#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4 -+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff -+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 -+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 -+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 -+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff -+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 -+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 -+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 -+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff -+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 -+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 -+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 -+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff -+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 -+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 -+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 -+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff -+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 -+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 -+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 -+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff -+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 -+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 -+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 -+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa -+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff -+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0 -+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00 -+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8 -+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000 -+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10 -+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff -+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 -+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 -+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 -+#define CUR_CONTROL__CURSOR_EN_MASK 0x1 -+#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 -+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 -+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 -+#define CUR_CONTROL__CURSOR_MODE_MASK 0x300 -+#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 -+#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 -+#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 -+#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 -+#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 -+#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 -+#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 -+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff -+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 -+#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f -+#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 -+#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 -+#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 -+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff -+#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 -+#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 -+#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 -+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f -+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 -+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 -+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 -+#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff -+#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 -+#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 -+#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 -+#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 -+#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 -+#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff -+#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 -+#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 -+#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 -+#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 -+#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 -+#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 -+#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 -+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 -+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 -+#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 -+#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 -+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 -+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 -+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 -+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 -+#define CUR2_CONTROL__CURSOR2_EN_MASK 0x1 -+#define CUR2_CONTROL__CURSOR2_EN__SHIFT 0x0 -+#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP_MASK 0x10 -+#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP__SHIFT 0x4 -+#define CUR2_CONTROL__CURSOR2_MODE_MASK 0x300 -+#define CUR2_CONTROL__CURSOR2_MODE__SHIFT 0x8 -+#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY_MASK 0x10000 -+#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY__SHIFT 0x10 -+#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON_MASK 0x100000 -+#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON__SHIFT 0x14 -+#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL_MASK 0x7000000 -+#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL__SHIFT 0x18 -+#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS_MASK 0xffffffff -+#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS__SHIFT 0x0 -+#define CUR2_SIZE__CURSOR2_HEIGHT_MASK 0x7f -+#define CUR2_SIZE__CURSOR2_HEIGHT__SHIFT 0x0 -+#define CUR2_SIZE__CURSOR2_WIDTH_MASK 0x7f0000 -+#define CUR2_SIZE__CURSOR2_WIDTH__SHIFT 0x10 -+#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define CUR2_POSITION__CURSOR2_Y_POSITION_MASK 0x3fff -+#define CUR2_POSITION__CURSOR2_Y_POSITION__SHIFT 0x0 -+#define CUR2_POSITION__CURSOR2_X_POSITION_MASK 0x3fff0000 -+#define CUR2_POSITION__CURSOR2_X_POSITION__SHIFT 0x10 -+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y_MASK 0x7f -+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y__SHIFT 0x0 -+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X_MASK 0x7f0000 -+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X__SHIFT 0x10 -+#define CUR2_COLOR1__CUR2_COLOR1_BLUE_MASK 0xff -+#define CUR2_COLOR1__CUR2_COLOR1_BLUE__SHIFT 0x0 -+#define CUR2_COLOR1__CUR2_COLOR1_GREEN_MASK 0xff00 -+#define CUR2_COLOR1__CUR2_COLOR1_GREEN__SHIFT 0x8 -+#define CUR2_COLOR1__CUR2_COLOR1_RED_MASK 0xff0000 -+#define CUR2_COLOR1__CUR2_COLOR1_RED__SHIFT 0x10 -+#define CUR2_COLOR2__CUR2_COLOR2_BLUE_MASK 0xff -+#define CUR2_COLOR2__CUR2_COLOR2_BLUE__SHIFT 0x0 -+#define CUR2_COLOR2__CUR2_COLOR2_GREEN_MASK 0xff00 -+#define CUR2_COLOR2__CUR2_COLOR2_GREEN__SHIFT 0x8 -+#define CUR2_COLOR2__CUR2_COLOR2_RED_MASK 0xff0000 -+#define CUR2_COLOR2__CUR2_COLOR2_RED__SHIFT 0x10 -+#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING_MASK 0x1 -+#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING__SHIFT 0x0 -+#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN_MASK 0x2 -+#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN__SHIFT 0x1 -+#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK_MASK 0x10000 -+#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK__SHIFT 0x10 -+#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 -+#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 -+#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE_MASK 0x6000000 -+#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE__SHIFT 0x19 -+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 -+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 -+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 -+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 -+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 -+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 -+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 -+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 -+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 -+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 -+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN_MASK 0x1 -+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN__SHIFT 0x0 -+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX_MASK 0x2 -+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX__SHIFT 0x1 -+#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET_MASK 0x3ff0 -+#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET__SHIFT 0x4 -+#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET_MASK 0x3ff0000 -+#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET__SHIFT 0x10 -+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 -+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 -+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff -+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 -+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff -+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 -+#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff -+#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 -+#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 -+#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 -+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff -+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 -+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 -+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa -+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 -+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 -+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 -+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 -+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 -+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 -+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 -+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 -+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 -+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 -+#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf -+#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 -+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 -+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 -+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 -+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 -+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 -+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 -+#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 -+#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 -+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 -+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc -+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 -+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd -+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 -+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe -+#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 -+#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 -+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 -+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 -+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 -+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 -+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 -+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 -+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff -+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 -+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff -+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 -+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff -+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 -+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff -+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 -+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff -+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 -+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff -+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 -+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 -+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 -+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c -+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 -+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 -+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 -+#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff -+#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 -+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff -+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 -+#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff -+#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 -+#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff -+#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 -+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 -+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 -+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 -+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 -+#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 -+#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 -+#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 -+#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 -+#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 -+#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 -+#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300 -+#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8 -+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 -+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc -+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 -+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 -+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 -+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 -+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 -+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b -+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 -+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c -+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf -+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 -+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0xf0 -+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 -+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1 -+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0 -+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 -+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 -+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1 -+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0 -+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300 -+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8 -+#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000 -+#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10 -+#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000 -+#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11 -+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 -+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c -+#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff -+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 -+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 -+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 -+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 -+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 -+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 -+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 -+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 -+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 -+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 -+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c -+#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff -+#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 -+#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 -+#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 -+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 -+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 -+#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70 -+#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4 -+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff -+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 -+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff -+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 -+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 -+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 -+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff -+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 -+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 -+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 -+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff -+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 -+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff -+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 -+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff -+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 -+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 -+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff -+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 -+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 -+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 -+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff -+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 -+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff -+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 -+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff -+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 -+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 -+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 -+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c -+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 -+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 -+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 -+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 -+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 -+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 -+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff -+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 -+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e -+#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 -+#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 -+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 -+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 -+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 -+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 -+#define DIG_FE_CNTL__DIG_START_MASK 0x400 -+#define DIG_FE_CNTL__DIG_START__SHIFT 0xa -+#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x10000 -+#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x10 -+#define DIG_FE_CNTL__DIG_SWAP_MASK 0x40000 -+#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x12 -+#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x100000 -+#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x14 -+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 -+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 -+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 -+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 -+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 -+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 -+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 -+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 -+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff -+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 -+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff -+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 -+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 -+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 -+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 -+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 -+#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4 -+#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2 -+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 -+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 -+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 -+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 -+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 -+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 -+#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100 -+#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8 -+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 -+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 -+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff -+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 -+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 -+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 -+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 -+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 -+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 -+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 -+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc -+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 -+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 -+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 -+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 -+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa -+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 -+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 -+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 -+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 -+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 -+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d -+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 -+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e -+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 -+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f -+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 -+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 -+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc -+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 -+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 -+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 -+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 -+#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 -+#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 -+#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 -+#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 -+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 -+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 -+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 -+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c -+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 -+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 -+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 -+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 -+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 -+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 -+#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 -+#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b -+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 -+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 -+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 -+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 -+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 -+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 -+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f -+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 -+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 -+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 -+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f -+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 -+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 -+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 -+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 -+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 -+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 -+#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 -+#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 -+#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 -+#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 -+#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 -+#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 -+#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 -+#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 -+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 -+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 -+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c -+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 -+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 -+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 -+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 -+#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 -+#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 -+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 -+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 -+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 -+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 -+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 -+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 -+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 -+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 -+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 -+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 -+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff -+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 -+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 -+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 -+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff -+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 -+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 -+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 -+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 -+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff -+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 -+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 -+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 -+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 -+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 -+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 -+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 -+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 -+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 -+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 -+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 -+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 -+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 -+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 -+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 -+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 -+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc -+#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff -+#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 -+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 -+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc -+#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff -+#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 -+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 -+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc -+#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff -+#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 -+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 -+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc -+#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff -+#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 -+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 -+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 -+#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 -+#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 -+#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 -+#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 -+#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 -+#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 -+#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 -+#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 -+#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 -+#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 -+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 -+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 -+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 -+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 -+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 -+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 -+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 -+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 -+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 -+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c -+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf -+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 -+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 -+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 -+#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 -+#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 -+#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 -+#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 -+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 -+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 -+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 -+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff -+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 -+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 -+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f -+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff -+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 -+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 -+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 -+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff -+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 -+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff -+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 -+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 -+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 -+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 -+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 -+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 -+#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 -+#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 -+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 -+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 -+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 -+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 -+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 -+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 -+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f -+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 -+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 -+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 -+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 -+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 -+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e -+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 -+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 -+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 -+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 -+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 -+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa -+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 -+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 -+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 -+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 -+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 -+#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 -+#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 -+#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 -+#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c -+#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 -+#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 -+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 -+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 -+#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 -+#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 -+#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10 -+#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x4 -+#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x300 -+#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x8 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 -+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 -+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 -+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 -+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 -+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 -+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 -+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 -+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff -+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 -+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 -+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 -+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff -+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 -+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 -+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 -+#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 -+#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 -+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 -+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 -+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 -+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 -+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 -+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 -+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 -+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 -+#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 -+#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 -+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 -+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 -+#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 -+#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 -+#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 -+#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 -+#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 -+#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 -+#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 -+#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 -+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 -+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 -+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 -+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 -+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c -+#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1 -+#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0 -+#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10 -+#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4 -+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100 -+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8 -+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200 -+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9 -+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400 -+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa -+#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000 -+#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc -+#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000 -+#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10 -+#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000 -+#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11 -+#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000 -+#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12 -+#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 -+#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 -+#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 -+#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 -+#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 -+#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 -+#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 -+#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 -+#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 -+#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 -+#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffff -+#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x0 -+#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffff -+#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x0 -+#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffff -+#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x0 -+#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffff -+#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x0 -+#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffff -+#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x0 -+#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffff -+#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x0 -+#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffff -+#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x0 -+#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffff -+#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x0 -+#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 -+#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 -+#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 -+#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 -+#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x1 -+#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x0 -+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x2 -+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x1 -+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x10 -+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x4 -+#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x100 -+#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x8 -+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 -+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc -+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 -+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x0 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x100 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x8 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x10000 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x10 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x100000 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x14 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x1000000 -+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x18 -+#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x1fff -+#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x0 -+#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x3ff0000 -+#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x10 -+#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000 -+#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x1c -+#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x1 -+#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x0 -+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x2 -+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x1 -+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x10 -+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x4 -+#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x100 -+#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x8 -+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 -+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc -+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 -+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x1 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x0 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x100 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x8 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x10000 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x10 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x100000 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x14 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x1000000 -+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x18 -+#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x1fff -+#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x0 -+#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x3ff0000 -+#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x10 -+#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000 -+#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x1c -+#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x1 -+#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x0 -+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x2 -+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x1 -+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x10 -+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x4 -+#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x100 -+#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x8 -+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 -+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc -+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 -+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x1 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x0 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x100 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x8 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x10000 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x10 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x100000 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x14 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x1000000 -+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x18 -+#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x1fff -+#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x0 -+#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x3ff0000 -+#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x10 -+#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000 -+#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x1c -+#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x1 -+#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x0 -+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x2 -+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x1 -+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x10 -+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x4 -+#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x100 -+#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x8 -+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 -+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc -+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 -+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x1 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x0 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x100 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x8 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x10000 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x10 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x100000 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x14 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x1000000 -+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x18 -+#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x1fff -+#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x0 -+#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x3ff0000 -+#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x10 -+#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000 -+#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x1c -+#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x1 -+#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x0 -+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x2 -+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x1 -+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x10 -+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x4 -+#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x100 -+#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x8 -+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 -+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc -+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 -+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x1 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x0 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x100 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x8 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x10000 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x10 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x100000 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x14 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x1000000 -+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x18 -+#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x1fff -+#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x0 -+#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x3ff0000 -+#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x10 -+#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000 -+#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x1c -+#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x1 -+#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x0 -+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x2 -+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x1 -+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x10 -+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x4 -+#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x100 -+#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x8 -+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 -+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc -+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 -+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x1 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x0 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x100 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x8 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x10000 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x10 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x100000 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x14 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x1000000 -+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x18 -+#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x1fff -+#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x0 -+#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x3ff0000 -+#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x10 -+#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000 -+#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x1c -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0xff -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x0 -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x1000000 -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x18 -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 -+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0xff -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x0 -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x1000000 -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x18 -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 -+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0xff -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x0 -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x1000000 -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x18 -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 -+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0xff -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x0 -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x1000000 -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x18 -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 -+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0xff -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x0 -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x1000000 -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x18 -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 -+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0xff -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x0 -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x1000000 -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x18 -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 -+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c -+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0xff -+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x0 -+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0xff00000 -+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x14 -+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0xff -+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x0 -+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0xff00000 -+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x14 -+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0xff -+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x0 -+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0xff00000 -+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x14 -+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0xff -+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x0 -+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0xff00000 -+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x14 -+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0xff -+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x0 -+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0xff00000 -+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x14 -+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0xff -+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x0 -+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0xff00000 -+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x14 -+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 -+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 -+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 -+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 -+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 -+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 -+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 -+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 -+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 -+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 -+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 -+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 -+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 -+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f -+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 -+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 -+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc -+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 -+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 -+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 -+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 -+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 -+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 -+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc -+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 -+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 -+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 -+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 -+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 -+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 -+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 -+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 -+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d -+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf -+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 -+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 -+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 -+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 -+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 -+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 -+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 -+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c -+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 -+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 -+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 -+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 -+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 -+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 -+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 -+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 -+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 -+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 -+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 -+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 -+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 -+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 -+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 -+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 -+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 -+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 -+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 -+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 -+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 -+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 -+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 -+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 -+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 -+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 -+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 -+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 -+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 -+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 -+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 -+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 -+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 -+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 -+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 -+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc -+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 -+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd -+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000 -+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 -+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 -+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 -+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 -+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 -+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 -+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc -+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 -+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd -+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000 -+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 -+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 -+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 -+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 -+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 -+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 -+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc -+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 -+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd -+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000 -+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 -+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 -+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 -+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 -+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 -+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 -+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc -+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 -+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd -+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000 -+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 -+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 -+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 -+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 -+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 -+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000 -+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 -+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 -+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 -+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f -+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 -+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 -+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 -+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 -+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 -+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf -+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 -+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa -+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 -+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 -+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 -+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 -+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 -+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 -+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 -+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 -+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 -+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 -+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 -+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 -+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 -+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f -+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f -+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 -+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 -+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 -+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a -+#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 -+#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b -+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 -+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 -+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 -+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x8000000 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x1b -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000 -+#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x1e -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 -+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c -+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 -+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 -+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 -+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 -+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 -+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 -+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 -+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff -+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 -+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 -+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 -+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 -+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c -+#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 -+#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 -+#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 -+#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 -+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0xff -+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x0 -+#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffff -+#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x0 -+#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffff -+#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x0 -+#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffff -+#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x0 -+#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffff -+#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x0 -+#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffff -+#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x0 -+#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffff -+#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x0 -+#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffff -+#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x0 -+#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffff -+#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x0 -+#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffff -+#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x0 -+#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J_MASK 0xffffffff -+#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J__SHIFT 0x0 -+#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K_MASK 0xffffffff -+#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K__SHIFT 0x0 -+#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L_MASK 0xffffffff -+#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L__SHIFT 0x0 -+#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M_MASK 0xffffffff -+#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M__SHIFT 0x0 -+#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N_MASK 0xffffffff -+#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N__SHIFT 0x0 -+#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O_MASK 0xffffffff -+#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O__SHIFT 0x0 -+#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P_MASK 0xffffffff -+#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P__SHIFT 0x0 -+#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q_MASK 0xffffffff -+#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q__SHIFT 0x0 -+#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffff -+#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x0 -+#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffff -+#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x0 -+#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffff -+#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x0 -+#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffff -+#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x0 -+#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffff -+#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x0 -+#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffff -+#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x0 -+#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffff -+#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x0 -+#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffff -+#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x0 -+#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffff -+#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x0 -+#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J_MASK 0xffffffff -+#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J__SHIFT 0x0 -+#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K_MASK 0xffffffff -+#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K__SHIFT 0x0 -+#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L_MASK 0xffffffff -+#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L__SHIFT 0x0 -+#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M_MASK 0xffffffff -+#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M__SHIFT 0x0 -+#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N_MASK 0xffffffff -+#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N__SHIFT 0x0 -+#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O_MASK 0xffffffff -+#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O__SHIFT 0x0 -+#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P_MASK 0xffffffff -+#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P__SHIFT 0x0 -+#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q_MASK 0xffffffff -+#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q__SHIFT 0x0 -+#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffff -+#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x0 -+#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffff -+#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x0 -+#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffff -+#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x0 -+#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffff -+#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x0 -+#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffff -+#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x0 -+#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffff -+#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x0 -+#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffff -+#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x0 -+#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffff -+#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x0 -+#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffff -+#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x0 -+#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J_MASK 0xffffffff -+#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J__SHIFT 0x0 -+#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K_MASK 0xffffffff -+#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K__SHIFT 0x0 -+#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L_MASK 0xffffffff -+#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L__SHIFT 0x0 -+#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M_MASK 0xffffffff -+#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M__SHIFT 0x0 -+#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N_MASK 0xffffffff -+#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N__SHIFT 0x0 -+#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O_MASK 0xffffffff -+#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O__SHIFT 0x0 -+#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P_MASK 0xffffffff -+#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P__SHIFT 0x0 -+#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q_MASK 0xffffffff -+#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q__SHIFT 0x0 -+#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffff -+#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x0 -+#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffff -+#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x0 -+#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffff -+#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x0 -+#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffff -+#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x0 -+#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffff -+#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x0 -+#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffff -+#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x0 -+#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffff -+#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x0 -+#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffff -+#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x0 -+#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffff -+#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x0 -+#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J_MASK 0xffffffff -+#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J__SHIFT 0x0 -+#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K_MASK 0xffffffff -+#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K__SHIFT 0x0 -+#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L_MASK 0xffffffff -+#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L__SHIFT 0x0 -+#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M_MASK 0xffffffff -+#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M__SHIFT 0x0 -+#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N_MASK 0xffffffff -+#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N__SHIFT 0x0 -+#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O_MASK 0xffffffff -+#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O__SHIFT 0x0 -+#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P_MASK 0xffffffff -+#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P__SHIFT 0x0 -+#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q_MASK 0xffffffff -+#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q__SHIFT 0x0 -+#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffff -+#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x0 -+#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffff -+#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x0 -+#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffff -+#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x0 -+#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffff -+#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x0 -+#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffff -+#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x0 -+#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffff -+#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x0 -+#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffff -+#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x0 -+#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffff -+#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x0 -+#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffff -+#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x0 -+#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J_MASK 0xffffffff -+#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J__SHIFT 0x0 -+#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K_MASK 0xffffffff -+#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K__SHIFT 0x0 -+#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L_MASK 0xffffffff -+#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L__SHIFT 0x0 -+#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M_MASK 0xffffffff -+#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M__SHIFT 0x0 -+#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N_MASK 0xffffffff -+#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N__SHIFT 0x0 -+#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O_MASK 0xffffffff -+#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O__SHIFT 0x0 -+#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P_MASK 0xffffffff -+#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P__SHIFT 0x0 -+#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q_MASK 0xffffffff -+#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q__SHIFT 0x0 -+#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffff -+#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x0 -+#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffff -+#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x0 -+#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffff -+#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x0 -+#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffff -+#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x0 -+#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffff -+#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x0 -+#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffff -+#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x0 -+#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffff -+#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x0 -+#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffff -+#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x0 -+#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffff -+#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x0 -+#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J_MASK 0xffffffff -+#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J__SHIFT 0x0 -+#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K_MASK 0xffffffff -+#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K__SHIFT 0x0 -+#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L_MASK 0xffffffff -+#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L__SHIFT 0x0 -+#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M_MASK 0xffffffff -+#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M__SHIFT 0x0 -+#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N_MASK 0xffffffff -+#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N__SHIFT 0x0 -+#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O_MASK 0xffffffff -+#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O__SHIFT 0x0 -+#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P_MASK 0xffffffff -+#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P__SHIFT 0x0 -+#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q_MASK 0xffffffff -+#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q__SHIFT 0x0 -+#define DMCU_CTRL__RESET_UC_MASK 0x1 -+#define DMCU_CTRL__RESET_UC__SHIFT 0x0 -+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 -+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 -+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 -+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 -+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 -+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 -+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 -+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 -+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000 -+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x16 -+#define DMCU_STATUS__UC_IN_RESET_MASK 0x1 -+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 -+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 -+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 -+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 -+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 -+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff -+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 -+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 -+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 -+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff -+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 -+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 -+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 -+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff -+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 -+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 -+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 -+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff -+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 -+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 -+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 -+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff -+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 -+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff -+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 -+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 -+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 -+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 -+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 -+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 -+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 -+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 -+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 -+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 -+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 -+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 -+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 -+#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00 -+#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8 -+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff -+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 -+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 -+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 -+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 -+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 -+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff -+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 -+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff -+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 -+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 -+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 -+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 -+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 -+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff -+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 -+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff -+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 -+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff -+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 -+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff -+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 -+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff -+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 -+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 -+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 -+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 -+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 -+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 -+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 -+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x1 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x0 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x2 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x1 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x4 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x2 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x8 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0x3 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x10 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0x4 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x20 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x5 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x100 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x8 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x200 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0x9 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x400 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xa -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x800 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0xb -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 -+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 -+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 -+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 -+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 -+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 -+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 -+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 -+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 -+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 -+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 -+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 -+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 -+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 -+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 -+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 -+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 -+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 -+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 -+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 -+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 -+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 -+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 -+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa -+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 -+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa -+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 -+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb -+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 -+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 -+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 -+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 -+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 -+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 -+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 -+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a -+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a -+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b -+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b -+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c -+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c -+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d -+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 -+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000 -+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 -+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 -+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d -+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff -+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 -+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff -+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 -+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 -+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 -+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 -+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 -+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 -+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 -+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc -+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 -+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 -+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 -+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 -+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 -+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 -+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 -+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 -+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 -+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 -+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 -+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 -+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 -+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 -+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 -+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 -+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 -+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 -+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 -+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 -+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 -+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff -+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK_MASK 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK_MASK 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK_MASK 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK_MASK 0x8 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK_MASK 0x10 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK_MASK 0x20 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK_MASK 0x40 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK_MASK 0x80 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 -+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 -+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 -+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 -+#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 -+#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 -+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 -+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 -+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 -+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 -+#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 -+#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 -+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 -+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 -+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 -+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 -+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff -+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 -+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 -+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 -+#define DP_CONFIG__DP_UDI_LANES_MASK 0x3 -+#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 -+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 -+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 -+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 -+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 -+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 -+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 -+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 -+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc -+#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 -+#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 -+#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 -+#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 -+#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 -+#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 -+#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 -+#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 -+#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 -+#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 -+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 -+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 -+#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 -+#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 -+#define DP_VID_N__DP_VID_N_MASK 0xffffff -+#define DP_VID_N__DP_VID_N__SHIFT 0x0 -+#define DP_VID_M__DP_VID_M_MASK 0xffffff -+#define DP_VID_M__DP_VID_M__SHIFT 0x0 -+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff -+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 -+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 -+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 -+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 -+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c -+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 -+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 -+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff -+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 -+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 -+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 -+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 -+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 -+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 -+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 -+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 -+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 -+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 -+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 -+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 -+#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 -+#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 -+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 -+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 -+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 -+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 -+#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff -+#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 -+#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 -+#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa -+#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 -+#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 -+#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff -+#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 -+#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 -+#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa -+#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 -+#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 -+#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff -+#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 -+#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 -+#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa -+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 -+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 -+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 -+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 -+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 -+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 -+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 -+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 -+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 -+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 -+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 -+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 -+#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 -+#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 -+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 -+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 -+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 -+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 -+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 -+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 -+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 -+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 -+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 -+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 -+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 -+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f -+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 -+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 -+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 -+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 -+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 -+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 -+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 -+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 -+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 -+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 -+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 -+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 -+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 -+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 -+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 -+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 -+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 -+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 -+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 -+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc -+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 -+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 -+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x1fff0 -+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 -+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x1fff -+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 -+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000 -+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 -+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 -+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 -+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 -+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 -+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 -+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 -+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 -+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc -+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 -+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 -+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 -+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 -+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 -+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 -+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 -+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 -+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 -+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 -+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 -+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 -+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 -+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c -+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 -+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 -+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff -+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 -+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 -+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 -+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff -+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 -+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 -+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 -+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff -+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 -+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 -+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 -+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 -+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 -+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 -+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 -+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 -+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c -+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 -+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d -+#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff -+#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 -+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff -+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 -+#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff -+#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 -+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff -+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 -+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 -+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 -+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe -+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 -+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 -+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 -+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 -+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 -+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 -+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 -+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff -+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 -+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 -+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a -+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 -+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 -+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 -+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 -+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 -+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 -+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 -+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 -+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 -+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 -+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 -+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 -+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 -+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 -+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 -+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 -+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 -+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 -+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 -+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 -+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 -+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 -+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 -+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 -+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 -+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 -+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 -+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 -+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 -+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 -+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff -+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 -+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 -+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 -+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 -+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 -+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 -+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 -+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 -+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 -+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff -+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 -+#define AUX_CONTROL__AUX_EN_MASK 0x1 -+#define AUX_CONTROL__AUX_EN__SHIFT 0x0 -+#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 -+#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 -+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 -+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc -+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 -+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 -+#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 -+#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 -+#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 -+#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 -+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 -+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 -+#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 -+#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c -+#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 -+#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d -+#define AUX_CONTROL__SPARE_0_MASK 0x40000000 -+#define AUX_CONTROL__SPARE_0__SHIFT 0x1e -+#define AUX_CONTROL__SPARE_1_MASK 0x80000000 -+#define AUX_CONTROL__SPARE_1__SHIFT 0x1f -+#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 -+#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 -+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 -+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 -+#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 -+#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 -+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 -+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 -+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 -+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 -+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc -+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 -+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 -+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 -+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 -+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa -+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 -+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 -+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 -+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 -+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 -+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 -+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 -+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 -+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 -+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 -+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 -+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 -+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 -+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 -+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 -+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 -+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 -+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 -+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 -+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 -+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 -+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 -+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 -+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 -+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe -+#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 -+#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 -+#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 -+#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 -+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 -+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 -+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 -+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 -+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 -+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 -+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 -+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 -+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 -+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa -+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 -+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb -+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 -+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc -+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 -+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe -+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 -+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 -+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 -+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 -+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 -+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 -+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 -+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 -+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 -+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 -+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 -+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 -+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 -+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 -+#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 -+#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e -+#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 -+#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 -+#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 -+#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 -+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 -+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 -+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 -+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 -+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 -+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 -+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 -+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 -+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 -+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa -+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 -+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb -+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 -+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc -+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 -+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe -+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 -+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 -+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 -+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 -+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 -+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 -+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 -+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 -+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 -+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 -+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 -+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 -+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 -+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 -+#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 -+#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d -+#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 -+#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e -+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 -+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f -+#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 -+#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 -+#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 -+#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 -+#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 -+#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 -+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 -+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f -+#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 -+#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 -+#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 -+#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 -+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 -+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 -+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 -+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 -+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 -+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 -+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 -+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 -+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 -+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 -+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 -+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 -+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c -+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff -+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 -+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 -+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 -+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 -+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 -+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 -+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 -+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 -+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 -+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 -+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 -+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 -+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 -+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 -+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000 -+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 -+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 -+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 -+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e -+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1 -+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0 -+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00 -+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8 -+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000 -+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10 -+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000 -+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f -+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1 -+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0 -+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0 -+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4 -+#define DVO_ENABLE__DVO_ENABLE_MASK 0x1 -+#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 -+#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 -+#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 -+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 -+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 -+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 -+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 -+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 -+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 -+#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 -+#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 -+#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 -+#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 -+#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 -+#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 -+#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 -+#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 -+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 -+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 -+#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 -+#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 -+#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 -+#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 -+#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 -+#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 -+#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 -+#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 -+#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 -+#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 -+#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 -+#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 -+#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 -+#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 -+#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 -+#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f -+#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 -+#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 -+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff -+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 -+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff -+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 -+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f -+#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 -+#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 -+#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe -+#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 -+#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 -+#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 -+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 -+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 -+#define FBC_CNTL__FBC_EN_MASK 0x80000000 -+#define FBC_CNTL__FBC_EN__SHIFT 0x1f -+#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff -+#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0 -+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff -+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 -+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f -+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 -+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 -+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 -+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 -+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 -+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf -+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 -+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 -+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 -+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 -+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 -+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 -+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 -+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 -+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 -+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 -+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 -+#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 -+#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 -+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 -+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 -+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 -+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 -+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 -+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa -+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 -+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb -+#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 -+#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 -+#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff -+#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 -+#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 -+#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 -+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 -+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 -+#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 -+#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 -+#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 -+#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 -+#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff -+#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 -+#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff -+#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 -+#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff -+#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 -+#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff -+#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 -+#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff -+#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 -+#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff -+#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 -+#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff -+#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 -+#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff -+#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 -+#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff -+#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 -+#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff -+#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 -+#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff -+#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 -+#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff -+#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 -+#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff -+#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 -+#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff -+#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 -+#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff -+#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 -+#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff -+#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 -+#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff -+#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 -+#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff -+#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 -+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff -+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 -+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000 -+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 -+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff -+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 -+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000 -+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 -+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 -+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 -+#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 -+#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 -+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 -+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 -+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 -+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 -+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 -+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 -+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 -+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa -+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 -+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 -+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f -+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff -+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 -+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff -+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 -+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff -+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 -+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff -+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 -+#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 -+#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 -+#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 -+#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 -+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 -+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 -+#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 -+#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 -+#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 -+#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 -+#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 -+#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa -+#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 -+#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb -+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 -+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc -+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 -+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 -+#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 -+#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 -+#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 -+#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 -+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000 -+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x1c -+#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 -+#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 -+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff -+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff -+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 -+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff -+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 -+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 -+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 -+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff -+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 -+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 -+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 -+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff -+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 -+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 -+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 -+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 -+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 -+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 -+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 -+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 -+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 -+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 -+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 -+#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000 -+#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 -+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000 -+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11 -+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000 -+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12 -+#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 -+#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1 -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0 -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700 -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8 -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000 -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x10000 -+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x10 -+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff -+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0 -+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000 -+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10 -+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff -+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0 -+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000 -+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 -+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 -+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 -+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 -+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 -+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 -+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb -+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd -+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe -+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 -+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a -+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c -+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 -+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e -+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff -+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 -+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 -+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 -+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff -+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 -+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 -+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 -+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff -+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 -+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 -+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 -+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1 -+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0 -+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10 -+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4 -+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff -+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0 -+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff -+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0 -+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 -+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 -+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 -+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 -+#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 -+#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 -+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 -+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 -+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 -+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 -+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x100 -+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x8 -+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 -+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc -+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 -+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 -+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 -+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 -+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 -+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 -+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff -+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 -+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 -+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 -+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff -+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 -+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 -+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 -+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff -+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 -+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 -+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 -+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff -+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 -+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 -+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 -+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 -+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 -+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff -+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff -+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 -+#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff -+#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 -+#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff -+#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 -+#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff -+#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 -+#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff -+#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 -+#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 -+#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 -+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 -+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 -+#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 -+#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 -+#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 -+#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc -+#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 -+#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 -+#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 -+#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f -+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff -+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 -+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 -+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 -+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 -+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 -+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff -+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 -+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff -+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 -+#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff -+#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 -+#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 -+#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 -+#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 -+#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f -+#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff -+#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 -+#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 -+#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 -+#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 -+#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f -+#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff -+#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 -+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff -+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 -+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 -+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 -+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 -+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 -+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 -+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 -+#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 -+#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 -+#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 -+#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 -+#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 -+#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc -+#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 -+#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 -+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 -+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 -+#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 -+#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 -+#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 -+#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 -+#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 -+#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc -+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 -+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 -+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 -+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 -+#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 -+#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 -+#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 -+#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 -+#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 -+#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc -+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 -+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 -+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 -+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 -+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 -+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 -+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 -+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 -+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 -+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 -+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 -+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 -+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 -+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 -+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 -+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 -+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 -+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 -+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 -+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 -+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 -+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 -+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 -+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 -+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 -+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 -+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 -+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 -+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 -+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 -+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 -+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 -+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 -+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 -+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f -+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 -+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 -+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa -+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 -+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 -+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 -+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c -+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff -+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 -+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 -+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 -+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff -+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 -+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 -+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 -+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc -+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 -+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 -+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 -+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 -+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 -+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 -+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 -+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 -+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 -+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 -+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 -+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e -+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 -+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 -+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c -+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 -+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f -+#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff -+#define LB_DEBUG__LB_DEBUG__SHIFT 0x0 -+#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff -+#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 -+#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff -+#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 -+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff -+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff -+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 -+#define MVP_CONTROL1__MVP_EN_MASK 0x1 -+#define MVP_CONTROL1__MVP_EN__SHIFT 0x0 -+#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 -+#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 -+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 -+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 -+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 -+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 -+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 -+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa -+#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 -+#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc -+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 -+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 -+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 -+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 -+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 -+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 -+#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 -+#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c -+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 -+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e -+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 -+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f -+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 -+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 -+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 -+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 -+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 -+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 -+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 -+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc -+#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 -+#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 -+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 -+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 -+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 -+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 -+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 -+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c -+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff -+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 -+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 -+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 -+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 -+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 -+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff -+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 -+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 -+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 -+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 -+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc -+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 -+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 -+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 -+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 -+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 -+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 -+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 -+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c -+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 -+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e -+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 -+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f -+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff -+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 -+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 -+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 -+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 -+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 -+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 -+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 -+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 -+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 -+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff -+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 -+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 -+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa -+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 -+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 -+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff -+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 -+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 -+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 -+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 -+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 -+#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 -+#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c -+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 -+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d -+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 -+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e -+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff -+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 -+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 -+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 -+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff -+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 -+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 -+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 -+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 -+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 -+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 -+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 -+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 -+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 -+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c -+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff -+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 -+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 -+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 -+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 -+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f -+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff -+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 -+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 -+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f -+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 -+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 -+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 -+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 -+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 -+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 -+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 -+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 -+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 -+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 -+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 -+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 -+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 -+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 -+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 -+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 -+#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 -+#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 -+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff -+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff -+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 -+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6 -+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 -+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6 -+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 -+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 -+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 -+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe -+#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 -+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 -+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 -+#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe -+#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 -+#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 -+#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 -+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 -+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a -+#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 -+#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b -+#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 -+#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 -+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 -+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 -+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 -+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 -+#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 -+#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 -+#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 -+#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa -+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 -+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb -+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 -+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc -+#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 -+#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd -+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 -+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe -+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 -+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf -+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 -+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 -+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 -+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 -+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 -+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 -+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 -+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 -+#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 -+#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 -+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 -+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 -+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 -+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 -+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 -+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 -+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 -+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 -+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 -+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 -+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 -+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc -+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 -+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf -+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 -+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 -+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 -+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 -+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 -+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f -+#define SCL_MODE__SCL_MODE_MASK 0x3 -+#define SCL_MODE__SCL_MODE__SHIFT 0x0 -+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 -+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 -+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 -+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 -+#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 -+#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 -+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 -+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 -+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf -+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 -+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 -+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 -+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 -+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 -+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 -+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 -+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 -+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 -+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 -+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 -+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff -+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 -+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff -+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 -+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 -+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 -+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 -+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 -+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 -+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 -+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff -+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 -+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff -+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 -+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 -+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 -+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff -+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 -+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 -+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 -+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff -+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 -+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 -+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 -+#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 -+#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 -+#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 -+#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 -+#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 -+#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 -+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 -+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 -+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 -+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 -+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 -+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 -+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 -+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 -+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 -+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc -+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 -+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 -+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 -+#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff -+#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 -+#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 -+#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 -+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff -+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 -+#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 -+#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 -+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff -+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 -+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 -+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 -+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff -+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 -+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 -+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 -+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 -+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 -+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 -+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 -+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 -+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 -+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff -+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 -+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff -+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 -+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 -+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 -+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 -+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 -+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 -+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 -+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 -+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 -+#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 -+#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 -+#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff -+#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 -+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff -+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff -+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 -+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 -+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 -+#define GENMO_WT__VGA_RAM_EN_MASK 0x2 -+#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 -+#define GENMO_WT__VGA_CKSEL_MASK 0xc -+#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 -+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 -+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 -+#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 -+#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 -+#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 -+#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 -+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 -+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 -+#define GENMO_RD__VGA_RAM_EN_MASK 0x2 -+#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 -+#define GENMO_RD__VGA_CKSEL_MASK 0xc -+#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 -+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 -+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 -+#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 -+#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 -+#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 -+#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 -+#define GENENB__BLK_IO_BASE_MASK 0xff -+#define GENENB__BLK_IO_BASE__SHIFT 0x0 -+#define GENFC_WT__VSYNC_SEL_W_MASK 0x8 -+#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 -+#define GENFC_RD__VSYNC_SEL_R_MASK 0x8 -+#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 -+#define GENS0__SENSE_SWITCH_MASK 0x10 -+#define GENS0__SENSE_SWITCH__SHIFT 0x4 -+#define GENS0__CRT_INTR_MASK 0x80 -+#define GENS0__CRT_INTR__SHIFT 0x7 -+#define GENS1__NO_DISPLAY_MASK 0x1 -+#define GENS1__NO_DISPLAY__SHIFT 0x0 -+#define GENS1__VGA_VSTATUS_MASK 0x8 -+#define GENS1__VGA_VSTATUS__SHIFT 0x3 -+#define GENS1__PIXEL_READ_BACK_MASK 0x30 -+#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 -+#define DAC_DATA__DAC_DATA_MASK 0x3f -+#define DAC_DATA__DAC_DATA__SHIFT 0x0 -+#define DAC_MASK__DAC_MASK_MASK 0xff -+#define DAC_MASK__DAC_MASK__SHIFT 0x0 -+#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff -+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 -+#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff -+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 -+#define SEQ8_IDX__SEQ_IDX_MASK 0x7 -+#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 -+#define SEQ8_DATA__SEQ_DATA_MASK 0xff -+#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 -+#define SEQ00__SEQ_RST0B_MASK 0x1 -+#define SEQ00__SEQ_RST0B__SHIFT 0x0 -+#define SEQ00__SEQ_RST1B_MASK 0x2 -+#define SEQ00__SEQ_RST1B__SHIFT 0x1 -+#define SEQ01__SEQ_DOT8_MASK 0x1 -+#define SEQ01__SEQ_DOT8__SHIFT 0x0 -+#define SEQ01__SEQ_SHIFT2_MASK 0x4 -+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 -+#define SEQ01__SEQ_PCLKBY2_MASK 0x8 -+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 -+#define SEQ01__SEQ_SHIFT4_MASK 0x10 -+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 -+#define SEQ01__SEQ_MAXBW_MASK 0x20 -+#define SEQ01__SEQ_MAXBW__SHIFT 0x5 -+#define SEQ02__SEQ_MAP0_EN_MASK 0x1 -+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 -+#define SEQ02__SEQ_MAP1_EN_MASK 0x2 -+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 -+#define SEQ02__SEQ_MAP2_EN_MASK 0x4 -+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 -+#define SEQ02__SEQ_MAP3_EN_MASK 0x8 -+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 -+#define SEQ03__SEQ_FONT_B1_MASK 0x1 -+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 -+#define SEQ03__SEQ_FONT_B2_MASK 0x2 -+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 -+#define SEQ03__SEQ_FONT_A1_MASK 0x4 -+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 -+#define SEQ03__SEQ_FONT_A2_MASK 0x8 -+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 -+#define SEQ03__SEQ_FONT_B0_MASK 0x10 -+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 -+#define SEQ03__SEQ_FONT_A0_MASK 0x20 -+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 -+#define SEQ04__SEQ_256K_MASK 0x2 -+#define SEQ04__SEQ_256K__SHIFT 0x1 -+#define SEQ04__SEQ_ODDEVEN_MASK 0x4 -+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 -+#define SEQ04__SEQ_CHAIN_MASK 0x8 -+#define SEQ04__SEQ_CHAIN__SHIFT 0x3 -+#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f -+#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 -+#define CRTC8_DATA__VCRTC_DATA_MASK 0xff -+#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 -+#define CRT00__H_TOTAL_MASK 0xff -+#define CRT00__H_TOTAL__SHIFT 0x0 -+#define CRT01__H_DISP_END_MASK 0xff -+#define CRT01__H_DISP_END__SHIFT 0x0 -+#define CRT02__H_BLANK_START_MASK 0xff -+#define CRT02__H_BLANK_START__SHIFT 0x0 -+#define CRT03__H_BLANK_END_MASK 0x1f -+#define CRT03__H_BLANK_END__SHIFT 0x0 -+#define CRT03__H_DE_SKEW_MASK 0x60 -+#define CRT03__H_DE_SKEW__SHIFT 0x5 -+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80 -+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 -+#define CRT04__H_SYNC_START_MASK 0xff -+#define CRT04__H_SYNC_START__SHIFT 0x0 -+#define CRT05__H_SYNC_END_MASK 0x1f -+#define CRT05__H_SYNC_END__SHIFT 0x0 -+#define CRT05__H_SYNC_SKEW_MASK 0x60 -+#define CRT05__H_SYNC_SKEW__SHIFT 0x5 -+#define CRT05__H_BLANK_END_B5_MASK 0x80 -+#define CRT05__H_BLANK_END_B5__SHIFT 0x7 -+#define CRT06__V_TOTAL_MASK 0xff -+#define CRT06__V_TOTAL__SHIFT 0x0 -+#define CRT07__V_TOTAL_B8_MASK 0x1 -+#define CRT07__V_TOTAL_B8__SHIFT 0x0 -+#define CRT07__V_DISP_END_B8_MASK 0x2 -+#define CRT07__V_DISP_END_B8__SHIFT 0x1 -+#define CRT07__V_SYNC_START_B8_MASK 0x4 -+#define CRT07__V_SYNC_START_B8__SHIFT 0x2 -+#define CRT07__V_BLANK_START_B8_MASK 0x8 -+#define CRT07__V_BLANK_START_B8__SHIFT 0x3 -+#define CRT07__LINE_CMP_B8_MASK 0x10 -+#define CRT07__LINE_CMP_B8__SHIFT 0x4 -+#define CRT07__V_TOTAL_B9_MASK 0x20 -+#define CRT07__V_TOTAL_B9__SHIFT 0x5 -+#define CRT07__V_DISP_END_B9_MASK 0x40 -+#define CRT07__V_DISP_END_B9__SHIFT 0x6 -+#define CRT07__V_SYNC_START_B9_MASK 0x80 -+#define CRT07__V_SYNC_START_B9__SHIFT 0x7 -+#define CRT08__ROW_SCAN_START_MASK 0x1f -+#define CRT08__ROW_SCAN_START__SHIFT 0x0 -+#define CRT08__BYTE_PAN_MASK 0x60 -+#define CRT08__BYTE_PAN__SHIFT 0x5 -+#define CRT09__MAX_ROW_SCAN_MASK 0x1f -+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 -+#define CRT09__V_BLANK_START_B9_MASK 0x20 -+#define CRT09__V_BLANK_START_B9__SHIFT 0x5 -+#define CRT09__LINE_CMP_B9_MASK 0x40 -+#define CRT09__LINE_CMP_B9__SHIFT 0x6 -+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 -+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 -+#define CRT0A__CURSOR_START_MASK 0x1f -+#define CRT0A__CURSOR_START__SHIFT 0x0 -+#define CRT0A__CURSOR_DISABLE_MASK 0x20 -+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 -+#define CRT0B__CURSOR_END_MASK 0x1f -+#define CRT0B__CURSOR_END__SHIFT 0x0 -+#define CRT0B__CURSOR_SKEW_MASK 0x60 -+#define CRT0B__CURSOR_SKEW__SHIFT 0x5 -+#define CRT0C__DISP_START_MASK 0xff -+#define CRT0C__DISP_START__SHIFT 0x0 -+#define CRT0D__DISP_START_MASK 0xff -+#define CRT0D__DISP_START__SHIFT 0x0 -+#define CRT0E__CURSOR_LOC_HI_MASK 0xff -+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 -+#define CRT0F__CURSOR_LOC_LO_MASK 0xff -+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 -+#define CRT10__V_SYNC_START_MASK 0xff -+#define CRT10__V_SYNC_START__SHIFT 0x0 -+#define CRT11__V_SYNC_END_MASK 0xf -+#define CRT11__V_SYNC_END__SHIFT 0x0 -+#define CRT11__V_INTR_CLR_MASK 0x10 -+#define CRT11__V_INTR_CLR__SHIFT 0x4 -+#define CRT11__V_INTR_EN_MASK 0x20 -+#define CRT11__V_INTR_EN__SHIFT 0x5 -+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40 -+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 -+#define CRT11__C0T7_WR_ONLY_MASK 0x80 -+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 -+#define CRT12__V_DISP_END_MASK 0xff -+#define CRT12__V_DISP_END__SHIFT 0x0 -+#define CRT13__DISP_PITCH_MASK 0xff -+#define CRT13__DISP_PITCH__SHIFT 0x0 -+#define CRT14__UNDRLN_LOC_MASK 0x1f -+#define CRT14__UNDRLN_LOC__SHIFT 0x0 -+#define CRT14__ADDR_CNT_BY4_MASK 0x20 -+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 -+#define CRT14__DOUBLE_WORD_MASK 0x40 -+#define CRT14__DOUBLE_WORD__SHIFT 0x6 -+#define CRT15__V_BLANK_START_MASK 0xff -+#define CRT15__V_BLANK_START__SHIFT 0x0 -+#define CRT16__V_BLANK_END_MASK 0xff -+#define CRT16__V_BLANK_END__SHIFT 0x0 -+#define CRT17__RA0_AS_A13B_MASK 0x1 -+#define CRT17__RA0_AS_A13B__SHIFT 0x0 -+#define CRT17__RA1_AS_A14B_MASK 0x2 -+#define CRT17__RA1_AS_A14B__SHIFT 0x1 -+#define CRT17__VCOUNT_BY2_MASK 0x4 -+#define CRT17__VCOUNT_BY2__SHIFT 0x2 -+#define CRT17__ADDR_CNT_BY2_MASK 0x8 -+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 -+#define CRT17__WRAP_A15TOA0_MASK 0x20 -+#define CRT17__WRAP_A15TOA0__SHIFT 0x5 -+#define CRT17__BYTE_MODE_MASK 0x40 -+#define CRT17__BYTE_MODE__SHIFT 0x6 -+#define CRT17__CRTC_SYNC_EN_MASK 0x80 -+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 -+#define CRT18__LINE_CMP_MASK 0xff -+#define CRT18__LINE_CMP__SHIFT 0x0 -+#define CRT1E__GRPH_DEC_RD1_MASK 0x2 -+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 -+#define CRT1F__GRPH_DEC_RD0_MASK 0xff -+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 -+#define CRT22__GRPH_LATCH_DATA_MASK 0xff -+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 -+#define GRPH8_IDX__GRPH_IDX_MASK 0xf -+#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 -+#define GRPH8_DATA__GRPH_DATA_MASK 0xff -+#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 -+#define GRA00__GRPH_SET_RESET0_MASK 0x1 -+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 -+#define GRA00__GRPH_SET_RESET1_MASK 0x2 -+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 -+#define GRA00__GRPH_SET_RESET2_MASK 0x4 -+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 -+#define GRA00__GRPH_SET_RESET3_MASK 0x8 -+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 -+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 -+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 -+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 -+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 -+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 -+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 -+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 -+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 -+#define GRA02__GRPH_CCOMP_MASK 0xf -+#define GRA02__GRPH_CCOMP__SHIFT 0x0 -+#define GRA03__GRPH_ROTATE_MASK 0x7 -+#define GRA03__GRPH_ROTATE__SHIFT 0x0 -+#define GRA03__GRPH_FN_SEL_MASK 0x18 -+#define GRA03__GRPH_FN_SEL__SHIFT 0x3 -+#define GRA04__GRPH_RMAP_MASK 0x3 -+#define GRA04__GRPH_RMAP__SHIFT 0x0 -+#define GRA05__GRPH_WRITE_MODE_MASK 0x3 -+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 -+#define GRA05__GRPH_READ1_MASK 0x8 -+#define GRA05__GRPH_READ1__SHIFT 0x3 -+#define GRA05__CGA_ODDEVEN_MASK 0x10 -+#define GRA05__CGA_ODDEVEN__SHIFT 0x4 -+#define GRA05__GRPH_OES_MASK 0x20 -+#define GRA05__GRPH_OES__SHIFT 0x5 -+#define GRA05__GRPH_PACK_MASK 0x40 -+#define GRA05__GRPH_PACK__SHIFT 0x6 -+#define GRA06__GRPH_GRAPHICS_MASK 0x1 -+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 -+#define GRA06__GRPH_ODDEVEN_MASK 0x2 -+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 -+#define GRA06__GRPH_ADRSEL_MASK 0xc -+#define GRA06__GRPH_ADRSEL__SHIFT 0x2 -+#define GRA07__GRPH_XCARE0_MASK 0x1 -+#define GRA07__GRPH_XCARE0__SHIFT 0x0 -+#define GRA07__GRPH_XCARE1_MASK 0x2 -+#define GRA07__GRPH_XCARE1__SHIFT 0x1 -+#define GRA07__GRPH_XCARE2_MASK 0x4 -+#define GRA07__GRPH_XCARE2__SHIFT 0x2 -+#define GRA07__GRPH_XCARE3_MASK 0x8 -+#define GRA07__GRPH_XCARE3__SHIFT 0x3 -+#define GRA08__GRPH_BMSK_MASK 0xff -+#define GRA08__GRPH_BMSK__SHIFT 0x0 -+#define ATTRX__ATTR_IDX_MASK 0x1f -+#define ATTRX__ATTR_IDX__SHIFT 0x0 -+#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 -+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 -+#define ATTRDW__ATTR_DATA_MASK 0xff -+#define ATTRDW__ATTR_DATA__SHIFT 0x0 -+#define ATTRDR__ATTR_DATA_MASK 0xff -+#define ATTRDR__ATTR_DATA__SHIFT 0x0 -+#define ATTR00__ATTR_PAL_MASK 0x3f -+#define ATTR00__ATTR_PAL__SHIFT 0x0 -+#define ATTR01__ATTR_PAL_MASK 0x3f -+#define ATTR01__ATTR_PAL__SHIFT 0x0 -+#define ATTR02__ATTR_PAL_MASK 0x3f -+#define ATTR02__ATTR_PAL__SHIFT 0x0 -+#define ATTR03__ATTR_PAL_MASK 0x3f -+#define ATTR03__ATTR_PAL__SHIFT 0x0 -+#define ATTR04__ATTR_PAL_MASK 0x3f -+#define ATTR04__ATTR_PAL__SHIFT 0x0 -+#define ATTR05__ATTR_PAL_MASK 0x3f -+#define ATTR05__ATTR_PAL__SHIFT 0x0 -+#define ATTR06__ATTR_PAL_MASK 0x3f -+#define ATTR06__ATTR_PAL__SHIFT 0x0 -+#define ATTR07__ATTR_PAL_MASK 0x3f -+#define ATTR07__ATTR_PAL__SHIFT 0x0 -+#define ATTR08__ATTR_PAL_MASK 0x3f -+#define ATTR08__ATTR_PAL__SHIFT 0x0 -+#define ATTR09__ATTR_PAL_MASK 0x3f -+#define ATTR09__ATTR_PAL__SHIFT 0x0 -+#define ATTR0A__ATTR_PAL_MASK 0x3f -+#define ATTR0A__ATTR_PAL__SHIFT 0x0 -+#define ATTR0B__ATTR_PAL_MASK 0x3f -+#define ATTR0B__ATTR_PAL__SHIFT 0x0 -+#define ATTR0C__ATTR_PAL_MASK 0x3f -+#define ATTR0C__ATTR_PAL__SHIFT 0x0 -+#define ATTR0D__ATTR_PAL_MASK 0x3f -+#define ATTR0D__ATTR_PAL__SHIFT 0x0 -+#define ATTR0E__ATTR_PAL_MASK 0x3f -+#define ATTR0E__ATTR_PAL__SHIFT 0x0 -+#define ATTR0F__ATTR_PAL_MASK 0x3f -+#define ATTR0F__ATTR_PAL__SHIFT 0x0 -+#define ATTR10__ATTR_GRPH_MODE_MASK 0x1 -+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 -+#define ATTR10__ATTR_MONO_EN_MASK 0x2 -+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 -+#define ATTR10__ATTR_LGRPH_EN_MASK 0x4 -+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 -+#define ATTR10__ATTR_BLINK_EN_MASK 0x8 -+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 -+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20 -+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 -+#define ATTR10__ATTR_PCLKBY2_MASK 0x40 -+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 -+#define ATTR10__ATTR_CSEL_EN_MASK 0x80 -+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 -+#define ATTR11__ATTR_OVSC_MASK 0xff -+#define ATTR11__ATTR_OVSC__SHIFT 0x0 -+#define ATTR12__ATTR_MAP_EN_MASK 0xf -+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 -+#define ATTR12__ATTR_VSMUX_MASK 0x30 -+#define ATTR12__ATTR_VSMUX__SHIFT 0x4 -+#define ATTR13__ATTR_PPAN_MASK 0xf -+#define ATTR13__ATTR_PPAN__SHIFT 0x0 -+#define ATTR14__ATTR_CSEL1_MASK 0x3 -+#define ATTR14__ATTR_CSEL1__SHIFT 0x0 -+#define ATTR14__ATTR_CSEL2_MASK 0xc -+#define ATTR14__ATTR_CSEL2__SHIFT 0x2 -+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f -+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 -+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 -+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 -+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 -+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 -+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 -+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 -+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 -+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 -+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 -+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 -+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 -+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 -+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 -+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 -+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 -+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 -+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 -+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 -+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 -+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 -+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 -+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 -+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 -+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 -+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 -+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 -+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 -+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 -+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 -+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 -+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 -+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 -+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 -+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa -+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 -+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb -+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 -+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc -+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 -+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd -+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 -+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 -+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 -+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 -+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 -+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 -+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 -+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 -+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 -+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 -+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 -+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 -+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 -+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 -+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 -+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 -+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 -+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 -+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff -+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 -+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff -+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 -+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff -+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 -+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff -+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 -+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 -+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 -+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 -+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 -+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 -+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 -+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 -+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 -+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 -+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 -+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 -+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 -+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 -+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 -+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 -+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 -+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 -+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 -+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 -+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 -+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 -+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 -+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 -+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 -+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 -+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 -+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 -+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 -+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 -+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 -+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 -+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 -+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 -+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 -+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 -+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 -+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 -+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 -+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 -+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 -+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 -+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 -+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 -+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 -+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 -+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 -+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 -+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 -+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 -+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 -+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 -+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 -+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 -+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 -+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 -+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 -+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 -+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 -+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 -+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 -+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 -+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 -+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 -+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 -+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 -+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 -+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 -+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 -+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 -+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 -+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 -+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 -+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 -+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 -+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 -+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 -+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 -+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 -+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 -+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 -+#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff -+#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 -+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 -+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 -+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 -+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 -+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 -+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 -+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 -+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 -+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 -+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 -+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 -+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 -+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 -+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 -+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 -+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 -+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 -+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 -+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 -+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 -+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 -+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 -+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 -+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 -+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 -+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 -+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 -+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 -+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 -+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 -+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 -+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 -+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 -+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 -+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 -+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 -+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 -+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 -+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 -+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 -+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 -+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 -+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 -+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 -+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 -+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a -+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 -+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b -+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 -+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c -+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 -+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d -+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 -+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f -+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 -+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 -+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 -+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 -+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 -+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 -+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 -+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 -+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff -+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 -+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff -+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 -+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff -+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 -+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 -+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 -+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff -+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 -+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 -+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 -+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff -+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff -+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 -+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff -+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 -+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 -+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c -+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff -+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 -+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 -+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 -+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff -+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 -+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 -+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 -+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 -+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 -+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 -+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 -+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 -+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 -+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff -+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 -+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 -+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 -+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 -+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 -+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 -+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 -+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 -+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb -+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 -+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 -+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 -+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 -+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff -+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 -+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff -+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 -+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff -+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff -+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 -+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff -+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 -+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff -+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff -+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 -+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff -+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 -+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff -+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 -+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f -+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 -+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff -+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 -+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff -+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 -+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 -+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 -+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f -+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 -+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f -+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 -+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 -+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 -+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 -+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 -+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffff -+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x0 -+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff -+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 -+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff -+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 -+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff -+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 -+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff -+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 -+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff -+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 -+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff -+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 -+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff -+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 -+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 -+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 -+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc -+#define MINOR_VERSION__MINOR_VERSION_MASK 0xff -+#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 -+#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff -+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 -+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff -+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 -+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff -+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 -+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 -+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 -+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 -+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 -+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 -+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 -+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 -+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 -+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 -+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 -+#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 -+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 -+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff -+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE_MASK 0x1 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE_MASK 0x2 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE_MASK 0x4 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE_MASK 0x8 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE_MASK 0x10 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE_MASK 0x20 -+#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 -+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 -+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e -+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 -+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f -+#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS_MASK 0x1 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS_MASK 0x2 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS_MASK 0x4 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS_MASK 0x8 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS_MASK 0x10 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS_MASK 0x20 -+#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 -+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 -+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e -+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 -+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f -+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff -+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 -+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 -+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 -+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 -+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 -+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 -+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 -+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 -+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 -+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 -+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 -+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 -+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 -+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f -+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 -+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 -+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 -+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff -+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 -+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff -+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 -+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff -+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 -+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 -+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf -+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 -+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 -+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 -+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 -+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 -+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 -+#define CORB_SIZE__CORB_SIZE_MASK 0x3 -+#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 -+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 -+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 -+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f -+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 -+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 -+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 -+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff -+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 -+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff -+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 -+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 -+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf -+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff -+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 -+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 -+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 -+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 -+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 -+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 -+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 -+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 -+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 -+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 -+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 -+#define RIRB_SIZE__RIRB_SIZE_MASK 0x3 -+#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 -+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 -+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff -+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 -+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff -+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 -+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 -+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 -+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 -+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 -+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 -+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 -+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e -+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 -+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 -+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 -+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff -+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 -+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff -+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 -+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d -+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff -+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff -+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff -+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff -+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 -+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe -+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f -+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 -+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 -+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff -+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 -+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff -+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 -+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff -+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 -+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff -+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff -+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 -+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 -+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 -+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 -+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff -+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 -+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 -+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f -+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 -+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00 -+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa -+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff -+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 -+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 -+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 -+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 -+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 -+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff -+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 -+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 -+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 -+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff -+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff -+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 -+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 -+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff -+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 -+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 -+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff -+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 -+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 -+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 -+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 -+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 -+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 -+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 -+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff -+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 -+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 -+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 -+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 -+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 -+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 -+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 -+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff -+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 -+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 -+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 -+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 -+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 -+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 -+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 -+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 -+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 -+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 -+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 -+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 -+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 -+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 -+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 -+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 -+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 -+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 -+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 -+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 -+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 -+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff -+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 -+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 -+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 -+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 -+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 -+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff -+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 -+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 -+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 -+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff -+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 -+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 -+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 -+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff -+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 -+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 -+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 -+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 -+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 -+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 -+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 -+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 -+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc -+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff -+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 -+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff -+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 -+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 -+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 -+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 -+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 -+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 -+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 -+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff -+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 -+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff -+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 -+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 -+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 -+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 -+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 -+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 -+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 -+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 -+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc -+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff -+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 -+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff -+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 -+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 -+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 -+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 -+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 -+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 -+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 -+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff -+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 -+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff -+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 -+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff -+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff -+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 -+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff -+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 -+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 -+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 -+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff -+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 -+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f -+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 -+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 -+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 -+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 -+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 -+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 -+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 -+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff -+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 -+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff -+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 -+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff -+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 -+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff -+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 -+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff -+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 -+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff -+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 -+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 -+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 -+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 -+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff -+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff -+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff -+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 -+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff -+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 -+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 -+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 -+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 -+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 -+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 -+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff -+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 -+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 -+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 -+#define BLND_CONTROL__BLND_MODE_MASK 0x300 -+#define BLND_CONTROL__BLND_MODE__SHIFT 0x8 -+#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 -+#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 -+#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 -+#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 -+#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 -+#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 -+#define SM_CONTROL2__SM_MODE_MASK 0x7 -+#define SM_CONTROL2__SM_MODE__SHIFT 0x0 -+#define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 -+#define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 -+#define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 -+#define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 -+#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 -+#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 -+#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 -+#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 -+#define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 -+#define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 -+#define PTI_CONTROL__PTI_ENABLE_MASK 0x1 -+#define PTI_CONTROL__PTI_ENABLE__SHIFT 0x0 -+#define PTI_CONTROL__PTI_NEW_PIXEL_GAP_MASK 0x30 -+#define PTI_CONTROL__PTI_NEW_PIXEL_GAP__SHIFT 0x4 -+#define PTI_CONTROL__BLND_NEW_PIXEL_MODE_MASK 0x40 -+#define PTI_CONTROL__BLND_NEW_PIXEL_MODE__SHIFT 0x6 -+#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 -+#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 -+#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 -+#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 -+#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 -+#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 -+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 -+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 -+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 -+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING_MASK 0x1 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING__SHIFT 0x0 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING_MASK 0x2 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING__SHIFT 0x1 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING_MASK 0x4 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING_MASK 0x8 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING_MASK 0x10 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING__SHIFT 0x4 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING_MASK 0x20 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING__SHIFT 0x5 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING_MASK 0x40 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING__SHIFT 0x6 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING_MASK 0x80 -+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING__SHIFT 0x7 -+#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING_MASK 0x100 -+#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING__SHIFT 0x8 -+#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING_MASK 0x200 -+#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING__SHIFT 0x9 -+#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 -+#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 -+#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe -+#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 -+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff -+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff -+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 -+#define SI_ENABLE__SI_ENABLE_MASK 0x1 -+#define SI_ENABLE__SI_ENABLE__SHIFT 0x0 -+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS_MASK 0x1 -+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS__SHIFT 0x0 -+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS_MASK 0x2 -+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS__SHIFT 0x1 -+#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS_MASK 0x4 -+#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS__SHIFT 0x2 -+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS_MASK 0x8 -+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS__SHIFT 0x3 -+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS_MASK 0x10 -+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS__SHIFT 0x4 -+#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS_MASK 0x20 -+#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS__SHIFT 0x5 -+#define SI_EC_CONFIG__SI_LB_LS_DIS_MASK 0x40 -+#define SI_EC_CONFIG__SI_LB_LS_DIS__SHIFT 0x6 -+#define SI_EC_CONFIG__SI_LB_SD_DIS_MASK 0x80 -+#define SI_EC_CONFIG__SI_LB_SD_DIS__SHIFT 0x7 -+#define SI_EC_CONFIG__SI_LUT_LS_DIS_MASK 0x100 -+#define SI_EC_CONFIG__SI_LUT_LS_DIS__SHIFT 0x8 -+#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL_MASK 0xf000 -+#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL__SHIFT 0xc -+#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE_MASK 0x800000 -+#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE__SHIFT 0x17 -+#define SI_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 -+#define SI_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c -+#define SI_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 -+#define SI_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e -+#define CNV_MODE__CNV_INPUT_SRC_SELECT_MASK 0x3 -+#define CNV_MODE__CNV_INPUT_SRC_SELECT__SHIFT 0x0 -+#define CNV_MODE__CNV_INPUT_PIPE_SELECT_MASK 0x1c -+#define CNV_MODE__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 -+#define CNV_MODE__CNV_FRAME_COUNT_MASK 0x300 -+#define CNV_MODE__CNV_FRAME_COUNT__SHIFT 0x8 -+#define CNV_MODE__CNV_WINDOW_EN_MASK 0x1000 -+#define CNV_MODE__CNV_WINDOW_EN__SHIFT 0xc -+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 -+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 -+#define CNV_MODE__CNV_STEREO_EYE_ORDER_MASK 0x40000 -+#define CNV_MODE__CNV_STEREO_EYE_ORDER__SHIFT 0x12 -+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 -+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 -+#define CNV_MODE__CNV_FRAME_EN_MASK 0x80000000 -+#define CNV_MODE__CNV_FRAME_EN__SHIFT 0x1f -+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff -+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 -+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 -+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 -+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff -+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 -+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 -+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 -+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 -+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 -+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 -+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 -+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 -+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 -+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff -+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 -+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 -+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 -+#define CNV_CSC_CONTROL__CNV_CSC_bypass_MASK 0x1 -+#define CNV_CSC_CONTROL__CNV_CSC_bypass__SHIFT 0x0 -+#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff -+#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 -+#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 -+#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 -+#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff -+#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 -+#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 -+#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 -+#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff -+#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 -+#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 -+#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 -+#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff -+#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 -+#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 -+#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 -+#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff -+#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 -+#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 -+#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 -+#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff -+#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 -+#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 -+#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 -+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff -+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 -+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff -+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 -+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff -+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 -+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff -+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 -+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 -+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 -+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff -+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 -+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 -+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 -+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff -+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 -+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 -+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 -+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 -+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 -+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 -+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 -+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 -+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 -+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xffff -+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x0 -+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 -+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 -+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xffff -+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x0 -+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 -+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 -+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xffff -+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x0 -+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 -+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 -+#define SI_DEBUG_CTRL__SI_DEBUG_SEL_MASK 0x3 -+#define SI_DEBUG_CTRL__SI_DEBUG_SEL__SHIFT 0x0 -+#define SI_DBG_MODE__SI_DBG_MODE_EN_MASK 0x1 -+#define SI_DBG_MODE__SI_DBG_MODE_EN__SHIFT 0x0 -+#define SI_DBG_MODE__SI_DBG_DIN_FMT_MASK 0x2 -+#define SI_DBG_MODE__SI_DBG_DIN_FMT__SHIFT 0x1 -+#define SI_DBG_MODE__SI_DBG_36MODE_MASK 0x4 -+#define SI_DBG_MODE__SI_DBG_36MODE__SHIFT 0x2 -+#define SI_DBG_MODE__SI_DBG_CMAP_MASK 0x8 -+#define SI_DBG_MODE__SI_DBG_CMAP__SHIFT 0x3 -+#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR_MASK 0x100 -+#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR__SHIFT 0x8 -+#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH_MASK 0x7fff0000 -+#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH__SHIFT 0x10 -+#define SI_HARD_DEBUG__SI_HARD_DEBUG_MASK 0xffffffff -+#define SI_HARD_DEBUG__SI_HARD_DEBUG__SHIFT 0x0 -+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff -+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff -+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 -+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x7 -+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 -+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE_MASK 0xf00 -+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE__SHIFT 0x8 -+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE_MASK 0x30000 -+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x3fff -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000 -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 -+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f -+#define SISCL_MODE__SISCL_MODE_MASK 0x3 -+#define SISCL_MODE__SISCL_MODE__SHIFT 0x0 -+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB_MASK 0xf -+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 -+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR_MASK 0xf0 -+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 -+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB_MASK 0xf00 -+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 -+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR_MASK 0xf000 -+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc -+#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT_MASK 0x7fff -+#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT__SHIFT 0x0 -+#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH_MASK 0x7fff0000 -+#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH__SHIFT 0x10 -+#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO_MASK 0x7ffffff -+#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO__SHIFT 0x0 -+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB_MASK 0xffffff -+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 -+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB_MASK 0x1f000000 -+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB__SHIFT 0x18 -+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR_MASK 0xffffff -+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR__SHIFT 0x0 -+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR_MASK 0x1f000000 -+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR__SHIFT 0x18 -+#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO_MASK 0x7ffffff -+#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO__SHIFT 0x0 -+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB_MASK 0xffffff -+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 -+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB_MASK 0x1f000000 -+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB__SHIFT 0x18 -+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR_MASK 0xffffff -+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR__SHIFT 0x0 -+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR_MASK 0x1f000000 -+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR__SHIFT 0x18 -+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB_MASK 0xffff -+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 -+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 -+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR__SHIFT 0x10 -+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB_MASK 0xff -+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 -+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB_MASK 0xff00 -+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8 -+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR_MASK 0xff0000 -+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR__SHIFT 0x10 -+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR_MASK 0xff000000 -+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR__SHIFT 0x18 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG_MASK 0x1 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK_MASK 0x100 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK__SHIFT 0x8 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK_MASK 0x1000 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK__SHIFT 0xc -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS_MASK 0x10000 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE_MASK 0x100000 -+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG_MASK 0x1 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG__SHIFT 0x0 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK_MASK 0x100 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK__SHIFT 0x8 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK_MASK 0x1000 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK__SHIFT 0xc -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE_MASK 0x100000 -+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY_MASK 0x1 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB_MASK 0xff00 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB__SHIFT 0x8 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y_MASK 0xff0000 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y__SHIFT 0x10 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR_MASK 0xff000000 -+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR__SHIFT 0x18 -+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN_MASK 0x10 -+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN__SHIFT 0x4 -+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN_MASK 0x100 -+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN__SHIFT 0x8 -+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY_MASK 0x10000 -+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY__SHIFT 0x10 -+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK_MASK 0xffff -+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK__SHIFT 0x0 -+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED_MASK 0xffff0000 -+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED__SHIFT 0x10 -+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK_MASK 0xffff -+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 -+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN_MASK 0xffff0000 -+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 -+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK_MASK 0xffff -+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK__SHIFT 0x0 -+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE_MASK 0xffff0000 -+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 -+#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN_MASK 0x1 -+#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 -+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE_MASK 0xffff -+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 -+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE_MASK 0xffff0000 -+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 -+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX_MASK 0xff -+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA_MASK 0xffffffff -+#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA__SHIFT 0x0 -+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 -+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 -+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 -+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc -+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 -+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 -+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 -+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 -+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 -+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 -+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 -+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 -+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b -+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 -+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 -+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 -+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 -+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 -+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa -+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x1000 -+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0xc -+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x2000 -+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0xd -+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x4000 -+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0xe -+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 -+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 -+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 -+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 -+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 -+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 -+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 -+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 -+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 -+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 -+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 -+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 -+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x1 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x100 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x8 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x10000 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x10 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x1000000 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x18 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000 -+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x1e -+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf -+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 -+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 -+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 -+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff -+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 -+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 -+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 -+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff -+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff -+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 -+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 -+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 -+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 -+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 -+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 -+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf -+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff -+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 -+#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff -+#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 -+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff -+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 -+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 -+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 -+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 -+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 -+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 -+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a -+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff -+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 -+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 -+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 -+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 -+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 -+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff -+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 -+ -+#endif /* DCE_8_0_SH_MASK_H */ --- -1.9.1 - |