diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch b/common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch new file mode 100644 index 00000000..2f9c4a8e --- /dev/null +++ b/common/recipes-kernel/linux/files/0094-drm-amd-powerplay-add-parts-of-system-clock-gating-s.patch @@ -0,0 +1,120 @@ +From 50771694e54dc5c1441506707ea3aedf02979c2d Mon Sep 17 00:00:00 2001 +From: Eric Huang <JinHuiEric.Huang@amd.com> +Date: Thu, 12 Nov 2015 16:59:47 -0500 +Subject: [PATCH 0094/1110] drm/amd/powerplay: add parts of system clock gating + support for Fiji. (v2) + +Removed fiji_mgcg_cgcg_init that is affected and redundant for new implementation. + +v2: re-add mgcg_cgcg init + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vi.c | 86 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 86 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c +index 8f2c5c9..89f5a1f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/vi.c +@@ -1544,9 +1544,95 @@ static int vi_common_soft_reset(void *handle) + return 0; + } + ++static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, ++ bool enable) ++{ ++ uint32_t temp, data; ++ ++ temp = data = RREG32_PCIE(ixPCIE_CNTL2); ++ ++ if (enable) ++ data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | ++ PCIE_CNTL2__MST_MEM_LS_EN_MASK | ++ PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; ++ else ++ data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | ++ PCIE_CNTL2__MST_MEM_LS_EN_MASK | ++ PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); ++ ++ if (temp != data) ++ WREG32_PCIE(ixPCIE_CNTL2, data); ++} ++ ++static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, ++ bool enable) ++{ ++ uint32_t temp, data; ++ ++ temp = data = RREG32(mmHDP_HOST_PATH_CNTL); ++ ++ if (enable) ++ data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; ++ else ++ data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; ++ ++ if (temp != data) ++ WREG32(mmHDP_HOST_PATH_CNTL, data); ++} ++ ++static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev, ++ bool enable) ++{ ++ uint32_t temp, data; ++ ++ temp = data = RREG32(mmHDP_MEM_POWER_LS); ++ ++ if (enable) ++ data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; ++ else ++ data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; ++ ++ if (temp != data) ++ WREG32(mmHDP_MEM_POWER_LS, data); ++} ++ ++static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, ++ bool enable) ++{ ++ uint32_t temp, data; ++ ++ temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); ++ ++ if (enable) ++ data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | ++ CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); ++ else ++ data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | ++ CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; ++ ++ if (temp != data) ++ WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); ++} ++ + static int vi_common_set_clockgating_state(void *handle, + enum amd_clockgating_state state) + { ++ struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ ++ switch (adev->asic_type) { ++ case CHIP_FIJI: ++ fiji_update_bif_medium_grain_light_sleep(adev, ++ state == AMD_CG_STATE_GATE ? true : false); ++ fiji_update_hdp_medium_grain_clock_gating(adev, ++ state == AMD_CG_STATE_GATE ? true : false); ++ fiji_update_hdp_light_sleep(adev, ++ state == AMD_CG_STATE_GATE ? true : false); ++ fiji_update_rom_medium_grain_clock_gating(adev, ++ state == AMD_CG_STATE_GATE ? true : false); ++ break; ++ default: ++ break; ++ } + return 0; + } + +-- +2.7.4 + |