diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch')
-rw-r--r-- | common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch | 202 |
1 files changed, 0 insertions, 202 deletions
diff --git a/common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch b/common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch deleted file mode 100644 index 1b327cb8..00000000 --- a/common/recipes-kernel/linux/files/0092-drm-amd-amdgpu-add-gmc-clock-gating-support-for-Fiji.patch +++ /dev/null @@ -1,202 +0,0 @@ -From 0690f9c20ec6f732f6f19249bcaef94c12e3b55a Mon Sep 17 00:00:00 2001 -From: Eric Huang <JinHuiEric.Huang@amd.com> -Date: Tue, 10 Nov 2015 11:27:39 -0500 -Subject: [PATCH 0092/1110] drm/amd/amdgpu: add gmc clock gating support for - Fiji. - -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 172 ++++++++++++++++++++++++++++++++++ - 1 file changed, 172 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c -index 3d4a923..2fcfa97 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c -@@ -1307,9 +1307,181 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, - return 0; - } - -+static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, -+ bool enable) -+{ -+ uint32_t data; -+ -+ if (enable) { -+ data = RREG32(mmMC_HUB_MISC_HUB_CG); -+ data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_HUB_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_SIP_CG); -+ data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_SIP_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_VM_CG); -+ data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_VM_CG, data); -+ -+ data = RREG32(mmMC_XPB_CLK_GAT); -+ data |= MC_XPB_CLK_GAT__ENABLE_MASK; -+ WREG32(mmMC_XPB_CLK_GAT, data); -+ -+ data = RREG32(mmATC_MISC_CG); -+ data |= ATC_MISC_CG__ENABLE_MASK; -+ WREG32(mmATC_MISC_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_WR_CG); -+ data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_WR_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_RD_CG); -+ data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_RD_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_VM_CG); -+ data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_VM_CG, data); -+ -+ data = RREG32(mmVM_L2_CG); -+ data |= VM_L2_CG__ENABLE_MASK; -+ WREG32(mmVM_L2_CG, data); -+ } else { -+ data = RREG32(mmMC_HUB_MISC_HUB_CG); -+ data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_HUB_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_SIP_CG); -+ data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_SIP_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_VM_CG); -+ data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_VM_CG, data); -+ -+ data = RREG32(mmMC_XPB_CLK_GAT); -+ data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; -+ WREG32(mmMC_XPB_CLK_GAT, data); -+ -+ data = RREG32(mmATC_MISC_CG); -+ data &= ~ATC_MISC_CG__ENABLE_MASK; -+ WREG32(mmATC_MISC_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_WR_CG); -+ data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_WR_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_RD_CG); -+ data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_RD_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_VM_CG); -+ data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_VM_CG, data); -+ -+ data = RREG32(mmVM_L2_CG); -+ data &= ~VM_L2_CG__ENABLE_MASK; -+ WREG32(mmVM_L2_CG, data); -+ } -+} -+ -+static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, -+ bool enable) -+{ -+ uint32_t data; -+ -+ if (enable) { -+ data = RREG32(mmMC_HUB_MISC_HUB_CG); -+ data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_HUB_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_SIP_CG); -+ data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_SIP_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_VM_CG); -+ data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_VM_CG, data); -+ -+ data = RREG32(mmMC_XPB_CLK_GAT); -+ data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_XPB_CLK_GAT, data); -+ -+ data = RREG32(mmATC_MISC_CG); -+ data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmATC_MISC_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_WR_CG); -+ data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_WR_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_RD_CG); -+ data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_RD_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_VM_CG); -+ data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_VM_CG, data); -+ -+ data = RREG32(mmVM_L2_CG); -+ data |= VM_L2_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmVM_L2_CG, data); -+ } else { -+ data = RREG32(mmMC_HUB_MISC_HUB_CG); -+ data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_HUB_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_SIP_CG); -+ data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_SIP_CG, data); -+ -+ data = RREG32(mmMC_HUB_MISC_VM_CG); -+ data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_HUB_MISC_VM_CG, data); -+ -+ data = RREG32(mmMC_XPB_CLK_GAT); -+ data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_XPB_CLK_GAT, data); -+ -+ data = RREG32(mmATC_MISC_CG); -+ data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmATC_MISC_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_WR_CG); -+ data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_WR_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_RD_CG); -+ data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_RD_CG, data); -+ -+ data = RREG32(mmMC_CITF_MISC_VM_CG); -+ data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmMC_CITF_MISC_VM_CG, data); -+ -+ data = RREG32(mmVM_L2_CG); -+ data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; -+ WREG32(mmVM_L2_CG, data); -+ } -+} -+ - static int gmc_v8_0_set_clockgating_state(void *handle, - enum amd_clockgating_state state) - { -+ struct amdgpu_device *adev = (struct amdgpu_device *)handle; -+ -+ switch (adev->asic_type) { -+ case CHIP_FIJI: -+ fiji_update_mc_medium_grain_clock_gating(adev, -+ state == AMD_CG_STATE_GATE ? true : false); -+ fiji_update_mc_light_sleep(adev, -+ state == AMD_CG_STATE_GATE ? true : false); -+ break; -+ default: -+ break; -+ } - return 0; - } - --- -2.7.4 - |