diff options
Diffstat (limited to 'common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch b/common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch new file mode 100644 index 00000000..3ffc4236 --- /dev/null +++ b/common/recipes-kernel/linux/files/0088-drm-amdgpu-powerplay-fiji-query-supported-pcie-info-.patch @@ -0,0 +1,56 @@ +From b6a83b14bdfdc66d6d25cfc4fe89d61de0560686 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 11 Nov 2015 21:02:16 -0500 +Subject: [PATCH 0088/1110] drm/amdgpu/powerplay/fiji: query supported pcie + info from cgs (v2) + +Rather than hardcode it. + +v2: integrate spc fix from Rex + +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 20 ++++++++++++++++++-- + 1 file changed, 18 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +index ccbdbef..5ef92e1 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +@@ -684,14 +684,30 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + PHM_PlatformCaps_StayInBootState); + + if (0 == result) { ++ struct cgs_system_info sys_info = {0}; ++ + data->is_tlu_enabled = 0; + hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = + FIJI_MAX_HARDWARE_POWERLEVELS; + hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; + hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; + +- data->pcie_gen_cap = 0x30007; +- data->pcie_lane_cap = 0x2f0000; ++ sys_info.size = sizeof(struct cgs_system_info); ++ sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; ++ result = cgs_query_system_info(hwmgr->device, &sys_info); ++ if (result) ++ data->pcie_gen_cap = 0x30007; ++ else ++ data->pcie_gen_cap = (uint32_t)sys_info.value; ++ if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) ++ data->pcie_spc_cap = 20; ++ sys_info.size = sizeof(struct cgs_system_info); ++ sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; ++ result = cgs_query_system_info(hwmgr->device, &sys_info); ++ if (result) ++ data->pcie_lane_cap = 0x2f0000; ++ else ++ data->pcie_lane_cap = (uint32_t)sys_info.value; + } else { + /* Ignore return value in here, we are cleaning up a mess. */ + tonga_hwmgr_backend_fini(hwmgr); +-- +2.7.4 + |