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-rw-r--r--common/recipes-kernel/linux/files/0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch64
1 files changed, 64 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch b/common/recipes-kernel/linux/files/0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch
new file mode 100644
index 00000000..1ec5c7d2
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0083-drm-amd-powerplay-fiji-enable-pcie-and-mclk-forcing-.patch
@@ -0,0 +1,64 @@
+From b0d91d2c1134404fb066c8ad0bd781e9fea591f4 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 11 Nov 2015 00:31:00 -0500
+Subject: [PATCH 0083/1110] drm/amd/powerplay/fiji: enable pcie and mclk
+ forcing for low
+
+When forcing the lowest state also force mclk and pcie.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 30 ++++++++++++++++++++----
+ 1 file changed, 25 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+index 4457878..adcc2f0 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+@@ -3576,18 +3576,38 @@ static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+ {
+ struct fiji_hwmgr *data =
+ (struct fiji_hwmgr *)(hwmgr->backend);
+- uint32_t level = 0;
++ uint32_t level;
+
+- /* Only force sclk for now */
+ if (!data->sclk_dpm_key_disabled)
+ if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
+ level = fiji_get_lowest_enabled_level(hwmgr,
+- data->dpm_level_enable_mask.sclk_dpm_enable_mask);
++ data->dpm_level_enable_mask.sclk_dpm_enable_mask);
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+- PPSMC_MSG_SCLKDPM_SetEnabledMask,
+- (1 << level));
++ PPSMC_MSG_SCLKDPM_SetEnabledMask,
++ (1 << level));
++
++ }
++
++ if (!data->mclk_dpm_key_disabled) {
++ if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
++ level = fiji_get_lowest_enabled_level(hwmgr,
++ data->dpm_level_enable_mask.mclk_dpm_enable_mask);
++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
++ PPSMC_MSG_MCLKDPM_SetEnabledMask,
++ (1 << level));
++ }
++ }
+
++ if (!data->pcie_dpm_key_disabled) {
++ if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
++ level = fiji_get_lowest_enabled_level(hwmgr,
++ data->dpm_level_enable_mask.pcie_dpm_enable_mask);
++ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
++ PPSMC_MSG_PCIeDPM_ForceLevel,
++ (1 << level));
++ }
+ }
++
+ return 0;
+
+ }
+--
+2.7.4
+