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-rw-r--r--common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch2338
1 files changed, 2338 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch b/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch
new file mode 100644
index 00000000..84fa3f14
--- /dev/null
+++ b/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch
@@ -0,0 +1,2338 @@
+From a420ce17e2154d83fa3c3f6c8ad91393cc49cdd6 Mon Sep 17 00:00:00 2001
+From: Tom St Denis <tom.stdenis@amd.com>
+Date: Tue, 1 Dec 2015 11:47:21 -0500
+Subject: [PATCH 0014/1110] amdgpu/gfxv8: Cleanup of
+ gfx_v8_0_tiling_mode_table_init() (v2)
+
+Simplification and LOC reduction of function gfx_v8_0_tiling_mode_table_init()
+
+v2: remove spurious break
+bug: https://bugs.freedesktop.org/show_bug.cgi?id=93236
+
+Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2286 +++++++++++++--------------------
+ 1 file changed, 898 insertions(+), 1388 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 2dd0583..f85de15 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -1639,1407 +1639,917 @@ static int gfx_v8_0_sw_fini(void *handle)
+
+ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
+ {
++ uint32_t *modearray, *mod2array;
+ const u32 num_tile_mode_states = 32;
+ const u32 num_secondary_tile_mode_states = 16;
+- u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
++ u32 reg_offset;
+
+- switch (adev->gfx.config.mem_row_size_in_kb) {
+- case 1:
+- split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
+- break;
+- case 2:
+- default:
+- split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
+- break;
+- case 4:
+- split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
+- break;
+- }
++ modearray = adev->gfx.config.tile_mode_array;
++ mod2array = adev->gfx.config.macrotile_mode_array;
++
++ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
++ modearray[reg_offset] = 0;
++
++ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
++ mod2array[reg_offset] = 0;
+
+ switch (adev->asic_type) {
+ case CHIP_TOPAZ:
+- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 1:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 2:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 3:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 4:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 5:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 6:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 8:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+- PIPE_CONFIG(ADDR_SURF_P2));
+- break;
+- case 9:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 10:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 11:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 13:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 14:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 15:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 16:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 18:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 19:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 20:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 21:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 22:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 24:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 25:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 26:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 27:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 28:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 29:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 7:
+- case 12:
+- case 17:
+- case 23:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
+- }
+- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 1:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 2:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 3:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 4:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 5:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 6:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 8:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 9:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 10:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 11:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 12:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 13:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 14:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 7:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
+- }
++ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++ PIPE_CONFIG(ADDR_SURF_P2));
++ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++
++ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++
++ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
++ if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
++ reg_offset != 23)
++ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
++
++ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
++ if (reg_offset != 7)
++ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
++
+ break;
+ case CHIP_FIJI:
+- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 1:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 2:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 3:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 4:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 5:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 6:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 7:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 8:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
+- break;
+- case 9:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 10:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 11:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 12:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 13:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 14:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 15:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 16:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 17:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 18:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 19:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 20:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 21:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 22:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 23:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 24:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 25:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 26:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 27:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 28:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 29:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 30:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- default:
+- gb_tile_moden = 0;
+- break;
+- }
+- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
+- }
+- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 1:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 2:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 3:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 4:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 5:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 6:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 8:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 9:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 10:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 11:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 12:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 13:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 14:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 7:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- }
+- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
+- }
++ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
++ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++
++ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_4_BANK));
++
++ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
++ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
++
++ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
++ if (reg_offset != 7)
++ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
++
+ break;
+ case CHIP_TONGA:
+- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 1:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 2:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 3:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 4:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 5:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 6:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 7:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 8:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
+- break;
+- case 9:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 10:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 11:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 12:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 13:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 14:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 15:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 16:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 17:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 18:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 19:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 20:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 21:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 22:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 23:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 24:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 25:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 26:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 27:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 28:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 29:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 30:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
+- }
+- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 1:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 2:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 3:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 4:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 5:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 6:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 8:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 9:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 10:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 11:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 12:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 13:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 14:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 7:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
+- }
++ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
++ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++
++ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_4_BANK));
++ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_4_BANK));
++
++ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
++ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
++
++ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
++ if (reg_offset != 7)
++ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
++
+ break;
+ case CHIP_STONEY:
+- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 1:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 2:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 3:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 4:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 5:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 6:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 8:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+- PIPE_CONFIG(ADDR_SURF_P2));
+- break;
+- case 9:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 10:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 11:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 13:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 14:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 15:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 16:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 18:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 19:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 20:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 21:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 22:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 24:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 25:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 26:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 27:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 28:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 29:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 7:
+- case 12:
+- case 17:
+- case 23:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
+- }
+- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 1:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 2:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 3:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 4:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 5:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 6:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 8:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 9:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 10:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 11:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 12:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 13:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 14:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 7:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
+- }
++ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++ PIPE_CONFIG(ADDR_SURF_P2));
++ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++
++ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++
++ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
++ if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
++ reg_offset != 23)
++ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
++
++ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
++ if (reg_offset != 7)
++ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
++
+ break;
+- case CHIP_CARRIZO:
+ default:
+- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 1:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 2:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 3:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 4:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 5:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 6:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+- break;
+- case 8:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+- PIPE_CONFIG(ADDR_SURF_P2));
+- break;
+- case 9:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 10:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 11:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 13:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 14:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 15:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 16:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 18:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 19:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 20:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 21:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 22:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 24:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 25:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 26:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+- break;
+- case 27:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 28:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+- break;
+- case 29:
+- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+- break;
+- case 7:
+- case 12:
+- case 17:
+- case 23:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
+- }
+- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
+- switch (reg_offset) {
+- case 0:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 1:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 2:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 3:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 4:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 5:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 6:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 8:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 9:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 10:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 11:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 12:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 13:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
+- break;
+- case 14:
+- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
+- break;
+- case 7:
+- /* unused idx */
+- continue;
+- default:
+- gb_tile_moden = 0;
+- break;
+- };
+- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
+- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
+- }
++ dev_warn(adev->dev,
++ "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
++ adev->asic_type);
++
++ case CHIP_CARRIZO:
++ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++ PIPE_CONFIG(ADDR_SURF_P2));
++ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
++ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P2) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
++
++ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++
++ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
++ if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
++ reg_offset != 23)
++ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
++
++ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
++ if (reg_offset != 7)
++ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
++
++ break;
+ }
+ }
+
+@@ -4957,7 +4467,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
+ EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+ EVENT_INDEX(5)));
+ amdgpu_ring_write(ring, addr & 0xfffffffc);
+- amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
++ amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
+ DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
+ amdgpu_ring_write(ring, lower_32_bits(seq));
+ amdgpu_ring_write(ring, upper_32_bits(seq));
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-26 07:52:07 +0000