diff options
114 files changed, 0 insertions, 9741 deletions
diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0001-intel-kbl-Add-Kabylake-PCI-ids.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0001-intel-kbl-Add-Kabylake-PCI-ids.patch deleted file mode 100644 index 9c9e815e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0001-intel-kbl-Add-Kabylake-PCI-ids.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 242f77ce03f4db371d8de3de1bef8622c0fe7488 Mon Sep 17 00:00:00 2001 -From: Rodrigo Vivi <rodrigo.vivi@intel.com> -Date: Fri, 18 Sep 2015 11:26:39 -0700 -Subject: [PATCH 001/117] intel/kbl: Add Kabylake PCI ids - -Also, following kernel definition Kabylake is skylake. - -Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> -Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> ---- - intel/intel_chipset.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 56 insertions(+), 1 deletion(-) - -diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h -index 26fbee4..35148e5 100644 ---- a/intel/intel_chipset.h -+++ b/intel/intel_chipset.h -@@ -187,6 +187,29 @@ - #define PCI_CHIP_SKYLAKE_H_GT4 0x193B - #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D - -+#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 -+#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 -+#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -+#define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926 -+#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 -+#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 -+#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E -+#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E -+#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -+#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 -+#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -+#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 -+#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B -+#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B -+#define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B -+#define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B -+#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -+#define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A -+#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A -+#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A -+#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D -+#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D -+ - #define PCI_CHIP_BROXTON_0 0x0A84 - #define PCI_CHIP_BROXTON_1 0x1A84 - #define PCI_CHIP_BROXTON_2 0x5A84 -@@ -375,6 +398,37 @@ - (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) - -+#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ -+ (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT1 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) -+ -+#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ -+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ -+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) -+ -+#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT3 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) -+ -+#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4 || \ -+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT4 || \ -+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT4 || \ -+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT4) -+ -+#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ -+ IS_KBL_GT2(devid) || \ -+ IS_KBL_GT3(devid) || \ -+ IS_KBL_GT4(devid)) -+ - #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ - IS_SKL_GT2(devid) || \ - IS_SKL_GT3(devid) || \ -@@ -385,7 +439,8 @@ - (devid) == PCI_CHIP_BROXTON_2) - - #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ -- IS_BROXTON(devid)) -+ IS_BROXTON(devid) || \ -+ IS_KABYLAKE(devid)) - - #define IS_9XX(dev) (IS_GEN3(dev) || \ - IS_GEN4(dev) || \ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0001-tests-also-install-tests-app.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0001-tests-also-install-tests-app.patch deleted file mode 100644 index 3d0e89dd..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0001-tests-also-install-tests-app.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 3ad69d49671cd8f29824840f9cc175f835e413b3 Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Sun, 17 Jan 2016 16:52:40 +0530 -Subject: [PATCH 1/1] tests: also install tests app - -Upstream-Status: Inappropriate [configuration] - -Signed-off-by: Yu Ke <ke.yu@intel.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> ---- - tests/Makefile.am | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/tests/Makefile.am b/tests/Makefile.am -index 58feb12..3e46e16 100644 ---- a/tests/Makefile.am -+++ b/tests/Makefile.am -@@ -29,13 +29,14 @@ AM_CFLAGS = \ - - LDADD = $(top_builddir)/libdrm.la - --check_PROGRAMS = \ -+bin_PROGRAMS = \ - dristat \ - drmdevice \ - drmstat - - dristat_LDADD = -lm - -+check_PROGRAMS = - if HAVE_NOUVEAU - SUBDIRS += nouveau - endif --- -1.9.1 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch deleted file mode 100644 index ff2d910f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch +++ /dev/null @@ -1,77 +0,0 @@ -From e342c0fc250f3f16b817c43e96ab9b839fcb15c2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> -Date: Tue, 15 Dec 2015 14:18:32 +0200 -Subject: [PATCH 002/117] Fix memory leak with drmModeGetConnectorCurrent() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -drmModeGetConnectorCurrent() must provide temporary storage for the -kernel to fill in at least one mode (asking for !=0 modes is how -you prevent the heavyweight probe in the kernel). Currently we malloc -that temp storage but we fail to free it before overwriting the -pointer with the address of the actual storage we use to store the -real mode list we get from the kernel in the second ioctl call. - -Let's just keep the temporary storage on the stack and thus we avoid the -leak and also eliminate some pointless mallocs. - -Cc: Chris Wilson <chris@chris-wilson.co.uk> -Fixes: 5ed5fa10600f ("mode: Retrieve only the current information for a Connector") -Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> -Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> ---- - xf86drmMode.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - -diff --git a/xf86drmMode.c b/xf86drmMode.c -index ab6b519..7710061 100644 ---- a/xf86drmMode.c -+++ b/xf86drmMode.c -@@ -475,12 +475,13 @@ _drmModeGetConnector(int fd, uint32_t connector_id, int probe) - { - struct drm_mode_get_connector conn, counts; - drmModeConnectorPtr r = NULL; -+ struct drm_mode_modeinfo stack_mode; - - memclear(conn); - conn.connector_id = connector_id; - if (!probe) { - conn.count_modes = 1; -- conn.modes_ptr = VOID2U64(drmMalloc(sizeof(struct drm_mode_modeinfo))); -+ conn.modes_ptr = VOID2U64(&stack_mode); - } - - if (drmIoctl(fd, DRM_IOCTL_MODE_GETCONNECTOR, &conn)) -@@ -504,7 +505,7 @@ retry: - goto err_allocs; - } else { - conn.count_modes = 1; -- conn.modes_ptr = VOID2U64(drmMalloc(sizeof(struct drm_mode_modeinfo))); -+ conn.modes_ptr = VOID2U64(&stack_mode); - } - - if (conn.count_encoders) { -@@ -525,7 +526,8 @@ retry: - counts.count_encoders < conn.count_encoders) { - drmFree(U642VOID(conn.props_ptr)); - drmFree(U642VOID(conn.prop_values_ptr)); -- drmFree(U642VOID(conn.modes_ptr)); -+ if (U642VOID(conn.modes_ptr) != &stack_mode) -+ drmFree(U642VOID(conn.modes_ptr)); - drmFree(U642VOID(conn.encoders_ptr)); - - goto retry; -@@ -567,7 +569,8 @@ retry: - err_allocs: - drmFree(U642VOID(conn.prop_values_ptr)); - drmFree(U642VOID(conn.props_ptr)); -- drmFree(U642VOID(conn.modes_ptr)); -+ if (U642VOID(conn.modes_ptr) != &stack_mode) -+ drmFree(U642VOID(conn.modes_ptr)); - drmFree(U642VOID(conn.encoders_ptr)); - - return r; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0003-configure.ac-disable-annoying-warning-Wmissing-field.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0003-configure.ac-disable-annoying-warning-Wmissing-field.patch deleted file mode 100644 index 5bc53983..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0003-configure.ac-disable-annoying-warning-Wmissing-field.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 5198f2b2e658651d9cb81d67998ba7b2c39e12d7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Tue, 12 Jan 2016 22:09:24 +0100 -Subject: [PATCH 003/117] configure.ac: disable annoying warning - -Wmissing-field-initializers - -It warns for all "{}" initializers. - -Reviewed-by: David Herrmann <dh.herrmann@gmail.com> -Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> ---- - configure.ac | 3 ++- - intel/intel_decode.c | 2 -- - 2 files changed, 2 insertions(+), 3 deletions(-) - -diff --git a/configure.ac b/configure.ac -index c8c4ace..057a846 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -174,7 +174,8 @@ MAYBE_WARN="-Wall -Wextra \ - -Wstrict-aliasing=2 -Winit-self \ - -Wdeclaration-after-statement -Wold-style-definition \ - -Wno-unused-parameter \ ---Wno-attributes -Wno-long-long -Winline -Wshadow" -+-Wno-attributes -Wno-long-long -Winline -Wshadow \ -+-Wno-missing-field-initializers" - - # invalidate cached value if MAYBE_WARN has changed - if test "x$libdrm_cv_warn_maybe" != "x$MAYBE_WARN"; then -diff --git a/intel/intel_decode.c b/intel/intel_decode.c -index e7aef74..287c342 100644 ---- a/intel/intel_decode.c -+++ b/intel/intel_decode.c -@@ -38,8 +38,6 @@ - #include "intel_chipset.h" - #include "intel_bufmgr.h" - --/* The compiler throws ~90 warnings. Do not spam the build, until we fix them. */ --#pragma GCC diagnostic ignored "-Wmissing-field-initializers" - - /* Struct for tracking drm_intel_decode state. */ - struct drm_intel_decode { --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0004-amdgpu-drop-address-patching-logics.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0004-amdgpu-drop-address-patching-logics.patch deleted file mode 100644 index 187930cd..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0004-amdgpu-drop-address-patching-logics.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 50386e09dbdc6fd70d02efd1371d9ad061c8d447 Mon Sep 17 00:00:00 2001 -From: "monk.liu" <monk.liu@amd.com> -Date: Tue, 25 Aug 2015 16:53:07 +0800 -Subject: [PATCH 004/117] amdgpu: drop address patching logics -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -we don't support non-page-aligned cpu pointer anymore - -Signed-off-by: monk.liu <monk.liu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_bo.c | 11 +---------- - 1 file changed, 1 insertion(+), 10 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 1a5a401..2ae1c18 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -537,17 +537,8 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - int r; - struct amdgpu_bo *bo; - struct drm_amdgpu_gem_userptr args; -- uintptr_t cpu0; -- uint32_t ps, off; - -- memset(&args, 0, sizeof(args)); -- ps = getpagesize(); -- -- cpu0 = ROUND_DOWN((uintptr_t)cpu, ps); -- off = (uintptr_t)cpu - cpu0; -- size = ROUND_UP(size + off, ps); -- -- args.addr = cpu0; -+ args.addr = (uintptr_t)cpu; - args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER; - args.size = size; - r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0005-amdgpu-validate-user-memory-for-userptr.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0005-amdgpu-validate-user-memory-for-userptr.patch deleted file mode 100644 index 9379fd99..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0005-amdgpu-validate-user-memory-for-userptr.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f06c9928198d9348fb31325a2a480afbc29c04b8 Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Mon, 30 Nov 2015 14:08:07 +0800 -Subject: [PATCH 005/117] amdgpu: validate user memory for userptr -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_bo.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 2ae1c18..d30fd1e 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -539,7 +539,8 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - struct drm_amdgpu_gem_userptr args; - - args.addr = (uintptr_t)cpu; -- args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER; -+ args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER | -+ AMDGPU_GEM_USERPTR_VALIDATE; - args.size = size; - r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR, - &args, sizeof(args)); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0006-amdgpu-add-semaphore-support.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0006-amdgpu-add-semaphore-support.patch deleted file mode 100644 index e3801da4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0006-amdgpu-add-semaphore-support.patch +++ /dev/null @@ -1,403 +0,0 @@ -From 6afadeaf13279fcdbc48999f522e1dc90a9dfdaf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> -Date: Tue, 12 Jan 2016 22:13:07 +0100 -Subject: [PATCH 006/117] amdgpu: add semaphore support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -the semaphore is a binary semaphore. the work flow is: -1. create sem -2. signal sem -3. wait sem, reset sem after signalled -4. destroy sem. - -Signed-off-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 65 ++++++++++++++++++ - amdgpu/amdgpu_cs.c | 173 +++++++++++++++++++++++++++++++++++++++++++++-- - amdgpu/amdgpu_internal.h | 15 ++++ - 3 files changed, 249 insertions(+), 4 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index e44d802..0851306 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -124,6 +124,11 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; - */ - typedef struct amdgpu_va *amdgpu_va_handle; - -+/** -+ * Define handle for semaphore -+ */ -+typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; -+ - /*--------------------------------------------------------------------------*/ - /* -------------------------- Structures ---------------------------------- */ - /*--------------------------------------------------------------------------*/ -@@ -1180,4 +1185,64 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - uint64_t flags, - uint32_t ops); - -+/** -+ * create semaphore -+ * -+ * \param sem - \c [out] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem); -+ -+/** -+ * signal semaphore -+ * -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [in] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem); -+ -+/** -+ * wait semaphore -+ * -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [in] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem); -+ -+/** -+ * destroy semaphore -+ * -+ * \param sem - \c [in] semaphore handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); -+ - #endif /* #ifdef _AMDGPU_H_ */ -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 6747158..1848ade 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -40,6 +40,9 @@ - #include "amdgpu_drm.h" - #include "amdgpu_internal.h" - -+static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem); -+static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem); -+ - /** - * Create command submission context - * -@@ -53,6 +56,7 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - { - struct amdgpu_context *gpu_context; - union drm_amdgpu_ctx args; -+ int i, j, k; - int r; - - if (NULL == dev) -@@ -66,6 +70,10 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - - gpu_context->dev = dev; - -+ r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL); -+ if (r) -+ goto error; -+ - /* Create the context */ - memset(&args, 0, sizeof(args)); - args.in.op = AMDGPU_CTX_OP_ALLOC_CTX; -@@ -74,11 +82,16 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - goto error; - - gpu_context->id = args.out.alloc.ctx_id; -+ for (i = 0; i < AMDGPU_HW_IP_NUM; i++) -+ for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) -+ for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) -+ list_inithead(&gpu_context->sem_list[i][j][k]); - *context = (amdgpu_context_handle)gpu_context; - - return 0; - - error: -+ pthread_mutex_destroy(&gpu_context->sequence_mutex); - free(gpu_context); - return r; - } -@@ -94,18 +107,32 @@ error: - int amdgpu_cs_ctx_free(amdgpu_context_handle context) - { - union drm_amdgpu_ctx args; -+ int i, j, k; - int r; - - if (NULL == context) - return -EINVAL; - -+ pthread_mutex_destroy(&context->sequence_mutex); -+ - /* now deal with kernel side */ - memset(&args, 0, sizeof(args)); - args.in.op = AMDGPU_CTX_OP_FREE_CTX; - args.in.ctx_id = context->id; - r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, - &args, sizeof(args)); -- -+ for (i = 0; i < AMDGPU_HW_IP_NUM; i++) { -+ for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) { -+ for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) { -+ amdgpu_semaphore_handle sem; -+ LIST_FOR_EACH_ENTRY(sem, &context->sem_list[i][j][k], list) { -+ list_del(&sem->list); -+ amdgpu_cs_reset_sem(sem); -+ amdgpu_cs_unreference_sem(sem); -+ } -+ } -+ } -+ } - free(context); - - return r; -@@ -150,7 +177,10 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - struct drm_amdgpu_cs_chunk *chunks; - struct drm_amdgpu_cs_chunk_data *chunk_data; - struct drm_amdgpu_cs_chunk_dep *dependencies = NULL; -- uint32_t i, size; -+ struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL; -+ struct list_head *sem_list; -+ amdgpu_semaphore_handle sem; -+ uint32_t i, size, sem_count = 0; - bool user_fence; - int r = 0; - -@@ -162,7 +192,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - return -EINVAL; - user_fence = (ibs_request->fence_info.handle != NULL); - -- size = ibs_request->number_of_ibs + (user_fence ? 2 : 1); -+ size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1; - - chunk_array = alloca(sizeof(uint64_t) * size); - chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size); -@@ -196,6 +226,8 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - chunk_data[i].ib_data.flags = ib->flags; - } - -+ pthread_mutex_lock(&context->sequence_mutex); -+ - if (user_fence) { - i = cs.in.num_chunks++; - -@@ -240,15 +272,49 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies; - } - -+ sem_list = &context->sem_list[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring]; -+ LIST_FOR_EACH_ENTRY(sem, sem_list, list) -+ sem_count++; -+ if (sem_count) { -+ sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count); -+ if (!sem_dependencies) { -+ r = -ENOMEM; -+ goto error_unlock; -+ } -+ sem_count = 0; -+ LIST_FOR_EACH_ENTRY(sem, sem_list, list) { -+ struct amdgpu_cs_fence *info = &sem->signal_fence; -+ struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++]; -+ dep->ip_type = info->ip_type; -+ dep->ip_instance = info->ip_instance; -+ dep->ring = info->ring; -+ dep->ctx_id = info->context->id; -+ dep->handle = info->fence; -+ -+ list_del(&sem->list); -+ amdgpu_cs_reset_sem(sem); -+ amdgpu_cs_unreference_sem(sem); -+ } -+ i = cs.in.num_chunks++; -+ -+ /* dependencies chunk */ -+ chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; -+ chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES; -+ chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count; -+ chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies; -+ } -+ - r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS, - &cs, sizeof(cs)); - if (r) - goto error_unlock; - - ibs_request->seq_no = cs.out.handle; -- -+ context->last_seq[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring] = ibs_request->seq_no; - error_unlock: -+ pthread_mutex_unlock(&context->sequence_mutex); - free(dependencies); -+ free(sem_dependencies); - return r; - } - -@@ -369,3 +435,102 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - return r; - } - -+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) -+{ -+ struct amdgpu_semaphore *gpu_semaphore; -+ -+ if (NULL == sem) -+ return -EINVAL; -+ -+ gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore)); -+ if (NULL == gpu_semaphore) -+ return -ENOMEM; -+ -+ atomic_set(&gpu_semaphore->refcount, 1); -+ *sem = gpu_semaphore; -+ -+ return 0; -+} -+ -+int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem) -+{ -+ if (NULL == ctx) -+ return -EINVAL; -+ if (ip_type >= AMDGPU_HW_IP_NUM) -+ return -EINVAL; -+ if (ring >= AMDGPU_CS_MAX_RINGS) -+ return -EINVAL; -+ if (NULL == sem) -+ return -EINVAL; -+ /* sem has been signaled */ -+ if (sem->signal_fence.context) -+ return -EINVAL; -+ pthread_mutex_lock(&ctx->sequence_mutex); -+ sem->signal_fence.context = ctx; -+ sem->signal_fence.ip_type = ip_type; -+ sem->signal_fence.ip_instance = ip_instance; -+ sem->signal_fence.ring = ring; -+ sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring]; -+ update_references(NULL, &sem->refcount); -+ pthread_mutex_unlock(&ctx->sequence_mutex); -+ return 0; -+} -+ -+int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_semaphore_handle sem) -+{ -+ if (NULL == ctx) -+ return -EINVAL; -+ if (ip_type >= AMDGPU_HW_IP_NUM) -+ return -EINVAL; -+ if (ring >= AMDGPU_CS_MAX_RINGS) -+ return -EINVAL; -+ if (NULL == sem) -+ return -EINVAL; -+ /* must signal first */ -+ if (NULL == sem->signal_fence.context) -+ return -EINVAL; -+ -+ pthread_mutex_lock(&ctx->sequence_mutex); -+ list_add(&sem->list, &ctx->sem_list[ip_type][ip_instance][ring]); -+ pthread_mutex_unlock(&ctx->sequence_mutex); -+ return 0; -+} -+ -+static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem) -+{ -+ if (NULL == sem) -+ return -EINVAL; -+ if (NULL == sem->signal_fence.context) -+ return -EINVAL; -+ -+ sem->signal_fence.context = NULL;; -+ sem->signal_fence.ip_type = 0; -+ sem->signal_fence.ip_instance = 0; -+ sem->signal_fence.ring = 0; -+ sem->signal_fence.fence = 0; -+ -+ return 0; -+} -+ -+static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem) -+{ -+ if (NULL == sem) -+ return -EINVAL; -+ -+ if (update_references(&sem->refcount, NULL)) -+ free(sem); -+ return 0; -+} -+ -+int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) -+{ -+ return amdgpu_cs_unreference_sem(sem); -+} -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 7dd5c1c..557ba1f 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -111,8 +111,23 @@ struct amdgpu_bo_list { - - struct amdgpu_context { - struct amdgpu_device *dev; -+ /** Mutex for accessing fences and to maintain command submissions -+ in good sequence. */ -+ pthread_mutex_t sequence_mutex; - /* context id*/ - uint32_t id; -+ uint64_t last_seq[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS]; -+ struct list_head sem_list[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS]; -+}; -+ -+/** -+ * Structure describing sw semaphore based on scheduler -+ * -+ */ -+struct amdgpu_semaphore { -+ atomic_t refcount; -+ struct list_head list; -+ struct amdgpu_cs_fence signal_fence; - }; - - /** --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0007-tests-amdgpu-add-semaphore-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0007-tests-amdgpu-add-semaphore-test.patch deleted file mode 100644 index ae7c4bd9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0007-tests-amdgpu-add-semaphore-test.patch +++ /dev/null @@ -1,183 +0,0 @@ -From d4d4184363a62ece6b8830cacaf390b5638d7f8e Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <david1.zhou@amd.com> -Date: Mon, 10 Aug 2015 17:08:25 +0800 -Subject: [PATCH 007/117] tests/amdgpu: add semaphore test -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/basic_tests.c | 133 +++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 133 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index e489e6e..fa0ed12 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -47,6 +47,7 @@ static void amdgpu_command_submission_gfx(void); - static void amdgpu_command_submission_compute(void); - static void amdgpu_command_submission_sdma(void); - static void amdgpu_userptr_test(void); -+static void amdgpu_semaphore_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -55,6 +56,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, - { "Command submission Test (Compute)", amdgpu_command_submission_compute }, - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, -+ { "SW semaphore Test", amdgpu_semaphore_test }, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -@@ -77,6 +79,9 @@ CU_TestInfo basic_tests[] = { - #define SDMA_OPCODE_COPY 1 - # define SDMA_COPY_SUB_OPCODE_LINEAR 0 - -+#define GFX_COMPUTE_NOP 0xffff1000 -+#define SDMA_NOP 0x0 -+ - int suite_basic_tests_init(void) - { - int r; -@@ -333,6 +338,134 @@ static void amdgpu_command_submission_gfx(void) - amdgpu_command_submission_gfx_shared_ib(); - } - -+static void amdgpu_semaphore_test(void) -+{ -+ amdgpu_context_handle context_handle[2]; -+ amdgpu_semaphore_handle sem; -+ amdgpu_bo_handle ib_result_handle[2]; -+ void *ib_result_cpu[2]; -+ uint64_t ib_result_mc_address[2]; -+ struct amdgpu_cs_request ibs_request[2] = {0}; -+ struct amdgpu_cs_ib_info ib_info[2] = {0}; -+ struct amdgpu_cs_fence fence_status = {0}; -+ uint32_t *ptr; -+ uint32_t expired; -+ amdgpu_bo_list_handle bo_list[2]; -+ amdgpu_va_handle va_handle[2]; -+ int r, i; -+ -+ r = amdgpu_cs_create_semaphore(&sem); -+ CU_ASSERT_EQUAL(r, 0); -+ for (i = 0; i < 2; i++) { -+ r = amdgpu_cs_ctx_create(device_handle, &context_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_result_handle[i], &ib_result_cpu[i], -+ &ib_result_mc_address[i], &va_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_get_bo_list(device_handle, ib_result_handle[i], -+ NULL, &bo_list[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ /* 1. same context different engine */ -+ ptr = ib_result_cpu[0]; -+ ptr[0] = SDMA_NOP; -+ ib_info[0].ib_mc_address = ib_result_mc_address[0]; -+ ib_info[0].size = 1; -+ -+ ibs_request[0].ip_type = AMDGPU_HW_IP_DMA; -+ ibs_request[0].number_of_ibs = 1; -+ ibs_request[0].ibs = &ib_info[0]; -+ ibs_request[0].resources = bo_list[0]; -+ ibs_request[0].fence_info.handle = NULL; -+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ ptr = ib_result_cpu[1]; -+ ptr[0] = GFX_COMPUTE_NOP; -+ ib_info[1].ib_mc_address = ib_result_mc_address[1]; -+ ib_info[1].size = 1; -+ -+ ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[1].number_of_ibs = 1; -+ ibs_request[1].ibs = &ib_info[1]; -+ ibs_request[1].resources = bo_list[1]; -+ ibs_request[1].fence_info.handle = NULL; -+ -+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[1], 1); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ fence_status.context = context_handle[0]; -+ fence_status.ip_type = AMDGPU_HW_IP_GFX; -+ fence_status.fence = ibs_request[1].seq_no; -+ r = amdgpu_cs_query_fence_status(&fence_status, -+ 500000000, 0, &expired); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_EQUAL(expired, true); -+ -+ /* 2. same engine different context */ -+ ptr = ib_result_cpu[0]; -+ ptr[0] = GFX_COMPUTE_NOP; -+ ib_info[0].ib_mc_address = ib_result_mc_address[0]; -+ ib_info[0].size = 1; -+ -+ ibs_request[0].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[0].number_of_ibs = 1; -+ ibs_request[0].ibs = &ib_info[0]; -+ ibs_request[0].resources = bo_list[0]; -+ ibs_request[0].fence_info.handle = NULL; -+ r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); -+ CU_ASSERT_EQUAL(r, 0); -+ ptr = ib_result_cpu[1]; -+ ptr[0] = GFX_COMPUTE_NOP; -+ ib_info[1].ib_mc_address = ib_result_mc_address[1]; -+ ib_info[1].size = 1; -+ -+ ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[1].number_of_ibs = 1; -+ ibs_request[1].ibs = &ib_info[1]; -+ ibs_request[1].resources = bo_list[1]; -+ ibs_request[1].fence_info.handle = NULL; -+ r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1); -+ -+ CU_ASSERT_EQUAL(r, 0); -+ -+ fence_status.context = context_handle[1]; -+ fence_status.ip_type = AMDGPU_HW_IP_GFX; -+ fence_status.fence = ibs_request[1].seq_no; -+ r = amdgpu_cs_query_fence_status(&fence_status, -+ 500000000, 0, &expired); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_EQUAL(expired, true); -+ for (i = 0; i < 2; i++) { -+ r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], -+ ib_result_mc_address[i], 4096); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_list_destroy(bo_list[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_ctx_free(context_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ r = amdgpu_cs_destroy_semaphore(sem); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ - static void amdgpu_command_submission_compute(void) - { - amdgpu_context_handle context_handle; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch deleted file mode 100644 index 58cb2238..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6b79c66b841dded6ffa6b56f14e4eb10a90a7c07 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 8 Dec 2015 08:34:55 +0800 -Subject: [PATCH 008/117] amdgpu: list each entry safely for sw semaphore when - submit ib -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> -Reviewed-by: David Zhou <david1.zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_cs.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 1848ade..b4f41b0 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -179,7 +179,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - struct drm_amdgpu_cs_chunk_dep *dependencies = NULL; - struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL; - struct list_head *sem_list; -- amdgpu_semaphore_handle sem; -+ amdgpu_semaphore_handle sem, tmp; - uint32_t i, size, sem_count = 0; - bool user_fence; - int r = 0; -@@ -282,7 +282,7 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - goto error_unlock; - } - sem_count = 0; -- LIST_FOR_EACH_ENTRY(sem, sem_list, list) { -+ LIST_FOR_EACH_ENTRY_SAFE(sem, tmp, sem_list, list) { - struct amdgpu_cs_fence *info = &sem->signal_fence; - struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++]; - dep->ip_type = info->ip_type; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch deleted file mode 100644 index 2130d0c9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 25712f1d35f6f64167ede45d3dc72a410f367ceb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> -Date: Wed, 20 Jan 2016 15:59:08 +0900 -Subject: [PATCH 009/117] amdgpu: Add new symbols to amdgpu-symbols-check - -Fixes make check. - -Trivial. ---- - amdgpu/amdgpu-symbol-check | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index 9a0b36c..648db9b 100755 ---- a/amdgpu/amdgpu-symbol-check -+++ b/amdgpu/amdgpu-symbol-check -@@ -24,11 +24,15 @@ amdgpu_bo_set_metadata - amdgpu_bo_va_op - amdgpu_bo_wait_for_idle - amdgpu_create_bo_from_user_mem -+amdgpu_cs_create_semaphore - amdgpu_cs_ctx_create - amdgpu_cs_ctx_free -+amdgpu_cs_destroy_semaphore - amdgpu_cs_query_fence_status - amdgpu_cs_query_reset_state -+amdgpu_cs_signal_semaphore - amdgpu_cs_submit -+amdgpu_cs_wait_semaphore - amdgpu_device_deinitialize - amdgpu_device_initialize - amdgpu_query_buffer_size_alignment --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch deleted file mode 100644 index 2eb10e95..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch +++ /dev/null @@ -1,30 +0,0 @@ -From db138b9ba12a0de5d6140832c0679c2418e3e7e0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> -Date: Thu, 21 Jan 2016 18:08:49 +0900 -Subject: [PATCH 010/117] radeon: Pass radeon_bo_open flags to the - DRM_RADEON_GEM_CREATE ioctl - -Not doing so makes it impossible for radeon_bo_open callers to set any -RADEON_GEM_* flags for the newly created BO. - -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - radeon/radeon_bo_gem.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c -index c9fe19f..fbd453d 100644 ---- a/radeon/radeon_bo_gem.c -+++ b/radeon/radeon_bo_gem.c -@@ -103,7 +103,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, - args.size = size; - args.alignment = alignment; - args.initial_domain = bo->base.domains; -- args.flags = 0; -+ args.flags = flags; - args.handle = 0; - r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE, - &args, sizeof(args)); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0011-xf86drm-Bound-strstr-to-the-allocated-data.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0011-xf86drm-Bound-strstr-to-the-allocated-data.patch deleted file mode 100644 index ecb7325a..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0011-xf86drm-Bound-strstr-to-the-allocated-data.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 3627f38da9fad7db7fef2a0c6d0faf706c2e21d6 Mon Sep 17 00:00:00 2001 -From: Damien Lespiau <damien.lespiau@intel.com> -Date: Fri, 22 Jan 2016 12:41:55 +0000 -Subject: [PATCH 011/117] xf86drm: Bound strstr() to the allocated data -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We are reading at most sizeof(data) bytes, but then data may not contain -a terminating '\0', at least in theory, so strstr() may overflow the -stack allocated array. - -Make sure that data always contains at least one '\0'. - -Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> -Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> ---- - xf86drm.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 7e28b4f..5f587d9 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -2863,7 +2863,7 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info) - { - #ifdef __linux__ - char path[PATH_MAX + 1]; -- char data[128]; -+ char data[128 + 1]; - char *str; - int domain, bus, dev, func; - int fd, ret; -@@ -2874,6 +2874,7 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info) - return -errno; - - ret = read(fd, data, sizeof(data)); -+ data[128] = '\0'; - close(fd); - if (ret < 0) - return -errno; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0012-configure.ac-don-t-detect-disabled-options-dependenc.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0012-configure.ac-don-t-detect-disabled-options-dependenc.patch deleted file mode 100644 index eef84dae..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0012-configure.ac-don-t-detect-disabled-options-dependenc.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 798022b61c58d945f9027c823a188dcedecd3d06 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= <marcin.slusarz@gmail.com> -Date: Sun, 24 Jan 2016 13:17:34 +0100 -Subject: [PATCH 012/117] configure.ac: don't detect disabled options - dependencies -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Currently with --disable-amdgpu --disable-valgrind --disable-cairo-tests -cunit, valgrind and cairo are still detected. - -Signed-off-by: Marcin Ślusarz <marcin.slusarz@gmail.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - configure.ac | 36 ++++++++++++++++++++++-------------- - 1 file changed, 22 insertions(+), 14 deletions(-) - -diff --git a/configure.ac b/configure.ac -index 057a846..a09be61 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -360,19 +360,23 @@ if test "x$RADEON" = xyes; then - AC_DEFINE(HAVE_RADEON, 1, [Have radeon support]) - fi - --# Detect cunit library --PKG_CHECK_MODULES([CUNIT], [cunit >= 2.1], [have_cunit=yes], [have_cunit=no]) --# If pkg-config does not find cunit, check it using AC_CHECK_LIB. We --# do this because Debian (Ubuntu) lacks pkg-config file for cunit. --# fixed in 2.1-2.dfsg-3: http://anonscm.debian.org/cgit/collab-maint/cunit.git/commit/?h=debian --if test "x${have_cunit}" = "xno"; then -- AC_CHECK_LIB([cunit], [CU_initialize_registry], [have_cunit=yes], [have_cunit=no]) -- if test "x${have_cunit}" = "xyes"; then -- CUNIT_LIBS="-lcunit" -- CUNIT_CFLAGS="" -- AC_SUBST([CUNIT_LIBS]) -- AC_SUBST([CUNIT_CFLAGS]) -+if test "x$AMDGPU" != xno; then -+ # Detect cunit library -+ PKG_CHECK_MODULES([CUNIT], [cunit >= 2.1], [have_cunit=yes], [have_cunit=no]) -+ # If pkg-config does not find cunit, check it using AC_CHECK_LIB. We -+ # do this because Debian (Ubuntu) lacks pkg-config file for cunit. -+ # fixed in 2.1-2.dfsg-3: http://anonscm.debian.org/cgit/collab-maint/cunit.git/commit/?h=debian -+ if test "x${have_cunit}" = "xno"; then -+ AC_CHECK_LIB([cunit], [CU_initialize_registry], [have_cunit=yes], [have_cunit=no]) -+ if test "x${have_cunit}" = "xyes"; then -+ CUNIT_LIBS="-lcunit" -+ CUNIT_CFLAGS="" -+ AC_SUBST([CUNIT_LIBS]) -+ AC_SUBST([CUNIT_CFLAGS]) -+ fi - fi -+else -+ have_cunit=no - fi - AM_CONDITIONAL(HAVE_CUNIT, [test "x$have_cunit" != "xno"]) - -@@ -401,7 +405,9 @@ AC_ARG_ENABLE([cairo-tests], - [AS_HELP_STRING([--enable-cairo-tests], - [Enable support for Cairo rendering in tests (default: auto)])], - [CAIRO=$enableval], [CAIRO=auto]) --PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) -+if test "x$CAIRO" != xno; then -+ PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) -+fi - AC_MSG_CHECKING([whether to enable Cairo tests]) - if test "x$CAIRO" = xauto; then - CAIRO="$HAVE_CAIRO" -@@ -446,7 +452,9 @@ AC_ARG_ENABLE(valgrind, - [AS_HELP_STRING([--enable-valgrind], - [Build libdrm with valgrind support (default: auto)])], - [VALGRIND=$enableval], [VALGRIND=auto]) --PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], [have_valgrind=no]) -+if test "x$VALGRIND" != xno; then -+ PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], [have_valgrind=no]) -+fi - AC_MSG_CHECKING([whether to enable Valgrind support]) - if test "x$VALGRIND" = xauto; then - VALGRIND="$have_valgrind" --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0013-kmstest-Use-util_open.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0013-kmstest-Use-util_open.patch deleted file mode 100644 index 88c71442..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0013-kmstest-Use-util_open.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 0caf58a6cb82327a3f6a53f05dea8e02f1412a05 Mon Sep 17 00:00:00 2001 -From: Stefan Agner <stefan@agner.ch> -Date: Sat, 19 Dec 2015 21:52:58 -0800 -Subject: [PATCH 013/117] kmstest: Use util_open() - -Use the new util_open() helper instead of open-coding the method for -finding a usable device. While at it, make the command-line interface -more consistent with that of modetest by adding the -D and -M options. - -Signed-off-by: Stefan Agner <stefan@agner.ch> -v2: correctly use util_open() - swap device, module -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/kmstest/Makefile.am | 4 +++- - tests/kmstest/main.c | 45 +++++++++++++++++++++++++++++---------------- - 2 files changed, 32 insertions(+), 17 deletions(-) - -diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am -index fd21e61..100662e 100644 ---- a/tests/kmstest/Makefile.am -+++ b/tests/kmstest/Makefile.am -@@ -2,6 +2,7 @@ AM_CFLAGS = \ - $(WARN_CFLAGS)\ - -I$(top_srcdir)/include/drm \ - -I$(top_srcdir)/libkms/ \ -+ -I$(top_srcdir)/tests/ \ - -I$(top_srcdir) - - if HAVE_INSTALL_TESTS -@@ -17,7 +18,8 @@ kmstest_SOURCES = \ - - kmstest_LDADD = \ - $(top_builddir)/libdrm.la \ -- $(top_builddir)/libkms/libkms.la -+ $(top_builddir)/libkms/libkms.la \ -+ $(top_builddir)/tests/util/libutil.la - - run: kmstest - ./kmstest -diff --git a/tests/kmstest/main.c b/tests/kmstest/main.c -index 120bc0f..a0e4ebb 100644 ---- a/tests/kmstest/main.c -+++ b/tests/kmstest/main.c -@@ -25,12 +25,14 @@ - * - **************************************************************************/ - -- -+#include <getopt.h> - #include <stdio.h> - #include <string.h> - #include "xf86drm.h" - #include "libkms.h" - -+#include "util/kms.h" -+ - #define CHECK_RET_RETURN(ret, str) \ - if (ret < 0) { \ - printf("%s: %s (%s)\n", __func__, str, strerror(-ret)); \ -@@ -56,26 +58,37 @@ static int test_bo(struct kms_driver *kms) - return 0; - } - --static const char *drivers[] = { -- "i915", -- "radeon", -- "nouveau", -- "vmwgfx", -- "exynos", -- "amdgpu", -- "imx-drm", -- "rockchip", -- "atmel-hlcdc", -- NULL --}; -+static void usage(const char *program) -+{ -+ fprintf(stderr, "Usage: %s [options]\n", program); -+ fprintf(stderr, "\n"); -+ fprintf(stderr, " -D DEVICE open the given device\n"); -+ fprintf(stderr, " -M MODULE open the given module\n"); -+} - - int main(int argc, char** argv) - { -+ static const char optstr[] = "D:M:"; - struct kms_driver *kms; -- int ret, fd, i; -+ int c, fd, ret; -+ char *device = NULL; -+ char *module = NULL; -+ -+ while ((c = getopt(argc, argv, optstr)) != -1) { -+ switch (c) { -+ case 'D': -+ device = optarg; -+ break; -+ case 'M': -+ module = optarg; -+ break; -+ default: -+ usage(argv[0]); -+ return 0; -+ } -+ } - -- for (i = 0, fd = -1; fd < 0 && drivers[i]; i++) -- fd = drmOpen(drivers[i], NULL); -+ fd = util_open(device, module); - CHECK_RET_RETURN(fd, "Could not open device"); - - ret = kms_create(fd, &kms); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0014-tests-add-fsl-dcu-drm-to-modules.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0014-tests-add-fsl-dcu-drm-to-modules.patch deleted file mode 100644 index fd43c02c..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0014-tests-add-fsl-dcu-drm-to-modules.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2ad5ea780b3cca83ae4f531ae0b4159e802ef825 Mon Sep 17 00:00:00 2001 -From: Stefan Agner <stefan@agner.ch> -Date: Sat, 19 Dec 2015 21:52:59 -0800 -Subject: [PATCH 014/117] tests: add fsl-dcu-drm to modules - -Signed-off-by: Stefan Agner <stefan@agner.ch> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/util/kms.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/tests/util/kms.c b/tests/util/kms.c -index 57b0191..dcd5a8e 100644 ---- a/tests/util/kms.c -+++ b/tests/util/kms.c -@@ -139,6 +139,7 @@ static const char * const modules[] = { - "imx-drm", - "rockchip", - "atmel-hlcdc", -+ "fsl-dcu-drm", - }; - - int util_open(const char *device, const char *module) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0015-tests-util-Fixup-util_open-parameter-order.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0015-tests-util-Fixup-util_open-parameter-order.patch deleted file mode 100644 index bb7969bb..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0015-tests-util-Fixup-util_open-parameter-order.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 1674147a149c2165a927a5d8eb0db4eee1f6a4e3 Mon Sep 17 00:00:00 2001 -From: Thierry Reding <treding@nvidia.com> -Date: Tue, 5 Jan 2016 15:21:23 +0100 -Subject: [PATCH 015/117] tests: util: Fixup util_open() parameter order - -util_open() takes a device parameter, followed by a module parameter. -The existing tests used the drmOpen() function, which uses a different -ordering of the parameters, and the old ordering was accidentally kept -during the conversion. - -Signed-off-by: Thierry Reding <treding@nvidia.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/modetest/modetest.c | 2 +- - tests/proptest/proptest.c | 2 +- - tests/vbltest/vbltest.c | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c -index 22e3e81..f665240 100644 ---- a/tests/modetest/modetest.c -+++ b/tests/modetest/modetest.c -@@ -1603,7 +1603,7 @@ int main(int argc, char **argv) - if (!args) - encoders = connectors = crtcs = planes = framebuffers = 1; - -- dev.fd = util_open(module, device); -+ dev.fd = util_open(device, module); - if (dev.fd < 0) - return -1; - -diff --git a/tests/proptest/proptest.c b/tests/proptest/proptest.c -index 24c6345..4bd0866 100644 ---- a/tests/proptest/proptest.c -+++ b/tests/proptest/proptest.c -@@ -295,7 +295,7 @@ int main(int argc, char *argv[]) - - args = argc - optind; - -- fd = util_open(module, device); -+ fd = util_open(device, module); - if (fd < 0) - return 1; - -diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c -index 1833321..4475b49 100644 ---- a/tests/vbltest/vbltest.c -+++ b/tests/vbltest/vbltest.c -@@ -120,7 +120,7 @@ int main(int argc, char **argv) - } - } - -- fd = util_open(module, device); -+ fd = util_open(device, module); - if (fd < 0) - return 1; - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0016-tests-Include-sys-select.h.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0016-tests-Include-sys-select.h.patch deleted file mode 100644 index 0427f35f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0016-tests-Include-sys-select.h.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 358615f416a8f3085a63c03a55564f71946083d1 Mon Sep 17 00:00:00 2001 -From: Khem Raj <raj.khem@gmail.com> -Date: Wed, 20 Jan 2016 05:35:11 +0000 -Subject: [PATCH 016/117] tests: Include sys/select.h - -Used in compliance with POSIX 2001/2008 - -Fixes errors e.g. -error: implicit declaration of function 'select' - -and helps with missing definitions of FD_* defines - -v2: conditionally include sys/select.h, include in every test where -needed. - -Signed-off-by: Khem Raj <raj.khem@gmail.com> -Reviewed-by: Thierry Reding <thierry.reding@gmail.com> (v1) -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - configure.ac | 2 +- - tests/kms/kms-steal-crtc.c | 3 +++ - tests/kms/kms-universal-planes.c | 3 +++ - tests/modetest/modetest.c | 3 +++ - tests/vbltest/vbltest.c | 3 +++ - 5 files changed, 13 insertions(+), 1 deletion(-) - -diff --git a/configure.ac b/configure.ac -index a09be61..4635d18 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -53,7 +53,7 @@ AC_USE_SYSTEM_EXTENSIONS - AC_SYS_LARGEFILE - AC_FUNC_ALLOCA - --AC_CHECK_HEADERS([sys/mkdev.h sys/sysctl.h]) -+AC_CHECK_HEADERS([sys/mkdev.h sys/sysctl.h sys/select.h]) - - # Initialize libtool - LT_PREREQ([2.2]) -diff --git a/tests/kms/kms-steal-crtc.c b/tests/kms/kms-steal-crtc.c -index 2f7f327..497772e 100644 ---- a/tests/kms/kms-steal-crtc.c -+++ b/tests/kms/kms-steal-crtc.c -@@ -31,6 +31,9 @@ - #include <stdio.h> - #include <string.h> - #include <unistd.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include <drm_fourcc.h> - -diff --git a/tests/kms/kms-universal-planes.c b/tests/kms/kms-universal-planes.c -index 9151231..d8e5fc4 100644 ---- a/tests/kms/kms-universal-planes.c -+++ b/tests/kms/kms-universal-planes.c -@@ -32,6 +32,9 @@ - #include <stdio.h> - #include <string.h> - #include <unistd.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include <drm_fourcc.h> - #include "xf86drm.h" -diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c -index f665240..b8aa94b 100644 ---- a/tests/modetest/modetest.c -+++ b/tests/modetest/modetest.c -@@ -55,6 +55,9 @@ - #include <errno.h> - #include <sys/poll.h> - #include <sys/time.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include "xf86drm.h" - #include "xf86drmMode.h" -diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c -index 4475b49..97dd44d 100644 ---- a/tests/vbltest/vbltest.c -+++ b/tests/vbltest/vbltest.c -@@ -37,6 +37,9 @@ - #include <errno.h> - #include <sys/poll.h> - #include <sys/time.h> -+#ifdef HAVE_SYS_SELECT_H -+#include <sys/select.h> -+#endif - - #include "xf86drm.h" - #include "xf86drmMode.h" --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0017-tests-Include-poll.h-rather-than-sys-poll.h.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0017-tests-Include-poll.h-rather-than-sys-poll.h.patch deleted file mode 100644 index e95eb5a7..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0017-tests-Include-poll.h-rather-than-sys-poll.h.patch +++ /dev/null @@ -1,46 +0,0 @@ -From ff0c9caa8e1e076b82241304dfd19d5b3e2a2aec Mon Sep 17 00:00:00 2001 -From: Kylie McClain <somasis@exherbo.org> -Date: Tue, 19 Jan 2016 22:27:28 -0500 -Subject: [PATCH 017/117] tests: Include poll.h rather than sys/poll.h - -sys/poll.h is a non-standard location of the poll.h header, and is -incorrect on non-glibc libcs. poll.h, however, is defined in SUS (v2) -and is more portable. - -Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93764 -http://pubs.opengroup.org/onlinepubs/007908799/xsh/poll.h.html -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/modetest/modetest.c | 2 +- - tests/vbltest/vbltest.c | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c -index b8aa94b..a5ac5bd 100644 ---- a/tests/modetest/modetest.c -+++ b/tests/modetest/modetest.c -@@ -53,7 +53,7 @@ - #include <string.h> - #include <strings.h> - #include <errno.h> --#include <sys/poll.h> -+#include <poll.h> - #include <sys/time.h> - #ifdef HAVE_SYS_SELECT_H - #include <sys/select.h> -diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c -index 97dd44d..3f6b803 100644 ---- a/tests/vbltest/vbltest.c -+++ b/tests/vbltest/vbltest.c -@@ -35,7 +35,7 @@ - #include <unistd.h> - #include <string.h> - #include <errno.h> --#include <sys/poll.h> -+#include <poll.h> - #include <sys/time.h> - #ifdef HAVE_SYS_SELECT_H - #include <sys/select.h> --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch deleted file mode 100644 index f76604c0..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 432e08de88a27313608cced27f133a65e8a56c52 Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Wed, 27 Jan 2016 11:59:43 +0000 -Subject: [PATCH 018/117] tests/kmstest: inverse the order of LDADD libraries - -The utils library depends on libdrm. Flip the order, orderwise we might -error during link stage like below: - - CC main.o - CCLD kmstest -/usr/bin/ld: ../../tests/util/.libs/libutil.a(libutil_la-kms.o): -undefined reference to symbol 'drmOpen' - -Reported-by: Tom Stellard <thomas.stellard@amd.com> -Tested-by: Tom Stellard <thomas.stellard@amd.com> -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - tests/kmstest/Makefile.am | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am -index 100662e..ced541b 100644 ---- a/tests/kmstest/Makefile.am -+++ b/tests/kmstest/Makefile.am -@@ -17,9 +17,9 @@ kmstest_SOURCES = \ - main.c - - kmstest_LDADD = \ -- $(top_builddir)/libdrm.la \ -+ $(top_builddir)/tests/util/libutil.la \ - $(top_builddir)/libkms/libkms.la \ -- $(top_builddir)/tests/util/libutil.la -+ $(top_builddir)/libdrm.la - - run: kmstest - ./kmstest --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0019-vc4-Add-the-DRM-header-file.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0019-vc4-Add-the-DRM-header-file.patch deleted file mode 100644 index b87d376d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0019-vc4-Add-the-DRM-header-file.patch +++ /dev/null @@ -1,316 +0,0 @@ -From eeb23de23bf2c0aeff4e36b0513ea13ac09c0438 Mon Sep 17 00:00:00 2001 -From: Eric Anholt <eric@anholt.net> -Date: Fri, 22 Jan 2016 16:34:14 -0800 -Subject: [PATCH 019/117] vc4: Add the DRM header file. - -I'll build some libdrm C code soon, but for now this lets libdrm users -use vc4 ioctls. Produced from headers_install of -1df59b8497f47495e873c23abd6d3d290c730505 (drm-next) in the kernel. - -Signed-off-by: Eric Anholt <eric@anholt.net> ---- - Makefile.sources | 1 + - include/drm/vc4_drm.h | 279 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 280 insertions(+) - create mode 100644 include/drm/vc4_drm.h - -diff --git a/Makefile.sources b/Makefile.sources -index a77f48d..1a1f0fe 100644 ---- a/Makefile.sources -+++ b/Makefile.sources -@@ -32,6 +32,7 @@ LIBDRM_INCLUDE_H_FILES := \ - include/drm/savage_drm.h \ - include/drm/sis_drm.h \ - include/drm/tegra_drm.h \ -+ include/drm/vc4_drm.h \ - include/drm/via_drm.h - - LIBDRM_INCLUDE_VMWGFX_H_FILES := \ -diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h -new file mode 100644 -index 0000000..da3caa0 ---- /dev/null -+++ b/include/drm/vc4_drm.h -@@ -0,0 +1,279 @@ -+/* -+ * Copyright © 2014-2015 Broadcom -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ */ -+ -+#ifndef _VC4_DRM_H_ -+#define _VC4_DRM_H_ -+ -+#include "drm.h" -+ -+#define DRM_VC4_SUBMIT_CL 0x00 -+#define DRM_VC4_WAIT_SEQNO 0x01 -+#define DRM_VC4_WAIT_BO 0x02 -+#define DRM_VC4_CREATE_BO 0x03 -+#define DRM_VC4_MMAP_BO 0x04 -+#define DRM_VC4_CREATE_SHADER_BO 0x05 -+#define DRM_VC4_GET_HANG_STATE 0x06 -+ -+#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) -+#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) -+#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) -+#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) -+#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) -+#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) -+#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) -+ -+struct drm_vc4_submit_rcl_surface { -+ __u32 hindex; /* Handle index, or ~0 if not present. */ -+ __u32 offset; /* Offset to start of buffer. */ -+ /* -+ * Bits for either render config (color_write) or load/store packet. -+ * Bits should all be 0 for MSAA load/stores. -+ */ -+ __u16 bits; -+ -+#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) -+ __u16 flags; -+}; -+ -+/** -+ * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D -+ * engine. -+ * -+ * Drivers typically use GPU BOs to store batchbuffers / command lists and -+ * their associated state. However, because the VC4 lacks an MMU, we have to -+ * do validation of memory accesses by the GPU commands. If we were to store -+ * our commands in BOs, we'd need to do uncached readback from them to do the -+ * validation process, which is too expensive. Instead, userspace accumulates -+ * commands and associated state in plain memory, then the kernel copies the -+ * data to its own address space, and then validates and stores it in a GPU -+ * BO. -+ */ -+struct drm_vc4_submit_cl { -+ /* Pointer to the binner command list. -+ * -+ * This is the first set of commands executed, which runs the -+ * coordinate shader to determine where primitives land on the screen, -+ * then writes out the state updates and draw calls necessary per tile -+ * to the tile allocation BO. -+ */ -+ __u64 bin_cl; -+ -+ /* Pointer to the shader records. -+ * -+ * Shader records are the structures read by the hardware that contain -+ * pointers to uniforms, shaders, and vertex attributes. The -+ * reference to the shader record has enough information to determine -+ * how many pointers are necessary (fixed number for shaders/uniforms, -+ * and an attribute count), so those BO indices into bo_handles are -+ * just stored as __u32s before each shader record passed in. -+ */ -+ __u64 shader_rec; -+ -+ /* Pointer to uniform data and texture handles for the textures -+ * referenced by the shader. -+ * -+ * For each shader state record, there is a set of uniform data in the -+ * order referenced by the record (FS, VS, then CS). Each set of -+ * uniform data has a __u32 index into bo_handles per texture -+ * sample operation, in the order the QPU_W_TMUn_S writes appear in -+ * the program. Following the texture BO handle indices is the actual -+ * uniform data. -+ * -+ * The individual uniform state blocks don't have sizes passed in, -+ * because the kernel has to determine the sizes anyway during shader -+ * code validation. -+ */ -+ __u64 uniforms; -+ __u64 bo_handles; -+ -+ /* Size in bytes of the binner command list. */ -+ __u32 bin_cl_size; -+ /* Size in bytes of the set of shader records. */ -+ __u32 shader_rec_size; -+ /* Number of shader records. -+ * -+ * This could just be computed from the contents of shader_records and -+ * the address bits of references to them from the bin CL, but it -+ * keeps the kernel from having to resize some allocations it makes. -+ */ -+ __u32 shader_rec_count; -+ /* Size in bytes of the uniform state. */ -+ __u32 uniforms_size; -+ -+ /* Number of BO handles passed in (size is that times 4). */ -+ __u32 bo_handle_count; -+ -+ /* RCL setup: */ -+ __u16 width; -+ __u16 height; -+ __u8 min_x_tile; -+ __u8 min_y_tile; -+ __u8 max_x_tile; -+ __u8 max_y_tile; -+ struct drm_vc4_submit_rcl_surface color_read; -+ struct drm_vc4_submit_rcl_surface color_write; -+ struct drm_vc4_submit_rcl_surface zs_read; -+ struct drm_vc4_submit_rcl_surface zs_write; -+ struct drm_vc4_submit_rcl_surface msaa_color_write; -+ struct drm_vc4_submit_rcl_surface msaa_zs_write; -+ __u32 clear_color[2]; -+ __u32 clear_z; -+ __u8 clear_s; -+ -+ __u32 pad:24; -+ -+#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) -+ __u32 flags; -+ -+ /* Returned value of the seqno of this render job (for the -+ * wait ioctl). -+ */ -+ __u64 seqno; -+}; -+ -+/** -+ * struct drm_vc4_wait_seqno - ioctl argument for waiting for -+ * DRM_VC4_SUBMIT_CL completion using its returned seqno. -+ * -+ * timeout_ns is the timeout in nanoseconds, where "0" means "don't -+ * block, just return the status." -+ */ -+struct drm_vc4_wait_seqno { -+ __u64 seqno; -+ __u64 timeout_ns; -+}; -+ -+/** -+ * struct drm_vc4_wait_bo - ioctl argument for waiting for -+ * completion of the last DRM_VC4_SUBMIT_CL on a BO. -+ * -+ * This is useful for cases where multiple processes might be -+ * rendering to a BO and you want to wait for all rendering to be -+ * completed. -+ */ -+struct drm_vc4_wait_bo { -+ __u32 handle; -+ __u32 pad; -+ __u64 timeout_ns; -+}; -+ -+/** -+ * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. -+ * -+ * There are currently no values for the flags argument, but it may be -+ * used in a future extension. -+ */ -+struct drm_vc4_create_bo { -+ __u32 size; -+ __u32 flags; -+ /** Returned GEM handle for the BO. */ -+ __u32 handle; -+ __u32 pad; -+}; -+ -+/** -+ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. -+ * -+ * This doesn't actually perform an mmap. Instead, it returns the -+ * offset you need to use in an mmap on the DRM device node. This -+ * means that tools like valgrind end up knowing about the mapped -+ * memory. -+ * -+ * There are currently no values for the flags argument, but it may be -+ * used in a future extension. -+ */ -+struct drm_vc4_mmap_bo { -+ /** Handle for the object being mapped. */ -+ __u32 handle; -+ __u32 flags; -+ /** offset into the drm node to use for subsequent mmap call. */ -+ __u64 offset; -+}; -+ -+/** -+ * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 -+ * shader BOs. -+ * -+ * Since allowing a shader to be overwritten while it's also being -+ * executed from would allow privlege escalation, shaders must be -+ * created using this ioctl, and they can't be mmapped later. -+ */ -+struct drm_vc4_create_shader_bo { -+ /* Size of the data argument. */ -+ __u32 size; -+ /* Flags, currently must be 0. */ -+ __u32 flags; -+ -+ /* Pointer to the data. */ -+ __u64 data; -+ -+ /** Returned GEM handle for the BO. */ -+ __u32 handle; -+ /* Pad, must be 0. */ -+ __u32 pad; -+}; -+ -+struct drm_vc4_get_hang_state_bo { -+ __u32 handle; -+ __u32 paddr; -+ __u32 size; -+ __u32 pad; -+}; -+ -+/** -+ * struct drm_vc4_hang_state - ioctl argument for collecting state -+ * from a GPU hang for analysis. -+*/ -+struct drm_vc4_get_hang_state { -+ /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ -+ __u64 bo; -+ /** -+ * On input, the size of the bo array. Output is the number -+ * of bos to be returned. -+ */ -+ __u32 bo_count; -+ -+ __u32 start_bin, start_render; -+ -+ __u32 ct0ca, ct0ea; -+ __u32 ct1ca, ct1ea; -+ __u32 ct0cs, ct1cs; -+ __u32 ct0ra0, ct1ra0; -+ -+ __u32 bpca, bpcs; -+ __u32 bpoa, bpos; -+ -+ __u32 vpmbase; -+ -+ __u32 dbge; -+ __u32 fdbgo; -+ __u32 fdbgb; -+ __u32 fdbgr; -+ __u32 fdbgs; -+ __u32 errstat; -+ -+ /* Pad that we may save more registers into in the future. */ -+ __u32 pad[16]; -+}; -+ -+#endif /* _VC4_DRM_H_ */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0020-util-Add-support-for-vc4.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0020-util-Add-support-for-vc4.patch deleted file mode 100644 index 4f5473e2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0020-util-Add-support-for-vc4.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 0ad32e7ff48e106d654acca79445389651ed6909 Mon Sep 17 00:00:00 2001 -From: Eric Anholt <eric@anholt.net> -Date: Fri, 22 Jan 2016 16:37:25 -0800 -Subject: [PATCH 020/117] util: Add support for vc4. - -This lets allows using modetest for overlay plane testing. - -Signed-off-by: Eric Anholt <eric@anholt.net> ---- - tests/util/kms.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/tests/util/kms.c b/tests/util/kms.c -index dcd5a8e..ce8aaab 100644 ---- a/tests/util/kms.c -+++ b/tests/util/kms.c -@@ -140,6 +140,7 @@ static const char * const modules[] = { - "rockchip", - "atmel-hlcdc", - "fsl-dcu-drm", -+ "vc4", - }; - - int util_open(const char *device, const char *module) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch deleted file mode 100644 index 3b6181fe..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch +++ /dev/null @@ -1,870 +0,0 @@ -From 3c717f61f885240980bfc4273dbd1fc837edc391 Mon Sep 17 00:00:00 2001 -From: Eric Anholt <eric@anholt.net> -Date: Mon, 25 Jan 2016 10:16:56 -0800 -Subject: [PATCH 021/117] vc4: Add headers and .pc files for VC4 userspace - development. - -The headers were originally written in Mesa, imported to the kernel, -and improved upon in vc4-gpu-tools. These come from the v-g-t copies -and will replace the Mesa and v-g-t copies, and hopefully be used from -new tests in igt, as well. - -v2: Fix linking against libdrm_intel instead of libdrm. -v3: Drop Libs and Cflags since they'll be inherited from libdrm. -v4: Switch to Requires.private. I was wrong about standard practice, - apparently only Intel was doing plain Requires (sorry to all - involved). - -Signed-off-by: Eric Anholt <eric@anholt.net> ---- - Makefile.am | 6 + - configure.ac | 19 +++ - vc4/Makefile.am | 34 +++++ - vc4/Makefile.sources | 3 + - vc4/libdrm_vc4.pc.in | 9 ++ - vc4/vc4_packet.h | 397 ++++++++++++++++++++++++++++++++++++++++++++++++++ - vc4/vc4_qpu_defines.h | 274 ++++++++++++++++++++++++++++++++++ - 7 files changed, 742 insertions(+) - create mode 100644 vc4/Makefile.am - create mode 100644 vc4/Makefile.sources - create mode 100644 vc4/libdrm_vc4.pc.in - create mode 100644 vc4/vc4_packet.h - create mode 100644 vc4/vc4_qpu_defines.h - -diff --git a/Makefile.am b/Makefile.am -index ca41508..feecba7 100644 ---- a/Makefile.am -+++ b/Makefile.am -@@ -29,6 +29,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \ - --enable-radeon \ - --enable-amdgpu \ - --enable-nouveau \ -+ --enable-vc4 \ - --enable-vmwgfx \ - --enable-omap-experimental-api \ - --enable-exynos-experimental-api \ -@@ -79,6 +80,10 @@ if HAVE_TEGRA - TEGRA_SUBDIR = tegra - endif - -+if HAVE_VC4 -+VC4_SUBDIR = vc4 -+endif -+ - if BUILD_MANPAGES - if HAVE_MANPAGES_STYLESHEET - MAN_SUBDIR = man -@@ -96,6 +101,7 @@ SUBDIRS = \ - $(EXYNOS_SUBDIR) \ - $(FREEDRENO_SUBDIR) \ - $(TEGRA_SUBDIR) \ -+ $(VC4_SUBDIR) \ - tests \ - $(MAN_SUBDIR) - -diff --git a/configure.ac b/configure.ac -index 4635d18..4eeebfb 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -126,6 +126,11 @@ AC_ARG_ENABLE(tegra-experimental-api, - [Enable support for Tegra's experimental API (default: disabled)]), - [TEGRA=$enableval], [TEGRA=no]) - -+AC_ARG_ENABLE(vc4, -+ AS_HELP_STRING([--disable-vc4], -+ [Enable support for vc4's API (default: auto, enabled on arm)]), -+ [VC4=$enableval], [VC4=auto]) -+ - AC_ARG_ENABLE(install-test-programs, - AS_HELP_STRING([--enable-install-test-programs], - [Install test programs (default: no)]), -@@ -290,6 +295,12 @@ else - *) FREEDRENO=no ;; - esac - fi -+ if test "x$VC4" = xauto; then -+ case $host_cpu in -+ arm*|aarch64) VC4=yes ;; -+ *) VC4=no ;; -+ esac -+ fi - fi - - if test "x$INTEL" != "xno"; then -@@ -396,6 +407,11 @@ if test "x$TEGRA" = xyes; then - AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support]) - fi - -+AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) -+if test "x$VC4" = xyes; then -+ AC_DEFINE(HAVE_VC4, 1, [Have VC4 support]) -+fi -+ - AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) - if test "x$INSTALL_TESTS" = xyes; then - AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs]) -@@ -505,6 +521,8 @@ AC_CONFIG_FILES([ - freedreno/libdrm_freedreno.pc - tegra/Makefile - tegra/libdrm_tegra.pc -+ vc4/Makefile -+ vc4/libdrm_vc4.pc - tests/Makefile - tests/modeprint/Makefile - tests/modetest/Makefile -@@ -535,4 +553,5 @@ echo " OMAP API $OMAP" - echo " EXYNOS API $EXYNOS" - echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)" - echo " Tegra API $TEGRA" -+echo " VC4 API $VC4" - echo "" -diff --git a/vc4/Makefile.am b/vc4/Makefile.am -new file mode 100644 -index 0000000..7e486b4 ---- /dev/null -+++ b/vc4/Makefile.am -@@ -0,0 +1,34 @@ -+# Copyright © 2016 Broadcom -+# -+# Permission is hereby granted, free of charge, to any person obtaining a -+# copy of this software and associated documentation files (the "Software"), -+# to deal in the Software without restriction, including without limitation -+# the rights to use, copy, modify, merge, publish, distribute, sublicense, -+# and/or sell copies of the Software, and to permit persons to whom the -+# Software is furnished to do so, subject to the following conditions: -+# -+# The above copyright notice and this permission notice (including the next -+# paragraph) shall be included in all copies or substantial portions of the -+# Software. -+# -+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+# IN THE SOFTWARE. -+ -+include Makefile.sources -+ -+AM_CFLAGS = \ -+ $(WARN_CFLAGS) \ -+ -I$(top_srcdir) \ -+ $(PTHREADSTUBS_CFLAGS) \ -+ $(VALGRIND_CFLAGS) \ -+ -I$(top_srcdir)/include/drm -+ -+libdrm_vc4includedir = ${includedir}/libdrm -+libdrm_vc4include_HEADERS = $(LIBDRM_VC4_H_FILES) -+ -+pkgconfig_DATA = libdrm_vc4.pc -diff --git a/vc4/Makefile.sources b/vc4/Makefile.sources -new file mode 100644 -index 0000000..8bf97ff ---- /dev/null -+++ b/vc4/Makefile.sources -@@ -0,0 +1,3 @@ -+LIBDRM_VC4_H_FILES := \ -+ vc4_packet.h \ -+ vc4_qpu_defines.h -diff --git a/vc4/libdrm_vc4.pc.in b/vc4/libdrm_vc4.pc.in -new file mode 100644 -index 0000000..a92678e ---- /dev/null -+++ b/vc4/libdrm_vc4.pc.in -@@ -0,0 +1,9 @@ -+prefix=@prefix@ -+exec_prefix=@exec_prefix@ -+libdir=@libdir@ -+includedir=@includedir@ -+ -+Name: libdrm_vc4 -+Description: Userspace interface to vc4 kernel DRM services -+Version: @PACKAGE_VERSION@ -+Requires.private: libdrm -diff --git a/vc4/vc4_packet.h b/vc4/vc4_packet.h -new file mode 100644 -index 0000000..e18e0bd ---- /dev/null -+++ b/vc4/vc4_packet.h -@@ -0,0 +1,397 @@ -+/* -+ * Copyright © 2014 Broadcom -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ */ -+ -+#ifndef VC4_PACKET_H -+#define VC4_PACKET_H -+ -+enum vc4_packet { -+ VC4_PACKET_HALT = 0, -+ VC4_PACKET_NOP = 1, -+ -+ VC4_PACKET_FLUSH = 4, -+ VC4_PACKET_FLUSH_ALL = 5, -+ VC4_PACKET_START_TILE_BINNING = 6, -+ VC4_PACKET_INCREMENT_SEMAPHORE = 7, -+ VC4_PACKET_WAIT_ON_SEMAPHORE = 8, -+ -+ VC4_PACKET_BRANCH = 16, -+ VC4_PACKET_BRANCH_TO_SUB_LIST = 17, -+ VC4_PACKET_RETURN_FROM_SUB_LIST = 18, -+ -+ VC4_PACKET_STORE_MS_TILE_BUFFER = 24, -+ VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, -+ VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, -+ VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, -+ VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, -+ VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, -+ -+ VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, -+ VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, -+ -+ VC4_PACKET_COMPRESSED_PRIMITIVE = 48, -+ VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, -+ -+ VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, -+ -+ VC4_PACKET_GL_SHADER_STATE = 64, -+ VC4_PACKET_NV_SHADER_STATE = 65, -+ VC4_PACKET_VG_SHADER_STATE = 66, -+ -+ VC4_PACKET_CONFIGURATION_BITS = 96, -+ VC4_PACKET_FLAT_SHADE_FLAGS = 97, -+ VC4_PACKET_POINT_SIZE = 98, -+ VC4_PACKET_LINE_WIDTH = 99, -+ VC4_PACKET_RHT_X_BOUNDARY = 100, -+ VC4_PACKET_DEPTH_OFFSET = 101, -+ VC4_PACKET_CLIP_WINDOW = 102, -+ VC4_PACKET_VIEWPORT_OFFSET = 103, -+ VC4_PACKET_Z_CLIPPING = 104, -+ VC4_PACKET_CLIPPER_XY_SCALING = 105, -+ VC4_PACKET_CLIPPER_Z_SCALING = 106, -+ -+ VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, -+ VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, -+ VC4_PACKET_CLEAR_COLORS = 114, -+ VC4_PACKET_TILE_COORDINATES = 115, -+ -+ /* Not an actual hardware packet -- this is what we use to put -+ * references to GEM bos in the command stream, since we need the u32 -+ * int the actual address packet in order to store the offset from the -+ * start of the BO. -+ */ -+ VC4_PACKET_GEM_HANDLES = 254, -+} __attribute__ ((__packed__)); -+ -+#define VC4_PACKET_HALT_SIZE 1 -+#define VC4_PACKET_NOP_SIZE 1 -+#define VC4_PACKET_FLUSH_SIZE 1 -+#define VC4_PACKET_FLUSH_ALL_SIZE 1 -+#define VC4_PACKET_START_TILE_BINNING_SIZE 1 -+#define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE 1 -+#define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE 1 -+#define VC4_PACKET_BRANCH_SIZE 5 -+#define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 5 -+#define VC4_PACKET_RETURN_FROM_SUB_LIST_SIZE 1 -+#define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE 1 -+#define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE 1 -+#define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 5 -+#define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 5 -+#define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE 7 -+#define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE 7 -+#define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE 14 -+#define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE 10 -+#define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE 1 -+#define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE 1 -+#define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE 2 -+#define VC4_PACKET_GL_SHADER_STATE_SIZE 5 -+#define VC4_PACKET_NV_SHADER_STATE_SIZE 5 -+#define VC4_PACKET_VG_SHADER_STATE_SIZE 5 -+#define VC4_PACKET_CONFIGURATION_BITS_SIZE 4 -+#define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5 -+#define VC4_PACKET_POINT_SIZE_SIZE 5 -+#define VC4_PACKET_LINE_WIDTH_SIZE 5 -+#define VC4_PACKET_RHT_X_BOUNDARY_SIZE 3 -+#define VC4_PACKET_DEPTH_OFFSET_SIZE 5 -+#define VC4_PACKET_CLIP_WINDOW_SIZE 9 -+#define VC4_PACKET_VIEWPORT_OFFSET_SIZE 5 -+#define VC4_PACKET_Z_CLIPPING_SIZE 9 -+#define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9 -+#define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9 -+#define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE 16 -+#define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE 11 -+#define VC4_PACKET_CLEAR_COLORS_SIZE 14 -+#define VC4_PACKET_TILE_COORDINATES_SIZE 3 -+#define VC4_PACKET_GEM_HANDLES_SIZE 9 -+ -+#define VC4_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) -+/* Using the GNU statement expression extension */ -+#define VC4_SET_FIELD(value, field) \ -+ ({ \ -+ uint32_t fieldval = (value) << field ## _SHIFT; \ -+ assert((fieldval & ~ field ## _MASK) == 0); \ -+ fieldval & field ## _MASK; \ -+ }) -+ -+#define VC4_GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) -+ -+/** @{ -+ * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. -+*/ -+#define VC4_TILING_FORMAT_LINEAR 0 -+#define VC4_TILING_FORMAT_T 1 -+#define VC4_TILING_FORMAT_LT 2 -+/** @} */ -+ -+/** @{ -+ * -+ * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and -+ * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. -+ */ -+#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3) -+#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2) -+#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1) -+#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0) -+ -+/** @{ -+ * -+ * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) -+ */ -+ -+#define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3) -+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2) -+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1) -+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0) -+ -+/** @} */ -+ -+/** @{ -+ * -+ * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL -+ */ -+#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15) -+#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14) -+#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13) -+#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12) -+ -+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) -+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 -+#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0 -+#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1 -+#define VC4_LOADSTORE_TILE_BUFFER_BGR565 2 -+/** @} */ -+ -+/** @{ -+ * -+ * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and -+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL -+ */ -+#define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6) -+#define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6 -+#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6) -+#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6) -+#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6) -+ -+/** The values of the field are VC4_TILING_FORMAT_* */ -+#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4) -+#define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4 -+ -+#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0) -+#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0 -+#define VC4_LOADSTORE_TILE_BUFFER_NONE 0 -+#define VC4_LOADSTORE_TILE_BUFFER_COLOR 1 -+#define VC4_LOADSTORE_TILE_BUFFER_ZS 2 -+#define VC4_LOADSTORE_TILE_BUFFER_Z 3 -+#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4 -+#define VC4_LOADSTORE_TILE_BUFFER_FULL 5 -+/** @} */ -+ -+#define VC4_INDEX_BUFFER_U8 (0 << 4) -+#define VC4_INDEX_BUFFER_U16 (1 << 4) -+ -+/* This flag is only present in NV shader state. */ -+#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3) -+#define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2) -+#define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1) -+#define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0) -+ -+/** @{ byte 2 of config bits. */ -+#define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1) -+#define VC4_CONFIG_BITS_EARLY_Z (1 << 0) -+/** @} */ -+ -+/** @{ byte 1 of config bits. */ -+#define VC4_CONFIG_BITS_Z_UPDATE (1 << 7) -+/** same values in this 3-bit field as PIPE_FUNC_* */ -+#define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 -+#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3) -+ -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) -+#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) -+ -+#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0) -+/** @} */ -+ -+/** @{ byte 0 of config bits. */ -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6) -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) -+#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_MASK (3 << 6) -+ -+#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4) -+#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3) -+#define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2) -+#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1) -+#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0) -+/** @} */ -+ -+/** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ -+#define VC4_BIN_CONFIG_DB_NON_MS (1 << 7) -+ -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 0 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64 1 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128 2 -+#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256 3 -+ -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3) -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32 0 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64 1 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 -+#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 -+ -+#define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2) -+#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1) -+#define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0) -+/** @} */ -+ -+/** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ -+#define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12) -+#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11) -+#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10) -+#define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9) -+#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8) -+ -+/** The values of the field are VC4_TILING_FORMAT_* */ -+#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) -+#define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6 -+ -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4) -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4) -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4) -+#define VC4_RENDER_CONFIG_DECIMATE_MODE_MASK (3 << 4) -+ -+#define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2) -+#define VC4_RENDER_CONFIG_FORMAT_SHIFT 2 -+#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0 -+#define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 -+#define VC4_RENDER_CONFIG_FORMAT_BGR565 2 -+ -+#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1) -+#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0) -+ -+#define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) -+#define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS (0 << 0) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES (1 << 0) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES (2 << 0) -+#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) -+ -+enum vc4_texture_data_type { -+ VC4_TEXTURE_TYPE_RGBA8888 = 0, -+ VC4_TEXTURE_TYPE_RGBX8888 = 1, -+ VC4_TEXTURE_TYPE_RGBA4444 = 2, -+ VC4_TEXTURE_TYPE_RGBA5551 = 3, -+ VC4_TEXTURE_TYPE_RGB565 = 4, -+ VC4_TEXTURE_TYPE_LUMINANCE = 5, -+ VC4_TEXTURE_TYPE_ALPHA = 6, -+ VC4_TEXTURE_TYPE_LUMALPHA = 7, -+ VC4_TEXTURE_TYPE_ETC1 = 8, -+ VC4_TEXTURE_TYPE_S16F = 9, -+ VC4_TEXTURE_TYPE_S8 = 10, -+ VC4_TEXTURE_TYPE_S16 = 11, -+ VC4_TEXTURE_TYPE_BW1 = 12, -+ VC4_TEXTURE_TYPE_A4 = 13, -+ VC4_TEXTURE_TYPE_A1 = 14, -+ VC4_TEXTURE_TYPE_RGBA64 = 15, -+ VC4_TEXTURE_TYPE_RGBA32R = 16, -+ VC4_TEXTURE_TYPE_YUV422R = 17, -+}; -+ -+#define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) -+#define VC4_TEX_P0_OFFSET_SHIFT 12 -+#define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10) -+#define VC4_TEX_P0_CSWIZ_SHIFT 10 -+#define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9) -+#define VC4_TEX_P0_CMMODE_SHIFT 9 -+#define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8) -+#define VC4_TEX_P0_FLIPY_SHIFT 8 -+#define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4) -+#define VC4_TEX_P0_TYPE_SHIFT 4 -+#define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0) -+#define VC4_TEX_P0_MIPLVLS_SHIFT 0 -+ -+#define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31) -+#define VC4_TEX_P1_TYPE4_SHIFT 31 -+#define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20) -+#define VC4_TEX_P1_HEIGHT_SHIFT 20 -+#define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19) -+#define VC4_TEX_P1_ETCFLIP_SHIFT 19 -+#define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8) -+#define VC4_TEX_P1_WIDTH_SHIFT 8 -+ -+#define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7) -+#define VC4_TEX_P1_MAGFILT_SHIFT 7 -+# define VC4_TEX_P1_MAGFILT_LINEAR 0 -+# define VC4_TEX_P1_MAGFILT_NEAREST 1 -+ -+#define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4) -+#define VC4_TEX_P1_MINFILT_SHIFT 4 -+# define VC4_TEX_P1_MINFILT_LINEAR 0 -+# define VC4_TEX_P1_MINFILT_NEAREST 1 -+# define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR 2 -+# define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN 3 -+# define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR 4 -+# define VC4_TEX_P1_MINFILT_LIN_MIP_LIN 5 -+ -+#define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2) -+#define VC4_TEX_P1_WRAP_T_SHIFT 2 -+#define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0) -+#define VC4_TEX_P1_WRAP_S_SHIFT 0 -+# define VC4_TEX_P1_WRAP_REPEAT 0 -+# define VC4_TEX_P1_WRAP_CLAMP 1 -+# define VC4_TEX_P1_WRAP_MIRROR 2 -+# define VC4_TEX_P1_WRAP_BORDER 3 -+ -+#define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30) -+#define VC4_TEX_P2_PTYPE_SHIFT 30 -+# define VC4_TEX_P2_PTYPE_IGNORED 0 -+# define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE 1 -+# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS 2 -+# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS 3 -+ -+/* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */ -+#define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12) -+#define VC4_TEX_P2_CMST_SHIFT 12 -+#define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0) -+#define VC4_TEX_P2_BSLOD_SHIFT 0 -+ -+/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */ -+#define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12) -+#define VC4_TEX_P2_CHEIGHT_SHIFT 12 -+#define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0) -+#define VC4_TEX_P2_CWIDTH_SHIFT 0 -+ -+/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */ -+#define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12) -+#define VC4_TEX_P2_CYOFF_SHIFT 12 -+#define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0) -+#define VC4_TEX_P2_CXOFF_SHIFT 0 -+ -+#endif /* VC4_PACKET_H */ -diff --git a/vc4/vc4_qpu_defines.h b/vc4/vc4_qpu_defines.h -new file mode 100644 -index 0000000..26fcf50 ---- /dev/null -+++ b/vc4/vc4_qpu_defines.h -@@ -0,0 +1,274 @@ -+/* -+ * Copyright © 2014 Broadcom -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -+ * IN THE SOFTWARE. -+ */ -+ -+#ifndef VC4_QPU_DEFINES_H -+#define VC4_QPU_DEFINES_H -+ -+enum qpu_op_add { -+ QPU_A_NOP, -+ QPU_A_FADD, -+ QPU_A_FSUB, -+ QPU_A_FMIN, -+ QPU_A_FMAX, -+ QPU_A_FMINABS, -+ QPU_A_FMAXABS, -+ QPU_A_FTOI, -+ QPU_A_ITOF, -+ QPU_A_ADD = 12, -+ QPU_A_SUB, -+ QPU_A_SHR, -+ QPU_A_ASR, -+ QPU_A_ROR, -+ QPU_A_SHL, -+ QPU_A_MIN, -+ QPU_A_MAX, -+ QPU_A_AND, -+ QPU_A_OR, -+ QPU_A_XOR, -+ QPU_A_NOT, -+ QPU_A_CLZ, -+ QPU_A_V8ADDS = 30, -+ QPU_A_V8SUBS = 31, -+}; -+ -+enum qpu_op_mul { -+ QPU_M_NOP, -+ QPU_M_FMUL, -+ QPU_M_MUL24, -+ QPU_M_V8MULD, -+ QPU_M_V8MIN, -+ QPU_M_V8MAX, -+ QPU_M_V8ADDS, -+ QPU_M_V8SUBS, -+}; -+ -+enum qpu_raddr { -+ QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ -+ /* 0-31 are the plain regfile a or b fields */ -+ QPU_R_UNIF = 32, -+ QPU_R_VARY = 35, -+ QPU_R_ELEM_QPU = 38, -+ QPU_R_NOP, -+ QPU_R_XY_PIXEL_COORD = 41, -+ QPU_R_MS_REV_FLAGS = 42, -+ QPU_R_VPM = 48, -+ QPU_R_VPM_LD_BUSY, -+ QPU_R_VPM_LD_WAIT, -+ QPU_R_MUTEX_ACQUIRE, -+}; -+ -+enum qpu_waddr { -+ /* 0-31 are the plain regfile a or b fields */ -+ QPU_W_ACC0 = 32, /* aka r0 */ -+ QPU_W_ACC1, -+ QPU_W_ACC2, -+ QPU_W_ACC3, -+ QPU_W_TMU_NOSWAP, -+ QPU_W_ACC5, -+ QPU_W_HOST_INT, -+ QPU_W_NOP, -+ QPU_W_UNIFORMS_ADDRESS, -+ QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ -+ QPU_W_MS_FLAGS = 42, -+ QPU_W_REV_FLAG = 42, -+ QPU_W_TLB_STENCIL_SETUP = 43, -+ QPU_W_TLB_Z, -+ QPU_W_TLB_COLOR_MS, -+ QPU_W_TLB_COLOR_ALL, -+ QPU_W_TLB_ALPHA_MASK, -+ QPU_W_VPM, -+ QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ -+ QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ -+ QPU_W_MUTEX_RELEASE, -+ QPU_W_SFU_RECIP, -+ QPU_W_SFU_RECIPSQRT, -+ QPU_W_SFU_EXP, -+ QPU_W_SFU_LOG, -+ QPU_W_TMU0_S, -+ QPU_W_TMU0_T, -+ QPU_W_TMU0_R, -+ QPU_W_TMU0_B, -+ QPU_W_TMU1_S, -+ QPU_W_TMU1_T, -+ QPU_W_TMU1_R, -+ QPU_W_TMU1_B, -+}; -+ -+enum qpu_sig_bits { -+ QPU_SIG_SW_BREAKPOINT, -+ QPU_SIG_NONE, -+ QPU_SIG_THREAD_SWITCH, -+ QPU_SIG_PROG_END, -+ QPU_SIG_WAIT_FOR_SCOREBOARD, -+ QPU_SIG_SCOREBOARD_UNLOCK, -+ QPU_SIG_LAST_THREAD_SWITCH, -+ QPU_SIG_COVERAGE_LOAD, -+ QPU_SIG_COLOR_LOAD, -+ QPU_SIG_COLOR_LOAD_END, -+ QPU_SIG_LOAD_TMU0, -+ QPU_SIG_LOAD_TMU1, -+ QPU_SIG_ALPHA_MASK_LOAD, -+ QPU_SIG_SMALL_IMM, -+ QPU_SIG_LOAD_IMM, -+ QPU_SIG_BRANCH -+}; -+ -+enum qpu_mux { -+ /* hardware mux values */ -+ QPU_MUX_R0, -+ QPU_MUX_R1, -+ QPU_MUX_R2, -+ QPU_MUX_R3, -+ QPU_MUX_R4, -+ QPU_MUX_R5, -+ QPU_MUX_A, -+ QPU_MUX_B, -+ -+ /** -+ * Non-hardware mux value, stores a small immediate field to be -+ * programmed into raddr_b in the qpu_reg.index. -+ */ -+ QPU_MUX_SMALL_IMM, -+}; -+ -+enum qpu_cond { -+ QPU_COND_NEVER, -+ QPU_COND_ALWAYS, -+ QPU_COND_ZS, -+ QPU_COND_ZC, -+ QPU_COND_NS, -+ QPU_COND_NC, -+ QPU_COND_CS, -+ QPU_COND_CC, -+}; -+ -+enum qpu_pack_mul { -+ QPU_PACK_MUL_NOP, -+ QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */ -+ QPU_PACK_MUL_8A, -+ QPU_PACK_MUL_8B, -+ QPU_PACK_MUL_8C, -+ QPU_PACK_MUL_8D, -+}; -+ -+enum qpu_pack_a { -+ QPU_PACK_A_NOP, -+ /* convert to 16 bit float if float input, or to int16. */ -+ QPU_PACK_A_16A, -+ QPU_PACK_A_16B, -+ /* replicated to each 8 bits of the 32-bit dst. */ -+ QPU_PACK_A_8888, -+ /* Convert to 8-bit unsigned int. */ -+ QPU_PACK_A_8A, -+ QPU_PACK_A_8B, -+ QPU_PACK_A_8C, -+ QPU_PACK_A_8D, -+ -+ /* Saturating variants of the previous instructions. */ -+ QPU_PACK_A_32_SAT, /* int-only */ -+ QPU_PACK_A_16A_SAT, /* int or float */ -+ QPU_PACK_A_16B_SAT, -+ QPU_PACK_A_8888_SAT, -+ QPU_PACK_A_8A_SAT, -+ QPU_PACK_A_8B_SAT, -+ QPU_PACK_A_8C_SAT, -+ QPU_PACK_A_8D_SAT, -+}; -+ -+enum qpu_unpack { -+ QPU_UNPACK_NOP, -+ QPU_UNPACK_16A, -+ QPU_UNPACK_16B, -+ QPU_UNPACK_8D_REP, -+ QPU_UNPACK_8A, -+ QPU_UNPACK_8B, -+ QPU_UNPACK_8C, -+ QPU_UNPACK_8D, -+}; -+ -+#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) -+/* Using the GNU statement expression extension */ -+#define QPU_SET_FIELD(value, field) \ -+ ({ \ -+ uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ -+ assert((fieldval & ~ field ## _MASK) == 0); \ -+ fieldval & field ## _MASK; \ -+ }) -+ -+#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) -+ -+#define QPU_UPDATE_FIELD(inst, value, field) \ -+ (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field)) -+ -+#define QPU_SIG_SHIFT 60 -+#define QPU_SIG_MASK QPU_MASK(63, 60) -+ -+#define QPU_UNPACK_SHIFT 57 -+#define QPU_UNPACK_MASK QPU_MASK(59, 57) -+ -+/** -+ * If set, the pack field means PACK_MUL or R4 packing, instead of normal -+ * regfile a packing. -+ */ -+#define QPU_PM ((uint64_t)1 << 56) -+ -+#define QPU_PACK_SHIFT 52 -+#define QPU_PACK_MASK QPU_MASK(55, 52) -+ -+#define QPU_COND_ADD_SHIFT 49 -+#define QPU_COND_ADD_MASK QPU_MASK(51, 49) -+#define QPU_COND_MUL_SHIFT 46 -+#define QPU_COND_MUL_MASK QPU_MASK(48, 46) -+ -+#define QPU_SF ((uint64_t)1 << 45) -+ -+#define QPU_WADDR_ADD_SHIFT 38 -+#define QPU_WADDR_ADD_MASK QPU_MASK(43, 38) -+#define QPU_WADDR_MUL_SHIFT 32 -+#define QPU_WADDR_MUL_MASK QPU_MASK(37, 32) -+ -+#define QPU_OP_MUL_SHIFT 29 -+#define QPU_OP_MUL_MASK QPU_MASK(31, 29) -+ -+#define QPU_RADDR_A_SHIFT 18 -+#define QPU_RADDR_A_MASK QPU_MASK(23, 18) -+#define QPU_RADDR_B_SHIFT 12 -+#define QPU_RADDR_B_MASK QPU_MASK(17, 12) -+#define QPU_SMALL_IMM_SHIFT 12 -+#define QPU_SMALL_IMM_MASK QPU_MASK(17, 12) -+ -+#define QPU_ADD_A_SHIFT 9 -+#define QPU_ADD_A_MASK QPU_MASK(11, 9) -+#define QPU_ADD_B_SHIFT 6 -+#define QPU_ADD_B_MASK QPU_MASK(8, 6) -+#define QPU_MUL_A_SHIFT 3 -+#define QPU_MUL_A_MASK QPU_MASK(5, 3) -+#define QPU_MUL_B_SHIFT 0 -+#define QPU_MUL_B_MASK QPU_MASK(2, 0) -+ -+#define QPU_WS ((uint64_t)1 << 44) -+ -+#define QPU_OP_ADD_SHIFT 24 -+#define QPU_OP_ADD_MASK QPU_MASK(28, 24) -+ -+#endif /* VC4_QPU_DEFINES_H */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch deleted file mode 100644 index 7a7efb6e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 87b3bf643de35223d9d038febc7d5e232325e7b2 Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Thu, 28 Jan 2016 11:26:24 +0000 -Subject: [PATCH 022/117] amdgpu: add libdrm as private requirement/dependency -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Otherwise libdrm.so won't end up in the --libs, when one static links -libdrm_amdgpu. - -Cc: Christian König <christian.koenig@amd.com> -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - amdgpu/libdrm_amdgpu.pc.in | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/amdgpu/libdrm_amdgpu.pc.in b/amdgpu/libdrm_amdgpu.pc.in -index 417865e..f1c552a 100644 ---- a/amdgpu/libdrm_amdgpu.pc.in -+++ b/amdgpu/libdrm_amdgpu.pc.in -@@ -8,3 +8,4 @@ Description: Userspace interface to kernel DRM services for amdgpu - Version: @PACKAGE_VERSION@ - Libs: -L${libdir} -ldrm_amdgpu - Cflags: -I${includedir} -I${includedir}/libdrm -+Requires.private: libdrm --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0023-radeon-add-libdrm-to-Requires.private.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0023-radeon-add-libdrm-to-Requires.private.patch deleted file mode 100644 index e8f750aa..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0023-radeon-add-libdrm-to-Requires.private.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 31badf031c90aba4609e1464e252311f96733a5e Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Thu, 28 Jan 2016 11:33:34 +0000 -Subject: [PATCH 023/117] radeon: add libdrm to Requires.private -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Equivalent to the amdgpu commit before. Additionally, when libdrm is -installed to a 'non-default' location, users of libdrm_radeon will fail -to build, as radeon_cs.h (and maybe others) won't have their -dependencies (drm.h radeon_drm.h) fulfilled. - -Cc: Christian König <christian.koenig@amd.com> -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - radeon/libdrm_radeon.pc.in | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/radeon/libdrm_radeon.pc.in b/radeon/libdrm_radeon.pc.in -index 68ef0ab..432993a 100644 ---- a/radeon/libdrm_radeon.pc.in -+++ b/radeon/libdrm_radeon.pc.in -@@ -8,3 +8,4 @@ Description: Userspace interface to kernel DRM services for radeon - Version: @PACKAGE_VERSION@ - Libs: -L${libdir} -ldrm_radeon - Cflags: -I${includedir} -I${includedir}/libdrm -+Requires.private: libdrm --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0024-libkms-add-libdrm-to-Requires.private.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0024-libkms-add-libdrm-to-Requires.private.patch deleted file mode 100644 index 9f3ee23b..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0024-libkms-add-libdrm-to-Requires.private.patch +++ /dev/null @@ -1,29 +0,0 @@ -From ca5017b69c43ef3bfada0abb77a82de1de345075 Mon Sep 17 00:00:00 2001 -From: Emil Velikov <emil.l.velikov@gmail.com> -Date: Thu, 28 Jan 2016 11:39:03 +0000 -Subject: [PATCH 024/117] libkms: add libdrm to Requires.private -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Analogous to last two changes (amdgpu and radeon). - -Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> -Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - libkms/libkms.pc.in | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/libkms/libkms.pc.in b/libkms/libkms.pc.in -index 511535a..1421b3e 100644 ---- a/libkms/libkms.pc.in -+++ b/libkms/libkms.pc.in -@@ -8,3 +8,4 @@ Description: Library that abstract aways the different mm interface for kernel d - Version: 1.0.0 - Libs: -L${libdir} -lkms - Cflags: -I${includedir}/libkms -+Requires.private: libdrm --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0025-android-enable-building-static-version-of-libdrm.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0025-android-enable-building-static-version-of-libdrm.patch deleted file mode 100644 index 98c11e7b..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0025-android-enable-building-static-version-of-libdrm.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 682eaa05e6bc6b191b826e1c9db4446caea43c49 Mon Sep 17 00:00:00 2001 -From: Sumit Semwal <sumit.semwal@linaro.org> -Date: Fri, 29 Jan 2016 10:00:47 -0600 -Subject: [PATCH 025/117] android: enable building static version of libdrm - -Android needs libdrm built statically for recovery; -enable that as well. - -Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> -Signed-off-by: Rob Herring <robh@kernel.org> -Cc: Chih-Wei Huang <cwhuang@linux.org.tw> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - Android.mk | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/Android.mk b/Android.mk -index 90cdcb3..1d8cd65 100644 ---- a/Android.mk -+++ b/Android.mk -@@ -27,6 +27,8 @@ include $(CLEAR_VARS) - # Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES - include $(LOCAL_PATH)/Makefile.sources - -+#static library for the device (recovery) -+include $(CLEAR_VARS) - LOCAL_MODULE := libdrm - LOCAL_MODULE_TAGS := optional - -@@ -41,7 +43,24 @@ LOCAL_C_INCLUDES := \ - LOCAL_CFLAGS := \ - -DHAVE_VISIBILITY=1 \ - -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 -+include $(BUILD_STATIC_LIBRARY) -+ -+# Shared library for the device -+include $(CLEAR_VARS) -+LOCAL_MODULE := libdrm -+LOCAL_MODULE_TAGS := optional - -+LOCAL_SRC_FILES := $(LIBDRM_FILES) -+LOCAL_EXPORT_C_INCLUDE_DIRS := \ -+ $(LOCAL_PATH) \ -+ $(LOCAL_PATH)/include/drm -+ -+LOCAL_C_INCLUDES := \ -+ $(LOCAL_PATH)/include/drm -+ -+LOCAL_CFLAGS := \ -+ -DHAVE_VISIBILITY=1 \ -+ -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 - include $(BUILD_SHARED_LIBRARY) - - include $(call all-makefiles-under,$(LOCAL_PATH)) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch deleted file mode 100644 index 67dd46bc..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 30da7e6ac1682b5de547686369d1b8199c6929c3 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 19 Aug 2015 17:39:37 +0800 -Subject: [PATCH 026/117] amdgpu: add the interface of waiting multiple fences -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> ---- - amdgpu/amdgpu.h | 22 +++++++++++++++ - amdgpu/amdgpu_cs.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 27 ++++++++++++++++++ - 3 files changed, 121 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 0851306..8822a0c 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -907,6 +907,28 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - uint64_t flags, - uint32_t *expired); - -+/** -+ * Wait for multiple fences -+ * -+ * \param fences - \c [in] The fence array to wait -+ * \param fence_count - \c [in] The fence count -+ * \param wait_all - \c [in] If true, wait all fences to be signaled, -+ * otherwise, wait at least one fence -+ * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds -+ * \param status - \c [out] '1' for signaled, '0' for timeout -+ * -+ * \return 0 on success -+ * <0 - Negative POSIX Error code -+ * -+ * \note Currently it supports only one amdgpu_device. All fences come from -+ * the same amdgpu_device with the same fd. -+*/ -+int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, -+ uint32_t fence_count, -+ bool wait_all, -+ uint64_t timeout_ns, -+ uint32_t *status); -+ - /* - * Query / Info API - * -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index b4f41b0..896352b 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -435,6 +435,78 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - return r; - } - -+static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, -+ uint32_t fence_count, -+ bool wait_all, -+ uint64_t timeout_ns, -+ uint32_t *status) -+{ -+ struct drm_amdgpu_fence *drm_fences; -+ amdgpu_device_handle dev = fences[0].context->dev; -+ union drm_amdgpu_wait_fences args; -+ int r; -+ uint32_t i; -+ -+ drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count); -+ for (i = 0; i < fence_count; i++) { -+ drm_fences[i].ctx_id = fences[i].context->id; -+ drm_fences[i].ip_type = fences[i].ip_type; -+ drm_fences[i].ip_instance = fences[i].ip_instance; -+ drm_fences[i].ring = fences[i].ring; -+ drm_fences[i].seq_no = fences[i].fence; -+ } -+ -+ memset(&args, 0, sizeof(args)); -+ args.in.fences = (uint64_t)(uintptr_t)drm_fences; -+ args.in.fence_count = fence_count; -+ args.in.wait_all = wait_all; -+ args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns); -+ -+ r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args); -+ if (r) -+ return -errno; -+ -+ *status = args.out.status; -+ return 0; -+} -+ -+int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, -+ uint32_t fence_count, -+ bool wait_all, -+ uint64_t timeout_ns, -+ uint32_t *status) -+{ -+ uint32_t ioctl_status = 0; -+ uint32_t i; -+ int r; -+ -+ /* Sanity check */ -+ if (NULL == fences) -+ return -EINVAL; -+ if (NULL == status) -+ return -EINVAL; -+ if (fence_count <= 0) -+ return -EINVAL; -+ for (i = 0; i < fence_count; i++) { -+ if (NULL == fences[i].context) -+ return -EINVAL; -+ if (fences[i].ip_type >= AMDGPU_HW_IP_NUM) -+ return -EINVAL; -+ if (fences[i].ring >= AMDGPU_CS_MAX_RINGS) -+ return -EINVAL; -+ } -+ -+ *status = 0; -+ -+ r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, timeout_ns, -+ &ioctl_status); -+ -+ if (!r) -+ *status = ioctl_status; -+ -+ return r; -+} -+ - int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) - { - struct amdgpu_semaphore *gpu_semaphore; -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index fbdd118..2cbea72 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -46,6 +46,7 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 -+#define DRM_AMDGPU_WAIT_FENCES 0x12 - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -59,6 +60,7 @@ - #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) -+#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -297,6 +299,31 @@ union drm_amdgpu_wait_cs { - struct drm_amdgpu_wait_cs_out out; - }; - -+struct drm_amdgpu_fence { -+ uint32_t ctx_id; -+ uint32_t ip_type; -+ uint32_t ip_instance; -+ uint32_t ring; -+ uint64_t seq_no; -+}; -+ -+struct drm_amdgpu_wait_fences_in { -+ /** This points to uint64_t * which points to fences */ -+ uint64_t fences; -+ uint32_t fence_count; -+ uint32_t wait_all; -+ uint64_t timeout_ns; -+}; -+ -+struct drm_amdgpu_wait_fences_out { -+ uint64_t status; -+}; -+ -+union drm_amdgpu_wait_fences { -+ struct drm_amdgpu_wait_fences_in in; -+ struct drm_amdgpu_wait_fences_out out; -+}; -+ - #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 - #define AMDGPU_GEM_OP_SET_PLACEMENT 1 - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch deleted file mode 100644 index 11eddff2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 41469768b0e55ae414aaf6b61b0d83f348518169 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Fri, 21 Aug 2015 10:14:48 +0800 -Subject: [PATCH 027/117] amdgpu/tests: add multi-fence test in base test - -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> ---- - tests/amdgpu/basic_tests.c | 100 +++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 100 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index fa0ed12..56db935 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -46,6 +46,7 @@ static void amdgpu_memory_alloc(void); - static void amdgpu_command_submission_gfx(void); - static void amdgpu_command_submission_compute(void); - static void amdgpu_command_submission_sdma(void); -+static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); - -@@ -56,6 +57,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, - { "Command submission Test (Compute)", amdgpu_command_submission_compute }, - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, -+ { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, - CU_TEST_INFO_NULL, - }; -@@ -898,6 +900,104 @@ static void amdgpu_command_submission_sdma(void) - amdgpu_command_submission_sdma_copy_linear(); - } - -+static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) -+{ -+ amdgpu_context_handle context_handle; -+ amdgpu_bo_handle ib_result_handle, ib_result_ce_handle; -+ void *ib_result_cpu, *ib_result_ce_cpu; -+ uint64_t ib_result_mc_address, ib_result_ce_mc_address; -+ struct amdgpu_cs_request ibs_request[2] = {0}; -+ struct amdgpu_cs_ib_info ib_info[2]; -+ struct amdgpu_cs_fence fence_status[2] = {0}; -+ uint32_t *ptr; -+ uint32_t expired; -+ amdgpu_bo_list_handle bo_list; -+ amdgpu_va_handle va_handle, va_handle_ce; -+ int r; -+ int i, ib_cs_num = 2; -+ -+ r = amdgpu_cs_ctx_create(device_handle, &context_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_result_handle, &ib_result_cpu, -+ &ib_result_mc_address, &va_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, -+ AMDGPU_GEM_DOMAIN_GTT, 0, -+ &ib_result_ce_handle, &ib_result_ce_cpu, -+ &ib_result_ce_mc_address, &va_handle_ce); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_get_bo_list(device_handle, ib_result_handle, -+ ib_result_ce_handle, &bo_list); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); -+ -+ /* IT_SET_CE_DE_COUNTERS */ -+ ptr = ib_result_ce_cpu; -+ ptr[0] = 0xc0008900; -+ ptr[1] = 0; -+ ptr[2] = 0xc0008400; -+ ptr[3] = 1; -+ ib_info[0].ib_mc_address = ib_result_ce_mc_address; -+ ib_info[0].size = 4; -+ ib_info[0].flags = AMDGPU_IB_FLAG_CE; -+ -+ /* IT_WAIT_ON_CE_COUNTER */ -+ ptr = ib_result_cpu; -+ ptr[0] = 0xc0008600; -+ ptr[1] = 0x00000001; -+ ib_info[1].ib_mc_address = ib_result_mc_address; -+ ib_info[1].size = 2; -+ -+ for (i = 0; i < ib_cs_num; i++) { -+ ibs_request[i].ip_type = AMDGPU_HW_IP_GFX; -+ ibs_request[i].number_of_ibs = 2; -+ ibs_request[i].ibs = ib_info; -+ ibs_request[i].resources = bo_list; -+ ibs_request[i].fence_info.handle = NULL; -+ } -+ -+ r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num); -+ -+ CU_ASSERT_EQUAL(r, 0); -+ -+ for (i = 0; i < ib_cs_num; i++) { -+ fence_status[i].context = context_handle; -+ fence_status[i].ip_type = AMDGPU_HW_IP_GFX; -+ fence_status[i].fence = ibs_request[i].seq_no; -+ } -+ -+ r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, -+ AMDGPU_TIMEOUT_INFINITE, -+ &expired); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, -+ ib_result_mc_address, 4096); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce, -+ ib_result_ce_mc_address, 4096); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_list_destroy(bo_list); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_cs_ctx_free(context_handle); -+ CU_ASSERT_EQUAL(r, 0); -+} -+ -+static void amdgpu_command_submission_multi_fence(void) -+{ -+ amdgpu_command_submission_multi_fence_wait_all(true); -+ amdgpu_command_submission_multi_fence_wait_all(false); -+} -+ - static void amdgpu_userptr_test(void) - { - int i, r, j; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0028-amdgpu-add-query-for-aperture-va-range.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0028-amdgpu-add-query-for-aperture-va-range.patch deleted file mode 100644 index 041f04e4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0028-amdgpu-add-query-for-aperture-va-range.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 6699587911b702ad612ad0e942214186ca04c1c2 Mon Sep 17 00:00:00 2001 -From: Flora Cui <flora.cui@amd.com> -Date: Sat, 10 Oct 2015 17:25:06 +0800 -Subject: [PATCH 028/117] amdgpu: add query for aperture va range - -Change-Id: I4358cdd7cd86f172967e063eac13708941c4e566 -Signed-off-by: Flora Cui <flora.cui@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++ - amdgpu/amdgpu_gpu_info.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 16 ++++++++++++++++ - 3 files changed, 91 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 8822a0c..ccb4971 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1081,6 +1081,36 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, - struct amdgpu_gds_resource_info *gds_info); - - /** -+* Query private aperture range -+* -+* \param dev - [in] Device handle. See #amdgpu_device_initialize() -+* \param start - \c [out] Start of private aperture -+* \param end - \c [out] End of private aperture -+* -+* \return 0 on success\n -+* <0 - Negative POSIX Error code -+* -+*/ -+int amdgpu_query_private_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end); -+ -+/** -+* Query shared aperture range -+* -+* \param dev - [in] Device handle. See #amdgpu_device_initialize() -+* \param start - \c [out] Start of shared aperture -+* \param end - \c [out] End of shared aperture -+* -+* \return 0 on success\n -+* <0 - Negative POSIX Error code -+* -+*/ -+int amdgpu_query_shared_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end); -+ -+/** - * Read a set of consecutive memory-mapped registers. - * Not all registers are allowed to be read by userspace. - * -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 0cc17f1..73d8d11 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -308,3 +308,48 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, - - return 0; - } -+ -+static int amdgpu_query_virtual_range_info(amdgpu_device_handle dev, -+ uint32_t aperture, -+ uint64_t *start, -+ uint64_t *end) -+{ -+ struct drm_amdgpu_virtual_range range_info; -+ struct drm_amdgpu_info request; -+ int r; -+ -+ memset(&range_info, 0, sizeof(range_info)); -+ request.return_pointer = (uintptr_t)&range_info; -+ request.return_size = sizeof(range_info); -+ request.query = AMDGPU_INFO_VIRTUAL_RANGE; -+ request.virtual_range.aperture = aperture; -+ -+ r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, -+ sizeof(struct drm_amdgpu_info)); -+ if (r) -+ return r; -+ -+ *start = range_info.start; -+ *end = range_info.end; -+ return 0; -+} -+ -+int amdgpu_query_private_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end) -+{ -+ return amdgpu_query_virtual_range_info(dev, -+ AMDGPU_SUA_APERTURE_PRIVATE, -+ start, -+ end); -+} -+ -+int amdgpu_query_shared_aperture(amdgpu_device_handle dev, -+ uint64_t *start, -+ uint64_t *end) -+{ -+ return amdgpu_query_virtual_range_info(dev, -+ AMDGPU_SUA_APERTURE_SHARED, -+ start, -+ end); -+} -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 2cbea72..f97acd1 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -504,6 +504,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_DEV_INFO 0x16 - /* visible vram usage */ - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 -+/* virtual range */ -+#define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -560,6 +562,11 @@ struct drm_amdgpu_info { - uint32_t index; - uint32_t _pad; - } query_fw; -+ -+ struct { -+ uint32_t aperture; -+ uint32_t _pad; -+ } virtual_range; - }; - }; - -@@ -669,4 +676,13 @@ struct drm_amdgpu_info_hw_ip { - #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ - #define AMDGPU_FAMILY_CZ 135 /* Carrizo */ - -+/** -+ * Definition of System Unified Address (SUA) apertures -+ */ -+#define AMDGPU_SUA_APERTURE_PRIVATE 1 -+#define AMDGPU_SUA_APERTURE_SHARED 2 -+struct drm_amdgpu_virtual_range { -+ uint64_t start; -+ uint64_t end; -+}; - #endif --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0029-amdgpu-Implement-SVM-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0029-amdgpu-Implement-SVM-v2.patch deleted file mode 100644 index 948d9072..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0029-amdgpu-Implement-SVM-v2.patch +++ /dev/null @@ -1,305 +0,0 @@ -From f34f4232b7a2dad9bb1aaaa68f77ed5a5fa76456 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 20 Oct 2015 11:47:14 -0400 -Subject: [PATCH 029/117] amdgpu: Implement SVM v2 - -SWDEV-75927: Coarse Grain SVM support for OpenCL 2.0 -Add SVM API. -Implement SVM to reserve CPU and GPU VM address space for SVM. Implement commit/uncommit function for SVM. - -v2: -Merge patch1 and patch2. -Update description of the commit. -Address review comments on coding style. -Update comments in source code. -Fix one issue in function amdgpu_va_range_query. The start of the range should be dev->vamgr_svm->va_min. -Fix an error code. - -Change-Id: Ib804b075347646ee6c4b4159583f1b4a0325df08 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu.h | 28 ++++++++- - amdgpu/amdgpu_device.c | 3 + - amdgpu/amdgpu_internal.h | 6 ++ - amdgpu/amdgpu_vamgr.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++- - 4 files changed, 178 insertions(+), 4 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index ccb4971..79314fb 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -87,7 +87,9 @@ enum amdgpu_bo_handle_type { - enum amdgpu_gpu_va_range - { - /** Allocate from "normal"/general range */ -- amdgpu_gpu_va_range_general = 0 -+ amdgpu_gpu_va_range_general = 0, -+ /** Allocate from svm range */ -+ amdgpu_gpu_va_range_svm = 1 - }; - - /*--------------------------------------------------------------------------*/ -@@ -1238,6 +1240,30 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - uint32_t ops); - - /** -+ * Commit SVM allocation in a process -+ * -+ * \param va_range_handle - \c [in] Handle of SVM allocation -+ * \param cpu - \c [out] CPU pointer. The value is equal to GPU VM address. -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, -+ void **cpu); -+ -+/** -+ * Uncommit SVM alloation in process's CPU_VM -+ * -+ * \param va_range_handle - \c [in] Handle of SVM allocation -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_svm_uncommit(amdgpu_va_handle va_range_handle); -+ -+/** - * create semaphore - * - * \param sem - \c [out] semaphore handle -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index e5a923e..eb71c44 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -130,6 +130,7 @@ static int amdgpu_get_auth(int fd, int *auth) - - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { -+ amdgpu_svm_vamgr_deinit(dev); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); - amdgpu_vamgr_deinit(dev->vamgr_32); -@@ -275,6 +276,8 @@ int amdgpu_device_initialize(int fd, - amdgpu_vamgr_init(dev->vamgr_32, start, max, - dev->dev_info.virtual_address_alignment); - -+ amdgpu_svm_vamgr_init(dev); -+ - *major_version = dev->major_version; - *minor_version = dev->minor_version; - *device_handle = dev; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 557ba1f..3ae92d9 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -54,6 +54,7 @@ struct amdgpu_bo_va_hole { - struct amdgpu_bo_va_mgr { - /* the start virtual address */ - uint64_t va_offset; -+ uint64_t va_min; - uint64_t va_max; - struct list_head va_holes; - pthread_mutex_t bo_va_mutex; -@@ -87,6 +88,8 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr *vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr *vamgr_32; -+ /** The VA manager for SVM address space */ -+ struct amdgpu_bo_va_mgr *vamgr_svm; - }; - - struct amdgpu_bo { -@@ -148,6 +151,9 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - drm_private void - amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); - -+int amdgpu_svm_vamgr_init(struct amdgpu_device *dev); -+void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev); -+ - drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); - - drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 8a707cb..f664216 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -36,18 +36,30 @@ - int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) - { -- if (type == amdgpu_gpu_va_range_general) { -+ switch (type) { -+ case amdgpu_gpu_va_range_general: - *start = dev->dev_info.virtual_address_offset; - *end = dev->dev_info.virtual_address_max; - return 0; -+ case amdgpu_gpu_va_range_svm: -+ if (dev->vamgr_svm) { -+ *start = dev->vamgr_svm->va_min; -+ *end = dev->vamgr_svm->va_max; -+ } else { -+ *start = 0ULL; -+ *end = 0ULL; -+ } -+ return 0; -+ default: -+ return -EINVAL; - } -- return -EINVAL; - } - - drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, - uint64_t max, uint64_t alignment) - { - mgr->va_offset = start; -+ mgr->va_min = start; - mgr->va_max = max; - mgr->va_alignment = alignment; - -@@ -235,7 +247,12 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - { - struct amdgpu_bo_va_mgr *vamgr; - -- if (flags & AMDGPU_VA_RANGE_32_BIT) -+ if (amdgpu_gpu_va_range_svm == va_range_type) { -+ vamgr = dev->vamgr_svm; -+ if (!vamgr) -+ return -EINVAL; -+ } -+ else if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = dev->vamgr_32; - else - vamgr = dev->vamgr; -@@ -285,3 +302,125 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) - free(va_range_handle); - return 0; - } -+ -+/** -+ * Initialize SVM VAM manager. -+ * When this function return error, future SVM allocation will fail. -+ * Caller may ignore the error code returned by this function. -+ * -+ * \param dev - \c [in] amdgpu_device pointer -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ */ -+int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) -+{ -+ uint64_t start; -+ uint64_t end; -+ /* size of SVM range */ -+ uint64_t size; -+ uint64_t base_required; -+ /* Size of step when looking for SVM range. */ -+ uint64_t step; -+ /*Will not search less than this address. */ -+ uint64_t min_base_required; -+ void * cpu_address; -+ /* return value of this function. */ -+ int ret; -+ -+ ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); -+ if (ret) -+ return ret; -+ -+ /* size of the general VM */ -+ size = end - start; -+ /* size of SVM range */ -+ size = size / 4; -+ /* at least keep lower 4G for process usage in CPU address space*/ -+ min_base_required = 4ULL * 1024ULL * 1024ULL * 1024ULL; -+ step = size / 8; -+ -+ ret = -ENOSPC; -+ /* We try to find a hole both in CPU/GPU VM address space for SVM from top -+ * to bottom. -+ */ -+ for (base_required = end - size; base_required >= min_base_required; -+ base_required -= step) { -+ start = amdgpu_vamgr_find_va(dev->vamgr, size, -+ dev->dev_info.virtual_address_alignment, base_required); -+ if (start != base_required) -+ continue; -+ -+ /* Try to map the SVM range in CPU VM */ -+ cpu_address = mmap((void *)start, size, PROT_NONE, -+ MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); -+ if (cpu_address == (void *)start) { -+ dev->vamgr_svm = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -+ if (dev->vamgr_svm == NULL) { -+ amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ munmap(cpu_address, size); -+ ret = -ENOMEM; -+ } else { -+ amdgpu_vamgr_init(dev->vamgr_svm, start, start + size, -+ dev->dev_info.virtual_address_alignment); -+ ret = 0; -+ } -+ break; -+ } else if (cpu_address == MAP_FAILED) { -+ /* Probably there is no space in this process's address space for -+ such size of SVM range. This is very rare for 64 bit CPU. -+ */ -+ amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ ret = -ENOMEM; -+ break; -+ } else { /* cpu_address != (void *)start */ -+ /* This CPU VM address (start) is not available*/ -+ amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ munmap(cpu_address, size); -+ base_required -= step; -+ } -+ } -+ -+ return ret; -+} -+ -+void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) -+{ -+ if (dev->vamgr_svm) { -+ amdgpu_vamgr_deinit(dev->vamgr_svm); -+ munmap((void *)dev->vamgr_svm->va_min, -+ dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); -+ free(dev->vamgr_svm); -+ } -+} -+ -+int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, -+ void **cpu) -+{ -+ if (!va_range_handle || !va_range_handle->address) -+ return -EINVAL; -+ if (va_range_handle->range != amdgpu_gpu_va_range_svm) -+ return -EINVAL; -+ -+ if (mprotect((void *)va_range_handle->address, -+ va_range_handle->size, PROT_READ | PROT_WRITE) == 0) { -+ *cpu = (void *)va_range_handle->address; -+ return 0; -+ } else -+ return errno; -+} -+ -+int amdgpu_svm_uncommit(amdgpu_va_handle va_range_handle) -+{ -+ if (!va_range_handle || !va_range_handle->address) -+ return -EINVAL; -+ if (va_range_handle->range != amdgpu_gpu_va_range_svm) -+ return -EINVAL; -+ -+ if (mprotect((void *)va_range_handle->address, -+ va_range_handle->size, PROT_NONE) == 0) { -+ return 0; -+ } else -+ return errno; -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0030-amdgpu-SVM-test-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0030-amdgpu-SVM-test-v2.patch deleted file mode 100644 index bacd7388..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0030-amdgpu-SVM-test-v2.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 7b1f524b40c1ec014265f49646d10ef8cd52659d Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 20 Oct 2015 11:52:08 -0400 -Subject: [PATCH 030/117] amdgpu: SVM test v2 - -SWDEV-75927: Coarse Grain SVM support for OpenCL 2.0 Add SVM relevant test. - -v2: -Update the description of this commit. -Fix an issue that the SVM feature should not be tested when SVM range is not supported. -Remove test for query function for general VM range. - -Change-Id: I21fad07611d88280ffa1375ecf1de95c305cac22 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/basic_tests.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 46 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 56db935..eb73578 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -49,6 +49,7 @@ static void amdgpu_command_submission_sdma(void); - static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); -+static void amdgpu_svm_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -59,9 +60,11 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, - { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, -+ { "SVM Test", amdgpu_svm_test }, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -+#define SVM_TEST_COUNT 16 - #define SDMA_PKT_HEADER_op_offset 0 - #define SDMA_PKT_HEADER_op_mask 0x000000FF - #define SDMA_PKT_HEADER_op_shift 0 -@@ -1077,3 +1080,46 @@ static void amdgpu_userptr_test(void) - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); - } -+ -+static void amdgpu_svm_test(void) -+{ -+ int r; -+ uint64_t svm_mc; -+ amdgpu_va_handle va_handle[SVM_TEST_COUNT]; -+ void *cpu; -+ uint64_t start; -+ uint64_t end; -+ int i; -+ -+ r = amdgpu_va_range_query(device_handle, -+ amdgpu_gpu_va_range_svm, &start, &end); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ /* If there is no SVM range, exit this function.*/ -+ if (start == 0ULL && end == 0ULL) -+ return; -+ -+ CU_ASSERT(start < end); -+ CU_ASSERT(end - start >= 1ULL * 1024ULL * 1024ULL * 1024ULL); -+ -+ for (i = 0; i < SVM_TEST_COUNT; i++) { -+ r = amdgpu_va_range_alloc(device_handle, -+ amdgpu_gpu_va_range_svm, -+ 64 * 1024 * 1024, 1, 0, &svm_mc, -+ &va_handle[i], 0); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_svm_commit(va_handle[i], &cpu); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_PTR_NOT_NULL(cpu); -+ CU_ASSERT_EQUAL(svm_mc, (uint64_t)cpu); -+ } -+ -+ for (i = 0; i < SVM_TEST_COUNT; i++) { -+ r = amdgpu_svm_uncommit(va_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_va_range_free(va_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch deleted file mode 100644 index 1e2c81e7..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch +++ /dev/null @@ -1,167 +0,0 @@ -From e977542110f13aa8b0d3e4cf89f56140f0a0009f Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Thu, 29 Oct 2015 16:13:45 -0400 -Subject: [PATCH 031/117] amdgpu: Implement multiGPU SVM support v2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -With this change, if there are multiple GPU devices, SVM range and allocation is global to all GPU devices. -This is to meet the OpenCL 2.0 SVM requirement. This is not a perfect solution. But we have not found better solution. - -Constraints: - 1. Application should initialize all relevant devices before allocate SVM address. - 2. If devices do not have similar GPU VM configuration, libdrm can disable SVM when new device are initialized. - -v2: - 1. Put svm_refcount and svm_valid as a field of amdgpu_bo_va_mgr. - 2. Adjust title. - -Change-Id: I2cfa97e61a9ae1184da9a95f15398e050cb5caaf -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_internal.h | 6 +++-- - amdgpu/amdgpu_vamgr.c | 61 ++++++++++++++++++++++++++++++++---------------- - 2 files changed, 45 insertions(+), 22 deletions(-) - -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3ae92d9..0506853 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -59,6 +59,10 @@ struct amdgpu_bo_va_mgr { - struct list_head va_holes; - pthread_mutex_t bo_va_mutex; - uint32_t va_alignment; -+ /* reference count. It is used by SVM for mulit GPU.*/ -+ atomic_t refcount; -+ /* Is the VM manager valid. It is used by SVM for mulit GPU.*/ -+ bool valid; - }; - - struct amdgpu_va { -@@ -88,8 +92,6 @@ struct amdgpu_device { - struct amdgpu_bo_va_mgr *vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr *vamgr_32; -- /** The VA manager for SVM address space */ -- struct amdgpu_bo_va_mgr *vamgr_svm; - }; - - struct amdgpu_bo { -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index f664216..945b006 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -33,6 +33,9 @@ - #include "amdgpu_internal.h" - #include "util_math.h" - -+/* Devices share SVM range. So a global SVM VAM manager is needed. */ -+static struct amdgpu_bo_va_mgr vamgr_svm; -+ - int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) - { -@@ -42,9 +45,9 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, - *end = dev->dev_info.virtual_address_max; - return 0; - case amdgpu_gpu_va_range_svm: -- if (dev->vamgr_svm) { -- *start = dev->vamgr_svm->va_min; -- *end = dev->vamgr_svm->va_max; -+ if (vamgr_svm.valid) { -+ *start = vamgr_svm.va_min; -+ *end = vamgr_svm.va_max; - } else { - *start = 0ULL; - *end = 0ULL; -@@ -248,8 +251,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - struct amdgpu_bo_va_mgr *vamgr; - - if (amdgpu_gpu_va_range_svm == va_range_type) { -- vamgr = dev->vamgr_svm; -- if (!vamgr) -+ vamgr = &vamgr_svm; -+ if (!vamgr->valid) - return -EINVAL; - } - else if (flags & AMDGPU_VA_RANGE_32_BIT) -@@ -329,6 +332,23 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - /* return value of this function. */ - int ret; - -+ if (atomic_inc_return(&vamgr_svm.refcount) != 1) { -+ /* This is not the first time to initialize SVM in this process. */ -+ if (!vamgr_svm.valid) -+ return -ENOSPC; -+ -+ start = amdgpu_vamgr_find_va(dev->vamgr, -+ vamgr_svm.va_max - vamgr_svm.va_min, -+ dev->dev_info.virtual_address_alignment, vamgr_svm.va_min); -+ -+ if (start != vamgr_svm.va_min) { -+ vamgr_svm.valid = false; -+ return -ENOSPC; -+ } -+ -+ return 0; -+ } -+ - ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); - if (ret) - return ret; -@@ -356,16 +376,9 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - cpu_address = mmap((void *)start, size, PROT_NONE, - MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); - if (cpu_address == (void *)start) { -- dev->vamgr_svm = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -- if (dev->vamgr_svm == NULL) { -- amdgpu_vamgr_free_va(dev->vamgr, start, size); -- munmap(cpu_address, size); -- ret = -ENOMEM; -- } else { -- amdgpu_vamgr_init(dev->vamgr_svm, start, start + size, -- dev->dev_info.virtual_address_alignment); -- ret = 0; -- } -+ amdgpu_vamgr_init(&vamgr_svm, start, start + size, -+ dev->dev_info.virtual_address_alignment); -+ ret = 0; - break; - } else if (cpu_address == MAP_FAILED) { - /* Probably there is no space in this process's address space for -@@ -382,16 +395,24 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - } - } - -+ if (!ret) -+ vamgr_svm.valid = true; -+ - return ret; - } - - void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) - { -- if (dev->vamgr_svm) { -- amdgpu_vamgr_deinit(dev->vamgr_svm); -- munmap((void *)dev->vamgr_svm->va_min, -- dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); -- free(dev->vamgr_svm); -+ if (atomic_dec_and_test(&vamgr_svm.refcount)) { -+ /* This is the last device referencing SVM. */ -+ if (vamgr_svm.va_max != 0) { -+ /* SVM was initialized successfull. So SVM need uninitialization.*/ -+ amdgpu_vamgr_deinit(&vamgr_svm); -+ munmap((void *)vamgr_svm.va_min, -+ vamgr_svm.va_max - vamgr_svm.va_min); -+ vamgr_svm.va_max = 0; -+ } -+ vamgr_svm.valid = false; - } - } - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch deleted file mode 100644 index 388419d8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch +++ /dev/null @@ -1,335 +0,0 @@ -From ce7de7e34c1a87d56bcc7a8ebeac1a25756c5991 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Fri, 30 Oct 2015 12:04:07 -0400 -Subject: [PATCH 032/117] tests/amdgpu: Add test for multi GPUs SVM test v3 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. We try to open all GPUs when test starts. -2. Test multi GPUs for SVM -3. Add verbose output option and facility into this unit test app. - -v2: -1. Adjust title -2. Use drmGetDevices to get the number of cards available. -3. Add warning output option and facility into this unit test app. -4. Adjust a comment and delete useless C statement when open function call fails. -5. Add two informative outputs in single SVM test. - -v3: -1. Use general device name from drmGetDevices instead of fixed name. -2. open devices in a single "for" statement. -3. Create a function to close all devices. - -Change-Id: I313c13eabd6f0c2d3107ba37413e8ebd871faa0e -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Acked-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/amdgpu_test.c | 92 +++++++++++++++++++++++++++++++++++++++------- - tests/amdgpu/amdgpu_test.h | 5 +++ - tests/amdgpu/basic_tests.c | 71 +++++++++++++++++++++++++++++++++++ - 3 files changed, 154 insertions(+), 14 deletions(-) - -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 71f357c..1e71fbf 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -56,6 +56,10 @@ - */ - int drm_amdgpu[MAX_CARDS_SUPPORTED]; - -+static int num_devices; -+static bool verbose = false; -+static bool warning = false; -+ - /** The table of all known test suites to run */ - static CU_SuiteInfo suites[] = { - { -@@ -106,14 +110,24 @@ static void display_test_suites(void) - } - } - -+static void amdgpu_close_all() -+{ -+ int i; -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) -+ close(drm_amdgpu[i]); -+} - - /** Help string for command line parameters */ --static const char usage[] = "Usage: %s [-hl] [<-s <suite id>> [-t <test id>]]\n" -+static const char usage[] = -+ "Usage: %s [-hlvw] [<-s <suite id>> [-t <test id>]]\n" - "where:\n" - " l - Display all suites and their tests\n" -+ " v - Verbose output\n" -+ " w - Output warning message\n" - " h - Display this help\n"; - /** Specified options strings for getopt */ --static const char options[] = "hls:t:"; -+static const char options[] = "hlvws:t:"; - - /* The main() function for setting up and running the tests. - * Returns a CUE_SUCCESS on successful running, another -@@ -127,8 +141,10 @@ int main(int argc, char **argv) - int test_id = -1; /* By default run all tests in the suite */ - CU_pSuite pSuite = NULL; - CU_pTest pTest = NULL; -+ drmDevicePtr devices[MAX_CARDS_SUPPORTED]; - - int aval = drmAvailable(); -+ char card_name[256]; - - if (aval == 0) { - fprintf(stderr, "DRM driver is not available\n"); -@@ -153,6 +169,12 @@ int main(int argc, char **argv) - case 't': - test_id = atoi(optarg); - break; -+ case 'v': -+ verbose = true; -+ break; -+ case 'w': -+ warning = true; -+ break; - case '?': - case 'h': - fprintf(stderr, usage, argv[0]); -@@ -163,17 +185,31 @@ int main(int argc, char **argv) - } - } - -- /* Try to open all possible radeon connections -- * Right now: Open only the 0. -+ /* Try to open all possible amdgpu connections - */ -- printf("Try to open the card 0..\n"); -- drm_amdgpu[0] = open("/dev/dri/card0", O_RDWR | O_CLOEXEC); -- -- if (drm_amdgpu[0] < 0) { -- perror("Cannot open /dev/dri/card0\n"); -+ num_devices = drmGetDevices(devices, MAX_CARDS_SUPPORTED); -+ amdgpu_vprintf("\n Number of DRI devices is %d\n", num_devices); -+ if (num_devices > MAX_CARDS_SUPPORTED) -+ num_devices = MAX_CARDS_SUPPORTED; -+ if (num_devices <= 0) { -+ perror("Cannot query number of DRI devices.\n"); - exit(EXIT_FAILURE); - } - -+ for (i = 0; i < num_devices; i++) { -+ amdgpu_vprintf("Try to open %s..\n", -+ devices[i]->nodes[DRM_NODE_PRIMARY]); -+ drm_amdgpu[i] = open(devices[i]->nodes[DRM_NODE_PRIMARY], -+ O_RDWR | O_CLOEXEC); -+ if (i == 0 && drm_amdgpu[i] < 0) { -+ drmFreeDevices(devices, num_devices); -+ /* It is essential to open first connection to run any test. */ -+ perror("Cannot open first card.\n"); -+ exit(EXIT_FAILURE); -+ } -+ } -+ drmFreeDevices(devices, num_devices); -+ - /** Display version of DRM driver */ - drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); - -@@ -191,7 +227,7 @@ int main(int argc, char **argv) - - /* initialize the CUnit test registry */ - if (CUE_SUCCESS != CU_initialize_registry()) { -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - return CU_get_error(); - } - -@@ -200,7 +236,7 @@ int main(int argc, char **argv) - fprintf(stderr, "suite registration failed - %s\n", - CU_get_error_msg()); - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - exit(EXIT_FAILURE); - } - -@@ -222,7 +258,7 @@ int main(int argc, char **argv) - fprintf(stderr, "Invalid test id: %d\n", - test_id); - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - exit(EXIT_FAILURE); - } - } else -@@ -231,13 +267,41 @@ int main(int argc, char **argv) - fprintf(stderr, "Invalid suite id : %d\n", - suite_id); - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); - exit(EXIT_FAILURE); - } - } else - CU_basic_run_tests(); - - CU_cleanup_registry(); -- close(drm_amdgpu[0]); -+ amdgpu_close_all(); -+ - return CU_get_error(); - } -+ -+void amdgpu_vprintf(char *fmt, ...) -+{ -+ va_list args; -+ if (verbose) { -+ va_start(args, fmt); -+ vprintf(fmt, args); -+ va_end(args); -+ } -+} -+ -+void amdgpu_warning(bool condition, char *fmt, ...) -+{ -+ if (warning && condition) -+ { -+ printf ("WARNING: "); -+ va_list args; -+ va_start(args, fmt); -+ vprintf(fmt, args); -+ va_end(args); -+ } -+} -+ -+int amdgpu_num_devices() -+{ -+ return num_devices; -+} -diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h -index fca92ad..5c47ba3 100644 ---- a/tests/amdgpu/amdgpu_test.h -+++ b/tests/amdgpu/amdgpu_test.h -@@ -104,6 +104,11 @@ extern CU_TestInfo vce_tests[]; - /** - * Helper functions - */ -+ -+void amdgpu_vprintf(char *fmt, ...); -+void amdgpu_warning(bool condition, char *fmt, ...); -+int amdgpu_num_devices(); -+ - static inline amdgpu_bo_handle gpu_mem_alloc( - amdgpu_device_handle device_handle, - uint64_t size, -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index eb73578..23178e0 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -50,6 +50,7 @@ static void amdgpu_command_submission_multi_fence(void); - static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); - static void amdgpu_svm_test(void); -+static void amdgpu_multi_svm_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -61,6 +62,7 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, - { "SVM Test", amdgpu_svm_test }, -+ { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -@@ -1094,6 +1096,8 @@ static void amdgpu_svm_test(void) - r = amdgpu_va_range_query(device_handle, - amdgpu_gpu_va_range_svm, &start, &end); - CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("\n"); -+ amdgpu_vprintf("SVM range is from 0x%llx to 0x%llx.\n", start, end); - - /* If there is no SVM range, exit this function.*/ - if (start == 0ULL && end == 0ULL) -@@ -1108,6 +1112,7 @@ static void amdgpu_svm_test(void) - 64 * 1024 * 1024, 1, 0, &svm_mc, - &va_handle[i], 0); - CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("Allocate SVM MC 0x%llx.\n", svm_mc); - - r = amdgpu_svm_commit(va_handle[i], &cpu); - CU_ASSERT_EQUAL(r, 0); -@@ -1123,3 +1128,69 @@ static void amdgpu_svm_test(void) - CU_ASSERT_EQUAL(r, 0); - } - } -+ -+static void amdgpu_multi_svm_test(void) -+{ -+ int r; -+ int i; -+ uint64_t svm_mcs[MAX_CARDS_SUPPORTED]; -+ amdgpu_va_handle va_handles[MAX_CARDS_SUPPORTED]; -+ amdgpu_device_handle device_handles[MAX_CARDS_SUPPORTED]; -+ uint32_t major_version; -+ uint32_t minor_version; -+ int num_devices; -+ -+ device_handles[0] = device_handle; -+ num_devices = amdgpu_num_devices(); -+ -+ for (i = 1; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_device_initialize(drm_amdgpu[i], &major_version, -+ &minor_version, &device_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ amdgpu_vprintf("\n"); -+ amdgpu_vprintf(" Testing to alloc and free SVM in all GPUs.\n"); -+ amdgpu_vprintf(" The svm_mcs generally are same.\n"); -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_va_range_alloc(device_handles[i], -+ amdgpu_gpu_va_range_svm, -+ 0x1000000, 1, 0, &svm_mcs[i], -+ &va_handles[i], 0); -+ CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf(" card %d, svm_mc 0x%llx\n", i, svm_mcs[i]); -+ amdgpu_warning(svm_mcs[i] != svm_mcs[0], -+ "The SVM from different GPUs should be able to be allocated" -+ " from same location."); -+ r = amdgpu_va_range_free(va_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ amdgpu_vprintf(" Testing to alloc SVM in all GPUs.\n"); -+ amdgpu_vprintf(" The svm_mcs are generally different by 0x1000000\n"); -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_va_range_alloc(device_handles[i], -+ amdgpu_gpu_va_range_svm, -+ 0x1000000, 1, 0, &svm_mcs[i], -+ &va_handles[i], 0); -+ CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf(" card %d, svm_mc 0x%llx\n", i, svm_mcs[i]); -+ amdgpu_warning(svm_mcs[i] - svm_mcs[0] != 0x1000000 * i, -+ "The SVM from GPUs should be allocated sequentially."); -+ } -+ -+ for (i = 0; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_va_range_free(va_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ for (i = 1; i < num_devices; i++) -+ if (drm_amdgpu[i] > 0) { -+ r = amdgpu_device_deinitialize(device_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0033-tests-amdgpu-Add-verbose-outputs-v2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0033-tests-amdgpu-Add-verbose-outputs-v2.patch deleted file mode 100644 index 81be4d87..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0033-tests-amdgpu-Add-verbose-outputs-v2.patch +++ /dev/null @@ -1,245 +0,0 @@ -From cb0741a52b97b4cf14a3407e74b5bf3973735a2f Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 11:03:21 -0500 -Subject: [PATCH 033/117] tests/amdgpu: Add verbose outputs v2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Add verbose output for information of compute rings. -2. Add verbose output for other hardware information, probably for test of harvesting. -3. Add verbose output for GPU information. This can provide information when reporting JIRA issue. -4. Add verbose output for firmware version. This can provide developer with firmware information. - -v2: Use 8 for the maximum ring number in function amd_query_hw_info_test - -Change-Id: I6e37332345007625456b33a20d7bfb8850eb53d5 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by:Jammy Zhou<Jammy.Zhou@amd.com> -Acked-by:Christian König<christian.koenig@amd.com> ---- - tests/amdgpu/amdgpu_test.c | 19 ++++++ - tests/amdgpu/amdgpu_test.h | 1 + - tests/amdgpu/basic_tests.c | 149 ++++++++++++++++++++++++++++++++++++++++++++- - 3 files changed, 167 insertions(+), 2 deletions(-) - -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 1e71fbf..46f55c7 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -305,3 +305,22 @@ int amdgpu_num_devices() - { - return num_devices; - } -+ -+/* Translate HW IP type to name. */ -+char * amdgpu_hw_ip_type_to_name(unsigned type) -+{ -+ switch (type) { -+ case AMDGPU_HW_IP_GFX: -+ return "graphic"; -+ case AMDGPU_HW_IP_COMPUTE: -+ return "compute"; -+ case AMDGPU_HW_IP_DMA: -+ return "DMA"; -+ case AMDGPU_HW_IP_UVD: -+ return "UVD"; -+ case AMDGPU_HW_IP_VCE: -+ return "VCE"; -+ default: -+ return NULL; -+ } -+} -diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h -index 5c47ba3..dd88eb5 100644 ---- a/tests/amdgpu/amdgpu_test.h -+++ b/tests/amdgpu/amdgpu_test.h -@@ -108,6 +108,7 @@ extern CU_TestInfo vce_tests[]; - void amdgpu_vprintf(char *fmt, ...); - void amdgpu_warning(bool condition, char *fmt, ...); - int amdgpu_num_devices(); -+char * amdgpu_hw_ip_type_to_name(unsigned type); - - static inline amdgpu_bo_handle gpu_mem_alloc( - amdgpu_device_handle device_handle, -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 23178e0..47c796e 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -112,18 +112,161 @@ int suite_basic_tests_clean(void) - return CUE_SCLEAN_FAILED; - } - --static void amdgpu_query_info_test(void) -+static void amdgpu_query_hw_info_test(unsigned type) -+{ -+ int r; -+ int i; -+ bool first_ring = true; -+ struct drm_amdgpu_info_hw_ip ip_info; -+ char *name; -+ -+ name = amdgpu_hw_ip_type_to_name(type); -+ CU_ASSERT_NOT_EQUAL(name, NULL); -+ -+ r = amdgpu_query_hw_ip_info(device_handle, type, -+ 0, &ip_info); -+ -+ CU_ASSERT_EQUAL(r, 0); -+ -+ amdgpu_vprintf("\n %s HW IP...\n", name); -+ amdgpu_vprintf(" major version:%d\n", ip_info.hw_ip_version_major); -+ amdgpu_vprintf(" minor version:%d\n", ip_info.hw_ip_version_minor); -+ amdgpu_vprintf(" capabilities_flags:0x%llx\n", -+ ip_info.capabilities_flags); -+ amdgpu_vprintf(" IB start alignment:%d\n", ip_info.ib_start_alignment); -+ amdgpu_vprintf(" IB size alignment:%d\n", ip_info.ib_size_alignment); -+ amdgpu_vprintf(" Following rings are supported: "); -+ for (i = 0; i < 8; i++) -+ if (ip_info.available_rings & 1 << i) { -+ if (first_ring) -+ first_ring = false; -+ else -+ amdgpu_vprintf(", "); -+ -+ amdgpu_vprintf("%d", i); -+ } -+ -+ amdgpu_vprintf(".\n"); -+} -+ -+static void amdgpu_query_gpu_info_test() - { - struct amdgpu_gpu_info gpu_info = {0}; -- uint32_t version, feature; - int r; -+ int i, j; - - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - -+ amdgpu_vprintf("\n GPU info...\n"); -+ -+ amdgpu_vprintf(" Asic id:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.asic_id); -+ amdgpu_vprintf(" Chip revision:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.chip_rev); -+ amdgpu_vprintf(" Chip external revision:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.chip_external_rev); -+ amdgpu_vprintf(" Family ID:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.family_id); -+ amdgpu_vprintf(" Special flags:"); -+ amdgpu_vprintf("0x%llx\n", gpu_info.ids_flags); -+ amdgpu_vprintf(" max engine clock:"); -+ amdgpu_vprintf("0x%llx\n", gpu_info.max_engine_clk); -+ amdgpu_vprintf(" max memory clock:"); -+ amdgpu_vprintf("0x%llx\n", gpu_info.max_memory_clk); -+ amdgpu_vprintf(" number of shader engines:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.num_shader_engines); -+ amdgpu_vprintf(" number of shader arrays per engine:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.num_shader_arrays_per_engine); -+ amdgpu_vprintf(" Number of available good shader pipes:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.avail_quad_shader_pipes); -+ amdgpu_vprintf(" Max. number of shader pipes." -+ "(including good and bad pipes :"); -+ amdgpu_vprintf("0x%x\n", gpu_info.max_quad_shader_pipes); -+ amdgpu_vprintf(" Number of parameter cache entries per shader quad " -+ "pipe:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.cache_entries_per_quad_pipe); -+ amdgpu_vprintf(" Number of available graphics context:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.num_hw_gfx_contexts); -+ amdgpu_vprintf(" Number of render backend pipes:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.rb_pipes); -+ amdgpu_vprintf(" Enabled render backend pipe mask:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.enabled_rb_pipes_mask); -+ amdgpu_vprintf(" Frequency of GPU Counter:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.gpu_counter_freq); -+ -+ amdgpu_vprintf(" CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE:\n"); -+ for (i = 0; i < 4; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.backend_disable[i]); -+ -+ amdgpu_vprintf(" Value of MC_ARB_RAMCFG register:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.mc_arb_ramcfg); -+ amdgpu_vprintf(" Value of GB_ADDR_CONFIG:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.gb_addr_cfg); -+ -+ amdgpu_vprintf(" Values of the GB_TILE_MODE0..31 registers:\n"); -+ for (i = 0; i < 32; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.gb_tile_mode[i]); -+ -+ amdgpu_vprintf(" Values of GB_MACROTILE_MODE0..15 registers:\n"); -+ for (i = 0; i < 16; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.gb_macro_tile_mode[i]); -+ -+ amdgpu_vprintf(" Value of PA_SC_RASTER_CONFIG register per SE:\n"); -+ for (i = 0; i < 4; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.pa_sc_raster_cfg[i]); -+ -+ amdgpu_vprintf(" Value of PA_SC_RASTER_CONFIG_1 register per SE:\n"); -+ for (i = 0; i < 4; i++) -+ amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.pa_sc_raster_cfg1[i]); -+ -+ amdgpu_vprintf(" CU info (active number):"); -+ amdgpu_vprintf("0x%x\n", gpu_info.cu_active_number); -+ amdgpu_vprintf(" CU info (AU mask):"); -+ amdgpu_vprintf("0x%x\n", gpu_info.cu_ao_mask); -+ -+ amdgpu_vprintf(" CU info (AU bit map):"); -+ for (i = 0; i < 4; i++) { -+ amdgpu_vprintf("\n "); -+ for (j = 0; j < 4; j++) -+ amdgpu_vprintf(" [%d][%d]=0x%08x", i, j, gpu_info.cu_bitmap[i][j]); -+ } -+ amdgpu_vprintf("\n"); -+ -+ amdgpu_vprintf(" video memory type info:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.vram_type); -+ amdgpu_vprintf(" video memory bit width:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.vram_bit_width); -+ amdgpu_vprintf(" constant engine ram size:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.ce_ram_size); -+ amdgpu_vprintf(" vce harvesting instance:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.vce_harvest_config); -+ amdgpu_vprintf(" PCI revision ID:"); -+ amdgpu_vprintf("0x%x\n", gpu_info.pci_rev_id); -+} -+ -+static void amdgpu_query_firmware_info_test(void) -+{ -+ uint32_t version, feature; -+ int r; -+ - r = amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0, - 0, &version, &feature); - CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("\n VCE firmware info...\n"); -+ amdgpu_vprintf(" vce version: 0x%x\n", version); -+ amdgpu_vprintf(" vce feature: 0x%x\n", feature); -+} -+ -+static void amdgpu_query_info_test(void) -+{ -+ amdgpu_query_gpu_info_test(); -+ amdgpu_query_firmware_info_test(); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_GFX); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_COMPUTE); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_DMA); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); -+ amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); - } - - static void amdgpu_memory_alloc(void) -@@ -491,7 +634,9 @@ static void amdgpu_command_submission_compute(void) - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - -+ amdgpu_vprintf("\n"); - for (instance = 0; instance < 8; instance++) { -+ amdgpu_vprintf(" Submit NOP command on ring %d.\n", instance); - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch deleted file mode 100644 index f22421ea..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch +++ /dev/null @@ -1,38 +0,0 @@ -From e32955cf3b88b111e8d80a0c45e6e6d284d7d9a2 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 15:26:09 -0500 -Subject: [PATCH 034/117] amdgpu: Free/uninit vamgr_32 in theoretically correct - order -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -vamgr_32 is a region inside general VAM range. It is better to free and deinitialize it before general VAM range. - -Change-Id: Iaafaf5c1be7f274e933f1295a8822d90c1c6200d -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_device.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index eb71c44..a58a9d4 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -131,10 +131,10 @@ static int amdgpu_get_auth(int fd, int *auth) - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { - amdgpu_svm_vamgr_deinit(dev); -- amdgpu_vamgr_deinit(dev->vamgr); -- free(dev->vamgr); - amdgpu_vamgr_deinit(dev->vamgr_32); - free(dev->vamgr_32); -+ amdgpu_vamgr_deinit(dev->vamgr); -+ free(dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); - util_hash_table_destroy(dev->bo_handles); - pthread_mutex_destroy(&dev->bo_table_mutex); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch deleted file mode 100644 index 790f0641..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 98342e54c0e8d290a70bfea2b0631169ea414787 Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 15:46:33 -0500 -Subject: [PATCH 035/117] amdgpu: vamgr_32 can be a struct instead of a pointer -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -vamgr_32 is an integral part of amdgpu_device. We don't need to callac and free it. -This can save CPU time. Reduce heap fragment. - -Change-Id: I7b5797058e68d0b4c12705d628d32a996b2f3644 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_device.c | 8 ++------ - amdgpu/amdgpu_internal.h | 2 +- - amdgpu/amdgpu_vamgr.c | 4 ++-- - 3 files changed, 5 insertions(+), 9 deletions(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index a58a9d4..259c1cc 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -131,8 +131,7 @@ static int amdgpu_get_auth(int fd, int *auth) - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { - amdgpu_svm_vamgr_deinit(dev); -- amdgpu_vamgr_deinit(dev->vamgr_32); -- free(dev->vamgr_32); -+ amdgpu_vamgr_deinit(&dev->vamgr_32); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); -@@ -270,10 +269,7 @@ int amdgpu_device_initialize(int fd, - if (start > 0xffffffff) - goto free_va; /* shouldn't get here */ - -- dev->vamgr_32 = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -- if (dev->vamgr_32 == NULL) -- goto free_va; -- amdgpu_vamgr_init(dev->vamgr_32, start, max, -+ amdgpu_vamgr_init(&dev->vamgr_32, start, max, - dev->dev_info.virtual_address_alignment); - - amdgpu_svm_vamgr_init(dev); -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 0506853..892b467 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -91,7 +91,7 @@ struct amdgpu_device { - /** The global VA manager for the whole virtual address space */ - struct amdgpu_bo_va_mgr *vamgr; - /** The VA manager for the 32bit address space */ -- struct amdgpu_bo_va_mgr *vamgr_32; -+ struct amdgpu_bo_va_mgr vamgr_32; - }; - - struct amdgpu_bo { -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 945b006..916eb9e 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -256,7 +256,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - return -EINVAL; - } - else if (flags & AMDGPU_VA_RANGE_32_BIT) -- vamgr = dev->vamgr_32; -+ vamgr = &dev->vamgr_32; - else - vamgr = dev->vamgr; - -@@ -269,7 +269,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - if (!(flags & AMDGPU_VA_RANGE_32_BIT) && - (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { - /* fallback to 32bit address */ -- vamgr = dev->vamgr_32; -+ vamgr = &dev->vamgr_32; - *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, - va_base_alignment, va_base_required); - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch deleted file mode 100644 index 04da011e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 8326d0420e94fffc413eb9ef23de37074a20efeb Mon Sep 17 00:00:00 2001 -From: Alex Xie <AlexBin.Xie@amd.com> -Date: Tue, 3 Nov 2015 15:52:57 -0500 -Subject: [PATCH 036/117] amdgpu: vamgr can be a struct instead of a pointer -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -vamgr is an integral part of amdgpu_device. We don't need to callac and free it. -This can save CPU time. Reduce heap fragment. - -Change-Id: Ib5ca9e93d007370d2d746aea2c21c2f91aefa3c2 -Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_device.c | 16 +++++----------- - amdgpu/amdgpu_internal.h | 2 +- - amdgpu/amdgpu_vamgr.c | 10 +++++----- - 3 files changed, 11 insertions(+), 17 deletions(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index 259c1cc..b1a7182 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -132,8 +132,7 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { - amdgpu_svm_vamgr_deinit(dev); - amdgpu_vamgr_deinit(&dev->vamgr_32); -- amdgpu_vamgr_deinit(dev->vamgr); -- free(dev->vamgr); -+ amdgpu_vamgr_deinit(&dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); - util_hash_table_destroy(dev->bo_handles); - pthread_mutex_destroy(&dev->bo_table_mutex); -@@ -254,16 +253,12 @@ int amdgpu_device_initialize(int fd, - if (r) - goto cleanup; - -- dev->vamgr = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); -- if (dev->vamgr == NULL) -- goto cleanup; -- -- amdgpu_vamgr_init(dev->vamgr, dev->dev_info.virtual_address_offset, -+ amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset, - dev->dev_info.virtual_address_max, - dev->dev_info.virtual_address_alignment); - - max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); -- start = amdgpu_vamgr_find_va(dev->vamgr, -+ start = amdgpu_vamgr_find_va(&dev->vamgr, - max - dev->dev_info.virtual_address_offset, - dev->dev_info.virtual_address_alignment, 0); - if (start > 0xffffffff) -@@ -284,10 +279,9 @@ int amdgpu_device_initialize(int fd, - - free_va: - r = -ENOMEM; -- amdgpu_vamgr_free_va(dev->vamgr, start, -+ amdgpu_vamgr_free_va(&dev->vamgr, start, - max - dev->dev_info.virtual_address_offset); -- amdgpu_vamgr_deinit(dev->vamgr); -- free(dev->vamgr); -+ amdgpu_vamgr_deinit(&dev->vamgr); - - cleanup: - if (dev->fd >= 0) -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 892b467..caec2a2 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -89,7 +89,7 @@ struct amdgpu_device { - struct drm_amdgpu_info_device dev_info; - struct amdgpu_gpu_info info; - /** The global VA manager for the whole virtual address space */ -- struct amdgpu_bo_va_mgr *vamgr; -+ struct amdgpu_bo_va_mgr vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr vamgr_32; - }; -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 916eb9e..64a3543 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -258,7 +258,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - else if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = &dev->vamgr_32; - else -- vamgr = dev->vamgr; -+ vamgr = &dev->vamgr; - - va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); - size = ALIGN(size, vamgr->va_alignment); -@@ -337,7 +337,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - if (!vamgr_svm.valid) - return -ENOSPC; - -- start = amdgpu_vamgr_find_va(dev->vamgr, -+ start = amdgpu_vamgr_find_va(&dev->vamgr, - vamgr_svm.va_max - vamgr_svm.va_min, - dev->dev_info.virtual_address_alignment, vamgr_svm.va_min); - -@@ -367,7 +367,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - */ - for (base_required = end - size; base_required >= min_base_required; - base_required -= step) { -- start = amdgpu_vamgr_find_va(dev->vamgr, size, -+ start = amdgpu_vamgr_find_va(&dev->vamgr, size, - dev->dev_info.virtual_address_alignment, base_required); - if (start != base_required) - continue; -@@ -384,12 +384,12 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - /* Probably there is no space in this process's address space for - such size of SVM range. This is very rare for 64 bit CPU. - */ -- amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ amdgpu_vamgr_free_va(&dev->vamgr, start, size); - ret = -ENOMEM; - break; - } else { /* cpu_address != (void *)start */ - /* This CPU VM address (start) is not available*/ -- amdgpu_vamgr_free_va(dev->vamgr, start, size); -+ amdgpu_vamgr_free_va(&dev->vamgr, start, size); - munmap(cpu_address, size); - base_required -= step; - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0037-tests-amdgpu-add-the-heap-info-for-query.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0037-tests-amdgpu-add-the-heap-info-for-query.patch deleted file mode 100644 index 2b79b5ae..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0037-tests-amdgpu-add-the-heap-info-for-query.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 30625ac043a1dd882df4f9d1feed4b08ebdd6371 Mon Sep 17 00:00:00 2001 -From: Jammy Zhou <Jammy.Zhou@amd.com> -Date: Mon, 9 Nov 2015 13:40:41 +0800 -Subject: [PATCH 037/117] tests/amdgpu: add the heap info for query - -Change-Id: Icdaad4e373c316e0dde9a24cda4252ffd5163f1a -Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/basic_tests.c | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 47c796e..ec68dac 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -258,6 +258,32 @@ static void amdgpu_query_firmware_info_test(void) - amdgpu_vprintf(" vce feature: 0x%x\n", feature); - } - -+static void amdgpu_query_heap_info_test(void) -+{ -+ struct amdgpu_heap_info info; -+ uint64_t total_vram, total_vram_used; -+ -+ amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, -+ 0, &info); -+ total_vram = info.heap_size; -+ total_vram_used = info.heap_usage; -+ -+ amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, -+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &info); -+ amdgpu_vprintf("\n Visible VRAM info...\n"); -+ amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+ amdgpu_vprintf("\n Invisible VRAM info...\n"); -+ amdgpu_vprintf(" size: 0x%x\n", total_vram - info.heap_size); -+ amdgpu_vprintf(" usage: 0x%x\n", total_vram_used - info.heap_usage); -+ -+ amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, -+ 0, &info); -+ amdgpu_vprintf("\n GTT info...\n"); -+ amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+} -+ - static void amdgpu_query_info_test(void) - { - amdgpu_query_gpu_info_test(); -@@ -267,6 +293,7 @@ static void amdgpu_query_info_test(void) - amdgpu_query_hw_info_test(AMDGPU_HW_IP_DMA); - amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); - amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); -+ amdgpu_query_heap_info_test(); - } - - static void amdgpu_memory_alloc(void) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch deleted file mode 100644 index 34cb4fd3..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch +++ /dev/null @@ -1,172 +0,0 @@ -From f639b2e37ecdcc49b4dbaf1dedac51ecabf7e20e Mon Sep 17 00:00:00 2001 -From: Jammy Zhou <Jammy.Zhou@amd.com> -Date: Tue, 10 Nov 2015 21:17:22 +0800 -Subject: [PATCH 038/117] amdgpu: reserve SVM range explicitly by clients (v3) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The SVM range is only used by OCL 2.0 now, and it shouldn't be -reserved when only other clients are used. With this change: - -amdgpu_svm_init() should be called to reserve the SVM range -amdgpu_svm_deinit() should be called to unreserve this range - -v3: fix a typo -v2: update the unit test as well - -Change-Id: Ia2495c3471a0c71c6b05fd81d84d5acfaf9a0a4c -Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> ---- - amdgpu/amdgpu.h | 21 +++++++++++++++++++++ - amdgpu/amdgpu_device.c | 3 --- - amdgpu/amdgpu_internal.h | 3 --- - amdgpu/amdgpu_vamgr.c | 4 ++-- - tests/amdgpu/basic_tests.c | 14 ++++++++++++++ - 5 files changed, 37 insertions(+), 8 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 79314fb..1db47c3 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1240,6 +1240,27 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, - uint32_t ops); - - /** -+ * Reserve the virtual address range for SVM support -+ * -+ * \param amdgpu_device_handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_svm_init(amdgpu_device_handle dev); -+ -+/** -+ * Free the virtual address range for SVM support -+ * -+ * \param amdgpu_device_handle -+ * -+ * \return -+ * -+*/ -+void amdgpu_svm_deinit(amdgpu_device_handle dev); -+ -+/** - * Commit SVM allocation in a process - * - * \param va_range_handle - \c [in] Handle of SVM allocation -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index b1a7182..b517b1a 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -130,7 +130,6 @@ static int amdgpu_get_auth(int fd, int *auth) - - static void amdgpu_device_free_internal(amdgpu_device_handle dev) - { -- amdgpu_svm_vamgr_deinit(dev); - amdgpu_vamgr_deinit(&dev->vamgr_32); - amdgpu_vamgr_deinit(&dev->vamgr); - util_hash_table_destroy(dev->bo_flink_names); -@@ -267,8 +266,6 @@ int amdgpu_device_initialize(int fd, - amdgpu_vamgr_init(&dev->vamgr_32, start, max, - dev->dev_info.virtual_address_alignment); - -- amdgpu_svm_vamgr_init(dev); -- - *major_version = dev->major_version; - *minor_version = dev->minor_version; - *device_handle = dev; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index caec2a2..3760f94 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -153,9 +153,6 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - drm_private void - amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); - --int amdgpu_svm_vamgr_init(struct amdgpu_device *dev); --void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev); -- - drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); - - drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 64a3543..973274d 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -317,7 +317,7 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) - * <0 - Negative POSIX Error code - * - */ --int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) -+int amdgpu_svm_init(amdgpu_device_handle dev) - { - uint64_t start; - uint64_t end; -@@ -401,7 +401,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) - return ret; - } - --void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) -+void amdgpu_svm_deinit(amdgpu_device_handle dev) - { - if (atomic_dec_and_test(&vamgr_svm.refcount)) { - /* This is the last device referencing SVM. */ -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index ec68dac..408a432 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -1265,6 +1265,9 @@ static void amdgpu_svm_test(void) - uint64_t end; - int i; - -+ r = amdgpu_svm_init(device_handle); -+ CU_ASSERT_EQUAL(r, 0); -+ - r = amdgpu_va_range_query(device_handle, - amdgpu_gpu_va_range_svm, &start, &end); - CU_ASSERT_EQUAL(r, 0); -@@ -1299,6 +1302,8 @@ static void amdgpu_svm_test(void) - r = amdgpu_va_range_free(va_handle[i]); - CU_ASSERT_EQUAL(r, 0); - } -+ -+ amdgpu_svm_deinit(device_handle); - } - - static void amdgpu_multi_svm_test(void) -@@ -1315,11 +1320,17 @@ static void amdgpu_multi_svm_test(void) - device_handles[0] = device_handle; - num_devices = amdgpu_num_devices(); - -+ r = amdgpu_svm_init(device_handles[0]); -+ CU_ASSERT_EQUAL(r, 0); -+ - for (i = 1; i < num_devices; i++) - if (drm_amdgpu[i] > 0) { - r = amdgpu_device_initialize(drm_amdgpu[i], &major_version, - &minor_version, &device_handles[i]); - CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_svm_init(device_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); - } - - amdgpu_vprintf("\n"); -@@ -1362,7 +1373,10 @@ static void amdgpu_multi_svm_test(void) - - for (i = 1; i < num_devices; i++) - if (drm_amdgpu[i] > 0) { -+ amdgpu_svm_deinit(device_handles[i]); - r = amdgpu_device_deinitialize(device_handles[i]); - CU_ASSERT_EQUAL(r, 0); - } -+ -+ amdgpu_svm_deinit(device_handles[0]); - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch deleted file mode 100644 index 371bc6de..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 3fb478b00e1f3123f4c9b1efbd4a7e804679b64b Mon Sep 17 00:00:00 2001 -From: Jammy Zhou <Jammy.Zhou@amd.com> -Date: Mon, 9 Nov 2015 12:42:52 +0800 -Subject: [PATCH 039/117] amdgpu: expose the AMDGPU_GEM_CREATE_NO_EVICT flag - -With this flag specified, the buffer will be pinned at allocation time. - -Change-Id: Ibb75f27dc79ca678e58590b188a749b762429fce -Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index f97acd1..1df0d9c 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -75,6 +75,8 @@ - #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) - /* Flag that USWC attributes should be used for GTT */ - #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -+/* Flag that the memory allocation should be pinned */ -+#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 3) - - struct drm_amdgpu_gem_create_in { - /** the requested memory size */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0040-amdgpu-add-query-amdgpu-capability-defination.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0040-amdgpu-add-query-amdgpu-capability-defination.patch deleted file mode 100644 index 1da9f9ea..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0040-amdgpu-add-query-amdgpu-capability-defination.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 813fc7d4532d77b0fc46c0f80813fb63c86e8097 Mon Sep 17 00:00:00 2001 -From: jimqu <Jim.Qu@amd.com> -Date: Mon, 16 Nov 2015 15:13:00 +0800 -Subject: [PATCH 040/117] amdgpu: add query amdgpu capability defination - -Signed-off-by: JimQu <Jim.Qu@amd.com> - -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> - -Change-Id: Id615b06a59bc5a49aa8f7c7e658eb1bb1f318bd6 ---- - include/drm/amdgpu_drm.h | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 1df0d9c..981b346 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -508,6 +508,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+/* gpu capability */ -+#define AMDGPU_INFO_CAPABILITY 0x50 - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -569,6 +571,10 @@ struct drm_amdgpu_info { - uint32_t aperture; - uint32_t _pad; - } virtual_range; -+ -+ struct { -+ uint64_t type; -+ } query_capability; - }; - }; - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch deleted file mode 100644 index 1194b8e8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 231f4155aba4fcef48298c44d02047db111885ca Mon Sep 17 00:00:00 2001 -From: jimqu <Jim.Qu@amd.com> -Date: Mon, 16 Nov 2015 15:15:14 +0800 -Subject: [PATCH 041/117] amdgpu: add query amdgpu pinning memory capability - defination - -Signed-off-by: JimQu <Jim.Qu@amd.com> - -Change-Id: I5f0095ef0cb550fad67aca222009b71634d79b4b -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 981b346..4ddb649 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -510,6 +510,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -+ /* query pin memory capability */ -+ #define AMDGPU_INFO_CAPABILITY_PIN_MEM 0x01 - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0042-amdgpu-add-amdgpu_query_capability-interface.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0042-amdgpu-add-amdgpu_query_capability-interface.patch deleted file mode 100644 index 61db1a40..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0042-amdgpu-add-amdgpu_query_capability-interface.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 8b7c227c3cb6429e2c53fd8375c415021626886d Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Mon, 16 Nov 2015 18:06:16 +0800 -Subject: [PATCH 042/117] amdgpu: add amdgpu_query_capability interface - -Change-Id: Iffdd157e411c19f4d9980994dad6952b183ef1a5 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Jim Qu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu.h | 18 ++++++++++++++++++ - amdgpu/amdgpu_gpu_info.c | 6 ++++++ - include/drm/amdgpu_drm.h | 8 +++----- - 3 files changed, 27 insertions(+), 5 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 1db47c3..baae113 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -62,6 +62,11 @@ struct drm_amdgpu_info_hw_ip; - */ - #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) - -+/** -+ * Used in amdgpu_query_capability(), meaning if pin feature is enabled. -+ */ -+#define AMDGPU_CAP_PIN_MEM (1 << 0) -+ - /*--------------------------------------------------------------------------*/ - /* ----------------------------- Enums ------------------------------------ */ - /*--------------------------------------------------------------------------*/ -@@ -1070,6 +1075,19 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - unsigned size, void *value); - - /** -+ * Query hardware or driver capabilities. -+ * -+ * -+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -+ * \param value - \c [out] Pointer to the return value. -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX error code -+ * -+*/ -+int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value); -+ -+/** - * Query information about GDS - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 73d8d11..133952d 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -48,6 +48,12 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - sizeof(struct drm_amdgpu_info)); - } - -+int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value) -+{ -+ return amdgpu_query_info(dev, AMDGPU_INFO_CAPABILITY, -+ sizeof(uint64_t), value); -+} -+ - int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, - int32_t *result) - { -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 4ddb649..050e7fe 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -508,10 +508,11 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+ - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -- /* query pin memory capability */ -- #define AMDGPU_INFO_CAPABILITY_PIN_MEM 0x01 -+/* query pin memory capability */ -+#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -574,9 +575,6 @@ struct drm_amdgpu_info { - uint32_t _pad; - } virtual_range; - -- struct { -- uint64_t type; -- } query_capability; - }; - }; - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch deleted file mode 100644 index 4e0bc1ae..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch +++ /dev/null @@ -1,143 +0,0 @@ -From c8b1ce6872eaf7793065b0e4ed308b2a92032f95 Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 26 Nov 2015 17:01:07 +0800 -Subject: [PATCH 043/117] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -userspace needs to know if the user memory is from BO or malloc. - -Change-Id: Ie2dbc13f1c02bc0a996f64f9db83a21da63c1d70 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 24 ++++++++++++++++++++++++ - amdgpu/amdgpu_bo.c | 37 +++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 12 ++++++++++++ - 3 files changed, 73 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index baae113..4925056 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -672,6 +672,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - amdgpu_bo_handle *buf_handle); - - /** -+ * Validate if the user memory comes from BO -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param cpu - [in] CPU address of user allocated memory which we -+ * want to map to GPU address space (make GPU accessible) -+ * (This address must be correctly aligned). -+ * \param size - [in] Size of allocation (must be correctly aligned) -+ * \param buf_handle - [out] Buffer handle for the userptr memory -+ * if the user memory is not from BO, the buf_handle will be NULL. -+ * \param offset_in_bo - [out] offset in this BO for this user memory -+ * -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, -+ void *cpu, -+ uint64_t size, -+ amdgpu_bo_handle *buf_handle, -+ uint64_t *offset_in_bo); -+ -+ -+/** - * Free previosuly allocated memory - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index d30fd1e..ff78039 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -529,6 +529,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, - } - } - -+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, -+ void *cpu, -+ uint64_t size, -+ amdgpu_bo_handle *buf_handle, -+ uint64_t *offset_in_bo) -+{ -+ int r; -+ struct amdgpu_bo *bo; -+ struct drm_amdgpu_gem_find_bo args; -+ -+ args.addr = (uintptr_t)cpu; -+ args.size = size; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_FIND_BO, -+ &args, sizeof(args)); -+ if (r) -+ return r; -+ if (args.handle == 0) -+ return -EINVAL; -+ bo = util_hash_table_get(dev->bo_handles, -+ (void*)(uintptr_t)args.handle); -+ if (!bo) { -+ bo = calloc(1, sizeof(struct amdgpu_bo)); -+ if (!bo) -+ return -ENOMEM; -+ atomic_set(&bo->refcount, 1); -+ bo->dev = dev; -+ bo->alloc_size = size; -+ bo->handle = args.handle; -+ } else -+ atomic_inc(&bo->refcount); -+ -+ *buf_handle = bo; -+ *offset_in_bo = args.offset; -+ return r; -+} -+ -+ - int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - void *cpu, - uint64_t size, -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 050e7fe..e07904c 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -47,6 +47,7 @@ - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 -+#define DRM_AMDGPU_GEM_FIND_BO 0x13 - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -61,6 +62,7 @@ - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) -+#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -201,6 +203,16 @@ struct drm_amdgpu_gem_userptr { - uint32_t handle; - }; - -+struct drm_amdgpu_gem_find_bo { -+ uint64_t addr; -+ uint64_t size; -+ uint32_t flags; -+ /* Resulting GEM handle */ -+ uint32_t handle; -+ /* offset in bo */ -+ uint64_t offset; -+}; -+ - /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ - #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 - #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0044-amdgpu-support-alloc-va-from-range.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0044-amdgpu-support-alloc-va-from-range.patch deleted file mode 100644 index 61ce6f88..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0044-amdgpu-support-alloc-va-from-range.patch +++ /dev/null @@ -1,265 +0,0 @@ -From 6cac1ca7faba752980ae58e4b10aef5b89c097dd Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 4 Feb 2016 09:42:45 +0800 -Subject: [PATCH 044/117] amdgpu: support alloc va from range - -Change-Id: Ib41ca6a99ce500fe783a1b1650f25be9cebec83a -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu.h | 51 +++++++++++++++ - amdgpu/amdgpu_vamgr.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 220 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 4925056..455f388 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1226,6 +1226,57 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - uint64_t flags); - - /** -+ * Allocate virtual address range in client defined range -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param va_range_type - \c [in] Type of MC va range from which to allocate -+ * \param size - \c [in] Size of range. Size must be correctly* aligned. -+ * It is client responsibility to correctly aligned size based on the future -+ * usage of allocated range. -+ * \param va_base_alignment - \c [in] Overwrite base address alignment -+ * requirement for GPU VM MC virtual -+ * address assignment. Must be multiple of size alignments received as -+ * 'amdgpu_buffer_size_alignments'. -+ * If 0 use the default one. -+ * \param va_base_required - \c [in] Specified required va base address. -+ * If 0 then library choose available one between [va_base_min, va_base_max]. -+ * If !0 value will be passed and those value already "in use" then -+ * corresponding error status will be returned. -+ * \param va_base_min- \c [in] Specified required va range min address. -+ * valid if va_base_required is 0 -+ * \param va_base_max - \c [in] Specified required va range max address. -+ * valid if va_base_required is 0 -+ * \param va_base_allocated - \c [out] On return: Allocated VA base to be used -+ * by client. -+ * \param va_range_handle - \c [out] On return: Handle assigned to allocation -+ * \param flags - \c [in] flags for special VA range -+ * -+ * \return 0 on success\n -+ * >0 - AMD specific error code\n -+ * <0 - Negative POSIX Error code -+ * -+ * \notes \n -+ * It is client responsibility to correctly handle VA assignments and usage. -+ * Neither kernel driver nor libdrm_amdpgu are able to prevent and -+ * detect wrong va assignemnt. -+ * -+ * It is client responsibility to correctly handle multi-GPU cases and to pass -+ * the corresponding arrays of all devices handles where corresponding VA will -+ * be used. -+ * -+*/ -+int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, -+ enum amdgpu_gpu_va_range va_range_type, -+ uint64_t size, -+ uint64_t va_base_alignment, -+ uint64_t va_base_required, -+ uint64_t va_range_min, -+ uint64_t va_range_max, -+ uint64_t *va_base_allocated, -+ amdgpu_va_handle *va_range_handle, -+ uint64_t flags); -+ -+/** - * Free previously allocated virtual address range - * - * -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 973274d..82653e9 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -169,6 +169,94 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - return offset; - } - -+static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint64_t size, -+ uint64_t alignment, uint64_t range_min, uint64_t range_max) -+{ -+ struct amdgpu_bo_va_hole *hole, *n; -+ uint64_t offset = 0, waste = 0; -+ -+ if (mgr->va_min >= range_max || -+ mgr->va_max <= range_min) -+ return AMDGPU_INVALID_VA_ADDRESS; -+ -+ alignment = MAX2(alignment, mgr->va_alignment); -+ size = ALIGN(size, mgr->va_alignment); -+ -+ pthread_mutex_lock(&mgr->bo_va_mutex); -+ /* TODO: using more appropriate way to track the holes */ -+ /* first look for a hole */ -+ LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { -+ if (hole->offset > range_max || -+ hole->offset + hole->size < range_min || -+ (hole->offset > range_min && hole->offset + size > range_max) || -+ (hole->offset < range_min && range_min + size > hole->offset + hole->size) || -+ hole->size < size) -+ continue; -+ offset = hole->offset; -+ waste = offset % alignment; -+ waste = waste ? alignment - waste : 0; -+ offset += waste; -+ if (offset >= (hole->offset + hole->size)) { -+ continue; -+ } -+ -+ if (!waste && hole->size == size) { -+ offset = hole->offset; -+ list_del(&hole->list); -+ free(hole); -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+ } -+ if ((hole->size - waste) > size) { -+ if (waste) { -+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); -+ n->size = waste; -+ n->offset = hole->offset; -+ list_add(&n->list, &hole->list); -+ } -+ hole->size -= (size + waste); -+ hole->offset += size + waste; -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+ } -+ if ((hole->size - waste) == size) { -+ hole->size = waste; -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+ } -+ } -+ -+ if (mgr->va_offset > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } else if (mgr->va_offset > range_min) { -+ offset = mgr->va_offset; -+ waste = offset % alignment; -+ waste = waste ? alignment - waste : 0; -+ if (offset + waste + size > range_max) { -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return AMDGPU_INVALID_VA_ADDRESS; -+ } -+ } else { -+ offset = mgr->va_offset; -+ waste = range_min % alignment; -+ waste = waste ? alignment - waste : 0; -+ waste += range_min - offset ; -+ } -+ -+ if (waste) { -+ n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); -+ n->size = waste; -+ n->offset = offset; -+ list_add(&n->list, &mgr->va_holes); -+ } -+ -+ offset += waste; -+ mgr->va_offset = size + offset; -+ pthread_mutex_unlock(&mgr->bo_va_mutex); -+ return offset; -+} -+ - drm_private void - amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) - { -@@ -294,6 +382,87 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, - return 0; - } - -+static int _amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, -+ enum amdgpu_gpu_va_range va_range_type, -+ uint64_t size, -+ uint64_t va_base_alignment, -+ uint64_t va_range_min, -+ uint64_t va_range_max, -+ uint64_t *va_base_allocated, -+ amdgpu_va_handle *va_range_handle, -+ uint64_t flags) -+{ -+ struct amdgpu_bo_va_mgr *vamgr; -+ -+ if (amdgpu_gpu_va_range_svm == va_range_type) { -+ vamgr = &vamgr_svm; -+ if (!vamgr->valid) -+ return -EINVAL; -+ } -+ else if (flags & AMDGPU_VA_RANGE_32_BIT) -+ vamgr = &dev->vamgr_32; -+ else -+ vamgr = &dev->vamgr; -+ -+ va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); -+ size = ALIGN(size, vamgr->va_alignment); -+ -+ *va_base_allocated = amdgpu_vamgr_find_va_in_range(vamgr, size, -+ va_base_alignment, va_range_min, va_range_max); -+ -+ if (!(flags & AMDGPU_VA_RANGE_32_BIT) && -+ (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { -+ /* fallback to 32bit address */ -+ vamgr = &dev->vamgr_32; -+ *va_base_allocated = amdgpu_vamgr_find_va_in_range(vamgr, size, -+ va_base_alignment, va_range_min, va_range_max); -+ } -+ -+ if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) { -+ struct amdgpu_va* va; -+ va = calloc(1, sizeof(struct amdgpu_va)); -+ if(!va){ -+ amdgpu_vamgr_free_va(vamgr, *va_base_allocated, size); -+ return -ENOMEM; -+ } -+ va->dev = dev; -+ va->address = *va_base_allocated; -+ va->size = size; -+ va->range = va_range_type; -+ va->vamgr = vamgr; -+ *va_range_handle = va; -+ } else { -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, -+ enum amdgpu_gpu_va_range va_range_type, -+ uint64_t size, -+ uint64_t va_base_alignment, -+ uint64_t va_base_required, -+ uint64_t va_range_min, -+ uint64_t va_range_max, -+ uint64_t *va_base_allocated, -+ amdgpu_va_handle *va_range_handle, -+ uint64_t flags) -+{ -+ if (va_base_required) -+ return amdgpu_va_range_alloc(dev, va_range_type, -+ size, va_base_alignment, -+ va_base_required, va_base_allocated, -+ va_range_handle, flags); -+ else -+ return _amdgpu_va_range_alloc_in_range(dev, -+ va_range_type, size, -+ va_base_alignment, -+ va_range_min, va_range_max, -+ va_base_allocated, -+ va_range_handle, flags); -+} -+ - int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) - { - if(!va_range_handle || !va_range_handle->address) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0045-tests-amdgpu-add-alloc-va-from-range-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0045-tests-amdgpu-add-alloc-va-from-range-test.patch deleted file mode 100644 index fe892fc5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0045-tests-amdgpu-add-alloc-va-from-range-test.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 9622440df581fd23d8dbf5fb2188b1fdad524b6f Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 4 Feb 2016 09:54:32 +0800 -Subject: [PATCH 045/117] tests/amdgpu: add alloc va from range test - -Change-Id: I22fa0255ad8f0b7e881a6d4d2de6a054ce3572db -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 408a432..78388a9 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -51,6 +51,7 @@ static void amdgpu_userptr_test(void); - static void amdgpu_semaphore_test(void); - static void amdgpu_svm_test(void); - static void amdgpu_multi_svm_test(void); -+static void amdgpu_va_range_test(void); - - CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, -@@ -63,6 +64,7 @@ CU_TestInfo basic_tests[] = { - { "SW semaphore Test", amdgpu_semaphore_test }, - { "SVM Test", amdgpu_svm_test }, - { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, -+ { "VA range Test", amdgpu_va_range_test}, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) -@@ -1380,3 +1382,55 @@ static void amdgpu_multi_svm_test(void) - - amdgpu_svm_deinit(device_handles[0]); - } -+ -+#define VA_RANGE_TEST_CNT 66 -+#define VA_RANGE_TEST_INT_BEL_CNT 20 -+#define VA_RANGE_TEST_INT_ABO_CNT 20 -+static void amdgpu_va_range_test(void) -+{ -+ amdgpu_va_handle va_handles[VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT]; -+ uint64_t va; -+ int i, r; -+ -+ amdgpu_vprintf("\n"); -+ amdgpu_vprintf(" Testing to alloc and free VA in user defined range.\n"); -+ memset(va_handles, 0, sizeof(va_handles)); -+ for (i = 0; i < VA_RANGE_TEST_CNT; i++) { -+ r = amdgpu_va_range_alloc_in_range(device_handle, -+ amdgpu_gpu_va_range_general, -+ 0x1000000, 9, 0, -+ 0x800000000, 0x840000000, -+ &va, &va_handles[i], 0); -+ amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); -+ if (!r) -+ amdgpu_vprintf(" alloc on addr %#llx\n", va); -+ CU_ASSERT_TRUE((r == 0) || -+ (r && i>=(0x840000000-0x800000000)/0x1000000)); -+ } -+ for (i = VA_RANGE_TEST_CNT; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT; i++) { -+ r = amdgpu_va_range_alloc_in_range(device_handle, -+ amdgpu_gpu_va_range_general, -+ 0x1000000, 9, 0, -+ 0x600000000, 0x840000000, -+ &va, &va_handles[i], 0); -+ amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); -+ if (!r) -+ amdgpu_vprintf(" alloc on addr %#llx\n", va); -+ CU_ASSERT_TRUE (r == 0 && va <=0x800000000); -+ } -+ for (i = VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT; i++) { -+ r = amdgpu_va_range_alloc_in_range(device_handle, -+ amdgpu_gpu_va_range_general, -+ 0x1000000, 9, 0, -+ 0x800000000, 0x940000000, -+ &va, &va_handles[i], 0); -+ amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); -+ if (!r) -+ amdgpu_vprintf(" alloc on addr %#llx\n", va); -+ CU_ASSERT_TRUE (r == 0 && va >= 0x840000000); -+ } -+ for (i = 0; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT; i++) { -+ r = amdgpu_va_range_free(va_handles[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0046-amdgpu-fix-for-submition-with-no-ibs.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0046-amdgpu-fix-for-submition-with-no-ibs.patch deleted file mode 100644 index 0af5f509..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0046-amdgpu-fix-for-submition-with-no-ibs.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 8494f5ecd3dae4266805c809f894495a29e73b38 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Thu, 4 Feb 2016 13:52:22 +0800 -Subject: [PATCH 046/117] amdgpu: fix for submition with no ibs - -Change-Id: I0b582ff0021c02fad9d77d51971a48d9ee5d1146 -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Acked-by: Alex Deucher <Alexander.Deucher@amd.com> ---- - amdgpu/amdgpu_cs.c | 8 ++++++++ - amdgpu/amdgpu_internal.h | 1 + - 2 files changed, 9 insertions(+) - -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 896352b..0c9bcc4 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -190,6 +190,10 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, - return -EINVAL; - if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT) - return -EINVAL; -+ if (ibs_request->number_of_ibs == 0) { -+ ibs_request->seq_no = AMDGPU_NULL_SUBMIT_SEQ; -+ return 0; -+ } - user_fence = (ibs_request->fence_info.handle != NULL); - - size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1; -@@ -422,6 +426,10 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - return -EINVAL; - if (fence->ring >= AMDGPU_CS_MAX_RINGS) - return -EINVAL; -+ if (fence->fence == AMDGPU_NULL_SUBMIT_SEQ) { -+ *expired = true; -+ return 0; -+ } - - *expired = false; - -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 3760f94..1160a12 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -44,6 +44,7 @@ - #define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y)) - - #define AMDGPU_INVALID_VA_ADDRESS 0xffffffffffffffff -+#define AMDGPU_NULL_SUBMIT_SEQ 0 - - struct amdgpu_bo_va_hole { - struct list_head list; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0047-tests-amdgpu-move-va_range_test-above-svm_test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0047-tests-amdgpu-move-va_range_test-above-svm_test.patch deleted file mode 100644 index e2b547cd..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0047-tests-amdgpu-move-va_range_test-above-svm_test.patch +++ /dev/null @@ -1,32 +0,0 @@ -From c7c7f25b214b694541d69bc3fb1a096a1725d6fb Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Fri, 5 Feb 2016 13:20:27 +0800 -Subject: [PATCH 047/117] tests/amdgpu: move va_range_test above svm_test - -svm_test won't release va range at exit. va_range_test would fail as the -desired range is occupied. - -Change-Id: I36bb3c23f185baa26a383e02a87a0b02f613e2d0 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - tests/amdgpu/basic_tests.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 78388a9..b7e6270 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -62,9 +62,9 @@ CU_TestInfo basic_tests[] = { - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, - { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, - { "SW semaphore Test", amdgpu_semaphore_test }, -+ { "VA range Test", amdgpu_va_range_test}, - { "SVM Test", amdgpu_svm_test }, - { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, -- { "VA range Test", amdgpu_va_range_test}, - CU_TEST_INFO_NULL, - }; - #define BUFFER_SIZE (8 * 1024) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0048-amdgpu-add-the-function-to-get-the-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0048-amdgpu-add-the-function-to-get-the-marketing-name.patch deleted file mode 100644 index dc1572c1..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0048-amdgpu-add-the-function-to-get-the-marketing-name.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 36a9c41b7b44bc8dee072733f1fc944e4bf66703 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Fri, 4 Mar 2016 13:00:09 +0800 -Subject: [PATCH 048/117] amdgpu: add the function to get the marketing name - -Change-Id: I6031d8012531de89d604f24e1d1bd1743012f980 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu.h | 10 +++++ - amdgpu/amdgpu_asic_id.h | 116 ++++++++++++++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_device.c | 15 +++++++ - 3 files changed, 141 insertions(+) - create mode 100644 amdgpu/amdgpu_asic_id.h - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 455f388..5415bd0 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -1437,4 +1437,14 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, - */ - int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); - -+/** -+ * Get the ASIC marketing name -+ * -+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -+ * -+ * \return the constant string of the marketing name -+ * "NULL" means the ASIC is not found -+*/ -+const char *amdgpu_get_marketing_name(amdgpu_device_handle dev); -+ - #endif /* #ifdef _AMDGPU_H_ */ -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -new file mode 100644 -index 0000000..4130de6 ---- /dev/null -+++ b/amdgpu/amdgpu_asic_id.h -@@ -0,0 +1,116 @@ -+struct amdgpu_asic_id_table_t { -+ uint32_t did; -+ uint32_t rid; -+ char marketing_name[64]; -+} const amdgpu_asic_id_table [] = { -+ {0x6600, 0x0, "AMD Radeon HD 8600/8700M"}, -+ {0x6600, 0x81, "AMD Radeon (TM) R7 M370"}, -+ {0x6601, 0x0, "AMD Radeon (TM) HD 8500M/8700M"}, -+ {0x6604, 0x0, "AMD Radeon R7 M265 Series"}, -+ {0x6604, 0x81, "AMD Radeon (TM) R7 M350"}, -+ {0x6605, 0x0, "AMD Radeon R7 M260 Series"}, -+ {0x6605, 0x81, "AMD Radeon (TM) R7 M340"}, -+ {0x6606, 0x0, "AMD Radeon HD 8790M"}, -+ {0x6607, 0x0, "AMD Radeon (TM) HD8530M"}, -+ {0x6608, 0x0, "AMD FirePro W2100"}, -+ {0x6610, 0x0, "AMD Radeon HD 8600 Series"}, -+ {0x6610, 0x81, "AMD Radeon (TM) R7 350"}, -+ {0x6610, 0x83, "AMD Radeon (TM) R5 340"}, -+ {0x6611, 0x0, "AMD Radeon HD 8500 Series"}, -+ {0x6613, 0x0, "AMD Radeon HD 8500 series"}, -+ {0x6617, 0xC7, "AMD Radeon R7 240 Series"}, -+ {0x6640, 0x0, "AMD Radeon HD 8950"}, -+ {0x6640, 0x80, "AMD Radeon (TM) R9 M380"}, -+ {0x6646, 0x0, "AMD Radeon R9 M280X"}, -+ {0x6646, 0x80, "AMD Radeon (TM) R9 M385"}, -+ {0x6647, 0x0, "AMD Radeon R9 M270X"}, -+ {0x6647, 0x80, "AMD Radeon (TM) R9 M380"}, -+ {0x6649, 0x0, "AMD FirePro W5100"}, -+ {0x6658, 0x0, "AMD Radeon R7 200 Series"}, -+ {0x665C, 0x0, "AMD Radeon HD 7700 Series"}, -+ {0x665D, 0x0, "AMD Radeon R7 200 Series"}, -+ {0x665F, 0x81, "AMD Radeon (TM) R7 300 Series"}, -+ {0x6660, 0x0, "AMD Radeon HD 8600M Series"}, -+ {0x6660, 0x81, "AMD Radeon (TM) R5 M335"}, -+ {0x6660, 0x83, "AMD Radeon (TM) R5 M330"}, -+ {0x6663, 0x0, "AMD Radeon HD 8500M Series"}, -+ {0x6663, 0x83, "AMD Radeon (TM) R5 M320"}, -+ {0x6664, 0x0, "AMD Radeon R5 M200 Series"}, -+ {0x6665, 0x0, "AMD Radeon R5 M200 Series"}, -+ {0x6665, 0x83, "AMD Radeon (TM) R5 M320"}, -+ {0x6667, 0x0, "AMD Radeon R5 M200 Series"}, -+ {0x666F, 0x0, "AMD Radeon HD 8500M"}, -+ {0x6780, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"}, -+ {0x678A, 0x0, "ATI FirePro V (FireGL V) Graphics Adapter"}, -+ {0x6798, 0x0, "AMD Radeon HD 7900 Series"}, -+ {0x679A, 0x0, "AMD Radeon HD 7900 Series"}, -+ {0x679B, 0x0, "AMD Radeon HD 7900 Series"}, -+ {0x679E, 0x0, "AMD Radeon HD 7800 Series"}, -+ {0x67A0, 0x0, "HAWAII XTGL (67A0)"}, -+ {0x67A1, 0x0, "HAWAII GL40 (67A1)"}, -+ {0x67B0, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67B0, 0x80, "AMD Radeon (TM) R9 390 Series"}, -+ {0x67B1, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67B1, 0x80, "AMD Radeon (TM) R9 390 Series"}, -+ {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x6800, 0x0, "AMD Radeon HD 7970M"}, -+ {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, -+ {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, -+ {0x6809, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, -+ {0x6810, 0x0, "AMD Radeon(TM) HD 8800 Series"}, -+ {0x6810, 0x81, "AMD Radeon (TM) R7 370 Series"}, -+ {0x6811, 0x0, "AMD Radeon(TM) HD8800 Series"}, -+ {0x6811, 0x81, "AMD Radeon (TM) R7 300 Series"}, -+ {0x6818, 0x0, "AMD Radeon HD 7800 Series"}, -+ {0x6819, 0x0, "AMD Radeon HD 7800 Series"}, -+ {0x6820, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x6820, 0x81, "AMD Radeon (TM) R9 M375"}, -+ {0x6820, 0x83, "AMD Radeon (TM) R9 M375X"}, -+ {0x6821, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x6821, 0x87, "AMD Radeon (TM) R7 M380"}, -+ {0x6821, 0x83, "AMD Radeon R9 (TM) M370X"}, -+ {0x6822, 0x0, "AMD Radeon E8860"}, -+ {0x6823, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x6825, 0x0, "AMD Radeon HD 7800M Series"}, -+ {0x6827, 0x0, "AMD Radeon HD 7800M Series"}, -+ {0x6828, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, -+ {0x682B, 0x0, "AMD Radeon HD 8800M Series"}, -+ {0x682B, 0x87, "AMD Radeon (TM) R9 M360"}, -+ {0x682C, 0x0, "AMD FirePro W4100"}, -+ {0x682D, 0x0, "AMD Radeon HD 7700M Series"}, -+ {0x682F, 0x0, "AMD Radeon HD 7700M Series"}, -+ {0x6835, 0x0, "AMD Radeon R7 Series / HD 9000 Series"}, -+ {0x6837, 0x0, "AMD Radeon HD7700 Series"}, -+ {0x683D, 0x0, "AMD Radeon HD 7700 Series"}, -+ {0x683F, 0x0, "AMD Radeon HD 7700 Series"}, -+ {0x6900, 0x0, "AMD Radeon R7 M260"}, -+ {0x6900, 0x81, "AMD Radeon (TM) R7 M360"}, -+ {0x6900, 0x83, "AMD Radeon (TM) R7 M340"}, -+ {0x6901, 0x0, "AMD Radeon R5 M255"}, -+ {0x6907, 0x0, "AMD Radeon R5 M255"}, -+ {0x6907, 0x87, "AMD Radeon (TM) R5 M315"}, -+ {0x6920, 0x0, "AMD RADEON R9 M395X"}, -+ {0x6920, 0x1, "AMD RADEON R9 M390X"}, -+ {0x6921, 0x0, "AMD Radeon R9 M295X"}, -+ {0x6929, 0x0, "AMD FirePro S7150"}, -+ {0x692B, 0x0, "AMD FirePro W7100"}, -+ {0x6938, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x6938, 0xF0, "AMD Radeon R9 200 Series"}, -+ {0x6938, 0xF1, "AMD Radeon (TM) R9 380 Series"}, -+ {0x6939, 0xF0, "AMD Radeon R9 200 Series"}, -+ {0x6939, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x6939, 0xF1, "AMD Radeon (TM) R9 380 Series"}, -+ {0x7300, 0xC8, "AMD Radeon (TM) R9 Fury Series"}, -+ {0x7300, 0xCB, "AMD Radeon (TM) R9 Fury Series"}, -+ {0x7300, 0xCA, "AMD Radeon (TM) R9 Fury Series"}, -+ {0x9874, 0xC4, "AMD Radeon R7 Graphics"}, -+ {0x9874, 0xC5, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0xC6, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0xC7, "AMD Radeon R5 Graphics"}, -+ {0x9874, 0x81, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0x87, "AMD Radeon R5 Graphics"}, -+ {0x9874, 0x85, "AMD Radeon R6 Graphics"}, -+ {0x9874, 0x84, "AMD Radeon R7 Graphics"}, -+ -+ {0x0000, 0x0, "\0"}, -+}; -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index b517b1a..8f1f781 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -44,6 +44,7 @@ - #include "amdgpu_internal.h" - #include "util_hash_table.h" - #include "util_math.h" -+#include "amdgpu_asic_id.h" - - #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) - #define UINT_TO_PTR(x) ((void *)((intptr_t)(x))) -@@ -293,3 +294,17 @@ int amdgpu_device_deinitialize(amdgpu_device_handle dev) - amdgpu_device_reference(&dev, NULL); - return 0; - } -+ -+const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) -+{ -+ const struct amdgpu_asic_id_table_t *t = amdgpu_asic_id_table; -+ -+ while (t->did) { -+ if ((t->did == dev->info.asic_id) && -+ (t->rid == dev->info.pci_rev_id)) -+ return t->marketing_name; -+ t++; -+ } -+ -+ return NULL; -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch deleted file mode 100644 index dc93abd6..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch +++ /dev/null @@ -1,59 +0,0 @@ -From de7234f8ae699b3c78043a19e32fc7a9596fbeac Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Tue, 8 Mar 2016 17:57:06 +0800 -Subject: [PATCH 049/117] tests/amdgpu: remove none amdgpu devices for hybrid - GPU platforms -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I5991e74ddea212bde4954924de12b26c1ac54936 -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/amdgpu_test.c | 22 +++++++++++++++++++++- - 1 file changed, 21 insertions(+), 1 deletion(-) - -diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c -index 46f55c7..dccf221 100644 ---- a/tests/amdgpu/amdgpu_test.c -+++ b/tests/amdgpu/amdgpu_test.c -@@ -136,7 +136,7 @@ static const char options[] = "hlvws:t:"; - int main(int argc, char **argv) - { - int c; /* Character received from getopt */ -- int i = 0; -+ int i = 0, j = 0; - int suite_id = -1; /* By default run everything */ - int test_id = -1; /* By default run all tests in the suite */ - CU_pSuite pSuite = NULL; -@@ -210,6 +210,26 @@ int main(int argc, char **argv) - } - drmFreeDevices(devices, num_devices); - -+ /* remove none amdgpu devices */ -+ for (i = 0; i < num_devices; i++) { -+ drmVersionPtr retval = drmGetVersion(drm_amdgpu[i]); -+ if (retval && !strcmp("amdgpu", retval->name)) { -+ if (i != j) { -+ drm_amdgpu[j] = drm_amdgpu[i]; -+ drm_amdgpu[i] = -1; -+ } -+ j++; -+ } -+ else { -+ close(drm_amdgpu[i]); -+ drm_amdgpu[i] = -1; -+ } -+ } -+ if (drm_amdgpu[0] < 0) { -+ perror("no amdgpu device found"); -+ exit(EXIT_FAILURE); -+ } -+ - /** Display version of DRM driver */ - drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch deleted file mode 100644 index b6221c08..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch +++ /dev/null @@ -1,60 +0,0 @@ -From c246e19bebdefd47f4d9f676391722ca5c98f2c2 Mon Sep 17 00:00:00 2001 -From: Sonny Jiang <sonny.jiang@amd.com> -Date: Thu, 18 Feb 2016 10:59:56 -0500 -Subject: [PATCH 050/117] amdgpu/tests: Fiji VCE is one instance - -Change-Id: I7a00160cfa3510ae072964981c921bf49c707155 -Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> -Reviewed-by: Leo Liu <leo.liu@amd.com> ---- - tests/amdgpu/vce_tests.c | 20 ++++++++++++-------- - 1 file changed, 12 insertions(+), 8 deletions(-) - -diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c -index 32fc001..4915170 100644 ---- a/tests/amdgpu/vce_tests.c -+++ b/tests/amdgpu/vce_tests.c -@@ -65,6 +65,7 @@ static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; - static uint32_t family_id; -+static uint32_t vce_harvest_config; - - static amdgpu_context_handle context_handle; - static amdgpu_bo_handle ib_handle; -@@ -97,6 +98,7 @@ int suite_vce_tests_init(void) - return CUE_SINIT_FAILED; - - family_id = device_handle->info.family_id; -+ vce_harvest_config = device_handle->info.vce_harvest_config; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) -@@ -440,14 +442,16 @@ static void amdgpu_cs_vce_encode(void) - check_result(&enc); - - /* two instances */ -- enc.two_instance = true; -- vce_taskinfo[2] = 0x83; -- vce_taskinfo[4] = 1; -- amdgpu_cs_vce_encode_idr(&enc); -- vce_taskinfo[2] = 0xffffffff; -- vce_taskinfo[4] = 2; -- amdgpu_cs_vce_encode_p(&enc); -- check_result(&enc); -+ if (vce_harvest_config == 0) { -+ enc.two_instance = true; -+ vce_taskinfo[2] = 0x83; -+ vce_taskinfo[4] = 1; -+ amdgpu_cs_vce_encode_idr(&enc); -+ vce_taskinfo[2] = 0xffffffff; -+ vce_taskinfo[4] = 2; -+ amdgpu_cs_vce_encode_p(&enc); -+ check_result(&enc); -+ } - } else { - vce_taskinfo[3] = 3; - vce_encode[16] = 0; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch deleted file mode 100644 index 889375a3..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 398bbb4523b13a9752785dd527e530cb07026762 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Mon, 16 May 2016 09:33:27 +0800 -Subject: [PATCH 052/117] amdgpu: [hybrid] update the gpu marketing name table - -Change-Id: I4e680fa71714f886e233e1ccdbb3a4121e7c8bc2 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Qiang Yu <Qiang.Yu@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 4130de6..c29a27e 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -22,7 +22,7 @@ struct amdgpu_asic_id_table_t { - {0x6640, 0x0, "AMD Radeon HD 8950"}, - {0x6640, 0x80, "AMD Radeon (TM) R9 M380"}, - {0x6646, 0x0, "AMD Radeon R9 M280X"}, -- {0x6646, 0x80, "AMD Radeon (TM) R9 M385"}, -+ {0x6646, 0x80, "AMD Radeon (TM) R9 M470X"}, - {0x6647, 0x0, "AMD Radeon R9 M270X"}, - {0x6647, 0x80, "AMD Radeon (TM) R9 M380"}, - {0x6649, 0x0, "AMD FirePro W5100"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0053-Hybrid-Version-16.30.2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0053-Hybrid-Version-16.30.2.patch deleted file mode 100644 index e515dff4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0053-Hybrid-Version-16.30.2.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 831fa03789a7a929b97ddbbe416b9cf96171c76a Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Tue, 17 May 2016 11:05:20 +0800 -Subject: [PATCH 053/117] Hybrid Version: 16.30.2 - -Change-Id: I554db242c9d58483fd197962d75e2d9512ff9390 ---- - .version.hybrid | 3 +++ - 1 file changed, 3 insertions(+) - create mode 100644 .version.hybrid - -diff --git a/.version.hybrid b/.version.hybrid -new file mode 100644 -index 0000000..1385b45 ---- /dev/null -+++ b/.version.hybrid -@@ -0,0 +1,3 @@ -+HYBRID_VERSION_MAJOR = 16 -+HYBRID_VERSION_MINOR = 30 -+HYBRID_VERSION_PATCH = 2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch deleted file mode 100644 index d9a45179..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch +++ /dev/null @@ -1,41 +0,0 @@ -From f50daceb4d345174ed24a0320edf78fe738f7634 Mon Sep 17 00:00:00 2001 -From: Leo Liu <leo.liu@amd.com> -Date: Thu, 17 Mar 2016 11:30:57 -0400 -Subject: [PATCH 054/117] tests/amdgpu: add interface to adapt firmware - requirement -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Leo Liu <leo.liu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> - -Conflicts: - tests/amdgpu/cs_tests.c - -Change-Id: I6cd8e626c9936a5ad41a971daa422142cb586b89 ---- - tests/amdgpu/cs_tests.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index dfbf5af..5b487a1 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -267,8 +267,11 @@ static void amdgpu_cs_uvd_decode(void) - CU_ASSERT_EQUAL(r, 0); - - memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg)); -- if (family_id >= AMDGPU_FAMILY_VI) -+ if (family_id >= AMDGPU_FAMILY_VI) { - ptr[0x10] = 7; -+ ptr[0x98] = 0xb0; -+ ptr[0x99] = 0x1; -+ } - - ptr += 4*1024; - memset(ptr, 0, 4*1024); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch deleted file mode 100644 index 34a6eabc..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 08d04097cb45735384e9100c620e044b32779d75 Mon Sep 17 00:00:00 2001 -From: Sonny Jiang <sonny.jiang@amd.com> -Date: Thu, 12 May 2016 12:48:43 -0400 -Subject: [PATCH 055/117] tests/amdgpu: adapt to new polaris10/11 uvd fw - -Change-Id: Ibf5fc9c84f478aa038ba3b8b3a79448d7b03a196 -Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - tests/amdgpu/cs_tests.c | 48 ++++++++++++++++++++++++++++++++++++++++++------ - 1 file changed, 42 insertions(+), 6 deletions(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 5b487a1..2c9c1ae 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -43,6 +43,8 @@ static amdgpu_device_handle device_handle; - static uint32_t major_version; - static uint32_t minor_version; - static uint32_t family_id; -+static uint32_t chip_rev; -+static uint32_t chip_id; - - static amdgpu_context_handle context_handle; - static amdgpu_bo_handle ib_handle; -@@ -78,6 +80,9 @@ int suite_cs_tests_init(void) - return CUE_SINIT_FAILED; - - family_id = device_handle->info.family_id; -+ /* VI asic POLARIS10/11 have specific external_rev_id */ -+ chip_rev = device_handle->info.chip_rev; -+ chip_id = device_handle->info.chip_external_rev; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) -@@ -200,8 +205,17 @@ static void amdgpu_cs_uvd_create(void) - CU_ASSERT_EQUAL(r, 0); - - memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); -- if (family_id >= AMDGPU_FAMILY_VI) -+ if (family_id >= AMDGPU_FAMILY_VI) { - ((uint8_t*)msg)[0x10] = 7; -+ /* chip polaris 10/11 */ -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ /* dpb size */ -+ ((uint8_t*)msg)[0x28] = 0x00; -+ ((uint8_t*)msg)[0x29] = 0x94; -+ ((uint8_t*)msg)[0x2A] = 0x6B; -+ ((uint8_t*)msg)[0x2B] = 0x00; -+ } -+ } - - r = amdgpu_bo_cpu_unmap(buf_handle); - CU_ASSERT_EQUAL(r, 0); -@@ -230,8 +244,8 @@ static void amdgpu_cs_uvd_create(void) - - static void amdgpu_cs_uvd_decode(void) - { -- const unsigned dpb_size = 15923584, dt_size = 737280; -- uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, dt_addr, it_addr; -+ const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280; -+ uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr; - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; -@@ -269,8 +283,21 @@ static void amdgpu_cs_uvd_decode(void) - memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg)); - if (family_id >= AMDGPU_FAMILY_VI) { - ptr[0x10] = 7; -- ptr[0x98] = 0xb0; -- ptr[0x99] = 0x1; -+ ptr[0x98] = 0x00; -+ ptr[0x99] = 0x02; -+ /* chip polaris10/11 */ -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ /*dpb size */ -+ ptr[0x24] = 0x00; -+ ptr[0x25] = 0x94; -+ ptr[0x26] = 0x6B; -+ ptr[0x27] = 0x00; -+ /*ctx size */ -+ ptr[0x2C] = 0x00; -+ ptr[0x2D] = 0xAF; -+ ptr[0x2E] = 0x50; -+ ptr[0x2F] = 0x00; -+ } - } - - ptr += 4*1024; -@@ -301,6 +328,12 @@ static void amdgpu_cs_uvd_decode(void) - } else - bs_addr = fb_addr + 4*1024; - dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); -+ -+ if ((family_id >= AMDGPU_FAMILY_VI) && -+ (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { -+ ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); -+ } -+ - dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); - - i = 0; -@@ -309,8 +342,11 @@ static void amdgpu_cs_uvd_decode(void) - uvd_cmd(dt_addr, 0x2, &i); - uvd_cmd(fb_addr, 0x3, &i); - uvd_cmd(bs_addr, 0x100, &i); -- if (family_id >= AMDGPU_FAMILY_VI) -+ if (family_id >= AMDGPU_FAMILY_VI) { - uvd_cmd(it_addr, 0x204, &i); -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) -+ uvd_cmd(ctx_addr, 0x206, &i); -+} - ib_cpu[i++] = 0x3BC6; - ib_cpu[i++] = 0x1; - for (; i % 16; ++i) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0056-amdgpu-change-max-allocation.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0056-amdgpu-change-max-allocation.patch deleted file mode 100644 index 03ca1e92..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0056-amdgpu-change-max-allocation.patch +++ /dev/null @@ -1,41 +0,0 @@ -From fca8e6d4d9638158770745d4da5870a131190b3e Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Wed, 23 Mar 2016 10:29:00 +0800 -Subject: [PATCH 056/117] amdgpu: change max allocation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I83f8f33140609d4d2c3e54954cc2dc96eeaec6ba -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - amdgpu/amdgpu_gpu_info.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 133952d..037df32 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -260,7 +260,7 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, - else /* query total vram heap */ - info->heap_size = vram_gtt_info.vram_size; - -- info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; -+ info->max_allocation = vram_gtt_info.vram_size * 3 / 4; - - if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) - r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, -@@ -275,7 +275,7 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, - break; - case AMDGPU_GEM_DOMAIN_GTT: - info->heap_size = vram_gtt_info.gtt_size; -- info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; -+ info->max_allocation = vram_gtt_info.gtt_size * 3 / 4; - - r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, - sizeof(info->heap_usage), --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0057-amdgpu-fix-print-format-error-V2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0057-amdgpu-fix-print-format-error-V2.patch deleted file mode 100644 index 251d7200..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0057-amdgpu-fix-print-format-error-V2.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 4dacb4b7d2f3ac211a485d088e7fcc1760af38db Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Mon, 28 Mar 2016 14:30:03 +0800 -Subject: [PATCH 057/117] amdgpu: fix print format error V2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -V2: use "PRIx64" instead of llx - -Change-Id: Idf79d58abe165f26dc6bc900e10fca30ea740509 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-By: Ken Wang <Qingqing.Wang@amd.com> (V1) -Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (V2) - -Conflicts: - tests/amdgpu/basic_tests.c ---- - tests/amdgpu/basic_tests.c | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index b7e6270..f308e9a 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -28,6 +28,7 @@ - #include <stdio.h> - #include <stdlib.h> - #include <unistd.h> -+#include <inttypes.h> - #ifdef HAVE_ALLOCA_H - # include <alloca.h> - #endif -@@ -273,17 +274,17 @@ static void amdgpu_query_heap_info_test(void) - amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &info); - amdgpu_vprintf("\n Visible VRAM info...\n"); -- amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -- amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+ amdgpu_vprintf(" size: 0x%"PRIx64"\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); - amdgpu_vprintf("\n Invisible VRAM info...\n"); -- amdgpu_vprintf(" size: 0x%x\n", total_vram - info.heap_size); -- amdgpu_vprintf(" usage: 0x%x\n", total_vram_used - info.heap_usage); -+ amdgpu_vprintf(" size: 0x%"PRIx64"\n", total_vram - info.heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", total_vram_used - info.heap_usage); - - amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, - 0, &info); - amdgpu_vprintf("\n GTT info...\n"); -- amdgpu_vprintf(" size: 0x%x\n", info.heap_size); -- amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); -+ amdgpu_vprintf(" size: 0x%"PRIx64"\n", info.heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); - } - - static void amdgpu_query_info_test(void) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0058-Hybrid-Version-16.30.3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0058-Hybrid-Version-16.30.3.patch deleted file mode 100644 index ef974b1e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0058-Hybrid-Version-16.30.3.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 34ac5db6d3e1387de3e69ac3fb61e31c2e02b8f9 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Mon, 30 May 2016 11:13:54 +0800 -Subject: [PATCH 058/117] Hybrid Version: 16.30.3 - -Change-Id: I27ee52f2fa44edc3a4adfea79a0caed9560ed760 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 1385b45..4cabeed 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 30 --HYBRID_VERSION_PATCH = 2 -+HYBRID_VERSION_PATCH = 3 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch deleted file mode 100644 index 40ba2ded..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 9d50d529f35b5ec2e9300bcff55fca1da84f75ec Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Mon, 30 May 2016 21:45:47 +0800 -Subject: [PATCH 059/117] drm: fix multi GPU drmGetDevices only return one - device - -When multi GPU present, after drmFoldDuplicatedDevices -merge same busid deveces, two different devices may be -seperated by zero in local_devices[]. The for loop -should check all local_devices instead of exit when -meet a zero. - -Change-Id: I0b655f795727492bd7886cb60e07832bd9849d89 -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by Jim Qu <Jim.Qu@amd.com> ---- - xf86drm.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 5f587d9..6689f7c 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -3267,7 +3267,10 @@ int drmGetDevices(drmDevicePtr devices[], int max_devices) - drmFoldDuplicatedDevices(local_devices, node_count); - - device_count = 0; -- for (i = 0; i < node_count && local_devices[i]; i++) { -+ for (i = 0; i < node_count; i++) { -+ if (!local_devices[i]) -+ continue; -+ - if ((devices != NULL) && (device_count < max_devices)) - devices[device_count] = local_devices[i]; - else --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch deleted file mode 100644 index 42201f1f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch +++ /dev/null @@ -1,32 +0,0 @@ -From e5512b2e226abad4e1719b4de4a7427900bc9317 Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 3 Dec 2015 16:52:33 +0800 -Subject: [PATCH 061/117] amdgpu: add bo handle to hash table when cpu mapping -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Id79d98877c61510a1986d65befec6ce6713edae7 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu_bo.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index ff78039..aa0d001 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -463,7 +463,7 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - pthread_mutex_unlock(&bo->cpu_access_mutex); - return -errno; - } -- -+ amdgpu_add_handle_to_table(bo); - bo->cpu_ptr = ptr; - bo->cpu_map_count = 1; - pthread_mutex_unlock(&bo->cpu_access_mutex); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch deleted file mode 100644 index 31a20bf2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 52bf3cba5dcb9064c6c174e6a69c0d40cd064594 Mon Sep 17 00:00:00 2001 -From: "monk.liu" <Monk.Liu@amd.com> -Date: Tue, 1 Dec 2015 17:48:18 +0800 -Subject: [PATCH 062/117] amdgpu: cs_wait_fences now can return the first - signaled fence index - -Change-Id: Idf3d3bf0f2d2396a77341f97174d0a173fdd8932 -Signed-off-by: monk.liu <Monk.Liu@amd.com> ---- - amdgpu/amdgpu.h | 3 ++- - amdgpu/amdgpu_cs.c | 12 +++++++++--- - include/drm/amdgpu_drm.h | 3 ++- - tests/amdgpu/basic_tests.c | 2 +- - 4 files changed, 14 insertions(+), 6 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 5415bd0..693d841 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -947,6 +947,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - * otherwise, wait at least one fence - * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds - * \param status - \c [out] '1' for signaled, '0' for timeout -+ * \param first - \c [out] the index of the first signaled fence from @fences - * - * \return 0 on success - * <0 - Negative POSIX Error code -@@ -958,7 +959,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, - uint32_t fence_count, - bool wait_all, - uint64_t timeout_ns, -- uint32_t *status); -+ uint32_t *status, uint32_t *first); - - /* - * Query / Info API -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index 0c9bcc4..b29e8c9 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -447,7 +447,8 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, - uint32_t fence_count, - bool wait_all, - uint64_t timeout_ns, -- uint32_t *status) -+ uint32_t *status, -+ uint32_t *first) - { - struct drm_amdgpu_fence *drm_fences; - amdgpu_device_handle dev = fences[0].context->dev; -@@ -475,6 +476,10 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, - return -errno; - - *status = args.out.status; -+ -+ if (first) -+ *first = args.out.first_signaled; -+ - return 0; - } - -@@ -482,7 +487,8 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, - uint32_t fence_count, - bool wait_all, - uint64_t timeout_ns, -- uint32_t *status) -+ uint32_t *status, -+ uint32_t *first) - { - uint32_t ioctl_status = 0; - uint32_t i; -@@ -507,7 +513,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, - *status = 0; - - r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, timeout_ns, -- &ioctl_status); -+ &ioctl_status, first); - - if (!r) - *status = ioctl_status; -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index e07904c..599c2e7 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -330,7 +330,8 @@ struct drm_amdgpu_wait_fences_in { - }; - - struct drm_amdgpu_wait_fences_out { -- uint64_t status; -+ uint32_t status; -+ uint32_t first_signaled; - }; - - union drm_amdgpu_wait_fences { -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index f308e9a..e1aaffc 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -1154,7 +1154,7 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) - - r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, - AMDGPU_TIMEOUT_INFINITE, -- &expired); -+ &expired, NULL); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0065-Hybrid-Version-16.30.4.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0065-Hybrid-Version-16.30.4.patch deleted file mode 100644 index 130473a8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0065-Hybrid-Version-16.30.4.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 2c13990aa362c397e95b71ce021a71c567fc1cb5 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 6 Jun 2016 13:42:15 +0800 -Subject: [PATCH 065/117] Hybrid Version: 16.30.4 - -Change-Id: Icca7fa5fcf2e3494102e69b6f1cca2ea558a3898 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 4cabeed..dfcfbd8 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 30 --HYBRID_VERSION_PATCH = 3 -+HYBRID_VERSION_PATCH = 4 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0066-amdgpu-add-marketing-name-for-RX480-RX470.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0066-amdgpu-add-marketing-name-for-RX480-RX470.patch deleted file mode 100644 index 1833e000..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0066-amdgpu-add-marketing-name-for-RX480-RX470.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2b42a0e09532467dc69771e3c11b86cc97e7b588 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Tue, 7 Jun 2016 10:14:18 +0800 -Subject: [PATCH 066/117] amdgpu: add marketing name for RX480/RX470 - -Change-Id: I42fd363a31d423ca80e8fef91225cacaab7d7257 -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index c29a27e..229a516 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -53,6 +53,8 @@ struct amdgpu_asic_id_table_t { - {0x67B1, 0x0, "AMD Radeon R9 200 Series"}, - {0x67B1, 0x80, "AMD Radeon (TM) R9 390 Series"}, - {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67DF, 0xC7, "AMD Radeon (TM) RX 480 Graphics"}, -+ {0x67DF, 0xCF, "AMD Radeon (TM) RX 470 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0068-Hybrid-Version-16.40.1.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0068-Hybrid-Version-16.40.1.patch deleted file mode 100644 index d50216d9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0068-Hybrid-Version-16.40.1.patch +++ /dev/null @@ -1,23 +0,0 @@ -From c9aff41c1564cbe2c8f10ed848108c4effc7f10b Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 13 Jun 2016 18:05:41 +0800 -Subject: [PATCH 068/117] Hybrid Version: 16.40.1 - -Change-Id: Ic4d7182c159ec77604e966a7153d361799cb0583 ---- - .version.hybrid | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/.version.hybrid b/.version.hybrid -index dfcfbd8..1c30410 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 --HYBRID_VERSION_MINOR = 30 --HYBRID_VERSION_PATCH = 4 -+HYBRID_VERSION_MINOR = 40 -+HYBRID_VERSION_PATCH = 1 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0069-Hybrid-Version-16.40.2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0069-Hybrid-Version-16.40.2.patch deleted file mode 100644 index 5f9f6088..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0069-Hybrid-Version-16.40.2.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 2009e1e770823632ca2b31e9db17b7b4a92d2324 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 20 Jun 2016 18:47:01 +0800 -Subject: [PATCH 069/117] Hybrid Version: 16.40.2 - -Change-Id: Ie6029626260838fe8f8cfa117f76ef6b4f6718f8 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 1c30410..5b8a2bc 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 1 -+HYBRID_VERSION_PATCH = 2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch deleted file mode 100644 index de435e2f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 056084ac47a9b6aab3c3815758b31ef961c1297f Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Fri, 24 Jun 2016 12:05:22 +0800 -Subject: [PATCH 070/117] amdgpu: add amdgpu_bo_inc_ref() function. -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Icdc00d3e22e48120ca6f4d73ffd05ba43551ad2c -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 13 +++++++++++++ - amdgpu/amdgpu_bo.c | 6 ++++++ - 2 files changed, 19 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 693d841..d8c436f 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -716,6 +716,19 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, - int amdgpu_bo_free(amdgpu_bo_handle buf_handle); - - /** -+ * Increase the reference count of a buffer object -+ * -+ * \param bo - \c [in] Buffer object handle to increase the reference count -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \sa amdgpu_bo_alloc(), amdgpu_bo_free() -+ * -+*/ -+int amdgpu_bo_inc_ref(amdgpu_bo_handle bo); -+ -+/** - * Request CPU access to GPU accessable memory - * - * \param buf_handle - \c [in] Buffer handle -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index aa0d001..c3f5fb9 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -424,6 +424,12 @@ int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - return 0; - } - -+int amdgpu_bo_inc_ref(amdgpu_bo_handle bo) -+{ -+ atomic_inc(&bo->refcount); -+ return 0; -+} -+ - int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) - { - union drm_amdgpu_gem_mmap args; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0071-Hybrid-Version-16.40.3.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0071-Hybrid-Version-16.40.3.patch deleted file mode 100644 index f4fd2fdf..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0071-Hybrid-Version-16.40.3.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 82760cd09721419720b3e091dd02f29ffcfb63c1 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 27 Jun 2016 19:21:03 +0800 -Subject: [PATCH 071/117] Hybrid Version: 16.40.3 - -Change-Id: I0358494494571d6e82cf005bc73d3f4d797f28b8 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 5b8a2bc..bd6f448 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 2 -+HYBRID_VERSION_PATCH = 3 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0072-amdgpu-add-marketing-name-for-RX460.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0072-amdgpu-add-marketing-name-for-RX460.patch deleted file mode 100644 index 485e097a..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0072-amdgpu-add-marketing-name-for-RX460.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0e43e7324f06369c3bef49a1263190b93b253fb7 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 28 Jun 2016 09:35:57 +0800 -Subject: [PATCH 072/117] amdgpu: add marketing name for RX460 - -Change-Id: I6d8406002bb1a4323b9de14b22aeebc5301faa19 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 229a516..8b270f5 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -55,6 +55,8 @@ struct amdgpu_asic_id_table_t { - {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, - {0x67DF, 0xC7, "AMD Radeon (TM) RX 480 Graphics"}, - {0x67DF, 0xCF, "AMD Radeon (TM) RX 470 Graphics"}, -+ {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch deleted file mode 100644 index 45205c05..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 1f7873fb8c46e42b4b83110289ac1c9a40ed93dd Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 28 Jun 2016 17:38:05 +0800 -Subject: [PATCH 073/117] amdgpu: va allocation may fall to the range outside - of requested [min,max] - -Change-Id: I3e1db613bdc7495a8968914d8560d5ea3aa6d76c -Signed-off-by: David Mao <david.mao@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_vamgr.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index 82653e9..f3e38f6 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -192,10 +192,16 @@ static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint - (hole->offset < range_min && range_min + size > hole->offset + hole->size) || - hole->size < size) - continue; -- offset = hole->offset; -+ /* -+ * it is possible that the hole covers more than one range, -+ * thus we need to respect the range_min -+ */ -+ offset = MAX2(hole->offset, range_min); - waste = offset % alignment; - waste = waste ? alignment - waste : 0; - offset += waste; -+ /* the gap between the range_min and hole->offset need to be covered as well */ -+ waste += offset - hole->offset; - if (offset >= (hole->offset + hole->size)) { - continue; - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0074-drm-fix-a-bug-in-va-range-allocation.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0074-drm-fix-a-bug-in-va-range-allocation.patch deleted file mode 100644 index 0d9c48a1..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0074-drm-fix-a-bug-in-va-range-allocation.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 7508b82630fc31ab2f02e3613747da3a64e05f60 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Thu, 30 Jun 2016 11:19:08 +0800 -Subject: [PATCH 074/117] drm: fix a bug in va range allocation - -Change-Id: Ic038990a14096ff12e3f309f68fd47d057d6bedd -Signed-off-by: David Mao <david.mao@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_vamgr.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c -index f3e38f6..1518b7a 100644 ---- a/amdgpu/amdgpu_vamgr.c -+++ b/amdgpu/amdgpu_vamgr.c -@@ -201,11 +201,15 @@ static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint - waste = waste ? alignment - waste : 0; - offset += waste; - /* the gap between the range_min and hole->offset need to be covered as well */ -- waste += offset - hole->offset; -+ waste = offset - hole->offset; - if (offset >= (hole->offset + hole->size)) { - continue; - } - -+ if (offset + size > range_max) { -+ continue; -+ } -+ - if (!waste && hole->size == size) { - offset = hole->offset; - list_del(&hole->list); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch deleted file mode 100644 index 9af75693..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 56d1958975665c03e3b291e941402df9891d6a95 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:46:37 +0800 -Subject: [PATCH 077/117] amdgpu: Make amdgpu_get_auth to non-static - -The amdgpu_get_auth will be used by another two functions amdgpu_get_fb_id -and amdgpu_get_bo_from_fb_id, so make it to non-static, and -add definition to amdgpu_internal.h. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - amdgpu/amdgpu_device.c | 2 +- - amdgpu/amdgpu_internal.h | 14 ++++++++++++++ - 2 files changed, 15 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c -index 8f1f781..e9ea39c 100644 ---- a/amdgpu/amdgpu_device.c -+++ b/amdgpu/amdgpu_device.c -@@ -113,7 +113,7 @@ static int fd_compare(void *key1, void *key2) - * >0 - AMD specific error code\n - * <0 - Negative POSIX Error code - */ --static int amdgpu_get_auth(int fd, int *auth) -+int amdgpu_get_auth(int fd, int *auth) - { - int r = 0; - drm_client_t client = {}; -diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h -index 1160a12..f722ab5 100644 ---- a/amdgpu/amdgpu_internal.h -+++ b/amdgpu/amdgpu_internal.h -@@ -159,6 +159,20 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); - drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); - - /** -+* Get the authenticated form fd, -+* -+* \param fd - \c [in] File descriptor for AMD GPU device -+* \param auth - \c [out] Pointer to output the fd is authenticated or not -+* A render node fd, output auth = 0 -+* A legacy fd, get the authenticated for compatibility root -+* -+* \return 0 on success\n -+* >0 - AMD specific error code\n -+* <0 - Negative POSIX Error code -+*/ -+int amdgpu_get_auth(int fd, int *auth); -+ -+/** - * Inline functions. - */ - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch deleted file mode 100644 index 5c4ad095..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 713485538f2f98590cd3e89ec10a8d9e77f304dc Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:43:37 +0800 -Subject: [PATCH 078/117] amdgpu: Add interface amdgpu_get_fb_id - -The amdgpu_get_fb_id is used to export the crtc's -framebuffer's buffer id to OpenGL driver for capturing -desktop to OpenGL texture. This is for linux rapidfire server. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - amdgpu/amdgpu-symbol-check | 1 + - amdgpu/amdgpu.h | 15 +++++++++++++++ - amdgpu/amdgpu_bo.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 64 insertions(+) - -diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index 648db9b..e26ffe2 100755 ---- a/amdgpu/amdgpu-symbol-check -+++ b/amdgpu/amdgpu-symbol-check -@@ -48,6 +48,7 @@ amdgpu_read_mm_registers - amdgpu_va_range_alloc - amdgpu_va_range_free - amdgpu_va_range_query -+amdgpu_get_fb_id - EOF - done) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index d8c436f..0f31100 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -637,6 +637,21 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - struct amdgpu_bo_import_result *output); - - /** -+ * Allow others to get access to crtc's framebuffer -+ * -+ * \param dev - \c [in] Device handle. -+ * See #amdgpu_device_initialize() -+ * \param fb_id - \c [out] the first crtc's framebuffer's buffer_id -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \sa amdgpu_get_fb_id() -+ * -+*/ -+int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); -+ -+/** - * Request GPU access to user allocated memory e.g. via "malloc" - * - * \param dev - [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index c3f5fb9..49b951b 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -43,6 +43,7 @@ - #include "amdgpu_internal.h" - #include "util_hash_table.h" - #include "util_math.h" -+#include "xf86drmMode.h" - - static void amdgpu_close_kms_handle(amdgpu_device_handle dev, - uint32_t handle) -@@ -417,6 +418,53 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - return 0; - } - -+/* Get the first use crtc's frame buffer's buffer_id. */ -+int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) -+{ -+ drmModeResPtr mode_res; -+ int count_crtcs; -+ drmModeCrtcPtr mode_crtc; -+ int current_id = 0; -+ drmModeFBPtr fbcur; -+ struct drm_amdgpu_gem_create_in bo_info = {}; -+ struct drm_amdgpu_gem_op gem_op = {}; -+ int r = 0; -+ int i; -+ struct amdgpu_bo *bo = NULL; -+ int flag_auth = 0; -+ int fd = dev->fd; -+ -+ amdgpu_get_auth(dev->fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->fd; -+ } else { -+ amdgpu_get_auth(dev->flink_fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->flink_fd; -+ } else { -+ fprintf(stderr, "amdgpu: amdgpu_get_fb_id, couldn't get the auth fd\n"); -+ return EINVAL; -+ } -+ } -+ -+ mode_res = drmModeGetResources(fd); -+ if (!mode_res) -+ return EFAULT; -+ -+ count_crtcs = mode_res->count_crtcs; -+ for (i = 0; i < mode_res->count_crtcs; i++) { -+ mode_crtc = drmModeGetCrtc(fd, mode_res->crtcs[i]); -+ if (mode_crtc->buffer_id) { -+ current_id = mode_crtc->buffer_id; -+ if (current_id != NULL) -+ break; -+ } -+ } -+ *fb_id = current_id; -+ -+ return r; -+} -+ - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { - /* Just drop the reference. */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch deleted file mode 100644 index 31fac2c5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch +++ /dev/null @@ -1,163 +0,0 @@ -From 562a5585d1c46a99b192c6cf080eb2aad582fa25 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:44:51 +0800 -Subject: [PATCH 079/117] amdgpu: Add interface amdgpu_get_bo_from_fb_id - -The amdgpu_get_bo_from_fb_id is used to export the -crtc's framebuffer's buffer object to OpenGL driver for capturing desktop to -OpenGL texture.This is alse used by linux rapidfire server. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - amdgpu/amdgpu-symbol-check | 1 + - amdgpu/amdgpu.h | 17 +++++++++ - amdgpu/amdgpu_bo.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 110 insertions(+) - -diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check -index e26ffe2..028ff78 100755 ---- a/amdgpu/amdgpu-symbol-check -+++ b/amdgpu/amdgpu-symbol-check -@@ -49,6 +49,7 @@ amdgpu_va_range_alloc - amdgpu_va_range_free - amdgpu_va_range_query - amdgpu_get_fb_id -+amdgpu_get_bo_from_fb_id - EOF - done) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 0f31100..08593ca 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -652,6 +652,23 @@ int amdgpu_bo_import(amdgpu_device_handle dev, - int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); - - /** -+ * Get the framebuffer's bo by fb_id -+ * -+ * \param dev - \c [in] Device handle. -+ * See #amdgpu_device_initialize() -+ * \param fb_id - \c [in] the framebuffer's buffer_id -+ * -+ * \param output - \c [output] the bo of fb_id -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \sa amdgpu_get_bo_from_fb_id() -+ * -+*/ -+int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struct amdgpu_bo_import_result *output); -+ -+/** - * Request GPU access to user allocated memory e.g. via "malloc" - * - * \param dev - [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index 49b951b..f311b94 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -465,6 +465,98 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) - return r; - } - -+/* Get the frame buffer's gem object handle by the fb_id. */ -+int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struct amdgpu_bo_import_result *output) -+{ -+ drmModeFBPtr fbcur; -+ struct drm_amdgpu_gem_create_in bo_info = {}; -+ struct drm_amdgpu_gem_op gem_op = {}; -+ int r = 0; -+ int i; -+ struct amdgpu_bo *bo = NULL; -+ int dma_fd; -+ int flag_auth = 0; -+ int fd = dev->fd; -+ -+ amdgpu_get_auth(dev->fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->fd; -+ } else { -+ amdgpu_get_auth(dev->flink_fd, &flag_auth); -+ if (flag_auth) { -+ fd = dev->flink_fd; -+ } else { -+ fprintf(stderr, "amdgpu: amdgpu_get_bo_from_fb_id, couldn't get the auth fd\n"); -+ return EINVAL; -+ } -+ } -+ -+ fbcur = drmModeGetFB(fd, fb_id); -+ -+ pthread_mutex_lock(&dev->bo_table_mutex); -+ if (fd != dev->fd) { -+ r = drmPrimeHandleToFD(fd, fbcur->handle, DRM_CLOEXEC, &dma_fd); -+ if (r) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return r; -+ } -+ r = drmPrimeFDToHandle(dev->fd, dma_fd, &fbcur->handle ); -+ -+ close(dma_fd); -+ -+ if (r) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return r; -+ } -+ } -+ bo = util_hash_table_get(dev->bo_handles, -+ (void*)(uintptr_t)fbcur->handle); -+ -+ if (bo) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ -+ /* The buffer already exists, just bump the refcount. */ -+ atomic_inc(&bo->refcount); -+ -+ output->buf_handle = bo; -+ output->alloc_size = bo->alloc_size; -+ return 0; -+ } -+ -+ bo = calloc(1, sizeof(struct amdgpu_bo)); -+ if (!bo) { -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return -ENOMEM; -+ } -+ -+ /* Query buffer info. */ -+ gem_op.handle = fbcur->handle; -+ gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO; -+ gem_op.value = (uintptr_t)&bo_info; -+ -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_OP, -+ &gem_op, sizeof(gem_op)); -+ if (r) { -+ free(bo); -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ return r; -+ } -+ -+ /* Initialize it. */ -+ atomic_set(&bo->refcount, 1); -+ bo->handle = fbcur->handle; -+ bo->dev = dev; -+ bo->alloc_size = bo_info.bo_size; -+ output->buf_handle = bo; -+ pthread_mutex_init(&bo->cpu_access_mutex, NULL); -+ -+ util_hash_table_set(dev->bo_handles, (void*)(uintptr_t)bo->handle, bo); -+ pthread_mutex_unlock(&dev->bo_table_mutex); -+ -+ output->alloc_size = bo->alloc_size; -+ return r; -+} -+ - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { - /* Just drop the reference. */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch deleted file mode 100644 index 933f9ea6..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch +++ /dev/null @@ -1,55 +0,0 @@ -From da3e76d7d0dacc732927990344dbe40e69abb8f0 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Tue, 5 Jul 2016 15:45:33 +0800 -Subject: [PATCH 080/117] amdgpu/tests: Add the test case for amdgpu_get_fb_id - and amdgpu_get_bo_from_fb_id. - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> ---- - tests/amdgpu/bo_tests.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 993895d..195667f 100644 ---- a/tests/amdgpu/bo_tests.c -+++ b/tests/amdgpu/bo_tests.c -@@ -46,6 +46,8 @@ static amdgpu_va_handle va_handle; - static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); -+static void amdgpu_get_fb_id_and_handle(void); -+ - - CU_TestInfo bo_tests[] = { - { "Export/Import", amdgpu_bo_export_import }, -@@ -53,6 +55,7 @@ CU_TestInfo bo_tests[] = { - { "Metadata", amdgpu_bo_metadata }, - #endif - { "CPU map/unmap", amdgpu_bo_map_unmap }, -+ { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, - CU_TEST_INFO_NULL, - }; - -@@ -184,3 +187,18 @@ static void amdgpu_bo_map_unmap(void) - r = amdgpu_bo_cpu_unmap(buffer_handle); - CU_ASSERT_EQUAL(r, 0); - } -+ -+static void amdgpu_get_fb_id_and_handle(void) -+{ -+ uint32_t *ptr; -+ int i, r; -+ unsigned int fb_id; -+ struct amdgpu_bo_import_result output; -+ -+ r = amdgpu_get_fb_id(device_handle, &fb_id); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_NOT_EQUAL(fb_id, 0); -+ r = amdgpu_get_bo_from_fb_id(device_handle, fb_id, &output); -+ CU_ASSERT_EQUAL(r, 0); -+ CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0081-Hybrid-Version-16.40.4.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0081-Hybrid-Version-16.40.4.patch deleted file mode 100644 index 198ab353..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0081-Hybrid-Version-16.40.4.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 38a6d82d6b796de64885d2a37b1ff9e130e62737 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Wed, 6 Jul 2016 18:43:24 +0800 -Subject: [PATCH 081/117] Hybrid Version: 16.40.4 - -Change-Id: I8ece2169f2a06f6dba83a6642e4c67a4124d0e57 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index bd6f448..f895f5b 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 3 -+HYBRID_VERSION_PATCH = 4 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch deleted file mode 100644 index 48a1856c..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 3edba3d8135eb76e45d6cac2681414a2af790b0c Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Thu, 14 Jul 2016 17:33:13 +0800 -Subject: [PATCH 082/117] amdgpu: Fix memory leak in amdgpu_get_fb_id - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Jim Qu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu_bo.c | 10 +++++++--- - 1 file changed, 7 insertions(+), 3 deletions(-) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index f311b94..ebfb7cf 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -454,13 +454,17 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) - count_crtcs = mode_res->count_crtcs; - for (i = 0; i < mode_res->count_crtcs; i++) { - mode_crtc = drmModeGetCrtc(fd, mode_res->crtcs[i]); -- if (mode_crtc->buffer_id) { -- current_id = mode_crtc->buffer_id; -- if (current_id != NULL) -+ if (mode_crtc) { -+ if (mode_crtc->buffer_id) { -+ current_id = mode_crtc->buffer_id; -+ drmModeFreeCrtc(mode_crtc); - break; -+ } -+ drmModeFreeCrtc(mode_crtc); - } - } - *fb_id = current_id; -+ drmModeFreeResources(mode_res); - - return r; - } --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch deleted file mode 100644 index 5be20c43..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 2f5986c7208a9b8534f2fb0981fc5d5fd7c65e30 Mon Sep 17 00:00:00 2001 -From: jqdeng <Emily.Deng@amd.com> -Date: Thu, 14 Jul 2016 17:32:27 +0800 -Subject: [PATCH 083/117] amdgpu: Fix memory leak in amdgpu_get_bo_from_fb_id - -Signed-off-by: jqdeng <Emily.Deng@amd.com> -Reviewed-by: Jim Qu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu_bo.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index ebfb7cf..a07d0b5 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -497,11 +497,15 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - - fbcur = drmModeGetFB(fd, fb_id); - -+ if (fbcur == NULL) -+ return EFAULT; -+ - pthread_mutex_lock(&dev->bo_table_mutex); - if (fd != dev->fd) { - r = drmPrimeHandleToFD(fd, fbcur->handle, DRM_CLOEXEC, &dma_fd); - if (r) { - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return r; - } - r = drmPrimeFDToHandle(dev->fd, dma_fd, &fbcur->handle ); -@@ -510,6 +514,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - - if (r) { - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return r; - } - } -@@ -524,12 +529,14 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - - output->buf_handle = bo; - output->alloc_size = bo->alloc_size; -+ drmModeFreeFB(fbcur); - return 0; - } - - bo = calloc(1, sizeof(struct amdgpu_bo)); - if (!bo) { - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return -ENOMEM; - } - -@@ -543,6 +550,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - if (r) { - free(bo); - pthread_mutex_unlock(&dev->bo_table_mutex); -+ drmModeFreeFB(fbcur); - return r; - } - -@@ -558,6 +566,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - pthread_mutex_unlock(&dev->bo_table_mutex); - - output->alloc_size = bo->alloc_size; -+ drmModeFreeFB(fbcur); - return r; - } - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch deleted file mode 100644 index 7f8d9f7d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 77886f605b2ea3db8c807a9e955c554f01ca831a Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Sat, 9 Jul 2016 12:00:41 +0800 -Subject: [PATCH 084/117] drm: Fix multi GPU drmGetDevice return wrong device - -drmGetDevice will always return the first device it find -under /dev/dri/. This is not true for multi GPU situation. - -Change-Id: I2a85a8a4feba8a5cc517ad75c6afb532fa07c53d -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - xf86drm.c | 17 +++++++++++++---- - 1 file changed, 13 insertions(+), 4 deletions(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 6689f7c..19001db 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -3087,6 +3087,7 @@ int drmGetDevice(int fd, drmDevicePtr *device) - int maj, min; - int ret, i, node_count; - int max_count = 16; -+ dev_t find_rdev; - - if (fd == -1 || device == NULL) - return -EINVAL; -@@ -3094,6 +3095,7 @@ int drmGetDevice(int fd, drmDevicePtr *device) - if (fstat(fd, &sbuf)) - return -errno; - -+ find_rdev = sbuf.st_rdev; - maj = major(sbuf.st_rdev); - min = minor(sbuf.st_rdev); - -@@ -3154,17 +3156,24 @@ int drmGetDevice(int fd, drmDevicePtr *device) - local_devices = temp; - } - -- local_devices[i] = d; -+ /* store target at local_devices[0] for ease to use below */ -+ if (find_rdev == sbuf.st_rdev && i) { -+ local_devices[i] = local_devices[0]; -+ local_devices[0] = d; -+ } -+ else -+ local_devices[i] = d; - i++; - } - node_count = i; - -- /* Fold nodes into a single device if they share the same bus info */ -+ /* Fold nodes into a single device if they share the same bus info -+ * and nodes with same bus info will be merged into the first node -+ * position in local_devices */ - drmFoldDuplicatedDevices(local_devices, node_count); - - *device = local_devices[0]; -- for (i = 1; i < node_count && local_devices[i]; i++) -- drmFreeDevice(&local_devices[i]); -+ drmFreeDevices(&local_devices[1], node_count - 1); - - closedir(sysdir); - free(local_devices); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch deleted file mode 100644 index a7e8721f..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9fbef91c92df8da1732bfc8584d6937fcab63bf8 Mon Sep 17 00:00:00 2001 -From: Qiang Yu <Qiang.Yu@amd.com> -Date: Thu, 14 Jul 2016 11:39:42 +0800 -Subject: [PATCH 085/117] drm: fix multi GPU drmFreeDevices memory leak - -When in multi GPU case, devices array may have some -NULL "hole" in between two devices. So check all -array elements and free non-NULL device. - -Change-Id: Ifc32d240f895059bc4b19138cb81de38d99fb88a -Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> -Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> ---- - xf86drm.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/xf86drm.c b/xf86drm.c -index 19001db..32bedeb 100644 ---- a/xf86drm.c -+++ b/xf86drm.c -@@ -2992,8 +2992,9 @@ void drmFreeDevices(drmDevicePtr devices[], int count) - if (devices == NULL) - return; - -- for (i = 0; i < count && devices[i] != NULL; i++) -- drmFreeDevice(&devices[i]); -+ for (i = 0; i < count; i++) -+ if (devices[i]) -+ drmFreeDevice(&devices[i]); - } - - static int drmProcessPciDevice(drmDevicePtr *device, const char *d_name, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0086-drm-add-marketing-names.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0086-drm-add-marketing-names.patch deleted file mode 100644 index 2516c27e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0086-drm-add-marketing-names.patch +++ /dev/null @@ -1,33 +0,0 @@ -From c9b023766d554e9325788b6dbeaaba578e413d14 Mon Sep 17 00:00:00 2001 -From: Ken Wang <Qingqing.Wang@amd.com> -Date: Fri, 15 Jul 2016 16:48:02 +0800 -Subject: [PATCH 086/117] drm: add marketing names - -Change-Id: I6f9b61bde22d9795bda93a7df72dfe2c561bb39a -Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> -Reviewed-by : JimQu <Jim.Qu@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 8b270f5..dada012 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -53,8 +53,13 @@ struct amdgpu_asic_id_table_t { - {0x67B1, 0x0, "AMD Radeon R9 200 Series"}, - {0x67B1, 0x80, "AMD Radeon (TM) R9 390 Series"}, - {0x67B9, 0x0, "AMD Radeon R9 200 Series"}, -+ {0x67DF, 0xC4, "AMD Radeon (TM) RX 480 Graphics"}, -+ {0x67DF, 0xC5, "AMD Radeon (TM) RX 470 Graphics"}, - {0x67DF, 0xC7, "AMD Radeon (TM) RX 480 Graphics"}, - {0x67DF, 0xCF, "AMD Radeon (TM) RX 470 Graphics"}, -+ {0x67C4, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, -+ {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0087-Hybrid-Version-16.40.5.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0087-Hybrid-Version-16.40.5.patch deleted file mode 100644 index 4e4b0315..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0087-Hybrid-Version-16.40.5.patch +++ /dev/null @@ -1,22 +0,0 @@ -From fed82247d220c1e58b8e9ee9cd1540cb53916997 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 18 Jul 2016 21:59:29 +0800 -Subject: [PATCH 087/117] Hybrid Version: 16.40.5 - -Change-Id: I9c6c41ff3f249f37fb664d9dbba73918ebd0ce7a ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index f895f5b..742801d 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 4 -+HYBRID_VERSION_PATCH = 5 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0088-drm-add-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0088-drm-add-marketing-name.patch deleted file mode 100644 index e4bfa080..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0088-drm-add-marketing-name.patch +++ /dev/null @@ -1,39 +0,0 @@ -From d6ffb1aad9eb34f52e9497967c66f345261ce343 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Thu, 21 Jul 2016 23:22:24 +0800 -Subject: [PATCH 088/117] drm: add marketing name - -Change-Id: Id98873392c171ab3381b8991774a7e667866a527 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index dada012..b163486 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -60,8 +60,19 @@ struct amdgpu_asic_id_table_t { - {0x67C4, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, -+ {0x67E0, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67EF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC7, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xEF, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67FF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67FF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0089-Hybrid-Version-16.40.6.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0089-Hybrid-Version-16.40.6.patch deleted file mode 100644 index 550191d5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0089-Hybrid-Version-16.40.6.patch +++ /dev/null @@ -1,22 +0,0 @@ -From d0eaf4ef0e9741cebac7e10fbaf3ade164ad00d2 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Fri, 22 Jul 2016 18:41:45 +0800 -Subject: [PATCH 089/117] Hybrid Version: 16.40.6 - -Change-Id: Icb6c016f122355d0bb38b9c28f64dad31b54d5b1 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 742801d..1b1ec19 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 5 -+HYBRID_VERSION_PATCH = 6 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch deleted file mode 100644 index 72dd11b2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7914d4696e9e94fabe816cba3445a013b43f671 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Tue, 19 Jul 2016 17:04:56 +0800 -Subject: [PATCH 090/117] amdgpu: change AMDGPU_GEM_CREATE_NO_EVICT flag - definition - -to avoid conflict with upstream flags. - -Change-Id: I1ec4aa23c94b7711dea4d75936c94b2655b2a100 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 599c2e7..46a3c40 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -78,7 +78,7 @@ - /* Flag that USWC attributes should be used for GTT */ - #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) - /* Flag that the memory allocation should be pinned */ --#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 3) -+#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 31) - - struct drm_amdgpu_gem_create_in { - /** the requested memory size */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0092-drm-add-marketing-names.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0092-drm-add-marketing-names.patch deleted file mode 100644 index 3d3c0c42..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0092-drm-add-marketing-names.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 6834d5e286f239063e6c9a4d4c283ead43fddaf5 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Sat, 23 Jul 2016 02:31:22 +0800 -Subject: [PATCH 092/117] drm: add marketing names - -Change-Id: Ib6c19ad8b473119de8ef531eafe91c90d1840f6b -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index b163486..11c25f5 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -61,10 +61,15 @@ struct amdgpu_asic_id_table_t { - {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67E0, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E0, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, -+ {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 4100 Graphics"}, - {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -+ {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0095-drm-update-marketing-names.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0095-drm-update-marketing-names.patch deleted file mode 100644 index e521eff6..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0095-drm-update-marketing-names.patch +++ /dev/null @@ -1,40 +0,0 @@ -From ab292275c8d18a9a97d95fab5737c7c9a6817008 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Sat, 23 Jul 2016 03:53:12 +0800 -Subject: [PATCH 095/117] drm: update marketing names - -Change-Id: Ic9f1f32305d0661b38d2d9b206e51ab749c8e31b -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 11c25f5..5585bc8 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -70,14 +70,14 @@ struct amdgpu_asic_id_table_t { - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, -- {0x67EF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xC7, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xC5, "AMD Radeon (TM) RX Graphics"}, -+ {0x67EF, 0xC7, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xEF, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67FF, 0xC0, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67FF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -+ {0x67EF, 0xEF, "AMD Radeon (TM) RX Graphics"}, -+ {0x67FF, 0xC0, "AMD Radeon (TM) RX Graphics"}, -+ {0x67FF, 0xC1, "AMD Radeon (TM) RX Graphics"}, - {0x6800, 0x0, "AMD Radeon HD 7970M"}, - {0x6801, 0x0, "AMD Radeon(TM) HD8970M"}, - {0x6808, 0x0, "ATI FirePro V(FireGL V) Graphics Adapter"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0097-drm-add-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0097-drm-add-marketing-name.patch deleted file mode 100644 index a45d1883..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0097-drm-add-marketing-name.patch +++ /dev/null @@ -1,27 +0,0 @@ -From a2066a7bdc9b36299f58339e73c6af56847e74d1 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Sat, 23 Jul 2016 04:12:44 +0800 -Subject: [PATCH 097/117] drm: add marketing name - -Change-Id: I13142a7605c56586313a9837ad23cdd29805a143 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 5585bc8..00815bd 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -68,6 +68,7 @@ struct amdgpu_asic_id_table_t { - {0x67E8, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, -+ {0x67E8, 0x80, "AMD Radeon (TM) E9260 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch deleted file mode 100644 index 410aaf70..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 0f7d07aacc6e4221dd79517b5465066650e7fc43 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Mon, 25 Jul 2016 13:53:45 +0800 -Subject: [PATCH 099/117] amdgpu: add the copyright and macros for the asic id - header file - -Change-Id: I83b2f0bb3828cc91b950a826bbfd2fcd5a6965ac -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 00815bd..d521175 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -1,3 +1,30 @@ -+/* -+ * Copyright © 2016 Advanced Micro Devices, Inc. -+ * All Rights Reserved. -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+ */ -+ -+#ifndef __AMDGPU_ASIC_ID_H__ -+#define __AMDGPU_ASIC_ID_H__ -+ - struct amdgpu_asic_id_table_t { - uint32_t did; - uint32_t rid; -@@ -140,3 +167,4 @@ struct amdgpu_asic_id_table_t { - - {0x0000, 0x0, "\0"}, - }; -+#endif --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0100-Hybrid-Version-16.40.7.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0100-Hybrid-Version-16.40.7.patch deleted file mode 100644 index c0f623b7..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0100-Hybrid-Version-16.40.7.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 360c7e9414bc61a7240b6703a0ab7c92fdeeb107 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Wed, 27 Jul 2016 19:17:38 +0800 -Subject: [PATCH 100/117] Hybrid Version: 16.40.7 - -Change-Id: Ib919f980255ad2df04dcc7a52c716d35c550e275 ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 1b1ec19..2f1b84f 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 6 -+HYBRID_VERSION_PATCH = 7 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0101-drm-change-the-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0101-drm-change-the-marketing-name.patch deleted file mode 100644 index e78eacdc..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0101-drm-change-the-marketing-name.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d0ff0115ebfa74bb00aef28aee2b8532e4d96f4f Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Fri, 29 Jul 2016 21:14:24 +0800 -Subject: [PATCH 101/117] drm: change the marketing name - -Change-Id: I9573cee6cd3aca25c2c639f39ab210069c09f48b -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> -Reviewed-by: Junwei Zhang Jerry.Zhang@amd.com ---- - amdgpu/amdgpu_asic_id.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index d521175..041ebe3 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -100,7 +100,7 @@ struct amdgpu_asic_id_table_t { - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, -- {0x67EF, 0xC5, "AMD Radeon (TM) RX Graphics"}, -+ {0x67EF, 0xC5, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xC7, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xCF, "AMD Radeon (TM) RX 460 Graphics"}, - {0x67EF, 0xEF, "AMD Radeon (TM) RX Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch deleted file mode 100644 index 1b61a838..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch +++ /dev/null @@ -1,32 +0,0 @@ -From fad00706737fb2593523dbf799d7c6889a0edd73 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Fri, 22 Jul 2016 11:56:52 +0800 -Subject: [PATCH 103/117] amdgpu: expose the AMDGPU_GEM_CREATE_VRAM_CLEARED - flag - -With this flag specified, VRAM buffer will be cleared at -allocation time. - -Change-Id: Ic587ed7e524a3bfc3862a57b42aa95ff458fe880 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com> ---- - include/drm/amdgpu_drm.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 46a3c40..9aa0420 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -77,6 +77,8 @@ - #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) - /* Flag that USWC attributes should be used for GTT */ - #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) -+/* Flag that the memory should be in VRAM and cleared */ -+#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) - /* Flag that the memory allocation should be pinned */ - #define AMDGPU_GEM_CREATE_NO_EVICT (1 << 31) - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0104-drm-amdgpu-add-freesync-ioctl-defines.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0104-drm-amdgpu-add-freesync-ioctl-defines.patch deleted file mode 100644 index a62f2258..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0104-drm-amdgpu-add-freesync-ioctl-defines.patch +++ /dev/null @@ -1,53 +0,0 @@ -From bd51d57069011aef5372d68942cee32a13013108 Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Thu, 4 Aug 2016 14:26:51 +0800 -Subject: [PATCH 104/117] drm/amdgpu: add freesync ioctl defines - -Change-Id: Id5d607fee4ae119015ca685a508a2ee140a8e331 -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - include/drm/amdgpu_drm.h | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 9aa0420..7ffd26b 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -48,6 +48,7 @@ - #define DRM_AMDGPU_GEM_USERPTR 0x11 - #define DRM_AMDGPU_WAIT_FENCES 0x12 - #define DRM_AMDGPU_GEM_FIND_BO 0x13 -+#define DRM_AMDGPU_FREESYNC 0x14 - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -63,6 +64,7 @@ - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -708,4 +710,17 @@ struct drm_amdgpu_virtual_range { - uint64_t start; - uint64_t end; - }; -+ -+/* -+ * Definition of free sync enter and exit signals -+ * We may have more options in the future -+ */ -+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 -+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 -+ -+struct drm_amdgpu_freesync { -+ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ -+ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ -+ __u32 spare[7]; -+}; - #endif --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch deleted file mode 100644 index 0859114e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch +++ /dev/null @@ -1,48 +0,0 @@ -From abd3f05b15245951daf6e6aa4228e176e433ae5c Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Tue, 9 Aug 2016 15:47:51 +0800 -Subject: [PATCH 106/117] amdgpu: move hybrid specific ioctl to the end - -To avoid conflicts - -Change-Id: I41a3b62363b2d653e6e8726073c2e9c816604030 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> -Reviewed-by: Chunming Zhou <david1.zhou@amd.com> ---- - include/drm/amdgpu_drm.h | 12 +++++++----- - 1 file changed, 7 insertions(+), 5 deletions(-) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 7ffd26b..6ccad71 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -46,9 +46,10 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 --#define DRM_AMDGPU_WAIT_FENCES 0x12 --#define DRM_AMDGPU_GEM_FIND_BO 0x13 --#define DRM_AMDGPU_FREESYNC 0x14 -+#define DRM_AMDGPU_FREESYNC 0x14 -+/* hybrid specific ioctls */ -+#define DRM_AMDGPU_WAIT_FENCES 0x5e -+#define DRM_AMDGPU_GEM_FIND_BO 0x5f - - #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) - #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) -@@ -62,9 +63,10 @@ - #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) --#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) --#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) -+/* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) -+#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch deleted file mode 100644 index ec35f992..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 38ff3dfb8dee467e37c1416a5c6d1cd9891426fc Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 10 Aug 2016 13:49:04 +0800 -Subject: [PATCH 108/117] amdgpu/tests: add Polaris12 support for cs test - -Change-Id: Ida31ea85ad851dbe41599a4d791ad2cbd0a14ee5 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> ---- - tests/amdgpu/cs_tests.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 2c9c1ae..6c4a915 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -208,8 +208,10 @@ static void amdgpu_cs_uvd_create(void) - if (family_id >= AMDGPU_FAMILY_VI) { - ((uint8_t*)msg)[0x10] = 7; - /* chip polaris 10/11 */ -- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A -+ || chip_id == chip_rev+0x64) { - /* dpb size */ -+ printf("===> chip_rev = %d, chip_id = 0x%x\n", chip_rev, chip_id); - ((uint8_t*)msg)[0x28] = 0x00; - ((uint8_t*)msg)[0x29] = 0x94; - ((uint8_t*)msg)[0x2A] = 0x6B; -@@ -286,7 +288,8 @@ static void amdgpu_cs_uvd_decode(void) - ptr[0x98] = 0x00; - ptr[0x99] = 0x02; - /* chip polaris10/11 */ -- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A -+ || chip_id == chip_rev+0x64) { - /*dpb size */ - ptr[0x24] = 0x00; - ptr[0x25] = 0x94; -@@ -330,7 +333,8 @@ static void amdgpu_cs_uvd_decode(void) - dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); - - if ((family_id >= AMDGPU_FAMILY_VI) && -- (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { -+ (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A -+ || chip_id == chip_rev+0x64)) { - ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); - } - -@@ -344,7 +348,8 @@ static void amdgpu_cs_uvd_decode(void) - uvd_cmd(bs_addr, 0x100, &i); - if (family_id >= AMDGPU_FAMILY_VI) { - uvd_cmd(it_addr, 0x204, &i); -- if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) -+ if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || -+ chip_id == chip_rev+0x64) - uvd_cmd(ctx_addr, 0x206, &i); - } - ib_cpu[i++] = 0x3BC6; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0109-amdgpu-tests-remove-debug-info-in-cs-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0109-amdgpu-tests-remove-debug-info-in-cs-test.patch deleted file mode 100644 index 06245ca4..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0109-amdgpu-tests-remove-debug-info-in-cs-test.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 51f97fee7269b84d498899fac0a1649131c3d5cc Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 10 Aug 2016 15:16:43 +0800 -Subject: [PATCH 109/117] amdgpu/tests: remove debug info in cs test -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Ic11256fe3f8fd6d80f4eefc85b9ea0ba665dc4fe -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/cs_tests.c | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c -index 6c4a915..ca741b7 100644 ---- a/tests/amdgpu/cs_tests.c -+++ b/tests/amdgpu/cs_tests.c -@@ -211,7 +211,6 @@ static void amdgpu_cs_uvd_create(void) - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A - || chip_id == chip_rev+0x64) { - /* dpb size */ -- printf("===> chip_rev = %d, chip_id = 0x%x\n", chip_rev, chip_id); - ((uint8_t*)msg)[0x28] = 0x00; - ((uint8_t*)msg)[0x29] = 0x94; - ((uint8_t*)msg)[0x2A] = 0x6B; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch deleted file mode 100644 index 56430290..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch +++ /dev/null @@ -1,40 +0,0 @@ -From fdcfc33fadaf63e01061fc41e113c0ed777cc137 Mon Sep 17 00:00:00 2001 -From: Hawking Zhang <Hawking.Zhang@amd.com> -Date: Fri, 12 Aug 2016 14:49:53 +0800 -Subject: [PATCH 110/117] drm/amdgpu: move freesync ioctl to hybrid specific - range - -Change-Id: If324e05ac71107d00c24567a0d2f3380b2084a4f -Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> -Reviewed-by: Flora Cui <Flora.Cui@amd.com> ---- - include/drm/amdgpu_drm.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 6ccad71..cda8f36 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -46,8 +46,8 @@ - #define DRM_AMDGPU_WAIT_CS 0x09 - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 --#define DRM_AMDGPU_FREESYNC 0x14 - /* hybrid specific ioctls */ -+#define DRM_AMDGPU_FREESYNC 0x5d - #define DRM_AMDGPU_WAIT_FENCES 0x5e - #define DRM_AMDGPU_GEM_FIND_BO 0x5f - -@@ -63,8 +63,8 @@ - #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) --#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - /* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) - --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0112-Hybrid-Version-16.50.0.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0112-Hybrid-Version-16.50.0.patch deleted file mode 100644 index cbf015ba..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0112-Hybrid-Version-16.50.0.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 8ccbd3cb964285c222d946dbbc399eb2f5c61f44 Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 15 Aug 2016 19:11:27 +0800 -Subject: [PATCH 112/117] Hybrid Version: 16.50.0 - -Change-Id: I8982d7b72c53032d611ce1b73cb22a28c43b12b5 ---- - .version.hybrid | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 2f1b84f..7c63056 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 --HYBRID_VERSION_MINOR = 40 --HYBRID_VERSION_PATCH = 7 -+HYBRID_VERSION_MINOR = 50 -+HYBRID_VERSION_PATCH = 0 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0113-Hybrid-Version-16.50.1.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0113-Hybrid-Version-16.50.1.patch deleted file mode 100644 index 1ce4a7a9..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0113-Hybrid-Version-16.50.1.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 86bb93c61134fcd9c6993916c3b15135ea14966d Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Thu, 18 Aug 2016 18:48:05 +0800 -Subject: [PATCH 113/117] Hybrid Version: 16.50.1 - -Change-Id: I0c3a8d70098ae332245bff754c51371f6c4c5810 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 7c63056..0cc63be 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 50 --HYBRID_VERSION_PATCH = 0 -+HYBRID_VERSION_PATCH = 1 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0114-amdgpu-add-more-capability-query.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0114-amdgpu-add-more-capability-query.patch deleted file mode 100644 index 7889fbea..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0114-amdgpu-add-more-capability-query.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 7e00543c422f00a68edb4227eeb56ba48175b399 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 11 Aug 2016 15:23:35 +0800 -Subject: [PATCH 114/117] amdgpu: add more capability query - -Change-Id: Ia77feea215a4eb7d0e41684fa5c9e44eedf7feb8 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu.h | 4 +++- - amdgpu/amdgpu_gpu_info.c | 5 +++-- - include/drm/amdgpu_drm.h | 12 ++++++++++-- - 3 files changed, 16 insertions(+), 5 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 08593ca..763a3a6 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -38,6 +38,7 @@ - #include <stdbool.h> - - struct drm_amdgpu_info_hw_ip; -+struct drm_amdgpu_capability; - - /*--------------------------------------------------------------------------*/ - /* --------------------------- Defines ------------------------------------ */ -@@ -1155,7 +1156,8 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - * <0 - Negative POSIX error code - * - */ --int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value); -+int amdgpu_query_capability(amdgpu_device_handle dev, -+ struct drm_amdgpu_capability *cap); - - /** - * Query information about GDS -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 037df32..406baf2 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -48,10 +48,11 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - sizeof(struct drm_amdgpu_info)); - } - --int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value) -+int amdgpu_query_capability(amdgpu_device_handle dev, -+ struct drm_amdgpu_capability *cap) - { - return amdgpu_query_info(dev, AMDGPU_INFO_CAPABILITY, -- sizeof(uint64_t), value); -+ sizeof(struct drm_amdgpu_capability), cap); - } - - int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index cda8f36..14d800e 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -530,8 +530,6 @@ struct drm_amdgpu_cs_chunk_data { - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 --/* query pin memory capability */ --#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) - - #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 - #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff -@@ -713,6 +711,16 @@ struct drm_amdgpu_virtual_range { - uint64_t end; - }; - -+/* query pin memory capability */ -+#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) -+/* query direct gma capability */ -+#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) -+ -+struct drm_amdgpu_capability { -+ uint32_t flag; -+ uint32_t direct_gma_size; -+}; -+ - /* - * Definition of free sync enter and exit signals - * We may have more options in the future --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0115-amdgpu-implement-direct-gma.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0115-amdgpu-implement-direct-gma.patch deleted file mode 100644 index bb19c3a2..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0115-amdgpu-implement-direct-gma.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 1474cc7321f29b223249f9f7c09797534aa67288 Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 11 Aug 2016 15:25:14 +0800 -Subject: [PATCH 115/117] amdgpu: implement direct gma - -Change-Id: I37a6a0f79a91b8e793fc90eb3955045bebf24848 -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - amdgpu/amdgpu.h | 43 +++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_bo.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++- - include/drm/amdgpu_drm.h | 12 +++++++++++ - 3 files changed, 109 insertions(+), 1 deletion(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 763a3a6..525bf8e 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -727,6 +727,49 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, - amdgpu_bo_handle *buf_handle, - uint64_t *offset_in_bo); - -+/** -+ * Request GPU access to physical memory from 3rd party device. -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param phys_address - [in] Physical address from 3rd party device which -+ * we want to map to GPU address space (make GPU accessible) -+ * (This address must be correctly aligned). -+ * \param size - [in] Size of allocation (must be correctly aligned) -+ * \param buf_handle - [out] Buffer handle for the userptr memory -+ * resource on submission and be used in other operations. -+ * -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ * \note -+ * This call should guarantee that such memory will be persistently -+ * "locked" / make non-pageable. The purpose of this call is to provide -+ * opportunity for GPU get access to this resource during submission. -+ * -+ * -+ * Supported (theoretical) max. size of mapping is restricted only by -+ * capability.direct_gma_size. See #amdgpu_query_capability() -+ * -+ * It is responsibility of caller to correctly specify physical_address -+*/ -+int amdgpu_create_bo_from_phys_mem(amdgpu_device_handle dev, -+ uint64_t phys_address, uint64_t size, -+ amdgpu_bo_handle *buf_handle); -+ -+/** -+ * Get physical address from BO -+ * -+ * \param buf_handle - [in] Buffer handle for the physical address. -+ * \param phys_address - [out] Physical address of this BO. -+ * -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, -+ uint64_t *phys_address); - - /** - * Free previosuly allocated memory -diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c -index a07d0b5..6abc5e3 100644 ---- a/amdgpu/amdgpu_bo.c -+++ b/amdgpu/amdgpu_bo.c -@@ -87,7 +87,8 @@ int amdgpu_bo_alloc(amdgpu_device_handle dev, - int r = 0; - - /* It's an error if the heap is not specified */ -- if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM))) -+ if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM -+ | AMDGPU_GEM_DOMAIN_DGMA))) - return -EINVAL; - - bo = calloc(1, sizeof(struct amdgpu_bo)); -@@ -570,6 +571,58 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc - return r; - } - -+int amdgpu_create_bo_from_phys_mem(amdgpu_device_handle dev, -+ uint64_t phys_address, uint64_t size, -+ amdgpu_bo_handle *buf_handle) -+{ -+ struct drm_amdgpu_gem_dgma args; -+ amdgpu_bo_handle bo; -+ int r; -+ -+ if (phys_address == 0 || phys_address & 4095 || -+ size == 0 || size & 4095) -+ return -EINVAL; -+ -+ args.addr = phys_address; -+ args.size = size; -+ args.op = AMDGPU_GEM_DGMA_IMPORT; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_DGMA, -+ &args, sizeof(args)); -+ if (r) -+ return r; -+ -+ bo = calloc(1, sizeof(struct amdgpu_bo)); -+ if (!bo) -+ return -ENOMEM; -+ -+ atomic_set(&bo->refcount, 1); -+ pthread_mutex_init(&bo->cpu_access_mutex, NULL); -+ bo->dev = dev; -+ bo->alloc_size = size; -+ bo->handle = args.handle; -+ -+ *buf_handle = bo; -+ -+ return 0; -+} -+ -+int amdgpu_bo_get_phys_address(amdgpu_bo_handle buf_handle, -+ uint64_t *phys_address) -+{ -+ struct drm_amdgpu_gem_dgma args; -+ int r; -+ -+ args.op = AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR; -+ args.handle = buf_handle->handle; -+ r = drmCommandWriteRead(buf_handle->dev->fd, DRM_AMDGPU_GEM_DGMA, -+ &args, sizeof(args)); -+ if (r) -+ return r; -+ -+ *phys_address = args.addr; -+ return 0; -+} -+ - int amdgpu_bo_free(amdgpu_bo_handle buf_handle) - { - /* Just drop the reference. */ -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 14d800e..413a9dc 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -47,6 +47,7 @@ - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 - /* hybrid specific ioctls */ -+#define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d - #define DRM_AMDGPU_WAIT_FENCES 0x5e - #define DRM_AMDGPU_GEM_FIND_BO 0x5f -@@ -64,6 +65,7 @@ - #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) - #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) - /* hybrid specific ioctls */ -+#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -@@ -74,6 +76,7 @@ - #define AMDGPU_GEM_DOMAIN_GDS 0x8 - #define AMDGPU_GEM_DOMAIN_GWS 0x10 - #define AMDGPU_GEM_DOMAIN_OA 0x20 -+#define AMDGPU_GEM_DOMAIN_DGMA 0x40 - - /* Flag that CPU access will be required for the case of VRAM domain */ - #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) -@@ -209,6 +212,15 @@ struct drm_amdgpu_gem_userptr { - uint32_t handle; - }; - -+#define AMDGPU_GEM_DGMA_IMPORT 0 -+#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 -+struct drm_amdgpu_gem_dgma { -+ uint64_t addr; -+ uint64_t size; -+ uint32_t op; -+ uint32_t handle; -+}; -+ - struct drm_amdgpu_gem_find_bo { - uint64_t addr; - uint64_t size; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0116-tests-amdgpu-add-direct-gma-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0116-tests-amdgpu-add-direct-gma-test.patch deleted file mode 100644 index 4b6766bb..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0116-tests-amdgpu-add-direct-gma-test.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 331577c5a8736f15fdf55a7606414efcf78a5dff Mon Sep 17 00:00:00 2001 -From: Flora Cui <Flora.Cui@amd.com> -Date: Thu, 11 Aug 2016 15:26:16 +0800 -Subject: [PATCH 116/117] tests/amdgpu: add direct gma test - -Change-Id: Ib00252eff16a84f16f01039ff39f957bff903bae -Signed-off-by: Flora Cui <Flora.Cui@amd.com> ---- - tests/amdgpu/bo_tests.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 63 insertions(+), 1 deletion(-) - -diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c -index 195667f..5d1f67b 100644 ---- a/tests/amdgpu/bo_tests.c -+++ b/tests/amdgpu/bo_tests.c -@@ -26,6 +26,7 @@ - #endif - - #include <stdio.h> -+#include <inttypes.h> - - #include "CUnit/Basic.h" - -@@ -47,7 +48,7 @@ static void amdgpu_bo_export_import(void); - static void amdgpu_bo_metadata(void); - static void amdgpu_bo_map_unmap(void); - static void amdgpu_get_fb_id_and_handle(void); -- -+static void amdgpu_bo_direct_gma(void); - - CU_TestInfo bo_tests[] = { - { "Export/Import", amdgpu_bo_export_import }, -@@ -56,6 +57,7 @@ CU_TestInfo bo_tests[] = { - #endif - { "CPU map/unmap", amdgpu_bo_map_unmap }, - { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, -+ { "Direct GMA", amdgpu_bo_direct_gma }, - CU_TEST_INFO_NULL, - }; - -@@ -202,3 +204,63 @@ static void amdgpu_get_fb_id_and_handle(void) - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); - } -+ -+#define TEST_LOOP 20 -+static void amdgpu_bo_direct_gma(void) -+{ -+ amdgpu_bo_handle buf_handle[TEST_LOOP] = {0}; -+ amdgpu_bo_handle buf_handle_import[TEST_LOOP] = {0}; -+ uint32_t *ptr[TEST_LOOP] = {0}; -+ struct amdgpu_bo_alloc_request req = {0}; -+ struct drm_amdgpu_capability cap; -+ uint64_t size=4096, phys_addr, remain; -+ int i, j, r; -+ -+ amdgpu_query_capability(device_handle, &cap); -+ if(!(cap.flag & AMDGPU_CAPABILITY_DIRECT_GMA_FLAG)) -+ return; -+ -+ amdgpu_vprintf("direct_gma_size is %d MB\n", cap.direct_gma_size); -+ remain = cap.direct_gma_size << 20; -+ -+ req.preferred_heap = AMDGPU_GEM_DOMAIN_DGMA; -+ for (i = 0; i < TEST_LOOP; i++) { -+ req.alloc_size = size; -+ r = amdgpu_bo_alloc(device_handle, &req, &buf_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ r = amdgpu_bo_get_phys_address(buf_handle[i], &phys_addr); -+ CU_ASSERT_EQUAL(r, 0); -+ amdgpu_vprintf("bo_size %"PRIx64" phys_addr %"PRIx64"\n", size, phys_addr); -+ r = amdgpu_create_bo_from_phys_mem(device_handle, phys_addr, size, &buf_handle_import[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ r = amdgpu_bo_cpu_map(buf_handle_import[i], (void **)&ptr[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ -+ for (j = 0; j < (size / 4); ++j) -+ ptr[i][j] = 0xdeadbeef; -+ remain -= size; -+ size <<= 1; -+ amdgpu_vprintf("test loop %d finished, remain %"PRIx64", try to alloc %"PRIx64"\n", i, remain, size); -+ if (remain < size) -+ break; -+ -+ } -+ -+ for (i = 0; i < TEST_LOOP; i++) { -+ if (ptr[i]) { -+ r = amdgpu_bo_cpu_unmap(buf_handle_import[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ if (buf_handle_import[i]) { -+ r = amdgpu_bo_free(buf_handle_import[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ -+ if (buf_handle[i]) { -+ r = amdgpu_bo_free(buf_handle[i]); -+ CU_ASSERT_EQUAL(r, 0); -+ } -+ } -+} --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0117-Hybrid-Version-16.50.2.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0117-Hybrid-Version-16.50.2.patch deleted file mode 100644 index da54475e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0117-Hybrid-Version-16.50.2.patch +++ /dev/null @@ -1,23 +0,0 @@ -From a2a9ff1f0617d3be4d6eea18e3f089f4c6a985cf Mon Sep 17 00:00:00 2001 -From: Junshan Fang <Junshan.Fang@amd.com> -Date: Mon, 12 Sep 2016 19:07:53 +0800 -Subject: [PATCH 117/117] Hybrid Version: 16.50.2 - -Change-Id: I06971cc46278b68cf80ca39e67fb5f361d8f7cf5 -Signed-off-by: Junshan Fang <Junshan.Fang@amd.com> ---- - .version.hybrid | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/.version.hybrid b/.version.hybrid -index 0cc63be..0f578c1 100644 ---- a/.version.hybrid -+++ b/.version.hybrid -@@ -1,3 +1,3 @@ - HYBRID_VERSION_MAJOR = 16 - HYBRID_VERSION_MINOR = 50 --HYBRID_VERSION_PATCH = 1 -+HYBRID_VERSION_PATCH = 2 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0118-amdgpu-add-SI-support.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0118-amdgpu-add-SI-support.patch deleted file mode 100644 index 0444cd55..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0118-amdgpu-add-SI-support.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 9a0070dbf6669f3374787667fa6a6df9d5acb2ea Mon Sep 17 00:00:00 2001 -From: Ronie Salgado <roniesalg@gmail.com> -Date: Wed, 13 Apr 2016 21:56:15 +0200 -Subject: [PATCH 01/10] amdgpu: add SI support - ---- - amdgpu/amdgpu_gpu_info.c | 18 +++++++++++------- - include/drm/amdgpu_drm.h | 1 + - 2 files changed, 12 insertions(+), 7 deletions(-) - -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index 406baf2..d801b86 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -194,10 +194,12 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) - if (r) - return r; - -- r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0, -+ if (dev->info.family_id >= AMDGPU_FAMILY_CI) { -+ r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0, - &dev->info.pa_sc_raster_cfg1[i]); -- if (r) -- return r; -+ if (r) -+ return r; -+ } - } - - r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0, -@@ -205,10 +207,12 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) - if (r) - return r; - -- r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0, -- dev->info.gb_macro_tile_mode); -- if (r) -- return r; -+ if (dev->info.family_id >= AMDGPU_FAMILY_CI) { -+ r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0, -+ dev->info.gb_macro_tile_mode); -+ if (r) -+ return r; -+ } - - r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0, - &dev->info.gb_addr_cfg); -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 413a9dc..29a2393 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -708,6 +708,7 @@ struct drm_amdgpu_info_hw_ip { - * Supported GPU families - */ - #define AMDGPU_FAMILY_UNKNOWN 0 -+#define AMDGPU_FAMILY_SI 100 /* Tahiti, Pitcairn, CapeVerde, Oland, Hainan */ - #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ - #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ - #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0119-amdgpu-add-vram-memory-info.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0119-amdgpu-add-vram-memory-info.patch deleted file mode 100644 index a52e792d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0119-amdgpu-add-vram-memory-info.patch +++ /dev/null @@ -1,155 +0,0 @@ -From 4bbad6a36ed6416d254a8c0e4bbab07fe29a7acf Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 21 Sep 2016 10:43:40 +0800 -Subject: [PATCH 02/10] amdgpu: add vram memory info -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: Ic73eb5ad601496530be5e8c84a6c2b18aa43f0f1 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - amdgpu/amdgpu.h | 50 ++++++++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_gpu_info.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 107 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 8b87990..7b466dd 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -415,6 +415,40 @@ struct amdgpu_heap_info { - uint64_t max_allocation; - }; - -+struct amdgpu_heap_info2 { -+ /** max. physical memory */ -+ uint64_t total_heap_size; -+ -+ /** Theoretical max. available memory in the given heap */ -+ uint64_t usable_heap_size; -+ -+ /** -+ * Number of bytes allocated in the heap. This includes all processes -+ * and private allocations in the kernel. It changes when new buffers -+ * are allocated, freed, and moved. It cannot be larger than -+ * heap_size. -+ */ -+ uint64_t heap_usage; -+ -+ /** -+ * Theoretical possible max. size of buffer which -+ * could be allocated in the given heap -+ */ -+ uint64_t max_allocation; -+}; -+ -+/** -+ * Structure which provide information about heap -+ * -+ * \sa amdgpu_query_memory_info() -+ * -+ */ -+struct amdgpu_memory_info { -+ struct amdgpu_heap_info2 vram; -+ struct amdgpu_heap_info2 cpu_accessible_vram; -+ struct amdgpu_heap_info2 gtt; -+}; -+ - /** - * Describe GPU h/w info needed for UMD correct initialization - * -@@ -1141,6 +1175,22 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, - uint32_t flags, struct amdgpu_heap_info *info); - - /** -+ * Query memory information -+ * -+ * This query allows UMD to query potentially available memory resources -+ * and total memory size. -+ * -+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -+ * \param mem - \c [out] Pointer to structure to get memory information -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_query_memory_info(amdgpu_device_handle dev, -+ struct amdgpu_memory_info *mem); -+ -+/** - * Get the CRTC ID from the mode object ID - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index d801b86..d3796ac 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -243,6 +243,63 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev, - return 0; - } - -+int amdgpu_query_memory_info(amdgpu_device_handle dev, -+ struct amdgpu_memory_info *mem) -+{ -+ struct drm_amdgpu_info_vram_gtt vram_gtt_info = {}; -+ struct drm_amdgpu_info_vram_gtt_total vram_gtt_total_info = {}; -+ struct drm_amdgpu_info_vram_gtt_max vram_gtt_max_info = {}; -+ int r; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT, -+ sizeof(vram_gtt_info), &vram_gtt_info); -+ if (r) -+ return r; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_TOTAL, -+ sizeof(vram_gtt_total_info), &vram_gtt_total_info); -+ if (r) -+ return r; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_MAX, -+ sizeof(vram_gtt_max_info), &vram_gtt_max_info); -+ if (r) -+ return r; -+ -+ /* vram info */ -+ mem->vram.total_heap_size = vram_gtt_total_info.vram_total_size; -+ mem->vram.usable_heap_size = vram_gtt_info.vram_size; -+ mem->vram.max_allocation = vram_gtt_max_info.vram_max_size; -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE, -+ sizeof(mem->vram.heap_usage), -+ &mem->vram.heap_usage); -+ if (r) -+ return r; -+ -+ /* visible vram info */ -+ mem->cpu_accessible_vram.total_heap_size = vram_gtt_total_info.vram_cpu_accessible_total_size; -+ mem->cpu_accessible_vram.usable_heap_size = vram_gtt_info.vram_cpu_accessible_size; -+ mem->cpu_accessible_vram.max_allocation = vram_gtt_max_info.vram_cpu_accessible_max_size; -+ r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, -+ sizeof(mem->cpu_accessible_vram.heap_usage), -+ &mem->cpu_accessible_vram.heap_usage); -+ if (r) -+ return r; -+ -+ /* gtt info */ -+ mem->gtt.total_heap_size = vram_gtt_total_info.gtt_total_size; -+ mem->gtt.usable_heap_size = vram_gtt_info.gtt_size; -+ mem->gtt.max_allocation = vram_gtt_max_info.gtt_max_size; -+ -+ r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, -+ sizeof(mem->gtt.heap_usage), -+ &mem->gtt.heap_usage); -+ if (r) -+ return r; -+ -+ return 0; -+} -+ - int amdgpu_query_heap_info(amdgpu_device_handle dev, - uint32_t heap, - uint32_t flags, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0120-tests-amdgpu-add-vram-memory-info-test.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0120-tests-amdgpu-add-vram-memory-info-test.patch deleted file mode 100644 index 03f6087b..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0120-tests-amdgpu-add-vram-memory-info-test.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 15f3ca07aaf1a5836e79b7fe9324559689e3b57a Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Tue, 20 Sep 2016 14:15:59 +0800 -Subject: [PATCH 03/10] tests/amdgpu: add vram memory info test -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: If8f26c99f408fa2706ffc2f62ad17720d83e254c -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - tests/amdgpu/basic_tests.c | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index 3817d27..ce14786 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -402,6 +402,31 @@ static void amdgpu_query_heap_info_test(void) - amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); - } - -+static void amdgpu_query_memory_info_test(void) -+{ -+ struct amdgpu_memory_info mem; -+ -+ amdgpu_query_memory_info(device_handle, &mem); -+ -+ amdgpu_vprintf("\n VRAM memory info...\n"); -+ amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.vram.total_heap_size); -+ amdgpu_vprintf(" usable: 0x%"PRIx64"\n", mem.vram.usable_heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", mem.vram.heap_usage); -+ amdgpu_vprintf(" max: 0x%"PRIx64"\n", mem.vram.max_allocation); -+ -+ amdgpu_vprintf("\n Visible VRAM memory info...\n"); -+ amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.cpu_accessible_vram.total_heap_size); -+ amdgpu_vprintf(" usable: 0x%"PRIx64"\n", mem.cpu_accessible_vram.usable_heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", mem.cpu_accessible_vram.heap_usage); -+ amdgpu_vprintf(" max: 0x%"PRIx64"\n", mem.cpu_accessible_vram.max_allocation); -+ -+ amdgpu_vprintf("\n GTT memory info...\n"); -+ amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.gtt.total_heap_size); -+ amdgpu_vprintf(" usable: 0x%"PRIx64"\n", mem.gtt.usable_heap_size); -+ amdgpu_vprintf(" usage: 0x%"PRIx64"\n", mem.gtt.heap_usage); -+ amdgpu_vprintf(" max: 0x%"PRIx64"\n", mem.gtt.max_allocation); -+} -+ - static void amdgpu_query_info_test(void) - { - amdgpu_query_gpu_info_test(); -@@ -412,6 +437,7 @@ static void amdgpu_query_info_test(void) - amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); - amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); - amdgpu_query_heap_info_test(); -+ amdgpu_query_memory_info_test(); - } - - static void amdgpu_memory_alloc(void) --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch deleted file mode 100644 index 145b698e..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 5ccf817adb7c0c97423be0fa5250de412657c35a Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 21 Sep 2016 10:45:21 +0800 -Subject: [PATCH 04/10] amdgpu: add info about vram and gtt total size -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I2bafe801770831c615d9c610fc32609b404b69ac -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - include/drm/amdgpu_drm.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 29a2393..bf5f849 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -539,6 +539,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 -+/* Query the total size of VRAM and GTT domains */ -+#define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -631,6 +633,12 @@ struct drm_amdgpu_info_vram_gtt { - uint64_t gtt_size; - }; - -+struct drm_amdgpu_info_vram_gtt_total { -+ uint64_t vram_total_size; -+ uint64_t vram_cpu_accessible_total_size; -+ uint64_t gtt_total_size; -+}; -+ - struct drm_amdgpu_info_firmware { - uint32_t ver; - uint32_t feature; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch deleted file mode 100644 index ca6f16c5..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 25b333c8535f53a7763655332e6dd6fc61e6407c Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Wed, 21 Sep 2016 10:47:04 +0800 -Subject: [PATCH 05/10] amdgpu: add info about vram and gtt max allocation size -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I40d3be59d10e6c6a199b53b8d9e2d432943762dc -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> ---- - include/drm/amdgpu_drm.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index bf5f849..81a82c7 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -541,6 +541,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - /* Query the total size of VRAM and GTT domains */ - #define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 -+/* Query the max allocation size of VRAM and GTT domains */ -+#define AMDGPU_INFO_VRAM_GTT_MAX 0x1a - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -639,6 +641,12 @@ struct drm_amdgpu_info_vram_gtt_total { - uint64_t gtt_total_size; - }; - -+struct drm_amdgpu_info_vram_gtt_max { -+ uint64_t vram_max_size; -+ uint64_t vram_cpu_accessible_max_size; -+ uint64_t gtt_max_size; -+}; -+ - struct drm_amdgpu_info_firmware { - uint32_t ver; - uint32_t feature; --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0123-amdgpu-unify-memory-query-info-interface.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0123-amdgpu-unify-memory-query-info-interface.patch deleted file mode 100644 index 2a1a2ad8..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0123-amdgpu-unify-memory-query-info-interface.patch +++ /dev/null @@ -1,231 +0,0 @@ -From 87a889d35949d75e8cea19af8cc14e6ad75ac975 Mon Sep 17 00:00:00 2001 -From: Junwei Zhang <Jerry.Zhang@amd.com> -Date: Thu, 29 Sep 2016 09:36:16 +0800 -Subject: [PATCH 06/10] amdgpu: unify memory query info interface -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Change-Id: I683f52309bb5e821bd49105064a9fb7ba0c9d970 -Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> -Reviewed-by: Marek Olšák <marek.olsak@amd.com> ---- - amdgpu/amdgpu.h | 50 ---------------------------------------- - amdgpu/amdgpu_gpu_info.c | 57 ---------------------------------------------- - include/drm/amdgpu_drm.h | 38 +++++++++++++++++++++---------- - tests/amdgpu/basic_tests.c | 4 ++-- - 4 files changed, 28 insertions(+), 121 deletions(-) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 7b466dd..8b87990 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -415,40 +415,6 @@ struct amdgpu_heap_info { - uint64_t max_allocation; - }; - --struct amdgpu_heap_info2 { -- /** max. physical memory */ -- uint64_t total_heap_size; -- -- /** Theoretical max. available memory in the given heap */ -- uint64_t usable_heap_size; -- -- /** -- * Number of bytes allocated in the heap. This includes all processes -- * and private allocations in the kernel. It changes when new buffers -- * are allocated, freed, and moved. It cannot be larger than -- * heap_size. -- */ -- uint64_t heap_usage; -- -- /** -- * Theoretical possible max. size of buffer which -- * could be allocated in the given heap -- */ -- uint64_t max_allocation; --}; -- --/** -- * Structure which provide information about heap -- * -- * \sa amdgpu_query_memory_info() -- * -- */ --struct amdgpu_memory_info { -- struct amdgpu_heap_info2 vram; -- struct amdgpu_heap_info2 cpu_accessible_vram; -- struct amdgpu_heap_info2 gtt; --}; -- - /** - * Describe GPU h/w info needed for UMD correct initialization - * -@@ -1175,22 +1141,6 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap, - uint32_t flags, struct amdgpu_heap_info *info); - - /** -- * Query memory information -- * -- * This query allows UMD to query potentially available memory resources -- * and total memory size. -- * -- * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -- * \param mem - \c [out] Pointer to structure to get memory information -- * -- * \return 0 on success\n -- * <0 - Negative POSIX Error code -- * --*/ --int amdgpu_query_memory_info(amdgpu_device_handle dev, -- struct amdgpu_memory_info *mem); -- --/** - * Get the CRTC ID from the mode object ID - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c -index d3796ac..d801b86 100644 ---- a/amdgpu/amdgpu_gpu_info.c -+++ b/amdgpu/amdgpu_gpu_info.c -@@ -243,63 +243,6 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev, - return 0; - } - --int amdgpu_query_memory_info(amdgpu_device_handle dev, -- struct amdgpu_memory_info *mem) --{ -- struct drm_amdgpu_info_vram_gtt vram_gtt_info = {}; -- struct drm_amdgpu_info_vram_gtt_total vram_gtt_total_info = {}; -- struct drm_amdgpu_info_vram_gtt_max vram_gtt_max_info = {}; -- int r; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT, -- sizeof(vram_gtt_info), &vram_gtt_info); -- if (r) -- return r; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_TOTAL, -- sizeof(vram_gtt_total_info), &vram_gtt_total_info); -- if (r) -- return r; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT_MAX, -- sizeof(vram_gtt_max_info), &vram_gtt_max_info); -- if (r) -- return r; -- -- /* vram info */ -- mem->vram.total_heap_size = vram_gtt_total_info.vram_total_size; -- mem->vram.usable_heap_size = vram_gtt_info.vram_size; -- mem->vram.max_allocation = vram_gtt_max_info.vram_max_size; -- r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE, -- sizeof(mem->vram.heap_usage), -- &mem->vram.heap_usage); -- if (r) -- return r; -- -- /* visible vram info */ -- mem->cpu_accessible_vram.total_heap_size = vram_gtt_total_info.vram_cpu_accessible_total_size; -- mem->cpu_accessible_vram.usable_heap_size = vram_gtt_info.vram_cpu_accessible_size; -- mem->cpu_accessible_vram.max_allocation = vram_gtt_max_info.vram_cpu_accessible_max_size; -- r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, -- sizeof(mem->cpu_accessible_vram.heap_usage), -- &mem->cpu_accessible_vram.heap_usage); -- if (r) -- return r; -- -- /* gtt info */ -- mem->gtt.total_heap_size = vram_gtt_total_info.gtt_total_size; -- mem->gtt.usable_heap_size = vram_gtt_info.gtt_size; -- mem->gtt.max_allocation = vram_gtt_max_info.gtt_max_size; -- -- r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, -- sizeof(mem->gtt.heap_usage), -- &mem->gtt.heap_usage); -- if (r) -- return r; -- -- return 0; --} -- - int amdgpu_query_heap_info(amdgpu_device_handle dev, - uint32_t heap, - uint32_t flags, -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 81a82c7..430f239 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -539,10 +539,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 - /* virtual range */ - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 --/* Query the total size of VRAM and GTT domains */ --#define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 --/* Query the max allocation size of VRAM and GTT domains */ --#define AMDGPU_INFO_VRAM_GTT_MAX 0x1a -+/* Query memory about VRAM and GTT domains */ -+#define AMDGPU_INFO_MEMORY 0x19 - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -635,16 +633,32 @@ struct drm_amdgpu_info_vram_gtt { - uint64_t gtt_size; - }; - --struct drm_amdgpu_info_vram_gtt_total { -- uint64_t vram_total_size; -- uint64_t vram_cpu_accessible_total_size; -- uint64_t gtt_total_size; -+struct drm_amdgpu_heap_info { -+ /** max. physical memory */ -+ __u64 total_heap_size; -+ -+ /** Theoretical max. available memory in the given heap */ -+ __u64 usable_heap_size; -+ -+ /** -+ * Number of bytes allocated in the heap. This includes all processes -+ * and private allocations in the kernel. It changes when new buffers -+ * are allocated, freed, and moved. It cannot be larger than -+ * heap_size. -+ */ -+ __u64 heap_usage; -+ -+ /** -+ * Theoretical possible max. size of buffer which -+ * could be allocated in the given heap -+ */ -+ __u64 max_allocation; - }; - --struct drm_amdgpu_info_vram_gtt_max { -- uint64_t vram_max_size; -- uint64_t vram_cpu_accessible_max_size; -- uint64_t gtt_max_size; -+struct drm_amdgpu_memory_info { -+ struct drm_amdgpu_heap_info vram; -+ struct drm_amdgpu_heap_info cpu_accessible_vram; -+ struct drm_amdgpu_heap_info gtt; - }; - - struct drm_amdgpu_info_firmware { -diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c -index ce14786..094e9d0 100644 ---- a/tests/amdgpu/basic_tests.c -+++ b/tests/amdgpu/basic_tests.c -@@ -404,9 +404,9 @@ static void amdgpu_query_heap_info_test(void) - - static void amdgpu_query_memory_info_test(void) - { -- struct amdgpu_memory_info mem; -+ struct drm_amdgpu_memory_info mem; - -- amdgpu_query_memory_info(device_handle, &mem); -+ amdgpu_query_info(device_handle, AMDGPU_INFO_MEMORY, sizeof(mem), &mem); - - amdgpu_vprintf("\n VRAM memory info...\n"); - amdgpu_vprintf(" total: 0x%"PRIx64"\n", mem.vram.total_heap_size); --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0124-amdgpu-remove-redundant-wrong-marketing-name.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0124-amdgpu-remove-redundant-wrong-marketing-name.patch deleted file mode 100644 index 37503f06..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0124-amdgpu-remove-redundant-wrong-marketing-name.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 57f3ea2f6643a477a3f932b1fb5bd41ed50b9d58 Mon Sep 17 00:00:00 2001 -From: Evan Quan <evan.quan@amd.com> -Date: Wed, 28 Sep 2016 17:49:40 +0800 -Subject: [PATCH 07/10] amdgpu: remove redundant wrong marketing name - -Change-Id: I85df90e3bf5ac50335cb848cfa0ae9283e3f4ba4 -Signed-off-by: Evan Quan <evan.quan@amd.com> -Reviewed-by: Junwei Zhange <Jerry.Zhang@amd.com> ---- - amdgpu/amdgpu_asic_id.h | 5 ----- - 1 file changed, 5 deletions(-) - -diff --git a/amdgpu/amdgpu_asic_id.h b/amdgpu/amdgpu_asic_id.h -index 041ebe3..27e2acd 100644 ---- a/amdgpu/amdgpu_asic_id.h -+++ b/amdgpu/amdgpu_asic_id.h -@@ -87,16 +87,11 @@ struct amdgpu_asic_id_table_t { - {0x67C4, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, - {0x67C7, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67C0, 0x00, "AMD Radeon (TM) Pro WX 7100 Graphics"}, -- {0x67E0, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E0, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 4100 Graphics"}, -- {0x67E3, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, -- {0x67E8, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, -- {0x67E8, 0x01, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67E8, 0x01, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67E8, 0x80, "AMD Radeon (TM) E9260 Graphics"}, -- {0x67EB, 0x00, "AMD Radeon (TM) Pro WX 5100 Graphics"}, - {0x67EB, 0x00, "AMD Radeon (TM) Pro WX Series Graphics"}, - {0x67EF, 0xC0, "AMD Radeon (TM) RX Graphics"}, - {0x67EF, 0xC1, "AMD Radeon (TM) RX 460 Graphics"}, --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0125-amdgpu-add-new-semaphore-support.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0125-amdgpu-add-new-semaphore-support.patch deleted file mode 100644 index 92ebad65..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0125-amdgpu-add-new-semaphore-support.patch +++ /dev/null @@ -1,268 +0,0 @@ -From ce0b923b29ebb4d9b66bc864667308ec0969bf5b Mon Sep 17 00:00:00 2001 -From: Chunming Zhou <David1.Zhou@amd.com> -Date: Thu, 22 Sep 2016 14:50:16 +0800 -Subject: [PATCH 08/10] amdgpu: add new semaphore support - -Change-Id: Iae7e4157d6184dab1cd4a944ae9cb803f9b11670 -Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> -Reviewed-by: Monk Liu <monk.liu@amd.com> ---- - amdgpu/amdgpu.h | 74 +++++++++++++++++++++++++++++++++++++++ - amdgpu/amdgpu_cs.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++ - include/drm/amdgpu_drm.h | 29 ++++++++++++++++ - 3 files changed, 193 insertions(+) - -diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h -index 8b87990..7185bec 100644 ---- a/amdgpu/amdgpu.h -+++ b/amdgpu/amdgpu.h -@@ -137,6 +137,12 @@ typedef struct amdgpu_va *amdgpu_va_handle; - */ - typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; - -+/** -+ * Define handle for sem file -+ */ -+typedef int amdgpu_sem_handle; -+ -+ - /*--------------------------------------------------------------------------*/ - /* -------------------------- Structures ---------------------------------- */ - /*--------------------------------------------------------------------------*/ -@@ -1529,6 +1535,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, - int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); - - /** -+ * create sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_create_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle *sem); -+ -+/** -+ * signal sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ */ -+int amdgpu_cs_signal_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem); -+ -+/** -+ * wait sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param context - \c [in] GPU Context -+ * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* -+ * \param ip_instance - \c [in] Index of the IP block of the same type -+ * \param ring - \c [in] Specify ring index of the IP -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+*/ -+int amdgpu_cs_wait_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem); -+ -+/** -+ * destroy sem -+ * -+ * \param dev - [in] Device handle. See #amdgpu_device_initialize() -+ * \param sem - \c [out] sem handle -+ * -+ * \return 0 on success\n -+ * <0 - Negative POSIX Error code -+ * -+ */ -+int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle sem); -+ -+/** - * Get the ASIC marketing name - * - * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() -diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c -index b29e8c9..893f934 100644 ---- a/amdgpu/amdgpu_cs.c -+++ b/amdgpu/amdgpu_cs.c -@@ -25,6 +25,8 @@ - #include "config.h" - #endif - -+#include <sys/stat.h> -+#include <unistd.h> - #include <stdlib.h> - #include <stdio.h> - #include <string.h> -@@ -620,3 +622,91 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) - { - return amdgpu_cs_unreference_sem(sem); - } -+ -+int amdgpu_cs_create_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle *sem) -+{ -+ union drm_amdgpu_sem args; -+ int r; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_CREATE_SEM; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+ if (r) -+ return r; -+ -+ *sem = args.out.fd; -+ -+ return 0; -+} -+ -+int amdgpu_cs_signal_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem) -+{ -+ union drm_amdgpu_sem args; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_SIGNAL_SEM; -+ args.in.ctx_id = ctx->id; -+ args.in.ip_type = ip_type; -+ args.in.ip_instance = ip_instance; -+ args.in.ring = ring; -+ args.in.fd = sem; -+ return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+} -+ -+int amdgpu_cs_wait_sem(amdgpu_device_handle dev, -+ amdgpu_context_handle ctx, -+ uint32_t ip_type, -+ uint32_t ip_instance, -+ uint32_t ring, -+ amdgpu_sem_handle sem) -+{ -+ union drm_amdgpu_sem args; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_WAIT_SEM; -+ args.in.ctx_id = ctx->id; -+ args.in.ip_type = ip_type; -+ args.in.ip_instance = ip_instance; -+ args.in.ring = ring; -+ args.in.fd = sem; -+ args.in.seq = 0; -+ return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+} -+ -+int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, -+ amdgpu_sem_handle sem) -+{ -+ union drm_amdgpu_sem args; -+ int r; -+ -+ if (NULL == dev) -+ return -EINVAL; -+ -+ /* Create the context */ -+ memset(&args, 0, sizeof(args)); -+ args.in.op = AMDGPU_SEM_OP_DESTROY_SEM; -+ args.in.fd = sem; -+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); -+ if (r) -+ return r; -+ close(sem); -+ return 0; -+} -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index 430f239..dfde605 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -47,6 +47,7 @@ - #define DRM_AMDGPU_GEM_OP 0x10 - #define DRM_AMDGPU_GEM_USERPTR 0x11 - /* hybrid specific ioctls */ -+#define DRM_AMDGPU_SEM 0x5b - #define DRM_AMDGPU_GEM_DGMA 0x5c - #define DRM_AMDGPU_FREESYNC 0x5d - #define DRM_AMDGPU_WAIT_FENCES 0x5e -@@ -69,6 +70,7 @@ - #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) - #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) - #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) -+#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) - - #define AMDGPU_GEM_DOMAIN_CPU 0x1 - #define AMDGPU_GEM_DOMAIN_GTT 0x2 -@@ -193,6 +195,33 @@ union drm_amdgpu_ctx { - union drm_amdgpu_ctx_out out; - }; - -+/* sync file related */ -+#define AMDGPU_SEM_OP_CREATE_SEM 1 -+#define AMDGPU_SEM_OP_WAIT_SEM 2 -+#define AMDGPU_SEM_OP_SIGNAL_SEM 3 -+#define AMDGPU_SEM_OP_DESTROY_SEM 4 -+ -+struct drm_amdgpu_sem_in { -+ /** AMDGPU_SEM_OP_* */ -+ uint32_t op; -+ int fd; -+ uint32_t ctx_id; -+ uint32_t ip_type; -+ uint32_t ip_instance; -+ uint32_t ring; -+ uint64_t seq; -+}; -+ -+union drm_amdgpu_sem_out { -+ int fd; -+ uint32_t _pad; -+}; -+ -+union drm_amdgpu_sem { -+ struct drm_amdgpu_sem_in in; -+ union drm_amdgpu_sem_out out; -+}; -+ - /* - * This is not a reliable API and you should expect it to fail for any - * number of reasons and have fallback path that do not use userptr to --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0126-amdgpu-new-ids-flag-for-preempt.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0126-amdgpu-new-ids-flag-for-preempt.patch deleted file mode 100644 index 1acd368d..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0126-amdgpu-new-ids-flag-for-preempt.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 6ecbb275511558539eb3126effd61f0ba21b9513 Mon Sep 17 00:00:00 2001 -From: Monk Liu <Monk.Liu@amd.com> -Date: Mon, 24 Oct 2016 11:36:35 +0800 -Subject: [PATCH 09/10] amdgpu:new ids flag for preempt - -Change-Id: I59ffac9728c0e83bc7fd61aa371126dd30691bcb -Signed-off-by: Monk Liu <Monk.Liu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - include/drm/amdgpu_drm.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index dfde605..d40742e 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -517,6 +517,7 @@ struct drm_amdgpu_cs_chunk_data { - * - */ - #define AMDGPU_IDS_FLAGS_FUSION 0x1 -+#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 - - /* indicate if acceleration can be working */ - #define AMDGPU_INFO_ACCEL_WORKING 0x00 --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm-2.4.66/0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch b/common/recipes-graphics/drm/libdrm-2.4.66/0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch deleted file mode 100644 index eb62bd42..00000000 --- a/common/recipes-graphics/drm/libdrm-2.4.66/0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 3002e9518ee9b3660f4bd676c546785364885f3c Mon Sep 17 00:00:00 2001 -From: Arindam Nath <arindam.nath@amd.com> -Date: Mon, 9 Jan 2017 14:56:25 +0530 -Subject: [PATCH 10/10] amdgpu: sync amdgpu_drm.h with the kernel -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -v1: -* User might want to query the maximum number of UVD - instances supported by firmware. In addition to that, - if there are multiple applications using UVD handles - at the same time, he might also want to query the - currently used number of handles. - - For this we add a new query AMDGPU_INFO_NUM_HANDLES - and a new struct drm_amdgpu_info_num_handles to - get these values. - -v2: -* Generated using make headers_install. -* Generated from linux-stable/master commit - a121103c922847ba5010819a3f250f1f7fc84ab8 - -Suggested-by: Emil Velikov <emil.l.velikov@gmail.com> -Signed-off-by: Arindam Nath <arindam.nath@amd.com> -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by:Raveendra Talabattula <raveendra.talabattula@amd.com> ---- - include/drm/amdgpu_drm.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h -index d40742e..8272f93 100644 ---- a/include/drm/amdgpu_drm.h -+++ b/include/drm/amdgpu_drm.h -@@ -571,6 +571,8 @@ struct drm_amdgpu_cs_chunk_data { - #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 - /* Query memory about VRAM and GTT domains */ - #define AMDGPU_INFO_MEMORY 0x19 -+/* Query UVD handles */ -+#define AMDGPU_INFO_NUM_HANDLES 0x1C - - /* gpu capability */ - #define AMDGPU_INFO_CAPABILITY 0x50 -@@ -764,6 +766,13 @@ struct drm_amdgpu_info_hw_ip { - uint32_t _pad; - }; - -+struct drm_amdgpu_info_num_handles { -+ /** Max handles as supported by firmware for UVD */ -+ uint32_t uvd_max_handles; -+ /** Handles currently in use for UVD */ -+ uint32_t uvd_used_handles; -+}; -+ - /* - * Supported GPU families - */ --- -2.7.4 - diff --git a/common/recipes-graphics/drm/libdrm_2.4.66.bb b/common/recipes-graphics/drm/libdrm_2.4.66.bb deleted file mode 100644 index c4c3bd61..00000000 --- a/common/recipes-graphics/drm/libdrm_2.4.66.bb +++ /dev/null @@ -1,160 +0,0 @@ -SUMMARY = "Userspace interface to the kernel DRM services" -DESCRIPTION = "The runtime library for accessing the kernel DRM services. DRM \ -stands for \"Direct Rendering Manager\", which is the kernel portion of the \ -\"Direct Rendering Infrastructure\" (DRI). DRI is required for many hardware \ -accelerated OpenGL drivers." -HOMEPAGE = "http://dri.freedesktop.org" -SECTION = "x11/base" -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://xf86drm.c;beginline=9;endline=32;md5=c8a3b961af7667c530816761e949dc71" -PROVIDES = "drm" -DEPENDS = "libpthread-stubs udev libpciaccess freetype libxext cairo fontconfig libxrender libpng pixman" - -SRC_URI_amd = "http://dri.freedesktop.org/libdrm/${BP}.tar.bz2 \ - file://0001-tests-also-install-tests-app.patch \ - file://0004-amdgpu-drop-address-patching-logics.patch \ - file://0005-amdgpu-validate-user-memory-for-userptr.patch \ - file://0006-amdgpu-add-semaphore-support.patch \ - file://0008-amdgpu-list-each-entry-safely-for-sw-semaphore-when-.patch \ - file://0046-amdgpu-fix-for-submition-with-no-ibs.patch \ - file://0001-intel-kbl-Add-Kabylake-PCI-ids.patch \ - file://0002-Fix-memory-leak-with-drmModeGetConnectorCurrent.patch \ - file://0003-configure.ac-disable-annoying-warning-Wmissing-field.patch \ - file://0007-tests-amdgpu-add-semaphore-test.patch \ - file://0009-amdgpu-Add-new-symbols-to-amdgpu-symbols-check.patch \ - file://0010-radeon-Pass-radeon_bo_open-flags-to-the-DRM_RADEON_G.patch \ - file://0011-xf86drm-Bound-strstr-to-the-allocated-data.patch \ - file://0012-configure.ac-don-t-detect-disabled-options-dependenc.patch \ - file://0013-kmstest-Use-util_open.patch \ - file://0014-tests-add-fsl-dcu-drm-to-modules.patch \ - file://0015-tests-util-Fixup-util_open-parameter-order.patch \ - file://0016-tests-Include-sys-select.h.patch \ - file://0017-tests-Include-poll.h-rather-than-sys-poll.h.patch \ - file://0018-tests-kmstest-inverse-the-order-of-LDADD-libraries.patch \ - file://0019-vc4-Add-the-DRM-header-file.patch \ - file://0020-util-Add-support-for-vc4.patch \ - file://0021-vc4-Add-headers-and-.pc-files-for-VC4-userspace-deve.patch \ - file://0022-amdgpu-add-libdrm-as-private-requirement-dependency.patch \ - file://0023-radeon-add-libdrm-to-Requires.private.patch \ - file://0024-libkms-add-libdrm-to-Requires.private.patch \ - file://0025-android-enable-building-static-version-of-libdrm.patch \ - file://0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch \ - file://0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch \ - file://0028-amdgpu-add-query-for-aperture-va-range.patch \ - file://0029-amdgpu-Implement-SVM-v2.patch \ - file://0030-amdgpu-SVM-test-v2.patch \ - file://0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch \ - file://0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch \ - file://0033-tests-amdgpu-Add-verbose-outputs-v2.patch \ - file://0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch \ - file://0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch \ - file://0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch \ - file://0037-tests-amdgpu-add-the-heap-info-for-query.patch \ - file://0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch \ - file://0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch \ - file://0040-amdgpu-add-query-amdgpu-capability-defination.patch \ - file://0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch \ - file://0042-amdgpu-add-amdgpu_query_capability-interface.patch \ - file://0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch \ - file://0044-amdgpu-support-alloc-va-from-range.patch \ - file://0045-tests-amdgpu-add-alloc-va-from-range-test.patch \ - file://0047-tests-amdgpu-move-va_range_test-above-svm_test.patch \ - file://0048-amdgpu-add-the-function-to-get-the-marketing-name.patch \ - file://0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch \ - file://0050-amdgpu-tests-Fiji-VCE-is-one-instance.patch \ - file://0052-amdgpu-hybrid-update-the-gpu-marketing-name-table.patch \ - file://0053-Hybrid-Version-16.30.2.patch \ - file://0054-tests-amdgpu-add-interface-to-adapt-firmware-require.patch \ - file://0055-tests-amdgpu-adapt-to-new-polaris10-11-uvd-fw.patch \ - file://0056-amdgpu-change-max-allocation.patch \ - file://0057-amdgpu-fix-print-format-error-V2.patch \ - file://0058-Hybrid-Version-16.30.3.patch \ - file://0059-drm-fix-multi-GPU-drmGetDevices-only-return-one-devi.patch \ - file://0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch \ - file://0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch \ - file://0065-Hybrid-Version-16.30.4.patch \ - file://0066-amdgpu-add-marketing-name-for-RX480-RX470.patch \ - file://0068-Hybrid-Version-16.40.1.patch \ - file://0069-Hybrid-Version-16.40.2.patch \ - file://0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch \ - file://0071-Hybrid-Version-16.40.3.patch \ - file://0072-amdgpu-add-marketing-name-for-RX460.patch \ - file://0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch \ - file://0074-drm-fix-a-bug-in-va-range-allocation.patch \ - file://0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch \ - file://0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch \ - file://0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch \ - file://0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch \ - file://0081-Hybrid-Version-16.40.4.patch \ - file://0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch \ - file://0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch \ - file://0084-drm-Fix-multi-GPU-drmGetDevice-return-wrong-device.patch \ - file://0085-drm-fix-multi-GPU-drmFreeDevices-memory-leak.patch \ - file://0086-drm-add-marketing-names.patch \ - file://0087-Hybrid-Version-16.40.5.patch \ - file://0088-drm-add-marketing-name.patch \ - file://0089-Hybrid-Version-16.40.6.patch \ - file://0090-amdgpu-change-AMDGPU_GEM_CREATE_NO_EVICT-flag-defini.patch \ - file://0092-drm-add-marketing-names.patch \ - file://0095-drm-update-marketing-names.patch \ - file://0097-drm-add-marketing-name.patch \ - file://0099-amdgpu-add-the-copyright-and-macros-for-the-asic-id-.patch \ - file://0100-Hybrid-Version-16.40.7.patch \ - file://0101-drm-change-the-marketing-name.patch \ - file://0103-amdgpu-expose-the-AMDGPU_GEM_CREATE_VRAM_CLEARED-fla.patch \ - file://0104-drm-amdgpu-add-freesync-ioctl-defines.patch \ - file://0106-amdgpu-move-hybrid-specific-ioctl-to-the-end.patch \ - file://0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch \ - file://0109-amdgpu-tests-remove-debug-info-in-cs-test.patch \ - file://0110-drm-amdgpu-move-freesync-ioctl-to-hybrid-specific-ra.patch \ - file://0112-Hybrid-Version-16.50.0.patch \ - file://0113-Hybrid-Version-16.50.1.patch \ - file://0114-amdgpu-add-more-capability-query.patch \ - file://0115-amdgpu-implement-direct-gma.patch \ - file://0116-tests-amdgpu-add-direct-gma-test.patch \ - file://0117-Hybrid-Version-16.50.2.patch \ - file://0118-amdgpu-add-SI-support.patch \ - file://0119-amdgpu-add-vram-memory-info.patch \ - file://0120-tests-amdgpu-add-vram-memory-info-test.patch \ - file://0121-amdgpu-add-info-about-vram-and-gtt-total-size.patch \ - file://0122-amdgpu-add-info-about-vram-and-gtt-max-allocation-si.patch \ - file://0123-amdgpu-unify-memory-query-info-interface.patch \ - file://0124-amdgpu-remove-redundant-wrong-marketing-name.patch \ - file://0125-amdgpu-add-new-semaphore-support.patch \ - file://0126-amdgpu-new-ids-flag-for-preempt.patch \ - file://0127-amdgpu-sync-amdgpu_drm.h-with-the-kernel.patch \ -" -SRC_URI[md5sum] = "c6809c48538d6e5999588832045ff014" -SRC_URI[sha256sum] = "79cb8e988749794edfb2d777b298d5292eff353bbbb71ed813589e61d2bc2d76" - -inherit autotools pkgconfig - -EXTRA_OECONF += "--disable-cairo-tests \ - --enable-omap-experimental-api \ - --enable-install-test-programs \ - --disable-manpages \ - --disable-valgrind \ - --enable-amdgpu \ - --enable-radeon \ - " - -ALLOW_EMPTY_${PN}-drivers = "1" -PACKAGES =+ "${PN}-tests ${PN}-drivers ${PN}-radeon ${PN}-nouveau ${PN}-omap \ - ${PN}-intel ${PN}-exynos ${PN}-kms ${PN}-freedreno ${PN}-amdgpu" - -RRECOMMENDS_${PN}-drivers = "${PN}-radeon ${PN}-nouveau ${PN}-omap ${PN}-intel \ - ${PN}-exynos ${PN}-freedreno ${PN}-amdgpu" - -FILES_${PN}-tests = "${bindir}/dr* ${bindir}/mode* ${bindir}/*test" -FILES_${PN}-radeon = "${libdir}/libdrm_radeon.so.*" -FILES_${PN}-nouveau = "${libdir}/libdrm_nouveau.so.*" -FILES_${PN}-omap = "${libdir}/libdrm_omap.so.*" -FILES_${PN}-intel = "${libdir}/libdrm_intel.so.*" -FILES_${PN}-exynos = "${libdir}/libdrm_exynos.so.*" -FILES_${PN}-kms = "${libdir}/libkms*.so.*" -FILES_${PN}-freedreno = "${libdir}/libdrm_freedreno.so.*" -FILES_${PN}-amdgpu = "${libdir}/libdrm_amdgpu.so.*" - -do_install_append_amd() { - cp ${S}/include/drm/amdgpu_drm.h ${D}/usr/include/libdrm -} diff --git a/meta-amdfalconx86/conf/machine/amdfalconx86.conf b/meta-amdfalconx86/conf/machine/amdfalconx86.conf index 81c1f235..5e1de8af 100644 --- a/meta-amdfalconx86/conf/machine/amdfalconx86.conf +++ b/meta-amdfalconx86/conf/machine/amdfalconx86.conf @@ -5,7 +5,6 @@ PREFERRED_PROVIDER_virtual/kernel ?= "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "linux-yocto-rt", "linux-yocto", d)}" PREFERRED_VERSION_linux-yocto-rt ?= "4.4%" -PREFERRED_VERSION_libdrm ?= "2.4.66" require conf/machine/include/tune-amdfalconx86.inc |