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-rw-r--r--RELEASE.md58
-rw-r--r--SETUP.md2
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.binbin49664 -> 86528 bytes
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.binbin9344 -> 9344 bytes
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.binbin17536 -> 17536 bytes
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.binbin268048 -> 268048 bytes
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.binbin268048 -> 268048 bytes
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.binbin21632 -> 21632 bytes
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.binbin17408 -> 17408 bytes
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch210
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch42
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch39
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch30
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch50
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch93
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch73
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch144
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch138
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch87
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch68
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch138
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch86
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch37
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch35
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch122
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch122
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch88
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch91
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch58
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch42
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch32
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch121
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch914
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch92
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch205
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch38
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch53
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch273
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch99
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch142
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch40
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch31
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch376
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch31
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch64
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch225
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch40
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch62
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch35
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch31
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch54
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch60
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch100
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch44
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch44
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch44
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch44
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch44
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch83
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch302
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch100
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch300
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch80
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch309
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch309
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch446
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch43
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch230
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch41
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch43
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch546
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch467
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch37
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch63
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch64
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch449
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch668
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch207
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch66
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch87
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4178-drm-amd-display-fix-incorrect-page-table-address-for.patch59
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch92
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch32
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch41
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch31
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch27
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4184-drm-amd-display-update-dcn21-hubbub-registers.patch59
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch88
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch36
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch62
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch31
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch61
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch50
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch43
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4192-drm-amd-display-enable-smu-set-dcfclk.patch43
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch56
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4194-drm-amd-display-handle-dp-is-usb-c.patch204
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch28
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4196-drm-amd-display-Make-dc_link_detect_helper-static.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4197-drm-amdgpu-soc15-remove-unused-variables.patch28
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch31
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch134
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch135
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch134
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch69
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch50
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4205-drm-amdgpu-psp11-fix-typo-in-comment.patch27
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch55
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch101
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch83
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch64
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch227
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch157
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch135
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch246
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch114
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch121
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch30
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch39
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch106
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4219-drm-amdgpu-vce-make-some-functions-static.patch77
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch133
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch30
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch44
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch49
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch75
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644 files changed, 86921 insertions, 32 deletions
diff --git a/RELEASE.md b/RELEASE.md
index e2c39467..7b9c20ff 100644
--- a/RELEASE.md
+++ b/RELEASE.md
@@ -1,16 +1,16 @@
# Release notes
-This is the release notes document for the AMD BSP V1000. This document
+This is the release notes document for the AMD BSP R1000. This document
contains information about the Yocto layers' git repos, their branches
and commit hashes, software versions, and known/fixed issues/limitations.
## Layers
| Layer | Git Repo | Branch | Commit Hash |
|:------------------|:---------------------------------------------|:--------|:-----------------------------------------|
-| poky | git://git.yoctoproject.org/poky | warrior | 79a850a10a4b88a6d20d607b322542f947874323 |
-| meta-openembedded | git://git.openembedded.org/meta-openembedded | warrior | f4ccdf2bc3fe4f00778629088baab840c868e36b |
+| poky | git://git.yoctoproject.org/poky | warrior | 023ff85a9ae94331926e923b346fd8a349881e63 |
+| meta-openembedded | git://git.openembedded.org/meta-openembedded | warrior | a24acf94d48d635eca668ea34598c6e5c857e3f8 |
| meta-dpdk | git://git.yoctoproject.org/meta-dpdk | warrior | c8c30c2c4e2f36b4a55a69a475fe774015423705 |
-| meta-amd | git://git.yoctoproject.org/meta-amd | warrior | tags/warrior-v1000-ga-201912 |
+| meta-amd | git://git.yoctoproject.org/meta-amd | warrior | tags/warrior-r1000-ga-202002 |
## Softwares
| Software | Version |
@@ -40,32 +40,28 @@ and commit hashes, software versions, and known/fixed issues/limitations.
| rgp | 1.5.1 |
## Fixed Issues
-| # V1000 Fixed Issues # |
-|:------------------------------------------------------------------------------------|
-| Hard hang with mpv vaapi-vappi configuration in fullscreen mode on V1000 |
-| Stutter observed with 4k@60 video playback on V1000 |
-| Display goes blank after hotplug of third monitor on V1000 |
-| Glmark2 overnight hang |
-| I2S Audio one side of headset is not audible while playing i2S audio on V1000/R1000 |
+| R1000 Fixed Issues |
+|:--------------------------------------------------------------------------------------------------------------------------------|
+| APU power consumption for static idle cases is on par with windows on Raven platforms. |
+| Heavy stutter and tearing observed with skype video conference on R1000 LP. |
+| [XGBE]: Peer to Peer network is unstable with 1/10G SFP (FC). |
+| [XGBE]: RJ45 Hotplug of XGBE function is not working. |
+| [XGBE]: Ethernet Link is showing always up on RJ45 ports of Bilby platforms. |
+| [XGBE]: Hot plug failures and stability issue with longer duration performance test on Bilby platforms with RG45 ports enabled. |
## Known Issues
-| # V1000 Known Issues/Limitations # |
-|:----------------------------------------------------------------------------------------------------------------------|
-| Stuttering is observed with vulkan hologram sample on 4k monitor full screen mode |
-| S3 fails at 25th cycle on Dibbler V1000 due to PSP bug |
-| Display artifacts while doing S3 with max 4k monitors on APU’s |
-| __* XGBE__ |
-| SFP wont work on V1807 platforms after few hours |
-| Ethernet link is showing always up on RJ45 ports of Bilby platforms |
-| _** Workaround: Disable the port which is not connected the ethernet cable_ |
-| Hotplug failures and stability issue with longer duration performance test on Bilby platforms with RJ45 ports enabled |
-| _** Workaround: Disable the port which is not connected the ethernet cable_ |
-| Can’t concurrently enable SFP+ and RJ45 interfaces |
-| Peer to Peer network is unstable with 1/10G SFP (FC) |
-| No IEEE 1588 Timestamp support |
-| No receive split header support |
-| __* Following features should be functional but have not been fully validated:__ |
-| *** Priority and VLAN (VLAN Priority Control) |
-| *** RMON Counter |
-| *** VLAN support and Receive-Side scaling |
-| *** 2.5G TCP/IP offload (duplex) and 2.5G jumbo frames (duplex) |
+| __* R1000 LP Known Issues/Limitations__ |
+|:-------------------------------------------------------------------------------------------------------------------------|
+| Stutter and frame drops observed 4k video playback. |
+| Minor Tearing is observed while doing skype video calling in fullscreen. |
+| Heavy stutters and framedrops observed after resuming from sleep. |
+| Heavy stutter in slideshow presentation and Multimedia playback in dual monitor usecase. |
+| Randomly video playback with S3 fails while doing manually on R1000LP. Workaround mentioned in R1000 issues list below. |
+| __* R1000 Known Issues/Limitations__ |
+| 1. Randomly Network is disabled after every suspend and resume on Raven platforms. |
+| SFP Port-0 is not getting detected for 10G RJ45 SFP Transceiver on Raven Platforms. |
+| SFP Port-0 is not getting detected for 2.5G network usecases on Raven Platforms. |
+| Soft hang observed on Video Playback and S3 in MST (Daisy Chain). |
+| Not showing GPU Load in amdgpu_pm_info sysfs entry on V1000 and R1000/LP. |
+| User experience is very poor after hotplug on mGPU config with more than 6 monitors. |
+| Stuttering is observed with vulkan hologram sample on 4k monitor full screen mode. |
diff --git a/SETUP.md b/SETUP.md
index e1a10f89..e0e9a6de 100644
--- a/SETUP.md
+++ b/SETUP.md
@@ -48,7 +48,7 @@ git checkout --quiet a24acf94d48d635eca668ea34598c6e5c857e3f8
cd ../meta-dpdk
git checkout --quiet c8c30c2c4e2f36b4a55a69a475fe774015423705
cd ../meta-amd
-git checkout --quiet HEAD
+git checkout --quiet tags/warrior-r1000-ga-202002
cd ..
```
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin
index 186cb5b4..2c4cda74 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin
Binary files differ
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin
index 015bb206..5e915181 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin
Binary files differ
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin
index b2e0ec2d..3abf70a0 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin
Binary files differ
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin
index 5b68507f..738dc4c5 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin
Binary files differ
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin
index 5b68507f..738dc4c5 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin
Binary files differ
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin
index 17597231..77caf229 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin
Binary files differ
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin
index 80e4fb65..139b9553 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin
Binary files differ
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch
new file mode 100644
index 00000000..447629ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch
@@ -0,0 +1,210 @@
+From 89a9f6eee64e54ce282584cfc7bedcdd944f7c4b Mon Sep 17 00:00:00 2001
+From: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com>
+Date: Tue, 12 Nov 2019 18:15:16 +0530
+Subject: [PATCH 4103/4736] modifying link and led state with respect to cable
+ connection
+
+ Enable Marvell PHY 10G linkup on Bilby. The current
+ 10G linkup happens only in backplane mode, meaning there will be no sideband
+ to talk to the external PHY connected onboard. So, when the driver reads the
+ port property as BACKPLANE, technically we are not supposed to go and read
+ what is the external PHY connected through MDIO. This changes are only a
+ workaround to read the external phy through MDIO in backplane mode.
+---
+ drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 30 ++++++--
+ drivers/net/phy/marvell10g.c | 80 ++++++++++++++++++++-
+ 2 files changed, 105 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+index 9cddcc8433e1..a6fb6754984f 100755
+--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+@@ -156,6 +156,11 @@
+ /* RRC frequency during link status check */
+ #define XGBE_RRC_FREQUENCY 10
+
++/* Enable Marvell PHY writes by forcing the MDIO connections */
++static int force_mdio_mv_bp_con = 1;
++module_param(force_mdio_mv_bp_con, uint, 0644);
++MODULE_PARM_DESC(force_mdio_mv_bp_con,
++ " Enable Marvell PHY writes by forcing the MDIO connections");
+ enum xgbe_port_mode {
+ XGBE_PORT_MODE_RSVD = 0,
+ XGBE_PORT_MODE_BACKPLANE,
+@@ -985,8 +990,15 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ pdata->an_again = 0;
+
+ /* Check for the use of an external PHY */
+- if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
+- return 0;
++ if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
++ if(force_mdio_mv_bp_con) {
++ phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
++ phy_data->conn_type = XGBE_CONN_TYPE_MDIO;
++ netif_dbg(pdata, drv, pdata->netdev, "*** DEBUG: %s - bypass phydev_mode check\n", __func__);
++ } else {
++ return 0;
++ }
++ }
+
+ /* For SFP, only use an external PHY if available */
+ if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
+@@ -1011,7 +1023,7 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ return -ENODEV;
+ }
+ netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
+- phydev->phy_id);
++ (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45) ? phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] : phydev->phy_id);
+
+ /*TODO: If c45, add request_module based on one of the MMD ids? */
+
+@@ -1034,6 +1046,14 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+
+ xgbe_phy_external_phy_quirks(pdata);
+
++ if(force_mdio_mv_bp_con) {
++ phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
++ phy_data->conn_type = XGBE_CONN_TYPE_BACKPLANE;
++ netif_dbg(pdata, drv, pdata->netdev, "phy_dev removed!\n");
++ xgbe_phy_free_phy_device(pdata);
++ return 0;
++ }
++
+ ethtool_convert_link_mode_to_legacy_u32(&advertising,
+ lks->link_modes.advertising);
+ phydev->advertising &= advertising;
+@@ -2551,8 +2571,10 @@ static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
+ return 0;
+
+ if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
+- !phy_aneg_done(phy_data->phydev))
++ !phy_aneg_done(phy_data->phydev)) {
++ netif_dbg(pdata, drv, pdata->netdev,"%s Ext phy AN not complete!\n", __func__);
+ return 0;
++ }
+
+ if (!phy_data->phydev->link)
+ return 0;
+diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
+index f77a2d9e7f9d..080272a3d2b6 100644
+--- a/drivers/net/phy/marvell10g.c
++++ b/drivers/net/phy/marvell10g.c
+@@ -25,6 +25,7 @@
+ #include <linux/hwmon.h>
+ #include <linux/marvell_phy.h>
+ #include <linux/phy.h>
++#include <linux/delay.h>
+
+ enum {
+ MV_PCS_BASE_T = 0x0000,
+@@ -48,7 +49,12 @@ enum {
+ MV_V2_TEMP_CTRL_MASK = 0xc000,
+ MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
+ MV_V2_TEMP_CTRL_DISABLE = 0xc000,
++ MV_V2_MODE_CFG = 0xf000,
++ MV_V2_PORT_CTRL = 0xf001,
++ MV_V2_LED0_CTRL = 0xf020,
+ MV_V2_TEMP = 0xf08c,
++ MV_V2_HOST_KR_ENABLE = 0xf084,
++ MV_V2_HOST_KR_TUNE = 0xf07c,
+ MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
+ };
+
+@@ -75,7 +81,7 @@ static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
+ return ret < 0 ? ret : 1;
+ }
+
+-#ifdef CONFIG_HWMON
++#ifdef CONFIG_HWMON_MV
+ static umode_t mv3310_hwmon_is_visible(const void *data,
+ enum hwmon_sensor_types type,
+ u32 attr, int channel)
+@@ -249,6 +255,77 @@ static int mv3310_resume(struct phy_device *phydev)
+ return mv3310_hwmon_config(phydev, true);
+ }
+
++
++/* Some PHYs within the Alaska family like 88x3310 has problems with the
++ * KR Auto-negotiation. marvell datasheet for 88x3310 section 6.2.11 says that
++ * KR auto-negotitaion can be enabled to adapt to the incoming SERDES by writing
++ * to autoneg registers and the PMA/PMD registers
++ */
++static int mv3310_amd_quirk(struct phy_device *phydev)
++{
++ int reg=0, count=0;
++ int version, subversion;
++
++ version = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 0xC011);
++ subversion = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 0xC012);
++ dev_dbg(&phydev->mdio.dev,"%s: Marvell FW Version: %x.%x \n", __func__, version, subversion);
++
++ if(subversion != 0x400)
++ return 0;
++
++ reg = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_ENABLE);
++ reg |= 0x8000;
++ phy_write_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_ENABLE, reg);
++
++ reg = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_TUNE);
++ reg = (reg & ~0x8000) | 0x4000;
++ phy_write_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_TUNE, reg);
++
++ if((reg & BIT(8)) && (reg & BIT(11))) {
++ reg = phy_read_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R);
++ /* disable BASE-R */
++ phy_write_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R, reg);
++ } else {
++ reg = phy_read_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R);
++ /* enable BASE-R for KR initiation */
++ reg |= 0x1000;
++ phy_write_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R, reg);
++ }
++
++ /* down the port if no link */
++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_MODE_CFG);
++ reg &= 0xFFF7;
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_MODE_CFG, reg);
++
++ /* reset port to effect above change */
++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
++ reg |= 0x8000;
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, reg);
++
++ /* wait till reset complete */
++ count = 50;
++ do {
++ msleep(10);
++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
++ } while ((reg & 0x8000) && --count);
++
++ if(reg & 0x8000){
++ dev_warn(&phydev->mdio.dev,"%s: Port Reset taking long time\n", __func__);
++ return -ETIMEDOUT;
++ }
++
++ /* LED0 Amber light On-Off settings [1:0]=01 */
++ reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_LED0_CTRL);
++ if((reg & 0x3) != 0x1) {
++ reg &= 0xFFFC;
++ reg |= 0x1;
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_LED0_CTRL, reg);
++ }
++
++ dev_dbg(&phydev->mdio.dev,"%s: quirk applied\n", __func__);
++ return 0;
++}
++
+ static int mv3310_config_init(struct phy_device *phydev)
+ {
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
+@@ -274,6 +351,7 @@ static int mv3310_config_init(struct phy_device *phydev)
+ __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
+ }
+
++ mv3310_amd_quirk(phydev);
+ val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
+ if (val < 0)
+ return val;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch
new file mode 100644
index 00000000..9bbb1ee4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch
@@ -0,0 +1,42 @@
+From e33b0e04ddd97a9ed4a04f001255fb23263cfa13 Mon Sep 17 00:00:00 2001
+From: Sudheer Anumolu <sudheer.anumolu@amd.com>
+Date: Tue, 26 Nov 2019 18:37:56 +0530
+Subject: [PATCH 4104/4736] Fix hot plug failure with SFP+RJ45 module. Do force
+ MDIO only if an external phy is available.
+
+---
+ drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+index a6fb6754984f..3fcfd7cb04d6 100755
+--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+@@ -989,6 +989,13 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ /* Clear the extra AN flag */
+ pdata->an_again = 0;
+
++ /* For SFP, only use an external PHY if available */
++ if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
++ force_mdio_mv_bp_con = 0;
++ if(!phy_data->sfp_phy_avail)
++ return 0;
++ }
++
+ /* Check for the use of an external PHY */
+ if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
+ if(force_mdio_mv_bp_con) {
+@@ -1000,10 +1007,6 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ }
+ }
+
+- /* For SFP, only use an external PHY if available */
+- if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
+- !phy_data->sfp_phy_avail)
+- return 0;
+
+ /* Set the proper MDIO mode for the PHY */
+ ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch
new file mode 100644
index 00000000..27db294f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch
@@ -0,0 +1,39 @@
+From d5b814c2e71b2bb51b3f24ef7fb0b5ea6e5f418c Mon Sep 17 00:00:00 2001
+From: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com>
+Date: Fri, 29 Nov 2019 09:44:24 +0530
+Subject: [PATCH 4105/4736] Reverting enable VCN DPG on Raven and Raven2 due to
+ power efficiency degradation and hang issues
+
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 3acfdc1e2bfd..a77f9b708f7f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1121,9 +1121,7 @@ static int soc15_common_early_init(void *handle)
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_VCN_MGCG;
+
+- adev->pg_flags = AMD_PG_SUPPORT_SDMA |
+- AMD_PG_SUPPORT_VCN |
+- AMD_PG_SUPPORT_VCN_DPG;
++ adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
+ } else if (adev->pdev->device == 0x15d8) {
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
+@@ -1166,9 +1164,7 @@ static int soc15_common_early_init(void *handle)
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_VCN_MGCG;
+
+- adev->pg_flags = AMD_PG_SUPPORT_SDMA |
+- AMD_PG_SUPPORT_VCN |
+- AMD_PG_SUPPORT_VCN_DPG;
++ adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
+ }
+ break;
+ case CHIP_ARCTURUS:
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch
new file mode 100644
index 00000000..9ea16d73
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch
@@ -0,0 +1,30 @@
+From 55c838d55e504ca7834858d16a72f644adbb59d3 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 10 Oct 2019 01:01:23 +0800
+Subject: [PATCH 4106/4736] drm/amdgpu/sdma5: fix mask value of POLL_REGMEM
+ packet for pipe sync
+
+sdma will hang once sequence number to be polled reaches 0x1000_0000
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index ad5c3566337c..3460c00f3eaa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1126,7 +1126,7 @@ static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ amdgpu_ring_write(ring, addr & 0xfffffffc);
+ amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
+ amdgpu_ring_write(ring, seq); /* reference */
+- amdgpu_ring_write(ring, 0xfffffff); /* mask */
++ amdgpu_ring_write(ring, 0xffffffff); /* mask */
+ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+ SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch
new file mode 100644
index 00000000..6d8301bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch
@@ -0,0 +1,50 @@
+From 6a850ace36127bc4ed674ce691f282c0aeeb930b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 2 Oct 2019 16:10:24 -0500
+Subject: [PATCH 4107/4736] drm/amdgpu/powerplay: fix typo in mvdd table setup
+
+Polaris and vegam use count for the value rather than
+level. This looks like a copy paste typo from when
+the code was adapted from previous asics.
+
+I'm not sure that the SMU actually uses this value, so
+I don't know that it actually is a bug per se.
+
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609
+Reported-by: Robert Strube <rstrube@gmail.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +-
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+index a1a9f6196009..2ab589e33b7b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+@@ -653,7 +653,7 @@ static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ count = SMU_MAX_SMIO_LEVELS;
+ for (level = 0; level < count; level++) {
+ table->SmioTable2.Pattern[level].Voltage =
+- PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
++ PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
+ /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
+ table->SmioTable2.Pattern[level].Smio =
+ (uint8_t) level;
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index 7c960b07746f..ae18fbcb26fb 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -456,7 +456,7 @@ static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ count = SMU_MAX_SMIO_LEVELS;
+ for (level = 0; level < count; level++) {
+ table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
+- data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
++ data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
+ /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
+ table->SmioTable2.Pattern[level].Smio =
+ (uint8_t) level;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch
new file mode 100644
index 00000000..2c20817a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch
@@ -0,0 +1,93 @@
+From 2fb67226c024d6c53c787651d548933ca91b9309 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 10 Oct 2019 16:11:58 +0300
+Subject: [PATCH 4108/4736] drm/amdgpu/powerplay: Use swap() where appropriate
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+@swap@
+identifier TEMP;
+expression A,B;
+@@
+- TEMP = A;
+- A = B;
+- B = TEMP;
++ swap(A, B);
+
+@@
+type T;
+identifier swap.TEMP;
+@@
+(
+- T TEMP;
+|
+- T TEMP = {...};
+)
+... when != TEMP
+
+Cc: Rex Zhu <rex.zhu@amd.com>
+Cc: Evan Quan <evan.quan@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: "Christian König" <christian.koenig@amd.com>
+Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
+Cc: amd-gfx@lists.freedesktop.org
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++----
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++----
+ 2 files changed, 4 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 25e68f245dba..897fd494fe33 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -1993,7 +1993,6 @@ static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ struct phm_ppt_v1_voltage_lookup_table *lookup_table)
+ {
+ uint32_t table_size, i, j;
+- struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
+ table_size = lookup_table->count;
+
+ PP_ASSERT_WITH_CODE(0 != lookup_table->count,
+@@ -2004,9 +2003,8 @@ static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ for (j = i + 1; j > 0; j--) {
+ if (lookup_table->entries[j].us_vdd <
+ lookup_table->entries[j - 1].us_vdd) {
+- tmp_voltage_lookup_record = lookup_table->entries[j - 1];
+- lookup_table->entries[j - 1] = lookup_table->entries[j];
+- lookup_table->entries[j] = tmp_voltage_lookup_record;
++ swap(lookup_table->entries[j - 1],
++ lookup_table->entries[j]);
+ }
+ }
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index ccceaba5914a..c31ef4262c9e 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -711,7 +711,6 @@ static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ struct phm_ppt_v1_voltage_lookup_table *lookup_table)
+ {
+ uint32_t table_size, i, j;
+- struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
+
+ PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
+ "Lookup table is empty", return -EINVAL);
+@@ -723,9 +722,8 @@ static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ for (j = i + 1; j > 0; j--) {
+ if (lookup_table->entries[j].us_vdd <
+ lookup_table->entries[j - 1].us_vdd) {
+- tmp_voltage_lookup_record = lookup_table->entries[j - 1];
+- lookup_table->entries[j - 1] = lookup_table->entries[j];
+- lookup_table->entries[j] = tmp_voltage_lookup_record;
++ swap(lookup_table->entries[j - 1],
++ lookup_table->entries[j]);
+ }
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch
new file mode 100644
index 00000000..a68d1424
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch
@@ -0,0 +1,73 @@
+From 685533c7ed2d5c4ad8d10df1f5d8a4868f440309 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 9 Oct 2019 08:14:03 -0500
+Subject: [PATCH 4109/4736] drm/amdgpu/swSMU/navi: add feature toggles for more
+ things
+
+Add toggles for more power features. Helpful in debugging.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 24 ++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 68cbcc792ec1..52a2feef7893 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -327,11 +327,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ memset(feature_mask, 0, sizeof(uint32_t) * num);
+
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
+- | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
+- | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
+ | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
+- | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
+- | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
+ | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
+ | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+ | FEATURE_MASK(FEATURE_PPT_BIT)
+@@ -342,8 +338,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
+ | FEATURE_MASK(FEATURE_THERMAL_BIT)
+ | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
+- | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
+- | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
+ | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
+ | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
+ | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
+@@ -354,11 +348,29 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ | FEATURE_MASK(FEATURE_FW_CTF_BIT)
+ | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
+
++ if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
++
++ if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
++
++ if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
++
++ if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
++
+ if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+ | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
+ | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
+
++ if (adev->pm.pp_feature & PP_ULV_MASK)
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
++
++ if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
++
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+ /* TODO: remove it once fw fix the bug */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch
new file mode 100644
index 00000000..8804632e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch
@@ -0,0 +1,144 @@
+From 38ff634117407a29df3b641470f954694492b934 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 10 Oct 2019 11:34:51 +0800
+Subject: [PATCH 4110/4736] drm/amd/powerplay: enable df cstate control on
+ powerplay routine
+
+Currently this is only supported on Vega20 with 40.50 and later
+SMC firmware.
+
+Change-Id: I4f2f7936a3bc6e1a32d590bc76ebfc9a5a53f9cb
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ .../gpu/drm/amd/include/kgd_pp_interface.h | 6 ++++++
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++
+ .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 19 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
+ .../gpu/drm/amd/powerplay/inc/vega20_ppsmc.h | 3 ++-
+ 5 files changed, 46 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 27cf0afaa0b4..5902f80d1fce 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -179,6 +179,11 @@ enum pp_mp1_state {
+ PP_MP1_STATE_RESET,
+ };
+
++enum pp_df_cstate {
++ DF_CSTATE_DISALLOW = 0,
++ DF_CSTATE_ALLOW,
++};
++
+ #define PP_GROUP_MASK 0xF0000000
+ #define PP_GROUP_SHIFT 28
+
+@@ -312,6 +317,7 @@ struct amd_pm_funcs {
+ int (*get_ppfeature_status)(void *handle, char *buf);
+ int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
+ int (*asic_reset_mode_2)(void *handle);
++ int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
+ };
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index fa8ad7db2b3a..83196b79edd5 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1548,6 +1548,23 @@ static int pp_smu_i2c_bus_access(void *handle, bool acquire)
+ return ret;
+ }
+
++static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
++{
++ struct pp_hwmgr *hwmgr = handle;
++
++ if (!hwmgr)
++ return -EINVAL;
++
++ if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
++ return 0;
++
++ mutex_lock(&hwmgr->smu_lock);
++ hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
++ mutex_unlock(&hwmgr->smu_lock);
++
++ return 0;
++}
++
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+ .load_firmware = pp_dpm_load_fw,
+ .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+@@ -1606,4 +1623,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ .set_ppfeature_status = pp_set_ppfeature_status,
+ .asic_reset_mode_2 = pp_asic_reset_mode_2,
+ .smu_i2c_bus_access = pp_smu_i2c_bus_access,
++ .set_df_cstate = pp_set_df_cstate,
+ };
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index f5915308e643..6629c475fe5d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -4155,6 +4155,24 @@ static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
+ return res;
+ }
+
++static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
++ enum pp_df_cstate state)
++{
++ int ret;
++
++ /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
++ if (hwmgr->smu_version < 0x283200) {
++ pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
++ return -EINVAL;
++ }
++
++ ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state);
++ if (ret)
++ pr_err("SetDfCstate failed!\n");
++
++ return ret;
++}
++
+ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ /* init/fini related */
+ .backend_init = vega20_hwmgr_backend_init,
+@@ -4223,6 +4241,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ .set_asic_baco_state = vega20_baco_set_state,
+ .set_mp1_state = vega20_set_mp1_state,
+ .smu_i2c_bus_access = vega20_smu_i2c_bus_access,
++ .set_df_cstate = vega20_set_df_cstate,
+ };
+
+ int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index 7bf9a14bfa0b..bd8c922dfd3e 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -355,6 +355,7 @@ struct pp_hwmgr_func {
+ int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+ int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
+ int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
++ int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
+ };
+
+ struct pp_table_func {
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+index a0883038f3c3..0c66f0fe1aaf 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+@@ -120,7 +120,8 @@
+ #define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x5D
+ #define PPSMC_MSG_GetAVFSVoltageByDpm 0x5F
+ #define PPSMC_MSG_BacoWorkAroundFlushVDCI 0x60
+-#define PPSMC_Message_Count 0x61
++#define PPSMC_MSG_DFCstateControl 0x63
++#define PPSMC_Message_Count 0x64
+
+ typedef uint32_t PPSMC_Result;
+ typedef uint32_t PPSMC_Msg;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch
new file mode 100644
index 00000000..d777f677
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch
@@ -0,0 +1,138 @@
+From b3603c96916c7799c3efaf21bf9038ceca4fb521 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 10 Oct 2019 11:40:37 +0800
+Subject: [PATCH 4111/4736] drm/amd/powerplay: enable df cstate control on
+ swSMU routine
+
+Currently this is only supported on Vega20 with 40.50 and later
+SMC firmware.
+
+Change-Id: I8397f9ccc5dec32dc86ef7635c5ed227c77e61a3
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 23 +++++++++++++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 25 ++++++++++++++++++-
+ 4 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 054376342454..a37a1b1d8abd 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1834,6 +1834,29 @@ int smu_set_mp1_state(struct smu_context *smu,
+ return ret;
+ }
+
++int smu_set_df_cstate(struct smu_context *smu,
++ enum pp_df_cstate state)
++{
++ int ret = 0;
++
++ /*
++ * The SMC is not fully ready. That may be
++ * expected as the IP may be masked.
++ * So, just return without error.
++ */
++ if (!smu->pm_enabled)
++ return 0;
++
++ if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
++ return 0;
++
++ ret = smu->ppt_funcs->set_df_cstate(smu, state);
++ if (ret)
++ pr_err("[SetDfCstate] failed!\n");
++
++ return ret;
++}
++
+ const struct amd_ip_funcs smu_ip_funcs = {
+ .name = "smu",
+ .early_init = smu_early_init,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index ccf711c327c8..401affdee49d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -468,6 +468,7 @@ struct pptable_funcs {
+ int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
+ int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t dpm_level, uint32_t *freq);
++ int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ };
+
+ struct smu_funcs
+@@ -852,5 +853,7 @@ int smu_force_clk_levels(struct smu_context *smu,
+ uint32_t mask);
+ int smu_set_mp1_state(struct smu_context *smu,
+ enum pp_mp1_state mp1_state);
++int smu_set_df_cstate(struct smu_context *smu,
++ enum pp_df_cstate state);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index 12a1de55ce3c..d8c9b7f91fcc 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -169,6 +169,7 @@
+ __SMU_DUMMY_MAP(PowerGateAtHub), \
+ __SMU_DUMMY_MAP(SetSoftMinJpeg), \
+ __SMU_DUMMY_MAP(SetHardMinFclkByFreq), \
++ __SMU_DUMMY_MAP(DFCstateControl), \
+
+ #undef __SMU_DUMMY_MAP
+ #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 99effde33ac1..1050566cb69a 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -143,6 +143,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] =
+ MSG_MAP(PrepareMp1ForShutdown),
+ MSG_MAP(SetMGpuFanBoostLimitRpm),
+ MSG_MAP(GetAVFSVoltageByDpm),
++ MSG_MAP(DFCstateControl),
+ };
+
+ static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
+@@ -3135,6 +3136,27 @@ static int vega20_get_thermal_temperature_range(struct smu_context *smu,
+ return 0;
+ }
+
++static int vega20_set_df_cstate(struct smu_context *smu,
++ enum pp_df_cstate state)
++{
++ uint32_t smu_version;
++ int ret;
++
++ ret = smu_get_smc_version(smu, NULL, &smu_version);
++ if (ret) {
++ pr_err("Failed to get smu version!\n");
++ return ret;
++ }
++
++ /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
++ if (smu_version < 0x283200) {
++ pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
++ return -EINVAL;
++ }
++
++ return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
++}
++
+ static const struct pptable_funcs vega20_ppt_funcs = {
+ .tables_init = vega20_tables_init,
+ .alloc_dpm_context = vega20_allocate_dpm_context,
+@@ -3177,7 +3199,8 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ .get_fan_speed_percent = vega20_get_fan_speed_percent,
+ .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
+ .set_watermarks_table = vega20_set_watermarks_table,
+- .get_thermal_temperature_range = vega20_get_thermal_temperature_range
++ .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
++ .set_df_cstate = vega20_set_df_cstate,
+ };
+
+ void vega20_set_ppt_funcs(struct smu_context *smu)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch
new file mode 100644
index 00000000..604ab73f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch
@@ -0,0 +1,87 @@
+From 881a616e2e79841ce68a3cd7426a40f41c495a74 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 30 Sep 2019 14:48:19 +0800
+Subject: [PATCH 4112/4736] drm/amdgpu: avoid ras error injection for retired
+ page
+
+check whether a page is bad page before umc error injection, bad page
+should not be accessed again
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 44 +++++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 18af80f1cffd..f3f3a98f93b3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -69,6 +69,9 @@ const char *ras_block_string[] = {
+
+ atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
+
++static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
++ uint64_t addr);
++
+ static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+ {
+@@ -289,6 +292,14 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ break;
+ }
+
++ /* umc ce/ue error injection for a bad page is not allowed */
++ if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
++ amdgpu_ras_check_bad_page(adev, data.inject.address)) {
++ DRM_WARN("RAS WARN: 0x%llx has been marked as bad before error injection!\n",
++ data.inject.address);
++ break;
++ }
++
+ /* data.inject.address is offset instead of absolute gpu address */
+ ret = amdgpu_ras_error_inject(adev, &data.inject);
+ break;
+@@ -1429,6 +1440,39 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
+ return ret;
+ }
+
++/*
++ * check if an address belongs to bad page
++ *
++ * Note: this check is only for umc block
++ */
++static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
++ uint64_t addr)
++{
++ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
++ struct ras_err_handler_data *data;
++ int i;
++ bool ret = false;
++
++ if (!con || !con->eh_data)
++ return ret;
++
++ mutex_lock(&con->recovery_lock);
++ data = con->eh_data;
++ if (!data)
++ goto out;
++
++ addr >>= AMDGPU_GPU_PAGE_SHIFT;
++ for (i = 0; i < data->count; i++)
++ if (addr == data->bps[i].retired_page) {
++ ret = true;
++ goto out;
++ }
++
++out:
++ mutex_unlock(&con->recovery_lock);
++ return ret;
++}
++
+ /* called in gpu recovery/init */
+ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch
new file mode 100644
index 00000000..e8a01f08
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch
@@ -0,0 +1,68 @@
+From 6ab8eec947ae191bede5fc2d9b9208a82a55196c Mon Sep 17 00:00:00 2001
+From: Nirmoy Das <nirmoy.das@amd.com>
+Date: Fri, 4 Oct 2019 11:53:37 +0200
+Subject: [PATCH 4113/4736] drm/amdgpu: fix memory leak
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+cleanup error handling code and make sure temporary info array
+with the handles are freed by amdgpu_bo_list_put() on
+idr_replace()'s failure.
+
+Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+index ea05784624ed..e143d9e110bd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+@@ -270,7 +270,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+
+ r = amdgpu_bo_create_list_entry_array(&args->in, &info);
+ if (r)
+- goto error_free;
++ return r;
+
+ switch (args->in.operation) {
+ case AMDGPU_BO_LIST_OP_CREATE:
+@@ -283,8 +283,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+ r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
+ mutex_unlock(&fpriv->bo_list_lock);
+ if (r < 0) {
+- amdgpu_bo_list_put(list);
+- return r;
++ goto error_put_list;
+ }
+
+ handle = r;
+@@ -306,9 +305,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+ mutex_unlock(&fpriv->bo_list_lock);
+
+ if (IS_ERR(old)) {
+- amdgpu_bo_list_put(list);
+ r = PTR_ERR(old);
+- goto error_free;
++ goto error_put_list;
+ }
+
+ amdgpu_bo_list_put(old);
+@@ -325,8 +323,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+
+ return 0;
+
++error_put_list:
++ amdgpu_bo_list_put(list);
++
+ error_free:
+- if (info)
+- kvfree(info);
++ kvfree(info);
+ return r;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch
new file mode 100644
index 00000000..ec27a9f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch
@@ -0,0 +1,138 @@
+From e2eaca86311ae7819b9b62f77287bd1165d0a6f9 Mon Sep 17 00:00:00 2001
+From: Ramalingam C <ramalingam.c@intel.com>
+Date: Mon, 29 Oct 2018 15:15:50 +0530
+Subject: [PATCH 4114/4736] drm: HDMI and DP specific HDCP2.2 defines
+
+This patch adds HDCP register definitions for HDMI and DP HDCP
+adaptations.
+
+HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
+where as HDCP2.2 register offsets in DPCD offsets are defined at
+drm_dp_helper.h.
+
+v2:
+ bit_field definitions are replaced by macros. [Tomas and Jani]
+v3:
+ No Changes.
+v4:
+ Comments style and typos are fixed [Uma]
+v5:
+ Fix for macros.
+v6:
+ Adds _MS to the timeouts to represent units [Sean Paul]
+v7:
+ Macro DP_HDCP_2_2_REG_EKH_KM_OFFSET renamed [Uma]
+ Redundant macro is removed [Uma]
+
+Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
+Reviewed-by: Sean Paul <seanpaul@chromium.org>
+Acked-by: Sean Paul <seanpaul@chromium.org> (for merging through drm-intel)
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-6-git-send-email-ramalingam.c@intel.com
+---
+ include/drm/drm_dp_helper.h | 51 +++++++++++++++++++++++++++++++++++++
+ include/drm/drm_hdcp.h | 28 ++++++++++++++++++++
+ 2 files changed, 79 insertions(+)
+
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index b81ec228ab8e..432e93ac3b3c 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -913,6 +913,57 @@
+ #define DP_AUX_HDCP_KSV_FIFO 0x6802C
+ #define DP_AUX_HDCP_AINFO 0x6803B
+
++/* DP HDCP2.2 parameter offsets in DPCD address space */
++#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
++#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
++#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
++#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
++#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
++#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
++#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
++#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
++#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
++#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
++#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
++#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
++#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
++#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
++#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
++#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
++#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
++#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
++#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
++#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
++#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
++#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
++#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
++#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
++#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
++#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
++
++/* DP HDCP message start offsets in DPCD address space */
++#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
++#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
++#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
++#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
++#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
++#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
++ DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
++#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
++#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
++#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
++#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
++#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
++#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
++#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
++
++#define HDCP_2_2_DP_RXSTATUS_LEN 1
++#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
++#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
++#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
++#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
++#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
++
+ /* DP 1.2 Sideband message defines */
+ /* peer device type - DP 1.2a Table 2-92 */
+ #define DP_PEER_DEVICE_NONE 0x0
+diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
+index 98e63d870139..5e93faaa7015 100644
+--- a/include/drm/drm_hdcp.h
++++ b/include/drm/drm_hdcp.h
+@@ -38,4 +38,32 @@
+ #define DRM_HDCP_DDC_BSTATUS 0x41
+ #define DRM_HDCP_DDC_KSV_FIFO 0x43
+
++/* HDCP2.2 TIMEOUTs in mSec */
++#define HDCP_2_2_CERT_TIMEOUT_MS 100
++#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000
++#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200
++#define HDCP_2_2_PAIRING_TIMEOUT_MS 200
++#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20
++#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7
++#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000
++#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100
++
++/* HDMI HDCP2.2 Register Offsets */
++#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
++#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
++#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
++#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
++#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
++
++#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
++#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
++#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
++#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
++
++/* Below macros take a byte at a time and mask the bit(s) */
++#define HDCP_2_2_HDMI_RXSTATUS_LEN 2
++#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
++#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
++#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
++
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch
new file mode 100644
index 00000000..3c5430bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch
@@ -0,0 +1,86 @@
+From 274e6cebf8d87f79c433c4d13ce82eb1d549aad3 Mon Sep 17 00:00:00 2001
+From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Date: Mon, 9 Sep 2019 21:21:47 +0000
+Subject: [PATCH 4115/4736] drm: Add link training repeaters addresses
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DP 1.3 specification introduces the Link Training-tunable PHY Repeater,
+and DP 1.4* supplemented it with new features. In the 1.4a spec, it was
+introduced some innovations to make handy to add support for systems
+with Thunderbolt or other repeater devices.
+
+It is important to highlight that DP specification had some updates from
+1.3 through 1.4a. In particular, DP 1.4 defines Repeater_FEC_CAPABILITY
+at the address 0xf0004, and DP 1.4a redefined the address 0xf0004 to
+DP_MAX_LANE_COUNT_PHY_REPEATER.
+
+Changes since V4:
+- Update commit message
+- Fix misleading comments related to the spec version
+Changes since V3:
+- Replace spaces by tabs
+Changes since V2:
+- Drop the kernel-doc comment
+- Reorder LTTPR according to register offset
+Changes since V1:
+- Adjusts registers names to be aligned with spec and the rest of the
+ file
+- Update spec comment from 1.4 to 1.4a
+
+Cc: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Leo Li <sunpeng.li@amd.com>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: Manasi Navare <manasi.d.navare@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190909212144.deeomlsqihwg4l3y@outlook.office365.com
+---
+ include/drm/drm_dp_helper.h | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index 432e93ac3b3c..b2a2c92ac67c 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -941,6 +941,32 @@
+ #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
+ #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
+
++/* Link Training (LT)-tunable PHY Repeaters */
++#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
++#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
++#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
++#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
++#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
++#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
++#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
++#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
++#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
++#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
++#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
++#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
++#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
++#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
++#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
++#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
++#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
++#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
++#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
++#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
++
+ /* DP HDCP message start offsets in DPCD address space */
+ #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
+ #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch
new file mode 100644
index 00000000..b590044a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch
@@ -0,0 +1,37 @@
+From c9926ea4a27022847c208c12d17c6b90206d71f1 Mon Sep 17 00:00:00 2001
+From: Stephen Rothwell <sfr@canb.auug.org.au>
+Date: Wed, 9 Oct 2019 11:35:57 +1100
+Subject: [PATCH 4116/4736] drm/amdkfd: update for drmP.h removal
+
+Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index f856c14a6ed0..e7913212c1f6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -40,6 +40,9 @@
+ #include <linux/interval_tree.h>
+ #include <linux/device_cgroup.h>
+ #include <drm/drmP.h>
++#include <drm/drm_file.h>
++#include <drm/drm_drv.h>
++#include <drm/drm_device.h>
+ #include <kgd_kfd_interface.h>
+
+ #include "amd_shared.h"
+@@ -51,8 +54,6 @@
+ /* GPU ID hash width in bits */
+ #define KFD_GPU_ID_HASH_WIDTH 16
+
+-struct drm_device;
+-
+ /* Use upper bits of mmap offset to store KFD driver specific information.
+ * BITS[63:62] - Encode MMAP type
+ * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch
new file mode 100644
index 00000000..3bdc66a4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch
@@ -0,0 +1,35 @@
+From a6ee800e9b828b18b24f685e85de0aa79ee36fcb Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Sun, 29 Sep 2019 10:58:43 +0800
+Subject: [PATCH 4117/4736] drm/amdgpu: Do not implement power-on for SDMA
+ after do mode2 reset on Renoir
+
+Find that ring sdma0 test failed if turn on SDMA powergating after do
+mode2 reset.
+
+Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is
+already powered up so there is no need to ask the SMU to power it up
+again. So I skip this function for a moment.
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 26f13de35b2c..78e21c12c17a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1792,7 +1792,7 @@ static int sdma_v4_0_hw_init(void *handle)
+
+ if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
+ adev->powerplay.pp_funcs->set_powergating_by_smu) ||
+- adev->asic_type == CHIP_RENOIR)
++ (adev->asic_type == CHIP_RENOIR && !adev->in_gpu_reset))
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+
+ if (!amdgpu_sriov_vf(adev))
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch
new file mode 100644
index 00000000..9b42282e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch
@@ -0,0 +1,122 @@
+From 34c14c75f78c119fe8a7e2c666131a225710fd72 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 10 Oct 2019 20:44:20 +0800
+Subject: [PATCH 4118/4736] drm/amdgpu/discovery: reserve discovery data at the
+ top of VRAM
+
+IP Discovery data is TMR fenced by the latest PSP BL,
+so we need to reserve this region.
+
+Tested on navi10/12/14 with VBIOS integrated with latest PSP BL.
+
+v2: use DISCOVERY_TMR_SIZE macro as bo size
+ use amdgpu_bo_create_kernel_at() to allocate bo
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 17 +++++++++++++++++
+ drivers/gpu/drm/amd/include/discovery.h | 1 -
+ 5 files changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 3bb4b7c6a42d..a994117c4edc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -799,6 +799,7 @@ struct amdgpu_device {
+ uint8_t *bios;
+ uint32_t bios_size;
+ struct amdgpu_bo *stolen_vga_memory;
++ struct amdgpu_bo *discovery_memory;
+ uint32_t bios_scratch_reg_offset;
+ uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+index 1481899f86c1..71198c5318e1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+@@ -136,7 +136,7 @@ static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *bin
+ {
+ uint32_t *p = (uint32_t *)binary;
+ uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
+- uint64_t pos = vram_size - BINARY_MAX_SIZE;
++ uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
+ unsigned long flags;
+
+ while (pos < vram_size) {
+@@ -179,7 +179,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev)
+ uint16_t checksum;
+ int r;
+
+- adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
++ adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL);
+ if (!adev->discovery)
+ return -ENOMEM;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+index 85b8c4d4d576..5a6693d7d269 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+@@ -24,6 +24,8 @@
+ #ifndef __AMDGPU_DISCOVERY__
+ #define __AMDGPU_DISCOVERY__
+
++#define DISCOVERY_TMR_SIZE (64 << 10)
++
+ int amdgpu_discovery_init(struct amdgpu_device *adev);
+ void amdgpu_discovery_fini(struct amdgpu_device *adev);
+ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 87284e8c8ece..0c1af24f8bc0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2063,6 +2063,20 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ NULL, &stolen_vga_buf);
+ if (r)
+ return r;
++
++ /*
++ * reserve one TMR (64K) memory at the top of VRAM which holds
++ * IP Discovery data and is protected by PSP.
++ */
++ r = amdgpu_bo_create_kernel_at(adev,
++ adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
++ DISCOVERY_TMR_SIZE,
++ AMDGPU_GEM_DOMAIN_VRAM,
++ &adev->discovery_memory,
++ NULL);
++ if (r)
++ return r;
++
+ DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
+ (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
+
+@@ -2132,6 +2146,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
+ void *stolen_vga_buf;
+ /* return the VGA stolen memory (if any) back to VRAM */
+ amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
++
++ /* return the IP Discovery TMR memory back to VRAM */
++ amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
+ }
+
+ /**
+diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h
+index 5dcb776548d8..7ec4331e67f2 100644
+--- a/drivers/gpu/drm/amd/include/discovery.h
++++ b/drivers/gpu/drm/amd/include/discovery.h
+@@ -25,7 +25,6 @@
+ #define _DISCOVERY_H_
+
+ #define PSP_HEADER_SIZE 256
+-#define BINARY_MAX_SIZE (64 << 10)
+ #define BINARY_SIGNATURE 0x28211407
+ #define DISCOVERY_TABLE_SIGNATURE 0x53445049
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch
new file mode 100644
index 00000000..c3713e34
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch
@@ -0,0 +1,122 @@
+From 5c9a30d8d57a134edb1e491aefc4b53f73335305 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 10 Oct 2019 16:11:57 +0300
+Subject: [PATCH 4119/4736] drm/amd/display: Use swap() where appropriate
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Mostly a cocci-job, but it flat out refused to remove the
+declaration in drivers/gpu/drm/amd/display/dc/core/dc.c so
+had to do that part manually.
+
+@swap@
+identifier TEMP;
+expression A,B;
+@@
+- TEMP = A;
+- A = B;
+- B = TEMP;
++ swap(A, B);
+
+@@
+type T;
+identifier swap.TEMP;
+@@
+(
+- T TEMP;
+|
+- T TEMP = {...};
+)
+... when != TEMP
+
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Leo Li <sunpeng.li@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: "Christian König" <christian.koenig@amd.com>
+Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
+Cc: amd-gfx@lists.freedesktop.org
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 7 ++-----
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 8 ++------
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-----
+ 3 files changed, 5 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 207f6084525c..7466e6332299 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2541,7 +2541,6 @@ static enum bp_result construct_integrated_info(
+
+ /* Sort voltage table from low to high*/
+ if (result == BP_RESULT_OK) {
+- struct clock_voltage_caps temp = {0, 0};
+ uint32_t i;
+ uint32_t j;
+
+@@ -2551,10 +2550,8 @@ static enum bp_result construct_integrated_info(
+ info->disp_clk_voltage[j].max_supported_clk <
+ info->disp_clk_voltage[j-1].max_supported_clk) {
+ /* swap j and j - 1*/
+- temp = info->disp_clk_voltage[j-1];
+- info->disp_clk_voltage[j-1] =
+- info->disp_clk_voltage[j];
+- info->disp_clk_voltage[j] = temp;
++ swap(info->disp_clk_voltage[j - 1],
++ info->disp_clk_voltage[j]);
+ }
+ }
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index c9f65c4df530..b4bbfb7bde12 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1611,8 +1611,6 @@ static enum bp_result construct_integrated_info(
+
+ struct atom_common_table_header *header;
+ struct atom_data_revision revision;
+-
+- struct clock_voltage_caps temp = {0, 0};
+ uint32_t i;
+ uint32_t j;
+
+@@ -1642,10 +1640,8 @@ static enum bp_result construct_integrated_info(
+ info->disp_clk_voltage[j-1].max_supported_clk
+ ) {
+ /* swap j and j - 1*/
+- temp = info->disp_clk_voltage[j-1];
+- info->disp_clk_voltage[j-1] =
+- info->disp_clk_voltage[j];
+- info->disp_clk_voltage[j] = temp;
++ swap(info->disp_clk_voltage[j - 1],
++ info->disp_clk_voltage[j]);
+ }
+ }
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 7142c014502a..699a215ca8ce 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -936,15 +936,11 @@ static void program_timing_sync(
+
+ /* set first pipe with plane as master */
+ for (j = 0; j < group_size; j++) {
+- struct pipe_ctx *temp;
+-
+ if (pipe_set[j]->plane_state) {
+ if (j == 0)
+ break;
+
+- temp = pipe_set[0];
+- pipe_set[0] = pipe_set[j];
+- pipe_set[j] = temp;
++ swap(pipe_set[0], pipe_set[j]);
+ break;
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch
new file mode 100644
index 00000000..1b2718c3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch
@@ -0,0 +1,88 @@
+From 363163a7abaed056e01ce4019c9b449a80fb588d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 10 Oct 2019 10:07:40 -0500
+Subject: [PATCH 4120/4736] drm/amdgpu/display: clean up dcn2*_pp_smu functions
+
+Use the dcn21 functions in dcn21_resource.c and make the
+dcn20 functions static since they are only used in
+dcn20_resource now.
+
+Cc: bhawanpreet.lakha@amd.com
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 ++++--
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 3 ---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +++-
+ 3 files changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 4ca819c223bd..968dc5fe4f1b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1185,6 +1185,8 @@ static const struct resource_create_funcs res_create_maximus_funcs = {
+ .create_hwseq = dcn20_hwseq_create,
+ };
+
++static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
++
+ void dcn20_clock_source_destroy(struct clock_source **clk_src)
+ {
+ kfree(TO_DCE110_CLK_SRC(*clk_src));
+@@ -2959,7 +2961,7 @@ bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+ return true;
+ }
+
+-struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
++static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
+ {
+ struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
+
+@@ -2974,7 +2976,7 @@ struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
+ return pp_smu;
+ }
+
+-void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
++static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+ {
+ if (pp_smu && *pp_smu) {
+ kfree(*pp_smu);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index 44f95aa0d61e..55006462f481 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -95,9 +95,6 @@ struct display_stream_compressor *dcn20_dsc_create(
+ struct dc_context *ctx, uint32_t inst);
+ void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
+
+-struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx);
+-void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+-
+ struct hubp *dcn20_hubp_create(
+ struct dc_context *ctx,
+ uint32_t inst);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 9fdfa213b47c..2cc93e2e6ec0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -636,6 +636,8 @@ static const struct dcn10_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
+ };
+
++static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
++
+ static struct input_pixel_processor *dcn21_ipp_create(
+ struct dc_context *ctx, uint32_t inst)
+ {
+@@ -939,7 +941,7 @@ static void destruct(struct dcn21_resource_pool *pool)
+ dcn_dccg_destroy(&pool->base.dccg);
+
+ if (pool->base.pp_smu != NULL)
+- dcn20_pp_smu_destroy(&pool->base.pp_smu);
++ dcn21_pp_smu_destroy(&pool->base.pp_smu);
+ }
+
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch
new file mode 100644
index 00000000..b8cb80d7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch
@@ -0,0 +1,34 @@
+From 7380d973669042490c0d393daa5e972b5dc0ed09 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 9 Oct 2019 18:52:51 +0800
+Subject: [PATCH 4121/4736] drm/amd/powerplay: re-enable FW_DSTATE feature bit
+
+SMU firmware has fix the bug, so remove this workaround.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 52a2feef7893..e8e5c889cc95 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -371,11 +371,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+
+- if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
++ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+- /* TODO: remove it once fw fix the bug */
+- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
+- }
+
+ if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch
new file mode 100644
index 00000000..451dd4bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch
@@ -0,0 +1,91 @@
+From 7bf9158b5981fbca65e8819df93fb2fc721c95bd Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 18:21:16 +0800
+Subject: [PATCH 4122/4736] drm/amdgpu/soc15: disable doorbell interrupt as
+ part of BACO entry sequence
+
+Workaround to make RAS recovery work in BACO reset.
+
+Change-Id: I4e4a81f719dcc88dfd49f583c4be3a373b5eab2c
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 8 ++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +++++++++
+ 3 files changed, 19 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 1f26a17e6561..919bd566ba3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -67,6 +67,8 @@ struct amdgpu_nbio_funcs {
+ bool enable);
+ void (*ih_doorbell_range)(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index);
++ void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
++ bool enable);
+ void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
+ bool enable);
+ void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 238c2483496a..0db458f9fafc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -502,6 +502,13 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ }
+ }
+
++static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
++ bool enable)
++{
++ WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
++ DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -516,6 +523,7 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
+ .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
+ .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
++ .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
+ .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
+ .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
+ .get_clockgating_state = nbio_v7_4_get_clockgating_state,
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index a77f9b708f7f..82b5bc4ddf9b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -492,10 +492,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ {
+ void *pp_handle = adev->powerplay.pp_handle;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+ if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
+ return -ENOENT;
+
++ /* avoid NBIF got stuck when do RAS recovery in BACO reset */
++ if (ras && ras->supported)
++ adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
++
+ /* enter BACO state */
+ if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+ return -EIO;
+@@ -504,6 +509,10 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+ return -EIO;
+
++ /* re-enable doorbell interrupt after BACO exit */
++ if (ras && ras->supported)
++ adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
++
+ dev_info(adev->dev, "GPU BACO reset\n");
+
+ adev->in_baco_reset = 1;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch
new file mode 100644
index 00000000..b7fb76fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch
@@ -0,0 +1,58 @@
+From d222b18bf2136356f9fae2b6df597e372ebf9da7 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 18:37:49 +0800
+Subject: [PATCH 4123/4736] drm/amd/powerplay: avoid disabling ECC if RAS is
+ enabled for VEGA20
+
+Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
+BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
+for ECC supported SKU.
+
+Change-Id: I2a82c128fa5e9731b886dd61f1273dc48ea1923c
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+index df6ff9252401..b068d1c7b44d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+@@ -29,7 +29,7 @@
+ #include "vega20_baco.h"
+ #include "vega20_smumgr.h"
+
+-
++#include "amdgpu_ras.h"
+
+ static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
+ {
+@@ -74,6 +74,7 @@ int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ enum BACO_STATE cur_state;
+ uint32_t data;
+
+@@ -84,10 +85,11 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ return 0;
+
+ if (state == BACO_STATE_IN) {
+- data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+- data |= 0x80000000;
+- WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+-
++ if (!ras || !ras->supported) {
++ data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
++ data |= 0x80000000;
++ WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
++ }
+
+ if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
+ return -EINVAL;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch
new file mode 100644
index 00000000..7d00c82b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch
@@ -0,0 +1,42 @@
+From f8e3ee206137a22a4172be249df166ebc49325ad Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 18:50:44 +0800
+Subject: [PATCH 4124/4736] drm/amd/powerplay: send EnterBaco msg with argument
+ as RAS recovery flag
+
+1 indicates RAS recovery flag in SMU FW.
+
+Change-Id: Icb8c14586fca1b8ae443bbde764570a9e41850fa
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+index b068d1c7b44d..9b5e72bdceca 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+@@ -89,10 +89,15 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+ data |= 0x80000000;
+ WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+- }
+
+- if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
+- return -EINVAL;
++ if(smum_send_msg_to_smc_with_parameter(hwmgr,
++ PPSMC_MSG_EnterBaco, 0))
++ return -EINVAL;
++ } else {
++ if(smum_send_msg_to_smc_with_parameter(hwmgr,
++ PPSMC_MSG_EnterBaco, 1))
++ return -EINVAL;
++ }
+
+ } else if (state == BACO_STATE_OUT) {
+ if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch
new file mode 100644
index 00000000..32d03754
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch
@@ -0,0 +1,32 @@
+From 2aa549a55977d90e59688b551961ced291631f8f Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 19:00:00 +0800
+Subject: [PATCH 4125/4736] drm/amd/powerplay: add BACO platformCaps for VEGA20
+
+BACO reset is needed for RAS recovery.
+
+Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 6629c475fe5d..3d3c647a63ff 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -182,6 +182,9 @@ static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_TablelessHardwareInterface);
+
++ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
++ PHM_PlatformCaps_BACO);
++
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EnableSMU7ThermalManagement);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch
new file mode 100644
index 00000000..c84b68c4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch
@@ -0,0 +1,121 @@
+From a2d92bf0a020c9db4eb2c9e4c53fd274813f8ad4 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Thu, 10 Oct 2019 18:28:17 +0200
+Subject: [PATCH 4126/4736] drm/amdgpu: Bail earlier when
+ amdgpu.cik_/si_support is not set to 1
+
+Bail from the pci_driver probe function instead of from the drm_driver
+load function.
+
+This avoid /dev/dri/card0 temporarily getting registered and then
+unregistered again, sending unwanted add / remove udev events to
+userspace.
+
+Specifically this avoids triggering the (userspace) bug fixed by this
+plymouth merge-request:
+https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59
+
+Note that despite that being a userspace bug, not sending unnecessary
+udev events is a good idea in general.
+
+BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 ----------------------
+ 2 files changed, 35 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 50927cd86cc9..9ca74f242fd1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1067,6 +1067,41 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
+ return -ENODEV;
+ }
+
++#ifdef CONFIG_DRM_AMDGPU_SI
++ if (!amdgpu_si_support) {
++ switch (flags & AMD_ASIC_MASK) {
++ case CHIP_TAHITI:
++ case CHIP_PITCAIRN:
++ case CHIP_VERDE:
++ case CHIP_OLAND:
++ case CHIP_HAINAN:
++ dev_info(&pdev->dev,
++ "SI support provided by radeon.\n");
++ dev_info(&pdev->dev,
++ "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
++ );
++ return -ENODEV;
++ }
++ }
++#endif
++#ifdef CONFIG_DRM_AMDGPU_CIK
++ if (!amdgpu_cik_support) {
++ switch (flags & AMD_ASIC_MASK) {
++ case CHIP_KAVERI:
++ case CHIP_BONAIRE:
++ case CHIP_HAWAII:
++ case CHIP_KABINI:
++ case CHIP_MULLINS:
++ dev_info(&pdev->dev,
++ "CIK support provided by radeon.\n");
++ dev_info(&pdev->dev,
++ "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
++ );
++ return -ENODEV;
++ }
++ }
++#endif
++
+ /* Get rid of things like offb */
+ ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
+ if (ret)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 20b11c024b87..ff47dd26e35a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -141,38 +141,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ struct amdgpu_device *adev;
+ int r, acpi_status;
+
+-#ifdef CONFIG_DRM_AMDGPU_SI
+- if (!amdgpu_si_support) {
+- switch (flags & AMD_ASIC_MASK) {
+- case CHIP_TAHITI:
+- case CHIP_PITCAIRN:
+- case CHIP_VERDE:
+- case CHIP_OLAND:
+- case CHIP_HAINAN:
+- dev_info(dev->dev,
+- "SI support provided by radeon.\n");
+- dev_info(dev->dev,
+- "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
+- );
+- return -ENODEV;
+- }
+- }
+-#endif
+-#ifdef CONFIG_DRM_AMDGPU_CIK
+- if (!amdgpu_cik_support) {
+- switch (flags & AMD_ASIC_MASK) {
+- case CHIP_KAVERI:
+- case CHIP_BONAIRE:
+- case CHIP_HAWAII:
+- case CHIP_KABINI:
+- case CHIP_MULLINS:
+- dev_info(dev->dev,
+- "CIK support disabled by module param\n");
+- return -ENODEV;
+- }
+- }
+-#endif
+-
+ adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
+ if (adev == NULL) {
+ return -ENOMEM;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch
new file mode 100644
index 00000000..3d1ddf2c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch
@@ -0,0 +1,914 @@
+From ffae45c6e296a3acaedd96fab920fb43672b2f50 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Sat, 12 Oct 2019 13:00:22 +0800
+Subject: [PATCH 4127/4736] drm/amdgpu: change to query the actual EDC counter
+
+For the potential request in the future, change to
+query the actual EDC counter.
+
+Change-Id: I783ccd76f4c65f9829f7a8967a539a23ae5484b5
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 821 ++++++++++++++++----------
+ drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
+ 2 files changed, 498 insertions(+), 325 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2e316e9da4cf..2d7140e57113 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -127,6 +127,18 @@ MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
+ #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c
+ #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0
+
++struct ras_gfx_subblock_reg {
++ const char *name;
++ uint32_t hwip;
++ uint32_t inst;
++ uint32_t seg;
++ uint32_t reg_offset;
++ uint32_t sec_count_mask;
++ uint32_t sec_count_shift;
++ uint32_t ded_count_mask;
++ uint32_t ded_count_shift;
++};
++
+ enum ta_ras_gfx_subblock {
+ /*CPC*/
+ TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+@@ -3976,6 +3988,7 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
+ { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16},
+ { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16},
+ { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16},
++ { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16},
+ { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16},
+ { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6},
+ { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16},
+@@ -5443,301 +5456,446 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
+ return 0;
+ }
+
+-static const struct {
+- const char *name;
+- uint32_t ip;
+- uint32_t inst;
+- uint32_t seg;
+- uint32_t reg_offset;
+- uint32_t per_se_instance;
+- int32_t num_instance;
+- uint32_t sec_count_mask;
+- uint32_t ded_count_mask;
+-} gfx_ras_edc_regs[] = {
+- { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1,
+- REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
+- REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
+- { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1,
+- REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT),
+- REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) },
+- { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
+- REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 },
+- { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
+- REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 },
+- { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1,
+- REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT),
+- REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) },
+- { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
+- REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 },
+- { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
+- REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
+- REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) },
+- { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1,
+- REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT),
+- REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) },
+- { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1,
+- REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 },
+- { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1,
+- REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 },
+- { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1,
+- REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 },
+- { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC),
+- REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) },
+- { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 },
++
++static const struct ras_gfx_subblock_reg ras_subblock_regs[] = {
++ { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
++ SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
++ SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
++ },
++ { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
++ SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
++ SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT)
++ },
++ { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
++ SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1),
++ 0, 0
++ },
++ { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
++ SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2),
++ 0, 0
++ },
++ { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
++ SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
++ SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT)
++ },
++ { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
++ SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT),
++ 0, 0
++ },
++ { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
++ SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
++ SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT)
++ },
++ { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT),
++ SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT),
++ SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT)
++ },
++ { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
++ SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1),
++ 0, 0
++ },
++ { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
++ SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1),
++ 0, 0
++ },
++ { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
++ SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1),
++ 0, 0
++ },
++ { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
++ SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
++ SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED)
++ },
++ { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
++ SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED),
++ 0, 0
++ },
+ { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
+- 0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
+- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED)
++ },
+ { "GDS_OA_PHY_PHY_CMD_RAM_MEM",
+- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
+- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED)
++ },
+ { "GDS_OA_PHY_PHY_DATA_RAM_MEM",
+- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 },
++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
++ SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED),
++ 0, 0
++ },
+ { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
+- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED)
++ },
+ { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
+- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED)
++ },
+ { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
+- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED)
++ },
+ { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
+- SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
+- REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
+- { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1,
+- REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 },
+- { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
+- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
+- { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 },
+- { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 },
+- { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 },
+- { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 },
+- { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
+- REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 },
+- { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
+- REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 },
+- { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
+- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
+- { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
+- REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
+- { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
+- REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
+- { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
+- REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
+- { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
+- REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
+- { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 },
+- { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 },
+- { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 },
+- { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 },
+- { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 },
+- { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 },
+- { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 },
+- { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
+- REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 },
+- { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
+- 16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 },
++ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
++ SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED)
++ },
++ { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
++ SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT),
++ 0, 0
++ },
++ { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT)
++ },
++ { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++ SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
++ SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
++ SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT)
++ },
++ { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT)
++ },
++ { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT)
++ },
++ { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT)
++ },
++ { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT)
++ },
++ { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++ SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++ SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++ SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++ SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT),
++ 0, 0
++ },
+ { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
+- 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
+- 0 },
+- { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
+- 16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 },
++ SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++ SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT),
++ 0, 0
++ },
+ { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
+- 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
+- 0 },
+- { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
+- 16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 },
+- { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72,
+- REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 },
+- { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
+- { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
+- { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 },
+- { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 },
+- { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 },
+- { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
+- { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
+- REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
+- { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
+- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
+- { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
+- REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
+- { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 },
+- { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT),
+- REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) },
+- { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT),
+- REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) },
+- { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT),
+- REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) },
+- { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT),
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) },
+- { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT),
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) },
+- { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT),
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) },
+- { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT),
+- REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) },
++ SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
++ 0, 0
++ },
++ { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++ SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT),
++ 0, 0
++ },
++ { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
++ SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT),
++ 0, 0
++ },
++ { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT)
++ },
++ { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT)
++ },
++ { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
++ 0, 0
++ },
++ { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT),
++ 0, 0
++ },
++ { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT)
++ },
++ { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
++ SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT)
++ },
++ { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT)
++ },
++ { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
++ SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT)
++ },
++ { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
++ SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT)
++ },
++ { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT)
++ },
++ { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT)
++ },
++ { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT)
++ },
++ { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT)
++ },
++ { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT)
++ },
++ { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
++ SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT)
++ },
+ { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
+- 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
+- { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT)
++ },
++ { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT)
++ },
+ { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
+- 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
+- { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT)
++ },
++ { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT)
++ },
+ { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
+- 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
+- { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
+- { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
+- { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
+- { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
+- { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
+- { "SQC_INST_BANKA_UTCL1_MISS_FIFO",
+- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
+- REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
+- 0 },
+- { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 },
+- { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 },
+- { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 },
+- { "SQC_DATA_BANKA_DIRTY_BIT_RAM",
+- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
+- REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 },
+- { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
+- REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
+- { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
+- { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
+- { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
+- { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
+- REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
+- { "SQC_INST_BANKB_UTCL1_MISS_FIFO",
+- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
+- REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
+- 0 },
+- { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 },
+- { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 },
+- { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+- 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 },
+- { "SQC_DATA_BANKB_DIRTY_BIT_RAM",
+- SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
+- REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 },
+- { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
+- { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
+- { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
+- { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
+- { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
+- { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 },
+- { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 },
+- { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 },
+- { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 },
+- { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 },
+- { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
+- { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
+- { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
+- { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 },
+- { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 },
+- { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 },
+- { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 },
+- { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 },
+- { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+- REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 },
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT)
++ },
++ { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT)
++ },
++ { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT)
++ },
++ { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT)
++ },
++ { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT)
++ },
++ { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT)
++ },
++ { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT)
++ },
++ { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT)
++ },
++ { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT)
++ },
++ { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT)
++ },
++ { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT)
++ },
++ { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT),
++ 0, 0
++ },
++ { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++ SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT),
++ 0, 0
++ },
++ { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT)
++ },
++ { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT)
++ },
++ { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT)
++ },
++ { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT)
++ },
++ { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT)
++ },
++ { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
++ 0, 0
++ },
++ { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
++ 0, 0
++ },
++ { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT),
++ 0, 0
++ },
++ { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
++ 0, 0
++ },
++ { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
++ 0, 0
++ },
++ { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT)
++ },
++ { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT)
++ },
++ { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT)
++ },
++ { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
++ 0, 0
++ },
++ { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
++ 0, 0
++ },
++ { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
++ 0, 0
++ },
++ { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
++ 0, 0
++ },
++ { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
++ 0, 0
++ },
++ { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++ SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
++ 0, 0
++ }
+ };
+
+ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+@@ -5786,14 +5944,52 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+ return ret;
+ }
+
++static int __get_ras_error_count(const struct soc15_reg_entry *reg,
++ uint32_t se_id, uint32_t inst_id, uint32_t value,
++ uint32_t *sec_count, uint32_t *ded_count)
++{
++ uint32_t i;
++ uint32_t sec_cnt, ded_cnt;
++
++ for (i = 0; i < ARRAY_SIZE(ras_subblock_regs); i++) {
++ if(ras_subblock_regs[i].reg_offset != reg->reg_offset ||
++ ras_subblock_regs[i].seg != reg->seg ||
++ ras_subblock_regs[i].inst != reg->inst)
++ continue;
++
++ sec_cnt = (value &
++ ras_subblock_regs[i].sec_count_mask) >>
++ ras_subblock_regs[i].sec_count_shift;
++ if (sec_cnt) {
++ DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
++ ras_subblock_regs[i].name,
++ se_id, inst_id,
++ sec_cnt);
++ *sec_count += sec_cnt;
++ }
++
++ ded_cnt = (value &
++ ras_subblock_regs[i].ded_count_mask) >>
++ ras_subblock_regs[i].ded_count_shift;
++ if (ded_cnt) {
++ DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
++ ras_subblock_regs[i].name,
++ se_id, inst_id,
++ ded_cnt);
++ *ded_count += ded_cnt;
++ }
++ }
++
++ return 0;
++}
++
+ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
+ void *ras_error_status)
+ {
+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+- uint32_t sec_count, ded_count;
+- uint32_t i;
++ uint32_t sec_count = 0, ded_count = 0;
++ uint32_t i, j, k;
+ uint32_t reg_value;
+- uint32_t se_id, instance_id;
+
+ if (adev->asic_type != CHIP_VEGA20)
+ return -EINVAL;
+@@ -5802,49 +5998,24 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
+ err_data->ce_count = 0;
+
+ mutex_lock(&adev->grbm_idx_mutex);
+- for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) {
+- for (instance_id = 0; instance_id < 256; instance_id++) {
+- for (i = 0;
+- i < sizeof(gfx_ras_edc_regs) / sizeof(gfx_ras_edc_regs[0]);
+- i++) {
+- if (se_id != 0 &&
+- !gfx_ras_edc_regs[i].per_se_instance)
+- continue;
+- if (instance_id >= gfx_ras_edc_regs[i].num_instance)
+- continue;
+
+- gfx_v9_0_select_se_sh(adev, se_id, 0,
+- instance_id);
+-
+- reg_value = RREG32(
+- adev->reg_offset[gfx_ras_edc_regs[i].ip]
+- [gfx_ras_edc_regs[i].inst]
+- [gfx_ras_edc_regs[i].seg] +
+- gfx_ras_edc_regs[i].reg_offset);
+- sec_count = reg_value &
+- gfx_ras_edc_regs[i].sec_count_mask;
+- ded_count = reg_value &
+- gfx_ras_edc_regs[i].ded_count_mask;
+- if (sec_count) {
+- DRM_INFO(
+- "Instance[%d][%d]: SubBlock %s, SEC %d\n",
+- se_id, instance_id,
+- gfx_ras_edc_regs[i].name,
+- sec_count);
+- err_data->ce_count++;
+- }
+-
+- if (ded_count) {
+- DRM_INFO(
+- "Instance[%d][%d]: SubBlock %s, DED %d\n",
+- se_id, instance_id,
+- gfx_ras_edc_regs[i].name,
+- ded_count);
+- err_data->ue_count++;
+- }
++ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) {
++ for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) {
++ for (k = 0; k < sec_ded_counter_registers[i].instance; k++) {
++ gfx_v9_0_select_se_sh(adev, j, 0, k);
++ reg_value =
++ RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
++ if (reg_value)
++ __get_ras_error_count(&sec_ded_counter_registers[i],
++ j, k, reg_value,
++ &sec_count, &ded_count);
+ }
+ }
+ }
++
++ err_data->ce_count += sec_count;
++ err_data->ue_count += ded_count;
++
+ gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+ mutex_unlock(&adev->grbm_idx_mutex);
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
+index a3dde0c31f57..9af6c6ffbfa2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
+@@ -67,6 +67,8 @@ struct soc15_allowed_register_entry {
+ #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
+ { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
+
++#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
++
+ void soc15_grbm_select(struct amdgpu_device *adev,
+ u32 me, u32 pipe, u32 queue, u32 vmid);
+ int soc15_set_ip_blocks(struct amdgpu_device *adev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch
new file mode 100644
index 00000000..3a3cdbe6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch
@@ -0,0 +1,92 @@
+From b4d660a216d1ef77aca09688ec730030d34befb9 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Fri, 9 Aug 2019 14:30:29 +0800
+Subject: [PATCH 4128/4736] drm/amd/include: add register define for VML2 and
+ ATCL2
+
+Add VML2 and ATCL2 ECC registers to support VEGA20 RAS
+
+Change-Id: I8860f2e37fa7afd8d6123290fb7b9dcee56edd6e
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../amd/include/asic_reg/gc/gc_9_0_offset.h | 18 ++++++++++++++++--
+ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 18 ++++++++++++++++--
+ 2 files changed, 32 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+index ca16d9125fbc..2bfaaa8157d0 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+@@ -1146,7 +1146,14 @@
+ #define mmATC_L2_MEM_POWER_LS_BASE_IDX 0
+ #define mmATC_L2_CGTT_CLK_CTRL 0x080c
+ #define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
+-
++#define mmATC_L2_CACHE_4K_EDC_INDEX 0x080e
++#define mmATC_L2_CACHE_4K_EDC_INDEX_BASE_IDX 0
++#define mmATC_L2_CACHE_2M_EDC_INDEX 0x080f
++#define mmATC_L2_CACHE_2M_EDC_INDEX_BASE_IDX 0
++#define mmATC_L2_CACHE_4K_EDC_CNT 0x0810
++#define mmATC_L2_CACHE_4K_EDC_CNT_BASE_IDX 0
++#define mmATC_L2_CACHE_2M_EDC_CNT 0x0811
++#define mmATC_L2_CACHE_2M_EDC_CNT_BASE_IDX 0
+
+ // addressBlock: gc_utcl2_vml2pfdec
+ // base address: 0xa100
+@@ -1206,7 +1213,14 @@
+ #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
+ #define mmVM_L2_CGTT_CLK_CTRL 0x085e
+ #define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
+-
++#define mmVM_L2_MEM_ECC_INDEX 0x0860
++#define mmVM_L2_MEM_ECC_INDEX_BASE_IDX 0
++#define mmVM_L2_WALKER_MEM_ECC_INDEX 0x0861
++#define mmVM_L2_WALKER_MEM_ECC_INDEX_BASE_IDX 0
++#define mmVM_L2_MEM_ECC_CNT 0x0862
++#define mmVM_L2_MEM_ECC_CNT_BASE_IDX 0
++#define mmVM_L2_WALKER_MEM_ECC_CNT 0x0863
++#define mmVM_L2_WALKER_MEM_ECC_CNT_BASE_IDX 0
+
+ // addressBlock: gc_utcl2_vml2vcdec
+ // base address: 0xa200
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+index 064c4bb1dc62..d4c613a85352 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+@@ -6661,7 +6661,6 @@
+ #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+ #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+
+-
+ // addressBlock: gc_utcl2_vml2pfdec
+ //VM_L2_CNTL
+ #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+@@ -6991,7 +6990,22 @@
+ #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
+ #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
+ #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
+-
++//VM_L2_MEM_ECC_INDEX
++#define VM_L2_MEM_ECC_INDEX__INDEX__SHIFT 0x0
++#define VM_L2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
++//VM_L2_WALKER_MEM_ECC_INDEX
++#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0
++#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL
++//VM_L2_MEM_ECC_CNT
++#define VM_L2_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc
++#define VM_L2_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe
++#define VM_L2_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L
++#define VM_L2_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L
++//VM_L2_WALKER_MEM_ECC_CNT
++#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT__SHIFT 0xc
++#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT__SHIFT 0xe
++#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT_MASK 0x00003000L
++#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT_MASK 0x0000C000L
+
+ // addressBlock: gc_utcl2_vml2vcdec
+ //VM_CONTEXT0_CNTL
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch
new file mode 100644
index 00000000..ca6b0fa0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch
@@ -0,0 +1,205 @@
+From 3524f56effff32b75337729b56e3209600be45a0 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Sun, 29 Sep 2019 16:04:10 +0800
+Subject: [PATCH 4129/4736] drm/amdgpu: add RAS support for VML2 and ATCL2
+
+v1: Add codes to query the EDC count of VML2 & ATCL2
+v2: Rename VML2/ATCL2 registers and drop their mask define
+v3: Add back the ECC mask for VML2 registers
+
+Change-Id: If2c251481ba0a1a34ce3405a85f86d65eecee461
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 167 ++++++++++++++++++++++++++
+ 1 file changed, 167 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2d7140e57113..24802e4d25e5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5944,6 +5944,171 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+ return ret;
+ }
+
++static const char *vml2_mems[] = {
++ "UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
++ "UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
++ "UTC_VML2_BANK_CACHE_0_4K_MEM0",
++ "UTC_VML2_BANK_CACHE_0_4K_MEM1",
++ "UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
++ "UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
++ "UTC_VML2_BANK_CACHE_1_4K_MEM0",
++ "UTC_VML2_BANK_CACHE_1_4K_MEM1",
++ "UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
++ "UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
++ "UTC_VML2_BANK_CACHE_2_4K_MEM0",
++ "UTC_VML2_BANK_CACHE_2_4K_MEM1",
++ "UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
++ "UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
++ "UTC_VML2_BANK_CACHE_3_4K_MEM0",
++ "UTC_VML2_BANK_CACHE_3_4K_MEM1",
++};
++
++static const char *vml2_walker_mems[] = {
++ "UTC_VML2_CACHE_PDE0_MEM0",
++ "UTC_VML2_CACHE_PDE0_MEM1",
++ "UTC_VML2_CACHE_PDE1_MEM0",
++ "UTC_VML2_CACHE_PDE1_MEM1",
++ "UTC_VML2_CACHE_PDE2_MEM0",
++ "UTC_VML2_CACHE_PDE2_MEM1",
++ "UTC_VML2_RDIF_LOG_FIFO",
++};
++
++static const char *atc_l2_cache_2m_mems[] = {
++ "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
++ "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
++ "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
++ "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
++};
++
++static const char *atc_l2_cache_4k_mems[] = {
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
++ "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
++ "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
++};
++
++static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev,
++ struct ras_err_data *err_data)
++{
++ uint32_t i, data;
++ uint32_t sec_count, ded_count;
++
++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
++
++ for (i = 0; i < 16; i++) {
++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
++ data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
++
++ sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);
++ if (sec_count) {
++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++ vml2_mems[i], sec_count);
++ err_data->ce_count += sec_count;
++ }
++
++ ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);
++ if (ded_count) {
++ DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
++ vml2_mems[i], ded_count);
++ err_data->ue_count += ded_count;
++ }
++ }
++
++ for (i = 0; i < 7; i++) {
++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
++ data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
++
++ sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
++ SEC_COUNT);
++ if (sec_count) {
++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++ vml2_walker_mems[i], sec_count);
++ err_data->ce_count += sec_count;
++ }
++
++ ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
++ DED_COUNT);
++ if (ded_count) {
++ DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
++ vml2_walker_mems[i], ded_count);
++ err_data->ue_count += ded_count;
++ }
++ }
++
++ for (i = 0; i < 4; i++) {
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
++ data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
++
++ sec_count = (data & 0x00006000L) >> 0xd;
++ if (sec_count) {
++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++ atc_l2_cache_2m_mems[i], sec_count);
++ err_data->ce_count += sec_count;
++ }
++ }
++
++ for (i = 0; i < 32; i++) {
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
++ data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
++
++ sec_count = (data & 0x00006000L) >> 0xd;
++ if (sec_count) {
++ DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++ atc_l2_cache_4k_mems[i], sec_count);
++ err_data->ce_count += sec_count;
++ }
++
++ ded_count = (data & 0x00018000L) >> 0xf;
++ if (ded_count) {
++ DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
++ atc_l2_cache_4k_mems[i], ded_count);
++ err_data->ue_count += ded_count;
++ }
++ }
++
++ WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
++ WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
++ WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
++
++ return 0;
++}
++
+ static int __get_ras_error_count(const struct soc15_reg_entry *reg,
+ uint32_t se_id, uint32_t inst_id, uint32_t value,
+ uint32_t *sec_count, uint32_t *ded_count)
+@@ -6019,6 +6184,8 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
+ gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+ mutex_unlock(&adev->grbm_idx_mutex);
+
++ gfx_v9_0_query_utc_edc_status(adev, err_data);
++
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch
new file mode 100644
index 00000000..bfa13d6e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch
@@ -0,0 +1,38 @@
+From 883eb361081a64867284c669a6263995512bcb59 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 18 Sep 2019 19:42:14 +0200
+Subject: [PATCH 4130/4736] drm/amdgpu: fix error handling in
+ amdgpu_bo_list_create
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to drop normal and userptr BOs separately.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+index e143d9e110bd..92df38fd794d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+@@ -140,7 +140,12 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,
+ return 0;
+
+ error_free:
+- while (i--) {
++ for (i = 0; i < last_entry; ++i) {
++ struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
++
++ amdgpu_bo_unref(&bo);
++ }
++ for (i = first_userptr; i < num_entries; ++i) {
+ struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
+
+ amdgpu_bo_unref(&bo);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch
new file mode 100644
index 00000000..80b32dc1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch
@@ -0,0 +1,34 @@
+From 34b82c5346e844f2f9ffb12745b79fce980f4542 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 19 Sep 2019 10:38:57 +0200
+Subject: [PATCH 4131/4736] drm/amdgpu: fix potential VM faults
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When we allocate new page tables under memory
+pressure we should not evict old ones.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index acb0755fe724..1350666355e0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -538,7 +538,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ .interruptible = (bp->type != ttm_bo_type_kernel),
+ .no_wait_gpu = bp->no_wait_gpu,
+ .resv = bp->resv,
+- .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
++ .flags = bp->type != ttm_bo_type_kernel ?
++ TTM_OPT_FLAG_ALLOW_RES_EVICT : 0
+ };
+ struct amdgpu_bo *bo;
+ unsigned long page_align, size = bp->size;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch
new file mode 100644
index 00000000..6813b358
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch
@@ -0,0 +1,53 @@
+From bacf25c006ff8772febc7f022976b07bd2b31882 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Tue, 15 Oct 2019 10:08:22 +0800
+Subject: [PATCH 4132/4736] drm/amdgpu: Fix tdr3 could hang with slow compute
+ issue
+
+When index is 1, need to set compute ring timeout for sriov and passthrough.
+
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++--
+ 2 files changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 1b972f531740..521af22ad916 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2622,8 +2622,11 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
+ * There is only one value specified and
+ * it should apply to all non-compute jobs.
+ */
+- if (index == 1)
++ if (index == 1) {
+ adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
++ if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
++ adev->compute_timeout = adev->gfx_timeout;
++ }
+ }
+
+ return ret;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 9ca74f242fd1..658fa3fd5fad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -252,9 +252,11 @@ module_param_named(msi, amdgpu_msi, int, 0444);
+ * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
+ * jobs is 10000. And there is no timeout enforced on compute jobs.
+ */
+-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs."
++MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
++ "for passthrough or sriov, 10000 for all jobs."
+ " 0: keep default value. negative: infinity timeout), "
+- "format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
++ "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
++ "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
+ module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
+
+ /**
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch
new file mode 100644
index 00000000..1907ed9b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch
@@ -0,0 +1,273 @@
+From 0d3a43711fc55bba4355010ec4c165bafad46c69 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Fri, 11 Oct 2019 17:51:34 +0800
+Subject: [PATCH 4133/4736] drm/amd/powerplay: bug fix for pcie parameters
+ override
+
+Bug fix for pcie paramerers override on swsmu.
+Below is a scenario to have this problem.
+pptable definition on pcie dpm:
+0 -> pcie gen speed:1, pcie lanes: *16
+1 -> pcie gen speed:4, pcie lanes: *16
+Then if we have a system only have the capbility:
+pcie gen speed: 3, pcie lanes: *8,
+we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
+But the code skips the dpm 0 configuration.
+So the real pcie dpm parameters are:
+0 -> pcie gen speed:1, pcie lanes: *16
+1 -> pcie gen speed:3, pcie lanes: *8
+Then the wrong pcie lanes will be toggled.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 44 -------------------
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 ++++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 44 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 23 ++++++++++
+ 5 files changed, 98 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a37a1b1d8abd..26cacc899dfe 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_override_pcie_parameters(struct smu_context *smu)
+-{
+- struct amdgpu_device *adev = smu->adev;
+- uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
+- int ret;
+-
+- if (adev->flags & AMD_IS_APU)
+- return 0;
+-
+- if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+- pcie_gen = 3;
+- else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+- pcie_gen = 2;
+- else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+- pcie_gen = 1;
+- else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
+- pcie_gen = 0;
+-
+- /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
+- * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
+- * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
+- */
+- if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+- pcie_width = 6;
+- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+- pcie_width = 5;
+- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+- pcie_width = 4;
+- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+- pcie_width = 3;
+- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+- pcie_width = 2;
+- else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+- pcie_width = 1;
+-
+- smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
+- ret = smu_send_smc_msg_with_param(smu,
+- SMU_MSG_OverridePcieParameters,
+- smu_pcie_arg);
+- if (ret)
+- pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
+- return ret;
+-}
+-
+ static int smu_smc_table_hw_init(struct smu_context *smu,
+ bool initialize)
+ {
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 401affdee49d..cdb845f5f23e 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -469,6 +469,7 @@ struct pptable_funcs {
+ int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t dpm_level, uint32_t *freq);
+ int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
++ int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
+ };
+
+ struct smu_funcs
+@@ -551,6 +552,7 @@ struct smu_funcs
+ int (*mode2_reset)(struct smu_context *smu);
+ int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
++ int (*override_pcie_parameters)(struct smu_context *smu);
+ };
+
+ #define smu_init_microcode(smu) \
+@@ -783,6 +785,12 @@ struct smu_funcs
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+
++#define smu_override_pcie_parameters(smu) \
++ ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
++
++#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
++ ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
++
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ uint16_t *size, uint8_t *frev, uint8_t *crev,
+ uint8_t **addr);
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index e8e5c889cc95..b88aae9bb242 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1628,6 +1628,28 @@ static int navi10_get_power_limit(struct smu_context *smu,
+ return 0;
+ }
+
++static int navi10_update_pcie_parameters(struct smu_context *smu,
++ uint32_t pcie_gen_cap,
++ uint32_t pcie_width_cap)
++{
++ PPTable_t *pptable = smu->smu_table.driver_pptable;
++ int ret, i;
++ uint32_t smu_pcie_arg;
++
++ for (i = 0; i < NUM_LINK_LEVELS; i++) {
++ smu_pcie_arg = (i << 16) |
++ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
++ (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
++ pptable->PcieLaneCount[i] : pcie_width_cap);
++ ret = smu_send_smc_msg_with_param(smu,
++ SMU_MSG_OverridePcieParameters,
++ smu_pcie_arg);
++ }
++
++ return ret;
++}
++
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ .tables_init = navi10_tables_init,
+ .alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -1666,6 +1688,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
+ .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
+ .get_power_limit = navi10_get_power_limit,
++ .update_pcie_parameters = navi10_update_pcie_parameters,
+ };
+
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 9883f0a4471a..df1f2b99fed7 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -32,6 +32,7 @@
+ #include "vega20_ppt.h"
+ #include "arcturus_ppt.h"
+ #include "navi10_ppt.h"
++#include "amd_pcie.h"
+
+ #include "asic_reg/thm/thm_11_0_2_offset.h"
+ #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
+@@ -1791,6 +1792,48 @@ static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
+ return ret;
+ }
+
++static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
++{
++ struct amdgpu_device *adev = smu->adev;
++ uint32_t pcie_gen = 0, pcie_width = 0;
++ int ret;
++
++ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
++ pcie_gen = 3;
++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
++ pcie_gen = 2;
++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
++ pcie_gen = 1;
++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
++ pcie_gen = 0;
++
++ /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
++ * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
++ * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
++ */
++ if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
++ pcie_width = 6;
++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
++ pcie_width = 5;
++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
++ pcie_width = 4;
++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
++ pcie_width = 3;
++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
++ pcie_width = 2;
++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
++ pcie_width = 1;
++
++ ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
++
++ if (ret)
++ pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
++
++ return ret;
++
++}
++
++
+ static const struct smu_funcs smu_v11_0_funcs = {
+ .init_microcode = smu_v11_0_init_microcode,
+ .load_microcode = smu_v11_0_load_microcode,
+@@ -1843,6 +1886,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ .baco_reset = smu_v11_0_baco_reset,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+
+ void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 1050566cb69a..a76ffd58404e 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3157,6 +3157,28 @@ static int vega20_set_df_cstate(struct smu_context *smu,
+ return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
+ }
+
++static int vega20_update_pcie_parameters(struct smu_context *smu,
++ uint32_t pcie_gen_cap,
++ uint32_t pcie_width_cap)
++{
++ PPTable_t *pptable = smu->smu_table.driver_pptable;
++ int ret, i;
++ uint32_t smu_pcie_arg;
++
++ for (i = 0; i < NUM_LINK_LEVELS; i++) {
++ smu_pcie_arg = (i << 16) |
++ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
++ (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
++ pptable->PcieLaneCount[i] : pcie_width_cap);
++ ret = smu_send_smc_msg_with_param(smu,
++ SMU_MSG_OverridePcieParameters,
++ smu_pcie_arg);
++ }
++
++ return ret;
++}
++
++
+ static const struct pptable_funcs vega20_ppt_funcs = {
+ .tables_init = vega20_tables_init,
+ .alloc_dpm_context = vega20_allocate_dpm_context,
+@@ -3201,6 +3223,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ .set_watermarks_table = vega20_set_watermarks_table,
+ .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
+ .set_df_cstate = vega20_set_df_cstate,
++ .update_pcie_parameters = vega20_update_pcie_parameters
+ };
+
+ void vega20_set_ppt_funcs(struct smu_context *smu)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch
new file mode 100644
index 00000000..86f15b3d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch
@@ -0,0 +1,99 @@
+From 7af8f2b4309f81b47562e1a04053d6073c7e47f0 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 10 Oct 2019 16:42:31 +0800
+Subject: [PATCH 4134/4736] drm/amd/powerplay: enable Arcturus runtime VCN dpm
+ on/off
+
+Enable runtime VCN DPM on/off on Arcturus.
+
+Change-Id: Ie7d94d67cb4c622c96acced1b5ef0f4e63db5aad
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 7 +++++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 30 ++++++++++++++++++++
+ 2 files changed, 37 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 2608c932a775..d270df892223 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -25,6 +25,7 @@
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_vcn.h"
++#include "amdgpu_pm.h"
+ #include "soc15.h"
+ #include "soc15d.h"
+ #include "vcn_v2_0.h"
+@@ -709,6 +710,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ uint32_t rb_bufsz, tmp;
+ int i, j, k, r;
+
++ if (adev->pm.dpm_enabled)
++ amdgpu_dpm_enable_uvd(adev, true);
++
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+@@ -939,6 +943,9 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+ }
+
++ if (adev->pm.dpm_enabled)
++ amdgpu_dpm_enable_uvd(adev, false);
++
+ return 0;
+ }
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 37ac01d37ae8..b33e451c7133 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1898,6 +1898,35 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)
+ return !!(feature_enabled & SMC_DPM_FEATURE);
+ }
+
++static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
++{
++ struct smu_power_context *smu_power = &smu->smu_power;
++ struct smu_power_gate *power_gate = &smu_power->power_gate;
++ int ret = 0;
++
++ if (enable) {
++ if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++ ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
++ if (ret) {
++ pr_err("[EnableVCNDPM] failed!\n");
++ return ret;
++ }
++ }
++ power_gate->vcn_gated = false;
++ } else {
++ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++ ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
++ if (ret) {
++ pr_err("[DisableVCNDPM] failed!\n");
++ return ret;
++ }
++ }
++ power_gate->vcn_gated = true;
++ }
++
++ return ret;
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+ /* translate smu index into arcturus specific index */
+ .get_smu_msg_index = arcturus_get_smu_msg_index,
+@@ -1936,6 +1965,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ .dump_pptable = arcturus_dump_pptable,
+ .get_power_limit = arcturus_get_power_limit,
+ .is_dpm_running = arcturus_is_dpm_running,
++ .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
+ };
+
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch
new file mode 100644
index 00000000..f8616d1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch
@@ -0,0 +1,142 @@
+From 61eca185219bdd4755932490ad86d255017c75ba Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Tue, 15 Oct 2019 10:34:54 -0400
+Subject: [PATCH 4135/4736] drm/amdgpu/display: hook renoir dc to pplib funcs
+
+enable dc get dmp clock table and set dcn watermarks
+via pplib.
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 93 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 2 +-
+ 2 files changed, 94 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 9b2ce0264df6..33564c707051 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -902,6 +902,90 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
+ return PP_SMU_RESULT_FAIL;
+ }
+
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++enum pp_smu_status pp_rn_get_dpm_clock_table(
++ struct pp_smu *pp, struct dpm_clocks *clock_table)
++{
++ const struct dc_context *ctx = pp->dm;
++ struct amdgpu_device *adev = ctx->driver_context;
++ struct smu_context *smu = &adev->smu;
++
++ if (!smu->ppt_funcs)
++ return PP_SMU_RESULT_UNSUPPORTED;
++
++ if (!smu->ppt_funcs->get_dpm_clock_table)
++ return PP_SMU_RESULT_UNSUPPORTED;
++
++ if (!smu->ppt_funcs->get_dpm_clock_table(smu, clock_table))
++ return PP_SMU_RESULT_OK;
++
++ return PP_SMU_RESULT_FAIL;
++}
++
++enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
++ struct pp_smu_wm_range_sets *ranges)
++{
++ const struct dc_context *ctx = pp->dm;
++ struct amdgpu_device *adev = ctx->driver_context;
++ struct smu_context *smu = &adev->smu;
++ struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
++ struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
++ wm_with_clock_ranges.wm_dmif_clocks_ranges;
++ struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
++ wm_with_clock_ranges.wm_mcif_clocks_ranges;
++ int32_t i;
++
++ if (!smu->funcs)
++ return PP_SMU_RESULT_UNSUPPORTED;
++
++ wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
++ wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
++
++ for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
++ if (ranges->reader_wm_sets[i].wm_inst > 3)
++ wm_dce_clocks[i].wm_set_id = WM_SET_A;
++ else
++ wm_dce_clocks[i].wm_set_id =
++ ranges->reader_wm_sets[i].wm_inst;
++
++ wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
++ ranges->reader_wm_sets[i].min_drain_clk_mhz;
++
++ wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
++ ranges->reader_wm_sets[i].max_drain_clk_mhz;
++
++ wm_dce_clocks[i].wm_min_mem_clk_in_khz =
++ ranges->reader_wm_sets[i].min_fill_clk_mhz;
++
++ wm_dce_clocks[i].wm_max_mem_clk_in_khz =
++ ranges->reader_wm_sets[i].max_fill_clk_mhz;
++ }
++
++ for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
++ if (ranges->writer_wm_sets[i].wm_inst > 3)
++ wm_soc_clocks[i].wm_set_id = WM_SET_A;
++ else
++ wm_soc_clocks[i].wm_set_id =
++ ranges->writer_wm_sets[i].wm_inst;
++ wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
++ ranges->writer_wm_sets[i].min_fill_clk_mhz;
++
++ wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
++ ranges->writer_wm_sets[i].max_fill_clk_mhz;
++
++ wm_soc_clocks[i].wm_min_mem_clk_in_khz =
++ ranges->writer_wm_sets[i].min_drain_clk_mhz;
++
++ wm_soc_clocks[i].wm_max_mem_clk_in_khz =
++ ranges->writer_wm_sets[i].max_drain_clk_mhz;
++ }
++
++ smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
++
++ return PP_SMU_RESULT_OK;
++}
++#endif
++
+ void dm_pp_get_funcs(
+ struct dc_context *ctx,
+ struct pp_smu_funcs *funcs)
+@@ -946,6 +1030,15 @@ void dm_pp_get_funcs(
+ funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
+ break;
+ #endif
++
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++ case DCN_VERSION_2_1:
++ funcs->ctx.ver = PP_SMU_VER_RN;
++ funcs->rn_funcs.pp_smu.dm = ctx;
++ funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;
++ funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table;
++ break;
++#endif
+ default:
+ DRM_ERROR("smu version is not supported !\n");
+ break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 6aa1686f59ab..ad082181a448 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -246,7 +246,7 @@ struct pp_smu_funcs_nv {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
+-#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 4
++#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
+ #define PP_SMU_NUM_FCLK_DPM_LEVELS 4
+ #define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch
new file mode 100644
index 00000000..c941254c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch
@@ -0,0 +1,40 @@
+From 1250d2c1f6d25613622af93f47b3bc9f24197a10 Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Tue, 15 Oct 2019 12:47:31 -0400
+Subject: [PATCH 4136/4736] drm/amdgpu/display: fix build error casused by
+ CONFIG_DRM_AMD_DC_DCN2_1
+
+when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config,
+there is build error. struct dpm_clocks shoud not be
+guarded.
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index ad082181a448..95f3193da951 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -243,8 +243,6 @@ struct pp_smu_funcs_nv {
+ };
+ #endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+-
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
+ #define PP_SMU_NUM_FCLK_DPM_LEVELS 4
+@@ -282,7 +280,6 @@ struct pp_smu_funcs_rn {
+ enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
+ struct dpm_clocks *clock_table);
+ };
+-#endif
+
+ struct pp_smu_funcs {
+ struct pp_smu ctx;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch
new file mode 100644
index 00000000..35a27b2b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch
@@ -0,0 +1,31 @@
+From 6296a192954b9f8740eacd7c13acd58e8b4d8cbe Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:49:30 -0400
+Subject: [PATCH 4137/4736] drm/amd/display: change PP_SM defs to 8
+
+DPM level is 8 these were incorrect before. Fix them
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 95f3193da951..60d6620530a8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -245,8 +245,8 @@ struct pp_smu_funcs_nv {
+
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
+-#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
+-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
++#define PP_SMU_NUM_FCLK_DPM_LEVELS 8
++#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8
+
+ struct dpm_clock {
+ uint32_t Freq; // In MHz
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch
new file mode 100644
index 00000000..034871d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch
@@ -0,0 +1,376 @@
+From c96339fb3bc2f93450f7df258c119580584619f1 Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Wed, 18 Sep 2019 09:53:30 -0400
+Subject: [PATCH 4138/4736] drm/amdgpu/powerplay: add renoir funcs to support
+ dc
+
+there are two paths for renoir dc access smu.
+one dc access smu directly using bios smc
+interface: set disply, dprefclk, etc.
+another goes through pplib for get dpm clock
+table and set watermmark.
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 35 +++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 16 ++--
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 96 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39 --------
+ 5 files changed, 141 insertions(+), 61 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 33564c707051..8a5eedb6a37a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -590,10 +590,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
+ if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
+ pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
+ &wm_with_clock_ranges);
+- else if (adev->smu.funcs &&
+- adev->smu.funcs->set_watermarks_for_clock_ranges)
++ else
+ smu_set_watermarks_for_clock_ranges(&adev->smu,
+- &wm_with_clock_ranges);
++ &wm_with_clock_ranges);
+ }
+
+ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
+@@ -666,7 +665,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
+ {
+ const struct dc_context *ctx = pp->dm;
+ struct amdgpu_device *adev = ctx->driver_context;
+- struct smu_context *smu = &adev->smu;
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
+ struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
+ wm_with_clock_ranges.wm_dmif_clocks_ranges;
+@@ -709,15 +707,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
+ ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
+ }
+
+- if (!smu->funcs)
+- return PP_SMU_RESULT_UNSUPPORTED;
+-
+- /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
+- * 1: fail
+- */
+- if (smu_set_watermarks_for_clock_ranges(&adev->smu,
+- &wm_with_clock_ranges))
+- return PP_SMU_RESULT_UNSUPPORTED;
++ smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
+
+ return PP_SMU_RESULT_OK;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 26cacc899dfe..a5255116785b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1813,6 +1813,41 @@ int smu_set_df_cstate(struct smu_context *smu,
+ return ret;
+ }
+
++int smu_write_watermarks_table(struct smu_context *smu)
++{
++ int ret = 0;
++ struct smu_table_context *smu_table = &smu->smu_table;
++ struct smu_table *table = NULL;
++
++ table = &smu_table->tables[SMU_TABLE_WATERMARKS];
++
++ if (!table->cpu_addr)
++ return -EINVAL;
++
++ ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
++ true);
++
++ return ret;
++}
++
++int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
++ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
++{
++ int ret = 0;
++ struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
++ void *table = watermarks->cpu_addr;
++
++ if (!smu->disable_watermark &&
++ smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
++ smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
++ smu_set_watermarks_table(smu, table, clock_ranges);
++ smu->watermarks_bitmap |= WATERMARKS_EXIST;
++ smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
++ }
++
++ return ret;
++}
++
+ const struct amd_ip_funcs smu_ip_funcs = {
+ .name = "smu",
+ .early_init = smu_early_init,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index cdb845f5f23e..bf13bf33ba0c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -470,6 +470,7 @@ struct pptable_funcs {
+ uint32_t dpm_level, uint32_t *freq);
+ int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
++ int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
+ };
+
+ struct smu_funcs
+@@ -495,7 +496,6 @@ struct smu_funcs
+ int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+ int (*set_tool_table_location)(struct smu_context *smu);
+ int (*notify_memory_pool_location)(struct smu_context *smu);
+- int (*write_watermarks_table)(struct smu_context *smu);
+ int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
+ int (*system_features_control)(struct smu_context *smu, bool en);
+ int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
+@@ -533,8 +533,6 @@ struct smu_funcs
+ int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
+ struct smu_clock_info *clocks);
+ int (*notify_smu_enable_pwe)(struct smu_context *smu);
+- int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
+- struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
+ int (*conv_power_profile_to_pplib_workload)(int power_profile);
+ uint32_t (*get_fan_control_mode)(struct smu_context *smu);
+ int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
+@@ -599,9 +597,6 @@ struct smu_funcs
+ ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+ #define smu_gfx_off_control(smu, enable) \
+ ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
+-
+-#define smu_write_watermarks_table(smu) \
+- ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
+ #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+ ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+ #define smu_system_features_control(smu, en) \
+@@ -741,8 +736,6 @@ struct smu_funcs
+ ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+ #define smu_notify_smu_enable_pwe(smu) \
+ ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
+-#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
+- ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+ #define smu_dpm_set_uvd_enable(smu, enable) \
+ ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+ #define smu_dpm_set_vce_enable(smu, enable) \
+@@ -781,9 +774,10 @@ struct smu_funcs
+ ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+ #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
+ ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+-
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
++#define smu_get_dpm_clock_table(smu, clock_table) \
++ ((smu)->ppt_funcs->get_dpm_clock_table ? (smu)->ppt_funcs->get_dpm_clock_table((smu), (clock_table)) : -EINVAL)
+
+ #define smu_override_pcie_parameters(smu) \
+ ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+@@ -823,6 +817,10 @@ int smu_sys_get_pp_table(struct smu_context *smu, void **table);
+ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
+ int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
+ enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
++int smu_write_watermarks_table(struct smu_context *smu);
++int smu_set_watermarks_for_clock_ranges(
++ struct smu_context *smu,
++ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
+
+ /* smu to display interface */
+ extern int smu_display_configuration_change(struct smu_context *smu, const
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 6aedffd739db..fa314c275a82 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -416,6 +416,40 @@ static int renoir_get_profiling_clk_mask(struct smu_context *smu,
+ return 0;
+ }
+
++/**
++ * This interface get dpm clock table for dc
++ */
++static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
++{
++ DpmClocks_t *table = smu->smu_table.clocks_table;
++ int i;
++
++ if (!clock_table || !table)
++ return -EINVAL;
++
++ for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
++ clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
++ clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
++ }
++
++ for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
++ clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
++ clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
++ }
++
++ for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
++ clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
++ clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
++ }
++
++ for (i = 0; i< PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) {
++ clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
++ clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
++ }
++
++ return 0;
++}
++
+ static int renoir_force_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type, uint32_t mask)
+ {
+@@ -546,6 +580,66 @@ static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_fo
+ return ret;
+ }
+
++/* save watermark settings into pplib smu structure,
++ * also pass data to smu controller
++ */
++static int renoir_set_watermarks_table(
++ struct smu_context *smu,
++ void *watermarks,
++ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
++{
++ int i;
++ int ret = 0;
++ Watermarks_t *table = watermarks;
++
++ if (!table || !clock_ranges)
++ return -EINVAL;
++
++ if (clock_ranges->num_wm_dmif_sets > 4 ||
++ clock_ranges->num_wm_mcif_sets > 4)
++ return -EINVAL;
++
++ /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
++ for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
++ table->WatermarkRow[WM_DCFCLK][i].MinClock =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
++ table->WatermarkRow[WM_DCFCLK][i].MaxClock =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
++ table->WatermarkRow[WM_DCFCLK][i].MinMclk =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
++ table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
++ table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
++ clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
++ }
++
++ for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
++ table->WatermarkRow[WM_SOCCLK][i].MinClock =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
++ table->WatermarkRow[WM_SOCCLK][i].MaxClock =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
++ table->WatermarkRow[WM_SOCCLK][i].MinMclk =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
++ table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
++ cpu_to_le16((uint16_t)
++ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
++ table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
++ clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
++ }
++
++ /* pass data to smu controller */
++ ret = smu_write_watermarks_table(smu);
++
++ return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_smu_msg_index = renoir_get_smu_msg_index,
+ .get_smu_table_index = renoir_get_smu_table_index,
+@@ -562,6 +656,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .force_clk_levels = renoir_force_clk_levels,
+ .set_power_profile_mode = renoir_set_power_profile_mode,
+ .set_performance_level = renoir_set_performance_level,
++ .get_dpm_clock_table = renoir_get_dpm_clock_table,
++ .set_watermarks_table = renoir_set_watermarks_table,
+ };
+
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index df1f2b99fed7..ac02bcd24da0 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -771,23 +771,6 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
+-{
+- int ret = 0;
+- struct smu_table_context *smu_table = &smu->smu_table;
+- struct smu_table *table = NULL;
+-
+- table = &smu_table->tables[SMU_TABLE_WATERMARKS];
+-
+- if (!table->cpu_addr)
+- return -EINVAL;
+-
+- ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
+- true);
+-
+- return ret;
+-}
+-
+ static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+ {
+ int ret;
+@@ -1337,26 +1320,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ return ret;
+ }
+
+-static int
+-smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
+- dm_pp_wm_sets_with_clock_ranges_soc15
+- *clock_ranges)
+-{
+- int ret = 0;
+- struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+- void *table = watermarks->cpu_addr;
+-
+- if (!smu->disable_watermark &&
+- smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+- smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+- smu_set_watermarks_table(smu, table, clock_ranges);
+- smu->watermarks_bitmap |= WATERMARKS_EXIST;
+- smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+- }
+-
+- return ret;
+-}
+-
+ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ {
+ int ret = 0;
+@@ -1854,7 +1817,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ .parse_pptable = smu_v11_0_parse_pptable,
+ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+ .write_pptable = smu_v11_0_write_pptable,
+- .write_watermarks_table = smu_v11_0_write_watermarks_table,
+ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .init_display_count = smu_v11_0_init_display_count,
+@@ -1870,7 +1832,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ .read_sensor = smu_v11_0_read_sensor,
+ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+- .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
+ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch
new file mode 100644
index 00000000..702b5411
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch
@@ -0,0 +1,31 @@
+From 8f499afce3448349e730f7865d953f1ef96085f9 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Tue, 15 Oct 2019 17:24:25 +0800
+Subject: [PATCH 4139/4736] drm/amdgpu: add GFX_PIPELINE capacity check for
+ updating gfx cgpg
+
+Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 24802e4d25e5..f5322313f93c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4294,7 +4294,8 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
+ gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
+ } else {
+ gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
+- gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
++ if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
++ gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
+ }
+
+ amdgpu_gfx_rlc_exit_safe_mode(adev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch
new file mode 100644
index 00000000..6cd21b6e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch
@@ -0,0 +1,64 @@
+From 3056eac53726a1cb97a3d989fb62d0cd57cf27e4 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Tue, 15 Oct 2019 17:11:49 +0800
+Subject: [PATCH 4140/4736] drm/amdgpu: fix S3 failed as RLC safe mode entry
+ stucked in polloing gfx acq
+
+Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response.
+The patch can fix VCN IB test failed and DAL get dispaly count failed issue.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 -----
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
+ 2 files changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index f5322313f93c..16043b824f97 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4285,9 +4285,6 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
+ {
+ amdgpu_gfx_rlc_enter_safe_mode(adev);
+
+- if (is_support_sw_smu(adev) && !enable)
+- smu_set_gfx_cgpg(&adev->smu, enable);
+-
+ if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
+ gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
+ if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
+@@ -4564,8 +4561,6 @@ static int gfx_v9_0_set_powergating_state(void *handle,
+ gfx_v9_0_enable_cp_power_gating(adev, false);
+
+ /* update gfx cgpg state */
+- if (is_support_sw_smu(adev) && enable)
+- smu_set_gfx_cgpg(&adev->smu, enable);
+ gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
+
+ /* update mgcg state */
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a5255116785b..d0a25dd8fcfc 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1188,6 +1188,7 @@ static int smu_hw_init(void *handle)
+ if (adev->flags & AMD_IS_APU) {
+ smu_powergate_sdma(&adev->smu, false);
+ smu_powergate_vcn(&adev->smu, false);
++ smu_set_gfx_cgpg(&adev->smu, true);
+ }
+
+ if (!smu->pm_enabled)
+@@ -1350,6 +1351,9 @@ static int smu_resume(void *handle)
+ if (ret)
+ goto failed;
+
++ if (smu->is_apu)
++ smu_set_gfx_cgpg(&adev->smu, true);
++
+ mutex_unlock(&smu->mutex);
+
+ pr_info("SMU is resumed successfully!\n");
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch
new file mode 100644
index 00000000..17141737
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch
@@ -0,0 +1,34 @@
+From 4bde2a3a41934d91fdbf726420c657fa1ce6e143 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 14 Aug 2019 09:09:19 -0400
+Subject: [PATCH 4141/4736] drm/amdgpu: set debug register values at init time
+
+We need to initialize the SPI_GDBG_TRAP_MASK EXCP_EN and REPLACE
+to 0, along with SPI_GDBG_TRAP_DATA0, and SPI_GDBG_TRAP_DATA1 when
+we initialize the debug vmid.
+
+Change-Id: Ib3887397578d63c110a4247d6b61bf62111bc1c5
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 16043b824f97..5e7a01c322ea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2273,6 +2273,11 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
+ TRAP_EN, 1);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
++
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
++
+ }
+
+ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch
new file mode 100644
index 00000000..deb670f1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch
@@ -0,0 +1,225 @@
+From 6d39c416f207a26d59b46ecff9aeb6023b29043d Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 14 Aug 2019 09:05:52 -0400
+Subject: [PATCH 4142/4736] drm/amdkfd: No longer support debug reg data vars
+
+The KFD debugger uses data0/data1 for the debug trap handler, we
+we need to prevent the them being updated from userspace.
+
+Change-Id: I91086062c744a70a2706050aa35f61014551c5ef
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 1 -
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 22 ----------------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 3 ---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 -----
+ .../gpu/drm/amd/include/kgd_kfd_interface.h | 3 ---
+ include/uapi/linux/kfd_ioctl.h | 26 +++++++------------
+ 6 files changed, 9 insertions(+), 52 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index db39c6653cce..7288810e0df5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -288,7 +288,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
+ .get_hive_id = amdgpu_amdkfd_get_hive_id,
+ .enable_debug_trap = kgd_gfx_v9_enable_debug_trap,
+ .disable_debug_trap = kgd_gfx_v9_disable_debug_trap,
+- .set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data,
+ .set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override,
+ .set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
+ .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 530b8ada1f8f..dae572c776cc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -845,9 +845,6 @@ uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd,
+ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
+
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
+-
+ data = 0;
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
+
+@@ -864,9 +861,6 @@ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd)
+
+ mutex_lock(&adev->grbm_idx_mutex);
+
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
+-
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
+
+ mutex_unlock(&adev->grbm_idx_mutex);
+@@ -874,21 +868,6 @@ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd)
+ return 0;
+ }
+
+-uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd,
+- int trap_data0,
+- int trap_data1)
+-{
+- struct amdgpu_device *adev = get_amdgpu_device(kgd);
+-
+- mutex_lock(&adev->grbm_idx_mutex);
+-
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), trap_data0);
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), trap_data1);
+-
+- mutex_unlock(&adev->grbm_idx_mutex);
+- return 0;
+-}
+-
+ uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd,
+ uint32_t trap_override,
+ uint32_t trap_mask)
+@@ -1037,7 +1016,6 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
+ .get_hive_id = amdgpu_amdkfd_get_hive_id,
+ .enable_debug_trap = kgd_gfx_v9_enable_debug_trap,
+ .disable_debug_trap = kgd_gfx_v9_disable_debug_trap,
+- .set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data,
+ .set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override,
+ .set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
+ .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+index 7611ba466aa4..2b41d810c68e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+@@ -67,9 +67,6 @@ uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd,
+ uint32_t trap_debug_wave_launch_mode,
+ uint32_t vmid);
+ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd);
+-uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd,
+- int trap_data0,
+- int trap_data1);
+ uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd,
+ uint32_t trap_override,
+ uint32_t trap_mask);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index c60c4480d124..52acb0064939 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2763,12 +2763,6 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ }
+ break;
+
+- case KFD_IOC_DBG_TRAP_SET_TRAP_DATA:
+- r = dev->kfd2kgd->set_debug_trap_data(dev->kgd,
+- data1,
+- data2);
+- break;
+-
+ case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
+ r = dev->kfd2kgd->set_wave_launch_trap_override(
+ dev->kgd,
+diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+index db00c2ec9277..975961a298d9 100644
+--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+@@ -327,9 +327,6 @@ struct kfd2kgd_calls {
+ uint32_t trap_debug_wave_launch_mode,
+ uint32_t vmid);
+ uint32_t (*disable_debug_trap)(struct kgd_dev *kgd);
+- uint32_t (*set_debug_trap_data)(struct kgd_dev *kgd,
+- int trap_data0,
+- int trap_data1);
+ uint32_t (*set_wave_launch_trap_override)(struct kgd_dev *kgd,
+ uint32_t trap_override,
+ uint32_t trap_mask);
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 8c9a5ab34d9e..760b3d6159fa 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -28,8 +28,8 @@
+
+ #define KFD_IOCTL_MAJOR_VERSION 1
+ #define KFD_IOCTL_MINOR_VERSION 2
+-#define KFD_IOCTL_DBG_MAJOR_VERSION 0
+-#define KFD_IOCTL_DBG_MINOR_VERSION 2
++#define KFD_IOCTL_DBG_MAJOR_VERSION 1
++#define KFD_IOCTL_DBG_MINOR_VERSION 0
+
+ struct kfd_ioctl_get_version_args {
+ __u32 major_version; /* from KFD */
+@@ -219,21 +219,13 @@ struct kfd_ioctl_dbg_wave_control_args {
+ */
+ #define KFD_IOC_DBG_TRAP_ENABLE 0
+
+-/* KFD_IOC_DBG_TRAP_SET_TRAP_DATA:
+- * ptr: unused
+- * data1: SPI_GDBG_TRAP_DATA0
+- * data2: SPI_GDBG_TRAP_DATA1
+- * data3: unused
+- */
+-#define KFD_IOC_DBG_TRAP_SET_TRAP_DATA 1
+-
+ /* KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
+ * ptr: unused
+ * data1: override mode: 0=OR, 1=REPLACE
+ * data2: mask
+ * data3: unused
+ */
+-#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE 2
++#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE 1
+
+ /* KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
+ * ptr: unused
+@@ -241,7 +233,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+ * data2: unused
+ * data3: unused
+ */
+-#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE 3
++#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE 2
+
+ /* KFD_IOC_DBG_TRAP_NODE_SUSPEND:
+ * ptr: pointer to an array of Queues IDs
+@@ -249,7 +241,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+ * data2: number of queues
+ * data3: grace period
+ */
+-#define KFD_IOC_DBG_TRAP_NODE_SUSPEND 4
++#define KFD_IOC_DBG_TRAP_NODE_SUSPEND 3
+
+ /* KFD_IOC_DBG_TRAP_NODE_RESUME:
+ * ptr: pointer to an array of Queues IDs
+@@ -257,7 +249,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+ * data2: number of queues
+ * data3: unused
+ */
+-#define KFD_IOC_DBG_TRAP_NODE_RESUME 5
++#define KFD_IOC_DBG_TRAP_NODE_RESUME 4
+
+ /* KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
+ * ptr: unused
+@@ -265,7 +257,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+ * data2: flags (IN)
+ * data3: suspend[2:2], event type [1:0] (OUT)
+ */
+-#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 6
++#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 5
+
+ /* KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
+ * ptr: user buffer (IN)
+@@ -273,7 +265,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+ * data2: number of queue snapshots (IN/OUT) - 0 for IN ignores buffer writes
+ * data3: unused
+ */
+-#define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 7
++#define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 6
+
+ /* KFD_IOC_DBG_TRAP_GET_VERSION:
+ * prt: unsused
+@@ -281,7 +273,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+ * data2: minor version (OUT)
+ * data3: unused
+ */
+-#define KFD_IOC_DBG_TRAP_GET_VERSION 8
++#define KFD_IOC_DBG_TRAP_GET_VERSION 7
+
+ struct kfd_ioctl_dbg_trap_args {
+ __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch
new file mode 100644
index 00000000..2ab9fda2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch
@@ -0,0 +1,40 @@
+From 572c9105eb8273143b2327887ef08c9c06362ed0 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 14 Aug 2019 09:32:55 -0400
+Subject: [PATCH 4143/4736] drm/amdkfd: Debugger: block non default trap masks
+
+On the current hardware, we only support the default trap mask,
+so we need to block non default values until supported in by
+future hardware.
+
+Change-Id: Iad94057bb33564b972cc3e7e0f401340f215c8ba
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 52acb0064939..22f7aa576c7e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2764,6 +2764,17 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ break;
+
+ case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
++ if (data2 != 0) {
++ /* On current hardware, we only support a trap
++ * mask value of 0. This is because the debug
++ * trap mask is global and shared by all processes
++ * on current hardware.
++ */
++ pr_err("Invalid trap override option: %i\n",
++ data2);
++ r = -EINVAL;
++ goto unlock_out;
++ }
+ r = dev->kfd2kgd->set_wave_launch_trap_override(
+ dev->kgd,
+ data1,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch
new file mode 100644
index 00000000..482f0848
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch
@@ -0,0 +1,62 @@
+From b375022c24b01407c736e4a959632368abab0ec1 Mon Sep 17 00:00:00 2001
+From: Philip Yang <Philip.Yang@amd.com>
+Date: Thu, 3 Oct 2019 14:18:25 -0400
+Subject: [PATCH 4144/4736] drm/amdgpu: user pages array memory leak fix
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+user_pages array should always be freed after validation regardless if
+user pages are changed after bo is created because with HMM change parse
+bo always allocate user pages array to get user pages for userptr bo.
+
+v2: remove unused local variable and amend commit
+
+v3: add back get user pages in gem_userptr_ioctl, to detect application
+bug where an userptr VMA is not ananymous memory and reject it.
+
+Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
+
+Signed-off-by: Philip Yang <Philip.Yang@amd.com>
+Tested-by: Joe Barnett <thejoe@gmail.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index ba43f3f6467b..e8dfbcfad034 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -475,7 +475,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
+
+ list_for_each_entry(lobj, validated, tv.head) {
+ struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
+- bool binding_userptr = false;
+ struct mm_struct *usermm;
+
+ usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
+@@ -492,17 +491,14 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
+
+ amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
+ lobj->user_pages);
+- binding_userptr = true;
+ }
+
+ r = amdgpu_cs_validate(p, bo);
+ if (r)
+ return r;
+
+- if (binding_userptr) {
+- kvfree(lobj->user_pages);
+- lobj->user_pages = NULL;
+- }
++ kvfree(lobj->user_pages);
++ lobj->user_pages = NULL;
+ }
+ return 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch
new file mode 100644
index 00000000..b52437d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch
@@ -0,0 +1,35 @@
+From a8345914d289569a43abf805e2492c036e8d1cae Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 11 Oct 2019 10:32:59 -0400
+Subject: [PATCH 4145/4736] dmr/amdgpu: Fix crash on SRIOV for
+ ERREVENT_ATHUB_INTERRUPT interrupt.
+
+Ignre the ERREVENT_ATHUB_INTERRUPT for systems without RAS.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-and-tested-by: Jack Zhang <Jack.Zhang1@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index f3f3a98f93b3..1ca613014126 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1886,6 +1886,12 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
+
+ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
+ {
++ uint32_t hw_supported, supported;
++
++ amdgpu_ras_check_supported(adev, &hw_supported, &supported);
++ if (!hw_supported)
++ return;
++
+ if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
+ DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n");
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch
new file mode 100644
index 00000000..d96baf07
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch
@@ -0,0 +1,31 @@
+From a2d71268b375d0bb2a5a0f2ad251ada05b44be49 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 14:33:39 -0500
+Subject: [PATCH 4146/4736] drm/amdgpu: move pci_save_state into suspend path
+
+for amdgpu_device_suspend. This follows the logic
+in the resume path.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 521af22ad916..cb4192e6062a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3179,8 +3179,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ */
+ amdgpu_bo_evict_vram(adev);
+
+- pci_save_state(dev->pdev);
+ if (suspend) {
++ pci_save_state(dev->pdev);
+ /* Shut down the device */
+ pci_disable_device(dev->pdev);
+ pci_set_power_state(dev->pdev, PCI_D3hot);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch
new file mode 100644
index 00000000..e4be600c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch
@@ -0,0 +1,54 @@
+From d36140c553925eecd978e388bc78d10af37eb90f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 14:57:21 -0500
+Subject: [PATCH 4147/4736] drm/amdgpu: move gpu reset out of
+ amdgpu_device_suspend
+
+Move it into the caller. There are cases were we don't
+want it. We need it for hibernation, but we don't need
+it for runtime pm, so drop it for runtime pm.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++++++-
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index cb4192e6062a..46723a10d98a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3184,10 +3184,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ /* Shut down the device */
+ pci_disable_device(dev->pdev);
+ pci_set_power_state(dev->pdev, PCI_D3hot);
+- } else {
+- r = amdgpu_asic_reset(adev);
+- if (r)
+- DRM_ERROR("amdgpu asic reset failed\n");
+ }
+
+ return 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 658fa3fd5fad..5ab426726849 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1201,8 +1201,13 @@ static int amdgpu_pmops_resume(struct device *dev)
+ static int amdgpu_pmops_freeze(struct device *dev)
+ {
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
++ struct amdgpu_device *adev = drm_dev->dev_private;
++ int r;
+
+- return amdgpu_device_suspend(drm_dev, false, true);
++ r = amdgpu_device_suspend(drm_dev, false, true);
++ if (r)
++ return r;
++ return amdgpu_asic_reset(adev);
+ }
+
+ static int amdgpu_pmops_thaw(struct device *dev)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch
new file mode 100644
index 00000000..247673fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch
@@ -0,0 +1,60 @@
+From a3b613233260dda95131f1651b3eb869ad0c9bbe Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 11:01:11 -0500
+Subject: [PATCH 4148/4736] drm/amdgpu: remove in_baco_reset hack
+
+It was a vega20 specific hack. Check if we are in reset
+and what reset method we are using.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 4 ++--
+ 3 files changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index a994117c4edc..e4172f9bece6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1008,8 +1008,6 @@ struct amdgpu_device {
+ int asic_reset_res;
+ struct work_struct xgmi_reset_work;
+
+- bool in_baco_reset;
+-
+ long gfx_timeout;
+ long sdma_timeout;
+ long video_timeout;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 82b5bc4ddf9b..5fadb237d103 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -515,8 +515,6 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+
+ dev_info(adev->dev, "GPU BACO reset\n");
+
+- adev->in_baco_reset = 1;
+-
+ return 0;
+ }
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 3d3c647a63ff..9295bd90b792 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -493,8 +493,8 @@ static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
+ "Failed to init sclk threshold!",
+ return ret);
+
+- if (adev->in_baco_reset) {
+- adev->in_baco_reset = 0;
++ if (adev->in_gpu_reset &&
++ (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) {
+
+ ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
+ if (ret)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch
new file mode 100644
index 00000000..f3fe7ccb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch
@@ -0,0 +1,100 @@
+From 34656170efd682732e9b3e565cb013055295dbbe Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 14:27:01 -0400
+Subject: [PATCH 4149/4736] drm/amdgpu/soc15: add support for baco reset with
+ swSMU
+
+Add support for vega20 when the swSMU path is used.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 53 ++++++++++++++++++++----------
+ 1 file changed, 35 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 5fadb237d103..438722c0b76a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -477,15 +477,22 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
+
+ static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
+ {
+- void *pp_handle = adev->powerplay.pp_handle;
+- const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++ if (is_support_sw_smu(adev)) {
++ struct smu_context *smu = &adev->smu;
+
+- if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
+- *cap = false;
+- return -ENOENT;
+- }
++ *cap = smu_baco_is_support(smu);
++ return 0;
++ } else {
++ void *pp_handle = adev->powerplay.pp_handle;
++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++ if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
++ *cap = false;
++ return -ENOENT;
++ }
+
+- return pp_funcs->get_asic_baco_capability(pp_handle, cap);
++ return pp_funcs->get_asic_baco_capability(pp_handle, cap);
++ }
+ }
+
+ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+@@ -494,27 +501,37 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+- if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
+- return -ENOENT;
+-
+ /* avoid NBIF got stuck when do RAS recovery in BACO reset */
+ if (ras && ras->supported)
+ adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
+
+- /* enter BACO state */
+- if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+- return -EIO;
++ dev_info(adev->dev, "GPU BACO reset\n");
++
++ if (is_support_sw_smu(adev)) {
++ struct smu_context *smu = &adev->smu;
++
++ if (smu_baco_reset(smu))
++ return -EIO;
++ } else {
++ void *pp_handle = adev->powerplay.pp_handle;
++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++ if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++ return -ENOENT;
++
++ /* enter BACO state */
++ if (pp_funcs->set_asic_baco_state(pp_handle, 1))
++ return -EIO;
+
+- /* exit BACO state */
+- if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+- return -EIO;
++ /* exit BACO state */
++ if (pp_funcs->set_asic_baco_state(pp_handle, 0))
++ return -EIO;
++ }
+
+ /* re-enable doorbell interrupt after BACO exit */
+ if (ras && ras->supported)
+ adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
+
+- dev_info(adev->dev, "GPU BACO reset\n");
+-
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch
new file mode 100644
index 00000000..4819597a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch
@@ -0,0 +1,44 @@
+From c6859827ffe21a626ef9a31179f937859d553c1d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 14:40:26 -0500
+Subject: [PATCH 4150/4736] drm/amdgpu: add new BIF 4.1 register for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
+index a761ba07f937..fce965984e76 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
+@@ -27,6 +27,7 @@
+ #define mmMM_INDEX 0x0
+ #define mmMM_INDEX_HI 0x6
+ #define mmMM_DATA 0x1
++#define mmCC_BIF_BX_FUSESTRAP0 0x14D7
+ #define mmBUS_CNTL 0x1508
+ #define mmCONFIG_CNTL 0x1509
+ #define mmCONFIG_MEMSIZE 0x150a
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
+index 8fbfd0261d27..39cc4880beb4 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
+@@ -32,6 +32,8 @@
+ #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+ #define MM_DATA__MM_DATA_MASK 0xffffffff
+ #define MM_DATA__MM_DATA__SHIFT 0x0
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
+ #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
+ #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
+ #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch
new file mode 100644
index 00000000..bae6f731
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch
@@ -0,0 +1,44 @@
+From 58c05ba33e4ff776d63e782cf1d41af513c4732e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 11 Feb 2019 12:28:45 -0500
+Subject: [PATCH 4151/4736] drm/amdgpu: add new BIF 5.0 register for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
+index 809759f7bb81..8d05d6ca1c8d 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
+@@ -27,6 +27,7 @@
+ #define mmMM_INDEX 0x0
+ #define mmMM_INDEX_HI 0x6
+ #define mmMM_DATA 0x1
++#define mmCC_BIF_BX_FUSESTRAP0 0x14D7
+ #define mmCC_BIF_BX_STRAP2 0x152A
+ #define mmBIF_MM_INDACCESS_CNTL 0x1500
+ #define mmBIF_DOORBELL_APER_EN 0x1501
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
+index adc71b01f793..73435687d049 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
+@@ -32,6 +32,8 @@
+ #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+ #define MM_DATA__MM_DATA_MASK 0xffffffff
+ #define MM_DATA__MM_DATA__SHIFT 0x0
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
+ #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
+ #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+ #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch
new file mode 100644
index 00000000..3640ee54
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch
@@ -0,0 +1,44 @@
+From ebcfe185bdd35b9616c29db859721ca3123c7933 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 15:14:18 -0500
+Subject: [PATCH 4152/4736] drm/amdgpu: add new SMU 7.0.1 registers for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
+index dbc2e723f659..71169daa701a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
+@@ -49,6 +49,7 @@
+ #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+ #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+ #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
++#define ixCG_SPLL_STATUS 0xC050015C
+ #define ixSPLL_CNTL_MODE 0xc0500160
+ #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+ #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+index 6af9f0217b34..61a9a84e0c3a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+@@ -194,6 +194,8 @@
+ #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+ #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch
new file mode 100644
index 00000000..e4183cdc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch
@@ -0,0 +1,44 @@
+From 4e9bf31212fdf138cab1d6bc69156609822a381b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 15:16:43 -0500
+Subject: [PATCH 4153/4736] drm/amdgpu: add new SMU 7.1.2 registers for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+index bd3685166779..351446754c72 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+@@ -49,6 +49,7 @@
+ #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+ #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+ #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
++#define ixCG_SPLL_STATUS 0xC050015C
+ #define ixSPLL_CNTL_MODE 0xc0500160
+ #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+ #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+index 627906674fe8..4bfd5f8ba66c 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+@@ -194,6 +194,8 @@
+ #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+ #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
new file mode 100644
index 00000000..bcb1a5c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
@@ -0,0 +1,44 @@
+From a991be32477d0862ec2ca93fc8c63f304570b897 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 15:18:52 -0500
+Subject: [PATCH 4154/4736] drm/amdgpu: add new SMU 7.1.3 registers for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+index f35aba72e640..21da61c398f5 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+@@ -52,6 +52,7 @@
+ #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+ #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+ #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
++#define ixCG_SPLL_STATUS 0xC050015C
+ #define ixSPLL_CNTL_MODE 0xc0500160
+ #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+ #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+index 481ee6560aa9..f64fe0fbcb32 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+@@ -220,6 +220,8 @@
+ #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+ #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch
new file mode 100644
index 00000000..47666b97
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch
@@ -0,0 +1,83 @@
+From 57a7d38e14d4b5eda2b000265b9714fc137b83df Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Sun, 10 Feb 2019 21:57:55 -0500
+Subject: [PATCH 4155/4736] drm/amdgpu/powerplay: add core support for
+ pre-SOC15 baco
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds core support for BACO on pre-vega asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/powerplay/hwmgr/common_baco.c | 19 +++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/common_baco.h | 13 +++++++++++++
+ 2 files changed, 32 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
+index 9c57c1f67749..1c73776bd606 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
+@@ -79,6 +79,25 @@ static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 m
+ return ret;
+ }
+
++bool baco_program_registers(struct pp_hwmgr *hwmgr,
++ const struct baco_cmd_entry *entry,
++ const u32 array_size)
++{
++ u32 i, reg = 0;
++
++ for (i = 0; i < array_size; i++) {
++ if ((entry[i].cmd == CMD_WRITE) ||
++ (entry[i].cmd == CMD_READMODIFYWRITE) ||
++ (entry[i].cmd == CMD_WAITFOR))
++ reg = entry[i].reg_offset;
++ if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
++ entry[i].shift, entry[i].val, entry[i].timeout))
++ return false;
++ }
++
++ return true;
++}
++
+ bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
+ const struct soc15_baco_cmd_entry *entry,
+ const u32 array_size)
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
+index 95296c916f4e..8393eb62706d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
+@@ -33,6 +33,15 @@ enum baco_cmd_type {
+ CMD_DELAY_US,
+ };
+
++struct baco_cmd_entry {
++ enum baco_cmd_type cmd;
++ uint32_t reg_offset;
++ uint32_t mask;
++ uint32_t shift;
++ uint32_t timeout;
++ uint32_t val;
++};
++
+ struct soc15_baco_cmd_entry {
+ enum baco_cmd_type cmd;
+ uint32_t hwip;
+@@ -44,6 +53,10 @@ struct soc15_baco_cmd_entry {
+ uint32_t timeout;
+ uint32_t val;
+ };
++
++extern bool baco_program_registers(struct pp_hwmgr *hwmgr,
++ const struct baco_cmd_entry *entry,
++ const u32 array_size);
+ extern bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
+ const struct soc15_baco_cmd_entry *entry,
+ const u32 array_size);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch
new file mode 100644
index 00000000..3e029169
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch
@@ -0,0 +1,302 @@
+From 718f101490fedd049c6a6a156d9af5701769cdb5 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:35:50 -0500
+Subject: [PATCH 4156/4736] drm/amdgpu/powerplay: add support for BACO on tonga
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Tonga.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c | 221 ++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.h | 32 +++
+ 3 files changed, 254 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index cc63705920dc..d66cfe5f80f9 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ pp_overdriver.o smu_helper.o \
+ vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
+- vega12_baco.o smu9_baco.o
++ vega12_baco.o smu9_baco.o tonga_baco.o
+
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+new file mode 100644
+index 000000000000..37a41b83c913
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+@@ -0,0 +1,221 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "tonga_baco.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "dce/dce_10_0_d.h"
++#include "dce/dce_10_0_sh_mask.h"
++
++#include "smu/smu_7_1_2_d.h"
++#include "smu/smu_7_1_2_sh_mask.h"
++
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 },
++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
++};
++
++int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ *cap = false;
++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++ return 0;
++
++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++ *cap = true;
++
++ return 0;
++}
++
++int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ reg = RREG32(mmBACO_CNTL);
++
++ if (reg & BACO_CNTL__BACO_MODE_MASK)
++ /* gfx has already entered BACO state */
++ *state = BACO_STATE_IN;
++ else
++ *state = BACO_STATE_OUT;
++ return 0;
++}
++
++int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++ enum BACO_STATE cur_state;
++
++ tonga_baco_get_state(hwmgr, &cur_state);
++
++ if (cur_state == state)
++ /* aisc already in the target state */
++ return 0;
++
++ if (state == BACO_STATE_IN) {
++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++ ARRAY_SIZE(enable_fb_req_rej_tbl));
++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++ baco_program_registers(hwmgr, turn_off_plls_tbl,
++ ARRAY_SIZE(turn_off_plls_tbl));
++ if (baco_program_registers(hwmgr, enter_baco_tbl,
++ ARRAY_SIZE(enter_baco_tbl)))
++ return 0;
++
++ } else if (state == BACO_STATE_OUT) {
++ /* HW requires at least 20ms between regulator off and on */
++ msleep(20);
++ /* Execute Hardware BACO exit sequence */
++ if (baco_program_registers(hwmgr, exit_baco_tbl,
++ ARRAY_SIZE(exit_baco_tbl))) {
++ if (baco_program_registers(hwmgr, clean_baco_tbl,
++ ARRAY_SIZE(clean_baco_tbl)))
++ return 0;
++ }
++ }
++
++ return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+new file mode 100644
+index 000000000000..21301b043255
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __TONGA_BACO_H__
++#define __TONGA_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch
new file mode 100644
index 00000000..823fb413
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch
@@ -0,0 +1,100 @@
+From c33a4cf13aff4cdcef3fdc3426ed18f5a3d4c9ef Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 11:56:56 -0500
+Subject: [PATCH 4157/4736] drm/amdgpu/powerplay: add support for BACO on
+ Iceland
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Iceland asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c | 54 ++++++++++++++++---
+ 1 file changed, 48 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+index 37a41b83c913..84b7217b7bda 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+@@ -152,6 +152,36 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
+ };
+
++static const struct baco_cmd_entry gpio_tbl_iceland[] =
++{
++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }
++};
++
++static const struct baco_cmd_entry exit_baco_tbl_iceland[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++ { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl_iceland[] =
++{
++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
++};
++
+ int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+@@ -195,7 +225,10 @@ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ return 0;
+
+ if (state == BACO_STATE_IN) {
+- baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++ if (hwmgr->chip_id == CHIP_TOPAZ)
++ baco_program_registers(hwmgr, gpio_tbl_iceland, ARRAY_SIZE(gpio_tbl_iceland));
++ else
++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
+ baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
+ ARRAY_SIZE(enable_fb_req_rej_tbl));
+ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
+@@ -209,11 +242,20 @@ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ /* HW requires at least 20ms between regulator off and on */
+ msleep(20);
+ /* Execute Hardware BACO exit sequence */
+- if (baco_program_registers(hwmgr, exit_baco_tbl,
+- ARRAY_SIZE(exit_baco_tbl))) {
+- if (baco_program_registers(hwmgr, clean_baco_tbl,
+- ARRAY_SIZE(clean_baco_tbl)))
+- return 0;
++ if (hwmgr->chip_id == CHIP_TOPAZ) {
++ if (baco_program_registers(hwmgr, exit_baco_tbl_iceland,
++ ARRAY_SIZE(exit_baco_tbl_iceland))) {
++ if (baco_program_registers(hwmgr, clean_baco_tbl_iceland,
++ ARRAY_SIZE(clean_baco_tbl_iceland)))
++ return 0;
++ }
++ } else {
++ if (baco_program_registers(hwmgr, exit_baco_tbl,
++ ARRAY_SIZE(exit_baco_tbl))) {
++ if (baco_program_registers(hwmgr, clean_baco_tbl,
++ ARRAY_SIZE(clean_baco_tbl)))
++ return 0;
++ }
+ }
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch
new file mode 100644
index 00000000..6bbe9db2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch
@@ -0,0 +1,300 @@
+From 0f5e17c868a5dd7e9b76cee03469690ba93de246 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:36:40 -0500
+Subject: [PATCH 4158/4736] drm/amdgpu/powerplay: add support for BACO on
+ polaris
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Polaris asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
+ .../drm/amd/powerplay/hwmgr/polaris_baco.c | 218 ++++++++++++++++++
+ .../drm/amd/powerplay/hwmgr/polaris_baco.h | 32 +++
+ 3 files changed, 251 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index d66cfe5f80f9..a1535e1430d5 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ pp_overdriver.o smu_helper.o \
+ vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
+- vega12_baco.o smu9_baco.o tonga_baco.o
++ vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o
+
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+new file mode 100644
+index 000000000000..d0c9de88f474
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+@@ -0,0 +1,218 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "polaris_baco.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "dce/dce_11_0_d.h"
++#include "dce/dce_11_0_sh_mask.h"
++
++#include "smu/smu_7_1_3_d.h"
++#include "smu/smu_7_1_3_sh_mask.h"
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 },
++ { CMD_DELAY_US, 0, 0, 0, 1, 0x0 },
++ { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++ { CMD_READMODIFYWRITE, 0xda2, 0x40, 0x6, 0, 0x0 },
++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++ { CMD_READMODIFYWRITE, 0xda2, 0x8, 0x3, 0, 0x0 },
++ { CMD_READMODIFYWRITE, 0xda2, 0x3fff00, 0x8, 0, 0x32 },
++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++ { CMD_READMODIFYWRITE, mmMPLL_FUNC_CNTL_2, MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK, MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT, 0, 0x0 },
++ { CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
++};
++
++static const struct baco_cmd_entry clk_req_b_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
++};
++
++int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ *cap = false;
++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++ return 0;
++
++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++ *cap = true;
++
++ return 0;
++}
++
++int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ reg = RREG32(mmBACO_CNTL);
++
++ if (reg & BACO_CNTL__BACO_MODE_MASK)
++ /* gfx has already entered BACO state */
++ *state = BACO_STATE_IN;
++ else
++ *state = BACO_STATE_OUT;
++ return 0;
++}
++
++int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++ enum BACO_STATE cur_state;
++
++ polaris_baco_get_state(hwmgr, &cur_state);
++
++ if (cur_state == state)
++ /* aisc already in the target state */
++ return 0;
++
++ if (state == BACO_STATE_IN) {
++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++ ARRAY_SIZE(enable_fb_req_rej_tbl));
++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++ baco_program_registers(hwmgr, turn_off_plls_tbl,
++ ARRAY_SIZE(turn_off_plls_tbl));
++ baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl));
++ if (baco_program_registers(hwmgr, enter_baco_tbl,
++ ARRAY_SIZE(enter_baco_tbl)))
++ return 0;
++
++ } else if (state == BACO_STATE_OUT) {
++ /* HW requires at least 20ms between regulator off and on */
++ msleep(20);
++ /* Execute Hardware BACO exit sequence */
++ if (baco_program_registers(hwmgr, exit_baco_tbl,
++ ARRAY_SIZE(exit_baco_tbl))) {
++ if (baco_program_registers(hwmgr, clean_baco_tbl,
++ ARRAY_SIZE(clean_baco_tbl)))
++ return 0;
++ }
++ }
++
++ return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+new file mode 100644
+index 000000000000..e48bfb1c5c6a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __POLARIS_BACO_H__
++#define __POLARIS_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch
new file mode 100644
index 00000000..0b557a14
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch
@@ -0,0 +1,80 @@
+From eadd75308b9e8442de6849d88575fa6788c3228b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 14 Feb 2019 16:53:42 -0500
+Subject: [PATCH 4159/4736] drm/amdgpu/powerplay: add support for BACO on VegaM
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for VegaM asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/hwmgr/polaris_baco.c | 42 +++++++++++++++++--
+ 1 file changed, 39 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+index d0c9de88f474..a9abe53df475 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+@@ -148,6 +148,36 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
+ };
+
++static const struct baco_cmd_entry use_bclk_tbl_vg[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =
++{
++ { CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 },
++ { CMD_DELAY_US, 0, 0, 0, 1, 0x0 },
++ { CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++ { CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++ { CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
++};
++
+ int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+@@ -194,9 +224,15 @@ int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
+ baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
+ ARRAY_SIZE(enable_fb_req_rej_tbl));
+- baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
+- baco_program_registers(hwmgr, turn_off_plls_tbl,
+- ARRAY_SIZE(turn_off_plls_tbl));
++ if (hwmgr->chip_id == CHIP_VEGAM) {
++ baco_program_registers(hwmgr, use_bclk_tbl_vg, ARRAY_SIZE(use_bclk_tbl_vg));
++ baco_program_registers(hwmgr, turn_off_plls_tbl_vg,
++ ARRAY_SIZE(turn_off_plls_tbl_vg));
++ } else {
++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++ baco_program_registers(hwmgr, turn_off_plls_tbl,
++ ARRAY_SIZE(turn_off_plls_tbl));
++ }
+ baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl));
+ if (baco_program_registers(hwmgr, enter_baco_tbl,
+ ARRAY_SIZE(enter_baco_tbl)))
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch
new file mode 100644
index 00000000..349ebad6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch
@@ -0,0 +1,309 @@
+From 7e1936b6ba966edb01b6826ce684c565411ee6bf Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:37:46 -0500
+Subject: [PATCH 4160/4736] drm/amdgpu/powerplay: add support for BACO on Fiji
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Fiji asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.c | 228 ++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.h | 32 +++
+ 3 files changed, 261 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index a1535e1430d5..bfd22d8b0aea 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ pp_overdriver.o smu_helper.o \
+ vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
+- vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o
++ vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o
+
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+new file mode 100644
+index 000000000000..ad01919ccb27
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+@@ -0,0 +1,228 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "fiji_baco.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "dce/dce_10_0_d.h"
++#include "dce/dce_10_0_sh_mask.h"
++
++#include "smu/smu_7_1_3_d.h"
++#include "smu/smu_7_1_3_sh_mask.h"
++
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry clk_req_b_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++ { CMD_WRITE, mmBIOS_SCRATCH_0, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_1, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_2, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_3, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_4, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_5, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_8, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_9, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_10, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_11, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_12, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_13, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_14, 0, 0, 0, 0 },
++ { CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 }
++};
++
++int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ *cap = false;
++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++ return 0;
++
++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++ *cap = true;
++
++ return 0;
++}
++
++int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ reg = RREG32(mmBACO_CNTL);
++
++ if (reg & BACO_CNTL__BACO_MODE_MASK)
++ /* gfx has already entered BACO state */
++ *state = BACO_STATE_IN;
++ else
++ *state = BACO_STATE_OUT;
++ return 0;
++}
++
++int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++ enum BACO_STATE cur_state;
++
++ fiji_baco_get_state(hwmgr, &cur_state);
++
++ if (cur_state == state)
++ /* aisc already in the target state */
++ return 0;
++
++ if (state == BACO_STATE_IN) {
++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++ ARRAY_SIZE(enable_fb_req_rej_tbl));
++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++ baco_program_registers(hwmgr, turn_off_plls_tbl,
++ ARRAY_SIZE(turn_off_plls_tbl));
++ baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl));
++ if (baco_program_registers(hwmgr, enter_baco_tbl,
++ ARRAY_SIZE(enter_baco_tbl)))
++ return 0;
++
++ } else if (state == BACO_STATE_OUT) {
++ /* HW requires at least 20ms between regulator off and on */
++ msleep(20);
++ /* Execute Hardware BACO exit sequence */
++ if (baco_program_registers(hwmgr, exit_baco_tbl,
++ ARRAY_SIZE(exit_baco_tbl))) {
++ if (baco_program_registers(hwmgr, clean_baco_tbl,
++ ARRAY_SIZE(clean_baco_tbl)))
++ return 0;
++ }
++ }
++
++ return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+new file mode 100644
+index 000000000000..2f7c8388667e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __FIJI_BACO_H__
++#define __FIJI_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch
new file mode 100644
index 00000000..362a646d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch
@@ -0,0 +1,309 @@
+From a835596fe3e90f66093459a5708c26b690d59e8d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:38:44 -0500
+Subject: [PATCH 4161/4736] drm/amdgpu/powerplay: add support for BACO on CI
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for CI asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 3 +-
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c | 227 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h | 32 +++
+ 3 files changed, 261 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index bfd22d8b0aea..5ad5893bdae1 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ pp_overdriver.o smu_helper.o \
+ vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
+- vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o
++ vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \
++ ci_baco.o
+
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+new file mode 100644
+index 000000000000..f1a8c9cc0d1f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+@@ -0,0 +1,227 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "ci_baco.h"
++
++#include "gmc/gmc_7_1_d.h"
++#include "gmc/gmc_7_1_sh_mask.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "dce/dce_8_0_d.h"
++#include "dce/dce_8_0_sh_mask.h"
++
++#include "smu/smu_7_0_1_d.h"
++#include "smu/smu_7_0_1_sh_mask.h"
++
++#include "gca/gfx_7_2_d.h"
++#include "gca/gfx_7_2_sh_mask.h"
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++ { CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++ { CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++ { CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++ { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++ { CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++ { CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmDISPPLL_BG_CNTL, DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK, DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_DC },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__OSC_EN_MASK, CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK, CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_RESET_MASK, PLL_CNTL__PLL_RESET__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_POWER_DOWN_MASK, PLL_CNTL__PLL_POWER_DOWN__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_BYPASS_CAL_MASK, PLL_CNTL__PLL_BYPASS_CAL__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 },
++ { CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 },
++ { CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 },
++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 },
++ { CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT, 0, 0x2 },
++ { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x2 },
++ { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x2 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++ { CMD_DELAY_MS, 0, 0, 0, 20, 0 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x20 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x10 },
++ { CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++ { CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++ { CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++ { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
++};
++
++int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ *cap = false;
++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++ return 0;
++
++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++ *cap = true;
++
++ return 0;
++}
++
++int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ reg = RREG32(mmBACO_CNTL);
++
++ if (reg & BACO_CNTL__BACO_MODE_MASK)
++ /* gfx has already entered BACO state */
++ *state = BACO_STATE_IN;
++ else
++ *state = BACO_STATE_OUT;
++ return 0;
++}
++
++int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++ enum BACO_STATE cur_state;
++
++ ci_baco_get_state(hwmgr, &cur_state);
++
++ if (cur_state == state)
++ /* aisc already in the target state */
++ return 0;
++
++ if (state == BACO_STATE_IN) {
++ baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++ baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++ ARRAY_SIZE(enable_fb_req_rej_tbl));
++ baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++ baco_program_registers(hwmgr, turn_off_plls_tbl,
++ ARRAY_SIZE(turn_off_plls_tbl));
++ if (baco_program_registers(hwmgr, enter_baco_tbl,
++ ARRAY_SIZE(enter_baco_tbl)))
++ return 0;
++
++ } else if (state == BACO_STATE_OUT) {
++ /* HW requires at least 20ms between regulator off and on */
++ msleep(20);
++ /* Execute Hardware BACO exit sequence */
++ if (baco_program_registers(hwmgr, exit_baco_tbl,
++ ARRAY_SIZE(exit_baco_tbl))) {
++ if (baco_program_registers(hwmgr, clean_baco_tbl,
++ ARRAY_SIZE(clean_baco_tbl)))
++ return 0;
++ }
++ }
++
++ return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+new file mode 100644
+index 000000000000..c9bedb51cb25
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __CI_BACO_H__
++#define __CI_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch
new file mode 100644
index 00000000..286aaa53
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch
@@ -0,0 +1,446 @@
+From 398407598af75bd60cc2a23431c992283eeff37e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:39:33 -0500
+Subject: [PATCH 4162/4736] drm/amdgpu/powerplay: split out common smu7 BACO
+ code
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Several of the BACO functions are common across smu7-based
+asics. Split the common code out.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c | 34 +------
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h | 5 +-
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.c | 34 +------
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.h | 5 +-
+ .../drm/amd/powerplay/hwmgr/polaris_baco.c | 34 +------
+ .../drm/amd/powerplay/hwmgr/polaris_baco.h | 5 +-
+ .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.c | 91 +++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.h | 32 +++++++
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c | 34 +------
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.h | 5 +-
+ 11 files changed, 132 insertions(+), 149 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index 5ad5893bdae1..2773966ae434 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -37,7 +37,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o \
+ vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \
+- ci_baco.o
++ ci_baco.o smu7_baco.o
+
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+index f1a8c9cc0d1f..3be40114e63d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
+ };
+
+-int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- *cap = false;
+- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+- return 0;
+-
+- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+- *cap = true;
+-
+- return 0;
+-}
+-
+-int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- reg = RREG32(mmBACO_CNTL);
+-
+- if (reg & BACO_CNTL__BACO_MODE_MASK)
+- /* gfx has already entered BACO state */
+- *state = BACO_STATE_IN;
+- else
+- *state = BACO_STATE_OUT;
+- return 0;
+-}
+-
+ int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ enum BACO_STATE cur_state;
+
+- ci_baco_get_state(hwmgr, &cur_state);
++ smu7_baco_get_state(hwmgr, &cur_state);
+
+ if (cur_state == state)
+ /* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+index c9bedb51cb25..17041f187020 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+@@ -22,11 +22,8 @@
+ */
+ #ifndef __CI_BACO_H__
+ #define __CI_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+
+-extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+index ad01919ccb27..c0368f2dfb21 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ { CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 }
+ };
+
+-int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- *cap = false;
+- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+- return 0;
+-
+- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+- *cap = true;
+-
+- return 0;
+-}
+-
+-int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- reg = RREG32(mmBACO_CNTL);
+-
+- if (reg & BACO_CNTL__BACO_MODE_MASK)
+- /* gfx has already entered BACO state */
+- *state = BACO_STATE_IN;
+- else
+- *state = BACO_STATE_OUT;
+- return 0;
+-}
+-
+ int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ enum BACO_STATE cur_state;
+
+- fiji_baco_get_state(hwmgr, &cur_state);
++ smu7_baco_get_state(hwmgr, &cur_state);
+
+ if (cur_state == state)
+ /* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+index 2f7c8388667e..47f402900bdb 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+@@ -22,11 +22,8 @@
+ */
+ #ifndef __FIJI_BACO_H__
+ #define __FIJI_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+
+-extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+index a9abe53df475..8f8e296f2fe9 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+@@ -178,43 +178,11 @@ static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =
+ { CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
+ };
+
+-int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- *cap = false;
+- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+- return 0;
+-
+- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+- *cap = true;
+-
+- return 0;
+-}
+-
+-int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- reg = RREG32(mmBACO_CNTL);
+-
+- if (reg & BACO_CNTL__BACO_MODE_MASK)
+- /* gfx has already entered BACO state */
+- *state = BACO_STATE_IN;
+- else
+- *state = BACO_STATE_OUT;
+- return 0;
+-}
+-
+ int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ enum BACO_STATE cur_state;
+
+- polaris_baco_get_state(hwmgr, &cur_state);
++ smu7_baco_get_state(hwmgr, &cur_state);
+
+ if (cur_state == state)
+ /* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+index e48bfb1c5c6a..87a5fa0a157a 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+@@ -22,11 +22,8 @@
+ */
+ #ifndef __POLARIS_BACO_H__
+ #define __POLARIS_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+
+-extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
+new file mode 100644
+index 000000000000..044cda005aed
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
+@@ -0,0 +1,91 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "smu7_baco.h"
++#include "tonga_baco.h"
++#include "fiji_baco.h"
++#include "polaris_baco.h"
++#include "ci_baco.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "smu/smu_7_1_2_d.h"
++#include "smu/smu_7_1_2_sh_mask.h"
++
++int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ *cap = false;
++ if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++ return 0;
++
++ reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++ if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++ *cap = true;
++
++ return 0;
++}
++
++int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++ uint32_t reg;
++
++ reg = RREG32(mmBACO_CNTL);
++
++ if (reg & BACO_CNTL__BACO_MODE_MASK)
++ /* gfx has already entered BACO state */
++ *state = BACO_STATE_IN;
++ else
++ *state = BACO_STATE_OUT;
++ return 0;
++}
++
++int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++
++ switch (adev->asic_type) {
++ case CHIP_TOPAZ:
++ case CHIP_TONGA:
++ return tonga_baco_set_state(hwmgr, state);
++ case CHIP_FIJI:
++ return fiji_baco_set_state(hwmgr, state);
++ case CHIP_POLARIS10:
++ case CHIP_POLARIS11:
++ case CHIP_POLARIS12:
++ case CHIP_VEGAM:
++ return polaris_baco_set_state(hwmgr, state);
++#ifdef CONFIG_DRM_AMDGPU_CIK
++ case CHIP_BONAIRE:
++ case CHIP_HAWAII:
++ return ci_baco_set_state(hwmgr, state);
++#endif
++ default:
++ return -EINVAL;
++ }
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
+new file mode 100644
+index 000000000000..be0d98abb536
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __SMU7_BACO_H__
++#define __SMU7_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+index 84b7217b7bda..ea743bea8e29 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+@@ -182,43 +182,11 @@ static const struct baco_cmd_entry clean_baco_tbl_iceland[] =
+ { CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
+ };
+
+-int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- *cap = false;
+- if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+- return 0;
+-
+- reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+- if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+- *cap = true;
+-
+- return 0;
+-}
+-
+-int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+- uint32_t reg;
+-
+- reg = RREG32(mmBACO_CNTL);
+-
+- if (reg & BACO_CNTL__BACO_MODE_MASK)
+- /* gfx has already entered BACO state */
+- *state = BACO_STATE_IN;
+- else
+- *state = BACO_STATE_OUT;
+- return 0;
+-}
+-
+ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ enum BACO_STATE cur_state;
+
+- tonga_baco_get_state(hwmgr, &cur_state);
++ smu7_baco_get_state(hwmgr, &cur_state);
+
+ if (cur_state == state)
+ /* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+index 21301b043255..5dc16cc8a295 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+@@ -22,11 +22,8 @@
+ */
+ #ifndef __TONGA_BACO_H__
+ #define __TONGA_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+
+-extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch
new file mode 100644
index 00000000..8bcd8982
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch
@@ -0,0 +1,43 @@
+From 822464648a32206c3ec2e1992a6d190a14234c85 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 18:17:24 -0500
+Subject: [PATCH 4163/4736] drm/amdgpu/powerplay: wire up BACO to powerplay API
+ for smu7
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Wire up the powerplay callbacks for for BACO for smu7 devices.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 897fd494fe33..80bfdf178892 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -47,6 +47,7 @@
+ #include "smu7_clockpowergating.h"
+ #include "processpptables.h"
+ #include "pp_thermal.h"
++#include "smu7_baco.h"
+
+ #include "ivsrcid/ivsrcid_vislands30.h"
+
+@@ -5142,6 +5143,9 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
+ .get_power_profile_mode = smu7_get_power_profile_mode,
+ .set_power_profile_mode = smu7_set_power_profile_mode,
+ .get_performance_level = smu7_get_performance_level,
++ .get_asic_baco_capability = smu7_baco_get_capability,
++ .get_asic_baco_state = smu7_baco_get_state,
++ .set_asic_baco_state = smu7_baco_set_state,
+ .power_off_asic = smu7_power_off_asic,
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch
new file mode 100644
index 00000000..15c281cd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch
@@ -0,0 +1,230 @@
+From 97b0504af3ca00ce13f45fbdfb17767ee4abc4c9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 11 Mar 2019 18:05:12 -0500
+Subject: [PATCH 4164/4736] drm/amdgpu: enable BACO reset for SMU7 based dGPUs
+ (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use BACO to reset the GPU if supported on SMU7 based
+dGPUs.
+
+v2: don't use baco on CI parts
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 48 ++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/cik.h | 3 ++
+ drivers/gpu/drm/amd/amdgpu/vi.c | 84 ++++++++++++++++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/vi.h | 3 ++
+ 4 files changed, 128 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index 7b63d7a8298a..e3c524c8926a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1269,15 +1269,15 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
+ }
+
+ /**
+- * cik_asic_reset - soft reset GPU
++ * cik_asic_pci_config_reset - soft reset GPU
+ *
+ * @adev: amdgpu_device pointer
+ *
+- * Look up which blocks are hung and attempt
+- * to reset them.
++ * Use PCI Config method to reset the GPU.
++ *
+ * Returns 0 for success.
+ */
+-static int cik_asic_reset(struct amdgpu_device *adev)
++static int cik_asic_pci_config_reset(struct amdgpu_device *adev)
+ {
+ int r;
+
+@@ -1293,7 +1293,45 @@ static int cik_asic_reset(struct amdgpu_device *adev)
+ static enum amd_reset_method
+ cik_asic_reset_method(struct amdgpu_device *adev)
+ {
+- return AMD_RESET_METHOD_LEGACY;
++ bool baco_reset;
++
++ switch (adev->asic_type) {
++ case CHIP_BONAIRE:
++ case CHIP_HAWAII:
++ /* disable baco reset until it works */
++ /* smu7_asic_get_baco_capability(adev, &baco_reset); */
++ baco_reset = false;
++ break;
++ default:
++ baco_reset = false;
++ break;
++ }
++
++ if (baco_reset)
++ return AMD_RESET_METHOD_BACO;
++ else
++ return AMD_RESET_METHOD_LEGACY;
++}
++
++/**
++ * cik_asic_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up which blocks are hung and attempt
++ * to reset them.
++ * Returns 0 for success.
++ */
++static int cik_asic_reset(struct amdgpu_device *adev)
++{
++ int r;
++
++ if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++ r = smu7_asic_baco_reset(adev);
++ else
++ r = cik_asic_pci_config_reset(adev);
++
++ return r;
+ }
+
+ static u32 cik_get_config_memsize(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
+index 54c625a2e570..9870bf27870e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.h
++++ b/drivers/gpu/drm/amd/amdgpu/cik.h
+@@ -31,4 +31,7 @@ void cik_srbm_select(struct amdgpu_device *adev,
+ int cik_set_ip_blocks(struct amdgpu_device *adev);
+
+ void legacy_doorbell_index_init(struct amdgpu_device *adev);
++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap);
++int smu7_asic_baco_reset(struct amdgpu_device *adev);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 56c882b3ea3c..34a466e785cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -687,16 +687,50 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
+ return -EINVAL;
+ }
+
++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
++{
++ void *pp_handle = adev->powerplay.pp_handle;
++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++ if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
++ *cap = false;
++ return -ENOENT;
++ }
++
++ return pp_funcs->get_asic_baco_capability(pp_handle, cap);
++}
++
++int smu7_asic_baco_reset(struct amdgpu_device *adev)
++{
++ void *pp_handle = adev->powerplay.pp_handle;
++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++ if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++ return -ENOENT;
++
++ /* enter BACO state */
++ if (pp_funcs->set_asic_baco_state(pp_handle, 1))
++ return -EIO;
++
++ /* exit BACO state */
++ if (pp_funcs->set_asic_baco_state(pp_handle, 0))
++ return -EIO;
++
++ dev_info(adev->dev, "GPU BACO reset\n");
++
++ return 0;
++}
++
+ /**
+- * vi_asic_reset - soft reset GPU
++ * vi_asic_pci_config_reset - soft reset GPU
+ *
+ * @adev: amdgpu_device pointer
+ *
+- * Look up which blocks are hung and attempt
+- * to reset them.
++ * Use PCI Config method to reset the GPU.
++ *
+ * Returns 0 for success.
+ */
+-static int vi_asic_reset(struct amdgpu_device *adev)
++static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
+ {
+ int r;
+
+@@ -712,7 +746,47 @@ static int vi_asic_reset(struct amdgpu_device *adev)
+ static enum amd_reset_method
+ vi_asic_reset_method(struct amdgpu_device *adev)
+ {
+- return AMD_RESET_METHOD_LEGACY;
++ bool baco_reset;
++
++ switch (adev->asic_type) {
++ case CHIP_FIJI:
++ case CHIP_TONGA:
++ case CHIP_POLARIS10:
++ case CHIP_POLARIS11:
++ case CHIP_POLARIS12:
++ case CHIP_TOPAZ:
++ smu7_asic_get_baco_capability(adev, &baco_reset);
++ break;
++ default:
++ baco_reset = false;
++ break;
++ }
++
++ if (baco_reset)
++ return AMD_RESET_METHOD_BACO;
++ else
++ return AMD_RESET_METHOD_LEGACY;
++}
++
++/**
++ * vi_asic_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up which blocks are hung and attempt
++ * to reset them.
++ * Returns 0 for success.
++ */
++static int vi_asic_reset(struct amdgpu_device *adev)
++{
++ int r;
++
++ if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++ r = smu7_asic_baco_reset(adev);
++ else
++ r = vi_asic_pci_config_reset(adev);
++
++ return r;
+ }
+
+ static u32 vi_get_config_memsize(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
+index 8de0772f986c..40d4174913a4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.h
++++ b/drivers/gpu/drm/amd/amdgpu/vi.h
+@@ -31,4 +31,7 @@ void vi_srbm_select(struct amdgpu_device *adev,
+ int vi_set_ip_blocks(struct amdgpu_device *adev);
+
+ void legacy_doorbell_index_init(struct amdgpu_device *adev);
++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap);
++int smu7_asic_baco_reset(struct amdgpu_device *adev);
++
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch
new file mode 100644
index 00000000..c292e9ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch
@@ -0,0 +1,41 @@
+From e1ba8d889f2a06ace9596ac989cd48618484bf9b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 9 Oct 2019 14:39:37 -0500
+Subject: [PATCH 4165/4736] drm/amdgpu: simplify ATPX detection
+
+Use the base class rather than the specific class and drop
+the second loop.
+
+Change-Id: Ic4d4dba633a655531c5bd6ec99f903a0805e7455
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 12 +-----------
+ 1 file changed, 1 insertion(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+index 354c8b6106dc..7bebe128dd7b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+@@ -614,17 +614,7 @@ static bool amdgpu_atpx_detect(void)
+ bool d3_supported = false;
+ struct pci_dev *parent_pdev;
+
+- while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
+- vga_count++;
+-
+- has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+-
+- parent_pdev = pci_upstream_bridge(pdev);
+- d3_supported |= parent_pdev && parent_pdev->bridge_d3;
+- amdgpu_atpx_get_quirks(pdev);
+- }
+-
+- while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
++ while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) {
+ vga_count++;
+
+ has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch
new file mode 100644
index 00000000..fe9f0230
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch
@@ -0,0 +1,34 @@
+From fea8cac04d037e0669ac0ac5fa54c1222cff8769 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Wed, 16 Oct 2019 16:20:38 +0800
+Subject: [PATCH 4166/4736] drm/amd/powerplay: bug fix for memory clock request
+ from display
+
+In some cases, display fixes memory clock frequency to a high value
+rather than the natural memory clock switching.
+When we comes back from s3 resume, the request from display is not reset,
+this causes the bug which makes the memory clock goes into a low value.
+Then due to the insuffcient memory clock, the screen flicks.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d0a25dd8fcfc..fb5a55091292 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1354,6 +1354,8 @@ static int smu_resume(void *handle)
+ if (smu->is_apu)
+ smu_set_gfx_cgpg(&adev->smu, true);
+
++ smu->disable_uclk_switch = 0;
++
+ mutex_unlock(&smu->mutex);
+
+ pr_info("SMU is resumed successfully!\n");
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch
new file mode 100644
index 00000000..57d925e9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch
@@ -0,0 +1,43 @@
+From d37f0200c8aa88982cb2358aac4684195d407585 Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Wed, 16 Oct 2019 18:04:02 +0800
+Subject: [PATCH 4167/4736] drm/amdgpu: No need to check gfxoff status after
+ enable gfxoff feature
+
+smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch.
+
+As to when GPU get into "GFXoff" will be up to drawing load.
+
+So we can not sure which state GPU should be in after enable gfxoff
+feature.
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index c9691d0fb523..cac4269cf1d1 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -244,15 +244,6 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ if (enable) {
+ ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
+
+- /* confirm gfx is back to "off" state, timeout is 5 seconds */
+- while (!(smu_v12_0_get_gfxoff_status(smu) == 0)) {
+- msleep(10);
+- timeout--;
+- if (timeout == 0) {
+- DRM_ERROR("enable gfxoff timeout and failed!\n");
+- break;
+- }
+- }
+ } else {
+ ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch
new file mode 100644
index 00000000..f41a5fc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch
@@ -0,0 +1,546 @@
+From 40d01f785cf532f60d467345b0f371059017537b Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Tue, 13 Aug 2019 09:24:10 -0400
+Subject: [PATCH 4168/4736] drm/amd/display: update register field access
+ mechanism
+
+1-add timeout length and multiplier fields to aux_control1 register
+2-update access mechanism from macro constructed name to uint32_t
+defined addresses.
+3-define registers and field per asic family
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 11 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 175 +++++++++++++++++-
+ .../amd/display/dc/dce100/dce100_resource.c | 12 +-
+ .../amd/display/dc/dce110/dce110_resource.c | 12 +-
+ .../amd/display/dc/dce112/dce112_resource.c | 12 +-
+ .../amd/display/dc/dce120/dce120_resource.c | 12 +-
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 12 +-
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 12 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 13 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 12 +-
+ 10 files changed, 271 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 16960ef29132..574447185f4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -39,6 +39,10 @@
+
+ #include "reg_helper.h"
+
++#undef FN
++#define FN(reg_name, field_name) \
++ aux110->shift->field_name, aux110->mask->field_name
++
+ #define FROM_AUX_ENGINE(ptr) \
+ container_of((ptr), struct aux_engine_dce110, base)
+
+@@ -411,11 +415,14 @@ void dce110_engine_destroy(struct dce_aux **engine)
+ *engine = NULL;
+
+ }
++
+ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ uint32_t timeout_period,
+- const struct dce110_aux_registers *regs)
++ const struct dce110_aux_registers *regs,
++ const struct dce110_aux_registers_mask *mask,
++ const struct dce110_aux_registers_shift *shift)
+ {
+ aux_engine110->base.ddc = NULL;
+ aux_engine110->base.ctx = ctx;
+@@ -425,6 +432,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine
+ aux_engine110->timeout_period = timeout_period;
+ aux_engine110->regs = regs;
+
++ aux_engine110->mask = mask;
++ aux_engine110->shift = shift;
+ return &aux_engine110->base;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index ed7fec8fe253..717378502e9d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -29,6 +29,7 @@
+ #include "i2caux_interface.h"
+ #include "inc/hw/aux_engine.h"
+
++
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define AUX_COMMON_REG_LIST0(id)\
+ SRI(AUX_CONTROL, DP_AUX, id), \
+@@ -36,6 +37,7 @@
+ SRI(AUX_SW_DATA, DP_AUX, id), \
+ SRI(AUX_SW_CONTROL, DP_AUX, id), \
+ SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
++ SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
+ SRI(AUX_SW_STATUS, DP_AUX, id)
+ #endif
+
+@@ -55,6 +57,7 @@ struct dce110_aux_registers {
+ uint32_t AUX_SW_DATA;
+ uint32_t AUX_SW_CONTROL;
+ uint32_t AUX_INTERRUPT_CONTROL;
++ uint32_t AUX_DPHY_RX_CONTROL1;
+ uint32_t AUX_SW_STATUS;
+ uint32_t AUXN_IMPCAL;
+ uint32_t AUXP_IMPCAL;
+@@ -62,6 +65,156 @@ struct dce110_aux_registers {
+ uint32_t AUX_RESET_MASK;
+ };
+
++#define DCE_AUX_REG_FIELD_LIST(type)\
++ type AUX_EN;\
++ type AUX_RESET;\
++ type AUX_RESET_DONE;\
++ type AUX_REG_RW_CNTL_STATUS;\
++ type AUX_SW_USE_AUX_REG_REQ;\
++ type AUX_SW_DONE_USING_AUX_REG;\
++ type AUX_SW_AUTOINCREMENT_DISABLE;\
++ type AUX_SW_DATA_RW;\
++ type AUX_SW_INDEX;\
++ type AUX_SW_GO;\
++ type AUX_SW_DATA;\
++ type AUX_SW_REPLY_BYTE_COUNT;\
++ type AUX_SW_DONE;\
++ type AUX_SW_DONE_ACK;\
++ type AUXN_IMPCAL_ENABLE;\
++ type AUXP_IMPCAL_ENABLE;\
++ type AUXN_IMPCAL_OVERRIDE_ENABLE;\
++ type AUXP_IMPCAL_OVERRIDE_ENABLE;\
++ type AUX_RX_TIMEOUT_LEN;\
++ type AUX_RX_TIMEOUT_LEN_MUL;\
++ type AUXN_CALOUT_ERROR_AK;\
++ type AUXP_CALOUT_ERROR_AK;\
++ type AUX_SW_START_DELAY;\
++ type AUX_SW_WR_BYTES
++
++#define DCE10_AUX_MASK_SH_LIST(mask_sh)\
++ AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
++ AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++ AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++ AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++ AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++ AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++ AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++ AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++#define DCE_AUX_MASK_SH_LIST(mask_sh)\
++ AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
++ AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
++ AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++ AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++ AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++ AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++ AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++ AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++ AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++ AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++ AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++ AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++#define DCE12_AUX_MASK_SH_LIST(mask_sh)\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++/* DCN10 MASK */
++#define DCN10_AUX_MASK_SH_LIST(mask_sh)\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++ AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++ AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++/* for all other DCN */
++#define DCN_AUX_MASK_SH_LIST(mask_sh)\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
++ AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
++
++#define AUX_SF(reg_name, field_name, post_fix)\
++ .field_name = reg_name ## __ ## field_name ## post_fix
++
+ enum { /* This is the timeout as defined in DP 1.2a,
+ * 2.3.4 "Detailed uPacket TX AUX CH State Description".
+ */
+@@ -97,17 +250,31 @@ struct dce_aux {
+ uint32_t max_defer_write_retry;
+
+ bool acquire_reset;
++ const struct dce_aux_funcs *funcs;
++};
++
++struct dce110_aux_registers_mask {
++ DCE_AUX_REG_FIELD_LIST(uint32_t);
+ };
+
++struct dce110_aux_registers_shift {
++ DCE_AUX_REG_FIELD_LIST(uint8_t);
++};
++
++
+ struct aux_engine_dce110 {
+ struct dce_aux base;
+ const struct dce110_aux_registers *regs;
++ const struct dce110_aux_registers_mask *mask;
++ const struct dce110_aux_registers_shift *shift;
+ struct {
+ uint32_t aux_control;
+ uint32_t aux_arb_control;
+ uint32_t aux_sw_data;
+ uint32_t aux_sw_control;
+ uint32_t aux_interrupt_control;
++ uint32_t aux_dphy_rx_control1;
++ uint32_t aux_dphy_rx_control0;
+ uint32_t aux_sw_status;
+ } addr;
+ uint32_t timeout_period;
+@@ -120,12 +287,14 @@ struct aux_engine_dce110_init_data {
+ const struct dce110_aux_registers *regs;
+ };
+
+-struct dce_aux *dce110_aux_engine_construct(
+- struct aux_engine_dce110 *aux_engine110,
++struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ uint32_t timeout_period,
+- const struct dce110_aux_registers *regs);
++ const struct dce110_aux_registers *regs,
++
++ const struct dce110_aux_registers_mask *mask,
++ const struct dce110_aux_registers_shift *shift);
+
+ void dce110_engine_destroy(struct dce_aux **engine);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 3614e516489f..fe1538ab76ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -534,6 +534,14 @@ static const struct dce_mem_input_mask mi_masks = {
+ .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCE10_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCE10_AUX_MASK_SH_LIST(_MASK)
++};
++
+ static struct mem_input *dce100_mem_input_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+@@ -643,7 +651,9 @@ struct dce_aux *dce100_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index a487b75d23b6..06ecdf044ddc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -273,6 +273,14 @@ static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCE_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCE_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define opp_regs(id)\
+ [id] = {\
+ OPP_DCE_110_REG_LIST(id),\
+@@ -690,7 +698,9 @@ struct dce_aux *dce110_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index ec67db9c86e8..8dc75f71240d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -170,6 +170,14 @@ static const struct dce_abm_mask abm_mask = {
+ ABM_MASK_SH_LIST_DCE110(_MASK)
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCE_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCE_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define ipp_regs(id)\
+ [id] = {\
+ IPP_DCE110_REG_LIST_DCE_BASE(id)\
+@@ -663,7 +671,9 @@ struct dce_aux *dce112_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index b5b9a74086a0..3aac593f9b2e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -291,6 +291,14 @@ static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCE12_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCE12_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define opp_regs(id)\
+ [id] = {\
+ OPP_DCE_120_REG_LIST(id),\
+@@ -433,7 +441,9 @@ struct dce_aux *dce120_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 8e2aa0abf87c..934d8deb95fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -286,6 +286,14 @@ static const struct dce_opp_mask opp_mask = {
+ OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCE10_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCE10_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define aux_engine_regs(id)\
+ [id] = {\
+ AUX_COMMON_REG_LIST(id), \
+@@ -520,7 +528,9 @@ struct dce_aux *dce80_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 4522097e8a26..82dbc00afe54 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -317,6 +317,14 @@ static const struct dcn10_link_enc_mask le_mask = {
+ LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCN10_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCN10_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define ipp_regs(id)\
+ [id] = {\
+ IPP_REG_LIST_DCN10(id),\
+@@ -662,7 +670,9 @@ struct dce_aux *dcn10_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 968dc5fe4f1b..f2db1fa2eba9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -732,6 +732,15 @@ static const struct dcn20_vmid_mask vmid_masks = {
+ DCN20_VMID_MASK_SH_LIST(_MASK)
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCN_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCN_AUX_MASK_SH_LIST(_MASK)
++};
++
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define dsc_regsDCN20(id)\
+ [id] = {\
+@@ -949,7 +958,9 @@ struct dce_aux *dcn20_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 2cc93e2e6ec0..dc5d28d002df 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -628,6 +628,14 @@ static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+ stream_enc_regs(4),
+ };
+
++static const struct dce110_aux_registers_shift aux_shift = {
++ DCN_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++ DCN_AUX_MASK_SH_LIST(_MASK)
++};
++
+ static const struct dcn10_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
+ };
+@@ -685,7 +693,9 @@ static struct dce_aux *dcn21_aux_engine_create(
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+- &aux_engine_regs[inst]);
++ &aux_engine_regs[inst],
++ &aux_mask,
++ &aux_shift);
+
+ return &aux_engine->base;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch
new file mode 100644
index 00000000..9f39709d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch
@@ -0,0 +1,467 @@
+From 7a69015f1ac7aad129d6750e20eb30493409e6ec Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Thu, 18 Jul 2019 15:58:25 -0400
+Subject: [PATCH 4169/4736] drm/amd/display: configurable aux timeout support
+
+[Description]
+1-add configurable timeout support to aux engine.
+2-add timeout support field to dc_caps
+3-add reg_key to override extended timeout support
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 ++++
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 73 ++++++++++++++++++-
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 16 +++-
+ .../amd/display/dc/dce100/dce100_resource.c | 5 +-
+ .../amd/display/dc/dce110/dce110_resource.c | 4 +-
+ .../amd/display/dc/dce112/dce112_resource.c | 5 +-
+ .../amd/display/dc/dce120/dce120_resource.c | 5 +-
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 4 +-
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 5 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +-
+ .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 3 +
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +
+ .../drm/amd/display/dc/inc/hw/aux_engine.h | 3 +
+ 15 files changed, 132 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 588a07b525a0..580594be1de5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -632,6 +632,20 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ return dce_aux_transfer_with_retries(ddc, payload);
+ }
+
++
++enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++ uint32_t timeout)
++{
++ enum dc_status status = DC_OK;
++ struct ddc *ddc_pin = ddc->ddc_pin;
++
++ if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout == NULL)
++ return DC_ERROR_UNEXPECTED;
++ if (!ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout))
++ status = DC_ERROR_UNEXPECTED;
++ return status;
++}
++
+ /*test only function*/
+ void dal_ddc_service_set_ddc_pin(
+ struct ddc_service *ddc_service,
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 41e366f59f10..5967106826ca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -111,6 +111,7 @@ struct dc_caps {
+ bool force_dp_tps4_for_cp2520;
+ bool disable_dp_clk_share;
+ bool psp_setup_panel_mode;
++ bool extended_aux_timeout_support;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hw_3d_lut;
+ #endif
+@@ -220,6 +221,7 @@ struct dc_config {
+ bool power_down_display_on_boot;
+ bool edp_not_connected;
+ bool forced_clocks;
++ bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well
+ bool multi_mon_pp_mclk_switch;
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 574447185f4a..a68edd0c2172 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -56,6 +56,14 @@ enum {
+ AUX_TIMED_OUT_RETRY_COUNTER = 2,
+ AUX_DEFER_RETRY_COUNTER = 6
+ };
++
++#define TIME_OUT_INCREMENT 1016
++#define TIME_OUT_MULTIPLIER_8 8
++#define TIME_OUT_MULTIPLIER_16 16
++#define TIME_OUT_MULTIPLIER_32 32
++#define TIME_OUT_MULTIPLIER_64 64
++#define MAX_TIMEOUT_LENGTH 127
++
+ static void release_engine(
+ struct dce_aux *engine)
+ {
+@@ -199,7 +207,7 @@ static void submit_channel_request(
+ REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
+
+ REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
+- 10, aux110->timeout_period/10);
++ 10, aux110->polling_timeout_period/10);
+
+ /* set the delay and the number of bytes to write */
+
+@@ -328,7 +336,7 @@ static enum aux_channel_operation_result get_channel_status(
+
+ /* poll to make sure that SW_DONE is asserted */
+ REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
+- 10, aux110->timeout_period/10);
++ 10, aux110->polling_timeout_period/10);
+
+ value = REG_READ(AUX_SW_STATUS);
+ /* in case HPD is LOW, exit AUX transaction */
+@@ -416,24 +424,81 @@ void dce110_engine_destroy(struct dce_aux **engine)
+
+ }
+
++static bool dce_aux_configure_timeout(struct ddc_service *ddc,
++ uint32_t timeout_in_us)
++{
++ uint32_t multiplier = 0;
++ uint32_t length = 0;
++ uint32_t timeout = 0;
++ struct ddc *ddc_pin = ddc->ddc_pin;
++ struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
++ struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
++
++ /* 1-Update polling timeout period */
++ aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER;
++
++ /* 2-Update aux timeout period length and multiplier */
++ if (timeout_in_us <= TIME_OUT_INCREMENT) {
++ multiplier = 0;
++ length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
++ if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
++ length++;
++ timeout = length * TIME_OUT_MULTIPLIER_8;
++ } else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) {
++ multiplier = 1;
++ length = timeout_in_us/TIME_OUT_MULTIPLIER_16;
++ if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0)
++ length++;
++ timeout = length * TIME_OUT_MULTIPLIER_16;
++ } else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) {
++ multiplier = 2;
++ length = timeout_in_us/TIME_OUT_MULTIPLIER_32;
++ if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0)
++ length++;
++ timeout = length * TIME_OUT_MULTIPLIER_32;
++ } else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) {
++ multiplier = 3;
++ length = timeout_in_us/TIME_OUT_MULTIPLIER_64;
++ if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0)
++ length++;
++ timeout = length * TIME_OUT_MULTIPLIER_64;
++ }
++
++ length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
++
++ REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier);
++
++ return true;
++}
++
++static struct dce_aux_funcs aux_functions = {
++ .configure_timeout = NULL,
++ .destroy = NULL,
++};
++
+ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ uint32_t timeout_period,
+ const struct dce110_aux_registers *regs,
+ const struct dce110_aux_registers_mask *mask,
+- const struct dce110_aux_registers_shift *shift)
++ const struct dce110_aux_registers_shift *shift,
++ bool is_ext_aux_timeout_configurable)
+ {
+ aux_engine110->base.ddc = NULL;
+ aux_engine110->base.ctx = ctx;
+ aux_engine110->base.delay = 0;
+ aux_engine110->base.max_defer_write_retry = 0;
+ aux_engine110->base.inst = inst;
+- aux_engine110->timeout_period = timeout_period;
++ aux_engine110->polling_timeout_period = timeout_period;
+ aux_engine110->regs = regs;
+
+ aux_engine110->mask = mask;
+ aux_engine110->shift = shift;
++ aux_engine110->base.funcs = &aux_functions;
++ if (is_ext_aux_timeout_configurable)
++ aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout;
++
+ return &aux_engine110->base;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index 717378502e9d..b4b2c79a8073 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -250,7 +250,7 @@ struct dce_aux {
+ uint32_t max_defer_write_retry;
+
+ bool acquire_reset;
+- const struct dce_aux_funcs *funcs;
++ struct dce_aux_funcs *funcs;
+ };
+
+ struct dce110_aux_registers_mask {
+@@ -277,7 +277,7 @@ struct aux_engine_dce110 {
+ uint32_t aux_dphy_rx_control0;
+ uint32_t aux_sw_status;
+ } addr;
+- uint32_t timeout_period;
++ uint32_t polling_timeout_period;
+ };
+
+ struct aux_engine_dce110_init_data {
+@@ -294,7 +294,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine
+ const struct dce110_aux_registers *regs,
+
+ const struct dce110_aux_registers_mask *mask,
+- const struct dce110_aux_registers_shift *shift);
++ const struct dce110_aux_registers_shift *shift,
++ bool is_ext_aux_timeout_configurable);
+
+ void dce110_engine_destroy(struct dce_aux **engine);
+
+@@ -308,4 +309,13 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
+
+ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ struct aux_payload *cmd);
++
++struct dce_aux_funcs {
++ bool (*configure_timeout)
++ (struct ddc_service *ddc,
++ uint32_t timeout);
++ void (*destroy)
++ (struct aux_engine **ptr);
++};
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index fe1538ab76ba..8ec9b4639fe7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -653,7 +653,8 @@ struct dce_aux *dce100_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -1039,6 +1040,8 @@ static bool construct(
+ dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
+ dc->caps.disable_dp_clk_share = true;
++ dc->caps.extended_aux_timeout_support = false;
++
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ pool->base.timing_generators[i] =
+ dce100_timing_generator_create(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 06ecdf044ddc..377fa9193ce1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -700,7 +700,8 @@ struct dce_aux *dce110_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -1336,6 +1337,7 @@ static bool construct(
+ dc->caps.i2c_speed_in_khz = 100;
+ dc->caps.max_cursor_size = 128;
+ dc->caps.is_apu = true;
++ dc->caps.extended_aux_timeout_support = false;
+
+ /*************************************************
+ * Create resources *
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 8dc75f71240d..5bde6ac2fa7e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -673,7 +673,8 @@ struct dce_aux *dce112_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -1206,7 +1207,7 @@ static bool construct(
+ dc->caps.i2c_speed_in_khz = 100;
+ dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
+-
++ dc->caps.extended_aux_timeout_support = false;
+
+ /*************************************************
+ * Create resources *
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 3aac593f9b2e..2dcc647ad27d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -443,7 +443,8 @@ struct dce_aux *dce120_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -1049,7 +1050,7 @@ static bool construct(
+ dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
+ dc->caps.psp_setup_panel_mode = true;
+-
++ dc->caps.extended_aux_timeout_support = true;
+ dc->debug = debug_defaults;
+
+ /*************************************************
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 934d8deb95fc..6a9efa3bb93e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -530,7 +530,8 @@ struct dce_aux *dce80_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -938,6 +939,7 @@ static bool dce80_construct(
+ dc->caps.i2c_speed_in_khz = 40;
+ dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
++ dc->caps.extended_aux_timeout_support = false;
+
+ /*************************************************
+ * Create resources *
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 82dbc00afe54..a38c83c6aa5c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -672,7 +672,8 @@ struct dce_aux *dcn10_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -1342,6 +1343,8 @@ static bool construct(
+ dc->caps.max_slave_planes = 1;
+ dc->caps.is_apu = true;
+ dc->caps.post_blend_color_processing = false;
++ dc->caps.extended_aux_timeout_support = false;
++
+ /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
+ dc->caps.force_dp_tps4_for_cp2520 = true;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f2db1fa2eba9..2796c84db740 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -960,7 +960,8 @@ struct dce_aux *dcn20_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -3372,6 +3373,7 @@ static bool construct(
+ dc->caps.post_blend_color_processing = true;
+ dc->caps.force_dp_tps4_for_cp2520 = true;
+ dc->caps.hw_3d_lut = true;
++ dc->caps.extended_aux_timeout_support = true;
+
+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
+ dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index dc5d28d002df..86005cb05c2a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -695,7 +695,8 @@ static struct dce_aux *dcn21_aux_engine_create(
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst],
+ &aux_mask,
+- &aux_shift);
++ &aux_shift,
++ ctx->dc->caps.extended_aux_timeout_support);
+
+ return &aux_engine->base;
+ }
+@@ -1539,6 +1540,7 @@ static bool construct(
+ dc->caps.max_slave_planes = 1;
+ dc->caps.post_blend_color_processing = true;
+ dc->caps.force_dp_tps4_for_cp2520 = true;
++ dc->caps.extended_aux_timeout_support = true;
+
+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+index 7d35d03a2d43..14716ba35662 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+@@ -105,6 +105,9 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
+ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ struct aux_payload *payload);
+
++enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++ uint32_t timeout);
++
+ void dal_ddc_service_write_scdc_data(
+ struct ddc_service *ddc_service,
+ uint32_t pix_clk,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 967706e7898e..045138dbdccb 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -28,6 +28,8 @@
+
+ #define LINK_TRAINING_ATTEMPTS 4
+ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
++#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 32000 /*us*/
++#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
+
+ struct dc_link;
+ struct dc_stream_state;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
+index e79cd4e92919..e77b3a76766d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
+@@ -140,6 +140,9 @@ struct write_command_context {
+
+
+ struct aux_engine_funcs {
++ bool (*configure_timeout)(
++ struct ddc_service *ddc,
++ uint32_t timeout);
+ void (*destroy)(
+ struct aux_engine **ptr);
+ bool (*acquire_engine)(
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch
new file mode 100644
index 00000000..51c374a0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch
@@ -0,0 +1,37 @@
+From 380cc83606e4cd2ca0b3b206955d7047d54ace0c Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Tue, 8 Oct 2019 17:35:48 -0400
+Subject: [PATCH 4170/4736] drm/amd/display: disable ext aux support for vega
+
+[Why]
+Earlier changes to support configurable aux timeout
+caused dc init failure on vega due to missing reg defs.
+Needs to be disabled until implemented for vega.
+
+[How]
+Set extended aux timeout cap for vega to false.
+
+fixes: drm/amd/display: configurable aux timeout support
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-By: abdoulaye berthe <abdoulaye.berthe@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 2dcc647ad27d..c982fd336cae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -1050,7 +1050,7 @@ static bool construct(
+ dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
+ dc->caps.psp_setup_panel_mode = true;
+- dc->caps.extended_aux_timeout_support = true;
++ dc->caps.extended_aux_timeout_support = false;
+ dc->debug = debug_defaults;
+
+ /*************************************************
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch
new file mode 100644
index 00000000..4b56b5b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch
@@ -0,0 +1,63 @@
+From 77b8a13374bac1feff732bbbce9233abd5f65aef Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:50:15 -0400
+Subject: [PATCH 4171/4736] drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+index be4249adb356..eddf83ec1c39 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+@@ -9859,6 +9859,8 @@
+ #define mmDP0_DP_STEER_FIFO_BASE_IDX 2
+ #define mmDP0_DP_MSA_MISC 0x210e
+ #define mmDP0_DP_MSA_MISC_BASE_IDX 2
++#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
++#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP0_DP_VID_TIMING 0x2110
+ #define mmDP0_DP_VID_TIMING_BASE_IDX 2
+ #define mmDP0_DP_VID_N 0x2111
+@@ -10187,6 +10189,8 @@
+ #define mmDP1_DP_STEER_FIFO_BASE_IDX 2
+ #define mmDP1_DP_MSA_MISC 0x220e
+ #define mmDP1_DP_MSA_MISC_BASE_IDX 2
++#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
++#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP1_DP_VID_TIMING 0x2210
+ #define mmDP1_DP_VID_TIMING_BASE_IDX 2
+ #define mmDP1_DP_VID_N 0x2211
+@@ -10515,6 +10519,8 @@
+ #define mmDP2_DP_STEER_FIFO_BASE_IDX 2
+ #define mmDP2_DP_MSA_MISC 0x230e
+ #define mmDP2_DP_MSA_MISC_BASE_IDX 2
++#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
++#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP2_DP_VID_TIMING 0x2310
+ #define mmDP2_DP_VID_TIMING_BASE_IDX 2
+ #define mmDP2_DP_VID_N 0x2311
+@@ -10843,6 +10849,8 @@
+ #define mmDP3_DP_STEER_FIFO_BASE_IDX 2
+ #define mmDP3_DP_MSA_MISC 0x240e
+ #define mmDP3_DP_MSA_MISC_BASE_IDX 2
++#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
++#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP3_DP_VID_TIMING 0x2410
+ #define mmDP3_DP_VID_TIMING_BASE_IDX 2
+ #define mmDP3_DP_VID_N 0x2411
+@@ -11171,6 +11179,8 @@
+ #define mmDP4_DP_STEER_FIFO_BASE_IDX 2
+ #define mmDP4_DP_MSA_MISC 0x250e
+ #define mmDP4_DP_MSA_MISC_BASE_IDX 2
++#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
++#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP4_DP_VID_TIMING 0x2510
+ #define mmDP4_DP_VID_TIMING_BASE_IDX 2
+ #define mmDP4_DP_VID_N 0x2511
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch
new file mode 100644
index 00000000..8374bd65
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch
@@ -0,0 +1,64 @@
+From 0fcb1884fb7b2db1e44bbdca280bce9284e3b902 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:51:20 -0400
+Subject: [PATCH 4172/4736] drm/amd/display: Add DCN_BASE regs
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/include/renoir_ip_offset.h | 34 +++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+index 094648cac392..07633e22e99a 100644
+--- a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
++++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+@@ -169,6 +169,11 @@ static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
++ { { 0, 0, 0, 0, 0 } },
++ { { 0, 0, 0, 0, 0 } },
++ { { 0, 0, 0, 0, 0 } },
++ { { 0, 0, 0, 0, 0 } } } };
+ static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+@@ -1361,4 +1366,33 @@ static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x0240300
+ #define UVD0_BASE__INST6_SEG3 0
+ #define UVD0_BASE__INST6_SEG4 0
+
++#define DCN_BASE__INST0_SEG0 0x00000012
++#define DCN_BASE__INST0_SEG1 0x000000C0
++#define DCN_BASE__INST0_SEG2 0x000034C0
++#define DCN_BASE__INST0_SEG3 0
++#define DCN_BASE__INST0_SEG4 0
++
++#define DCN_BASE__INST1_SEG0 0
++#define DCN_BASE__INST1_SEG1 0
++#define DCN_BASE__INST1_SEG2 0
++#define DCN_BASE__INST1_SEG3 0
++#define DCN_BASE__INST1_SEG4 0
++
++#define DCN_BASE__INST2_SEG0 0
++#define DCN_BASE__INST2_SEG1 0
++#define DCN_BASE__INST2_SEG2 0
++#define DCN_BASE__INST2_SEG3 0
++#define DCN_BASE__INST2_SEG4 0
++
++#define DCN_BASE__INST3_SEG0 0
++#define DCN_BASE__INST3_SEG1 0
++#define DCN_BASE__INST3_SEG2 0
++#define DCN_BASE__INST3_SEG3 0
++#define DCN_BASE__INST3_SEG4 0
++
++#define DCN_BASE__INST4_SEG0 0
++#define DCN_BASE__INST4_SEG1 0
++#define DCN_BASE__INST4_SEG2 0
++#define DCN_BASE__INST4_SEG3 0
++#define DCN_BASE__INST4_SEG4 0
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch
new file mode 100644
index 00000000..8f133525
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch
@@ -0,0 +1,449 @@
+From 8e48ee9e07fb0aa2b88f1e157660f182afafd7cc Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:54:56 -0400
+Subject: [PATCH 4173/4736] drm/amd/display: Add renoir hw_seq
+
+This change adds renoir hw_seq, needed to do renoir
+specific hw programing
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 1 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 122 ++++++++++++++++++
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.h | 33 +++++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 118 +++++++++++++----
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +
+ 7 files changed, 255 insertions(+), 28 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index ac04d77058f0..32d145a0d6fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -679,6 +679,7 @@ struct dce_hwseq_registers {
+ HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
++ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \
+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 3b55716bf63b..7c02f646feed 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -669,6 +669,10 @@ static void dcn10_bios_golden_init(struct dc *dc)
+ int i;
+ bool allow_self_fresh_force_enable = true;
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++ if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
++ return;
++#endif
+ if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
+ allow_self_fresh_force_enable =
+ dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index b2b39090fb57..5b8f42ae2334 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN21.
+
+-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
++DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
+
+ CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+new file mode 100644
+index 000000000000..b25215cadf85
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+@@ -0,0 +1,122 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dm_services.h"
++#include "dm_helpers.h"
++#include "core_types.h"
++#include "resource.h"
++#include "dce/dce_hwseq.h"
++#include "dcn20/dcn20_hwseq.h"
++#include "vmid.h"
++#include "reg_helper.h"
++#include "hw/clk_mgr.h"
++
++
++#define DC_LOGGER_INIT(logger)
++
++#define CTX \
++ hws->ctx
++#define REG(reg)\
++ hws->regs->reg
++
++#undef FN
++#define FN(reg_name, field_name) \
++ hws->shifts->field_name, hws->masks->field_name
++
++/* Temporary read settings, future will get values from kmd directly */
++static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config,
++ struct dce_hwseq *hws)
++{
++ uint32_t page_table_base_hi;
++ uint32_t page_table_base_lo;
++
++ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
++ PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi);
++ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
++ PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo);
++
++ config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo;
++
++}
++
++static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
++{
++ struct dcn_hubbub_phys_addr_config config;
++
++ config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
++ config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
++ config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
++ config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
++ config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
++ config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
++ config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
++ config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
++ config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
++
++ mmhub_update_page_table_config(&config, hws);
++
++ return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
++}
++
++// work around for Renoir s0i3, if register is programmed, bypass golden init.
++
++static bool dcn21_s0i3_golden_init_wa(struct dc *dc)
++{
++ struct dce_hwseq *hws = dc->hwseq;
++ uint32_t value = 0;
++
++ value = REG_READ(MICROSECOND_TIME_BASE_DIV);
++
++ return value != 0x00120464;
++}
++
++void dcn21_exit_optimized_pwr_state(
++ const struct dc *dc,
++ struct dc_state *context)
++{
++ dc->clk_mgr->funcs->update_clocks(
++ dc->clk_mgr,
++ context,
++ false);
++}
++
++void dcn21_optimize_pwr_state(
++ const struct dc *dc,
++ struct dc_state *context)
++{
++ dc->clk_mgr->funcs->update_clocks(
++ dc->clk_mgr,
++ context,
++ true);
++}
++
++void dcn21_hw_sequencer_construct(struct dc *dc)
++{
++ dcn20_hw_sequencer_construct(dc);
++ dc->hwss.init_sys_ctx = dcn21_init_sys_ctx;
++ dc->hwss.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa;
++ dc->hwss.optimize_pwr_state = dcn21_optimize_pwr_state;
++ dc->hwss.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+new file mode 100644
+index 000000000000..be67b62e6fb1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+@@ -0,0 +1,33 @@
++/*
++* Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_HWSS_DCN21_H__
++#define __DC_HWSS_DCN21_H__
++
++struct dc;
++
++void dcn21_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_HWSS_DCN21_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 86005cb05c2a..1bac7eca5963 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -23,8 +23,6 @@
+ *
+ */
+
+-#include <linux/slab.h>
+-
+ #include "dm_services.h"
+ #include "dc.h"
+
+@@ -42,7 +40,7 @@
+ #include "irq/dcn21/irq_service_dcn21.h"
+ #include "dcn20/dcn20_dpp.h"
+ #include "dcn20/dcn20_optc.h"
+-#include "dcn20/dcn20_hwseq.h"
++#include "dcn21/dcn21_hwseq.h"
+ #include "dce110/dce110_hw_sequencer.h"
+ #include "dcn20/dcn20_opp.h"
+ #include "dcn20/dcn20_dsc.h"
+@@ -350,6 +348,30 @@ static const struct bios_registers bios_regs = {
+ NBIO_SR(BIOS_SCRATCH_6)
+ };
+
++static const struct dce_dmcu_registers dmcu_regs = {
++ DMCU_DCN10_REG_LIST()
++};
++
++static const struct dce_dmcu_shift dmcu_shift = {
++ DMCU_MASK_SH_LIST_DCN10(__SHIFT)
++};
++
++static const struct dce_dmcu_mask dmcu_mask = {
++ DMCU_MASK_SH_LIST_DCN10(_MASK)
++};
++
++static const struct dce_abm_registers abm_regs = {
++ ABM_DCN20_REG_LIST()
++};
++
++static const struct dce_abm_shift abm_shift = {
++ ABM_MASK_SH_LIST_DCN20(__SHIFT)
++};
++
++static const struct dce_abm_mask abm_mask = {
++ ABM_MASK_SH_LIST_DCN20(_MASK)
++};
++
+ #ifdef CONFIG_DRM_AMD_DC_DMUB
+ static const struct dcn21_dmcub_registers dmcub_regs = {
+ DMCUB_REG_LIST_DCN()
+@@ -1491,6 +1513,19 @@ static struct link_encoder *dcn21_link_encoder_create(
+ return &enc21->enc10.base;
+ }
+
++#define CTX ctx
++
++#define REG(reg_name) \
++ (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
++
++static uint32_t read_pipe_fuses(struct dc_context *ctx)
++{
++ uint32_t value = REG_READ(CC_DC_PIPE_DIS);
++ /* RV1 support max 4 pipes */
++ value = value & 0xf;
++ return value;
++}
++
+ static struct resource_funcs dcn21_res_pool_funcs = {
+ .destroy = dcn21_destroy_resource_pool,
+ .link_enc_create = dcn20_link_encoder_create,
+@@ -1510,9 +1545,10 @@ static bool construct(
+ struct dc *dc,
+ struct dcn21_resource_pool *pool)
+ {
+- int i;
++ int i, j;
+ struct dc_context *ctx = dc->ctx;
+ struct irq_service_init_data init_data;
++ uint32_t pipe_fuses = read_pipe_fuses(ctx);
+
+ ctx->dc_bios->regs = &bios_regs;
+
+@@ -1530,7 +1566,9 @@ static bool construct(
+ *************************************************/
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+
+- pool->base.pipe_count = 4;
++ /* max pipe num for ASIC before check pipe fuses */
++ pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
++
+ dc->caps.max_downscale_ratio = 200;
+ dc->caps.i2c_speed_in_khz = 100;
+ dc->caps.max_cursor_size = 256;
+@@ -1590,6 +1628,26 @@ static bool construct(
+ goto create_fail;
+ }
+
++ pool->base.dmcu = dcn20_dmcu_create(ctx,
++ &dmcu_regs,
++ &dmcu_shift,
++ &dmcu_mask);
++ if (pool->base.dmcu == NULL) {
++ dm_error("DC: failed to create dmcu!\n");
++ BREAK_TO_DEBUGGER();
++ goto create_fail;
++ }
++
++ pool->base.abm = dce_abm_create(ctx,
++ &abm_regs,
++ &abm_shift,
++ &abm_mask);
++ if (pool->base.abm == NULL) {
++ dm_error("DC: failed to create abm!\n");
++ BREAK_TO_DEBUGGER();
++ goto create_fail;
++ }
++
+ #ifdef CONFIG_DRM_AMD_DC_DMUB
+ pool->base.dmcub = dcn21_dmcub_create(ctx,
+ &dmcub_regs,
+@@ -1611,8 +1669,15 @@ static bool construct(
+ if (!pool->base.irqs)
+ goto create_fail;
+
++ j = 0;
+ /* mem input -> ipp -> dpp -> opp -> TG */
+ for (i = 0; i < pool->base.pipe_count; i++) {
++ /* if pipe is disabled, skip instance of HW pipe,
++ * i.e, skip ASIC register instance
++ */
++ if ((pipe_fuses & (1 << i)) != 0)
++ continue;
++
+ pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
+ if (pool->base.hubps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+@@ -1636,6 +1701,23 @@ static bool construct(
+ "DC: failed to create dpps!\n");
+ goto create_fail;
+ }
++
++ pool->base.opps[i] = dcn21_opp_create(ctx, i);
++ if (pool->base.opps[i] == NULL) {
++ BREAK_TO_DEBUGGER();
++ dm_error(
++ "DC: failed to create output pixel processor!\n");
++ goto create_fail;
++ }
++
++ pool->base.timing_generators[i] = dcn21_timing_generator_create(
++ ctx, i);
++ if (pool->base.timing_generators[i] == NULL) {
++ BREAK_TO_DEBUGGER();
++ dm_error("DC: failed to create tg!\n");
++ goto create_fail;
++ }
++ j++;
+ }
+
+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+@@ -1656,27 +1738,9 @@ static bool construct(
+ pool->base.sw_i2cs[i] = NULL;
+ }
+
+- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+- pool->base.opps[i] = dcn21_opp_create(ctx, i);
+- if (pool->base.opps[i] == NULL) {
+- BREAK_TO_DEBUGGER();
+- dm_error(
+- "DC: failed to create output pixel processor!\n");
+- goto create_fail;
+- }
+- }
+-
+- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+- pool->base.timing_generators[i] = dcn21_timing_generator_create(
+- ctx, i);
+- if (pool->base.timing_generators[i] == NULL) {
+- BREAK_TO_DEBUGGER();
+- dm_error("DC: failed to create tg!\n");
+- goto create_fail;
+- }
+- }
+-
+- pool->base.timing_generator_count = i;
++ pool->base.timing_generator_count = j;
++ pool->base.pipe_count = j;
++ pool->base.mpcc_count = j;
+
+ pool->base.mpc = dcn21_mpc_create(ctx);
+ if (pool->base.mpc == NULL) {
+@@ -1719,7 +1783,7 @@ static bool construct(
+ &res_create_funcs : &res_create_maximus_funcs)))
+ goto create_fail;
+
+- dcn20_hw_sequencer_construct(dc);
++ dcn21_hw_sequencer_construct(dc);
+
+ dc->caps.max_planes = pool->base.pipe_count;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index e775d7aa062f..d39c1e11def5 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -349,6 +349,9 @@ struct hw_sequencer_funcs {
+ enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg);
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++ bool (*s0i3_golden_init_wa)(struct dc *dc);
++#endif
+ };
+
+ void color_space_to_black_color(
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch
new file mode 100644
index 00000000..69b71fce
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch
@@ -0,0 +1,668 @@
+From eedab588549241d11646033a4667dd8851e5a97f Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:55:12 -0400
+Subject: [PATCH 4174/4736] drm/amd/display: create dcn21_link_encoder files
+
+[Why]
+DCN20 and DCN21 have different phy programming sequences.
+
+[How]
+Create a separate dcn21_link_encoder for Renoir
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h | 35 +-
+ .../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 +
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +-
+ .../amd/display/dc/dcn21/dcn21_link_encoder.c | 379 ++++++++++++++++++
+ .../amd/display/dc/dcn21/dcn21_link_encoder.h | 51 +++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 85 +++-
+ 6 files changed, 555 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 0c12395cfa36..239a6c90ffb9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -250,6 +250,10 @@ struct dcn10_link_enc_registers {
+ type RDPCS_EXT_REFCLK_EN;\
+ type RDPCS_TX_FIFO_EN;\
+ type UNIPHY_LINK_ENABLE;\
++ type UNIPHY_CHANNEL0_XBAR_SOURCE;\
++ type UNIPHY_CHANNEL1_XBAR_SOURCE;\
++ type UNIPHY_CHANNEL2_XBAR_SOURCE;\
++ type UNIPHY_CHANNEL3_XBAR_SOURCE;\
+ type UNIPHY_CHANNEL0_INVERT;\
+ type UNIPHY_CHANNEL1_INVERT;\
+ type UNIPHY_CHANNEL2_INVERT;\
+@@ -342,12 +346,41 @@ struct dcn10_link_enc_registers {
+ type RDPCS_PHY_DPALT_DISABLE_ACK;\
+ type RDPCS_PHY_DP_MPLLB_V2I;\
+ type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
++ type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
++ type RDPCS_PHY_RX_VREF_CTRL;\
+ type RDPCS_PHY_DP_MPLLB_CP_INT;\
+ type RDPCS_PHY_DP_MPLLB_CP_PROP;\
+ type RDPCS_PHY_RX_REF_LD_VAL;\
+ type RDPCS_PHY_RX_VCO_LD_VAL;\
+ type DPCSTX_DEBUG_CONFIG; \
+- type RDPCSTX_DEBUG_CONFIG
++ type RDPCSTX_DEBUG_CONFIG; \
++ type RDPCS_PHY_DP_TX0_EQ_MAIN;\
++ type RDPCS_PHY_DP_TX0_EQ_PRE;\
++ type RDPCS_PHY_DP_TX0_EQ_POST;\
++ type RDPCS_PHY_DP_TX1_EQ_MAIN;\
++ type RDPCS_PHY_DP_TX1_EQ_PRE;\
++ type RDPCS_PHY_DP_TX1_EQ_POST;\
++ type RDPCS_PHY_DP_TX2_EQ_MAIN;\
++ type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
++ type RDPCS_PHY_DP_TX2_EQ_PRE;\
++ type RDPCS_PHY_DP_TX2_EQ_POST;\
++ type RDPCS_PHY_DP_TX3_EQ_MAIN;\
++ type RDPCS_PHY_DCO_RANGE;\
++ type RDPCS_PHY_DCO_FINETUNE;\
++ type RDPCS_PHY_DP_TX3_EQ_PRE;\
++ type RDPCS_PHY_DP_TX3_EQ_POST;\
++ type RDPCS_PHY_SUP_PRE_HP;\
++ type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
++ type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
++ type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
++ type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
++ type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
++ type UNIPHYA_SOFT_RESET;\
++ type UNIPHYB_SOFT_RESET;\
++ type UNIPHYC_SOFT_RESET;\
++ type UNIPHYD_SOFT_RESET;\
++ type UNIPHYE_SOFT_RESET;\
++ type UNIPHYF_SOFT_RESET
+
+ #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
+ type DIG_LANE0EN;\
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+index 3736b5548a25..0c98a0bbbd14 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+@@ -91,6 +91,13 @@ struct mpll_cfg {
+ uint32_t ref_range;
+ uint32_t ref_clk;
+ bool hdmimode_enable;
++ bool sup_pre_hp;
++ bool dp_tx0_vergdrv_byp;
++ bool dp_tx1_vergdrv_byp;
++ bool dp_tx2_vergdrv_byp;
++ bool dp_tx3_vergdrv_byp;
++
++
+ };
+
+ struct dpcssys_phy_seq_cfg {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 5b8f42ae2334..b7a9285348fb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN21.
+
+-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
++DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+
+ CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+new file mode 100644
+index 000000000000..526865c43b48
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+@@ -0,0 +1,379 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "reg_helper.h"
++
++#include <linux/delay.h>
++#include "core_types.h"
++#include "link_encoder.h"
++#include "dcn21_link_encoder.h"
++#include "stream_encoder.h"
++
++#include "i2caux_interface.h"
++#include "dc_bios_types.h"
++
++#include "gpio_service_interface.h"
++
++#define CTX \
++ enc10->base.ctx
++#define DC_LOGGER \
++ enc10->base.ctx->logger
++
++#define REG(reg)\
++ (enc10->link_regs->reg)
++
++#undef FN
++#define FN(reg_name, field_name) \
++ enc10->link_shift->field_name, enc10->link_mask->field_name
++
++#define IND_REG(index) \
++ (enc10->link_regs->index)
++
++static struct mpll_cfg dcn21_mpll_cfg_ref[] = {
++ // RBR
++ {
++ .hdmimode_enable = 0,
++ .ref_range = 1,
++ .ref_clk_mpllb_div = 1,
++ .mpllb_ssc_en = 1,
++ .mpllb_div5_clk_en = 1,
++ .mpllb_multiplier = 238,
++ .mpllb_fracn_en = 0,
++ .mpllb_fracn_quot = 0,
++ .mpllb_fracn_rem = 0,
++ .mpllb_fracn_den = 1,
++ .mpllb_ssc_up_spread = 0,
++ .mpllb_ssc_peak = 44237,
++ .mpllb_ssc_stepsize = 59454,
++ .mpllb_div_clk_en = 0,
++ .mpllb_div_multiplier = 0,
++ .mpllb_hdmi_div = 0,
++ .mpllb_tx_clk_div = 2,
++ .tx_vboost_lvl = 5,
++ .mpllb_pmix_en = 1,
++ .mpllb_word_div2_en = 0,
++ .mpllb_ana_v2i = 2,
++ .mpllb_ana_freq_vco = 2,
++ .mpllb_ana_cp_int = 9,
++ .mpllb_ana_cp_prop = 15,
++ .hdmi_pixel_clk_div = 0,
++ },
++ // HBR
++ {
++ .hdmimode_enable = 0,
++ .ref_range = 1,
++ .ref_clk_mpllb_div = 1,
++ .mpllb_ssc_en = 1,
++ .mpllb_div5_clk_en = 1,
++ .mpllb_multiplier = 192,
++ .mpllb_fracn_en = 1,
++ .mpllb_fracn_quot = 32768,
++ .mpllb_fracn_rem = 0,
++ .mpllb_fracn_den = 1,
++ .mpllb_ssc_up_spread = 0,
++ .mpllb_ssc_peak = 36864,
++ .mpllb_ssc_stepsize = 49545,
++ .mpllb_div_clk_en = 0,
++ .mpllb_div_multiplier = 0,
++ .mpllb_hdmi_div = 0,
++ .mpllb_tx_clk_div = 1,
++ .tx_vboost_lvl = 5,
++ .mpllb_pmix_en = 1,
++ .mpllb_word_div2_en = 0,
++ .mpllb_ana_v2i = 2,
++ .mpllb_ana_freq_vco = 3,
++ .mpllb_ana_cp_int = 9,
++ .mpllb_ana_cp_prop = 15,
++ .hdmi_pixel_clk_div = 0,
++ },
++ //HBR2
++ {
++ .hdmimode_enable = 0,
++ .ref_range = 1,
++ .ref_clk_mpllb_div = 1,
++ .mpllb_ssc_en = 1,
++ .mpllb_div5_clk_en = 1,
++ .mpllb_multiplier = 192,
++ .mpllb_fracn_en = 1,
++ .mpllb_fracn_quot = 32768,
++ .mpllb_fracn_rem = 0,
++ .mpllb_fracn_den = 1,
++ .mpllb_ssc_up_spread = 0,
++ .mpllb_ssc_peak = 36864,
++ .mpllb_ssc_stepsize = 49545,
++ .mpllb_div_clk_en = 0,
++ .mpllb_div_multiplier = 0,
++ .mpllb_hdmi_div = 0,
++ .mpllb_tx_clk_div = 0,
++ .tx_vboost_lvl = 5,
++ .mpllb_pmix_en = 1,
++ .mpllb_word_div2_en = 0,
++ .mpllb_ana_v2i = 2,
++ .mpllb_ana_freq_vco = 3,
++ .mpllb_ana_cp_int = 9,
++ .mpllb_ana_cp_prop = 15,
++ .hdmi_pixel_clk_div = 0,
++ },
++ //HBR3
++ {
++ .hdmimode_enable = 0,
++ .ref_range = 1,
++ .ref_clk_mpllb_div = 1,
++ .mpllb_ssc_en = 1,
++ .mpllb_div5_clk_en = 1,
++ .mpllb_multiplier = 304,
++ .mpllb_fracn_en = 1,
++ .mpllb_fracn_quot = 49152,
++ .mpllb_fracn_rem = 0,
++ .mpllb_fracn_den = 1,
++ .mpllb_ssc_up_spread = 0,
++ .mpllb_ssc_peak = 55296,
++ .mpllb_ssc_stepsize = 74318,
++ .mpllb_div_clk_en = 0,
++ .mpllb_div_multiplier = 0,
++ .mpllb_hdmi_div = 0,
++ .mpllb_tx_clk_div = 0,
++ .tx_vboost_lvl = 5,
++ .mpllb_pmix_en = 1,
++ .mpllb_word_div2_en = 0,
++ .mpllb_ana_v2i = 2,
++ .mpllb_ana_freq_vco = 1,
++ .mpllb_ana_cp_int = 7,
++ .mpllb_ana_cp_prop = 16,
++ .hdmi_pixel_clk_div = 0,
++ },
++};
++
++
++static bool update_cfg_data(
++ struct dcn10_link_encoder *enc10,
++ const struct dc_link_settings *link_settings,
++ struct dpcssys_phy_seq_cfg *cfg)
++{
++ int i;
++
++ cfg->load_sram_fw = false;
++ cfg->use_calibration_setting = true;
++
++ //TODO: need to implement a proper lane mapping for Renoir.
++ for (i = 0; i < 4; i++)
++ cfg->lane_en[i] = true;
++
++ switch (link_settings->link_rate) {
++ case LINK_RATE_LOW:
++ cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];
++ break;
++ case LINK_RATE_HIGH:
++ cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];
++ break;
++ case LINK_RATE_HIGH2:
++ cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];
++ break;
++ case LINK_RATE_HIGH3:
++ cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];
++ break;
++ default:
++ DC_LOG_ERROR("%s: No supported link rate found %X!\n",
++ __func__, link_settings->link_rate);
++ return false;
++ }
++
++ return true;
++}
++
++void dcn21_link_encoder_enable_dp_output(
++ struct link_encoder *enc,
++ const struct dc_link_settings *link_settings,
++ enum clock_source_id clock_source)
++{
++ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++ struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
++ struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg;
++
++ if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
++ dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
++ return;
++ }
++
++ if (!update_cfg_data(enc10, link_settings, cfg))
++ return;
++
++ enc1_configure_encoder(enc10, link_settings);
++
++ dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
++
++}
++
++void dcn21_link_encoder_disable_output(
++ struct link_encoder *enc,
++ enum signal_type signal)
++{
++ dcn10_link_encoder_disable_output(enc, signal);
++
++}
++static const struct link_encoder_funcs dcn21_link_enc_funcs = {
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++ .read_state = link_enc2_read_state,
++#endif
++ .validate_output_with_stream =
++ dcn10_link_encoder_validate_output_with_stream,
++ .hw_init = enc2_hw_init,
++ .setup = dcn10_link_encoder_setup,
++ .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
++ .enable_dp_output = dcn21_link_encoder_enable_dp_output,
++ .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
++ .disable_output = dcn21_link_encoder_disable_output,
++ .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
++ .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
++ .update_mst_stream_allocation_table =
++ dcn10_link_encoder_update_mst_stream_allocation_table,
++ .psr_program_dp_dphy_fast_training =
++ dcn10_psr_program_dp_dphy_fast_training,
++ .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
++ .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
++ .enable_hpd = dcn10_link_encoder_enable_hpd,
++ .disable_hpd = dcn10_link_encoder_disable_hpd,
++ .is_dig_enabled = dcn10_is_dig_enabled,
++ .destroy = dcn10_link_encoder_destroy,
++ .fec_set_enable = enc2_fec_set_enable,
++ .fec_set_ready = enc2_fec_set_ready,
++ .fec_is_active = enc2_fec_is_active,
++ .get_dig_frontend = dcn10_get_dig_frontend,
++};
++
++void dcn21_link_encoder_construct(
++ struct dcn21_link_encoder *enc21,
++ const struct encoder_init_data *init_data,
++ const struct encoder_feature_support *enc_features,
++ const struct dcn10_link_enc_registers *link_regs,
++ const struct dcn10_link_enc_aux_registers *aux_regs,
++ const struct dcn10_link_enc_hpd_registers *hpd_regs,
++ const struct dcn10_link_enc_shift *link_shift,
++ const struct dcn10_link_enc_mask *link_mask)
++{
++ struct bp_encoder_cap_info bp_cap_info = {0};
++ const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
++ enum bp_result result = BP_RESULT_OK;
++ struct dcn10_link_encoder *enc10 = &enc21->enc10;
++
++ enc10->base.funcs = &dcn21_link_enc_funcs;
++ enc10->base.ctx = init_data->ctx;
++ enc10->base.id = init_data->encoder;
++
++ enc10->base.hpd_source = init_data->hpd_source;
++ enc10->base.connector = init_data->connector;
++
++ enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
++
++ enc10->base.features = *enc_features;
++
++ enc10->base.transmitter = init_data->transmitter;
++
++ /* set the flag to indicate whether driver poll the I2C data pin
++ * while doing the DP sink detect
++ */
++
++/* if (dal_adapter_service_is_feature_supported(as,
++ FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
++ enc10->base.features.flags.bits.
++ DP_SINK_DETECT_POLL_DATA_PIN = true;*/
++
++ enc10->base.output_signals =
++ SIGNAL_TYPE_DVI_SINGLE_LINK |
++ SIGNAL_TYPE_DVI_DUAL_LINK |
++ SIGNAL_TYPE_LVDS |
++ SIGNAL_TYPE_DISPLAY_PORT |
++ SIGNAL_TYPE_DISPLAY_PORT_MST |
++ SIGNAL_TYPE_EDP |
++ SIGNAL_TYPE_HDMI_TYPE_A;
++
++ /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
++ * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
++ * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
++ * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
++ * Prefer DIG assignment is decided by board design.
++ * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
++ * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
++ * By this, adding DIGG should not hurt DCE 8.0.
++ * This will let DCE 8.1 share DCE 8.0 as much as possible
++ */
++
++ enc10->link_regs = link_regs;
++ enc10->aux_regs = aux_regs;
++ enc10->hpd_regs = hpd_regs;
++ enc10->link_shift = link_shift;
++ enc10->link_mask = link_mask;
++
++ switch (enc10->base.transmitter) {
++ case TRANSMITTER_UNIPHY_A:
++ enc10->base.preferred_engine = ENGINE_ID_DIGA;
++ break;
++ case TRANSMITTER_UNIPHY_B:
++ enc10->base.preferred_engine = ENGINE_ID_DIGB;
++ break;
++ case TRANSMITTER_UNIPHY_C:
++ enc10->base.preferred_engine = ENGINE_ID_DIGC;
++ break;
++ case TRANSMITTER_UNIPHY_D:
++ enc10->base.preferred_engine = ENGINE_ID_DIGD;
++ break;
++ case TRANSMITTER_UNIPHY_E:
++ enc10->base.preferred_engine = ENGINE_ID_DIGE;
++ break;
++ case TRANSMITTER_UNIPHY_F:
++ enc10->base.preferred_engine = ENGINE_ID_DIGF;
++ break;
++ case TRANSMITTER_UNIPHY_G:
++ enc10->base.preferred_engine = ENGINE_ID_DIGG;
++ break;
++ default:
++ ASSERT_CRITICAL(false);
++ enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
++ }
++
++ /* default to one to mirror Windows behavior */
++ enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
++
++ result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
++ enc10->base.id, &bp_cap_info);
++
++ /* Override features with DCE-specific values */
++ if (result == BP_RESULT_OK) {
++ enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
++ bp_cap_info.DP_HBR2_EN;
++ enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
++ bp_cap_info.DP_HBR3_EN;
++ enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
++ enc10->base.features.flags.bits.DP_IS_USB_C =
++ bp_cap_info.DP_IS_USB_C;
++ } else {
++ DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
++ __func__,
++ result);
++ }
++ if (enc10->base.ctx->dc->debug.hdmi20_disable) {
++ enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
++ }
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+new file mode 100644
+index 000000000000..438321e547db
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_LINK_ENCODER__DCN21_H__
++#define __DC_LINK_ENCODER__DCN21_H__
++
++#include "dcn20/dcn20_link_encoder.h"
++
++struct dcn21_link_encoder {
++ struct dcn10_link_encoder enc10;
++ struct dpcssys_phy_seq_cfg phy_seq_cfg;
++};
++
++void dcn21_link_encoder_enable_dp_output(
++ struct link_encoder *enc,
++ const struct dc_link_settings *link_settings,
++ enum clock_source_id clock_source);
++
++void dcn21_link_encoder_construct(
++ struct dcn21_link_encoder *enc21,
++ const struct encoder_init_data *init_data,
++ const struct encoder_feature_support *enc_features,
++ const struct dcn10_link_enc_registers *link_regs,
++ const struct dcn10_link_enc_aux_registers *aux_regs,
++ const struct dcn10_link_enc_hpd_registers *hpd_regs,
++ const struct dcn10_link_enc_shift *link_shift,
++ const struct dcn10_link_enc_mask *link_mask);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 1bac7eca5963..085e6d38c45e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -44,7 +44,7 @@
+ #include "dce110/dce110_hw_sequencer.h"
+ #include "dcn20/dcn20_opp.h"
+ #include "dcn20/dcn20_dsc.h"
+-#include "dcn20/dcn20_link_encoder.h"
++#include "dcn21/dcn21_link_encoder.h"
+ #include "dcn20/dcn20_stream_encoder.h"
+ #include "dce/dce_clock_source.h"
+ #include "dce/dce_audio.h"
+@@ -1513,6 +1513,87 @@ static struct link_encoder *dcn21_link_encoder_create(
+ return &enc21->enc10.base;
+ }
+
++static const struct encoder_feature_support link_enc_feature = {
++ .max_hdmi_deep_color = COLOR_DEPTH_121212,
++ .max_hdmi_pixel_clock = 600000,
++ .hdmi_ycbcr420_supported = true,
++ .dp_ycbcr420_supported = true,
++ .flags.bits.IS_HBR2_CAPABLE = true,
++ .flags.bits.IS_HBR3_CAPABLE = true,
++ .flags.bits.IS_TPS3_CAPABLE = true,
++ .flags.bits.IS_TPS4_CAPABLE = true
++};
++
++
++#define link_regs(id, phyid)\
++[id] = {\
++ LE_DCN10_REG_LIST(id), \
++ UNIPHY_DCN2_REG_LIST(phyid), \
++ SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
++}
++
++static const struct dcn10_link_enc_registers link_enc_regs[] = {
++ link_regs(0, A),
++ link_regs(1, B),
++ link_regs(2, C),
++ link_regs(3, D),
++ link_regs(4, E),
++};
++
++#define aux_regs(id)\
++[id] = {\
++ DCN2_AUX_REG_LIST(id)\
++}
++
++static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
++ aux_regs(0),
++ aux_regs(1),
++ aux_regs(2),
++ aux_regs(3),
++ aux_regs(4)
++};
++
++#define hpd_regs(id)\
++[id] = {\
++ HPD_REG_LIST(id)\
++}
++
++static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
++ hpd_regs(0),
++ hpd_regs(1),
++ hpd_regs(2),
++ hpd_regs(3),
++ hpd_regs(4)
++};
++
++static const struct dcn10_link_enc_shift le_shift = {
++ LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
++};
++
++static const struct dcn10_link_enc_mask le_mask = {
++ LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
++};
++
++static struct link_encoder *dcn21_link_encoder_create(
++ const struct encoder_init_data *enc_init_data)
++{
++ struct dcn21_link_encoder *enc21 =
++ kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
++
++ if (!enc21)
++ return NULL;
++
++ dcn21_link_encoder_construct(enc21,
++ enc_init_data,
++ &link_enc_feature,
++ &link_enc_regs[enc_init_data->transmitter],
++ &link_enc_aux_regs[enc_init_data->channel - 1],
++ &link_enc_hpd_regs[enc_init_data->hpd_source],
++ &le_shift,
++ &le_mask);
++
++ return &enc21->enc10.base;
++}
+ #define CTX ctx
+
+ #define REG(reg_name) \
+@@ -1528,7 +1609,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+
+ static struct resource_funcs dcn21_res_pool_funcs = {
+ .destroy = dcn21_destroy_resource_pool,
+- .link_enc_create = dcn20_link_encoder_create,
++ .link_enc_create = dcn21_link_encoder_create,
+ .validate_bandwidth = dcn21_validate_bandwidth,
+ .add_stream_to_ctx = dcn20_add_stream_to_ctx,
+ .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch
new file mode 100644
index 00000000..43cf27f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch
@@ -0,0 +1,207 @@
+From fbcf6e7ad774bd6a1f3895a9eae0c4e6150f28a2 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 14:04:54 -0400
+Subject: [PATCH 4175/4736] drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY
+ programming
+
+it allows us to do urgent latency programming
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 16 ++++++++
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 39 +++++++++++++++++--
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 ++++++++
+ .../gpu/drm/amd/display/dc/inc/hw/mem_input.h | 1 +
+ 4 files changed, 69 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2796c84db740..58678b679661 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2606,6 +2606,10 @@ void dcn20_calculate_wm(
+ context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++ context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++ context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+
+ if (vlevel < 2) {
+ pipes[0].clks_cfg.voltage = 2;
+@@ -2617,6 +2621,10 @@ void dcn20_calculate_wm(
+ context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++ context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++ context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+
+ if (vlevel < 3) {
+ pipes[0].clks_cfg.voltage = 3;
+@@ -2628,6 +2636,10 @@ void dcn20_calculate_wm(
+ context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++ context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++ context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+
+ pipes[0].clks_cfg.voltage = vlevel;
+ pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+@@ -2637,6 +2649,10 @@ void dcn20_calculate_wm(
+ context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++ context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++ context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+ }
+
+ void dcn20_calculate_dlg_params(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index d1266741763b..8e7e79f44272 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -97,7 +97,7 @@ void dcn21_dchvm_init(struct hubbub *hubbub)
+ REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+ }
+
+-static int hubbub21_init_dchub(struct hubbub *hubbub,
++int hubbub21_init_dchub(struct hubbub *hubbub,
+ struct dcn_hubbub_phys_addr_config *pa_config)
+ {
+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+@@ -120,7 +120,7 @@ static int hubbub21_init_dchub(struct hubbub *hubbub,
+ return NUM_VMID;
+ }
+
+-static void hubbub21_program_urgent_watermarks(
++void hubbub21_program_urgent_watermarks(
+ struct hubbub *hubbub,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz,
+@@ -160,6 +160,13 @@ static void hubbub21_program_urgent_watermarks(
+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
+ }
++ if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub1->watermarks.a.urgent_latency_ns) {
++ hubbub1->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns;
++ prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns,
++ refclk_mhz, 0x1fffff);
++ REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
++ DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value);
++ }
+
+ /* clock state B */
+ if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
+@@ -192,6 +199,14 @@ static void hubbub21_program_urgent_watermarks(
+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom);
+ }
+
++ if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub1->watermarks.b.urgent_latency_ns) {
++ hubbub1->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns;
++ prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns,
++ refclk_mhz, 0x1fffff);
++ REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
++ DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value);
++ }
++
+ /* clock state C */
+ if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {
+ hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
+@@ -223,6 +238,14 @@ static void hubbub21_program_urgent_watermarks(
+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom);
+ }
+
++ if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub1->watermarks.c.urgent_latency_ns) {
++ hubbub1->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns;
++ prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns,
++ refclk_mhz, 0x1fffff);
++ REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
++ DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value);
++ }
++
+ /* clock state D */
+ if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {
+ hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
+@@ -253,9 +276,17 @@ static void hubbub21_program_urgent_watermarks(
+ REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
+ DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom);
+ }
++
++ if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub1->watermarks.d.urgent_latency_ns) {
++ hubbub1->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns;
++ prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns,
++ refclk_mhz, 0x1fffff);
++ REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,
++ DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value);
++ }
+ }
+
+-static void hubbub21_program_stutter_watermarks(
++void hubbub21_program_stutter_watermarks(
+ struct hubbub *hubbub,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz,
+@@ -389,7 +420,7 @@ static void hubbub21_program_stutter_watermarks(
+ }
+ }
+
+-static void hubbub21_program_pstate_watermarks(
++void hubbub21_program_pstate_watermarks(
+ struct hubbub *hubbub,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+index 6ff3cdb89178..698c470cc0f6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+@@ -114,11 +114,28 @@
+ HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
+
+ void dcn21_dchvm_init(struct hubbub *hubbub);
++int hubbub21_init_dchub(struct hubbub *hubbub,
++ struct dcn_hubbub_phys_addr_config *pa_config);
+ void hubbub21_program_watermarks(
+ struct hubbub *hubbub,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz,
+ bool safe_to_lower);
++void hubbub21_program_urgent_watermarks(
++ struct hubbub *hubbub,
++ struct dcn_watermark_set *watermarks,
++ unsigned int refclk_mhz,
++ bool safe_to_lower);
++void hubbub21_program_stutter_watermarks(
++ struct hubbub *hubbub,
++ struct dcn_watermark_set *watermarks,
++ unsigned int refclk_mhz,
++ bool safe_to_lower);
++void hubbub21_program_pstate_watermarks(
++ struct hubbub *hubbub,
++ struct dcn_watermark_set *watermarks,
++ unsigned int refclk_mhz,
++ bool safe_to_lower);
+
+ void hubbub21_wm_read_state(struct hubbub *hubbub,
+ struct dcn_hubbub_wm *wm);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+index e8668388581b..67b610d6d91f 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+@@ -43,6 +43,7 @@ struct dcn_watermarks {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ uint32_t frac_urg_bw_nom;
+ uint32_t frac_urg_bw_flip;
++ int32_t urgent_latency_ns;
+ #endif
+ struct cstate_pstate_watermarks_st cstate_pstate;
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch
new file mode 100644
index 00000000..d83d3ade
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch
@@ -0,0 +1,66 @@
+From db7b94316b5d854d1eaf74fd7d9f97f331252ac7 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Wed, 2 Oct 2019 14:09:52 -0400
+Subject: [PATCH 4176/4736] drm/amd/display: move the bounding box patch before
+ calculate wm
+
+[why]
+driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box
+
+[How]
+Move the patch function before calculate wm.
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Signed-off-by: joseph graveno <joseph.gravenor@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 25 +++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 085e6d38c45e..05baf0e4d79f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1009,6 +1009,29 @@ static void calculate_wm_set_for_vlevel(
+
+ }
+
++static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
++{
++ kernel_fpu_begin();
++ if (dc->bb_overrides.sr_exit_time_ns) {
++ bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
++ }
++
++ if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
++ bb->sr_enter_plus_exit_time_us =
++ dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
++ }
++
++ if (dc->bb_overrides.urgent_latency_ns) {
++ bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
++ }
++
++ if (dc->bb_overrides.dram_clock_change_latency_ns) {
++ bb->dram_clock_change_latency_us =
++ dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
++ }
++ kernel_fpu_end();
++}
++
+ void dcn21_calculate_wm(
+ struct dc *dc, struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+@@ -1023,6 +1046,8 @@ void dcn21_calculate_wm(
+
+ ASSERT(bw_params);
+
++ patch_bounding_box(dc, &context->bw_ctx.dml.soc);
++
+ for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+ if (!context->res_ctx.pipe_ctx[i].stream)
+ continue;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch
new file mode 100644
index 00000000..1840beaf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch
@@ -0,0 +1,87 @@
+From 029033b0e5f6415f7e129232b13f402a41763c9d Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 2 Oct 2019 15:19:41 -0400
+Subject: [PATCH 4177/4736] drm/amd/display: enable hostvm based on roimmu
+ active for dcn2.1
+
+Enabling hostvm when ROIMMU is not active seems to break GPUVM.
+This fixes the issue by not enabling hostvm if ROIMMU is not
+activated.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 40 ++++++++++++-------
+ 1 file changed, 25 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index 8e7e79f44272..bd247e5e753e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -22,6 +22,7 @@
+ * Authors: AMD
+ *
+ */
++#include <linux/delay.h>
+ #include "dm_services.h"
+ #include "dcn20/dcn20_hubbub.h"
+ #include "dcn21_hubbub.h"
+@@ -71,30 +72,39 @@ static uint32_t convert_and_clamp(
+ void dcn21_dchvm_init(struct hubbub *hubbub)
+ {
+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++ uint32_t riommu_active;
++ int i;
+
+ //Init DCHVM block
+ REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
+
+ //Poll until RIOMMU_ACTIVE = 1
+- //TODO: Figure out interval us and retry count
+- REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);
++ for (i = 0; i < 100; i++) {
++ REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active);
+
+- //Reflect the power status of DCHUBBUB
+- REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
++ if (riommu_active)
++ break;
++ else
++ udelay(5);
++ }
++
++ if (riommu_active) {
++ //Reflect the power status of DCHUBBUB
++ REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
+
+- //Start rIOMMU prefetching
+- REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
++ //Start rIOMMU prefetching
++ REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
+
+- // Enable dynamic clock gating
+- REG_UPDATE_4(DCHVM_CLK_CTRL,
+- HVM_DISPCLK_R_GATE_DIS, 0,
+- HVM_DISPCLK_G_GATE_DIS, 0,
+- HVM_DCFCLK_R_GATE_DIS, 0,
+- HVM_DCFCLK_G_GATE_DIS, 0);
++ // Enable dynamic clock gating
++ REG_UPDATE_4(DCHVM_CLK_CTRL,
++ HVM_DISPCLK_R_GATE_DIS, 0,
++ HVM_DISPCLK_G_GATE_DIS, 0,
++ HVM_DCFCLK_R_GATE_DIS, 0,
++ HVM_DCFCLK_G_GATE_DIS, 0);
+
+- //Poll until HOSTVM_PREFETCH_DONE = 1
+- //TODO: Figure out interval us and retry count
+- REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
++ //Poll until HOSTVM_PREFETCH_DONE = 1
++ REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
++ }
+ }
+
+ int hubbub21_init_dchub(struct hubbub *hubbub,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4178-drm-amd-display-fix-incorrect-page-table-address-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4178-drm-amd-display-fix-incorrect-page-table-address-for.patch
new file mode 100644
index 00000000..df23f56e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4178-drm-amd-display-fix-incorrect-page-table-address-for.patch
@@ -0,0 +1,59 @@
+From 91e966568edf9bd745a26c96b77708cf3092a02a Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 15:31:03 -0400
+Subject: [PATCH 4178/4736] drm/amd/display: fix incorrect page table address
+ for renoir
+
+Incorrect page table address and programming sys aperture for
+stutter gather, so fix it.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 23 ++++++++++++++-----
+ 1 file changed, 17 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index bd247e5e753e..fdfbdeb32459 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -111,19 +111,30 @@ int hubbub21_init_dchub(struct hubbub *hubbub,
+ struct dcn_hubbub_phys_addr_config *pa_config)
+ {
+ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++ struct dcn_vmid_page_table_config phys_config;
+
+ REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
+- FB_BASE, pa_config->system_aperture.fb_base);
++ FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
+- FB_TOP, pa_config->system_aperture.fb_top);
++ FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ REG_SET(DCN_VM_FB_OFFSET, 0,
+- FB_OFFSET, pa_config->system_aperture.fb_offset);
++ FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ REG_SET(DCN_VM_AGP_BOT, 0,
+- AGP_BOT, pa_config->system_aperture.agp_bot);
++ AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ REG_SET(DCN_VM_AGP_TOP, 0,
+- AGP_TOP, pa_config->system_aperture.agp_top);
++ AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ REG_SET(DCN_VM_AGP_BASE, 0,
+- AGP_BASE, pa_config->system_aperture.agp_base);
++ AGP_BASE, pa_config->system_aperture.agp_base >> 24);
++
++ if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
++ phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
++ phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
++ phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr | 1; //Note: hack
++ phys_config.depth = 0;
++ phys_config.block_size = 0;
++ // Init VMID 0 based on PA config
++ dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
++ }
+
+ dcn21_dchvm_init(hubbub);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch
new file mode 100644
index 00000000..d76a05db
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch
@@ -0,0 +1,92 @@
+From 4a2de49201a3d53abc4c27c8a93e368d7e65c926 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Sat, 6 Jul 2019 16:02:25 -0500
+Subject: [PATCH 4179/4736] drm/amd/display: Temporary workaround to toggle
+ watermark setting
+
+[Why]
+Watermarks not propagated to DCHUBP after it is powered on
+
+[How]
+Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 +
+ 4 files changed, 15 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index ce2530509e12..6229a8ca0013 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1533,6 +1533,10 @@ static void dcn20_program_front_end_for_ctx(
+ msleep(1);
+ }
+ }
++
++ /* WA to apply WM setting*/
++ if (dc->hwseq->wa.DEGVIDCN21)
++ dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
+ }
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index fdfbdeb32459..2232ccf14bdd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -616,6 +616,14 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
+ DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
+ }
+
++void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
++{
++ struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++ uint32_t prog_wm_value;
++
++ prog_wm_value = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
++ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
++}
+
+ static const struct hubbub_funcs hubbub21_funcs = {
+ .update_dchub = hubbub2_update_dchub,
+@@ -627,6 +635,7 @@ static const struct hubbub_funcs hubbub21_funcs = {
+ .wm_read_state = hubbub21_wm_read_state,
+ .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+ .program_watermarks = hubbub21_program_watermarks,
++ .apply_DEDCN21_147_wa = hubbub21_apply_DEDCN21_147_wa,
+ };
+
+ void hubbub21_construct(struct dcn20_hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 05baf0e4d79f..a9e2dd71d7a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1470,6 +1470,7 @@ static struct dce_hwseq *dcn21_hwseq_create(
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
++ hws->wa.DEGVIDCN21 = true;
+ }
+ return hws;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index a6297219d7fc..c81a17aeaa25 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -147,6 +147,7 @@ struct hubbub_funcs {
+ bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
+ void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
+
++ void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
+ };
+
+ struct hubbub {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch
new file mode 100644
index 00000000..92948dc2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch
@@ -0,0 +1,32 @@
+From 3e89f7c5fc264a02e59fefb7d9057d3801dad48b Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 2 Oct 2019 15:55:48 -0400
+Subject: [PATCH 4180/4736] drm/amd/display: initialize RN gpuvm context
+ programming function
+
+Renoir can use vm contexes as long as HOSTVM is off so
+this should be initialized.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index 2232ccf14bdd..44f64a8e33f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -628,7 +628,7 @@ void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
+ static const struct hubbub_funcs hubbub21_funcs = {
+ .update_dchub = hubbub2_update_dchub,
+ .init_dchub_sys_ctx = hubbub21_init_dchub,
+- .init_vm_ctx = NULL,
++ .init_vm_ctx = hubbub2_init_vm_ctx,
+ .dcc_support_swizzle = hubbub2_dcc_support_swizzle,
+ .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+ .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch
new file mode 100644
index 00000000..7e2aae99
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch
@@ -0,0 +1,41 @@
+From f9655dbe5243835a39463a6fc5833bcc07ff64d6 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Wed, 2 Oct 2019 15:57:13 -0400
+Subject: [PATCH 4181/4736] drm/amd/display: use dcn10 version of program
+ tiling on Renoir
+
+[Why]
+Renoir is gfx9, same as dcn10, not dcn20.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index a00af513aa2b..2f5a5867e674 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -22,6 +22,8 @@
+ * Authors: AMD
+ *
+ */
++
++#include "dcn10/dcn10_hubp.h"
+ #include "dcn21_hubp.h"
+
+ #include "dm_services.h"
+@@ -202,7 +204,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
+ .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+ .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+ .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
+- .hubp_program_surface_config = hubp2_program_surface_config,
++ .hubp_program_surface_config = hubp1_program_surface_config,
+ .hubp_is_flip_pending = hubp1_is_flip_pending,
+ .hubp_setup = hubp21_setup,
+ .hubp_setup_interdependent = hubp2_setup_interdependent,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch
new file mode 100644
index 00000000..d0549b65
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch
@@ -0,0 +1,31 @@
+From bc38311a711c0dd65138f1253bec9d8f021dc821 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 2 Oct 2019 15:59:23 -0400
+Subject: [PATCH 4182/4736] drm/amd/display: correct dcn21 NUM_VMID to 16
+
+1 vmid limitation only exists for HOSTVM which is a custom
+use case anyway.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index 44f64a8e33f1..aeb5de6f4530 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -52,7 +52,7 @@
+ #ifdef NUM_VMID
+ #undef NUM_VMID
+ #endif
+-#define NUM_VMID 1
++#define NUM_VMID 16
+
+ static uint32_t convert_and_clamp(
+ uint32_t wm_ns,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch
new file mode 100644
index 00000000..8a6b5a32
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch
@@ -0,0 +1,27 @@
+From 42c60ff4f15362f4645549a8090d4f22ea8ef7df Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:35:36 -0400
+Subject: [PATCH 4183/4736] drm/amd/display: add detile buffer size for renoir
+
+Detile buffer size affects dcc caps, it was already added for
+dcn2. Now add it for dcn21
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index aeb5de6f4530..f546260c15b7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -653,4 +653,5 @@ void hubbub21_construct(struct dcn20_hubbub *hubbub,
+ hubbub->masks = hubbub_mask;
+
+ hubbub->debug_test_index_pstate = 0xB;
++ hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4184-drm-amd-display-update-dcn21-hubbub-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4184-drm-amd-display-update-dcn21-hubbub-registers.patch
new file mode 100644
index 00000000..3f1d24ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4184-drm-amd-display-update-dcn21-hubbub-registers.patch
@@ -0,0 +1,59 @@
+From 32559e89cd648263466d70e07de915d1409a9a49 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:38:57 -0400
+Subject: [PATCH 4184/4736] drm/amd/display: update dcn21 hubbub registers
+
+use dcn20 common regs define to share some regs with dcn20
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 +++++++----------
+ 1 file changed, 7 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+index 698c470cc0f6..c4840dfb1fa5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+@@ -36,6 +36,10 @@
+ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
+ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
+ SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
++ SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
++ SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
++ SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
++ SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
+ SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
+ SR(DCHVM_CTRL0), \
+ SR(DCHVM_MEM_CTRL), \
+@@ -44,16 +48,9 @@
+ SR(DCHVM_RIOMMU_STAT0)
+
+ #define HUBBUB_REG_LIST_DCN21()\
+- HUBBUB_REG_LIST_DCN_COMMON(), \
++ HUBBUB_REG_LIST_DCN20_COMMON(), \
+ HUBBUB_SR_WATERMARK_REG_LIST(), \
+- HUBBUB_HVM_REG_LIST(), \
+- SR(DCHUBBUB_CRC_CTRL), \
+- SR(DCN_VM_FB_LOCATION_BASE),\
+- SR(DCN_VM_FB_LOCATION_TOP),\
+- SR(DCN_VM_FB_OFFSET),\
+- SR(DCN_VM_AGP_BOT),\
+- SR(DCN_VM_AGP_TOP),\
+- SR(DCN_VM_AGP_BASE)
++ HUBBUB_HVM_REG_LIST()
+
+ #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \
+ HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \
+@@ -102,7 +99,7 @@
+ HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh)
+
+ #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\
+- HUBBUB_MASK_SH_LIST_HVM(mask_sh),\
++ HUBBUB_MASK_SH_LIST_HVM(mask_sh), \
+ HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
+ HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
+ HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch
new file mode 100644
index 00000000..5a4277ba
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch
@@ -0,0 +1,88 @@
+From c926472982c5f3f9b43d2e2c6becd6961df3e24e Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:42:24 -0400
+Subject: [PATCH 4185/4736] drm/amd/display: update renoir bounding box and
+ res_caps
+
+The values for bounding box and res_caps were incorrect. So
+Fix them
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 24 ++++++++++---------
+ 1 file changed, 13 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index a9e2dd71d7a6..05b0b9ae37ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -82,6 +82,7 @@
+
+
+ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
++ .odm_capable = 1,
+ .gpuvm_enable = 0,
+ .hostvm_enable = 0,
+ .gpuvm_max_page_table_levels = 1,
+@@ -203,11 +204,11 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
+ .state = 4,
+ .dcfclk_mhz = 810.0,
+ .fabricclk_mhz = 1600.0,
+- .dispclk_mhz = 1015.0,
+- .dppclk_mhz = 1015.0,
+- .phyclk_mhz = 810.0,
++ .dispclk_mhz = 1395.0,
++ .dppclk_mhz = 1285.0,
++ .phyclk_mhz = 1325.0,
+ .socclk_mhz = 953.0,
+- .dscclk_mhz = 318.334,
++ .dscclk_mhz = 489.0,
+ .dram_speed_mts = 4266.0,
+ },
+ /*Extra state, no dispclk ramping*/
+@@ -215,18 +216,18 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
+ .state = 5,
+ .dcfclk_mhz = 810.0,
+ .fabricclk_mhz = 1600.0,
+- .dispclk_mhz = 1015.0,
+- .dppclk_mhz = 1015.0,
+- .phyclk_mhz = 810.0,
++ .dispclk_mhz = 1395.0,
++ .dppclk_mhz = 1285.0,
++ .phyclk_mhz = 1325.0,
+ .socclk_mhz = 953.0,
+- .dscclk_mhz = 318.334,
++ .dscclk_mhz = 489.0,
+ .dram_speed_mts = 4266.0,
+ },
+
+ },
+
+- .sr_exit_time_us = 9.0,
+- .sr_enter_plus_exit_time_us = 11.0,
++ .sr_exit_time_us = 12.5,
++ .sr_enter_plus_exit_time_us = 17.0,
+ .urgent_latency_us = 4.0,
+ .urgent_latency_pixel_data_only_us = 4.0,
+ .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+@@ -766,6 +767,7 @@ static const struct resource_caps res_cap_rn = {
+ .num_pll = 5, // maybe 3 because the last two used for USB-c
+ .num_dwb = 1,
+ .num_ddc = 5,
++ .num_vmid = 1,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .num_dsc = 3,
+ #endif
+@@ -835,7 +837,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ .disable_dcc = DCC_ENABLE,
+ .vsr_support = true,
+ .performance_trace = false,
+- .max_downscale_src_width = 5120,/*upto 5K*/
++ .max_downscale_src_width = 3840,
+ .disable_pplib_wm_range = false,
+ .scl_reset_length10 = true,
+ .sanity_checks = true,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch
new file mode 100644
index 00000000..7d97dff1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch
@@ -0,0 +1,36 @@
+From fc5567ddc6bf05ed6d8078ca1b5d23c93f9012bb Mon Sep 17 00:00:00 2001
+From: Sung Lee <sung.lee@amd.com>
+Date: Fri, 30 Aug 2019 13:36:40 -0400
+Subject: [PATCH 4186/4736] drm/amd/display: add dummy functions to smu for
+ Renoir Silicon Diags
+
+[Why]
+Previously only dummy functions were added in Diags for FPGA.
+On silicon, this would lead to a segmentation fault on silicon diags.
+
+[How]
+Check if diags silicon and if so, add dummy functions.
+
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 05b0b9ae37ac..2125a3e50b0b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1399,7 +1399,7 @@ static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
+ if (!pp_smu)
+ return pp_smu;
+
+- if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
+ pp_smu->ctx.ver = PP_SMU_VER_RN;
+ pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
+ pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
new file mode 100644
index 00000000..5ce208f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
@@ -0,0 +1,62 @@
+From bbd12c8b9ac0d46f8738b88e6716ebabb2e7dc16 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 30 Aug 2019 16:32:13 -0400
+Subject: [PATCH 4187/4736] drm/amd/display: update odm mode validation to be
+ in line with policy
+
+Previously 8k30 worked with dsc and odm combine due to a workaround that ran
+the formula a second time with dsc support enable should dsc validation fail.
+This worked when clocks were low enough for formula to enable odm to lower
+voltage, however now broke due to increased clocks.
+
+This change updates the ODM combine policy within the formula to properly
+reflect our current policy within DC, only enabling ODM when we have to, as
+well as adding a check for viewport width when dsc is enabled.
+
+As a side effect the redundant call to dml when odm is required is now
+unnecessary.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index 3b6ed60dcd35..fd707e7459b5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -65,6 +65,7 @@ typedef struct {
+
+ #define BPP_INVALID 0
+ #define BPP_BLENDED_PIPE 0xffffffff
++#define DCN21_MAX_DSC_IMAGE_WIDTH 5184
+
+ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
+ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
+@@ -3936,6 +3937,10 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
+ mode_lib->vba.MaximumSwathWidthInLineBuffer);
+ }
+ for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++ double MaxMaxDispclkRoundedDown = RoundToDFSGranularityDown(
++ mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
++ mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++
+ for (j = 0; j < 2; j++) {
+ mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
+ mode_lib->vba.MaxDispclk[i],
+@@ -3965,7 +3970,9 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
+ && i == mode_lib->vba.soc.num_states)
+ mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
+ * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+- if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
++ if (mode_lib->vba.ODMCapability == false ||
++ (locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown
++ && (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN21_MAX_DSC_IMAGE_WIDTH))) {
+ locals->ODMCombineEnablePerState[i][k] = false;
+ mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
+ } else {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch
new file mode 100644
index 00000000..ec668b3f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch
@@ -0,0 +1,31 @@
+From b3dffd458cd73f615a072c4226fde585cc2b7e4f Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 14:48:10 -0400
+Subject: [PATCH 4188/4736] drm/amd/display: handle "18" case in
+ TruncToValidBPP
+
+Handle 18 DecimalBPP like other cases
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index fd707e7459b5..ba77957aefe3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -3380,6 +3380,8 @@ static unsigned int TruncToValidBPP(
+ return 30;
+ else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
+ return 24;
++ else if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
++ return 18;
+ else
+ return BPP_INVALID;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch
new file mode 100644
index 00000000..218a424c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch
@@ -0,0 +1,61 @@
+From 126d6092ca5e7273958180f377881ec38b0efa8f Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Wed, 7 Aug 2019 16:52:20 -0400
+Subject: [PATCH 4189/4736] drm/amd/display: Fix rn audio playback and video
+ playback speed
+
+[WHY]
+dprefclk is improperly read due to incorrect units used.
+Causes an audio clock to be improperly set, making audio
+non-functional and videos play back too fast
+
+[HOW]
+Scale dprefclk value from MHz to KHz (multiply by 1000)
+to ensure that dprefclk_khz is in correct units
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 93e46e376bb1..fb8aa9436bf0 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -377,7 +377,7 @@ void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
+
+ rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
+
+- s->dprefclk_khz = sb.dprefclk;
++ s->dprefclk_khz = sb.dprefclk * 1000;
+ }
+
+ void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+@@ -633,16 +633,15 @@ void rn_clk_mgr_construct(
+ clk_mgr->dentist_vco_freq_khz = 3600000;
+
+ rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
+- clk_mgr->base.dprefclk_khz = s.dprefclk;
+-
+- if (clk_mgr->base.dprefclk_khz != 600000) {
+- clk_mgr->base.dprefclk_khz = 600000;
+- ASSERT(1); //TODO: Renoir follow up.
+- }
++ /* Convert dprefclk units from MHz to KHz */
++ /* Value already divided by 10, some resolution lost */
++ clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
+
+ /* in case we don't get a value from the register, use default */
+- if (clk_mgr->base.dprefclk_khz == 0)
++ if (clk_mgr->base.dprefclk_khz == 0) {
++ ASSERT(clk_mgr->base.dprefclk_khz == 600000);
+ clk_mgr->base.dprefclk_khz = 600000;
++ }
+ }
+
+ dce_clock_read_ss_info(clk_mgr);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch
new file mode 100644
index 00000000..cb1dfa41
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch
@@ -0,0 +1,50 @@
+From cd651b9c1930cc2c2c05ea02f788c390adf9e10a Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Thu, 3 Oct 2019 15:06:01 -0400
+Subject: [PATCH 4190/4736] drm/amd/display: add sanity check for clk table
+ from smu
+
+[Why]
+Handle the case where we don't get a valid table. Also fixes compiler
+warning for variable potentially used before assignment.
+
+[How]
+If the entire table has no valid fclk, reject the table and use our own
+hard code.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index fb8aa9436bf0..0e712df87109 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -546,6 +546,8 @@ void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struc
+ {
+ int i, j = 0;
+
++ j = -1;
++
+ ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
+
+ /* Find lowest DPM, FCLK is filled in reverse order*/
+@@ -557,6 +559,12 @@ void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struc
+ }
+ }
+
++ if (j == -1) {
++ /* clock table is all 0s, just use our own hardcode */
++ ASSERT(0);
++ return;
++ }
++
+ bw_params->clk_table.num_entries = j + 1;
+
+ for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch
new file mode 100644
index 00000000..d2e45a53
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch
@@ -0,0 +1,43 @@
+From 76c869d28bc5e2577e9af4b4ad53936333cac8ef Mon Sep 17 00:00:00 2001
+From: joseph gravenor <joseph.gravenor@amd.com>
+Date: Mon, 8 Jul 2019 13:41:01 -0400
+Subject: [PATCH 4191/4736] drm/amd/display: fix header for RN clk mgr
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[why]
+Should always MP0_BASE for any register definition from MP per-IP header files.
+I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table
+of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file.
+The reason we should only use MP0_BASE is There is only one set of per-IP headers MP
+that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2
+and an ecryption engine that can be used only by MP0. As a result all register definitions from
+MP file should be based only on MP0_BASE data.
+
+[How]
+Change MP1_BASE to MP0_BASE
+
+Signed-off-by: joseph gravenor <joseph.gravenor@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index 8e860f567d5c..db28e91adb3d 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -33,7 +33,7 @@
+ #include "mp/mp_12_0_0_sh_mask.h"
+
+ #define REG(reg_name) \
+- (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
++ (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+ #define FN(reg_name, field) \
+ FD(reg_name##__##field)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4192-drm-amd-display-enable-smu-set-dcfclk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4192-drm-amd-display-enable-smu-set-dcfclk.patch
new file mode 100644
index 00000000..c3badf7b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4192-drm-amd-display-enable-smu-set-dcfclk.patch
@@ -0,0 +1,43 @@
+From 17eb350281c4b09d8236036578f4a545af143205 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Fri, 26 Jul 2019 14:02:03 -0400
+Subject: [PATCH 4192/4736] drm/amd/display: enable smu set dcfclk
+
+[Why]
+SMU fixed this issue after version 0x370c00
+
+[How]
+enable smu send message to set dcfclk after smu version 0x370c00
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index db28e91adb3d..2650776acbc3 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -124,7 +124,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque
+ {
+ int actual_dcfclk_set_mhz = -1;
+
+- if (clk_mgr->smu_ver < 0xFFFFFFFF)
++ if (clk_mgr->smu_ver < 0x370c00)
+ return actual_dcfclk_set_mhz;
+
+ actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+@@ -139,7 +139,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int
+ {
+ int actual_min_ds_dcfclk_mhz = -1;
+
+- if (clk_mgr->smu_ver < 0xFFFFFFFF)
++ if (clk_mgr->smu_ver < 0x370c00)
+ return actual_min_ds_dcfclk_mhz;
+
+ actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch
new file mode 100644
index 00000000..ba6e6d11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch
@@ -0,0 +1,56 @@
+From a52e0d8d91005bb469581eefb5f3ec5bff836452 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 15:39:14 -0400
+Subject: [PATCH 4193/4736] drm/amd/display: use requested_dispclk_khz instead
+ of clk
+
+Use requested_dispclk_khz / 1000 directly
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 ++-----------
+ 1 file changed, 2 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index 2650776acbc3..5647fcf10717 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -84,16 +84,12 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
+ int actual_dispclk_set_mhz = -1;
+ struct dc *core_dc = clk_mgr->base.ctx->dc;
+ struct dmcu *dmcu = core_dc->res_pool->dmcu;
+- uint32_t clk = requested_dispclk_khz / 1000;
+-
+- if (clk <= 100)
+- clk = 101;
+
+ /* Unit of SMU msg parameter is Mhz */
+ actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetDispclkFreq,
+- clk);
++ requested_dispclk_khz / 1000);
+
+ if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
+ if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+@@ -162,15 +158,10 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_
+ {
+ int actual_dppclk_set_mhz = -1;
+
+- uint32_t clk = requested_dpp_khz / 1000;
+-
+- if (clk <= 100)
+- clk = 101;
+-
+ actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+ clk_mgr,
+ VBIOSSMC_MSG_SetDppclkFreq,
+- clk);
++ requested_dpp_khz / 1000);
+
+ return actual_dppclk_set_mhz * 1000;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4194-drm-amd-display-handle-dp-is-usb-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4194-drm-amd-display-handle-dp-is-usb-c.patch
new file mode 100644
index 00000000..858e7590
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4194-drm-amd-display-handle-dp-is-usb-c.patch
@@ -0,0 +1,204 @@
+From 9f9a2f7528397a663e8472ddaa522e8bea6eece4 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 11 Oct 2019 10:37:49 -0400
+Subject: [PATCH 4194/4736] drm/amd/display: handle dp is usb-c
+
+This patch adds handling of dp is usb-c, it is not tested but is
+needed to support dp over usb-c
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h | 14 +++
+ .../amd/display/dc/dcn21/dcn21_link_encoder.c | 93 ++++++++++++++++++-
+ .../amd/display/dc/dcn21/dcn21_link_encoder.h | 10 ++
+ 3 files changed, 116 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 239a6c90ffb9..88fcc395adf5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -113,6 +113,20 @@ struct dcn10_link_enc_registers {
+ uint32_t DIG_LANE_ENABLE;
+ /* UNIPHY */
+ uint32_t CHANNEL_XBAR_CNTL;
++ /* DPCS */
++ uint32_t RDPCSTX_PHY_CNTL3;
++ uint32_t RDPCSTX_PHY_CNTL4;
++ uint32_t RDPCSTX_PHY_CNTL5;
++ uint32_t RDPCSTX_PHY_CNTL6;
++ uint32_t RDPCSTX_PHY_CNTL7;
++ uint32_t RDPCSTX_PHY_CNTL8;
++ uint32_t RDPCSTX_PHY_CNTL9;
++ uint32_t RDPCSTX_PHY_CNTL10;
++ uint32_t RDPCSTX_PHY_CNTL11;
++ uint32_t RDPCSTX_PHY_CNTL12;
++ uint32_t RDPCSTX_PHY_CNTL13;
++ uint32_t RDPCSTX_PHY_CNTL14;
++ uint32_t RDPCSTX_PHY_CNTL15;
+ /* indirect registers */
+ uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+index 526865c43b48..e8a504ca5890 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+@@ -203,6 +203,77 @@ static bool update_cfg_data(
+ return true;
+ }
+
++void dcn21_link_encoder_get_max_link_cap(struct link_encoder *enc,
++ struct dc_link_settings *link_settings)
++{
++ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++ uint32_t value;
++
++ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value);
++
++ if (!value && link_settings->lane_count > LANE_COUNT_TWO)
++ link_settings->lane_count = LANE_COUNT_TWO;
++}
++
++bool dcn21_link_encoder_is_in_alt_mode(struct link_encoder *enc)
++{
++ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++ uint32_t value;
++
++ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value);
++
++ // if value == 1 alt mode is disabled, otherwise it is enabled
++ return !value;
++}
++
++bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
++{
++ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++ int value;
++
++ if (enc->features.flags.bits.DP_IS_USB_C) {
++ REG_GET(RDPCSTX_PHY_CNTL6,
++ RDPCS_PHY_DPALT_DISABLE, &value);
++
++ if (value == 1) {
++ ASSERT(0);
++ return false;
++ }
++ REG_UPDATE(RDPCSTX_PHY_CNTL6,
++ RDPCS_PHY_DPALT_DISABLE_ACK, 0);
++
++ udelay(40);
++
++ REG_GET(RDPCSTX_PHY_CNTL6,
++ RDPCS_PHY_DPALT_DISABLE, &value);
++ if (value == 1) {
++ ASSERT(0);
++ REG_UPDATE(RDPCSTX_PHY_CNTL6,
++ RDPCS_PHY_DPALT_DISABLE_ACK, 1);
++ return false;
++ }
++ }
++
++ REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1);
++
++ return true;
++}
++
++
++
++static void dcn21_link_encoder_release_phy(struct link_encoder *enc)
++{
++ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++
++ if (enc->features.flags.bits.DP_IS_USB_C) {
++ REG_UPDATE(RDPCSTX_PHY_CNTL6,
++ RDPCS_PHY_DPALT_DISABLE_ACK, 1);
++ }
++
++ REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0);
++
++}
++
+ void dcn21_link_encoder_enable_dp_output(
+ struct link_encoder *enc,
+ const struct dc_link_settings *link_settings,
+@@ -212,6 +283,9 @@ void dcn21_link_encoder_enable_dp_output(
+ struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
+ struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg;
+
++ if (!dcn21_link_encoder_acquire_phy(enc))
++ return;
++
+ if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+ dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
+ return;
+@@ -226,13 +300,28 @@ void dcn21_link_encoder_enable_dp_output(
+
+ }
+
++void dcn21_link_encoder_enable_dp_mst_output(
++ struct link_encoder *enc,
++ const struct dc_link_settings *link_settings,
++ enum clock_source_id clock_source)
++{
++ if (!dcn21_link_encoder_acquire_phy(enc))
++ return;
++
++ dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
++}
++
+ void dcn21_link_encoder_disable_output(
+ struct link_encoder *enc,
+ enum signal_type signal)
+ {
+ dcn10_link_encoder_disable_output(enc, signal);
+
++ if (dc_is_dp_signal(signal))
++ dcn21_link_encoder_release_phy(enc);
+ }
++
++
+ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .read_state = link_enc2_read_state,
+@@ -243,7 +332,7 @@ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+ .setup = dcn10_link_encoder_setup,
+ .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+ .enable_dp_output = dcn21_link_encoder_enable_dp_output,
+- .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
++ .enable_dp_mst_output = dcn21_link_encoder_enable_dp_mst_output,
+ .disable_output = dcn21_link_encoder_disable_output,
+ .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+ .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+@@ -261,6 +350,8 @@ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+ .fec_set_ready = enc2_fec_set_ready,
+ .fec_is_active = enc2_fec_is_active,
+ .get_dig_frontend = dcn10_get_dig_frontend,
++ .is_in_alt_mode = dcn21_link_encoder_is_in_alt_mode,
++ .get_max_link_cap = dcn21_link_encoder_get_max_link_cap,
+ };
+
+ void dcn21_link_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+index 438321e547db..1d7a1a51f13d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+@@ -33,6 +33,16 @@ struct dcn21_link_encoder {
+ struct dpcssys_phy_seq_cfg phy_seq_cfg;
+ };
+
++#define LINK_ENCODER_MASK_SH_LIST_DCN21(mask_sh)\
++ LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\
++ LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
++ LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
++ LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
++ LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh), \
++ SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
++ SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
++ SR(RDPCSTX0_RDPCSTX_SCRATCH)
++
+ void dcn21_link_encoder_enable_dp_output(
+ struct link_encoder *enc,
+ const struct dc_link_settings *link_settings,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch
new file mode 100644
index 00000000..7cd67919
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch
@@ -0,0 +1,28 @@
+From 3c1c5221e17232b6e28de486f39948cc66ac3aec Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 11 Oct 2019 14:58:02 -0400
+Subject: [PATCH 4195/4736] drm/amd/display: null check pp_smu clock table
+ before using it
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 0e712df87109..b647e0320e4b 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -656,7 +656,7 @@ void rn_clk_mgr_construct(
+
+ clk_mgr->base.bw_params = &rn_bw_params;
+
+- if (pp_smu) {
++ if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
+ pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
+ rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4196-drm-amd-display-Make-dc_link_detect_helper-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4196-drm-amd-display-Make-dc_link_detect_helper-static.patch
new file mode 100644
index 00000000..ff1fe442
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4196-drm-amd-display-Make-dc_link_detect_helper-static.patch
@@ -0,0 +1,34 @@
+From 7ce4c5d8b0adaa37aaf0a0bb434274c1dec9d982 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Wed, 16 Oct 2019 19:15:41 +0800
+Subject: [PATCH 4196/4736] drm/amd/display: Make dc_link_detect_helper static
+
+Fix sparse warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:746:6:
+ warning: symbol 'dc_link_detect_helper' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 2a7fb79ad9f3..5474e2525e0c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -741,7 +741,8 @@ static bool wait_for_alt_mode(struct dc_link *link)
+ * This does not create remote sinks but will trigger DM
+ * to start MST detection if a branch is detected.
+ */
+-bool dc_link_detect_helper(struct dc_link *link, enum dc_detect_reason reason)
++static bool dc_link_detect_helper(struct dc_link *link,
++ enum dc_detect_reason reason)
+ {
+ struct dc_sink_init_data sink_init_data = { 0 };
+ struct display_sink_capability sink_caps = { 0 };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4197-drm-amdgpu-soc15-remove-unused-variables.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4197-drm-amdgpu-soc15-remove-unused-variables.patch
new file mode 100644
index 00000000..1d7385ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4197-drm-amdgpu-soc15-remove-unused-variables.patch
@@ -0,0 +1,28 @@
+From f25033019e1a27a4f1cb90dba3ce989449dfa28a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 16 Oct 2019 12:20:09 -0400
+Subject: [PATCH 4197/4736] drm/amdgpu/soc15: remove unused variables
+
+Leftover when I rebased my last baco patches. Trivial.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 438722c0b76a..9457502a9909 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -497,8 +497,6 @@ static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
+
+ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ {
+- void *pp_handle = adev->powerplay.pp_handle;
+- const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+ /* avoid NBIF got stuck when do RAS recovery in BACO reset */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch
new file mode 100644
index 00000000..5b7472f9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch
@@ -0,0 +1,31 @@
+From ba843799853807d7e4ae8dd5fe09fa9cc99e115b Mon Sep 17 00:00:00 2001
+From: Stephen Rothwell <sfr@canb.auug.org.au>
+Date: Wed, 16 Oct 2019 11:22:07 +1100
+Subject: [PATCH 4198/4736] drm/amdgpu: fix up for amdgpu_tmz.c and removal of
+ drm/drmP.h
+
+Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+index 14a55003dd81..823527a0fa47 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+@@ -20,7 +20,10 @@
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+-#include <drm/drmP.h>
++#include <linux/device.h>
++
++#include <drm/amd_asic_type.h>
++
+ #include "amdgpu.h"
+ #include "amdgpu_tmz.h"
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..d16214f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,134 @@
+From d621bffdf3894c0199526204509d46f2450a0a95 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 18:07:19 -0400
+Subject: [PATCH 4199/4736] drm/amdgpu/uvd6: fix allocation size in enc ring
+ test (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+session info, otherwise the IB test can overwrite
+other memory.
+
+v2: - session info is 128K according to mesa
+ - use the same session info for create and destroy
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Tested-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 31 ++++++++++++++++++---------
+ 1 file changed, 21 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+index 16682b7998be..aa3849282bd4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+@@ -206,13 +206,14 @@ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
+ * Open up a stream for HW test
+ */
+ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+- uint64_t dummy;
++ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -220,15 +221,15 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+ return r;
+
+ ib = &job->ibs[0];
+- dummy = ib->gpu_addr + 1024;
++ addr = amdgpu_bo_gpu_offset(bo);
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = 0x00010000;
+- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+- ib->ptr[ib->length_dw++] = dummy;
++ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++ ib->ptr[ib->length_dw++] = addr;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+@@ -268,13 +269,14 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+ */
+ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+ uint32_t handle,
++ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+- uint64_t dummy;
++ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -282,15 +284,15 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+ return r;
+
+ ib = &job->ibs[0];
+- dummy = ib->gpu_addr + 1024;
++ addr = amdgpu_bo_gpu_offset(bo);
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = 0x00010000;
+- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+- ib->ptr[ib->length_dw++] = dummy;
++ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++ ib->ptr[ib->length_dw++] = addr;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+@@ -327,13 +329,20 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ struct dma_fence *fence = NULL;
++ struct amdgpu_bo *bo = NULL;
+ long r;
+
+- r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
++ r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
++ AMDGPU_GEM_DOMAIN_VRAM,
++ &bo, NULL, NULL);
++ if (r)
++ return r;
++
++ r = uvd_v6_0_enc_get_create_msg(ring, 1, bo, NULL);
+ if (r)
+ goto error;
+
+- r = uvd_v6_0_enc_get_destroy_msg(ring, 1, &fence);
++ r = uvd_v6_0_enc_get_destroy_msg(ring, 1, bo, &fence);
+ if (r)
+ goto error;
+
+@@ -345,6 +354,8 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+
+ error:
+ dma_fence_put(fence);
++ amdgpu_bo_unreserve(bo);
++ amdgpu_bo_unref(&bo);
+ return r;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..1dec99e5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,135 @@
+From d1e49d328cc2bb2be51b267f0a2c3db43d23155f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 18:08:59 -0400
+Subject: [PATCH 4200/4736] drm/amdgpu/uvd7: fix allocation size in enc ring
+ test (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+session info, otherwise the IB test can overwrite
+other memory.
+
+v2: - session info is 128K according to mesa
+ - use the same session info for create and destroy
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Tested-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 33 ++++++++++++++++++---------
+ 1 file changed, 22 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+index 2f3d4e8032d5..8c2b31d4017e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+@@ -214,13 +214,14 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
+ * Open up a stream for HW test
+ */
+ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+- uint64_t dummy;
++ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -228,15 +229,15 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+ return r;
+
+ ib = &job->ibs[0];
+- dummy = ib->gpu_addr + 1024;
++ addr = amdgpu_bo_gpu_offset(bo);
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+- ib->ptr[ib->length_dw++] = dummy;
++ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++ ib->ptr[ib->length_dw++] = addr;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+@@ -275,13 +276,14 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+ * Close up a stream for HW test or if userspace failed to do so
+ */
+ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+- struct dma_fence **fence)
++ struct amdgpu_bo *bo,
++ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+- uint64_t dummy;
++ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -289,15 +291,15 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
+ return r;
+
+ ib = &job->ibs[0];
+- dummy = ib->gpu_addr + 1024;
++ addr = amdgpu_bo_gpu_offset(bo);
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001;
+ ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+- ib->ptr[ib->length_dw++] = dummy;
++ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++ ib->ptr[ib->length_dw++] = addr;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002;
+@@ -334,13 +336,20 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
+ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ struct dma_fence *fence = NULL;
++ struct amdgpu_bo *bo = NULL;
+ long r;
+
+- r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
++ r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
++ AMDGPU_GEM_DOMAIN_VRAM,
++ &bo, NULL, NULL);
++ if (r)
++ return r;
++
++ r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL);
+ if (r)
+ goto error;
+
+- r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &fence);
++ r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence);
+ if (r)
+ goto error;
+
+@@ -352,6 +361,8 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+
+ error:
+ dma_fence_put(fence);
++ amdgpu_bo_unreserve(bo);
++ amdgpu_bo_unref(&bo);
+ return r;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..59365577
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,134 @@
+From 32f8b69dcac7547e2603bb3eb643c3eeeac2ac66 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 18:09:41 -0400
+Subject: [PATCH 4201/4736] drm/amdgpu/vcn: fix allocation size in enc ring
+ test
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+session info, otherwise the IB test can overwrite
+other memory.
+
+- Session info is 128K according to mesa
+- Use the same session info for create and destroy
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Tested-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 35 ++++++++++++++++---------
+ 1 file changed, 23 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 8566a264961f..6b31410a5ff9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -568,13 +568,14 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
+ }
+
+ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+- struct dma_fence **fence)
++ struct amdgpu_bo *bo,
++ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+- uint64_t dummy;
++ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -582,14 +583,14 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
+ return r;
+
+ ib = &job->ibs[0];
+- dummy = ib->gpu_addr + 1024;
++ addr = amdgpu_bo_gpu_offset(bo);
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ ib->ptr[ib->length_dw++] = handle;
+- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+- ib->ptr[ib->length_dw++] = dummy;
++ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++ ib->ptr[ib->length_dw++] = addr;
+ ib->ptr[ib->length_dw++] = 0x0000000b;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+@@ -620,13 +621,14 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
+ }
+
+ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+- struct dma_fence **fence)
++ struct amdgpu_bo *bo,
++ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 16;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+- uint64_t dummy;
++ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -634,14 +636,14 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
+ return r;
+
+ ib = &job->ibs[0];
+- dummy = ib->gpu_addr + 1024;
++ addr = amdgpu_bo_gpu_offset(bo);
+
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001;
+ ib->ptr[ib->length_dw++] = handle;
+- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+- ib->ptr[ib->length_dw++] = dummy;
++ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++ ib->ptr[ib->length_dw++] = addr;
+ ib->ptr[ib->length_dw++] = 0x0000000b;
+
+ ib->ptr[ib->length_dw++] = 0x00000014;
+@@ -674,13 +676,20 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
+ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ struct dma_fence *fence = NULL;
++ struct amdgpu_bo *bo = NULL;
+ long r;
+
+- r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
++ r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
++ AMDGPU_GEM_DOMAIN_VRAM,
++ &bo, NULL, NULL);
++ if (r)
++ return r;
++
++ r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
+ if (r)
+ goto error;
+
+- r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
++ r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
+ if (r)
+ goto error;
+
+@@ -692,6 +701,8 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+
+ error:
+ dma_fence_put(fence);
++ amdgpu_bo_unreserve(bo);
++ amdgpu_bo_unref(&bo);
+ return r;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch
new file mode 100644
index 00000000..7986c5eb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch
@@ -0,0 +1,69 @@
+From 294d2d513a5497a9d67c88257830a27105f49de1 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Wed, 16 Oct 2019 14:28:33 +0800
+Subject: [PATCH 4202/4736] drm/amdgpu/powerplay: implement interface
+ pp_power_profile_mode
+
+implement get_power_profile_mode for getting power profile mode status.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 34 ++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index fa314c275a82..953e347633ec 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -640,6 +640,39 @@ static int renoir_set_watermarks_table(
+ return ret;
+ }
+
++static int renoir_get_power_profile_mode(struct smu_context *smu,
++ char *buf)
++{
++ static const char *profile_name[] = {
++ "BOOTUP_DEFAULT",
++ "3D_FULL_SCREEN",
++ "POWER_SAVING",
++ "VIDEO",
++ "VR",
++ "COMPUTE",
++ "CUSTOM"};
++ uint32_t i, size = 0;
++ int16_t workload_type = 0;
++
++ if (!smu->pm_enabled || !buf)
++ return -EINVAL;
++
++ for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
++ /*
++ * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
++ * Not all profile modes are supported on arcturus.
++ */
++ workload_type = smu_workload_get_type(smu, i);
++ if (workload_type < 0)
++ continue;
++
++ size += sprintf(buf + size, "%2d %14s%s\n",
++ i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
++ }
++
++ return size;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_smu_msg_index = renoir_get_smu_msg_index,
+ .get_smu_table_index = renoir_get_smu_table_index,
+@@ -658,6 +691,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .set_performance_level = renoir_set_performance_level,
+ .get_dpm_clock_table = renoir_get_dpm_clock_table,
+ .set_watermarks_table = renoir_set_watermarks_table,
++ .get_power_profile_mode = renoir_get_power_profile_mode,
+ };
+
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch
new file mode 100644
index 00000000..08ee2dcb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch
@@ -0,0 +1,50 @@
+From a5c4f7383c296cbd8b46b997b5f10fcaa0d93f1c Mon Sep 17 00:00:00 2001
+From: Ahzo <Ahzo@tutanota.com>
+Date: Fri, 11 Oct 2019 19:55:03 +0200
+Subject: [PATCH 4203/4736] drm/amd/display: add NULL checks for clock manager
+ pointer
+
+This fixes kernel NULL pointer dereferences on shutdown:
+RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu]
+RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu]
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Ahzo <Ahzo@tutanota.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++--
+ 2 files changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 5474e2525e0c..5ce5db7818e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1528,7 +1528,7 @@ static enum dc_status enable_link_dp(
+
+ pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
+ link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+- if (!apply_seamless_boot_optimization)
++ if (state->clk_mgr && !apply_seamless_boot_optimization)
+ state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
+
+ dp_enable_link_phy(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 27542c22fa55..d1e14393a0f0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1158,8 +1158,9 @@ static void build_audio_output(
+ }
+ }
+
+- if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
+- pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
++ if (state->clk_mgr &&
++ (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
++ pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
+ audio_output->pll_info.dp_dto_source_clock_in_khz =
+ state->clk_mgr->funcs->get_dp_ref_clk_frequency(
+ state->clk_mgr);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch
new file mode 100644
index 00000000..6b96882c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch
@@ -0,0 +1,34 @@
+From 998f52b4faf6292c926fa83719fb4fa925e00ee0 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 18 Oct 2019 18:46:38 +0800
+Subject: [PATCH 4204/4736] drm/amdgpu/psp11: wait for sOS ready for ring
+ creation
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index f5bc9c176e7b..4f382bdd5f01 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -469,6 +469,14 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
+ 0x80000000, 0x8000FFFF, false);
+
+ } else {
++ /* Wait for sOS ready for ring creation */
++ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
++ 0x80000000, 0x80000000, false);
++ if (ret) {
++ DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
++ return ret;
++ }
++
+ /* Write low address of the ring to C2PMSG_69 */
+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4205-drm-amdgpu-psp11-fix-typo-in-comment.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4205-drm-amdgpu-psp11-fix-typo-in-comment.patch
new file mode 100644
index 00000000..35555a03
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4205-drm-amdgpu-psp11-fix-typo-in-comment.patch
@@ -0,0 +1,27 @@
+From 1ac72bb28d442ed2def64b9b9d1b63e1a9674c90 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 18 Oct 2019 18:47:20 +0800
+Subject: [PATCH 4205/4736] drm/amdgpu/psp11: fix typo in comment
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 4f382bdd5f01..f2f67af65b94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -242,7 +242,7 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
+ /* Copy PSP KDB binary to memory */
+ memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
+
+- /* Provide the sys driver to bootloader */
++ /* Provide the PSP KDB to bootloader */
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
+ (uint32_t)(psp->fw_pri_mc_addr >> 20));
+ psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch
new file mode 100644
index 00000000..941c710f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch
@@ -0,0 +1,55 @@
+From e91ec6627e027d48956b9dac7c09d160d7064977 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 13:10:03 +0800
+Subject: [PATCH 4206/4736] drm/amdgpu: update amdgpu_discovery to handle
+ revision
+
+update amdgpu_discovery to get IP revision.
+
+Change-Id: I7a26f3b70da3b53771b5cc24e40a048d8f7ec005
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 +++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 +-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+index 71198c5318e1..ddd8364102a2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+@@ -333,7 +333,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
+ }
+
+ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+- int *major, int *minor)
++ int *major, int *minor, int *revision)
+ {
+ struct binary_header *bhdr;
+ struct ip_discovery_header *ihdr;
+@@ -369,6 +369,8 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+ *major = ip->major;
+ if (minor)
+ *minor = ip->minor;
++ if (revision)
++ *revision = ip->revision;
+ return 0;
+ }
+ ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+index 5a6693d7d269..ba78e15d9b05 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+@@ -30,7 +30,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev);
+ void amdgpu_discovery_fini(struct amdgpu_device *adev);
+ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
+ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+- int *major, int *minor);
++ int *major, int *minor, int *revision);
+ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
+
+ #endif /* __AMDGPU_DISCOVERY__ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch
new file mode 100644
index 00000000..3da523f2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch
@@ -0,0 +1,101 @@
+From 127264c9ea12a42fbb31f94eecb20d7917f73efe Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 13:33:50 +0800
+Subject: [PATCH 4207/4736] drm/amdgpu: add a generic fb accessing helper
+ function(v3)
+
+add a generic helper function for accessing framebuffer via MMIO
+
+Change-Id: I075e138083e5aef57485a09fe44f27c34ff483a3
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 30 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 12 +-------
+ 3 files changed, 33 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index e4172f9bece6..6ed17115a56d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1029,6 +1029,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ void amdgpu_device_fini(struct amdgpu_device *adev);
+ int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
+
++void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
++ uint32_t *buf, size_t size, bool write);
+ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
+ uint32_t acc_flags);
+ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 46723a10d98a..634b581f96b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -153,6 +153,36 @@ bool amdgpu_device_is_px(struct drm_device *dev)
+ return false;
+ }
+
++/**
++ * VRAM access helper functions.
++ *
++ * amdgpu_device_vram_access - read/write a buffer in vram
++ *
++ * @adev: amdgpu_device pointer
++ * @pos: offset of the buffer in vram
++ * @buf: virtual address of the buffer in system memory
++ * @size: read/write size, sizeof(@buf) must > @size
++ * @write: true - write to vram, otherwise - read from vram
++ */
++void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
++ uint32_t *buf, size_t size, bool write)
++{
++ uint64_t last;
++ unsigned long flags;
++
++ last = size - 4;
++ for (last += pos; pos <= last; pos += 4) {
++ spin_lock_irqsave(&adev->mmio_idx_lock, flags);
++ WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
++ WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
++ if (write)
++ WREG32_NO_KIQ(mmMM_DATA, *buf++);
++ else
++ *buf++ = RREG32_NO_KIQ(mmMM_DATA);
++ spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
++ }
++}
++
+ /*
+ * MMIO register access helper functions.
+ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+index ddd8364102a2..f95092741c38 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+@@ -134,20 +134,10 @@ static int hw_id_map[MAX_HWIP] = {
+
+ static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
+ {
+- uint32_t *p = (uint32_t *)binary;
+ uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
+ uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
+- unsigned long flags;
+-
+- while (pos < vram_size) {
+- spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+- WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
+- WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
+- *p++ = RREG32_NO_KIQ(mmMM_DATA);
+- spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+- pos += 4;
+- }
+
++ amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, DISCOVERY_TMR_SIZE, false);
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch
new file mode 100644
index 00000000..3ff1fa42
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch
@@ -0,0 +1,83 @@
+From bb67d025b4fb92d3be1356c7ccb43d89fab544c8 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:16:42 +0800
+Subject: [PATCH 4208/4736] drm/amdgpu: introduce psp_v11_0_is_sos_alive
+ interface(v2)
+
+introduce psp_v11_0_is_sos_alive func for common use.
+
+Change-Id: I5ab83987da84fe19fce93f35ae385c0d8ae3c39e
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 22 +++++++++++++---------
+ 1 file changed, 13 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index f2f67af65b94..b52af59079b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -214,18 +214,26 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ return err;
+ }
+
++static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
++{
++ struct amdgpu_device *adev = psp->adev;
++ uint32_t sol_reg;
++
++ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
++
++ return sol_reg != 0x0;
++}
++
+ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
+ {
+ int ret;
+ uint32_t psp_gfxdrv_command_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+- uint32_t sol_reg;
+
+ /* Check tOS sign of life register to confirm sys driver and sOS
+ * are already been loaded.
+ */
+- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+- if (sol_reg) {
++ if (psp_v11_0_is_sos_alive(psp)) {
+ psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+ dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
+ return 0;
+@@ -261,13 +269,11 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
+ int ret;
+ uint32_t psp_gfxdrv_command_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+- uint32_t sol_reg;
+
+ /* Check sOS sign of life register to confirm sys driver and sOS
+ * are already been loaded.
+ */
+- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+- if (sol_reg) {
++ if (psp_v11_0_is_sos_alive(psp)) {
+ psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+ dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
+ return 0;
+@@ -305,13 +311,11 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
+ int ret;
+ unsigned int psp_gfxdrv_command_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+- uint32_t sol_reg;
+
+ /* Check sOS sign of life register to confirm sys driver and sOS
+ * are already been loaded.
+ */
+- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+- if (sol_reg)
++ if (psp_v11_0_is_sos_alive(psp))
+ return 0;
+
+ /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch
new file mode 100644
index 00000000..2114c913
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch
@@ -0,0 +1,64 @@
+From dafc724cbbe01c1a41e14a948dd5165c839e8e5f Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Tue, 8 Oct 2019 13:57:28 +0800
+Subject: [PATCH 4209/4736] drm/amdgpu: update atomfirmware header with memory
+ training related members(v3)
+
+add new vram_reserve_block structure and atomfirmware_internal_constants enumeration
+
+Change-Id: I1187d8916b2ad04764e4fdad6f56b72e71adae27
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/include/atomfirmware.h | 27 +++++++++++++++++-----
+ 1 file changed, 21 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
+index 73e31c377402..4e5eb4c8097e 100644
+--- a/drivers/gpu/drm/amd/include/atomfirmware.h
++++ b/drivers/gpu/drm/amd/include/atomfirmware.h
+@@ -492,12 +492,13 @@ struct atom_firmware_info_v3_1
+ /* Total 32bit cap indication */
+ enum atombios_firmware_capability
+ {
+- ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
+- ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
+- ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
+- ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
+- ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
+- ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
++ ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
++ ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
++ ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
++ ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
++ ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
++ ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
++ ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
+ };
+
+ enum atom_cooling_solution_id{
+@@ -671,6 +672,20 @@ struct vram_usagebyfirmware_v2_1
+ uint16_t used_by_driver_in_kb;
+ };
+
++/* This is part of vram_usagebyfirmware_v2_1 */
++struct vram_reserve_block
++{
++ uint32_t start_address_in_kb;
++ uint16_t used_by_firmware_in_kb;
++ uint16_t used_by_driver_in_kb;
++};
++
++/* Definitions for constance */
++enum atomfirmware_internal_constants
++{
++ ONE_KiB = 0x400,
++ ONE_MiB = 0x100000,
++};
+
+ /*
+ ***************************************************************************
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch
new file mode 100644
index 00000000..042e3e58
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch
@@ -0,0 +1,227 @@
+From 99f25c59abada45c37619e5681b141bec1fb28db Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 13:43:31 +0800
+Subject: [PATCH 4210/4736] drm/amdgpu/atomfirmware: add memory training
+ related helper functions(v3)
+
+parse firmware to get memory training capability and fb location.
+
+Change-Id: I8515203c09a207674b1721a8eac453b407394503
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 5 +
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 136 ++++++++++++++++++
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 1 +
+ 4 files changed, 150 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 6ed17115a56d..8c5c1833aca7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -296,6 +296,9 @@ struct amdgpu_ip_block_version {
+ const struct amd_ip_funcs *funcs;
+ };
+
++#define HW_REV(_Major, _Minor, _Rev) \
++ ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
++
+ struct amdgpu_ip_block {
+ struct amdgpu_ip_block_status status;
+ const struct amdgpu_ip_block_version *version;
+@@ -647,6 +650,11 @@ struct amdgpu_fw_vram_usage {
+ u64 size;
+ struct amdgpu_bo *reserved_bo;
+ void *va;
++
++ /* Offset on the top of VRAM, used as c2p write buffer.
++ */
++ u64 mem_train_fb_loc;
++ bool mem_train_support;
+ };
+
+ /*
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+index e02781b37e73..a0d582a1e8c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+@@ -2038,6 +2038,11 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
+ if (adev->is_atom_fw) {
+ amdgpu_atomfirmware_scratch_regs_init(adev);
+ amdgpu_atomfirmware_allocate_fb_scratch(adev);
++ ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
++ if (ret) {
++ DRM_ERROR("Failed to get mem train fb location.\n");
++ return ret;
++ }
+ } else {
+ amdgpu_atombios_scratch_regs_init(adev);
+ amdgpu_atombios_allocate_fb_scratch(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+index a253a554f41f..37ab291217f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+@@ -27,6 +27,7 @@
+ #include "amdgpu_atomfirmware.h"
+ #include "atom.h"
+ #include "atombios.h"
++#include "soc15_hw_ip.h"
+
+ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
+ {
+@@ -462,3 +463,138 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
+ }
+ return -EINVAL;
+ }
++
++/*
++ * Check if VBIOS supports GDDR6 training data save/restore
++ */
++static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
++{
++ uint16_t data_offset;
++ int index;
++
++ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
++ firmwareinfo);
++ if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
++ NULL, NULL, &data_offset)) {
++ struct atom_firmware_info_v3_1 *firmware_info =
++ (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
++ data_offset);
++
++ DRM_DEBUG("atom firmware capability:0x%08x.\n",
++ le32_to_cpu(firmware_info->firmware_capability));
++
++ if (le32_to_cpu(firmware_info->firmware_capability) &
++ ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
++ return true;
++ }
++
++ return false;
++}
++
++static int gddr6_mem_train_support(struct amdgpu_device *adev)
++{
++ int ret;
++ uint32_t major, minor, revision, hw_v;
++
++ if (gddr6_mem_train_vbios_support(adev)) {
++ amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
++ hw_v = HW_REV(major, minor, revision);
++ /*
++ * treat 0 revision as a special case since register for MP0 and MMHUB is missing
++ * for some Navi10 A0, preventing driver from discovering the hwip information since
++ * none of the functions will be initialized, it should not cause any problems
++ */
++ switch (hw_v) {
++ case HW_REV(11, 0, 0):
++ case HW_REV(11, 0, 5):
++ ret = 1;
++ break;
++ default:
++ DRM_ERROR("memory training vbios supports but psp hw(%08x)"
++ " doesn't support!\n", hw_v);
++ ret = -1;
++ break;
++ }
++ } else {
++ ret = 0;
++ hw_v = -1;
++ }
++
++
++ DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
++ return ret;
++}
++
++int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev)
++{
++ struct atom_context *ctx = adev->mode_info.atom_context;
++ unsigned char *bios = ctx->bios;
++ struct vram_reserve_block *reserved_block;
++ int index, block_number;
++ uint8_t frev, crev;
++ uint16_t data_offset, size;
++ uint32_t start_address_in_kb;
++ uint64_t offset;
++ int ret;
++
++ adev->fw_vram_usage.mem_train_support = false;
++
++ if (adev->asic_type != CHIP_NAVI10 &&
++ adev->asic_type != CHIP_NAVI14)
++ return 0;
++
++ if (amdgpu_sriov_vf(adev))
++ return 0;
++
++ ret = gddr6_mem_train_support(adev);
++ if (ret == -1)
++ return -EINVAL;
++ else if (ret == 0)
++ return 0;
++
++ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
++ vram_usagebyfirmware);
++ ret = amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev,
++ &data_offset);
++ if (ret == 0) {
++ DRM_ERROR("parse data header failed.\n");
++ return -EINVAL;
++ }
++
++ DRM_DEBUG("atom firmware common table header size:0x%04x, frev:0x%02x,"
++ " crev:0x%02x, data_offset:0x%04x.\n", size, frev, crev, data_offset);
++ /* only support 2.1+ */
++ if (((uint16_t)frev << 8 | crev) < 0x0201) {
++ DRM_ERROR("frev:0x%02x, crev:0x%02x < 2.1 !\n", frev, crev);
++ return -EINVAL;
++ }
++
++ reserved_block = (struct vram_reserve_block *)
++ (bios + data_offset + sizeof(struct atom_common_table_header));
++ block_number = ((unsigned int)size - sizeof(struct atom_common_table_header))
++ / sizeof(struct vram_reserve_block);
++ reserved_block += (block_number > 0) ? block_number-1 : 0;
++ DRM_DEBUG("block_number:0x%04x, last block: 0x%08xkb sz, %dkb fw, %dkb drv.\n",
++ block_number,
++ le32_to_cpu(reserved_block->start_address_in_kb),
++ le16_to_cpu(reserved_block->used_by_firmware_in_kb),
++ le16_to_cpu(reserved_block->used_by_driver_in_kb));
++ if (reserved_block->used_by_firmware_in_kb > 0) {
++ start_address_in_kb = le32_to_cpu(reserved_block->start_address_in_kb);
++ offset = (uint64_t)start_address_in_kb * ONE_KiB;
++ if ((offset & (ONE_MiB - 1)) < (4 * ONE_KiB + 1) ) {
++ offset -= ONE_MiB;
++ }
++
++ offset &= ~(ONE_MiB - 1);
++ adev->fw_vram_usage.mem_train_fb_loc = offset;
++ adev->fw_vram_usage.mem_train_support = true;
++ DRM_DEBUG("mem_train_fb_loc:0x%09llx.\n", offset);
++ ret = 0;
++ } else {
++ DRM_ERROR("used_by_firmware_in_kb is 0!\n");
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+index 53449fc7baf4..f871af5ea6f3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+@@ -31,6 +31,7 @@ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ int *vram_width, int *vram_type, int *vram_vendor);
++int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
+ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch
new file mode 100644
index 00000000..9a3cf1d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch
@@ -0,0 +1,157 @@
+From e91173d7f1aa3ae91424e81e73e50072c688c522 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:07:00 +0800
+Subject: [PATCH 4211/4736] drm/amdgpu: add psp memory training callbacks and
+ macro
+
+add interface for memory training.
+
+Change-Id: I20f5e3dc574d87bc6d261db69d5717bd4db73ebc
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 ++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 55 +++++++++++++++++++++++++
+ 2 files changed, 73 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index e4f4ae99280a..64db0c8cee4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -88,6 +88,17 @@ static int psp_sw_init(void *handle)
+ return ret;
+ }
+
++ ret = psp_mem_training_init(psp);
++ if (ret) {
++ DRM_ERROR("Failed to initliaze memory training!\n");
++ return ret;
++ }
++ ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
++ if (ret) {
++ DRM_ERROR("Failed to process memory training!\n");
++ return ret;
++ }
++
+ return 0;
+ }
+
+@@ -95,6 +106,7 @@ static int psp_sw_fini(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
++ psp_mem_training_fini(&adev->psp);
+ release_firmware(adev->psp.sos_fw);
+ adev->psp.sos_fw = NULL;
+ release_firmware(adev->psp.asd_fw);
+@@ -1610,6 +1622,12 @@ static int psp_resume(void *handle)
+
+ DRM_INFO("PSP is resuming...\n");
+
++ ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
++ if (ret) {
++ DRM_ERROR("Failed to process memory training!\n");
++ return ret;
++ }
++
+ mutex_lock(&adev->firmware.mutex);
+
+ ret = psp_hw_start(psp);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 7dd9ae7dbbe4..09c5474ebcc3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -49,6 +49,8 @@ enum psp_bootloader_cmd {
+ PSP_BL__LOAD_SYSDRV = 0x10000,
+ PSP_BL__LOAD_SOSDRV = 0x20000,
+ PSP_BL__LOAD_KEY_DATABASE = 0x80000,
++ PSP_BL__DRAM_LONG_TRAIN = 0x100000,
++ PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
+ };
+
+ enum psp_ring_type
+@@ -111,6 +113,9 @@ struct psp_funcs
+ struct ta_ras_trigger_error_input *info);
+ int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
+ int (*rlc_autoload_start)(struct psp_context *psp);
++ int (*mem_training_init)(struct psp_context *psp);
++ void (*mem_training_fini)(struct psp_context *psp);
++ int (*mem_training)(struct psp_context *psp, uint32_t ops);
+ };
+
+ #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
+@@ -161,6 +166,49 @@ struct psp_dtm_context {
+ void *dtm_shared_buf;
+ };
+
++#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
++#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
++#define GDDR6_MEM_TRAINING_OFFSET 0x8000
++
++enum psp_memory_training_init_flag {
++ PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
++ PSP_MEM_TRAIN_SUPPORT = 0x1,
++ PSP_MEM_TRAIN_INIT_FAILED = 0x2,
++ PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
++ PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
++};
++
++enum psp_memory_training_ops {
++ PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
++ PSP_MEM_TRAIN_SAVE = 0x2,
++ PSP_MEM_TRAIN_RESTORE = 0x4,
++ PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
++ PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
++ PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
++};
++
++struct psp_memory_training_context {
++ /*training data size*/
++ u64 train_data_size;
++ /*
++ * sys_cache
++ * cpu virtual address
++ * system memory buffer that used to store the training data.
++ */
++ void *sys_cache;
++
++ /*vram offset of the p2c training data*/
++ u64 p2c_train_data_offset;
++ struct amdgpu_bo *p2c_bo;
++
++ /*vram offset of the c2p training data*/
++ u64 c2p_train_data_offset;
++ struct amdgpu_bo *c2p_bo;
++
++ enum psp_memory_training_init_flag init;
++ u32 training_cnt;
++};
++
+ struct psp_context
+ {
+ struct amdgpu_device *adev;
+@@ -239,6 +287,7 @@ struct psp_context
+ struct psp_hdcp_context hdcp_context;
+ struct psp_dtm_context dtm_context;
+ struct mutex mutex;
++ struct psp_memory_training_context mem_train_ctx;
+ };
+
+ struct amdgpu_psp_funcs {
+@@ -281,6 +330,12 @@ struct amdgpu_psp_funcs {
+ (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
+ #define psp_rlc_autoload(psp) \
+ ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
++#define psp_mem_training_init(psp) \
++ ((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0)
++#define psp_mem_training_fini(psp) \
++ ((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0)
++#define psp_mem_training(psp, ops) \
++ ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
+
+ #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch
new file mode 100644
index 00000000..4c224e55
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch
@@ -0,0 +1,135 @@
+From eafe58cb56a6d67ea90e24de16257fdfab5a7e76 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:28:17 +0800
+Subject: [PATCH 4212/4736] drm/amdgpu: reserve vram for memory training(v4)
+
+memory training using specific fixed vram segment, reserve these
+segments before anyone may allocate it.
+
+Change-Id: I9a37cd4f61b04ba1ca041a752bc16901488ac341
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 91 +++++++++++++++++++++++++
+ 1 file changed, 91 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 0c1af24f8bc0..968595138b32 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1975,6 +1975,88 @@ static void amdgpu_ssg_fini(struct amdgpu_device *adev)
+ }
+ #endif
+
++/*
++ * Memoy training reservation functions
++ */
++
++/**
++ * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * free memory training reserved vram if it has been reserved.
++ */
++static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
++{
++ struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
++
++ ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
++ amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
++ ctx->c2p_bo = NULL;
++
++ amdgpu_bo_free_kernel(&ctx->p2c_bo, NULL, NULL);
++ ctx->p2c_bo = NULL;
++
++ return 0;
++}
++
++/**
++ * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * create bo vram reservation from memory training.
++ */
++static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
++{
++ int ret;
++ struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
++
++ memset(ctx, 0, sizeof(*ctx));
++ if (!adev->fw_vram_usage.mem_train_support) {
++ DRM_DEBUG("memory training does not support!\n");
++ return 0;
++ }
++
++ ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
++ ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
++ ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
++
++ DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
++ ctx->train_data_size,
++ ctx->p2c_train_data_offset,
++ ctx->c2p_train_data_offset);
++
++ ret = amdgpu_bo_create_kernel_at(adev,
++ ctx->p2c_train_data_offset,
++ ctx->train_data_size,
++ AMDGPU_GEM_DOMAIN_VRAM,
++ &ctx->p2c_bo,
++ NULL);
++ if (ret) {
++ DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
++ goto Err_out;
++ }
++
++ ret = amdgpu_bo_create_kernel_at(adev,
++ ctx->c2p_train_data_offset,
++ ctx->train_data_size,
++ AMDGPU_GEM_DOMAIN_VRAM,
++ &ctx->c2p_bo,
++ NULL);
++ if (ret) {
++ DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
++ goto Err_out;
++ }
++
++ ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
++ return 0;
++
++Err_out:
++ amdgpu_ttm_training_reserve_vram_fini(adev);
++ return ret;
++}
++
+ /**
+ * amdgpu_ttm_init - Init the memory management (ttm) as well as various
+ * gtt/vram related fields.
+@@ -2053,6 +2135,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ return r;
+ }
+
++ /*
++ *The reserved vram for memory training must be pinned to the specified
++ *place on the VRAM, so reserve it early.
++ */
++ r = amdgpu_ttm_training_reserve_vram_init(adev);
++ if (r)
++ return r;
++
+ /* allocate memory as required for VGA
+ * This is used for VGA emulation and pre-OS scanout buffers to
+ * avoid display artifacts while transitioning between pre-OS
+@@ -2160,6 +2250,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
+ return;
+
+ amdgpu_ttm_debugfs_fini(adev);
++ amdgpu_ttm_training_reserve_vram_fini(adev);
+ amdgpu_ttm_fw_reserve_vram_fini(adev);
+ if (adev->mman.aper_base_kaddr)
+ iounmap(adev->mman.aper_base_kaddr);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch
new file mode 100644
index 00000000..b6a6644f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch
@@ -0,0 +1,246 @@
+From 7759546a09a7816345f83d60f9c04ec7ecda191a Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:29:33 +0800
+Subject: [PATCH 4213/4736] drm/amdgpu/psp: add psp memory training
+ implementation(v3)
+
+add memory training implementation code to save resume time.
+
+Change-Id: Ib74fec65eb4db1f7343d5ff54e9169e3ade1a882
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 ++
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 161 ++++++++++++++++++++++++
+ 3 files changed, 171 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 8c5c1833aca7..f1f258a2790a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -156,6 +156,7 @@ extern char *amdgpu_disable_cu;
+ extern char *amdgpu_virtual_display;
+ extern uint amdgpu_pp_feature_mask;
+ extern int amdgpu_ssg_enabled;
++extern uint amdgpu_force_long_training;
+ extern int amdgpu_job_hang_limit;
+ extern int amdgpu_lbpw;
+ extern int amdgpu_compute_multipipe;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 5ab426726849..699cab407158 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -129,6 +129,7 @@ char *amdgpu_disable_cu = NULL;
+ char *amdgpu_virtual_display = NULL;
+ /* OverDrive(bit 14) disabled by default*/
+ uint amdgpu_pp_feature_mask = 0xffffbfff;
++uint amdgpu_force_long_training = 0;
+ int amdgpu_job_hang_limit = 0;
+ int amdgpu_lbpw = -1;
+ int amdgpu_compute_multipipe = -1;
+@@ -403,6 +404,14 @@ module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
+ MODULE_PARM_DESC(ssg, "SSG support (1 = enable, 0 = disable (default))");
+ module_param_named(ssg, amdgpu_ssg_enabled, int, 0444);
+
++/**
++ * DOC: forcelongtraining (uint)
++ * Force long memory training in resume.
++ * The default is zero, indicates short training in resume.
++ */
++MODULE_PARM_DESC(forcelongtraining, "force memory long training");
++module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
++
+ /**
+ * DOC: pcie_gen_cap (uint)
+ * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index b52af59079b7..0875ece1bea2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
+ #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
+ #define mmSDMA0_UCODE_ADDR_NV10 0x5880
+ #define mmSDMA0_UCODE_DATA_NV10 0x5881
++/* memory training timeout define */
++#define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
+
+ #define VEGA20_BL_VERSION_VAR_NEW 0xA1
+
+@@ -918,6 +920,162 @@ static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
+ return psp_rlc_autoload_start(psp);
+ }
+
++static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
++{
++ int ret;
++ int i;
++ uint32_t data_32;
++ int max_wait;
++ struct amdgpu_device *adev = psp->adev;
++
++ data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
++
++ max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
++ for (i = 0; i < max_wait; i++) {
++ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
++ 0x80000000, 0x80000000, false);
++ if (ret == 0)
++ break;
++ }
++ if (i < max_wait)
++ ret = 0;
++ else
++ ret = -ETIME;
++
++ DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
++ (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
++ (ret == 0) ? "succeed" : "failed",
++ i, adev->usec_timeout/1000);
++ return ret;
++}
++
++static void psp_v11_0_memory_training_fini(struct psp_context *psp)
++{
++ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
++
++ ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
++ kfree(ctx->sys_cache);
++ ctx->sys_cache = NULL;
++}
++
++static int psp_v11_0_memory_training_init(struct psp_context *psp)
++{
++ int ret;
++ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
++
++ if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
++ DRM_DEBUG("memory training is not supported!\n");
++ return 0;
++ }
++
++ ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
++ if (ctx->sys_cache == NULL) {
++ DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
++ ret = -ENOMEM;
++ goto Err_out;
++ }
++
++ DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
++ ctx->train_data_size,
++ ctx->p2c_train_data_offset,
++ ctx->c2p_train_data_offset);
++ ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
++ return 0;
++
++Err_out:
++ psp_v11_0_memory_training_fini(psp);
++ return ret;
++}
++
++/*
++ * save and restore proces
++ */
++static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
++{
++ int ret;
++ uint32_t p2c_header[4];
++ struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
++ uint32_t *pcache = (uint32_t*)ctx->sys_cache;
++
++ if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
++ DRM_DEBUG("Memory training is not supported.\n");
++ return 0;
++ } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
++ DRM_ERROR("Memory training initialization failure.\n");
++ return -EINVAL;
++ }
++
++ if (psp_v11_0_is_sos_alive(psp)) {
++ DRM_DEBUG("SOS is alive, skip memory training.\n");
++ return 0;
++ }
++
++ amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
++ DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
++ pcache[0], pcache[1], pcache[2], pcache[3],
++ p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
++
++ if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
++ DRM_DEBUG("Short training depends on restore.\n");
++ ops |= PSP_MEM_TRAIN_RESTORE;
++ }
++
++ if ((ops & PSP_MEM_TRAIN_RESTORE) &&
++ pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
++ DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
++ ops |= PSP_MEM_TRAIN_SAVE;
++ }
++
++ if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
++ !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
++ pcache[3] == p2c_header[3])) {
++ DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
++ ops |= PSP_MEM_TRAIN_SAVE;
++ }
++
++ if ((ops & PSP_MEM_TRAIN_SAVE) &&
++ p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
++ DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
++ ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
++ }
++
++ if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
++ ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
++ ops |= PSP_MEM_TRAIN_SAVE;
++ }
++
++ DRM_DEBUG("Memory training ops:%x.\n", ops);
++
++ if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
++ ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
++ if (ret) {
++ DRM_ERROR("Send long training msg failed.\n");
++ return ret;
++ }
++ }
++
++ if (ops & PSP_MEM_TRAIN_SAVE) {
++ amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
++ }
++
++ if (ops & PSP_MEM_TRAIN_RESTORE) {
++ amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
++ }
++
++ if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
++ ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
++ PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
++ if (ret) {
++ DRM_ERROR("send training msg failed.\n");
++ return ret;
++ }
++ }
++ ctx->training_cnt++;
++ return 0;
++}
++
+ static const struct psp_funcs psp_v11_0_funcs = {
+ .init_microcode = psp_v11_0_init_microcode,
+ .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
+@@ -938,6 +1096,9 @@ static const struct psp_funcs psp_v11_0_funcs = {
+ .ras_trigger_error = psp_v11_0_ras_trigger_error,
+ .ras_cure_posion = psp_v11_0_ras_cure_posion,
+ .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
++ .mem_training_init = psp_v11_0_memory_training_init,
++ .mem_training_fini = psp_v11_0_memory_training_fini,
++ .mem_training = psp_v11_0_memory_training,
+ };
+
+ void psp_v11_0_set_psp_funcs(struct psp_context *psp)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch
new file mode 100644
index 00000000..9a278ecf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch
@@ -0,0 +1,114 @@
+From 650f26bbe12a83eb29debdd57b36bd20fde749e1 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Wed, 16 Oct 2019 10:51:32 +0800
+Subject: [PATCH 4214/4736] drm/amdgpu: fix amdgpu trace event print string
+ format error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+the trace event print string format error.
+(use integer type to handle string)
+
+before:
+amdgpu_test_kev-1556 [002] 138.508781: amdgpu_cs_ioctl:
+sched_job=8, timeline=gfx_0.0.0, context=177, seqno=1,
+ring_name=ffff94d01c207bf0, num_ibs=2
+
+after:
+amdgpu_test_kev-1506 [004] 370.703783: amdgpu_cs_ioctl:
+sched_job=12, timeline=gfx_0.0.0, context=234, seqno=2,
+ring_name=gfx_0.0.0, num_ibs=1
+
+change trace event list:
+1.amdgpu_cs_ioctl
+2.amdgpu_sched_run_job
+3.amdgpu_ib_pipe_sync
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+index e9feb5a8fb9d..61d4bfa2f6cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+@@ -172,7 +172,7 @@ TRACE_EVENT(amdgpu_cs_ioctl,
+ __field(unsigned int, context)
+ __field(unsigned int, seqno)
+ __field(struct dma_fence *, fence)
+- __field(char *, ring_name)
++ __string(ring, to_amdgpu_ring(job->base.sched)->name)
+ __field(u32, num_ibs)
+ ),
+
+@@ -181,12 +181,12 @@ TRACE_EVENT(amdgpu_cs_ioctl,
+ __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
+ __entry->context = job->base.s_fence->finished.context;
+ __entry->seqno = job->base.s_fence->finished.seqno;
+- __entry->ring_name = to_amdgpu_ring(job->base.sched)->name;
++ __assign_str(ring, to_amdgpu_ring(job->base.sched)->name)
+ __entry->num_ibs = job->num_ibs;
+ ),
+ TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
+ __entry->sched_job_id, __get_str(timeline), __entry->context,
+- __entry->seqno, __entry->ring_name, __entry->num_ibs)
++ __entry->seqno, __get_str(ring), __entry->num_ibs)
+ );
+
+ TRACE_EVENT(amdgpu_sched_run_job,
+@@ -197,7 +197,7 @@ TRACE_EVENT(amdgpu_sched_run_job,
+ __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
+ __field(unsigned int, context)
+ __field(unsigned int, seqno)
+- __field(char *, ring_name)
++ __string(ring, to_amdgpu_ring(job->base.sched)->name)
+ __field(u32, num_ibs)
+ ),
+
+@@ -206,12 +206,12 @@ TRACE_EVENT(amdgpu_sched_run_job,
+ __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
+ __entry->context = job->base.s_fence->finished.context;
+ __entry->seqno = job->base.s_fence->finished.seqno;
+- __entry->ring_name = to_amdgpu_ring(job->base.sched)->name;
++ __assign_str(ring, to_amdgpu_ring(job->base.sched)->name)
+ __entry->num_ibs = job->num_ibs;
+ ),
+ TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
+ __entry->sched_job_id, __get_str(timeline), __entry->context,
+- __entry->seqno, __entry->ring_name, __entry->num_ibs)
++ __entry->seqno, __get_str(ring), __entry->num_ibs)
+ );
+
+
+@@ -475,7 +475,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
+ TP_PROTO(struct amdgpu_job *sched_job, struct dma_fence *fence),
+ TP_ARGS(sched_job, fence),
+ TP_STRUCT__entry(
+- __field(const char *,name)
++ __string(ring, sched_job->base.sched->name);
+ __field(uint64_t, id)
+ __field(struct dma_fence *, fence)
+ __field(uint64_t, ctx)
+@@ -483,14 +483,14 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
+ ),
+
+ TP_fast_assign(
+- __entry->name = sched_job->base.sched->name;
++ __assign_str(ring, sched_job->base.sched->name)
+ __entry->id = sched_job->base.id;
+ __entry->fence = fence;
+ __entry->ctx = fence->context;
+ __entry->seqno = fence->seqno;
+ ),
+ TP_printk("job ring=%s, id=%llu, need pipe sync to fence=%p, context=%llu, seq=%u",
+- __entry->name, __entry->id,
++ __get_str(ring), __entry->id,
+ __entry->fence, __entry->ctx,
+ __entry->seqno)
+ );
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch
new file mode 100644
index 00000000..d628013a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch
@@ -0,0 +1,121 @@
+From 18e07e3bc6419d1bb47aed0d7139d360982ca394 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Wed, 16 Oct 2019 20:40:08 -0400
+Subject: [PATCH 4215/4736] drm/amdgpu: disable c-states on xgmi perfmons
+
+read or writes to df registers when gpu df is in c-states will result in
+hang. df c-states should be disabled prior to read or writes then
+re-enabled after read or writes.
+
+Change-Id: I6d5a83e4fe13e29c73dfb03a94fe7c611e867fec
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Evan Quan <Evan.Quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 36 +++++++++++++++++++++++++++-
+ 1 file changed, 35 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 72bfefdbfa65..839a948d70de 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -93,6 +93,21 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
+ NULL
+ };
+
++static df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
++{
++ int r = 0;
++
++ if (is_support_sw_smu(adev)) {
++ r = smu_set_df_cstate(&adev->smu, allow);
++ } else if (adev->powerplay.pp_funcs
++ && adev->powerplay.pp_funcs->set_df_cstate) {
++ r = adev->powerplay.pp_funcs->set_df_cstate(
++ adev->powerplay.pp_handle, allow);
++ }
++
++ return r;
++}
++
+ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ uint32_t ficaa_val)
+ {
+@@ -102,6 +117,9 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
++ if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++ return 0xFFFFFFFFFFFFFFFF;
++
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ WREG32(data, ficaa_val);
+@@ -114,6 +132,8 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+
++ df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
++
+ return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
+ }
+
+@@ -125,6 +145,9 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
++ if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++ return;
++
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ WREG32(data, ficaa_val);
+@@ -134,8 +157,9 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+ WREG32(data, ficadh_val);
+-
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++
++ df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+
+ /*
+@@ -153,12 +177,17 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
++ if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++ return;
++
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, lo_addr);
+ *lo_val = RREG32(data);
+ WREG32(address, hi_addr);
+ *hi_val = RREG32(data);
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++
++ df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+
+ /*
+@@ -175,12 +204,17 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
++ if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++ return;
++
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, lo_addr);
+ WREG32(data, lo_val);
+ WREG32(address, hi_addr);
+ WREG32(data, hi_val);
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++
++ df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+
+ /* get the number of df counters available */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch
new file mode 100644
index 00000000..66b4d571
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch
@@ -0,0 +1,30 @@
+From ab4a7e3256ba093a8d634dcac13ec33838227b5a Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Mon, 14 Oct 2019 18:27:11 +0800
+Subject: [PATCH 4216/4736] drm/amdgpu/psp: declare PSP TA firmware
+
+Add PSP TA firmware declaration for raven raven2 picasso
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index f24760dab4e0..ed8beff02e62 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -37,6 +37,9 @@
+ MODULE_FIRMWARE("amdgpu/raven_asd.bin");
+ MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
+ MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
++MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
++MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
++MODULE_FIRMWARE("amdgpu/raven_ta.bin");
+
+ static int psp_v10_0_init_microcode(struct psp_context *psp)
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch
new file mode 100644
index 00000000..a75abf7c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch
@@ -0,0 +1,39 @@
+From e83bffab9a34e2db3c19b25c2e5841fbb8c03e15 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Thu, 17 Oct 2019 13:52:38 -0400
+Subject: [PATCH 4217/4736] drm/amdgpu: fix compiler warnings for df perfmons
+
+fixing compiler warnings in df v3.6 for c-state toggle and pmc count.
+
+Change-Id: I74f8f1eafccf523a89d60d005e3549235f75c6b8
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Philip Yang <Philip.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 839a948d70de..766615f8c0ba 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -93,7 +93,7 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
+ NULL
+ };
+
+-static df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
++static int df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
+ {
+ int r = 0;
+
+@@ -547,7 +547,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
+ uint64_t config,
+ uint64_t *count)
+ {
+- uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
++ uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
+ *count = 0;
+
+ switch (adev->asic_type) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..4c72bc51
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,106 @@
+From 44b1bc20a6e024c71c00dfd37c81c93a236ab858 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 17 Oct 2019 11:36:47 -0400
+Subject: [PATCH 4218/4736] drm/amdgpu/vce: fix allocation size in enc ring
+ test
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+feedback buffer, otherwise the IB test can overwrite
+other memory.
+
+Reviewed-by: James Zhu<James.Zhu@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 20 +++++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 +
+ 2 files changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index f7189e22f6b7..db545182d4bb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -429,13 +429,14 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
+ * Open up a stream for HW test
+ */
+ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++ struct amdgpu_bo *bo,
+ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 1024;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+- uint64_t dummy;
++ uint64_t addr;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -444,7 +445,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+
+ ib = &job->ibs[0];
+
+- dummy = ib->gpu_addr + 1024;
++ addr = amdgpu_bo_gpu_offset(bo);
+
+ /* stitch together an VCE create msg */
+ ib->length_dw = 0;
+@@ -476,8 +477,8 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+
+ ib->ptr[ib->length_dw++] = 0x00000014; /* len */
+ ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
+- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+- ib->ptr[ib->length_dw++] = dummy;
++ ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++ ib->ptr[ib->length_dw++] = addr;
+ ib->ptr[ib->length_dw++] = 0x00000001;
+
+ for (i = ib->length_dw; i < ib_size_dw; ++i)
+@@ -1110,13 +1111,20 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
+ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ struct dma_fence *fence = NULL;
++ struct amdgpu_bo *bo = NULL;
+ long r;
+
+ /* skip vce ring1/2 ib test for now, since it's not reliable */
+ if (ring != &ring->adev->vce.ring[0])
+ return 0;
+
+- r = amdgpu_vce_get_create_msg(ring, 1, NULL);
++ r = amdgpu_bo_create_reserved(ring->adev, 512, PAGE_SIZE,
++ AMDGPU_GEM_DOMAIN_VRAM,
++ &bo, NULL, NULL);
++ if (r)
++ return r;
++
++ r = amdgpu_vce_get_create_msg(ring, 1, bo, NULL);
+ if (r)
+ goto error;
+
+@@ -1132,5 +1140,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+
+ error:
+ dma_fence_put(fence);
++ amdgpu_bo_unreserve(bo);
++ amdgpu_bo_unref(&bo);
+ return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+index 30ea54dd9117..e802f7d9db0a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+@@ -59,6 +59,7 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev);
+ int amdgpu_vce_suspend(struct amdgpu_device *adev);
+ int amdgpu_vce_resume(struct amdgpu_device *adev);
+ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++ struct amdgpu_bo *bo,
+ struct dma_fence **fence);
+ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+ bool direct, struct dma_fence **fence);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4219-drm-amdgpu-vce-make-some-functions-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4219-drm-amdgpu-vce-make-some-functions-static.patch
new file mode 100644
index 00000000..c7b7bf5b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4219-drm-amdgpu-vce-make-some-functions-static.patch
@@ -0,0 +1,77 @@
+From 0303158fcca21d8a3fb6646e73fa1f32eed7d94e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 17 Oct 2019 11:41:13 -0400
+Subject: [PATCH 4219/4736] drm/amdgpu/vce: make some functions static
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+They are not used outside of the file they are defined in.
+
+Reviewed-by: James Zhu<James.Zhu@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 15 ++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 5 -----
+ 2 files changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index db545182d4bb..92aa3b1b34ce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -80,6 +80,11 @@ MODULE_FIRMWARE(FIRMWARE_VEGA12);
+ MODULE_FIRMWARE(FIRMWARE_VEGA20);
+
+ static void amdgpu_vce_idle_work_handler(struct work_struct *work);
++static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++ struct amdgpu_bo *bo,
++ struct dma_fence **fence);
++static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++ bool direct, struct dma_fence **fence);
+
+ /**
+ * amdgpu_vce_init - allocate memory, load vce firmware
+@@ -428,9 +433,9 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
+ *
+ * Open up a stream for HW test
+ */
+-int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+- struct amdgpu_bo *bo,
+- struct dma_fence **fence)
++static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++ struct amdgpu_bo *bo,
++ struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 1024;
+ struct amdgpu_job *job;
+@@ -508,8 +513,8 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+ *
+ * Close up a stream for HW test or if userspace failed to do so
+ */
+-int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+- bool direct, struct dma_fence **fence)
++static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++ bool direct, struct dma_fence **fence)
+ {
+ const unsigned ib_size_dw = 1024;
+ struct amdgpu_job *job;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+index e802f7d9db0a..d6d83a3ec803 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+@@ -58,11 +58,6 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
+ int amdgpu_vce_entity_init(struct amdgpu_device *adev);
+ int amdgpu_vce_suspend(struct amdgpu_device *adev);
+ int amdgpu_vce_resume(struct amdgpu_device *adev);
+-int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+- struct amdgpu_bo *bo,
+- struct dma_fence **fence);
+-int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+- bool direct, struct dma_fence **fence);
+ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
+ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
+ int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch
new file mode 100644
index 00000000..5fcd0074
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch
@@ -0,0 +1,34 @@
+From 98b68ce2eed4d671b7c485352105b81a28fd5187 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Thu, 17 Oct 2019 12:12:16 +0300
+Subject: [PATCH 4220/4736] drm/amdgpu/vi: silence an uninitialized variable
+ warning
+
+Smatch complains that we need to initialized "*cap" otherwise it can
+lead to an uninitialized variable bug in the caller. This seems like a
+reasonable warning and it doesn't hurt to silence it at least.
+
+drivers/gpu/drm/amd/amdgpu/vi.c:767 vi_asic_reset_method() error: uninitialized symbol 'baco_reset'.
+
+Fixes: 425db2553e43 ("drm/amdgpu: expose BACO interfaces to upper level from PP")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 83196b79edd5..f4ff15378e61 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1421,6 +1421,7 @@ static int pp_get_asic_baco_capability(void *handle, bool *cap)
+ {
+ struct pp_hwmgr *hwmgr = handle;
+
++ *cap = false;
+ if (!hwmgr)
+ return -EINVAL;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch
new file mode 100644
index 00000000..b8ea18d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch
@@ -0,0 +1,133 @@
+From ded09343b5c1253376dca4acb97fa56e9eab2749 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Fri, 18 Oct 2019 15:26:05 -0400
+Subject: [PATCH 4221/4736] drm/amdgpu: revert calling smu msg in df callbacks
+
+reverting the following changes:
+commit 7dd2eb31fcd5 ("drm/amdgpu: fix compiler warnings for df perfmons")
+commit 54275cd1649f ("drm/amdgpu: disable c-states on xgmi perfmons")
+
+perf events use spin-locks. embedded smu messages have potential long
+response times and potentially deadlocks the system.
+
+Change-Id: Ic36c35a62dec116d0a2f5b69c22af4d414458679
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 38 ++--------------------------
+ 1 file changed, 2 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 766615f8c0ba..72bfefdbfa65 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -93,21 +93,6 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
+ NULL
+ };
+
+-static int df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
+-{
+- int r = 0;
+-
+- if (is_support_sw_smu(adev)) {
+- r = smu_set_df_cstate(&adev->smu, allow);
+- } else if (adev->powerplay.pp_funcs
+- && adev->powerplay.pp_funcs->set_df_cstate) {
+- r = adev->powerplay.pp_funcs->set_df_cstate(
+- adev->powerplay.pp_handle, allow);
+- }
+-
+- return r;
+-}
+-
+ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ uint32_t ficaa_val)
+ {
+@@ -117,9 +102,6 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+- if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+- return 0xFFFFFFFFFFFFFFFF;
+-
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ WREG32(data, ficaa_val);
+@@ -132,8 +114,6 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+
+- df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+-
+ return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
+ }
+
+@@ -145,9 +125,6 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+- if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+- return;
+-
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ WREG32(data, ficaa_val);
+@@ -157,9 +134,8 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+ WREG32(data, ficadh_val);
+- spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+
+- df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
++ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+ }
+
+ /*
+@@ -177,17 +153,12 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+- if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+- return;
+-
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, lo_addr);
+ *lo_val = RREG32(data);
+ WREG32(address, hi_addr);
+ *hi_val = RREG32(data);
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+-
+- df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+
+ /*
+@@ -204,17 +175,12 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+ address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+- if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+- return;
+-
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, lo_addr);
+ WREG32(data, lo_val);
+ WREG32(address, hi_addr);
+ WREG32(data, hi_val);
+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+-
+- df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+
+ /* get the number of df counters available */
+@@ -547,7 +513,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
+ uint64_t config,
+ uint64_t *count)
+ {
+- uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
++ uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
+ *count = 0;
+
+ switch (adev->asic_type) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch
new file mode 100644
index 00000000..07b3bd71
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch
@@ -0,0 +1,30 @@
+From 4b98e703e6d18a4716e811c8373dee984821629a Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 18 Oct 2019 09:15:08 +0100
+Subject: [PATCH 4222/4736] drm/amdgpu/psp: fix spelling mistake "initliaze" ->
+ "initialize"
+
+There is a spelling mistake in a DRM_ERROR error message. Fix it.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 64db0c8cee4c..f289a84363c4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -90,7 +90,7 @@ static int psp_sw_init(void *handle)
+
+ ret = psp_mem_training_init(psp);
+ if (ret) {
+- DRM_ERROR("Failed to initliaze memory training!\n");
++ DRM_ERROR("Failed to initialize memory training!\n");
+ return ret;
+ }
+ ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
new file mode 100644
index 00000000..c51b4d98
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
@@ -0,0 +1,44 @@
+From ff90d9ae73aebf86db14dfe520031dd4226f3293 Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Thu, 17 Oct 2019 14:55:56 -0400
+Subject: [PATCH 4223/4736] drm/amd/display: setting the DIG_MODE to the
+ correct value.
+
+[Why]
+This patch is for fixing Navi14 HDMI display pink screen issue.
+
+[How]
+Call stream->link->link_enc->funcs->setup twice. This is setting
+the DIG_MODE to the correct value after having been overridden by
+the call to transmitter control.
+
+Change-Id: Ie739e345753440280bfeecff0b0ac9fda09c5ed0
+Signed-off-by: Zhan liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 5ce5db7818e4..ea50ba20dd68 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2840,6 +2840,15 @@ void core_link_enable_stream(
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ COLOR_DEPTH_UNDEFINED);
+
++ /* This second call is needed to reconfigure the DIG
++ * as a workaround for the incorrect value being applied
++ * from transmitter control.
++ */
++ if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
++ stream->link->link_enc->funcs->setup(
++ stream->link->link_enc,
++ pipe_ctx->stream->signal);
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (pipe_ctx->stream->timing.flags.DSC) {
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch
new file mode 100644
index 00000000..ee892995
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch
@@ -0,0 +1,34 @@
+From 80f4743bc70ce2ebd516b8d5657ee5862f20d202 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 11 Oct 2019 12:26:10 -0400
+Subject: [PATCH 4224/4736] drm/amd/display: Free gamma after calculating
+ legacy transfer function
+
+[Why]
+We're leaking memory by not freeing the gamma used to calculate the
+transfer function for legacy gamma.
+
+[How]
+Release the gamma after we're done with it.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+index 5005eb07159e..2eb1313c0728 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+@@ -209,6 +209,7 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
+ res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,
+ NULL);
+
++ dc_gamma_release(&gamma);
+ return res ? 0 : -ENOMEM;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch
new file mode 100644
index 00000000..810e0d85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch
@@ -0,0 +1,49 @@
+From ea42425830d84635db15d611dcd1232b4400f5fa Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 17 Oct 2019 11:57:45 -0400
+Subject: [PATCH 4225/4736] drm/amdgpu/powerplay: use local renoir array sizes
+ for clock fetching
+
+To avoid walking past the end of the arrays since the PP_SMU
+defines don't match the renoir defines.
+
+Reviewed-by: Prike Liang <Prike.Liang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 953e347633ec..57930c9e22ff 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -427,22 +427,22 @@ static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks
+ if (!clock_table || !table)
+ return -EINVAL;
+
+- for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
++ for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
+ clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
+ clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
+ }
+
+- for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
++ for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
+ clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
+ clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
+ }
+
+- for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
++ for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
+ clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
+ clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
+ }
+
+- for (i = 0; i< PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) {
++ for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
+ clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
+ clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
new file mode 100644
index 00000000..d738d7f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
@@ -0,0 +1,75 @@
+From 7f9d518d0ff5775839b5112e5f7d86bcafd5add2 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 18 Oct 2019 13:36:41 +0800
+Subject: [PATCH 4226/4736] drm/amd/powerplay: update Arcturus driver smu
+ interface XGMI link part
+
+To fit the latest SMU firmware.
+
+Change-Id: Ie34e6930577b7a6fe993273f213732696628b264
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ .../powerplay/inc/smu11_driver_if_arcturus.h | 28 +++++++++++++------
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
+ 2 files changed, 21 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index 2248d682c462..886b9a21ebd8 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -423,18 +423,30 @@ typedef enum {
+ } PwrConfig_e;
+
+ typedef enum {
+- XGMI_LINK_RATE_12 = 0, // 12Gbps
+- XGMI_LINK_RATE_16, // 16Gbps
+- XGMI_LINK_RATE_22, // 22Gbps
+- XGMI_LINK_RATE_25, // 25Gbps
++ XGMI_LINK_RATE_2 = 2, // 2Gbps
++ XGMI_LINK_RATE_4 = 4, // 4Gbps
++ XGMI_LINK_RATE_8 = 8, // 8Gbps
++ XGMI_LINK_RATE_12 = 12, // 12Gbps
++ XGMI_LINK_RATE_16 = 16, // 16Gbps
++ XGMI_LINK_RATE_17 = 17, // 17Gbps
++ XGMI_LINK_RATE_18 = 18, // 18Gbps
++ XGMI_LINK_RATE_19 = 19, // 19Gbps
++ XGMI_LINK_RATE_20 = 20, // 20Gbps
++ XGMI_LINK_RATE_21 = 21, // 21Gbps
++ XGMI_LINK_RATE_22 = 22, // 22Gbps
++ XGMI_LINK_RATE_23 = 23, // 23Gbps
++ XGMI_LINK_RATE_24 = 24, // 24Gbps
++ XGMI_LINK_RATE_25 = 25, // 25Gbps
+ XGMI_LINK_RATE_COUNT
+ } XGMI_LINK_RATE_e;
+
+ typedef enum {
+- XGMI_LINK_WIDTH_2 = 0, // x2
+- XGMI_LINK_WIDTH_4, // x4
+- XGMI_LINK_WIDTH_8, // x8
+- XGMI_LINK_WIDTH_16, // x16
++ XGMI_LINK_WIDTH_1 = 1, // x1
++ XGMI_LINK_WIDTH_2 = 2, // x2
++ XGMI_LINK_WIDTH_4 = 4, // x4
++ XGMI_LINK_WIDTH_8 = 8, // x8
++ XGMI_LINK_WIDTH_9 = 9, // x9
++ XGMI_LINK_WIDTH_16 = 16, // x16
+ XGMI_LINK_WIDTH_COUNT
+ } XGMI_LINK_WIDTH_e;
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index e71f6fedf3c6..6b2a901492b2 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,7 +27,7 @@
+
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+-#define SMU11_DRIVER_IF_VERSION_ARCT 0x0D
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x0F
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x34
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4227-drm-amd-display-Avoid-sending-abnormal-VSIF.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4227-drm-amd-display-Avoid-sending-abnormal-VSIF.patch
new file mode 100644
index 00000000..f90aad89
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4227-drm-amd-display-Avoid-sending-abnormal-VSIF.patch
@@ -0,0 +1,36 @@
+From dc2c0a3b42a09f7da9070d05ae16d97d15f2feec Mon Sep 17 00:00:00 2001
+From: Wayne Lin <Wayne.Lin@amd.com>
+Date: Mon, 21 Oct 2019 13:24:36 +0800
+Subject: [PATCH 4227/4736] drm/amd/display: Avoid sending abnormal VSIF
+
+[Why]
+While setting hdmi_vic, hv_frame.vic is not initialized and might
+assign a wrong value to hdmi_vic. Cause to send out VSIF with
+abnormal value.
+
+[How]
+Initialize hv_frame and avi_frame
+
+Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 70ca73d2a80b..b55dd3680581 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3452,6 +3452,9 @@ static void fill_stream_properties_from_drm_display_mode(
+ struct hdmi_vendor_infoframe hv_frame;
+ struct hdmi_avi_infoframe avi_frame;
+
++ memset(&hv_frame, 0, sizeof(hv_frame));
++ memset(&avi_frame, 0, sizeof(avi_frame));
++
+ timing_out->h_border_left = 0;
+ timing_out->h_border_right = 0;
+ timing_out->v_border_top = 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4228-drm-amd-display-add-50us-buffer-as-WA-for-pstate-swi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4228-drm-amd-display-add-50us-buffer-as-WA-for-pstate-swi.patch
new file mode 100644
index 00000000..5d59357b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4228-drm-amd-display-add-50us-buffer-as-WA-for-pstate-swi.patch
@@ -0,0 +1,30 @@
+From 4f1c705d9a430f770150cfd26b8e929c19fe05e7 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Thu, 19 Sep 2019 17:43:45 -0400
+Subject: [PATCH 4228/4736] drm/amd/display: add 50us buffer as WA for pstate
+ switch in active
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+index 649883777f62..6c6c486b774a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+@@ -2577,7 +2577,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
+ mode_lib->vba.MinActiveDRAMClockChangeMargin
+ + mode_lib->vba.DRAMClockChangeLatency;
+
+- if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++ mode_lib->vba.DRAMClockChangeWatermark += 25;
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else {
+ if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch
new file mode 100644
index 00000000..972ba138
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch
@@ -0,0 +1,92 @@
+From ba021ad1542c7c7c4e1739eb4b51d2288e729c43 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Wed, 25 Sep 2019 09:46:38 -0400
+Subject: [PATCH 4229/4736] drm/amd/display: add odm visual confirm
+
+[why]
+Hard to determine if pipe combine is done with MPC or ODM
+
+[how]
+Add new visual confirm type, this will mark each MPCC tree
+with a different color
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 1 +
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 25 +++++++++++++++++++
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 4 ++-
+ 3 files changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 5967106826ca..b7e7181bad78 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -229,6 +229,7 @@ enum visual_confirm {
+ VISUAL_CONFIRM_DISABLE = 0,
+ VISUAL_CONFIRM_SURFACE = 1,
+ VISUAL_CONFIRM_HDR = 2,
++ VISUAL_CONFIRM_MPCTREE = 4,
+ };
+
+ enum dcc_option {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 6229a8ca0013..e237ec39d193 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1996,6 +1996,28 @@ static void dcn20_reset_hw_ctx_wrap(
+ }
+ }
+
++void dcn20_get_mpctree_visual_confirm_color(
++ struct pipe_ctx *pipe_ctx,
++ struct tg_color *color)
++{
++ const struct tg_color pipe_colors[6] = {
++ {MAX_TG_COLOR_VALUE, 0, 0}, // red
++ {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
++ {0, MAX_TG_COLOR_VALUE, 0}, // blue
++ {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
++ {0, 0, MAX_TG_COLOR_VALUE}, // green
++ {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
++ };
++
++ struct pipe_ctx *top_pipe = pipe_ctx;
++
++ while (top_pipe->top_pipe) {
++ top_pipe = top_pipe->top_pipe;
++ }
++
++ *color = pipe_colors[top_pipe->pipe_idx];
++}
++
+ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+@@ -2013,6 +2035,9 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+ dcn10_get_surface_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
++ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
++ dcn20_get_mpctree_visual_confirm_color(
++ pipe_ctx, &blnd_cfg.black_color);
+ }
+
+ if (per_pixel_alpha)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 9dbc2effa4ea..3098f1049ed7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -109,5 +109,7 @@ bool dcn20_set_blend_lut(
+ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+ bool dcn20_set_shaper_3dlut(
+ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+-
++void dcn20_get_mpctree_visual_confirm_color(
++ struct pipe_ctx *pipe_ctx,
++ struct tg_color *color);
+ #endif /* __DC_HWSS_DCN20_H__ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4230-drm-amd-display-Add-unknown-clk-state.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4230-drm-amd-display-Add-unknown-clk-state.patch
new file mode 100644
index 00000000..19f913ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4230-drm-amd-display-Add-unknown-clk-state.patch
@@ -0,0 +1,100 @@
+From d7ca9f0278e03c1d90753feab813ac4661740c6d Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Thu, 26 Sep 2019 14:08:41 -0400
+Subject: [PATCH 4230/4736] drm/amd/display: Add unknown clk state.
+
+[Why]
+System hang during S0i3 if DP only connected due to clk is disabled when
+doing link training.
+During S0i3, clk is disabled while the clk state is updated when ini_hw
+called, and at the moment clk is still disabled which indicating a wrong
+state for next time trying to enable clk.
+
+[How]
+Add an unknown state and initialize it during int_hw, make sure enable clk
+command be sent to smu.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 ++++++++--------
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dc.h | 5 +++--
+ 3 files changed, 12 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index b647e0320e4b..6212b407cd01 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -114,22 +114,22 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
+ */
+ if (safe_to_lower) {
+ /* check that we're not already in lower */
+- if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_OPTIMIZED) {
++ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+
+ display_count = rn_get_active_display_cnt_wa(dc, context);
+ /* if we can go lower, go lower */
+ if (display_count == 0) {
+- rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_OPTIMIZED);
++ rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
+ /* update power state */
+- clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_OPTIMIZED;
++ clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+ }
+ }
+ } else {
+- /* check that we're not already in the normal state */
+- if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_NORMAL) {
+- rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_NORMAL);
++ /* check that we're not already in D0 */
++ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
++ rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
+ /* update power state */
+- clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_NORMAL;
++ clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
+ }
+ }
+
+@@ -393,7 +393,7 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
+ // Assumption is that boot state always supports pstate
+ clk_mgr->clks.p_state_change_support = true;
+ clk_mgr->clks.prev_p_state_change_support = true;
+- clk_mgr->clks.pwr_state = DCN_PWR_STATE_NORMAL;
++ clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+ }
+
+ static struct clk_mgr_funcs dcn21_funcs = {
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index 5647fcf10717..cb7c0e8b7e1b 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -170,7 +170,7 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum
+ {
+ int disp_count;
+
+- if (state == DCN_PWR_STATE_OPTIMIZED)
++ if (state == DCN_PWR_STATE_LOW_POWER)
+ disp_count = 0;
+ else
+ disp_count = 1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b7e7181bad78..2e1d34882684 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -257,8 +257,9 @@ enum dtm_pstate{
+ };
+
+ enum dcn_pwr_state {
+- DCN_PWR_STATE_OPTIMIZED = 0,
+- DCN_PWR_STATE_NORMAL = 1
++ DCN_PWR_STATE_UNKNOWN = -1,
++ DCN_PWR_STATE_MISSION_MODE = 0,
++ DCN_PWR_STATE_LOW_POWER = 3,
+ };
+
+ /*
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4231-drm-amd-display-Don-t-use-optimized-gamma22-with-eet.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4231-drm-amd-display-Don-t-use-optimized-gamma22-with-eet.patch
new file mode 100644
index 00000000..07abae8c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4231-drm-amd-display-Don-t-use-optimized-gamma22-with-eet.patch
@@ -0,0 +1,101 @@
+From f4810baf1e8c60ea47c2ca238f8a5967fbbaa19d Mon Sep 17 00:00:00 2001
+From: Aidan Yang <Aidan.Yang@amd.com>
+Date: Wed, 25 Sep 2019 16:57:37 -0400
+Subject: [PATCH 4231/4736] drm/amd/display: Don't use optimized gamma22 with
+ eetf
+
+[why]
+Optimized gamma22 assumes fixed point distribution which is not true
+for eetf true.
+
+[how]
+Use long calculation for eetf.
+
+Signed-off-by: Aidan Yang <Aidan.Yang@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Reza Amini <Reza.Amini@amd.com>
+---
+ .../amd/display/modules/color/color_gamma.c | 45 +++++++++++++++++--
+ 1 file changed, 41 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 19475cf5ab72..0accdae5e675 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -370,7 +370,42 @@ static struct fixed31_32 translate_from_linear_space(
+ return dc_fixpt_mul(args->arg, args->a1);
+ }
+
+-static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
++
++static struct fixed31_32 translate_from_linear_space_long(
++ struct translate_from_linear_space_args *args)
++{
++ const struct fixed31_32 one = dc_fixpt_from_int(1);
++
++ if (dc_fixpt_lt(one, args->arg))
++ return one;
++
++ if (dc_fixpt_le(args->arg, dc_fixpt_neg(args->a0)))
++ return dc_fixpt_sub(
++ args->a2,
++ dc_fixpt_mul(
++ dc_fixpt_add(
++ one,
++ args->a3),
++ dc_fixpt_pow(
++ dc_fixpt_neg(args->arg),
++ dc_fixpt_recip(args->gamma))));
++ else if (dc_fixpt_le(args->a0, args->arg))
++ return dc_fixpt_sub(
++ dc_fixpt_mul(
++ dc_fixpt_add(
++ one,
++ args->a3),
++ dc_fixpt_pow(
++ args->arg,
++ dc_fixpt_recip(args->gamma))),
++ args->a2);
++ else
++ return dc_fixpt_mul(
++ args->arg,
++ args->a1);
++}
++
++static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg, bool use_eetf)
+ {
+ struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10);
+
+@@ -381,9 +416,13 @@ static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
+ scratch_gamma_args.a3 = dc_fixpt_zero;
+ scratch_gamma_args.gamma = gamma;
+
++ if (use_eetf)
++ return translate_from_linear_space_long(&scratch_gamma_args);
++
+ return translate_from_linear_space(&scratch_gamma_args);
+ }
+
++
+ static struct fixed31_32 translate_to_linear_space(
+ struct fixed31_32 arg,
+ struct fixed31_32 a0,
+@@ -947,7 +986,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ if (dc_fixpt_lt(scaledX, dc_fixpt_zero))
+ output = dc_fixpt_zero;
+ else
+- output = calculate_gamma22(scaledX);
++ output = calculate_gamma22(scaledX, use_eetf);
+
+ rgb->r = output;
+ rgb->g = output;
+@@ -2170,5 +2209,3 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
+ rgb_degamma_alloc_fail:
+ return ret;
+ }
+-
+-
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4232-drm-amd-display-Remove-superfluous-assert.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4232-drm-amd-display-Remove-superfluous-assert.patch
new file mode 100644
index 00000000..8f43bc0d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4232-drm-amd-display-Remove-superfluous-assert.patch
@@ -0,0 +1,35 @@
+From f7fdc386484c1551024b4e8644f174bd85e2a33a Mon Sep 17 00:00:00 2001
+From: Jordan Lazare <Jordan.Lazare@amd.com>
+Date: Fri, 27 Sep 2019 14:39:01 -0400
+Subject: [PATCH 4232/4736] drm/amd/display: Remove superfluous assert
+
+[Why]
+For loop below the assert already checks for the number of instances to
+create. ASSERT is meaningless and causing spam.
+
+[How]
+dd
+
+Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 58678b679661..ac20d39ec8ce 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2942,8 +2942,6 @@ bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+ int i;
+ uint32_t pipe_count = pool->res_cap->num_dwb;
+
+- ASSERT(pipe_count > 0);
+-
+ for (i = 0; i < pipe_count; i++) {
+ struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
+ GFP_KERNEL);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4233-drm-amd-display-remove-unused-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4233-drm-amd-display-remove-unused-code.patch
new file mode 100644
index 00000000..d015840c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4233-drm-amd-display-remove-unused-code.patch
@@ -0,0 +1,70 @@
+From 762b81f7f405abd6f034606910e7fe645b03c095 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 30 Aug 2019 16:58:29 -0400
+Subject: [PATCH 4233/4736] drm/amd/display: remove unused code
+
+Commit hints are unnecessary after front end programming redesign.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 --
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 -----
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 ----
+ 3 files changed, 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 699a215ca8ce..bd623404772d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1245,8 +1245,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ for (i = 0; i < context->stream_count; i++)
+ context->streams[i]->mode_changed = false;
+
+- memset(&context->commit_hints, 0, sizeof(context->commit_hints));
+-
+ dc_release_state(dc->current_state);
+
+ dc->current_state = context;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index ac20d39ec8ce..c60f8e538cef 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2304,7 +2304,6 @@ bool dcn20_fast_validate_bw(
+ int split_threshold = dc->res_pool->pipe_count / 2;
+ bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+
+-
+ ASSERT(pipes);
+ if (!pipes)
+ return false;
+@@ -2382,10 +2381,6 @@ bool dcn20_fast_validate_bw(
+ if (vlevel > context->bw_ctx.dml.soc.num_states)
+ goto validate_fail;
+
+- if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
+- || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
+- context->commit_hints.full_update_needed = true;
+-
+ /*initialize pipe_just_split_from to invalid idx*/
+ for (i = 0; i < MAX_PIPES; i++)
+ pipe_split_from[i] = -1;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index eee78a73d88c..a831079607cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -398,10 +398,6 @@ struct dc_state {
+
+ struct clk_mgr *clk_mgr;
+
+- struct {
+- bool full_update_needed : 1;
+- } commit_hints;
+-
+ struct kref refcount;
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4234-drm-amd-display-3.2.55.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4234-drm-amd-display-3.2.55.patch
new file mode 100644
index 00000000..34f6be5f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4234-drm-amd-display-3.2.55.patch
@@ -0,0 +1,27 @@
+From 367f8878c378a314902e46420270dccc5ce7e0f9 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sat, 28 Sep 2019 15:57:53 -0400
+Subject: [PATCH 4234/4736] drm/amd/display: 3.2.55
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 2e1d34882684..a86dad3808b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.54"
++#define DC_VER "3.2.55"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4235-drm-amd-display-Add-debugfs-entry-for-reading-psr-st.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4235-drm-amd-display-Add-debugfs-entry-for-reading-psr-st.patch
new file mode 100644
index 00000000..4168b65b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4235-drm-amd-display-Add-debugfs-entry-for-reading-psr-st.patch
@@ -0,0 +1,225 @@
+From 9f74b4bb1486008f7a9eb18a165ceae1c87a22f6 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Fri, 30 Aug 2019 10:44:48 -0400
+Subject: [PATCH 4235/4736] drm/amd/display: Add debugfs entry for reading psr
+ state
+
+[Why]
+For upcoming PSR stupport it's useful to have debug entry
+to verify psr state.
+
+[How]
+ - Enable psr dc api for Linux
+ - Add psr_state file to eDP connector debugfs
+usage e.g.: cat /sys/kernel/debug/dri/0/DP-1/psr_state
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 21 +++
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 149 ++++++++++++++++++
+ 2 files changed, 170 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+index 1f1ed64dd78d..2bb1fae452d9 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+@@ -968,6 +968,25 @@ static int force_yuv420_output_get(void *data, u64 *val)
+ DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
+ force_yuv420_output_set, "%llu\n");
+
++/*
++ * Read PSR state
++ */
++static int psr_get(void *data, u64 *val)
++{
++ struct amdgpu_dm_connector *connector = data;
++ struct dc_link *link = connector->dc_link;
++ uint32_t psr_state = 0;
++
++ dc_link_get_psr_state(link, &psr_state);
++
++ *val = psr_state;
++
++ return 0;
++}
++
++
++DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
++
+ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
+ {
+ int i;
+@@ -981,6 +1000,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
+ dp_debugfs_entries[i].fops);
+ }
+ }
++ if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
++ debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
+
+ debugfs_create_file_unsafe("force_yuv420_output", 0644, dir, connector,
+ &force_yuv420_output_fops);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ea50ba20dd68..84813ef735c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2434,6 +2434,155 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool
+ return true;
+ }
+
++bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
++{
++ struct dc *core_dc = link->ctx->dc;
++ struct dmcu *dmcu = core_dc->res_pool->dmcu;
++
++ if (dmcu != NULL && link->psr_feature_enabled)
++ dmcu->funcs->get_psr_state(dmcu, psr_state);
++
++ return true;
++}
++
++bool dc_link_setup_psr(struct dc_link *link,
++ const struct dc_stream_state *stream, struct psr_config *psr_config,
++ struct psr_context *psr_context)
++{
++ struct dc *core_dc;
++ struct dmcu *dmcu;
++ int i;
++ /* updateSinkPsrDpcdConfig*/
++ union dpcd_psr_configuration psr_configuration;
++
++ psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
++
++ if (!link)
++ return false;
++
++ core_dc = link->ctx->dc;
++ dmcu = core_dc->res_pool->dmcu;
++
++ if (!dmcu)
++ return false;
++
++
++ memset(&psr_configuration, 0, sizeof(psr_configuration));
++
++ psr_configuration.bits.ENABLE = 1;
++ psr_configuration.bits.CRC_VERIFICATION = 1;
++ psr_configuration.bits.FRAME_CAPTURE_INDICATION =
++ psr_config->psr_frame_capture_indication_req;
++
++ /* Check for PSR v2*/
++ if (psr_config->psr_version == 0x2) {
++ /* For PSR v2 selective update.
++ * Indicates whether sink should start capturing
++ * immediately following active scan line,
++ * or starting with the 2nd active scan line.
++ */
++ psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
++ /*For PSR v2, determines whether Sink should generate
++ * IRQ_HPD when CRC mismatch is detected.
++ */
++ psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
++ }
++
++ dm_helpers_dp_write_dpcd(
++ link->ctx,
++ link,
++ 368,
++ &psr_configuration.raw,
++ sizeof(psr_configuration.raw));
++
++ psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
++ psr_context->transmitterId = link->link_enc->transmitter;
++ psr_context->engineId = link->link_enc->preferred_engine;
++
++ for (i = 0; i < MAX_PIPES; i++) {
++ if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
++ == stream) {
++ /* dmcu -1 for all controller id values,
++ * therefore +1 here
++ */
++ psr_context->controllerId =
++ core_dc->current_state->res_ctx.
++ pipe_ctx[i].stream_res.tg->inst + 1;
++ break;
++ }
++ }
++
++ /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
++ psr_context->phyType = PHY_TYPE_UNIPHY;
++ /*PhyId is associated with the transmitter id*/
++ psr_context->smuPhyId = link->link_enc->transmitter;
++
++ psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
++ psr_context->vsyncRateHz = div64_u64(div64_u64((stream->
++ timing.pix_clk_100hz * 100),
++ stream->timing.v_total),
++ stream->timing.h_total);
++
++ psr_context->psrSupportedDisplayConfig = true;
++ psr_context->psrExitLinkTrainingRequired =
++ psr_config->psr_exit_link_training_required;
++ psr_context->sdpTransmitLineNumDeadline =
++ psr_config->psr_sdp_transmit_line_num_deadline;
++ psr_context->psrFrameCaptureIndicationReq =
++ psr_config->psr_frame_capture_indication_req;
++
++ psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
++
++ psr_context->numberOfControllers =
++ link->dc->res_pool->timing_generator_count;
++
++ psr_context->rfb_update_auto_en = true;
++
++ /* 2 frames before enter PSR. */
++ psr_context->timehyst_frames = 2;
++ /* half a frame
++ * (units in 100 lines, i.e. a value of 1 represents 100 lines)
++ */
++ psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
++ psr_context->aux_repeats = 10;
++
++ psr_context->psr_level.u32all = 0;
++
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
++ /*skip power down the single pipe since it blocks the cstate*/
++ if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
++ psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
++#endif
++
++ /* SMU will perform additional powerdown sequence.
++ * For unsupported ASICs, set psr_level flag to skip PSR
++ * static screen notification to SMU.
++ * (Always set for DAL2, did not check ASIC)
++ */
++ psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
++
++ /* Complete PSR entry before aborting to prevent intermittent
++ * freezes on certain eDPs
++ */
++ psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
++
++ /* Controls additional delay after remote frame capture before
++ * continuing power down, default = 0
++ */
++ psr_context->frame_delay = 0;
++
++ link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
++
++ /* psr_enabled == 0 indicates setup_psr did not succeed, but this
++ * should not happen since firmware should be running at this point
++ */
++ if (link->psr_feature_enabled == 0)
++ ASSERT(0);
++
++ return true;
++
++}
++
+ const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
+ {
+ return &link->link_status;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4236-drm-amd-display-Enable-PSR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4236-drm-amd-display-Enable-PSR.patch
new file mode 100644
index 00000000..7983bd1a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4236-drm-amd-display-Enable-PSR.patch
@@ -0,0 +1,229 @@
+From a8ee241de4c89b32b586e89e150b1471714b6ffa Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Fri, 20 Sep 2019 19:03:17 -0400
+Subject: [PATCH 4236/4736] drm/amd/display: Enable PSR
+
+[Why]
+PSR (Panel Self-Refresh) is a power-saving feature for eDP panels.
+The feature has support in DMCU (Display MicroController Unit).
+DMCU/driver communication is implemented in DC.
+DM can use existing DC PSR interface to use PSR feature.
+
+[How]
+- Read psr caps via dpcd
+- Send vsc infoframe if panel supports psr
+- Disable psr before h/w programming (FULL_UPDATE)
+- Enable psr after h/w programming
+- Disable psr for fb console
+
+Change-Id: Ic52045fc6c68d66d744b1bdd99f14274f69322c6
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 133 +++++++++++++++++-
+ 1 file changed, 130 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index b55dd3680581..8139cffd5b88 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -146,6 +146,12 @@ static void prepare_flip_isr(struct amdgpu_crtc *acrtc);
+ static void handle_cursor_update(struct drm_plane *plane,
+ struct drm_plane_state *old_plane_state);
+
++static void amdgpu_dm_set_psr_caps(struct dc_link *link);
++static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
++static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
++static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
++
++
+ /*
+ * dm_vblank_get_counter
+ *
+@@ -2400,6 +2406,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
+ amdgpu_dm_update_connector_after_detect(aconnector);
+ register_backlight_device(dm, link);
++ amdgpu_dm_set_psr_caps(link);
+ }
+
+
+@@ -3799,7 +3806,16 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+
+ if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
++ if (stream->link->psr_feature_enabled) {
++ struct dc *core_dc = stream->link->ctx->dc;
+
++ if (dc_is_dmcu_initialized(core_dc)) {
++ struct dmcu *dmcu = core_dc->res_pool->dmcu;
++
++ stream->psr_version = dmcu->dmcu_version.psr_version;
++ mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
++ }
++ }
+ finish:
+ dc_sink_release(sink);
+
+@@ -5782,6 +5798,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ uint32_t target_vblank, last_flip_vblank;
+ bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
+ bool pflip_present = false;
++ bool swizzle = true;
+ struct {
+ struct dc_surface_update surface_updates[MAX_SURFACES];
+ struct dc_plane_info plane_infos[MAX_SURFACES];
+@@ -5827,6 +5844,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+
+ dc_plane = dm_new_plane_state->dc_state;
+
++ if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
++ swizzle = false;
++
+ bundle->surface_updates[planes_count].surface = dc_plane;
+ if (new_pcrtc_state->color_mgmt_changed) {
+ bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
+@@ -6017,14 +6037,29 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ &acrtc_state->vrr_params.adjust);
+ spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
+ }
+-
+ mutex_lock(&dm->dc_lock);
++ if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
++ acrtc_state->stream->link->psr_allow_active)
++ amdgpu_dm_psr_disable(acrtc_state->stream);
++
+ dc_commit_updates_for_stream(dm->dc,
+ bundle->surface_updates,
+ planes_count,
+ acrtc_state->stream,
+ &bundle->stream_update,
+ dc_state);
++
++ if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
++ acrtc_state->stream->psr_version &&
++ !acrtc_state->stream->link->psr_feature_enabled)
++ amdgpu_dm_link_setup_psr(acrtc_state->stream);
++ else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
++ acrtc_state->stream->link->psr_feature_enabled &&
++ !acrtc_state->stream->link->psr_allow_active &&
++ swizzle) {
++ amdgpu_dm_psr_enable(acrtc_state->stream);
++ }
++
+ mutex_unlock(&dm->dc_lock);
+ }
+
+@@ -6329,10 +6364,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ crtc->hwmode = new_crtc_state->mode;
+ } else if (modereset_required(new_crtc_state)) {
+ DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
+-
+ /* i.e. reset mode */
+- if (dm_old_crtc_state->stream)
++ if (dm_old_crtc_state->stream) {
++ if (dm_old_crtc_state->stream->link->psr_allow_active)
++ amdgpu_dm_psr_disable(dm_old_crtc_state->stream);
++
+ remove_stream(adev, acrtc, dm_old_crtc_state->stream);
++ }
+ }
+ } /* for_each_crtc_in_state() */
+
+@@ -7688,3 +7726,92 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
+ freesync_capable);
+ }
+
++static void amdgpu_dm_set_psr_caps(struct dc_link *link)
++{
++ uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
++
++ if (!(link->connector_signal & SIGNAL_TYPE_EDP))
++ return;
++ if (link->type == dc_connection_none)
++ return;
++ if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
++ dpcd_data, sizeof(dpcd_data))) {
++ link->psr_feature_enabled = dpcd_data[0] ? true:false;
++ DRM_INFO("PSR support:%d\n", link->psr_feature_enabled);
++ }
++}
++
++/*
++ * amdgpu_dm_link_setup_psr() - configure psr link
++ * @stream: stream state
++ *
++ * Return: true if success
++ */
++static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
++{
++ struct dc_link *link = NULL;
++ struct psr_config psr_config = {0};
++ struct psr_context psr_context = {0};
++ struct dc *dc = NULL;
++ bool ret = false;
++
++ if (stream == NULL)
++ return false;
++
++ link = stream->link;
++ dc = link->ctx->dc;
++
++ psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version;
++
++ if (psr_config.psr_version > 0) {
++ psr_config.psr_exit_link_training_required = 0x1;
++ psr_config.psr_frame_capture_indication_req = 0;
++ psr_config.psr_rfb_setup_time = 0x37;
++ psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
++ psr_config.allow_smu_optimizations = 0x0;
++
++ ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
++
++ }
++ DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_feature_enabled);
++
++ return ret;
++}
++
++/*
++ * amdgpu_dm_psr_enable() - enable psr f/w
++ * @stream: stream state
++ *
++ * Return: true if success
++ */
++bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
++{
++ struct dc_link *link = stream->link;
++ struct dc_static_screen_events triggers = {0};
++
++ DRM_DEBUG_DRIVER("Enabling psr...\n");
++
++ triggers.cursor_update = true;
++ triggers.overlay_update = true;
++ triggers.surface_update = true;
++
++ dc_stream_set_static_screen_events(link->ctx->dc,
++ &stream, 1,
++ &triggers);
++
++ return dc_link_set_psr_allow_active(link, true, false);
++}
++
++/*
++ * amdgpu_dm_psr_disable() - disable psr f/w
++ * @stream: stream state
++ *
++ * Return: true if success
++ */
++static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
++{
++
++ DRM_DEBUG_DRIVER("Disabling psr...\n");
++
++ return dc_link_set_psr_allow_active(stream->link, false, true);
++}
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch
new file mode 100644
index 00000000..cbf9be13
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch
@@ -0,0 +1,58 @@
+From c1457d444d163b12fd5457314507acce75f9a34a Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Fri, 27 Sep 2019 10:52:15 -0400
+Subject: [PATCH 4237/4736] drm/amd/display: correctly populate dpp refclk in
+ fpga
+
+[Why]
+In diags environment we are not programming the DPP DTO
+correctly.
+
+[How]
+Populate the dpp refclk in dccg so it can be used to correctly
+program DPP DTO.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index ecd2cb4840e3..69daddbfbf29 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -260,6 +260,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
+ struct dc_state *context,
+ bool safe_to_lower)
+ {
++ struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
++
+ struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+ /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
+ int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
+@@ -297,14 +299,18 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
+ clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
+ }
+
+- /* Both fclk and dppclk ref are run on the same scemi clock so we
+- * need to keep the same value for both
++ /* Both fclk and ref_dppclk run on the same scemi clock.
++ * So take the higher value since the DPP DTO is typically programmed
++ * such that max dppclk is 1:1 with ref_dppclk.
+ */
+ if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
+ clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
+ if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
+ clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
+
++ // Both fclk and ref_dppclk run on the same scemi clock.
++ clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
++
+ dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4238-drm-amd-display-split-dcn20-fast-validate-into-more-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4238-drm-amd-display-split-dcn20-fast-validate-into-more-.patch
new file mode 100644
index 00000000..32ace21b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4238-drm-amd-display-split-dcn20-fast-validate-into-more-.patch
@@ -0,0 +1,373 @@
+From 5552d85b5ad24d5fa12a61d5d8e500f880a2e36d Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Mon, 23 Sep 2019 12:56:20 -0400
+Subject: [PATCH 4238/4736] drm/amd/display: split dcn20 fast validate into
+ more functions
+
+Split a large function into smaller, reusable chunks.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 182 ++++++++++--------
+ .../drm/amd/display/dc/dcn20/dcn20_resource.h | 31 +++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
+ 3 files changed, 136 insertions(+), 78 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index c60f8e538cef..2ea4879b834f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1641,7 +1641,7 @@ static void swizzle_to_dml_params(
+ }
+ }
+
+-static bool dcn20_split_stream_for_odm(
++bool dcn20_split_stream_for_odm(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct pipe_ctx *prev_odm_pipe,
+@@ -1719,7 +1719,7 @@ static bool dcn20_split_stream_for_odm(
+ return true;
+ }
+
+-static void dcn20_split_stream_for_mpc(
++void dcn20_split_stream_for_mpc(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct pipe_ctx *primary_pipe,
+@@ -2177,7 +2177,7 @@ void dcn20_set_mcif_arb_params(
+ }
+
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
++bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ {
+ int i;
+
+@@ -2212,7 +2212,7 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ }
+ #endif
+
+-static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
++struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *primary_pipe)
+@@ -2289,24 +2289,11 @@ static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ return secondary_pipe;
+ }
+
+-bool dcn20_fast_validate_bw(
++void dcn20_merge_pipes_for_validate(
+ struct dc *dc,
+- struct dc_state *context,
+- display_e2e_pipe_params_st *pipes,
+- int *pipe_cnt_out,
+- int *pipe_split_from,
+- int *vlevel_out)
++ struct dc_state *context)
+ {
+- bool out = false;
+-
+- int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
+- bool force_split = false;
+- int split_threshold = dc->res_pool->pipe_count / 2;
+- bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+-
+- ASSERT(pipes);
+- if (!pipes)
+- return false;
++ int i;
+
+ /* merge previously split odm pipes since mode support needs to make the decision */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+@@ -2361,31 +2348,18 @@ bool dcn20_fast_validate_bw(
+ if (pipe->plane_state)
+ resource_build_scaling_params(pipe);
+ }
++}
+
+- if (dc->res_pool->funcs->populate_dml_pipes)
+- pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+- &context->res_ctx, pipes);
+- else
+- pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+- &context->res_ctx, pipes);
+-
+- *pipe_cnt_out = pipe_cnt;
+-
+- if (!pipe_cnt) {
+- out = true;
+- goto validate_out;
+- }
+-
+- vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+-
+- if (vlevel > context->bw_ctx.dml.soc.num_states)
+- goto validate_fail;
+-
+- /*initialize pipe_just_split_from to invalid idx*/
+- for (i = 0; i < MAX_PIPES; i++)
+- pipe_split_from[i] = -1;
++int dcn20_validate_apply_pipe_split_flags(
++ struct dc *dc,
++ struct dc_state *context,
++ int vlevel,
++ bool *split)
++{
++ int i, pipe_idx, vlevel_unsplit;
++ bool force_split = false;
++ bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+
+- /* Single display only conditionals get set here */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ bool exit_loop = false;
+@@ -2412,38 +2386,105 @@ bool dcn20_fast_validate_bw(
+ if (exit_loop)
+ break;
+ }
+-
+- if (context->stream_count > split_threshold)
++ /* TODO: fix dc bugs and remove this split threshold thing */
++ if (context->stream_count > dc->res_pool->pipe_count / 2)
+ avoid_split = true;
+
+- vlevel_unsplit = vlevel;
++ if (avoid_split) {
++ for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
++ if (!context->res_ctx.pipe_ctx[i].stream)
++ continue;
++
++ for (vlevel_unsplit = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
++ if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
++ break;
++ /* Impossible to not split this pipe */
++ if (vlevel == context->bw_ctx.dml.soc.num_states)
++ vlevel = vlevel_unsplit;
++ pipe_idx++;
++ }
++ context->bw_ctx.dml.vba.maxMpcComb = 0;
++ }
++
+ for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
++ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
++
+ if (!context->res_ctx.pipe_ctx[i].stream)
+ continue;
+- for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
+- if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
+- break;
++
++ if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
++ split[i] = true;
++ if ((pipe->stream->view_format ==
++ VIEW_3D_FORMAT_SIDE_BY_SIDE ||
++ pipe->stream->view_format ==
++ VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
++ (pipe->stream->timing.timing_3d_format ==
++ TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
++ pipe->stream->timing.timing_3d_format ==
++ TIMING_3D_FORMAT_SIDE_BY_SIDE))
++ split[i] = true;
++ if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
++ split[i] = true;
++ context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
++ }
++ context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]
++ = context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
++ /* Adjust dppclk when split is forced, do not bother with dispclk */
++ if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
++ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+ pipe_idx++;
+ }
+
++ return vlevel;
++}
++
++bool dcn20_fast_validate_bw(
++ struct dc *dc,
++ struct dc_state *context,
++ display_e2e_pipe_params_st *pipes,
++ int *pipe_cnt_out,
++ int *pipe_split_from,
++ int *vlevel_out)
++{
++ bool out = false;
++ bool split[MAX_PIPES] = { false };
++ int pipe_cnt, i, pipe_idx, vlevel;
++
++ ASSERT(pipes);
++ if (!pipes)
++ return false;
++
++ dcn20_merge_pipes_for_validate(dc, context);
++
++ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, &context->res_ctx, pipes);
++
++ *pipe_cnt_out = pipe_cnt;
++
++ if (!pipe_cnt) {
++ out = true;
++ goto validate_out;
++ }
++
++ vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
++
++ if (vlevel > context->bw_ctx.dml.soc.num_states)
++ goto validate_fail;
++
++ vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split);
++
++ /*initialize pipe_just_split_from to invalid idx*/
++ for (i = 0; i < MAX_PIPES; i++)
++ pipe_split_from[i] = -1;
++
+ for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
+- bool need_split = true;
+- bool need_split3d;
+
+ if (!pipe->stream || pipe_split_from[i] >= 0)
+ continue;
+
+ pipe_idx++;
+
+- if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
+- force_split = true;
+- context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
+- context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
+- }
+- if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
+- context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+ if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+ hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+ ASSERT(hsplit_pipe);
+@@ -2461,32 +2502,16 @@ bool dcn20_fast_validate_bw(
+ if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
+ continue;
+
+- need_split3d = ((pipe->stream->view_format ==
+- VIEW_3D_FORMAT_SIDE_BY_SIDE ||
+- pipe->stream->view_format ==
+- VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
+- (pipe->stream->timing.timing_3d_format ==
+- TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+- pipe->stream->timing.timing_3d_format ==
+- TIMING_3D_FORMAT_SIDE_BY_SIDE));
+-
+- if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
+- need_split = false;
+- vlevel = vlevel_unsplit;
+- context->bw_ctx.dml.vba.maxMpcComb = 0;
+- } else
+- need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
+-
+ /* We do not support mpo + odm at the moment */
+ if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
+ && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
+ goto validate_fail;
+
+- if (need_split3d || need_split || force_split) {
++ if (split[i]) {
+ if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
+ /* pipe not split previously needs split */
+ hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+- ASSERT(hsplit_pipe || force_split);
++ ASSERT(hsplit_pipe);
+ if (!hsplit_pipe)
+ continue;
+
+@@ -2549,7 +2574,7 @@ void dcn20_calculate_wm(
+ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
+ if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
+ pipes[pipe_cnt].pipe.dest.odm_combine =
+- context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
++ context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
+ else
+ pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+ pipe_idx++;
+@@ -2558,7 +2583,7 @@ void dcn20_calculate_wm(
+ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
+ if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
+ pipes[pipe_cnt].pipe.dest.odm_combine =
+- context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
++ context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
+ else
+ pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+ }
+@@ -2929,6 +2954,7 @@ static struct resource_funcs dcn20_res_pool_funcs = {
+ .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
+ .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
+ .set_mcif_arb_params = dcn20_set_mcif_arb_params,
++ .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
+ .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index 55006462f481..fe68669a1f0c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -113,6 +113,31 @@ void dcn20_set_mcif_arb_params(
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt);
+ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
++void dcn20_merge_pipes_for_validate(
++ struct dc *dc,
++ struct dc_state *context);
++int dcn20_validate_apply_pipe_split_flags(
++ struct dc *dc,
++ struct dc_state *context,
++ int vlevel,
++ bool *split);
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
++#endif
++void dcn20_split_stream_for_mpc(
++ struct resource_context *res_ctx,
++ const struct resource_pool *pool,
++ struct pipe_ctx *primary_pipe,
++ struct pipe_ctx *secondary_pipe);
++bool dcn20_split_stream_for_odm(
++ struct resource_context *res_ctx,
++ const struct resource_pool *pool,
++ struct pipe_ctx *prev_odm_pipe,
++ struct pipe_ctx *next_odm_pipe);
++struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
++ struct resource_context *res_ctx,
++ const struct resource_pool *pool,
++ const struct pipe_ctx *primary_pipe);
+ bool dcn20_fast_validate_bw(
+ struct dc *dc,
+ struct dc_state *context,
+@@ -125,6 +150,12 @@ void dcn20_calculate_dlg_params(
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt,
+ int vlevel);
++void dcn20_calculate_wm(
++ struct dc *dc, struct dc_state *context,
++ display_e2e_pipe_params_st *pipes,
++ int *out_pipe_cnt,
++ int *pipe_split_from,
++ int vlevel);
+
+ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
+ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 2125a3e50b0b..7a87a79326ca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1639,6 +1639,7 @@ static struct resource_funcs dcn21_res_pool_funcs = {
+ .destroy = dcn21_destroy_resource_pool,
+ .link_enc_create = dcn21_link_encoder_create,
+ .validate_bandwidth = dcn21_validate_bandwidth,
++ .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
+ .add_stream_to_ctx = dcn20_add_stream_to_ctx,
+ .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+ .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4239-drm-amd-display-correctly-initialize-dml-odm-variabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4239-drm-amd-display-correctly-initialize-dml-odm-variabl.patch
new file mode 100644
index 00000000..aa5e5bb0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4239-drm-amd-display-correctly-initialize-dml-odm-variabl.patch
@@ -0,0 +1,64 @@
+From 90b5c719195b98a04b8ab74d4694bf55238cf684 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 25 Sep 2019 08:25:24 -0400
+Subject: [PATCH 4239/4736] drm/amd/display: correctly initialize dml odm
+ variables
+
+One of odm variables was not initialized in dml.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Tony Cheng <Tony.Cheng@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 6 ------
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 ++
+ 3 files changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2ea4879b834f..f283fdcfd3b2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2553,7 +2553,7 @@ bool dcn20_fast_validate_bw(
+ return out;
+ }
+
+-void dcn20_calculate_wm(
++static void dcn20_calculate_wm(
+ struct dc *dc, struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int *out_pipe_cnt,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index fe68669a1f0c..dccfe07832e3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -150,12 +150,6 @@ void dcn20_calculate_dlg_params(
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt,
+ int vlevel);
+-void dcn20_calculate_wm(
+- struct dc *dc, struct dc_state *context,
+- display_e2e_pipe_params_st *pipes,
+- int *out_pipe_cnt,
+- int *pipe_split_from,
+- int vlevel);
+
+ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
+ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 362dc6ea98ae..038701d7383d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -432,6 +432,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ dst->recout_width; // TODO: or should this be full_recout_width???...maybe only when in hsplit mode?
+ mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =
+ dst->odm_combine;
++ mode_lib->vba.ODMCombineTypeEnabled[mode_lib->vba.NumberOfActivePlanes] =
++ dst->odm_combine;
+ mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
+ (enum output_format_class) (dout->output_format);
+ mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4240-drm-amd-display-move-dispclk-vco-freq-to-clk-mgr-bas.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4240-drm-amd-display-move-dispclk-vco-freq-to-clk-mgr-bas.patch
new file mode 100644
index 00000000..2f63ca28
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4240-drm-amd-display-move-dispclk-vco-freq-to-clk-mgr-bas.patch
@@ -0,0 +1,316 @@
+From 8ee40e6139e1d3b8d5b099bfad953a8e1cdddc50 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 25 Sep 2019 17:12:10 -0400
+Subject: [PATCH 4240/4736] drm/amd/display: move dispclk vco freq to clk mgr
+ base
+
+This value will be needed by dml and therefore should be externally
+accessible.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 14 +++++++-------
+ .../amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c | 4 ++--
+ .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 10 +++++-----
+ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 14 +++++++-------
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 12 ++++++------
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h | 7 -------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 12 ++++++------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 6 ++++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 +-
+ .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 2 --
+ 10 files changed, 40 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+index 7634982a6bb0..aa0e6ee205c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+@@ -144,7 +144,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
+
+ /* Calculate the current DFS clock, in kHz.*/
+ dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+- * clk_mgr->dentist_vco_freq_khz) / target_div;
++ * clk_mgr->base.dentist_vco_freq_khz) / target_div;
+
+ return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
+ }
+@@ -236,7 +236,7 @@ int dce_set_clock(
+ /* Make sure requested clock isn't lower than minimum threshold*/
+ if (requested_clk_khz > 0)
+ requested_clk_khz = max(requested_clk_khz,
+- clk_mgr_dce->dentist_vco_freq_khz / 64);
++ clk_mgr_dce->base.dentist_vco_freq_khz / 64);
+
+ /* Prepare to program display clock*/
+ pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
+@@ -273,11 +273,11 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ int i;
+
+ if (bp->integrated_info)
+- clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+- if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
+- clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+- if (clk_mgr_dce->dentist_vco_freq_khz == 0)
+- clk_mgr_dce->dentist_vco_freq_khz = 3600000;
++ clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
++ if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
++ clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
++ if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
++ clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
+ }
+
+ /*update the maximum display clock for each power state*/
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+index 7c746ef1e32e..a6c46e903ff9 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+@@ -81,7 +81,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+ /* Make sure requested clock isn't lower than minimum threshold*/
+ if (requested_clk_khz > 0)
+ requested_clk_khz = max(requested_clk_khz,
+- clk_mgr_dce->dentist_vco_freq_khz / 62);
++ clk_mgr_dce->base.dentist_vco_freq_khz / 62);
+
+ dce_clk_params.target_clock_frequency = requested_clk_khz;
+ dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
+@@ -135,7 +135,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ /* Make sure requested clock isn't lower than minimum threshold*/
+ if (requested_clk_khz > 0)
+ requested_clk_khz = max(requested_clk_khz,
+- clk_mgr->dentist_vco_freq_khz / 62);
++ clk_mgr->base.dentist_vco_freq_khz / 62);
+
+ dce_clk_params.target_clock_frequency = requested_clk_khz;
+ dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index 6e03805e1b87..3c8b4d5dd843 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -271,11 +271,11 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ clk_mgr->base.dprefclk_khz = 600000;
+
+ if (bp->integrated_info)
+- clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+- if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
+- clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+- if (clk_mgr->dentist_vco_freq_khz == 0)
+- clk_mgr->dentist_vco_freq_khz = 3600000;
++ clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
++ if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {
++ clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
++ if (clk_mgr->base.dentist_vco_freq_khz == 0)
++ clk_mgr->base.dentist_vco_freq_khz = 3600000;
+ }
+
+ if (!debug->disable_dfs_bypass && bp->integrated_info)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 69daddbfbf29..607d8afc56ec 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -121,9 +121,9 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
+ {
+ int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+- * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
++ * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
+ int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+- * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
++ * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
+
+ uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
+ uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+@@ -412,7 +412,7 @@ void dcn20_clk_mgr_construct(
+
+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
+- clk_mgr->dentist_vco_freq_khz = 3850000;
++ clk_mgr->base.dentist_vco_freq_khz = 3850000;
+
+ } else {
+ /* DFS Slice 2 should be used for DPREFCLK */
+@@ -436,15 +436,15 @@ void dcn20_clk_mgr_construct(
+ pll_req = dc_fixpt_mul_int(pll_req, 100000);
+
+ /* integer part is now VCO frequency in kHz */
+- clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
++ clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
+
+ /* in case we don't get a value from the register, use default */
+- if (clk_mgr->dentist_vco_freq_khz == 0)
+- clk_mgr->dentist_vco_freq_khz = 3850000;
++ if (clk_mgr->base.dentist_vco_freq_khz == 0)
++ clk_mgr->base.dentist_vco_freq_khz = 3850000;
+
+ /* Calculate the DPREFCLK in kHz.*/
+ clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+- * clk_mgr->dentist_vco_freq_khz) / target_div;
++ * clk_mgr->base.dentist_vco_freq_khz) / target_div;
+ }
+ //Integrated_info table does not exist on dGPU projects so should not be referenced
+ //anywhere in code for dGPUs.
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 6212b407cd01..e8b8ee4f1b1e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -472,7 +472,7 @@ struct clk_bw_params rn_bw_params = {
+ }
+ };
+
+-void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
++static void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
+ {
+ int i, num_valid_sets;
+
+@@ -542,7 +542,7 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi
+ return 0;
+ }
+
+-void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
+ {
+ int i, j = 0;
+
+@@ -628,17 +628,17 @@ void rn_clk_mgr_construct(
+
+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
+- clk_mgr->dentist_vco_freq_khz = 3600000;
++ clk_mgr->base.dentist_vco_freq_khz = 3600000;
+ clk_mgr->base.dprefclk_khz = 600000;
+ } else {
+ struct clk_log_info log_info = {0};
+
+ /* TODO: Check we get what we expect during bringup */
+- clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
++ clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
+
+ /* in case we don't get a value from the register, use default */
+- if (clk_mgr->dentist_vco_freq_khz == 0)
+- clk_mgr->dentist_vco_freq_khz = 3600000;
++ if (clk_mgr->base.dentist_vco_freq_khz == 0)
++ clk_mgr->base.dentist_vco_freq_khz = 3600000;
+
+ rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
+ /* Convert dprefclk units from MHz to KHz */
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+index 761bfda970a5..e4322fa5475b 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+@@ -33,13 +33,6 @@ struct rn_clk_registers {
+ uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
+ };
+
+-void rn_build_watermark_ranges(
+- struct clk_bw_params *bw_params,
+- struct pp_smu_wm_range_sets *ranges);
+-void rn_clk_mgr_helper_populate_bw_params(
+- struct clk_bw_params *bw_params,
+- struct dpm_clocks *clock_table,
+- struct hw_asic_id *asic_id);
+ void rn_clk_mgr_construct(struct dc_context *ctx,
+ struct clk_mgr_internal *clk_mgr,
+ struct pp_smu_funcs *pp_smu,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f283fdcfd3b2..5e939d20e88f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -3031,7 +3031,7 @@ static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+ }
+ }
+
+-static void cap_soc_clocks(
++void dcn20_cap_soc_clocks(
+ struct _vcs_dpi_soc_bounding_box_st *bb,
+ struct pp_smu_nv_clock_table max_clocks)
+ {
+@@ -3098,7 +3098,7 @@ static void cap_soc_clocks(
+ }
+ }
+
+-static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
++void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
+ struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
+ {
+ struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
+@@ -3156,7 +3156,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
+ bb->clock_limits[num_calculated_states].state = bb->num_states;
+ }
+
+-static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
++void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
+ {
+ kernel_fpu_begin();
+ if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
+@@ -3355,14 +3355,14 @@ static bool init_soc_bounding_box(struct dc *dc,
+ }
+
+ if (clock_limits_available && uclk_states_available && num_states)
+- update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
++ dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
+ else if (clock_limits_available)
+- cap_soc_clocks(loaded_bb, max_clocks);
++ dcn20_cap_soc_clocks(loaded_bb, max_clocks);
+ }
+
+ loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
+ loaded_ip->max_num_dpp = pool->base.pipe_count;
+- patch_bounding_box(dc, loaded_bb);
++ dcn20_patch_bounding_box(dc, loaded_bb);
+
+ return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index dccfe07832e3..fef473d68a4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -95,6 +95,12 @@ struct display_stream_compressor *dcn20_dsc_create(
+ struct dc_context *ctx, uint32_t inst);
+ void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
+
++void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb);
++void dcn20_cap_soc_clocks(
++ struct _vcs_dpi_soc_bounding_box_st *bb,
++ struct pp_smu_nv_clock_table max_clocks);
++void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
++ struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
+ struct hubp *dcn20_hubp_create(
+ struct dc_context *ctx,
+ uint32_t inst);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index f2e21cb9fbd5..da43523a7bfe 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -149,7 +149,6 @@ struct wm_table {
+ struct clk_bw_params {
+ unsigned int vram_type;
+ unsigned int num_channels;
+- unsigned int dispclk_vco_khz;
+ struct clk_limit_table clk_table;
+ struct wm_table wm_table;
+ };
+@@ -192,6 +191,7 @@ struct clk_mgr {
+ struct dc_clocks clks;
+ bool psr_allow_active_cache;
+ int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
++ int dentist_vco_freq_khz;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ struct clk_bw_params *bw_params;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 2e8cd7956a17..a17a77192690 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -225,8 +225,6 @@ struct clk_mgr_internal {
+ struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
+
+ /*TODO: figure out which of the below fields should be here vs in asic specific portion */
+- int dentist_vco_freq_khz;
+-
+ /* Cache the status of DFS-bypass feature*/
+ bool dfs_bypass_enabled;
+ /* True if the DFS-bypass feature is enabled and active. */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4241-drm-amd-display-remove-unnecessary-assert.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4241-drm-amd-display-remove-unnecessary-assert.patch
new file mode 100644
index 00000000..44f1d048
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4241-drm-amd-display-remove-unnecessary-assert.patch
@@ -0,0 +1,38 @@
+From 48f867d199e53a69984315e4a82f217bb5f03017 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 25 Sep 2019 18:11:12 -0400
+Subject: [PATCH 4241/4736] drm/amd/display: remove unnecessary assert
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 5e939d20e88f..58a427d30075 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1662,7 +1662,6 @@ bool dcn20_split_stream_for_odm(
+ next_odm_pipe->stream_res.dsc = NULL;
+ #endif
+ if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
+- ASSERT(!next_odm_pipe->next_odm_pipe);
+ next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
+ next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
+ }
+@@ -2427,8 +2426,8 @@ int dcn20_validate_apply_pipe_split_flags(
+ split[i] = true;
+ context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
+ }
+- context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]
+- = context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
++ context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =
++ context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
+ /* Adjust dppclk when split is forced, do not bother with dispclk */
+ if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
+ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4242-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4242-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch
new file mode 100644
index 00000000..b8d32ee5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4242-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch
@@ -0,0 +1,63 @@
+From f30704ee3bcfebbcd399848f2cc8dab6e78ecf9a Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Tue, 1 Oct 2019 11:24:32 -0400
+Subject: [PATCH 4242/4736] drm/amd/display: Fix MPO & pipe split on 3-pipe
+ dcn2x
+
+[WHY]
+DML is incorrectly initialized with 4 pipes on 3 pipe configs
+RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe
+case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display)
+
+[HOW]
+Set correct number of DPP/OTGs for dml init to generate correct DPP topology
+Double RequiredDPPCLK after clock is halved for pipe split
+and find_secondary_pipe fails to fix underflow
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 +++--
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 ++++++++
+ 2 files changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 58a427d30075..0ef5c5d60f79 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2511,9 +2511,10 @@ bool dcn20_fast_validate_bw(
+ /* pipe not split previously needs split */
+ hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+ ASSERT(hsplit_pipe);
+- if (!hsplit_pipe)
++ if (!hsplit_pipe) {
++ context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
+ continue;
+-
++ }
+ if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+ if (!dcn20_split_stream_for_odm(
+ &context->res_ctx, dc->res_pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 7a87a79326ca..47a8955003a5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1772,6 +1772,14 @@ static bool construct(
+
+ pool->base.pp_smu = dcn21_pp_smu_create(ctx);
+
++ uint32_t num_pipes = dcn2_1_ip.max_num_dpp;
++
++ for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
++ if (pipe_fuses & 1 << i)
++ num_pipes--;
++ dcn2_1_ip.max_num_dpp = num_pipes;
++ dcn2_1_ip.max_num_otg = num_pipes;
++
+ dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
+
+ init_data.ctx = dc->ctx;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4243-drm-amd-display-audio-endpoint-cannot-switch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4243-drm-amd-display-audio-endpoint-cannot-switch.patch
new file mode 100644
index 00000000..bae703da
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4243-drm-amd-display-audio-endpoint-cannot-switch.patch
@@ -0,0 +1,45 @@
+From 27c0ad919ed09d031d01e7ada90941d9758795a1 Mon Sep 17 00:00:00 2001
+From: Paul Hsieh <paul.hsieh@amd.com>
+Date: Tue, 1 Oct 2019 17:06:04 +0800
+Subject: [PATCH 4243/4736] drm/amd/display: audio endpoint cannot switch
+
+[Why]
+On some systems, we need to check the dcn version in runtime
+system, not in compile time.
+
+[How]
+Stub in dcn version parameter to find_first_free_audio
+
+Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 23313c8808b3..66a910ac3cbd 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1626,7 +1626,8 @@ static int acquire_first_free_pipe(
+ static struct audio *find_first_free_audio(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+- enum engine_id id)
++ enum engine_id id,
++ enum dce_version dc_version)
+ {
+ int i, available_audio_count;
+
+@@ -1962,7 +1963,7 @@ enum dc_status resource_map_pool_resources(
+ dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
+ stream->audio_info.mode_count && stream->audio_info.flags.all) {
+ pipe_ctx->stream_res.audio = find_first_free_audio(
+- &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
++ &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
+
+ /*
+ * Audio assigned in order first come first get.
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4244-drm-amd-display-Update-min-dcfclk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4244-drm-amd-display-Update-min-dcfclk.patch
new file mode 100644
index 00000000..e473562b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4244-drm-amd-display-Update-min-dcfclk.patch
@@ -0,0 +1,44 @@
+From c0f19d299a31a816850d57d275d5fd7225844ac1 Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Fri, 27 Sep 2019 12:24:05 -0400
+Subject: [PATCH 4244/4736] drm/amd/display: Update min dcfclk
+
+[Why]
+NV12 has lower min dcfclk
+
+[How]
+Add update in update_bounding_box
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 0ef5c5d60f79..a094eac4dc95 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -3113,10 +3113,14 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
+
+ if (dc->bb_overrides.min_dcfclk_mhz > 0)
+ min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
+- else
+- // Accounting for SOC/DCF relationship, we can go as high as
+- // 506Mhz in Vmin. We need to code 507 since SMU will round down to 506.
+- min_dcfclk = 507;
++ else {
++ if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
++ min_dcfclk = 310;
++ else
++ // Accounting for SOC/DCF relationship, we can go as high as
++ // 506Mhz in Vmin.
++ min_dcfclk = 506;
++ }
+
+ for (i = 0; i < num_states; i++) {
+ int min_fclk_required_by_uclk;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4245-drm-amd-display-Allow-inverted-gamma.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4245-drm-amd-display-Allow-inverted-gamma.patch
new file mode 100644
index 00000000..a40334e4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4245-drm-amd-display-Allow-inverted-gamma.patch
@@ -0,0 +1,77 @@
+From fd51f9ea463e8b3c3f2d9827a8a591b1fd18f838 Mon Sep 17 00:00:00 2001
+From: Aidan Yang <Aidan.Yang@amd.com>
+Date: Wed, 2 Oct 2019 10:47:31 -0400
+Subject: [PATCH 4245/4736] drm/amd/display: Allow inverted gamma
+
+[why]
+There's a use case for inverted gamma
+and it's been confirmed that negative slopes are ok.
+
+[how]
+Remove code for blocking non-monotonically increasing gamma
+
+Signed-off-by: Aidan Yang <Aidan.Yang@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Reza Amini <Reza.Amini@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_cm_common.c | 22 +++++++------------
+ 1 file changed, 8 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+index 01c7e30b9ce1..bbd6e01b3eca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+@@ -393,6 +393,10 @@ bool cm_helper_translate_curve_to_hw_format(
+ rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+ rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+
++ rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
++ rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
++ rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
++
+ // All 3 color channels have same x
+ corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
+ dc_fixpt_from_int(region_start));
+@@ -464,13 +468,6 @@ bool cm_helper_translate_curve_to_hw_format(
+
+ i = 1;
+ while (i != hw_points + 1) {
+- if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
+- rgb_plus_1->red = rgb->red;
+- if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
+- rgb_plus_1->green = rgb->green;
+- if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
+- rgb_plus_1->blue = rgb->blue;
+-
+ rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
+ rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
+ rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
+@@ -562,6 +559,10 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
+ rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+ rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+
++ rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
++ rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
++ rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
++
+ corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
+ dc_fixpt_from_int(region_start));
+ corner_points[0].green.x = corner_points[0].red.x;
+@@ -624,13 +625,6 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
+
+ i = 1;
+ while (i != hw_points + 1) {
+- if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
+- rgb_plus_1->red = rgb->red;
+- if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
+- rgb_plus_1->green = rgb->green;
+- if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
+- rgb_plus_1->blue = rgb->blue;
+-
+ rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
+ rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
+ rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4246-drm-amd-display-enable-vm-by-default-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4246-drm-amd-display-enable-vm-by-default-for-rn.patch
new file mode 100644
index 00000000..13e19170
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4246-drm-amd-display-enable-vm-by-default-for-rn.patch
@@ -0,0 +1,85 @@
+From 414c896e764d9775d404c7dff8e90bbfd48944ff Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Wed, 2 Oct 2019 14:09:06 -0400
+Subject: [PATCH 4246/4736] drm/amd/display: enable vm by default for rn.
+
+[Why & How]
+vm should be enabled by default for rn to get
+right dml.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 29 ++++++++++++++++---
+ 1 file changed, 25 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 47a8955003a5..c5c67cb823ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -83,8 +83,8 @@
+
+ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
+ .odm_capable = 1,
+- .gpuvm_enable = 0,
+- .hostvm_enable = 0,
++ .gpuvm_enable = 1,
++ .hostvm_enable = 1,
+ .gpuvm_max_page_table_levels = 1,
+ .hostvm_max_page_table_levels = 4,
+ .hostvm_cached_page_table_levels = 2,
+@@ -669,6 +669,9 @@ static const struct dcn10_stream_encoder_mask se_mask = {
+
+ static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+
++static int dcn21_populate_dml_pipes_from_context(
++ struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
++
+ static struct input_pixel_processor *dcn21_ipp_create(
+ struct dc_context *ctx, uint32_t inst)
+ {
+@@ -1083,7 +1086,7 @@ void dcn21_calculate_wm(
+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+ &context->res_ctx, pipes);
+ else
+- pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
++ pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
+ &context->res_ctx, pipes);
+ }
+
+@@ -1635,11 +1638,29 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ return value;
+ }
+
++static int dcn21_populate_dml_pipes_from_context(
++ struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
++{
++ uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, pipes);
++ int i;
++
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
++
++ if (!res_ctx->pipe_ctx[i].stream)
++ continue;
++
++ pipes[i].pipe.src.hostvm = 1;
++ pipes[i].pipe.src.gpuvm = 1;
++ }
++
++ return pipe_cnt;
++}
++
+ static struct resource_funcs dcn21_res_pool_funcs = {
+ .destroy = dcn21_destroy_resource_pool,
+ .link_enc_create = dcn21_link_encoder_create,
+ .validate_bandwidth = dcn21_validate_bandwidth,
+- .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
++ .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
+ .add_stream_to_ctx = dcn20_add_stream_to_ctx,
+ .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+ .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4247-drm-amd-display-fix-number-of-dcn21-dpm-clock-levels.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4247-drm-amd-display-fix-number-of-dcn21-dpm-clock-levels.patch
new file mode 100644
index 00000000..8ca1deee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4247-drm-amd-display-fix-number-of-dcn21-dpm-clock-levels.patch
@@ -0,0 +1,34 @@
+From bcd12b314c04a6585ae32353612874158493f92d Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 1 Oct 2019 11:01:00 -0400
+Subject: [PATCH 4247/4736] drm/amd/display: fix number of dcn21 dpm clock
+ levels
+
+These are specific to dcn21 and should not be increased for
+reuse on other asics.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 60d6620530a8..95f3193da951 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -245,8 +245,8 @@ struct pp_smu_funcs_nv {
+
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
+-#define PP_SMU_NUM_FCLK_DPM_LEVELS 8
+-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8
++#define PP_SMU_NUM_FCLK_DPM_LEVELS 4
++#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
+
+ struct dpm_clock {
+ uint32_t Freq; // In MHz
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4248-drm-amd-display-add-embedded-flag-to-dml.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4248-drm-amd-display-add-embedded-flag-to-dml.patch
new file mode 100644
index 00000000..8d80c22e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4248-drm-amd-display-add-embedded-flag-to-dml.patch
@@ -0,0 +1,53 @@
+From 516fc8ba1c91bfb9fd317d4bc1e4bf75048e8e1c Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 1 Oct 2019 16:08:31 -0400
+Subject: [PATCH 4248/4736] drm/amd/display: add embedded flag to dml
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index 83f84cdd4055..cfacd6027467 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -318,6 +318,7 @@ struct _vcs_dpi_display_pipe_dest_params_st {
+ unsigned int vupdate_width;
+ unsigned int vready_offset;
+ unsigned char interlaced;
++ unsigned char embedded;
+ double pixel_rate_mhz;
+ unsigned char synchronized_vblank_all_planes;
+ unsigned char otg_inst;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 038701d7383d..7f9a5621922f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -375,6 +375,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+
+ mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;
+
++ mode_lib->vba.EmbeddedPanel[mode_lib->vba.NumberOfActivePlanes] = dst->embedded;
+ mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;
+ mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
+ (enum scan_direction_class) (src->source_scan);
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 91decac50557..1540ffbe3979 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -387,6 +387,7 @@ struct vba_vars_st {
+
+ /* vba mode support */
+ /*inputs*/
++ bool EmbeddedPanel[DC__NUM_DPP__MAX];
+ bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
+ double MaxHSCLRatio;
+ double MaxVSCLRatio;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4249-drm-amd-display-add-flag-to-allow-diag-to-force-enum.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4249-drm-amd-display-add-flag-to-allow-diag-to-force-enum.patch
new file mode 100644
index 00000000..10635a7a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4249-drm-amd-display-add-flag-to-allow-diag-to-force-enum.patch
@@ -0,0 +1,49 @@
+From 84f08f4a0536fa2ff71442d177f1dc066431c377 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Tue, 1 Oct 2019 11:31:37 -0400
+Subject: [PATCH 4249/4736] drm/amd/display: add flag to allow diag to force
+ enumerate edp
+
+[why]
+SLT tests require that diag can drive eDP even if nothing is connected, this is not
+typical production use case, so we need to add flag
+
+[how]
+add flag, and this flag supercedes "should destroy" logic
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dc.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index bd623404772d..072ac5e5e99a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -191,7 +191,7 @@ static bool create_links(
+ }
+ }
+
+- if (!should_destory_link) {
++ if (dc->config.force_enum_edp || !should_destory_link) {
+ dc->links[dc->link_count] = link;
+ link->dc = dc;
+ ++dc->link_count;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index a86dad3808b6..b578b2148e45 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -220,6 +220,7 @@ struct dc_config {
+ bool allow_seamless_boot_optimization;
+ bool power_down_display_on_boot;
+ bool edp_not_connected;
++ bool force_enum_edp;
+ bool forced_clocks;
+ bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well
+ bool multi_mon_pp_mclk_switch;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4250-drm-amd-display-Passive-DP-HDMI-dongle-detection-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4250-drm-amd-display-Passive-DP-HDMI-dongle-detection-fix.patch
new file mode 100644
index 00000000..e83601c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4250-drm-amd-display-Passive-DP-HDMI-dongle-detection-fix.patch
@@ -0,0 +1,67 @@
+From e926130b39049167cc8f9f52fb87b32a787c86c0 Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Thu, 3 Oct 2019 11:54:15 -0400
+Subject: [PATCH 4250/4736] drm/amd/display: Passive DP->HDMI dongle detection
+ fix
+
+[WHY]
+i2c_read is called to differentiate passive DP->HDMI and DP->DVI-D dongles
+The call is expected to fail in DVI-D case but pass in HDMI case
+Some HDMI dongles have a chance to fail as well, causing misdetection as DVI-D
+
+[HOW]
+Retry i2c_read to ensure failed result is valid
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 24 ++++++++++++++-----
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 580594be1de5..d98640f49874 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -372,6 +372,7 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
+ enum display_dongle_type *dongle = &sink_cap->dongle_type;
+ uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
+ bool is_type2_dongle = false;
++ int retry_count = 2;
+ struct dp_hdmi_dongle_signature_data *dongle_signature;
+
+ /* Assume we have no valid DP passive dongle connected */
+@@ -384,13 +385,24 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
+ DP_HDMI_DONGLE_ADDRESS,
+ type2_dongle_buf,
+ sizeof(type2_dongle_buf))) {
+- *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
+- sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
++ /* Passive HDMI dongles can sometimes fail here without retrying*/
++ while (retry_count > 0) {
++ if (i2c_read(ddc,
++ DP_HDMI_DONGLE_ADDRESS,
++ type2_dongle_buf,
++ sizeof(type2_dongle_buf)))
++ break;
++ retry_count--;
++ }
++ if (retry_count == 0) {
++ *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
++ sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
+
+- CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
+- "DP-DVI passive dongle %dMhz: ",
+- DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
+- return;
++ CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
++ "DP-DVI passive dongle %dMhz: ",
++ DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
++ return;
++ }
+ }
+
+ /* Check if Type 2 dongle.*/
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4251-drm-amd-display-Disable-force_single_disp_pipe_split.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4251-drm-amd-display-Disable-force_single_disp_pipe_split.patch
new file mode 100644
index 00000000..e7f4097d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4251-drm-amd-display-Disable-force_single_disp_pipe_split.patch
@@ -0,0 +1,48 @@
+From 46de063efa708713349a25fb1731d2f5006fa55d Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Tue, 1 Oct 2019 12:04:16 -0400
+Subject: [PATCH 4251/4736] drm/amd/display: Disable
+ force_single_disp_pipe_split on DCN2+
+
+[WHY]
+force_single_disp_pipe_split is a debug flag for use on DCN1
+but isn't necessary otherwise as DCN2+ splits by default
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index a094eac4dc95..b5b085aeef2b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -834,7 +834,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ .clock_trace = true,
+ .disable_pplib_clock_request = true,
+ .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+- .force_single_disp_pipe_split = true,
++ .force_single_disp_pipe_split = false,
+ .disable_dcc = DCC_ENABLE,
+ .vsr_support = true,
+ .performance_trace = false,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index c5c67cb823ac..51f23680244a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -836,7 +836,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ .clock_trace = true,
+ .disable_pplib_clock_request = true,
+ .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+- .force_single_disp_pipe_split = true,
++ .force_single_disp_pipe_split = false,
+ .disable_dcc = DCC_ENABLE,
+ .vsr_support = true,
+ .performance_trace = false,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4252-drm-amd-display-Proper-return-of-result-when-aux-eng.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4252-drm-amd-display-Proper-return-of-result-when-aux-eng.patch
new file mode 100644
index 00000000..96a9998e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4252-drm-amd-display-Proper-return-of-result-when-aux-eng.patch
@@ -0,0 +1,77 @@
+From 028bb6e29c093f31f569f7e129229312f25b7e7d Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Wed, 2 Oct 2019 12:22:29 -0400
+Subject: [PATCH 4252/4736] drm/amd/display: Proper return of result when aux
+ engine acquire fails
+
+[Why]
+When aux engine acquire fails, we missed populating the operation_result
+that describes the failure reason.
+
+[How]
+Set operation_result to new type:
+AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
+in the case aux engine acquire has failed.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 5 ++++-
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index 430155730c29..c765fcbd1386 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -113,6 +113,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
+ result = -EIO;
+ break;
+ case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
++ case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
+ result = -EBUSY;
+ break;
+ case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+index 4ef97f65e55d..4f8f576d5fcf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+@@ -49,7 +49,8 @@ enum aux_channel_operation_result {
+ AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
+ AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
+ AUX_CHANNEL_OPERATION_FAILED_TIMEOUT,
+- AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
++ AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON,
++ AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
+ };
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index a68edd0c2172..3c3830f7908f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -535,8 +535,10 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
+ memset(&aux_rep, 0, sizeof(aux_rep));
+
+ aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+- if (!acquire(aux_engine, ddc_pin))
++ if (!acquire(aux_engine, ddc_pin)) {
++ *operation_result = AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE;
+ return -1;
++ }
+
+ if (payload->i2c_over_aux)
+ aux_req.type = AUX_TRANSACTION_TYPE_I2C;
+@@ -660,6 +662,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ break;
+
+ case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
++ case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
+ case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
+ default:
+ goto fail;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4253-drm-amd-display-do-not-synchronize-drr-displays.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4253-drm-amd-display-do-not-synchronize-drr-displays.patch
new file mode 100644
index 00000000..832f216f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4253-drm-amd-display-do-not-synchronize-drr-displays.patch
@@ -0,0 +1,52 @@
+From 53020e71768ea377f2ab79c94ee7a45d6d6b7565 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Thu, 3 Oct 2019 15:09:53 -0400
+Subject: [PATCH 4253/4736] drm/amd/display: do not synchronize "drr" displays
+
+[why]
+A display that supports DRR can never really be considered
+"synchronized" with any other display because we can dynamically
+enable DRR (i.e. without modeset). this will cause their
+relative CRTC positions to drift and lose sync. this will disrupt
+features such as MCLK switching that assume and depend on
+their permanent alignment (that can only change with modeset)
+
+[how]
+check for ignore_msa in stream when considered synchronizability
+this ignore_msa is basically actually implemented as "supports drr"
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 66a910ac3cbd..4154f1eedece 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -401,6 +401,9 @@ bool resource_are_streams_timing_synchronizable(
+ if (stream1->view_format != stream2->view_format)
+ return false;
+
++ if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
++ return false;
++
+ return true;
+ }
+ static bool is_dp_and_hdmi_sharable(
+@@ -1537,6 +1540,9 @@ bool dc_is_stream_unchanged(
+ if (!are_stream_backends_same(old_stream, stream))
+ return false;
+
++ if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
++ return false;
++
+ return true;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4254-drm-amd-display-move-wm-ranges-reporting-to-end-of-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4254-drm-amd-display-move-wm-ranges-reporting-to-end-of-i.patch
new file mode 100644
index 00000000..4bfe3379
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4254-drm-amd-display-move-wm-ranges-reporting-to-end-of-i.patch
@@ -0,0 +1,231 @@
+From 9660422158b380fa32fd18ba9d56424ced83d18c Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Tue, 24 Sep 2019 12:02:38 -0400
+Subject: [PATCH 4254/4736] drm/amd/display: move wm ranges reporting to end of
+ init hw
+
+[Why]
+SMU does not keep the wm table across S3, S4, need to re-send
+the table. Also defer sending the cable to after DCN bave initialized
+
+[How]
+Send table at end of init hw
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 149 +++++++++---------
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 +
+ 3 files changed, 81 insertions(+), 73 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index e8b8ee4f1b1e..f64d221ad6f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -396,12 +396,87 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
+ clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+ }
+
++void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
++{
++ int i, num_valid_sets;
++
++ num_valid_sets = 0;
++
++ for (i = 0; i < WM_SET_COUNT; i++) {
++ /* skip empty entries, the smu array has no holes*/
++ if (!bw_params->wm_table.entries[i].valid)
++ continue;
++
++ ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
++ ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;;
++ /* We will not select WM based on dcfclk, so leave it as unconstrained */
++ ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++ ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++ /* fclk wil be used to select WM*/
++
++ if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
++ if (i == 0)
++ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
++ else {
++ /* add 1 to make it non-overlapping with next lvl */
++ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
++ }
++ ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
++
++ } else {
++ /* unconstrained for memory retraining */
++ ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++ ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++ /* Modify previous watermark range to cover up to max */
++ ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++ }
++ num_valid_sets++;
++ }
++
++ ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
++ ranges->num_reader_wm_sets = num_valid_sets;
++
++ /* modify the min and max to make sure we cover the whole range*/
++ ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++ ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++ ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++ ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++ /* This is for writeback only, does not matter currently as no writeback support*/
++ ranges->num_writer_wm_sets = 1;
++ ranges->writer_wm_sets[0].wm_inst = WM_A;
++ ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++ ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++ ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++ ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++}
++
++static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
++{
++ struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
++ struct pp_smu_wm_range_sets ranges = {0};
++ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++ struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
++
++ if (!debug->disable_pplib_wm_range) {
++ build_watermark_ranges(clk_mgr_base->bw_params, &ranges);
++
++ /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
++ if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
++ pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
++ }
++
++}
++
+ static struct clk_mgr_funcs dcn21_funcs = {
+ .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ .update_clocks = rn_update_clocks,
+ .init_clocks = rn_init_clocks,
+ .enable_pme_wa = rn_enable_pme_wa,
+- /* .dump_clk_registers = rn_dump_clk_registers */
++ /* .dump_clk_registers = rn_dump_clk_registers, */
++ .notify_wm_ranges = rn_notify_wm_ranges
+ };
+
+ struct clk_bw_params rn_bw_params = {
+@@ -472,63 +547,6 @@ struct clk_bw_params rn_bw_params = {
+ }
+ };
+
+-static void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
+-{
+- int i, num_valid_sets;
+-
+- num_valid_sets = 0;
+-
+- for (i = 0; i < WM_SET_COUNT; i++) {
+- /* skip empty entries, the smu array has no holes*/
+- if (!bw_params->wm_table.entries[i].valid)
+- continue;
+-
+- ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
+- ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;;
+- /* We will not select WM based on dcfclk, so leave it as unconstrained */
+- ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+- ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+- /* fclk wil be used to select WM*/
+-
+- if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
+- if (i == 0)
+- ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
+- else {
+- /* add 1 to make it non-overlapping with next lvl */
+- ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
+- }
+- ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
+-
+- } else {
+- /* unconstrained for memory retraining */
+- ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+- ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-
+- /* Modify previous watermark range to cover up to max */
+- ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+- }
+- num_valid_sets++;
+- }
+-
+- ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
+- ranges->num_reader_wm_sets = num_valid_sets;
+-
+- /* modify the min and max to make sure we cover the whole range*/
+- ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+- ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+- ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+- ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-
+- /* This is for writeback only, does not matter currently as no writeback support*/
+- ranges->num_writer_wm_sets = 1;
+- ranges->writer_wm_sets[0].wm_inst = WM_A;
+- ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+- ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+- ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+- ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-
+-}
+-
+ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
+ {
+ int i;
+@@ -661,21 +679,6 @@ void rn_clk_mgr_construct(
+ rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
+ }
+
+- /*
+- * Notify SMU which set of WM should be selected for different ranges of fclk
+- * On Renoir there is a maximumum of 4 DF pstates supported, could be less
+- * depending on DDR speed and fused maximum fclk.
+- */
+- if (!debug->disable_pplib_wm_range) {
+- struct pp_smu_wm_range_sets ranges = {0};
+-
+- rn_build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
+-
+- /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
+- if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
+- pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
+- }
+-
+ if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
+ /* enable powerfeatures when displaycount goes to 0 */
+ rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 7c02f646feed..b61cc211e659 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1303,6 +1303,10 @@ static void dcn10_init_hw(struct dc *dc)
+ }
+
+ dc->hwss.enable_power_gating_plane(dc->hwseq, true);
++
++ if (dc->clk_mgr->funcs->notify_wm_ranges)
++ dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
++
+ }
+
+ static void dcn10_reset_hw_ctx_wrap(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index da43523a7bfe..4e18e77dcf42 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -183,6 +183,7 @@ struct clk_mgr_funcs {
+
+ bool (*are_clock_states_equal) (struct dc_clocks *a,
+ struct dc_clocks *b);
++ void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
+ };
+
+ struct clk_mgr {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4255-drm-amd-display-Only-use-EETF-when-maxCL-max-display.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4255-drm-amd-display-Only-use-EETF-when-maxCL-max-display.patch
new file mode 100644
index 00000000..a55b89c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4255-drm-amd-display-Only-use-EETF-when-maxCL-max-display.patch
@@ -0,0 +1,43 @@
+From ccd1cf77b10a987d5287b07fef6fcb21cc647b42 Mon Sep 17 00:00:00 2001
+From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Date: Fri, 4 Oct 2019 13:49:03 -0400
+Subject: [PATCH 4255/4736] drm/amd/display: Only use EETF when maxCL > max
+ display
+
+[Why&How]
+BT.2390 EETF is used for tone mapping/range reduction.
+Say display is 0.1 - 500 nits.
+The problematic case is when content is 0-400. We apply EETF because
+0<0.1 so we need to reduce the range by 0.1.
+
+In the commit, we ignore the bottom range. Most displays map 0 to min and
+then have a ramp to 0.1, so sending 0.1 is actually >0.1.
+Furthermode, HW that uses 3D LUT also assumes min=0.
+
+Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 0accdae5e675..962a57f75e12 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -956,11 +956,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ if (fs_params->max_display < 100) // cap at 100 at the top
+ max_display = dc_fixpt_from_int(100);
+
+- if (fs_params->min_content < fs_params->min_display)
+- use_eetf = true;
+- else
+- min_content = min_display;
+-
++ // only max used, we don't adjust min luminance
+ if (fs_params->max_content > fs_params->max_display)
+ use_eetf = true;
+ else
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4256-drm-amd-display-Make-clk-mgr-the-only-dto-update-poi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4256-drm-amd-display-Make-clk-mgr-the-only-dto-update-poi.patch
new file mode 100644
index 00000000..b5339e48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4256-drm-amd-display-Make-clk-mgr-the-only-dto-update-poi.patch
@@ -0,0 +1,135 @@
+From 45cd082ac07baee76c1abdeb52dbae610fe51a5b Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Fri, 27 Sep 2019 16:30:57 -0400
+Subject: [PATCH 4256/4736] drm/amd/display: Make clk mgr the only dto update
+ point
+
+[Why]
+
+* Clk Mgr DTO update point did not cover all needed updates, as it included a
+ check for plane_state which does not exist yet when the updater is called on
+ driver startup
+* This resulted in another update path in the pipe programming sequence, based
+ on a dppclk update flag
+* However, this alternate path allowed for stray DTO updates, some of which would
+ occur in the wrong order during dppclk lowering and cause underflow
+
+[How]
+
+* Remove plane_state check and use of plane_res.dpp->inst, getting rid
+ of sequence dependencies (this results in extra dto programming for unused
+ pipes but that doesn't cause issues and is a small cost)
+* Allow DTOs to be updated even if global clock is equal, to account for
+ edge case exposed by diags tests
+* Remove update_dpp_dto call in pipe programming sequence (leave update to
+ dppclk_control there, as that update is necessary and shouldn't occur in clk
+ mgr)
+* Remove call to optimize_bandwidth when committing state, as it is not needed
+ and resulted in sporadic underflows even with other fixes in place
+
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 14 +++++++++-----
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ----
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 8 +-------
+ 4 files changed, 12 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 607d8afc56ec..25d7b7c6681c 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -108,11 +108,12 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+ int dpp_inst, dppclk_khz;
+
+- if (!context->res_ctx.pipe_ctx[i].plane_state)
+- continue;
+-
+- dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
++ /* Loop index will match dpp->inst if resource exists,
++ * and we want to avoid dependency on dpp object
++ */
++ dpp_inst = i;
+ dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
++
+ clk_mgr->dccg->funcs->update_dpp_dto(
+ clk_mgr->dccg, dpp_inst, dppclk_khz);
+ }
+@@ -235,6 +236,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+
+ update_dispclk = true;
+ }
++
+ if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
+ if (dpp_clock_lowered) {
+ // if clock is being lowered, increase DTO before lowering refclk
+@@ -244,10 +246,12 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ // if clock is being raised, increase refclk before lowering DTO
+ if (update_dppclk || update_dispclk)
+ dcn20_update_clocks_update_dentist(clk_mgr);
+- if (update_dppclk)
++ // always update dtos unless clock is lowered and not safe to lower
++ if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+ dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ }
+ }
++
+ if (update_dispclk &&
+ dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ /*update dmcu for wait_loop count*/
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index f64d221ad6f1..790a2d211bd6 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -171,7 +171,8 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
+ // if clock is being raised, increase refclk before lowering DTO
+ if (update_dppclk || update_dispclk)
+ rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+- if (update_dppclk)
++ // always update dtos unless clock is lowered and not safe to lower
++ if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+ dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 072ac5e5e99a..3d38e7e071a4 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1238,10 +1238,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+
+ dc_enable_stereo(dc, context, dc_streams, context->stream_count);
+
+- if (!dc->optimize_seamless_boot)
+- /* pplib is notified if disp_num changed */
+- dc->hwss.optimize_bandwidth(dc, context);
+-
+ for (i = 0; i < context->stream_count; i++)
+ context->streams[i]->mode_changed = false;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index e237ec39d193..921a36668ced 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1202,15 +1202,9 @@ static void dcn20_update_dchubp_dpp(
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+
+- if (pipe_ctx->update_flags.bits.dppclk) {
++ if (pipe_ctx->update_flags.bits.dppclk)
+ dpp->funcs->dpp_dppclk_control(dpp, false, true);
+
+- dc->res_pool->dccg->funcs->update_dpp_dto(
+- dc->res_pool->dccg,
+- dpp->inst,
+- pipe_ctx->plane_res.bw.dppclk_khz);
+- }
+-
+ /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
+ * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
+ * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4257-drm-amd-display-3.2.56.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4257-drm-amd-display-3.2.56.patch
new file mode 100644
index 00000000..3318974d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4257-drm-amd-display-3.2.56.patch
@@ -0,0 +1,27 @@
+From 70d7f35b7fcfabd58e68598560a498572b1312d6 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sun, 6 Oct 2019 23:21:07 -0400
+Subject: [PATCH 4257/4736] drm/amd/display: 3.2.56
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b578b2148e45..0416a17b0897 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.55"
++#define DC_VER "3.2.56"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4258-drm-amd-display-take-signal-type-from-link.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4258-drm-amd-display-take-signal-type-from-link.patch
new file mode 100644
index 00000000..c8aec992
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4258-drm-amd-display-take-signal-type-from-link.patch
@@ -0,0 +1,56 @@
+From 2d6d7bd8a7b1cbbb60f5a4233e389ee45d278973 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Thu, 3 Oct 2019 16:01:25 +0800
+Subject: [PATCH 4258/4736] drm/amd/display: take signal type from link
+
+[Why]
+Signal is update to EDP when driver disable first encoder. The
+following encoder using SIGNAL_TYPE_EDP to handle other
+device. When encoder signal is HDMI, driver will detect it is dp
+and release phy. It cause hw hang.
+
+[How]
+Take signal type from link->connector_signal.
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index d1e14393a0f0..0d171874ef4e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1418,8 +1418,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ static void power_down_encoders(struct dc *dc)
+ {
+ int i;
+- enum connector_id connector_id;
+- enum signal_type signal = SIGNAL_TYPE_NONE;
+
+ /* do not know BIOS back-front mapping, simply blank all. It will not
+ * hurt for non-DP
+@@ -1430,15 +1428,12 @@ static void power_down_encoders(struct dc *dc)
+ }
+
+ for (i = 0; i < dc->link_count; i++) {
+- connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
+- if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
+- (connector_id == CONNECTOR_ID_EDP)) {
++ enum signal_type signal = dc->links[i]->connector_signal;
+
++ if ((signal == SIGNAL_TYPE_EDP) ||
++ (signal == SIGNAL_TYPE_DISPLAY_PORT))
+ if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
+ dp_receiver_power_ctrl(dc->links[i], false);
+- if (connector_id == CONNECTOR_ID_EDP)
+- signal = SIGNAL_TYPE_EDP;
+- }
+
+ dc->links[i]->link_enc->funcs->disable_output(
+ dc->links[i]->link_enc, signal);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4259-drm-amd-display-Add-center-mode-for-integer-scaling-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4259-drm-amd-display-Add-center-mode-for-integer-scaling-.patch
new file mode 100644
index 00000000..18d2ca37
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4259-drm-amd-display-Add-center-mode-for-integer-scaling-.patch
@@ -0,0 +1,98 @@
+From 9512f38631a80c41fad301c2a9bd58fe45b35798 Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Mon, 30 Sep 2019 10:11:24 -0400
+Subject: [PATCH 4259/4736] drm/amd/display: Add center mode for integer
+ scaling in DC
+
+[why]
+We want to use maximum space on display to show source
+
+[how]
+For Centered Mode: Replicate source as many times as possible to use
+maximum of display active space add borders.
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 43 +++++++++++++++----
+ 1 file changed, 35 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 4154f1eedece..e8b16b4acacc 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -948,7 +948,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
+ data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
+
+ }
+-static bool are_rect_integer_multiples(struct rect src, struct rect dest)
++static bool are_rects_integer_multiples(struct rect src, struct rect dest)
+ {
+ if (dest.width >= src.width && dest.width % src.width == 0 &&
+ dest.height >= src.height && dest.height % src.height == 0)
+@@ -956,6 +956,38 @@ static bool are_rect_integer_multiples(struct rect src, struct rect dest)
+
+ return false;
+ }
++
++void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
++{
++ if (!pipe_ctx->plane_state->scaling_quality.integer_scaling)
++ return;
++
++ //for Centered Mode
++ if (pipe_ctx->stream->dst.width == pipe_ctx->stream->src.width &&
++ pipe_ctx->stream->dst.height == pipe_ctx->stream->src.height) {
++ // calculate maximum # of replication of src onto addressable
++ unsigned int integer_multiple = min(
++ pipe_ctx->stream->timing.h_addressable / pipe_ctx->stream->src.width,
++ pipe_ctx->stream->timing.v_addressable / pipe_ctx->stream->src.height);
++
++ //scale dst
++ pipe_ctx->stream->dst.width = integer_multiple * pipe_ctx->stream->src.width;
++ pipe_ctx->stream->dst.height = integer_multiple * pipe_ctx->stream->src.height;
++
++ //center dst onto addressable
++ pipe_ctx->stream->dst.x = (pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
++ pipe_ctx->stream->dst.y = (pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
++ }
++
++ //disable taps if src & dst are integer ratio
++ if (are_rects_integer_multiples(pipe_ctx->stream->src, pipe_ctx->stream->dst)) {
++ pipe_ctx->plane_state->scaling_quality.v_taps = 1;
++ pipe_ctx->plane_state->scaling_quality.h_taps = 1;
++ pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
++ pipe_ctx->plane_state->scaling_quality.h_taps_c = 1;
++ }
++}
++
+ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ {
+ const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+@@ -969,6 +1001,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
+ pipe_ctx->plane_state->format);
+
++ calculate_integer_scaling(pipe_ctx);
++
+ calculate_scaling_ratios(pipe_ctx);
+
+ calculate_viewport(pipe_ctx);
+@@ -999,13 +1033,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
+ pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
+
+- if (res &&
+- plane_state->scaling_quality.integer_scaling &&
+- are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
+- pipe_ctx->plane_res.scl_data.recout)) {
+- pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
+- pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
+- }
+
+ if (!res) {
+ /* Try 24 bpp linebuffer */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4260-drm-amd-display-Do-not-call-update-bounding-box-on-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4260-drm-amd-display-Do-not-call-update-bounding-box-on-d.patch
new file mode 100644
index 00000000..fedc85cf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4260-drm-amd-display-Do-not-call-update-bounding-box-on-d.patch
@@ -0,0 +1,57 @@
+From 0caa5e8f858285f13345c2898ca9c9b680b978a6 Mon Sep 17 00:00:00 2001
+From: Sung Lee <sung.lee@amd.com>
+Date: Mon, 7 Oct 2019 12:05:34 -0400
+Subject: [PATCH 4260/4736] drm/amd/display: Do not call update bounding box on
+ dc create
+
+[Why]
+In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP.
+This causes an issue on dc init where dcn2_1_soc which has been
+updated by update_bw_bounding_box gets put into dml->soc.
+As update_bw_bounding_box is currently incorrect for dcn2.1,
+this makes dml calculations fail due to incorrect parameters,
+leading to a crash on PnP.
+
+[How]
+Comment out update_bw_bounding_box call for now.
+
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 51f23680244a..910c850701af 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1336,6 +1336,12 @@ struct display_stream_compressor *dcn21_dsc_create(
+
+ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+ {
++ /*
++ TODO: Fix this function to calcualte correct values.
++ There are known issues with this function currently
++ that will need to be investigated. Use hardcoded known good values for now.
++
++
+ struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
+ struct clk_limit_table *clk_table = &bw_params->clk_table;
+ int i;
+@@ -1350,11 +1356,11 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
+ dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+ dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+- /* This is probably wrong, TODO: find correct calculation */
+ dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
+ }
+ dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
+ dcn2_1_soc.num_states = i;
++ */
+ }
+
+ /* Temporary Place holder until we can get them from fuse */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4261-drm-amd-display-fix-avoid_split-for-dcn2-validation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4261-drm-amd-display-fix-avoid_split-for-dcn2-validation.patch
new file mode 100644
index 00000000..9b6d53ac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4261-drm-amd-display-fix-avoid_split-for-dcn2-validation.patch
@@ -0,0 +1,64 @@
+From 98fd9d8313513693c43106e77d5cabd3cb63f6b2 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 8 Oct 2019 12:53:19 -0400
+Subject: [PATCH 4261/4736] drm/amd/display: fix avoid_split for dcn2+
+ validation
+
+We are currently incorrectly processing avoid split at highest
+voltage level.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index b5b085aeef2b..9c96242f0ad9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2355,10 +2355,11 @@ int dcn20_validate_apply_pipe_split_flags(
+ int vlevel,
+ bool *split)
+ {
+- int i, pipe_idx, vlevel_unsplit;
++ int i, pipe_idx, vlevel_split;
+ bool force_split = false;
+ bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+
++ /* Single display loop, exits if there is more than one display */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ bool exit_loop = false;
+@@ -2389,22 +2390,24 @@ int dcn20_validate_apply_pipe_split_flags(
+ if (context->stream_count > dc->res_pool->pipe_count / 2)
+ avoid_split = true;
+
++ /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
+ if (avoid_split) {
+ for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ if (!context->res_ctx.pipe_ctx[i].stream)
+ continue;
+
+- for (vlevel_unsplit = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
++ for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
+ if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
+ break;
+ /* Impossible to not split this pipe */
+- if (vlevel == context->bw_ctx.dml.soc.num_states)
+- vlevel = vlevel_unsplit;
++ if (vlevel > context->bw_ctx.dml.soc.num_states)
++ vlevel = vlevel_split;
+ pipe_idx++;
+ }
+ context->bw_ctx.dml.vba.maxMpcComb = 0;
+ }
+
++ /* Split loop sets which pipe should be split based on dml outputs and dc flags */
+ for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4262-drm-amd-display-fix-hubbub-deadline-programing.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4262-drm-amd-display-fix-hubbub-deadline-programing.patch
new file mode 100644
index 00000000..03552f62
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4262-drm-amd-display-fix-hubbub-deadline-programing.patch
@@ -0,0 +1,44 @@
+From 3e524c60423cee992127ddc9487298a65bffb782 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Thu, 10 Oct 2019 11:25:48 -0400
+Subject: [PATCH 4262/4736] drm/amd/display: fix hubbub deadline programing
+
+[Why]
+Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A.
+Was not filled in.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 9c96242f0ad9..b6ec81096d3a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2632,6 +2632,7 @@ static void dcn20_calculate_wm(
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++ context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ #endif
+
+ if (vlevel < 2) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 910c850701af..ff32c7380efb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1009,6 +1009,7 @@ static void calculate_wm_set_for_vlevel(
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
+ wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
++ wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
+ #endif
+ dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4263-drm-amd-display-Apply-vactive-dram-clock-change-work.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4263-drm-amd-display-Apply-vactive-dram-clock-change-work.patch
new file mode 100644
index 00000000..01984706
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4263-drm-amd-display-Apply-vactive-dram-clock-change-work.patch
@@ -0,0 +1,33 @@
+From b1e8156d48159d180922edeb7083e491477ebcca Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Fri, 11 Oct 2019 15:49:07 -0400
+Subject: [PATCH 4263/4736] drm/amd/display: Apply vactive dram clock change
+ workaround to dcn2 DMLv2
+
+[Why]
+This workaround was put in dcn2 DMLv1, and now we need it in DMLv2.
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 841ed6c23f93..3c70dd577292 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2611,7 +2611,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ mode_lib->vba.MinActiveDRAMClockChangeMargin
+ + mode_lib->vba.DRAMClockChangeLatency;
+
+- if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++ mode_lib->vba.DRAMClockChangeWatermark += 25;
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else {
+ if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4264-drm-amdgpu-vcn-Enable-VCN2.5-encoding.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4264-drm-amdgpu-vcn-Enable-VCN2.5-encoding.patch
new file mode 100644
index 00000000..bdad93ff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4264-drm-amdgpu-vcn-Enable-VCN2.5-encoding.patch
@@ -0,0 +1,35 @@
+From f263c1b507bfcd6050838e722537cf72c2efe0a1 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 22 Oct 2019 10:40:45 -0400
+Subject: [PATCH 4264/4736] drm/amdgpu/vcn: Enable VCN2.5 encoding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+After VCN2.5 firmware (Version ENC: 1.1 Revision: 11),
+VCN2.5 encoding can work properly.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index d270df892223..ff6cc77ad0b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -265,9 +265,6 @@ static int vcn_v2_5_hw_init(void *handle)
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ ring = &adev->vcn.inst[j].ring_enc[i];
+- /* disable encode rings till the robustness of the FW */
+- ring->sched.ready = false;
+- continue;
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4265-drm-amdgpu-add-VCN0-and-VCN1-needed-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4265-drm-amdgpu-add-VCN0-and-VCN1-needed-headers.patch
new file mode 100644
index 00000000..6d99cb7a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4265-drm-amdgpu-add-VCN0-and-VCN1-needed-headers.patch
@@ -0,0 +1,39 @@
+From d2bb67b8b61d4da39441647cf483eff12f1b1dc2 Mon Sep 17 00:00:00 2001
+From: Jane Jian <jane.jian@amd.com>
+Date: Thu, 17 Oct 2019 23:30:20 +0800
+Subject: [PATCH 4265/4736] drm/amdgpu: add VCN0 and VCN1 needed headers
+
+Add mmsch part registers
+
+Signed-off-by: Jane Jian <jane.jian@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
+index cf2149cc12ee..90350f46a0c4 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
+@@ -24,6 +24,18 @@
+
+ // addressBlock: uvd0_mmsch_dec
+ // base address: 0x1e000
++#define mmMMSCH_VF_VMID 0x000b
++#define mmMMSCH_VF_VMID_BASE_IDX 0
++#define mmMMSCH_VF_CTX_ADDR_LO 0x000c
++#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
++#define mmMMSCH_VF_CTX_ADDR_HI 0x000d
++#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
++#define mmMMSCH_VF_CTX_SIZE 0x000e
++#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0
++#define mmMMSCH_VF_MAILBOX_HOST 0x0012
++#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
++#define mmMMSCH_VF_MAILBOX_RESP 0x0013
++#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
+
+
+ // addressBlock: uvd0_jpegnpdec
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4266-drm-amd-powerplay-add-lock-protection-for-swSMU-APIs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4266-drm-amd-powerplay-add-lock-protection-for-swSMU-APIs.patch
new file mode 100644
index 00000000..cbfdf0d1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4266-drm-amd-powerplay-add-lock-protection-for-swSMU-APIs.patch
@@ -0,0 +1,1829 @@
+From dc6cf14a58b1339db33016faef4de4f2efbb300a Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 16 Oct 2019 14:43:07 +0800
+Subject: [PATCH 4266/4736] drm/amd/powerplay: add lock protection for swSMU
+ APIs V2
+
+This is a quick and low risk fix. Those APIs which
+are exposed to other IPs or to support sysfs/hwmon
+interfaces or DAL will have lock protection. Meanwhile
+no lock protection is enforced for swSMU internal used
+APIs. Future optimization is needed.
+
+V2: strip the lock protection for all swSMU internal APIs
+
+Change-Id: I8392652c9da1574a85acd9b171f04380f3630852
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 6 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 23 +-
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 6 +-
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 700 ++++++++++++++++--
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 -
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 162 ++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 15 +-
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 14 +-
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 22 +-
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 -
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 20 +-
+ 12 files changed, 781 insertions(+), 199 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+index 263265245e19..28d32725285b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+@@ -912,7 +912,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
+ if (is_support_sw_smu(adev)) {
+ ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
+ low ? &clk_freq : NULL,
+- !low ? &clk_freq : NULL);
++ !low ? &clk_freq : NULL,
++ true);
+ if (ret)
+ return 0;
+ return clk_freq * 100;
+@@ -930,7 +931,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
+ if (is_support_sw_smu(adev)) {
+ ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
+ low ? &clk_freq : NULL,
+- !low ? &clk_freq : NULL);
++ !low ? &clk_freq : NULL,
++ true);
+ if (ret)
+ return 0;
+ return clk_freq * 100;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+index 1c5c0fd76dbf..2cfb677272af 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+@@ -298,12 +298,6 @@ enum amdgpu_pcie_gen {
+ #define amdgpu_dpm_get_current_power_state(adev) \
+ ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
+
+-#define amdgpu_smu_get_current_power_state(adev) \
+- ((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
+-
+-#define amdgpu_smu_set_power_state(adev) \
+- ((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
+-
+ #define amdgpu_dpm_get_pp_num_states(adev, data) \
+ ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 571d10de9eca..dd94467a3d5d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -158,7 +158,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
+
+ if (is_support_sw_smu(adev)) {
+ if (adev->smu.ppt_funcs->get_current_power_state)
+- pm = amdgpu_smu_get_current_power_state(adev);
++ pm = smu_get_current_power_state(&adev->smu);
+ else
+ pm = adev->pm.dpm.user_state;
+ } else if (adev->powerplay.pp_funcs->get_current_power_state) {
+@@ -904,7 +904,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
+ return ret;
+
+ if (is_support_sw_smu(adev))
+- ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
++ ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
+ ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+
+@@ -951,7 +951,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
+ return ret;
+
+ if (is_support_sw_smu(adev))
+- ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
++ ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
+ ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+
+@@ -991,7 +991,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
+ return ret;
+
+ if (is_support_sw_smu(adev))
+- ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
++ ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
+ ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
+
+@@ -1031,7 +1031,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
+ return ret;
+
+ if (is_support_sw_smu(adev))
+- ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
++ ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
+ ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
+
+@@ -1071,7 +1071,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
+ return ret;
+
+ if (is_support_sw_smu(adev))
+- ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
++ ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
+ ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
+
+@@ -1111,7 +1111,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
+ return ret;
+
+ if (is_support_sw_smu(adev))
+- ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
++ ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
+ ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+
+@@ -1303,7 +1303,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
+ }
+ parameter[parameter_size] = profile_mode;
+ if (is_support_sw_smu(adev))
+- ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
++ ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
+ else if (adev->powerplay.pp_funcs->set_power_profile_mode)
+ ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
+ if (!ret)
+@@ -2012,7 +2012,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
+ uint32_t limit = 0;
+
+ if (is_support_sw_smu(adev)) {
+- smu_get_power_limit(&adev->smu, &limit, true);
++ smu_get_power_limit(&adev->smu, &limit, true, true);
+ return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
+ } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
+ adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
+@@ -2030,7 +2030,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
+ uint32_t limit = 0;
+
+ if (is_support_sw_smu(adev)) {
+- smu_get_power_limit(&adev->smu, &limit, false);
++ smu_get_power_limit(&adev->smu, &limit, false, true);
+ return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
+ } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
+ adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
+@@ -3011,7 +3011,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
+ struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
+ smu_handle_task(&adev->smu,
+ smu_dpm->dpm_level,
+- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
++ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
++ true);
+ } else {
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ if (!amdgpu_device_has_dc_support(adev)) {
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 8a5eedb6a37a..c1b6abf2634c 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -866,7 +866,7 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
+ if (!smu->funcs->get_max_sustainable_clocks_by_dc)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+- if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))
++ if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
+ return PP_SMU_RESULT_OK;
+
+ return PP_SMU_RESULT_FAIL;
+@@ -885,7 +885,7 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
+ if (!smu->ppt_funcs->get_uclk_dpm_states)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+- if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
++ if (!smu_get_uclk_dpm_states(smu,
+ clock_values_in_khz, num_states))
+ return PP_SMU_RESULT_OK;
+
+@@ -906,7 +906,7 @@ enum pp_smu_status pp_rn_get_dpm_clock_table(
+ if (!smu->ppt_funcs->get_dpm_clock_table)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+- if (!smu->ppt_funcs->get_dpm_clock_table(smu, clock_table))
++ if (!smu_get_dpm_clock_table(smu, clock_table))
+ return PP_SMU_RESULT_OK;
+
+ return PP_SMU_RESULT_FAIL;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index fb5a55091292..d748ad9c2159 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -67,6 +67,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ uint32_t sort_feature[SMU_FEATURE_COUNT];
+ uint64_t hw_feature_count = 0;
+
++ mutex_lock(&smu->mutex);
++
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ if (ret)
+ goto failed;
+@@ -92,6 +94,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ }
+
+ failed:
++ mutex_unlock(&smu->mutex);
++
+ return size;
+ }
+
+@@ -149,9 +153,11 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+ uint64_t feature_2_disabled = 0;
+ uint64_t feature_enables = 0;
+
++ mutex_lock(&smu->mutex);
++
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ if (ret)
+- return ret;
++ goto out;
+
+ feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+@@ -161,14 +167,17 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+ if (feature_2_enabled) {
+ ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+ if (ret)
+- return ret;
++ goto out;
+ }
+ if (feature_2_disabled) {
+ ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+ if (ret)
+- return ret;
++ goto out;
+ }
+
++out:
++ mutex_unlock(&smu->mutex);
++
+ return ret;
+ }
+
+@@ -254,7 +263,7 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ }
+
+ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+- uint32_t *min, uint32_t *max)
++ uint32_t *min, uint32_t *max, bool lock_needed)
+ {
+ uint32_t clock_limit;
+ int ret = 0;
+@@ -262,6 +271,9 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ if (!min && !max)
+ return -EINVAL;
+
++ if (lock_needed)
++ mutex_lock(&smu->mutex);
++
+ if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
+ switch (clk_type) {
+ case SMU_MCLK:
+@@ -285,14 +297,17 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ *min = clock_limit / 100;
+ if (max)
+ *max = clock_limit / 100;
+-
+- return 0;
++ } else {
++ /*
++ * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
++ * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
++ */
++ ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
+ }
+- /*
+- * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
+- * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
+- */
+- ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
++
++ if (lock_needed)
++ mutex_unlock(&smu->mutex);
++
+ return ret;
+ }
+
+@@ -369,6 +384,8 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ {
+ int ret = 0;
+
++ mutex_lock(&smu->mutex);
++
+ switch (block_type) {
+ case AMD_IP_BLOCK_TYPE_UVD:
+ ret = smu_dpm_set_uvd_enable(smu, gate);
+@@ -386,13 +403,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ break;
+ }
+
+- return ret;
+-}
++ mutex_unlock(&smu->mutex);
+
+-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+-{
+- /* not support power state */
+- return POWER_STATE_TYPE_DEFAULT;
++ return ret;
+ }
+
+ int smu_get_power_num_states(struct smu_context *smu,
+@@ -520,16 +533,23 @@ bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
+ int smu_sys_get_pp_table(struct smu_context *smu, void **table)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
++ uint32_t powerplay_table_size;
+
+ if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
+ return -EINVAL;
+
++ mutex_lock(&smu->mutex);
++
+ if (smu_table->hardcode_pptable)
+ *table = smu_table->hardcode_pptable;
+ else
+ *table = smu_table->power_play_table;
+
+- return smu_table->power_play_table_size;
++ powerplay_table_size = smu_table->power_play_table_size;
++
++ mutex_unlock(&smu->mutex);
++
++ return powerplay_table_size;
+ }
+
+ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
+@@ -556,14 +576,11 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
+ memcpy(smu_table->hardcode_pptable, buf, size);
+ smu_table->power_play_table = smu_table->hardcode_pptable;
+ smu_table->power_play_table_size = size;
+- mutex_unlock(&smu->mutex);
+
+ ret = smu_reset(smu);
+ if (ret)
+ pr_info("smu reset failed, ret = %d\n", ret);
+
+- return ret;
+-
+ failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
+@@ -726,11 +743,10 @@ static int smu_late_init(void *handle)
+ if (!smu->pm_enabled)
+ return 0;
+
+- mutex_lock(&smu->mutex);
+ smu_handle_task(&adev->smu,
+ smu->smu_dpm.dpm_level,
+- AMD_PP_TASK_COMPLETE_INIT);
+- mutex_unlock(&smu->mutex);
++ AMD_PP_TASK_COMPLETE_INIT,
++ false);
+
+ return 0;
+ }
+@@ -1074,7 +1090,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ if (ret)
+ return ret;
+
+- ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
++ ret = smu_get_power_limit(smu, &smu->default_power_limit, true, false);
+ if (ret)
+ return ret;
+ }
+@@ -1160,15 +1176,19 @@ static int smu_start_smc_engine(struct smu_context *smu)
+
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ if (adev->asic_type < CHIP_NAVI10) {
+- ret = smu_load_microcode(smu);
+- if (ret)
+- return ret;
++ if (smu->funcs->load_microcode) {
++ ret = smu->funcs->load_microcode(smu);
++ if (ret)
++ return ret;
++ }
+ }
+ }
+
+- ret = smu_check_fw_status(smu);
+- if (ret)
+- pr_err("SMC is not ready\n");
++ if (smu->funcs->check_fw_status) {
++ ret = smu->funcs->check_fw_status(smu);
++ if (ret)
++ pr_err("SMC is not ready\n");
++ }
+
+ return ret;
+ }
+@@ -1335,8 +1355,6 @@ static int smu_resume(void *handle)
+
+ pr_info("SMU is resuming...\n");
+
+- mutex_lock(&smu->mutex);
+-
+ ret = smu_start_smc_engine(smu);
+ if (ret) {
+ pr_err("SMU is not ready yet!\n");
+@@ -1356,13 +1374,11 @@ static int smu_resume(void *handle)
+
+ smu->disable_uclk_switch = 0;
+
+- mutex_unlock(&smu->mutex);
+-
+ pr_info("SMU is resumed successfully!\n");
+
+ return 0;
++
+ failed:
+- mutex_unlock(&smu->mutex);
+ return ret;
+ }
+
+@@ -1380,8 +1396,9 @@ int smu_display_configuration_change(struct smu_context *smu,
+
+ mutex_lock(&smu->mutex);
+
+- smu_set_deep_sleep_dcefclk(smu,
+- display_config->min_dcef_deep_sleep_set_clk / 100);
++ if (smu->funcs->set_deep_sleep_dcefclk)
++ smu->funcs->set_deep_sleep_dcefclk(smu,
++ display_config->min_dcef_deep_sleep_set_clk / 100);
+
+ for (index = 0; index < display_config->num_path_including_non_display; index++) {
+ if (display_config->displays[index].controller_id != 0)
+@@ -1559,9 +1576,9 @@ static int smu_default_set_performance_level(struct smu_context *smu, enum amd_d
+ &soc_mask);
+ if (ret)
+ return ret;
+- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
+- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
++ smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
++ smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
++ smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+ break;
+ case AMD_DPM_FORCED_LEVEL_MANUAL:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+@@ -1625,7 +1642,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ workload = smu->workload_setting[index];
+
+ if (smu->power_profile_mode != workload)
+- smu_set_power_profile_mode(smu, &workload, 0);
++ smu_set_power_profile_mode(smu, &workload, 0, false);
+ }
+
+ return ret;
+@@ -1633,18 +1650,22 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+
+ int smu_handle_task(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+- enum amd_pp_task task_id)
++ enum amd_pp_task task_id,
++ bool lock_needed)
+ {
+ int ret = 0;
+
++ if (lock_needed)
++ mutex_lock(&smu->mutex);
++
+ switch (task_id) {
+ case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
+ ret = smu_pre_display_config_changed(smu);
+ if (ret)
+- return ret;
++ goto out;
+ ret = smu_set_cpu_power_state(smu);
+ if (ret)
+- return ret;
++ goto out;
+ ret = smu_adjust_power_state_dynamic(smu, level, false);
+ break;
+ case AMD_PP_TASK_COMPLETE_INIT:
+@@ -1655,6 +1676,10 @@ int smu_handle_task(struct smu_context *smu,
+ break;
+ }
+
++out:
++ if (lock_needed)
++ mutex_unlock(&smu->mutex);
++
+ return ret;
+ }
+
+@@ -1687,7 +1712,7 @@ int smu_switch_power_profile(struct smu_context *smu,
+ }
+
+ if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+- smu_set_power_profile_mode(smu, &workload, 0);
++ smu_set_power_profile_mode(smu, &workload, 0, false);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -1717,12 +1742,19 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
+ if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
+ return -EINVAL;
+
++ mutex_lock(&smu->mutex);
++
+ ret = smu_enable_umd_pstate(smu, &level);
+- if (ret)
++ if (ret) {
++ mutex_unlock(&smu->mutex);
+ return ret;
++ }
+
+ ret = smu_handle_task(smu, level,
+- AMD_PP_TASK_READJUST_POWER_STATE);
++ AMD_PP_TASK_READJUST_POWER_STATE,
++ false);
++
++ mutex_unlock(&smu->mutex);
+
+ return ret;
+ }
+@@ -1740,7 +1772,8 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
+
+ int smu_force_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+- uint32_t mask)
++ uint32_t mask,
++ bool lock_needed)
+ {
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ int ret = 0;
+@@ -1750,9 +1783,15 @@ int smu_force_clk_levels(struct smu_context *smu,
+ return -EINVAL;
+ }
+
++ if (lock_needed)
++ mutex_lock(&smu->mutex);
++
+ if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
+ ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
+
++ if (lock_needed)
++ mutex_unlock(&smu->mutex);
++
+ return ret;
+ }
+
+@@ -1770,6 +1809,8 @@ int smu_set_mp1_state(struct smu_context *smu,
+ if (!smu->pm_enabled)
+ return 0;
+
++ mutex_lock(&smu->mutex);
++
+ switch (mp1_state) {
+ case PP_MP1_STATE_SHUTDOWN:
+ msg = SMU_MSG_PrepareMp1ForShutdown;
+@@ -1782,17 +1823,22 @@ int smu_set_mp1_state(struct smu_context *smu,
+ break;
+ case PP_MP1_STATE_NONE:
+ default:
++ mutex_unlock(&smu->mutex);
+ return 0;
+ }
+
+ /* some asics may not support those messages */
+- if (smu_msg_get_index(smu, msg) < 0)
++ if (smu_msg_get_index(smu, msg) < 0) {
++ mutex_unlock(&smu->mutex);
+ return 0;
++ }
+
+ ret = smu_send_smc_msg(smu, msg);
+ if (ret)
+ pr_err("[PrepareMp1] Failed!\n");
+
++ mutex_unlock(&smu->mutex);
++
+ return ret;
+ }
+
+@@ -1812,10 +1858,14 @@ int smu_set_df_cstate(struct smu_context *smu,
+ if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
+ return 0;
+
++ mutex_lock(&smu->mutex);
++
+ ret = smu->ppt_funcs->set_df_cstate(smu, state);
+ if (ret)
+ pr_err("[SetDfCstate] failed!\n");
+
++ mutex_unlock(&smu->mutex);
++
+ return ret;
+ }
+
+@@ -1843,6 +1893,8 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+ void *table = watermarks->cpu_addr;
+
++ mutex_lock(&smu->mutex);
++
+ if (!smu->disable_watermark &&
+ smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+@@ -1851,6 +1903,8 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+ }
+
++ mutex_unlock(&smu->mutex);
++
+ return ret;
+ }
+
+@@ -1890,3 +1944,549 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block =
+ .rev = 0,
+ .funcs = &smu_ip_funcs,
+ };
++
++int smu_load_microcode(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->load_microcode)
++ ret = smu->funcs->load_microcode(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_check_fw_status(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->check_fw_status)
++ ret = smu->funcs->check_fw_status(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_gfx_cgpg)
++ ret = smu->funcs->set_gfx_cgpg(smu, enabled);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_fan_speed_rpm)
++ ret = smu->funcs->set_fan_speed_rpm(smu, speed);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_power_limit(struct smu_context *smu,
++ uint32_t *limit,
++ bool def,
++ bool lock_needed)
++{
++ int ret = 0;
++
++ if (lock_needed)
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_power_limit)
++ ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
++
++ if (lock_needed)
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_power_limit)
++ ret = smu->funcs->set_power_limit(smu, limit);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->print_clk_levels)
++ ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_od_percentage)
++ ret = smu->ppt_funcs->get_od_percentage(smu, type);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->set_od_percentage)
++ ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_od_edit_dpm_table(struct smu_context *smu,
++ enum PP_OD_DPM_TABLE_COMMAND type,
++ long *input, uint32_t size)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->od_edit_dpm_table)
++ ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->read_sensor)
++ ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_power_profile_mode)
++ ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_power_profile_mode(struct smu_context *smu,
++ long *param,
++ uint32_t param_size,
++ bool lock_needed)
++{
++ int ret = 0;
++
++ if (lock_needed)
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->set_power_profile_mode)
++ ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
++
++ if (lock_needed)
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++
++int smu_get_fan_control_mode(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->get_fan_control_mode)
++ ret = smu->funcs->get_fan_control_mode(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_fan_control_mode(struct smu_context *smu, int value)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_fan_control_mode)
++ ret = smu->funcs->set_fan_control_mode(smu, value);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_fan_speed_percent)
++ ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_fan_speed_percent)
++ ret = smu->funcs->set_fan_speed_percent(smu, speed);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_fan_speed_rpm)
++ ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_deep_sleep_dcefclk)
++ ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_active_display_count)
++ ret = smu->funcs->set_active_display_count(smu, count);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_clock_by_type(struct smu_context *smu,
++ enum amd_pp_clock_type type,
++ struct amd_pp_clocks *clocks)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->get_clock_by_type)
++ ret = smu->funcs->get_clock_by_type(smu, type, clocks);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_max_high_clocks(struct smu_context *smu,
++ struct amd_pp_simple_clock_info *clocks)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->get_max_high_clocks)
++ ret = smu->funcs->get_max_high_clocks(smu, clocks);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_clock_by_type_with_latency(struct smu_context *smu,
++ enum smu_clk_type clk_type,
++ struct pp_clock_levels_with_latency *clocks)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_clock_by_type_with_latency)
++ ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
++ enum amd_pp_clock_type type,
++ struct pp_clock_levels_with_voltage *clocks)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_clock_by_type_with_voltage)
++ ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++
++int smu_display_clock_voltage_request(struct smu_context *smu,
++ struct pp_display_clock_request *clock_req)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->display_clock_voltage_request)
++ ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++
++int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
++{
++ int ret = -EINVAL;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->display_disable_memory_clock_switch)
++ ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_notify_smu_enable_pwe(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->notify_smu_enable_pwe)
++ ret = smu->funcs->notify_smu_enable_pwe(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_xgmi_pstate(struct smu_context *smu,
++ uint32_t pstate)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_xgmi_pstate)
++ ret = smu->funcs->set_xgmi_pstate(smu, pstate);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_set_azalia_d3_pme(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->set_azalia_d3_pme)
++ ret = smu->funcs->set_azalia_d3_pme(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++bool smu_baco_is_support(struct smu_context *smu)
++{
++ bool ret = false;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->baco_is_support)
++ ret = smu->funcs->baco_is_support(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
++{
++ if (smu->funcs->baco_get_state)
++ return -EINVAL;
++
++ mutex_lock(&smu->mutex);
++ *state = smu->funcs->baco_get_state(smu);
++ mutex_unlock(&smu->mutex);
++
++ return 0;
++}
++
++int smu_baco_reset(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->baco_reset)
++ ret = smu->funcs->baco_reset(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_mode2_reset(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->mode2_reset)
++ ret = smu->funcs->mode2_reset(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++ struct pp_smu_nv_clock_table *max_clocks)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->funcs->get_max_sustainable_clocks_by_dc)
++ ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_get_uclk_dpm_states(struct smu_context *smu,
++ unsigned int *clock_values_in_khz,
++ unsigned int *num_states)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_uclk_dpm_states)
++ ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
++{
++ enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_current_power_state)
++ pm_state = smu->ppt_funcs->get_current_power_state(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return pm_state;
++}
++
++int smu_get_dpm_clock_table(struct smu_context *smu,
++ struct dpm_clocks *clock_table)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->get_dpm_clock_table)
++ ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index b33e451c7133..90b124dbdc14 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -763,8 +763,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
+ uint32_t soft_min_level, soft_max_level;
+ int ret = 0;
+
+- mutex_lock(&(smu->mutex));
+-
+ soft_min_level = mask ? (ffs(mask) - 1) : 0;
+ soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+@@ -883,7 +881,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
+ break;
+ }
+
+- mutex_unlock(&(smu->mutex));
+ return ret;
+ }
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index bf13bf33ba0c..3a1245f369a2 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -563,18 +563,17 @@ struct smu_funcs
+ ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+ #define smu_fini_power(smu) \
+ ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
+-#define smu_load_microcode(smu) \
+- ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
+-#define smu_check_fw_status(smu) \
+- ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
++int smu_load_microcode(struct smu_context *smu);
++
++int smu_check_fw_status(struct smu_context *smu);
++
+ #define smu_setup_pptable(smu) \
+ ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+ #define smu_powergate_sdma(smu, gate) \
+ ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_powergate_vcn(smu, gate) \
+ ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+-#define smu_set_gfx_cgpg(smu, enabled) \
+- ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
++int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
+ #define smu_get_vbios_bootup_values(smu) \
+ ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+ #define smu_get_clk_info_from_vbios(smu) \
+@@ -605,8 +604,8 @@ struct smu_funcs
+ ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+ #define smu_set_default_od_settings(smu, initialize) \
+ ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+-#define smu_set_fan_speed_rpm(smu, speed) \
+- ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
++int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
++
+ #define smu_send_smc_msg(smu, msg) \
+ ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+ #define smu_send_smc_msg_with_param(smu, msg, param) \
+@@ -637,20 +636,22 @@ struct smu_funcs
+ ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+ #define smu_set_default_od8_settings(smu) \
+ ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+-#define smu_get_power_limit(smu, limit, def) \
+- ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
+-#define smu_set_power_limit(smu, limit) \
+- ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
++
++int smu_get_power_limit(struct smu_context *smu,
++ uint32_t *limit,
++ bool def,
++ bool lock_needed);
++
++int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
+ #define smu_get_current_clk_freq(smu, clk_id, value) \
+ ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+-#define smu_print_clk_levels(smu, clk_type, buf) \
+- ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
+-#define smu_get_od_percentage(smu, type) \
+- ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
+-#define smu_set_od_percentage(smu, type, value) \
+- ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
+-#define smu_od_edit_dpm_table(smu, type, input, size) \
+- ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
++int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
++int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
++int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
++
++int smu_od_edit_dpm_table(struct smu_context *smu,
++ enum PP_OD_DPM_TABLE_COMMAND type,
++ long *input, uint32_t size);
+ #define smu_tables_init(smu, tab) \
+ ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
+ #define smu_set_thermal_fan_table(smu) \
+@@ -659,14 +660,18 @@ struct smu_funcs
+ ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+ #define smu_stop_thermal_control(smu) \
+ ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+-#define smu_read_sensor(smu, sensor, data, size) \
+- ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
++
++int smu_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size);
+ #define smu_smc_read_sensor(smu, sensor, data, size) \
+ ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+-#define smu_get_power_profile_mode(smu, buf) \
+- ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
+-#define smu_set_power_profile_mode(smu, param, param_size) \
+- ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
++int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
++
++int smu_set_power_profile_mode(struct smu_context *smu,
++ long *param,
++ uint32_t param_size,
++ bool lock_needed);
+ #define smu_pre_display_config_changed(smu) \
+ ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+ #define smu_display_config_changed(smu) \
+@@ -683,16 +688,11 @@ struct smu_funcs
+ ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
+ #define smu_set_cpu_power_state(smu) \
+ ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
+-#define smu_get_fan_control_mode(smu) \
+- ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
+-#define smu_set_fan_control_mode(smu, value) \
+- ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
+-#define smu_get_fan_speed_percent(smu, speed) \
+- ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
+-#define smu_set_fan_speed_percent(smu, speed) \
+- ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
+-#define smu_get_fan_speed_rpm(smu, speed) \
+- ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
++int smu_get_fan_control_mode(struct smu_context *smu);
++int smu_set_fan_control_mode(struct smu_context *smu, int value);
++int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
++int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
++int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
+
+ #define smu_msg_get_index(smu, msg) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+@@ -710,38 +710,44 @@ struct smu_funcs
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
+ #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+-#define smu_set_deep_sleep_dcefclk(smu, clk) \
+- ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
+-#define smu_set_active_display_count(smu, count) \
+- ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
++int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
++int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
+ #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+ ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+-#define smu_get_clock_by_type(smu, type, clocks) \
+- ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
+-#define smu_get_max_high_clocks(smu, clocks) \
+- ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
+-#define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
+- ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
+-#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
+- ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
+-#define smu_display_clock_voltage_request(smu, clock_req) \
+- ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
+-#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
+- ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
++
++int smu_get_clock_by_type(struct smu_context *smu,
++ enum amd_pp_clock_type type,
++ struct amd_pp_clocks *clocks);
++
++int smu_get_max_high_clocks(struct smu_context *smu,
++ struct amd_pp_simple_clock_info *clocks);
++
++int smu_get_clock_by_type_with_latency(struct smu_context *smu,
++ enum smu_clk_type clk_type,
++ struct pp_clock_levels_with_latency *clocks);
++
++int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
++ enum amd_pp_clock_type type,
++ struct pp_clock_levels_with_voltage *clocks);
++
++int smu_display_clock_voltage_request(struct smu_context *smu,
++ struct pp_display_clock_request *clock_req);
++int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
+ #define smu_get_dal_power_level(smu, clocks) \
+ ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+ #define smu_get_perf_level(smu, designation, level) \
+ ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+ #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+ ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+-#define smu_notify_smu_enable_pwe(smu) \
+- ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
++int smu_notify_smu_enable_pwe(struct smu_context *smu);
++
+ #define smu_dpm_set_uvd_enable(smu, enable) \
+ ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+ #define smu_dpm_set_vce_enable(smu, enable) \
+ ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
+-#define smu_set_xgmi_pstate(smu, pstate) \
+- ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
++
++int smu_set_xgmi_pstate(struct smu_context *smu,
++ uint32_t pstate);
+ #define smu_set_watermarks_table(smu, tab, clock_ranges) \
+ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+ #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
+@@ -752,22 +758,18 @@ struct smu_funcs
+ ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
+ #define smu_register_irq_handler(smu) \
+ ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+-#define smu_set_azalia_d3_pme(smu) \
+- ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
++
++int smu_set_azalia_d3_pme(struct smu_context *smu);
+ #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+ ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+- ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+-#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
+- ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
+-#define smu_baco_is_support(smu) \
+- ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
+-#define smu_baco_get_state(smu, state) \
+- ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
+-#define smu_baco_reset(smu) \
+- ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
+-#define smu_mode2_reset(smu) \
+- ((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
++
++bool smu_baco_is_support(struct smu_context *smu);
++
++int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
++
++int smu_baco_reset(struct smu_context *smu);
++
++int smu_mode2_reset(struct smu_context *smu);
+ #define smu_asic_set_performance_level(smu, level) \
+ ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+ #define smu_dump_pptable(smu) \
+@@ -776,8 +778,6 @@ struct smu_funcs
+ ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+-#define smu_get_dpm_clock_table(smu, clock_table) \
+- ((smu)->ppt_funcs->get_dpm_clock_table ? (smu)->ppt_funcs->get_dpm_clock_table((smu), (clock_table)) : -EINVAL)
+
+ #define smu_override_pcie_parameters(smu) \
+ ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+@@ -831,7 +831,8 @@ extern int smu_get_current_clocks(struct smu_context *smu,
+ extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
+ extern int smu_handle_task(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+- enum amd_pp_task task_id);
++ enum amd_pp_task task_id,
++ bool lock_needed);
+ int smu_switch_power_profile(struct smu_context *smu,
+ enum PP_SMC_POWER_PROFILE type,
+ bool en);
+@@ -841,7 +842,7 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
+ int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *value);
+ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+- uint32_t *min, uint32_t *max);
++ uint32_t *min, uint32_t *max, bool lock_needed);
+ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t min, uint32_t max);
+ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+@@ -856,10 +857,21 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
+ int smu_force_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+- uint32_t mask);
++ uint32_t mask,
++ bool lock_needed);
+ int smu_set_mp1_state(struct smu_context *smu,
+ enum pp_mp1_state mp1_state);
+ int smu_set_df_cstate(struct smu_context *smu,
+ enum pp_df_cstate state);
+
++int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++ struct pp_smu_nv_clock_table *max_clocks);
++
++int smu_get_uclk_dpm_states(struct smu_context *smu,
++ unsigned int *clock_values_in_khz,
++ unsigned int *num_states);
++
++int smu_get_dpm_clock_table(struct smu_context *smu,
++ struct dpm_clocks *clock_table);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index b88aae9bb242..ead40b2840f9 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -795,13 +795,13 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
+ int ret = 0;
+ uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
+
+- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
++ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
+ if (ret)
+ return ret;
+
+ smu->pstate_sclk = min_sclk_freq * 100;
+
+- ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
++ ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
+ if (ret)
+ return ret;
+
+@@ -854,7 +854,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
+ return ret;
+
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
++ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
+ if (ret)
+ return ret;
+ ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
+@@ -904,7 +904,7 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ clk_type = clks[i];
+- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ if (ret)
+ return ret;
+
+@@ -931,7 +931,7 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu)
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ clk_type = clks[i];
+- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ if (ret)
+ return ret;
+
+@@ -1266,7 +1266,10 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
+ if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ clock_req.clock_type = amd_pp_dcef_clock;
+ clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+- if (!smu_display_clock_voltage_request(smu, &clock_req)) {
++
++ if (smu->funcs->display_clock_voltage_request)
++ ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
++ if (!ret) {
+ if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetMinDeepSleepDcefclk,
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 57930c9e22ff..0203da74b7d5 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -194,7 +194,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
+ case SMU_SCLK:
+ /* retirve table returned paramters unit is MHz */
+ cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
+- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
++ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
+ if (!ret) {
+ /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
+ if (cur_value == max)
+@@ -251,7 +251,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
+ !smu_dpm_ctx->dpm_current_power_state)
+ return -EINVAL;
+
+- mutex_lock(&(smu->mutex));
+ switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
+ case SMU_STATE_UI_LABEL_BATTERY:
+ pm_type = POWER_STATE_TYPE_BATTERY;
+@@ -269,7 +268,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
+ pm_type = POWER_STATE_TYPE_DEFAULT;
+ break;
+ }
+- mutex_unlock(&(smu->mutex));
+
+ return pm_type;
+ }
+@@ -314,7 +312,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ clk_type = clks[i];
+- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ if (ret)
+ return ret;
+
+@@ -348,7 +346,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+
+ clk_type = clk_feature_map[i].clk_type;
+
+- ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++ ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ if (ret)
+ return ret;
+
+@@ -469,7 +467,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
+ return -EINVAL;
+ }
+
+- ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq);
++ ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
+@@ -545,7 +543,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
+ int ret = 0;
+ uint32_t sclk_freq = 0, uclk_freq = 0;
+
+- ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);
++ ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
+ if (ret)
+ return ret;
+
+@@ -553,7 +551,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
+ if (ret)
+ return ret;
+
+- ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);
++ ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
+ if (ret)
+ return ret;
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index ac02bcd24da0..54f9d3dd837f 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -792,8 +792,11 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+ if (!table_context)
+ return -EINVAL;
+
+- return smu_set_deep_sleep_dcefclk(smu,
+- table_context->boot_values.dcefclk / 100);
++ if (smu->funcs->set_deep_sleep_dcefclk)
++ return smu->funcs->set_deep_sleep_dcefclk(smu,
++ table_context->boot_values.dcefclk / 100);
++
++ return 0;
+ }
+
+ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+@@ -1308,9 +1311,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
+ return 0;
+
+- mutex_lock(&smu->mutex);
+ ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
+- mutex_unlock(&smu->mutex);
+
+ if(clk_select == SMU_UCLK)
+ smu->hard_min_uclk_req_from_dal = clk_freq;
+@@ -1333,12 +1334,10 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ case CHIP_NAVI12:
+ if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
+ return 0;
+- mutex_lock(&smu->mutex);
+ if (enable)
+ ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
+ else
+ ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
+- mutex_unlock(&smu->mutex);
+ break;
+ default:
+ break;
+@@ -1454,10 +1453,9 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ if (!speed)
+ return -EINVAL;
+
+- mutex_lock(&(smu->mutex));
+ ret = smu_v11_0_auto_fan_control(smu, 0);
+ if (ret)
+- goto set_fan_speed_rpm_failed;
++ return ret;
+
+ crystal_clock_freq = amdgpu_asic_get_xclk(adev);
+ tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
+@@ -1468,8 +1466,6 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+
+ ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
+
+-set_fan_speed_rpm_failed:
+- mutex_unlock(&(smu->mutex));
+ return ret;
+ }
+
+@@ -1480,11 +1476,9 @@ static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate)
+ {
+ int ret = 0;
+- mutex_lock(&(smu->mutex));
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetXgmiMode,
+ pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
+- mutex_unlock(&(smu->mutex));
+ return ret;
+ }
+
+@@ -1596,9 +1590,7 @@ static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
+ {
+ int ret = 0;
+
+- mutex_lock(&smu->mutex);
+ ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
+- mutex_unlock(&smu->mutex);
+
+ return ret;
+ }
+@@ -1695,7 +1687,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ int ret = 0, clk_id = 0;
+ uint32_t param = 0;
+
+- mutex_lock(&smu->mutex);
+ clk_id = smu_clk_get_index(smu, clk_type);
+ if (clk_id < 0) {
+ ret = -EINVAL;
+@@ -1722,7 +1713,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ }
+
+ failed:
+- mutex_unlock(&smu->mutex);
+ return ret;
+ }
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index cac4269cf1d1..6b9eef20554b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -316,8 +316,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ int ret = 0;
+ uint32_t mclk_mask, soc_mask;
+
+- mutex_lock(&smu->mutex);
+-
+ if (max) {
+ ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
+ NULL,
+@@ -387,7 +385,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ }
+ }
+ failed:
+- mutex_unlock(&smu->mutex);
+ return ret;
+ }
+
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index a76ffd58404e..c249df9256c7 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -635,7 +635,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
+ !smu_dpm_ctx->dpm_current_power_state)
+ return -EINVAL;
+
+- mutex_lock(&(smu->mutex));
+ switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
+ case SMU_STATE_UI_LABEL_BATTERY:
+ pm_type = POWER_STATE_TYPE_BATTERY;
+@@ -653,7 +652,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
+ pm_type = POWER_STATE_TYPE_DEFAULT;
+ break;
+ }
+- mutex_unlock(&(smu->mutex));
+
+ return pm_type;
+ }
+@@ -1277,8 +1275,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
+ uint32_t soft_min_level, soft_max_level, hard_min_level;
+ int ret = 0;
+
+- mutex_lock(&(smu->mutex));
+-
+ soft_min_level = mask ? (ffs(mask) - 1) : 0;
+ soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+@@ -1431,7 +1427,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
+ break;
+ }
+
+- mutex_unlock(&(smu->mutex));
+ return ret;
+ }
+
+@@ -1446,8 +1441,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
+
+ dpm_table = smu_dpm->dpm_context;
+
+- mutex_lock(&smu->mutex);
+-
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ single_dpm_table = &(dpm_table->gfx_table);
+@@ -1469,7 +1462,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
+ ret = -EINVAL;
+ }
+
+- mutex_unlock(&smu->mutex);
+ return ret;
+ }
+
+@@ -2542,8 +2534,6 @@ static int vega20_set_od_percentage(struct smu_context *smu,
+ int feature_enabled;
+ PPCLK_e clk_id;
+
+- mutex_lock(&(smu->mutex));
+-
+ dpm_table = smu_dpm->dpm_context;
+ golden_table = smu_dpm->golden_dpm_context;
+
+@@ -2593,11 +2583,10 @@ static int vega20_set_od_percentage(struct smu_context *smu,
+ }
+
+ ret = smu_handle_task(smu, smu_dpm->dpm_level,
+- AMD_PP_TASK_READJUST_POWER_STATE);
++ AMD_PP_TASK_READJUST_POWER_STATE,
++ false);
+
+ set_od_failed:
+- mutex_unlock(&(smu->mutex));
+-
+ return ret;
+ }
+
+@@ -2822,10 +2811,9 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
+ }
+
+ if (type == PP_OD_COMMIT_DPM_TABLE) {
+- mutex_lock(&(smu->mutex));
+ ret = smu_handle_task(smu, smu_dpm->dpm_level,
+- AMD_PP_TASK_READJUST_POWER_STATE);
+- mutex_unlock(&(smu->mutex));
++ AMD_PP_TASK_READJUST_POWER_STATE,
++ false);
+ }
+
+ return ret;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4267-drm-amd-powerplay-split-out-those-internal-used-swSM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4267-drm-amd-powerplay-split-out-those-internal-used-swSM.patch
new file mode 100644
index 00000000..4bb6270d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4267-drm-amd-powerplay-split-out-those-internal-used-swSM.patch
@@ -0,0 +1,555 @@
+From 3ec8ab435fb3ed0b87a4b782440df9d59ea16c21 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 17 Oct 2019 14:15:41 +0800
+Subject: [PATCH 4267/4736] drm/amd/powerplay: split out those internal used
+ swSMU APIs V2
+
+Those swSMU APIs used internally are moved to smu_internal.h while
+others are kept in amdgpu_smu.h.
+
+V2: give a better name smu_internal.h for the place to hold
+ those internal APIs
+
+Change-Id: Ib726ef7f65dee46e47a07680b71e6e043e459f42
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 +
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 +
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 161 +-------------
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 +
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_internal.h | 204 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 1 +
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 +
+ 9 files changed, 212 insertions(+), 160 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/smu_internal.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d748ad9c2159..75c4e297b788 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -25,6 +25,7 @@
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "soc15_common.h"
+ #include "smu_v11_0.h"
+ #include "smu_v12_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 90b124dbdc14..a2262464d141 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -25,6 +25,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 3a1245f369a2..79fe32acc838 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -553,89 +553,13 @@ struct smu_funcs
+ int (*override_pcie_parameters)(struct smu_context *smu);
+ };
+
+-#define smu_init_microcode(smu) \
+- ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+-#define smu_init_smc_tables(smu) \
+- ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
+-#define smu_fini_smc_tables(smu) \
+- ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
+-#define smu_init_power(smu) \
+- ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+-#define smu_fini_power(smu) \
+- ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
+ int smu_load_microcode(struct smu_context *smu);
+
+ int smu_check_fw_status(struct smu_context *smu);
+
+-#define smu_setup_pptable(smu) \
+- ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+-#define smu_powergate_sdma(smu, gate) \
+- ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+-#define smu_powergate_vcn(smu, gate) \
+- ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
+-#define smu_get_vbios_bootup_values(smu) \
+- ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+-#define smu_get_clk_info_from_vbios(smu) \
+- ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
+-#define smu_check_pptable(smu) \
+- ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
+-#define smu_parse_pptable(smu) \
+- ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+-#define smu_populate_smc_tables(smu) \
+- ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
+-#define smu_check_fw_version(smu) \
+- ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
+-#define smu_write_pptable(smu) \
+- ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
+-#define smu_set_min_dcef_deep_sleep(smu) \
+- ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
+-#define smu_set_tool_table_location(smu) \
+- ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
+-#define smu_notify_memory_pool_location(smu) \
+- ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+-#define smu_gfx_off_control(smu, enable) \
+- ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
+-#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+- ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+-#define smu_system_features_control(smu, en) \
+- ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
+-#define smu_init_max_sustainable_clocks(smu) \
+- ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+-#define smu_set_default_od_settings(smu, initialize) \
+- ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+-int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+
+-#define smu_send_smc_msg(smu, msg) \
+- ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+-#define smu_send_smc_msg_with_param(smu, msg, param) \
+- ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+-#define smu_read_smc_arg(smu, arg) \
+- ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+-#define smu_alloc_dpm_context(smu) \
+- ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
+-#define smu_init_display_count(smu, count) \
+- ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
+-#define smu_feature_set_allowed_mask(smu) \
+- ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
+-#define smu_feature_get_enabled_mask(smu, mask, num) \
+- ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+-#define smu_is_dpm_running(smu) \
+- ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
+-#define smu_notify_display_change(smu) \
+- ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
+-#define smu_store_powerplay_table(smu) \
+- ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
+-#define smu_check_powerplay_table(smu) \
+- ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
+-#define smu_append_powerplay_table(smu) \
+- ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
+-#define smu_set_default_dpm_table(smu) \
+- ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
+-#define smu_populate_umd_state_clk(smu) \
+- ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+-#define smu_set_default_od8_settings(smu) \
+- ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
++int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+
+ int smu_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+@@ -643,8 +567,6 @@ int smu_get_power_limit(struct smu_context *smu,
+ bool lock_needed);
+
+ int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
+-#define smu_get_current_clk_freq(smu, clk_id, value) \
+- ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+ int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
+ int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
+ int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
+@@ -652,68 +574,24 @@ int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint3
+ int smu_od_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size);
+-#define smu_tables_init(smu, tab) \
+- ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
+-#define smu_set_thermal_fan_table(smu) \
+- ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
+-#define smu_start_thermal_control(smu) \
+- ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+-#define smu_stop_thermal_control(smu) \
+- ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+
+ int smu_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
+-#define smu_smc_read_sensor(smu, sensor, data, size) \
+- ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+ int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
+
+ int smu_set_power_profile_mode(struct smu_context *smu,
+ long *param,
+ uint32_t param_size,
+ bool lock_needed);
+-#define smu_pre_display_config_changed(smu) \
+- ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+-#define smu_display_config_changed(smu) \
+- ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
+-#define smu_apply_clocks_adjust_rules(smu) \
+- ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
+-#define smu_notify_smc_dispaly_config(smu) \
+- ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
+-#define smu_force_dpm_limit_value(smu, highest) \
+- ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
+-#define smu_unforce_dpm_levels(smu) \
+- ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
+-#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
+- ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
+-#define smu_set_cpu_power_state(smu) \
+- ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
+ int smu_get_fan_control_mode(struct smu_context *smu);
+ int smu_set_fan_control_mode(struct smu_context *smu, int value);
+ int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
+ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
+ int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
+
+-#define smu_msg_get_index(smu, msg) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+-#define smu_clk_get_index(smu, msg) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
+-#define smu_feature_get_index(smu, msg) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
+-#define smu_table_get_index(smu, tab) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
+-#define smu_power_get_index(smu, src) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
+-#define smu_workload_get_type(smu, profile) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
+-#define smu_run_btc(smu) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
+-#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
+- ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
+ int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
+-#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+- ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+
+ int smu_get_clock_by_type(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+@@ -733,35 +611,12 @@ int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ int smu_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request *clock_req);
+ int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
+-#define smu_get_dal_power_level(smu, clocks) \
+- ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+-#define smu_get_perf_level(smu, designation, level) \
+- ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+-#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+- ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+ int smu_notify_smu_enable_pwe(struct smu_context *smu);
+
+-#define smu_dpm_set_uvd_enable(smu, enable) \
+- ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+-#define smu_dpm_set_vce_enable(smu, enable) \
+- ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
+-
+ int smu_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate);
+-#define smu_set_watermarks_table(smu, tab, clock_ranges) \
+- ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+-#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
+- ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
+-#define smu_thermal_temperature_range_update(smu, range, rw) \
+- ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
+-#define smu_get_thermal_temperature_range(smu, range) \
+- ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
+-#define smu_register_irq_handler(smu) \
+- ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+
+ int smu_set_azalia_d3_pme(struct smu_context *smu);
+-#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+- ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+
+ bool smu_baco_is_support(struct smu_context *smu);
+
+@@ -770,20 +625,6 @@ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
+ int smu_baco_reset(struct smu_context *smu);
+
+ int smu_mode2_reset(struct smu_context *smu);
+-#define smu_asic_set_performance_level(smu, level) \
+- ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+-#define smu_dump_pptable(smu) \
+- ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+-#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
+- ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+-#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+- ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+-
+-#define smu_override_pcie_parameters(smu) \
+- ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+-
+-#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
+- ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
+
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ uint16_t *size, uint8_t *frev, uint8_t *crev,
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index ead40b2840f9..54d5c91dda23 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -25,6 +25,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 0203da74b7d5..6df91b1a9daa 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -23,6 +23,7 @@
+
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "soc15_common.h"
+ #include "smu_v12_0_ppsmc.h"
+ #include "smu12_driver_if.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+new file mode 100644
+index 000000000000..c26eede7e36a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -0,0 +1,204 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef __SMU_INTERNAL_H__
++#define __SMU_INTERNAL_H__
++
++#include "amdgpu_smu.h"
++
++#define smu_init_microcode(smu) \
++ ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
++#define smu_init_smc_tables(smu) \
++ ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
++#define smu_fini_smc_tables(smu) \
++ ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
++#define smu_init_power(smu) \
++ ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
++#define smu_fini_power(smu) \
++ ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
++
++#define smu_setup_pptable(smu) \
++ ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
++#define smu_powergate_sdma(smu, gate) \
++ ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
++#define smu_powergate_vcn(smu, gate) \
++ ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
++
++#define smu_get_vbios_bootup_values(smu) \
++ ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
++#define smu_get_clk_info_from_vbios(smu) \
++ ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
++#define smu_check_pptable(smu) \
++ ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
++#define smu_parse_pptable(smu) \
++ ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
++#define smu_populate_smc_tables(smu) \
++ ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
++#define smu_check_fw_version(smu) \
++ ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
++#define smu_write_pptable(smu) \
++ ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
++#define smu_set_min_dcef_deep_sleep(smu) \
++ ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
++#define smu_set_tool_table_location(smu) \
++ ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
++#define smu_notify_memory_pool_location(smu) \
++ ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
++#define smu_gfx_off_control(smu, enable) \
++ ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
++
++#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
++ ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
++#define smu_system_features_control(smu, en) \
++ ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
++#define smu_init_max_sustainable_clocks(smu) \
++ ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
++#define smu_set_default_od_settings(smu, initialize) \
++ ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
++
++#define smu_send_smc_msg(smu, msg) \
++ ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
++#define smu_send_smc_msg_with_param(smu, msg, param) \
++ ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
++#define smu_read_smc_arg(smu, arg) \
++ ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
++#define smu_alloc_dpm_context(smu) \
++ ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
++#define smu_init_display_count(smu, count) \
++ ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
++#define smu_feature_set_allowed_mask(smu) \
++ ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
++#define smu_feature_get_enabled_mask(smu, mask, num) \
++ ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
++#define smu_is_dpm_running(smu) \
++ ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
++#define smu_notify_display_change(smu) \
++ ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
++#define smu_store_powerplay_table(smu) \
++ ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
++#define smu_check_powerplay_table(smu) \
++ ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
++#define smu_append_powerplay_table(smu) \
++ ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
++#define smu_set_default_dpm_table(smu) \
++ ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
++#define smu_populate_umd_state_clk(smu) \
++ ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
++#define smu_set_default_od8_settings(smu) \
++ ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
++
++#define smu_get_current_clk_freq(smu, clk_id, value) \
++ ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
++
++#define smu_tables_init(smu, tab) \
++ ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
++#define smu_set_thermal_fan_table(smu) \
++ ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
++#define smu_start_thermal_control(smu) \
++ ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
++#define smu_stop_thermal_control(smu) \
++ ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
++
++#define smu_smc_read_sensor(smu, sensor, data, size) \
++ ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
++
++#define smu_pre_display_config_changed(smu) \
++ ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
++#define smu_display_config_changed(smu) \
++ ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
++#define smu_apply_clocks_adjust_rules(smu) \
++ ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
++#define smu_notify_smc_dispaly_config(smu) \
++ ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
++#define smu_force_dpm_limit_value(smu, highest) \
++ ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
++#define smu_unforce_dpm_levels(smu) \
++ ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
++#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
++ ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
++#define smu_set_cpu_power_state(smu) \
++ ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
++
++#define smu_msg_get_index(smu, msg) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
++#define smu_clk_get_index(smu, msg) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
++#define smu_feature_get_index(smu, msg) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
++#define smu_table_get_index(smu, tab) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
++#define smu_power_get_index(smu, src) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
++#define smu_workload_get_type(smu, profile) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
++#define smu_run_btc(smu) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
++#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
++ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
++
++
++#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
++ ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
++
++#define smu_get_dal_power_level(smu, clocks) \
++ ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
++#define smu_get_perf_level(smu, designation, level) \
++ ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
++#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
++ ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
++
++#define smu_dpm_set_uvd_enable(smu, enable) \
++ ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
++#define smu_dpm_set_vce_enable(smu, enable) \
++ ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
++
++#define smu_set_watermarks_table(smu, tab, clock_ranges) \
++ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
++#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
++ ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
++#define smu_thermal_temperature_range_update(smu, range, rw) \
++ ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
++#define smu_get_thermal_temperature_range(smu, range) \
++ ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
++#define smu_register_irq_handler(smu) \
++ ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
++
++#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
++ ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
++
++#define smu_asic_set_performance_level(smu, level) \
++ ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
++#define smu_dump_pptable(smu) \
++ ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
++#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
++ ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
++
++#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
++ ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
++
++#define smu_override_pcie_parameters(smu) \
++ ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
++
++#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
++ ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
++
++#endif
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 54f9d3dd837f..6794fc4cacb5 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -24,6 +24,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 6b9eef20554b..92e1c0a3f428 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -24,6 +24,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v12_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index c249df9256c7..4039efcdcb1f 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -25,6 +25,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4268-drm-amd-powerplay-clear-the-swSMU-code-layer.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4268-drm-amd-powerplay-clear-the-swSMU-code-layer.patch
new file mode 100644
index 00000000..d4a448be
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4268-drm-amd-powerplay-clear-the-swSMU-code-layer.patch
@@ -0,0 +1,1907 @@
+From f8ce766413a519f8c78170815c26fa4e7bf5fbdd Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 17 Oct 2019 19:59:29 +0800
+Subject: [PATCH 4268/4736] drm/amd/powerplay: clear the swSMU code layer
+
+With this cleanup, the APIs from amdgpu_smu.c will map to
+ASIC specific ones directly. Those can be shared around
+all SMU V11/V12 ASICs will be put in smu_v11_0.c and
+smu_v12_0.c respectively.
+
+Change-Id: I9b98eb5ace5df19896de4b05c37255a38d1079ce
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 42 ++--
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 115 +++++------
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 51 ++++-
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 9 +-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 120 +++++++++++-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 41 +++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 54 +++++-
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 15 ++
+ drivers/gpu/drm/amd/powerplay/smu_internal.h | 82 ++++----
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 183 +++++-------------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 70 ++-----
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 55 +++++-
+ 12 files changed, 519 insertions(+), 318 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index c1b6abf2634c..e42b162ee5d3 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -346,7 +346,7 @@ bool dm_pp_get_clock_levels_by_type(
+ /* Error in pplib. Provide default values. */
+ return true;
+ }
+- } else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
++ } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
+ if (smu_get_clock_by_type(&adev->smu,
+ dc_to_pp_clock_type(clk_type),
+ &pp_clks)) {
+@@ -366,7 +366,7 @@ bool dm_pp_get_clock_levels_by_type(
+ validation_clks.memory_max_clock = 80000;
+ validation_clks.level = 0;
+ }
+- } else if (adev->smu.funcs && adev->smu.funcs->get_max_high_clocks) {
++ } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_max_high_clocks) {
+ if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
+ DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
+ validation_clks.engine_max_clock = 72000;
+@@ -507,8 +507,8 @@ bool dm_pp_apply_clock_for_voltage_request(
+ ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
+ adev->powerplay.pp_handle,
+ &pp_clock_request);
+- else if (adev->smu.funcs &&
+- adev->smu.funcs->display_clock_voltage_request)
++ else if (adev->smu.ppt_funcs &&
++ adev->smu.ppt_funcs->display_clock_voltage_request)
+ ret = smu_display_clock_voltage_request(&adev->smu,
+ &pp_clock_request);
+ if (ret)
+@@ -528,7 +528,7 @@ bool dm_pp_get_static_clocks(
+ ret = adev->powerplay.pp_funcs->get_current_clocks(
+ adev->powerplay.pp_handle,
+ &pp_clk_info);
+- else if (adev->smu.funcs)
++ else if (adev->smu.ppt_funcs)
+ ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
+ if (ret)
+ return false;
+@@ -604,7 +604,7 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
+
+ if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
+ pp_funcs->notify_smu_enable_pwe(pp_handle);
+- else if (adev->smu.funcs)
++ else if (adev->smu.ppt_funcs)
+ smu_notify_smu_enable_pwe(&adev->smu);
+ }
+
+@@ -718,10 +718,10 @@ enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = &adev->smu;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+- /* 0: successful or smu.funcs->set_azalia_d3_pme = NULL; 1: fail */
++ /* 0: successful or smu.ppt_funcs->set_azalia_d3_pme = NULL; 1: fail */
+ if (smu_set_azalia_d3_pme(smu))
+ return PP_SMU_RESULT_FAIL;
+
+@@ -734,10 +734,10 @@ enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = &adev->smu;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+- /* 0: successful or smu.funcs->set_display_count = NULL; 1: fail */
++ /* 0: successful or smu.ppt_funcs->set_display_count = NULL; 1: fail */
+ if (smu_set_display_count(smu, count))
+ return PP_SMU_RESULT_FAIL;
+
+@@ -750,10 +750,10 @@ enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = &adev->smu;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+- /* 0: successful or smu.funcs->set_deep_sleep_dcefclk = NULL;1: fail */
++ /* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */
+ if (smu_set_deep_sleep_dcefclk(smu, mhz))
+ return PP_SMU_RESULT_FAIL;
+
+@@ -768,13 +768,13 @@ enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
+ struct smu_context *smu = &adev->smu;
+ struct pp_display_clock_request clock_req;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ clock_req.clock_type = amd_pp_dcef_clock;
+ clock_req.clock_freq_in_khz = mhz * 1000;
+
+- /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
++ /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
+ * 1: fail
+ */
+ if (smu_display_clock_voltage_request(smu, &clock_req))
+@@ -790,13 +790,13 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
+ struct smu_context *smu = &adev->smu;
+ struct pp_display_clock_request clock_req;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ clock_req.clock_type = amd_pp_mem_clock;
+ clock_req.clock_freq_in_khz = mhz * 1000;
+
+- /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
++ /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
+ * 1: fail
+ */
+ if (smu_display_clock_voltage_request(smu, &clock_req))
+@@ -826,7 +826,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
+ struct smu_context *smu = &adev->smu;
+ struct pp_display_clock_request clock_req;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ switch (clock_id) {
+@@ -844,7 +844,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
+ }
+ clock_req.clock_freq_in_khz = mhz * 1000;
+
+- /* 0: successful or smu.funcs->display_clock_voltage_request = NULL
++ /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
+ * 1: fail
+ */
+ if (smu_display_clock_voltage_request(smu, &clock_req))
+@@ -860,10 +860,10 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = &adev->smu;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+- if (!smu->funcs->get_max_sustainable_clocks_by_dc)
++ if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
+@@ -925,7 +925,7 @@ enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
+ wm_with_clock_ranges.wm_mcif_clocks_ranges;
+ int32_t i;
+
+- if (!smu->funcs)
++ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 75c4e297b788..3ce01e1994fc 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -31,6 +31,10 @@
+ #include "smu_v12_0.h"
+ #include "atom.h"
+ #include "amd_pcie.h"
++#include "vega20_ppt.h"
++#include "arcturus_ppt.h"
++#include "navi10_ppt.h"
++#include "renoir_ppt.h"
+
+ #undef __SMU_DUMMY_MAP
+ #define __SMU_DUMMY_MAP(type) #type
+@@ -703,23 +707,26 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
++ vega20_set_ppt_funcs(smu);
++ break;
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
+ case CHIP_NAVI12:
++ navi10_set_ppt_funcs(smu);
++ break;
+ case CHIP_ARCTURUS:
+- if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+- smu->od_enabled = true;
+- smu_v11_0_set_smu_funcs(smu);
++ arcturus_set_ppt_funcs(smu);
+ break;
+ case CHIP_RENOIR:
+- if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+- smu->od_enabled = true;
+- smu_v12_0_set_smu_funcs(smu);
++ renoir_set_ppt_funcs(smu);
+ break;
+ default:
+ return -EINVAL;
+ }
+
++ if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
++ smu->od_enabled = true;
++
+ return 0;
+ }
+
+@@ -1177,16 +1184,16 @@ static int smu_start_smc_engine(struct smu_context *smu)
+
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ if (adev->asic_type < CHIP_NAVI10) {
+- if (smu->funcs->load_microcode) {
+- ret = smu->funcs->load_microcode(smu);
++ if (smu->ppt_funcs->load_microcode) {
++ ret = smu->ppt_funcs->load_microcode(smu);
+ if (ret)
+ return ret;
+ }
+ }
+ }
+
+- if (smu->funcs->check_fw_status) {
+- ret = smu->funcs->check_fw_status(smu);
++ if (smu->ppt_funcs->check_fw_status) {
++ ret = smu->ppt_funcs->check_fw_status(smu);
+ if (ret)
+ pr_err("SMC is not ready\n");
+ }
+@@ -1397,8 +1404,8 @@ int smu_display_configuration_change(struct smu_context *smu,
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_deep_sleep_dcefclk)
+- smu->funcs->set_deep_sleep_dcefclk(smu,
++ if (smu->ppt_funcs->set_deep_sleep_dcefclk)
++ smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
+ display_config->min_dcef_deep_sleep_set_clk / 100);
+
+ for (index = 0; index < display_config->num_path_including_non_display; index++) {
+@@ -1952,8 +1959,8 @@ int smu_load_microcode(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->load_microcode)
+- ret = smu->funcs->load_microcode(smu);
++ if (smu->ppt_funcs->load_microcode)
++ ret = smu->ppt_funcs->load_microcode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -1966,8 +1973,8 @@ int smu_check_fw_status(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->check_fw_status)
+- ret = smu->funcs->check_fw_status(smu);
++ if (smu->ppt_funcs->check_fw_status)
++ ret = smu->ppt_funcs->check_fw_status(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -1980,8 +1987,8 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_gfx_cgpg)
+- ret = smu->funcs->set_gfx_cgpg(smu, enabled);
++ if (smu->ppt_funcs->set_gfx_cgpg)
++ ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -1994,8 +2001,8 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_fan_speed_rpm)
+- ret = smu->funcs->set_fan_speed_rpm(smu, speed);
++ if (smu->ppt_funcs->set_fan_speed_rpm)
++ ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2027,8 +2034,8 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_power_limit)
+- ret = smu->funcs->set_power_limit(smu, limit);
++ if (smu->ppt_funcs->set_power_limit)
++ ret = smu->ppt_funcs->set_power_limit(smu, limit);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2149,8 +2156,8 @@ int smu_get_fan_control_mode(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->get_fan_control_mode)
+- ret = smu->funcs->get_fan_control_mode(smu);
++ if (smu->ppt_funcs->get_fan_control_mode)
++ ret = smu->ppt_funcs->get_fan_control_mode(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2163,8 +2170,8 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_fan_control_mode)
+- ret = smu->funcs->set_fan_control_mode(smu, value);
++ if (smu->ppt_funcs->set_fan_control_mode)
++ ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2191,8 +2198,8 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_fan_speed_percent)
+- ret = smu->funcs->set_fan_speed_percent(smu, speed);
++ if (smu->ppt_funcs->set_fan_speed_percent)
++ ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2219,8 +2226,8 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_deep_sleep_dcefclk)
+- ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
++ if (smu->ppt_funcs->set_deep_sleep_dcefclk)
++ ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2233,8 +2240,8 @@ int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_active_display_count)
+- ret = smu->funcs->set_active_display_count(smu, count);
++ if (smu->ppt_funcs->set_active_display_count)
++ ret = smu->ppt_funcs->set_active_display_count(smu, count);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2249,8 +2256,8 @@ int smu_get_clock_by_type(struct smu_context *smu,
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->get_clock_by_type)
+- ret = smu->funcs->get_clock_by_type(smu, type, clocks);
++ if (smu->ppt_funcs->get_clock_by_type)
++ ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2264,8 +2271,8 @@ int smu_get_max_high_clocks(struct smu_context *smu,
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->get_max_high_clocks)
+- ret = smu->funcs->get_max_high_clocks(smu, clocks);
++ if (smu->ppt_funcs->get_max_high_clocks)
++ ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2312,8 +2319,8 @@ int smu_display_clock_voltage_request(struct smu_context *smu,
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->display_clock_voltage_request)
+- ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
++ if (smu->ppt_funcs->display_clock_voltage_request)
++ ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2341,8 +2348,8 @@ int smu_notify_smu_enable_pwe(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->notify_smu_enable_pwe)
+- ret = smu->funcs->notify_smu_enable_pwe(smu);
++ if (smu->ppt_funcs->notify_smu_enable_pwe)
++ ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2356,8 +2363,8 @@ int smu_set_xgmi_pstate(struct smu_context *smu,
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_xgmi_pstate)
+- ret = smu->funcs->set_xgmi_pstate(smu, pstate);
++ if (smu->ppt_funcs->set_xgmi_pstate)
++ ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2370,8 +2377,8 @@ int smu_set_azalia_d3_pme(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->set_azalia_d3_pme)
+- ret = smu->funcs->set_azalia_d3_pme(smu);
++ if (smu->ppt_funcs->set_azalia_d3_pme)
++ ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2384,8 +2391,8 @@ bool smu_baco_is_support(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->baco_is_support)
+- ret = smu->funcs->baco_is_support(smu);
++ if (smu->ppt_funcs->baco_is_support)
++ ret = smu->ppt_funcs->baco_is_support(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2394,11 +2401,11 @@ bool smu_baco_is_support(struct smu_context *smu)
+
+ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
+ {
+- if (smu->funcs->baco_get_state)
++ if (smu->ppt_funcs->baco_get_state)
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+- *state = smu->funcs->baco_get_state(smu);
++ *state = smu->ppt_funcs->baco_get_state(smu);
+ mutex_unlock(&smu->mutex);
+
+ return 0;
+@@ -2410,8 +2417,8 @@ int smu_baco_reset(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->baco_reset)
+- ret = smu->funcs->baco_reset(smu);
++ if (smu->ppt_funcs->baco_reset)
++ ret = smu->ppt_funcs->baco_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2424,8 +2431,8 @@ int smu_mode2_reset(struct smu_context *smu)
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->mode2_reset)
+- ret = smu->funcs->mode2_reset(smu);
++ if (smu->ppt_funcs->mode2_reset)
++ ret = smu->ppt_funcs->mode2_reset(smu);
+
+ mutex_unlock(&smu->mutex);
+
+@@ -2439,8 +2446,8 @@ int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->funcs->get_max_sustainable_clocks_by_dc)
+- ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
++ if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
++ ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
+
+ mutex_unlock(&smu->mutex);
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index a2262464d141..ffefa89c295b 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1048,7 +1048,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ *size = 4;
+ break;
+ default:
+- ret = smu_smc_read_sensor(smu, sensor, data, size);
++ ret = smu_v11_0_read_sensor(smu, sensor, data, size);
+ }
+ mutex_unlock(&smu->sensor_lock);
+
+@@ -1964,6 +1964,55 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ .get_power_limit = arcturus_get_power_limit,
+ .is_dpm_running = arcturus_is_dpm_running,
+ .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
++ .init_microcode = smu_v11_0_init_microcode,
++ .load_microcode = smu_v11_0_load_microcode,
++ .init_smc_tables = smu_v11_0_init_smc_tables,
++ .fini_smc_tables = smu_v11_0_fini_smc_tables,
++ .init_power = smu_v11_0_init_power,
++ .fini_power = smu_v11_0_fini_power,
++ .check_fw_status = smu_v11_0_check_fw_status,
++ .setup_pptable = smu_v11_0_setup_pptable,
++ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
++ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
++ .check_pptable = smu_v11_0_check_pptable,
++ .parse_pptable = smu_v11_0_parse_pptable,
++ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
++ .check_fw_version = smu_v11_0_check_fw_version,
++ .write_pptable = smu_v11_0_write_pptable,
++ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
++ .set_tool_table_location = smu_v11_0_set_tool_table_location,
++ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
++ .system_features_control = smu_v11_0_system_features_control,
++ .send_smc_msg = smu_v11_0_send_msg,
++ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
++ .read_smc_arg = smu_v11_0_read_arg,
++ .init_display_count = smu_v11_0_init_display_count,
++ .set_allowed_mask = smu_v11_0_set_allowed_mask,
++ .get_enabled_mask = smu_v11_0_get_enabled_mask,
++ .notify_display_change = smu_v11_0_notify_display_change,
++ .set_power_limit = smu_v11_0_set_power_limit,
++ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
++ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
++ .start_thermal_control = smu_v11_0_start_thermal_control,
++ .stop_thermal_control = smu_v11_0_stop_thermal_control,
++ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
++ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
++ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
++ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
++ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
++ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
++ .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
++ .gfx_off_control = smu_v11_0_gfx_off_control,
++ .register_irq_handler = smu_v11_0_register_irq_handler,
++ .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
++ .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
++ .baco_is_support= smu_v11_0_baco_is_support,
++ .baco_get_state = smu_v11_0_baco_get_state,
++ .baco_set_state = smu_v11_0_baco_set_state,
++ .baco_reset = smu_v11_0_baco_reset,
++ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
++ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 79fe32acc838..402a021f237b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -347,7 +347,6 @@ struct smu_context
+ struct amdgpu_device *adev;
+ struct amdgpu_irq_src *irq_source;
+
+- const struct smu_funcs *funcs;
+ const struct pptable_funcs *ppt_funcs;
+ struct mutex mutex;
+ struct mutex sensor_lock;
+@@ -471,16 +470,12 @@ struct pptable_funcs {
+ int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
+ int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
+-};
+-
+-struct smu_funcs
+-{
+ int (*init_microcode)(struct smu_context *smu);
++ int (*load_microcode)(struct smu_context *smu);
+ int (*init_smc_tables)(struct smu_context *smu);
+ int (*fini_smc_tables)(struct smu_context *smu);
+ int (*init_power)(struct smu_context *smu);
+ int (*fini_power)(struct smu_context *smu);
+- int (*load_microcode)(struct smu_context *smu);
+ int (*check_fw_status)(struct smu_context *smu);
+ int (*setup_pptable)(struct smu_context *smu);
+ int (*get_vbios_bootup_values)(struct smu_context *smu);
+@@ -510,8 +505,6 @@ struct smu_funcs
+ int (*init_max_sustainable_clocks)(struct smu_context *smu);
+ int (*start_thermal_control)(struct smu_context *smu);
+ int (*stop_thermal_control)(struct smu_context *smu);
+- int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
+- void *data, uint32_t *size);
+ int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
+ int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
+ int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 6b2a901492b2..88ee66683271 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -131,6 +131,124 @@ enum smu_v11_0_baco_seq {
+ BACO_SEQ_COUNT,
+ };
+
+-void smu_v11_0_set_smu_funcs(struct smu_context *smu);
++int smu_v11_0_init_microcode(struct smu_context *smu);
++
++int smu_v11_0_load_microcode(struct smu_context *smu);
++
++int smu_v11_0_init_smc_tables(struct smu_context *smu);
++
++int smu_v11_0_fini_smc_tables(struct smu_context *smu);
++
++int smu_v11_0_init_power(struct smu_context *smu);
++
++int smu_v11_0_fini_power(struct smu_context *smu);
++
++int smu_v11_0_check_fw_status(struct smu_context *smu);
++
++int smu_v11_0_setup_pptable(struct smu_context *smu);
++
++int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
++
++int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
++
++int smu_v11_0_check_pptable(struct smu_context *smu);
++
++int smu_v11_0_parse_pptable(struct smu_context *smu);
++
++int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
++
++int smu_v11_0_check_fw_version(struct smu_context *smu);
++
++int smu_v11_0_write_pptable(struct smu_context *smu);
++
++int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
++
++int smu_v11_0_set_tool_table_location(struct smu_context *smu);
++
++int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
++
++int smu_v11_0_system_features_control(struct smu_context *smu,
++ bool en);
++
++int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
++
++int
++smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++ uint32_t param);
++
++int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
++
++int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
++
++int smu_v11_0_set_allowed_mask(struct smu_context *smu);
++
++int smu_v11_0_get_enabled_mask(struct smu_context *smu,
++ uint32_t *feature_mask, uint32_t num);
++
++int smu_v11_0_notify_display_change(struct smu_context *smu);
++
++int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
++
++int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
++ enum smu_clk_type clk_id,
++ uint32_t *value);
++
++int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
++
++int smu_v11_0_start_thermal_control(struct smu_context *smu);
++
++int smu_v11_0_stop_thermal_control(struct smu_context *smu);
++
++int smu_v11_0_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size);
++
++int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
++
++int
++smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
++ struct pp_display_clock_request
++ *clock_req);
++
++uint32_t
++smu_v11_0_get_fan_control_mode(struct smu_context *smu);
++
++int
++smu_v11_0_set_fan_control_mode(struct smu_context *smu,
++ uint32_t mode);
++
++int
++smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
++
++int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
++ uint32_t speed);
++
++int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
++ uint32_t pstate);
++
++int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
++
++int smu_v11_0_register_irq_handler(struct smu_context *smu);
++
++int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
++
++int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++ struct pp_smu_nv_clock_table *max_clocks);
++
++bool smu_v11_0_baco_is_support(struct smu_context *smu);
++
++enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
++
++int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
++
++int smu_v11_0_baco_reset(struct smu_context *smu);
++
++int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++ uint32_t *min, uint32_t *max);
++
++int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++ uint32_t min, uint32_t max);
++
++int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index acf3db12f59f..9b9f5df0911c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -37,6 +37,45 @@ struct smu_12_0_cmn2aisc_mapping {
+ int map_to;
+ };
+
+-void smu_v12_0_set_smu_funcs(struct smu_context *smu);
++int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
++ uint16_t msg);
++
++int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
++
++int smu_v12_0_wait_for_response(struct smu_context *smu);
++
++int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg);
++
++int
++smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++ uint32_t param);
++
++int smu_v12_0_check_fw_status(struct smu_context *smu);
++
++int smu_v12_0_check_fw_version(struct smu_context *smu);
++
++int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
++
++int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
++
++int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
++
++uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
++
++int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
++
++int smu_v12_0_init_smc_tables(struct smu_context *smu);
++
++int smu_v12_0_fini_smc_tables(struct smu_context *smu);
++
++int smu_v12_0_populate_smc_tables(struct smu_context *smu);
++
++int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++ uint32_t *min, uint32_t *max);
++
++int smu_v12_0_mode2_reset(struct smu_context *smu);
++
++int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++ uint32_t min, uint32_t max);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 54d5c91dda23..34390656a03e 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1268,8 +1268,7 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
+ clock_req.clock_type = amd_pp_dcef_clock;
+ clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+
+- if (smu->funcs->display_clock_voltage_request)
+- ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
++ ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
+ if (!ret) {
+ if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu,
+@@ -1424,7 +1423,7 @@ static int navi10_read_sensor(struct smu_context *smu,
+ *size = 4;
+ break;
+ default:
+- ret = smu_smc_read_sensor(smu, sensor, data, size);
++ ret = smu_v11_0_read_sensor(smu, sensor, data, size);
+ }
+ mutex_unlock(&smu->sensor_lock);
+
+@@ -1693,6 +1692,55 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
+ .get_power_limit = navi10_get_power_limit,
+ .update_pcie_parameters = navi10_update_pcie_parameters,
++ .init_microcode = smu_v11_0_init_microcode,
++ .load_microcode = smu_v11_0_load_microcode,
++ .init_smc_tables = smu_v11_0_init_smc_tables,
++ .fini_smc_tables = smu_v11_0_fini_smc_tables,
++ .init_power = smu_v11_0_init_power,
++ .fini_power = smu_v11_0_fini_power,
++ .check_fw_status = smu_v11_0_check_fw_status,
++ .setup_pptable = smu_v11_0_setup_pptable,
++ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
++ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
++ .check_pptable = smu_v11_0_check_pptable,
++ .parse_pptable = smu_v11_0_parse_pptable,
++ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
++ .check_fw_version = smu_v11_0_check_fw_version,
++ .write_pptable = smu_v11_0_write_pptable,
++ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
++ .set_tool_table_location = smu_v11_0_set_tool_table_location,
++ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
++ .system_features_control = smu_v11_0_system_features_control,
++ .send_smc_msg = smu_v11_0_send_msg,
++ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
++ .read_smc_arg = smu_v11_0_read_arg,
++ .init_display_count = smu_v11_0_init_display_count,
++ .set_allowed_mask = smu_v11_0_set_allowed_mask,
++ .get_enabled_mask = smu_v11_0_get_enabled_mask,
++ .notify_display_change = smu_v11_0_notify_display_change,
++ .set_power_limit = smu_v11_0_set_power_limit,
++ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
++ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
++ .start_thermal_control = smu_v11_0_start_thermal_control,
++ .stop_thermal_control = smu_v11_0_stop_thermal_control,
++ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
++ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
++ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
++ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
++ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
++ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
++ .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
++ .gfx_off_control = smu_v11_0_gfx_off_control,
++ .register_irq_handler = smu_v11_0_register_irq_handler,
++ .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
++ .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
++ .baco_is_support= smu_v11_0_baco_is_support,
++ .baco_get_state = smu_v11_0_baco_get_state,
++ .baco_set_state = smu_v11_0_baco_set_state,
++ .baco_reset = smu_v11_0_baco_reset,
++ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
++ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 6df91b1a9daa..45c5f54e60d8 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -691,6 +691,21 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_dpm_clock_table = renoir_get_dpm_clock_table,
+ .set_watermarks_table = renoir_set_watermarks_table,
+ .get_power_profile_mode = renoir_get_power_profile_mode,
++ .check_fw_status = smu_v12_0_check_fw_status,
++ .check_fw_version = smu_v12_0_check_fw_version,
++ .powergate_sdma = smu_v12_0_powergate_sdma,
++ .powergate_vcn = smu_v12_0_powergate_vcn,
++ .send_smc_msg = smu_v12_0_send_msg,
++ .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
++ .read_smc_arg = smu_v12_0_read_arg,
++ .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
++ .gfx_off_control = smu_v12_0_gfx_off_control,
++ .init_smc_tables = smu_v12_0_init_smc_tables,
++ .fini_smc_tables = smu_v12_0_fini_smc_tables,
++ .populate_smc_tables = smu_v12_0_populate_smc_tables,
++ .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
++ .mode2_reset = smu_v12_0_mode2_reset,
++ .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
+ };
+
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index c26eede7e36a..8bcda7871309 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -26,73 +26,73 @@
+ #include "amdgpu_smu.h"
+
+ #define smu_init_microcode(smu) \
+- ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
++ ((smu)->ppt_funcs->init_microcode ? (smu)->ppt_funcs->init_microcode((smu)) : 0)
+ #define smu_init_smc_tables(smu) \
+- ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
++ ((smu)->ppt_funcs->init_smc_tables ? (smu)->ppt_funcs->init_smc_tables((smu)) : 0)
+ #define smu_fini_smc_tables(smu) \
+- ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
++ ((smu)->ppt_funcs->fini_smc_tables ? (smu)->ppt_funcs->fini_smc_tables((smu)) : 0)
+ #define smu_init_power(smu) \
+- ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
++ ((smu)->ppt_funcs->init_power ? (smu)->ppt_funcs->init_power((smu)) : 0)
+ #define smu_fini_power(smu) \
+- ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
++ ((smu)->ppt_funcs->fini_power ? (smu)->ppt_funcs->fini_power((smu)) : 0)
+
+ #define smu_setup_pptable(smu) \
+- ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
++ ((smu)->ppt_funcs->setup_pptable ? (smu)->ppt_funcs->setup_pptable((smu)) : 0)
+ #define smu_powergate_sdma(smu, gate) \
+- ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
++ ((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_powergate_vcn(smu, gate) \
+- ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
++ ((smu)->ppt_funcs->powergate_vcn ? (smu)->ppt_funcs->powergate_vcn((smu), (gate)) : 0)
+
+ #define smu_get_vbios_bootup_values(smu) \
+- ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
++ ((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
+ #define smu_get_clk_info_from_vbios(smu) \
+- ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
++ ((smu)->ppt_funcs->get_clk_info_from_vbios ? (smu)->ppt_funcs->get_clk_info_from_vbios((smu)) : 0)
+ #define smu_check_pptable(smu) \
+- ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
++ ((smu)->ppt_funcs->check_pptable ? (smu)->ppt_funcs->check_pptable((smu)) : 0)
+ #define smu_parse_pptable(smu) \
+- ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
++ ((smu)->ppt_funcs->parse_pptable ? (smu)->ppt_funcs->parse_pptable((smu)) : 0)
+ #define smu_populate_smc_tables(smu) \
+- ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
++ ((smu)->ppt_funcs->populate_smc_tables ? (smu)->ppt_funcs->populate_smc_tables((smu)) : 0)
+ #define smu_check_fw_version(smu) \
+- ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
++ ((smu)->ppt_funcs->check_fw_version ? (smu)->ppt_funcs->check_fw_version((smu)) : 0)
+ #define smu_write_pptable(smu) \
+- ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
++ ((smu)->ppt_funcs->write_pptable ? (smu)->ppt_funcs->write_pptable((smu)) : 0)
+ #define smu_set_min_dcef_deep_sleep(smu) \
+- ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
++ ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep((smu)) : 0)
+ #define smu_set_tool_table_location(smu) \
+- ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
++ ((smu)->ppt_funcs->set_tool_table_location ? (smu)->ppt_funcs->set_tool_table_location((smu)) : 0)
+ #define smu_notify_memory_pool_location(smu) \
+- ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
++ ((smu)->ppt_funcs->notify_memory_pool_location ? (smu)->ppt_funcs->notify_memory_pool_location((smu)) : 0)
+ #define smu_gfx_off_control(smu, enable) \
+- ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
++ ((smu)->ppt_funcs->gfx_off_control ? (smu)->ppt_funcs->gfx_off_control((smu), (enable)) : 0)
+
+ #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+- ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
++ ((smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+ #define smu_system_features_control(smu, en) \
+- ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
++ ((smu)->ppt_funcs->system_features_control ? (smu)->ppt_funcs->system_features_control((smu), (en)) : 0)
+ #define smu_init_max_sustainable_clocks(smu) \
+- ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
++ ((smu)->ppt_funcs->init_max_sustainable_clocks ? (smu)->ppt_funcs->init_max_sustainable_clocks((smu)) : 0)
+ #define smu_set_default_od_settings(smu, initialize) \
+ ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+
+ #define smu_send_smc_msg(smu, msg) \
+- ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
++ ((smu)->ppt_funcs->send_smc_msg? (smu)->ppt_funcs->send_smc_msg((smu), (msg)) : 0)
+ #define smu_send_smc_msg_with_param(smu, msg, param) \
+- ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
++ ((smu)->ppt_funcs->send_smc_msg_with_param? (smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+ #define smu_read_smc_arg(smu, arg) \
+- ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
++ ((smu)->ppt_funcs->read_smc_arg? (smu)->ppt_funcs->read_smc_arg((smu), (arg)) : 0)
+ #define smu_alloc_dpm_context(smu) \
+ ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
+ #define smu_init_display_count(smu, count) \
+- ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
++ ((smu)->ppt_funcs->init_display_count ? (smu)->ppt_funcs->init_display_count((smu), (count)) : 0)
+ #define smu_feature_set_allowed_mask(smu) \
+- ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
++ ((smu)->ppt_funcs->set_allowed_mask? (smu)->ppt_funcs->set_allowed_mask((smu)) : 0)
+ #define smu_feature_get_enabled_mask(smu, mask, num) \
+- ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
++ ((smu)->ppt_funcs->get_enabled_mask? (smu)->ppt_funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+ #define smu_is_dpm_running(smu) \
+ ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
+ #define smu_notify_display_change(smu) \
+- ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
++ ((smu)->ppt_funcs->notify_display_change? (smu)->ppt_funcs->notify_display_change((smu)) : 0)
+ #define smu_store_powerplay_table(smu) \
+ ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
+ #define smu_check_powerplay_table(smu) \
+@@ -107,19 +107,19 @@
+ ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+
+ #define smu_get_current_clk_freq(smu, clk_id, value) \
+- ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
++ ((smu)->ppt_funcs->get_current_clk_freq? (smu)->ppt_funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+
+ #define smu_tables_init(smu, tab) \
+ ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
+ #define smu_set_thermal_fan_table(smu) \
+ ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
+ #define smu_start_thermal_control(smu) \
+- ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
++ ((smu)->ppt_funcs->start_thermal_control? (smu)->ppt_funcs->start_thermal_control((smu)) : 0)
+ #define smu_stop_thermal_control(smu) \
+- ((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
++ ((smu)->ppt_funcs->stop_thermal_control? (smu)->ppt_funcs->stop_thermal_control((smu)) : 0)
+
+ #define smu_smc_read_sensor(smu, sensor, data, size) \
+- ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
++ ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+
+ #define smu_pre_display_config_changed(smu) \
+ ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+@@ -157,14 +157,14 @@
+
+
+ #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+- ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
++ ((smu)->ppt_funcs->store_cc6_data ? (smu)->ppt_funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+
+ #define smu_get_dal_power_level(smu, clocks) \
+- ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
++ ((smu)->ppt_funcs->get_dal_power_level ? (smu)->ppt_funcs->get_dal_power_level((smu), (clocks)) : 0)
+ #define smu_get_perf_level(smu, designation, level) \
+- ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
++ ((smu)->ppt_funcs->get_perf_level ? (smu)->ppt_funcs->get_perf_level((smu), (designation), (level)) : 0)
+ #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+- ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
++ ((smu)->ppt_funcs->get_current_shallow_sleep_clocks ? (smu)->ppt_funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+
+ #define smu_dpm_set_uvd_enable(smu, enable) \
+ ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+@@ -180,10 +180,10 @@
+ #define smu_get_thermal_temperature_range(smu, range) \
+ ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
+ #define smu_register_irq_handler(smu) \
+- ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
++ ((smu)->ppt_funcs->register_irq_handler ? (smu)->ppt_funcs->register_irq_handler(smu) : 0)
+
+ #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+- ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
++ ((smu)->ppt_funcs->get_dpm_ultimate_freq ? (smu)->ppt_funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+
+ #define smu_asic_set_performance_level(smu, level) \
+ ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+@@ -193,10 +193,10 @@
+ ((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+- ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
++ ((smu)->ppt_funcs->set_soft_freq_limited_range ? (smu)->ppt_funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+
+ #define smu_override_pcie_parameters(smu) \
+- ((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
++ ((smu)->ppt_funcs->override_pcie_parameters ? (smu)->ppt_funcs->override_pcie_parameters((smu)) : 0)
+
+ #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
+ ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 6794fc4cacb5..7e882999abad 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -30,9 +30,6 @@
+ #include "smu_v11_0.h"
+ #include "soc15_common.h"
+ #include "atom.h"
+-#include "vega20_ppt.h"
+-#include "arcturus_ppt.h"
+-#include "navi10_ppt.h"
+ #include "amd_pcie.h"
+
+ #include "asic_reg/thm/thm_11_0_2_offset.h"
+@@ -60,7 +57,7 @@ static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
+ return 0;
+ }
+
+-static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
++int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
+ {
+ struct amdgpu_device *adev = smu->adev;
+
+@@ -87,7 +84,7 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+
+-static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
++int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0, index = 0;
+@@ -112,7 +109,7 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+
+ }
+
+-static int
++int
+ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ uint32_t param)
+ {
+@@ -143,7 +140,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ return ret;
+ }
+
+-static int smu_v11_0_init_microcode(struct smu_context *smu)
++int smu_v11_0_init_microcode(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ const char *chip_name;
+@@ -205,7 +202,7 @@ static int smu_v11_0_init_microcode(struct smu_context *smu)
+ return err;
+ }
+
+-static int smu_v11_0_load_microcode(struct smu_context *smu)
++int smu_v11_0_load_microcode(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ const uint32_t *src;
+@@ -243,7 +240,7 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_check_fw_status(struct smu_context *smu)
++int smu_v11_0_check_fw_status(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t mp1_fw_flags;
+@@ -258,7 +255,7 @@ static int smu_v11_0_check_fw_status(struct smu_context *smu)
+ return -EIO;
+ }
+
+-static int smu_v11_0_check_fw_version(struct smu_context *smu)
++int smu_v11_0_check_fw_version(struct smu_context *smu)
+ {
+ uint32_t if_version = 0xff, smu_version = 0xff;
+ uint16_t smu_major;
+@@ -356,7 +353,7 @@ static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
+ return 0;
+ }
+
+-static int smu_v11_0_setup_pptable(struct smu_context *smu)
++int smu_v11_0_setup_pptable(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ const struct smc_firmware_header_v1_0 *hdr;
+@@ -435,7 +432,7 @@ static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_init_smc_tables(struct smu_context *smu)
++int smu_v11_0_init_smc_tables(struct smu_context *smu)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = NULL;
+@@ -462,7 +459,7 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
++int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+ int ret = 0;
+@@ -482,7 +479,7 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_init_power(struct smu_context *smu)
++int smu_v11_0_init_power(struct smu_context *smu)
+ {
+ struct smu_power_context *smu_power = &smu->smu_power;
+
+@@ -500,7 +497,7 @@ static int smu_v11_0_init_power(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_fini_power(struct smu_context *smu)
++int smu_v11_0_fini_power(struct smu_context *smu)
+ {
+ struct smu_power_context *smu_power = &smu->smu_power;
+
+@@ -577,7 +574,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
++int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+ {
+ int ret, index;
+ struct amdgpu_device *adev = smu->adev;
+@@ -674,7 +671,7 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
++int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *memory_pool = &smu_table->memory_pool;
+@@ -720,7 +717,7 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_check_pptable(struct smu_context *smu)
++int smu_v11_0_check_pptable(struct smu_context *smu)
+ {
+ int ret;
+
+@@ -728,7 +725,7 @@ static int smu_v11_0_check_pptable(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_parse_pptable(struct smu_context *smu)
++int smu_v11_0_parse_pptable(struct smu_context *smu)
+ {
+ int ret;
+
+@@ -752,7 +749,7 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
++int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
+ {
+ int ret;
+
+@@ -761,7 +758,7 @@ static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_write_pptable(struct smu_context *smu)
++int smu_v11_0_write_pptable(struct smu_context *smu)
+ {
+ struct smu_table_context *table_context = &smu->smu_table;
+ int ret = 0;
+@@ -772,7 +769,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
++int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+ {
+ int ret;
+
+@@ -784,7 +781,7 @@ static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t cl
+ return ret;
+ }
+
+-static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
++int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+ {
+ struct smu_table_context *table_context = &smu->smu_table;
+
+@@ -793,14 +790,10 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+ if (!table_context)
+ return -EINVAL;
+
+- if (smu->funcs->set_deep_sleep_dcefclk)
+- return smu->funcs->set_deep_sleep_dcefclk(smu,
+- table_context->boot_values.dcefclk / 100);
+-
+- return 0;
++ return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
+ }
+
+-static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
++int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+ {
+ int ret = 0;
+ struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
+@@ -818,7 +811,7 @@ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
++int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
+ {
+ int ret = 0;
+
+@@ -830,7 +823,7 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
+ }
+
+
+-static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
++int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+ {
+ struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+@@ -857,7 +850,7 @@ static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
++int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+ uint32_t *feature_mask, uint32_t num)
+ {
+ uint32_t feature_mask_high = 0, feature_mask_low = 0;
+@@ -886,7 +879,7 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+ return ret;
+ }
+
+-static int smu_v11_0_system_features_control(struct smu_context *smu,
++int smu_v11_0_system_features_control(struct smu_context *smu,
+ bool en)
+ {
+ struct smu_feature *feature = &smu->smu_feature;
+@@ -912,7 +905,7 @@ static int smu_v11_0_system_features_control(struct smu_context *smu,
+ return ret;
+ }
+
+-static int smu_v11_0_notify_display_change(struct smu_context *smu)
++int smu_v11_0_notify_display_change(struct smu_context *smu)
+ {
+ int ret = 0;
+
+@@ -970,7 +963,7 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
+ return ret;
+ }
+
+-static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
++int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+ {
+ struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
+ int ret = 0;
+@@ -1050,7 +1043,7 @@ static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
++int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ {
+ int ret = 0;
+
+@@ -1078,7 +1071,7 @@ static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ return 0;
+ }
+
+-static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
++int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+ enum smu_clk_type clk_id,
+ uint32_t *value)
+ {
+@@ -1157,7 +1150,7 @@ static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v11_0_start_thermal_control(struct smu_context *smu)
++int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ {
+ int ret = 0;
+ struct smu_temperature_range range;
+@@ -1199,7 +1192,7 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_stop_thermal_control(struct smu_context *smu)
++int smu_v11_0_stop_thermal_control(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+
+@@ -1232,7 +1225,7 @@ static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
+
+ }
+
+-static int smu_v11_0_read_sensor(struct smu_context *smu,
++int smu_v11_0_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+ {
+@@ -1269,7 +1262,7 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
+ return ret;
+ }
+
+-static int
++int
+ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request
+ *clock_req)
+@@ -1322,7 +1315,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ return ret;
+ }
+
+-static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
++int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ {
+ int ret = 0;
+ struct amdgpu_device *adev = smu->adev;
+@@ -1347,7 +1340,7 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ return ret;
+ }
+
+-static uint32_t
++uint32_t
+ smu_v11_0_get_fan_control_mode(struct smu_context *smu)
+ {
+ if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+@@ -1387,7 +1380,7 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
+ return 0;
+ }
+
+-static int
++int
+ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+ {
+ struct amdgpu_device *adev = smu->adev;
+@@ -1416,7 +1409,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+ return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
+ }
+
+-static int
++int
+ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+ uint32_t mode)
+ {
+@@ -1444,7 +1437,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+ return ret;
+ }
+
+-static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
++int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ uint32_t speed)
+ {
+ struct amdgpu_device *adev = smu->adev;
+@@ -1473,7 +1466,7 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ #define XGMI_STATE_D0 1
+ #define XGMI_STATE_D3 0
+
+-static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
++int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate)
+ {
+ int ret = 0;
+@@ -1525,7 +1518,7 @@ static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs= {
+ .process = smu_v11_0_irq_process,
+ };
+
+-static int smu_v11_0_register_irq_handler(struct smu_context *smu)
++int smu_v11_0_register_irq_handler(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ struct amdgpu_irq_src *irq_src = smu->irq_source;
+@@ -1557,7 +1550,7 @@ static int smu_v11_0_register_irq_handler(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks)
+ {
+ struct smu_table_context *table_context = &smu->smu_table;
+@@ -1587,7 +1580,7 @@ static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ return 0;
+ }
+
+-static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
++int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
+ {
+ int ret = 0;
+
+@@ -1601,7 +1594,7 @@ static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v
+ return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
+ }
+
+-static bool smu_v11_0_baco_is_support(struct smu_context *smu)
++bool smu_v11_0_baco_is_support(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ struct smu_baco_context *smu_baco = &smu->smu_baco;
+@@ -1625,7 +1618,7 @@ static bool smu_v11_0_baco_is_support(struct smu_context *smu)
+ return false;
+ }
+
+-static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
++enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
+ {
+ struct smu_baco_context *smu_baco = &smu->smu_baco;
+ enum smu_baco_state baco_state;
+@@ -1637,7 +1630,7 @@ static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
+ return baco_state;
+ }
+
+-static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
++int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ {
+
+ struct smu_baco_context *smu_baco = &smu->smu_baco;
+@@ -1661,7 +1654,7 @@ static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state
+ return ret;
+ }
+
+-static int smu_v11_0_baco_reset(struct smu_context *smu)
++int smu_v11_0_baco_reset(struct smu_context *smu)
+ {
+ int ret = 0;
+
+@@ -1682,7 +1675,7 @@ static int smu_v11_0_baco_reset(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *min, uint32_t *max)
+ {
+ int ret = 0, clk_id = 0;
+@@ -1717,7 +1710,7 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ return ret;
+ }
+
+-static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t min, uint32_t max)
+ {
+ int ret = 0, clk_id = 0;
+@@ -1746,7 +1739,7 @@ static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
+ return ret;
+ }
+
+-static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
++int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t pcie_gen = 0, pcie_width = 0;
+@@ -1786,79 +1779,3 @@ static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+ return ret;
+
+ }
+-
+-
+-static const struct smu_funcs smu_v11_0_funcs = {
+- .init_microcode = smu_v11_0_init_microcode,
+- .load_microcode = smu_v11_0_load_microcode,
+- .check_fw_status = smu_v11_0_check_fw_status,
+- .check_fw_version = smu_v11_0_check_fw_version,
+- .send_smc_msg = smu_v11_0_send_msg,
+- .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+- .read_smc_arg = smu_v11_0_read_arg,
+- .setup_pptable = smu_v11_0_setup_pptable,
+- .init_smc_tables = smu_v11_0_init_smc_tables,
+- .fini_smc_tables = smu_v11_0_fini_smc_tables,
+- .init_power = smu_v11_0_init_power,
+- .fini_power = smu_v11_0_fini_power,
+- .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+- .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+- .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+- .check_pptable = smu_v11_0_check_pptable,
+- .parse_pptable = smu_v11_0_parse_pptable,
+- .populate_smc_tables = smu_v11_0_populate_smc_pptable,
+- .write_pptable = smu_v11_0_write_pptable,
+- .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+- .set_tool_table_location = smu_v11_0_set_tool_table_location,
+- .init_display_count = smu_v11_0_init_display_count,
+- .set_allowed_mask = smu_v11_0_set_allowed_mask,
+- .get_enabled_mask = smu_v11_0_get_enabled_mask,
+- .system_features_control = smu_v11_0_system_features_control,
+- .notify_display_change = smu_v11_0_notify_display_change,
+- .set_power_limit = smu_v11_0_set_power_limit,
+- .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+- .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+- .start_thermal_control = smu_v11_0_start_thermal_control,
+- .stop_thermal_control = smu_v11_0_stop_thermal_control,
+- .read_sensor = smu_v11_0_read_sensor,
+- .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+- .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+- .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+- .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+- .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+- .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+- .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+- .gfx_off_control = smu_v11_0_gfx_off_control,
+- .register_irq_handler = smu_v11_0_register_irq_handler,
+- .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+- .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+- .baco_is_support= smu_v11_0_baco_is_support,
+- .baco_get_state = smu_v11_0_baco_get_state,
+- .baco_set_state = smu_v11_0_baco_set_state,
+- .baco_reset = smu_v11_0_baco_reset,
+- .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+- .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+- .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+-};
+-
+-void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+-{
+- struct amdgpu_device *adev = smu->adev;
+-
+- smu->funcs = &smu_v11_0_funcs;
+- switch (adev->asic_type) {
+- case CHIP_VEGA20:
+- vega20_set_ppt_funcs(smu);
+- break;
+- case CHIP_ARCTURUS:
+- arcturus_set_ppt_funcs(smu);
+- break;
+- case CHIP_NAVI10:
+- case CHIP_NAVI14:
+- case CHIP_NAVI12:
+- navi10_set_ppt_funcs(smu);
+- break;
+- default:
+- pr_warn("Unknown asic for smu11\n");
+- }
+-}
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 92e1c0a3f428..139dd737eaa5 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -30,7 +30,6 @@
+ #include "smu_v12_0.h"
+ #include "soc15_common.h"
+ #include "atom.h"
+-#include "renoir_ppt.h"
+
+ #include "asic_reg/mp/mp_12_0_0_offset.h"
+ #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
+@@ -42,7 +41,7 @@
+ #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
+ #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
+
+-static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
++int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ uint16_t msg)
+ {
+ struct amdgpu_device *adev = smu->adev;
+@@ -51,7 +50,7 @@ static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ return 0;
+ }
+
+-static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
++int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
+ {
+ struct amdgpu_device *adev = smu->adev;
+
+@@ -59,7 +58,7 @@ static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
+ return 0;
+ }
+
+-static int smu_v12_0_wait_for_response(struct smu_context *smu)
++int smu_v12_0_wait_for_response(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t cur_value, i;
+@@ -78,7 +77,7 @@ static int smu_v12_0_wait_for_response(struct smu_context *smu)
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+
+-static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
++int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0, index = 0;
+@@ -103,7 +102,7 @@ static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+
+ }
+
+-static int
++int
+ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ uint32_t param)
+ {
+@@ -133,7 +132,7 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ return ret;
+ }
+
+-static int smu_v12_0_check_fw_status(struct smu_context *smu)
++int smu_v12_0_check_fw_status(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t mp1_fw_flags;
+@@ -148,7 +147,7 @@ static int smu_v12_0_check_fw_status(struct smu_context *smu)
+ return -EIO;
+ }
+
+-static int smu_v12_0_check_fw_version(struct smu_context *smu)
++int smu_v12_0_check_fw_version(struct smu_context *smu)
+ {
+ uint32_t if_version = 0xff, smu_version = 0xff;
+ uint16_t smu_major;
+@@ -182,7 +181,7 @@ static int smu_v12_0_check_fw_version(struct smu_context *smu)
+ return ret;
+ }
+
+-static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
++int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+ {
+ if (!(smu->adev->flags & AMD_IS_APU))
+ return 0;
+@@ -193,7 +192,7 @@ static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+ return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
+ }
+
+-static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
++int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+ {
+ if (!(smu->adev->flags & AMD_IS_APU))
+ return 0;
+@@ -204,7 +203,7 @@ static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+ return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
+ }
+
+-static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
++int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ {
+ if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+ return 0;
+@@ -225,7 +224,7 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */
+-static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
++uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
+ {
+ uint32_t reg;
+ uint32_t gfxOff_Status = 0;
+@@ -238,7 +237,7 @@ static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
+ return gfxOff_Status;
+ }
+
+-static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
++int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ {
+ int ret = 0, timeout = 500;
+
+@@ -262,7 +261,7 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ return ret;
+ }
+
+-static int smu_v12_0_init_smc_tables(struct smu_context *smu)
++int smu_v12_0_init_smc_tables(struct smu_context *smu)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = NULL;
+@@ -280,7 +279,7 @@ static int smu_v12_0_init_smc_tables(struct smu_context *smu)
+ return smu_tables_init(smu, tables);
+ }
+
+-static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
++int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+@@ -296,7 +295,7 @@ static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+ return 0;
+ }
+
+-static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
++int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *table = NULL;
+@@ -311,7 +310,7 @@ static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+ }
+
+-static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *min, uint32_t *max)
+ {
+ int ret = 0;
+@@ -389,11 +388,11 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ return ret;
+ }
+
+-static int smu_v12_0_mode2_reset(struct smu_context *smu){
++int smu_v12_0_mode2_reset(struct smu_context *smu){
+ return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
+ }
+
+-static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t min, uint32_t max)
+ {
+ int ret = 0;
+@@ -446,36 +445,3 @@ static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
+
+ return ret;
+ }
+-
+-static const struct smu_funcs smu_v12_0_funcs = {
+- .check_fw_status = smu_v12_0_check_fw_status,
+- .check_fw_version = smu_v12_0_check_fw_version,
+- .powergate_sdma = smu_v12_0_powergate_sdma,
+- .powergate_vcn = smu_v12_0_powergate_vcn,
+- .send_smc_msg = smu_v12_0_send_msg,
+- .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+- .read_smc_arg = smu_v12_0_read_arg,
+- .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+- .gfx_off_control = smu_v12_0_gfx_off_control,
+- .init_smc_tables = smu_v12_0_init_smc_tables,
+- .fini_smc_tables = smu_v12_0_fini_smc_tables,
+- .populate_smc_tables = smu_v12_0_populate_smc_tables,
+- .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+- .mode2_reset = smu_v12_0_mode2_reset,
+- .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
+-};
+-
+-void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-{
+- struct amdgpu_device *adev = smu->adev;
+-
+- smu->funcs = &smu_v12_0_funcs;
+-
+- switch (adev->asic_type) {
+- case CHIP_RENOIR:
+- renoir_set_ppt_funcs(smu);
+- break;
+- default:
+- pr_warn("Unknown asic for smu12\n");
+- }
+-}
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 4039efcdcb1f..7125406c6256 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -2248,7 +2248,7 @@ vega20_notify_smc_dispaly_config(struct smu_context *smu)
+ if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ clock_req.clock_type = amd_pp_dcef_clock;
+ clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+- if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
++ if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) {
+ if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetMinDeepSleepDcefclk,
+@@ -3031,7 +3031,7 @@ static int vega20_read_sensor(struct smu_context *smu,
+ *size = 4;
+ break;
+ default:
+- ret = smu_smc_read_sensor(smu, sensor, data, size);
++ ret = smu_v11_0_read_sensor(smu, sensor, data, size);
+ }
+ mutex_unlock(&smu->sensor_lock);
+
+@@ -3212,7 +3212,56 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ .set_watermarks_table = vega20_set_watermarks_table,
+ .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
+ .set_df_cstate = vega20_set_df_cstate,
+- .update_pcie_parameters = vega20_update_pcie_parameters
++ .update_pcie_parameters = vega20_update_pcie_parameters,
++ .init_microcode = smu_v11_0_init_microcode,
++ .load_microcode = smu_v11_0_load_microcode,
++ .init_smc_tables = smu_v11_0_init_smc_tables,
++ .fini_smc_tables = smu_v11_0_fini_smc_tables,
++ .init_power = smu_v11_0_init_power,
++ .fini_power = smu_v11_0_fini_power,
++ .check_fw_status = smu_v11_0_check_fw_status,
++ .setup_pptable = smu_v11_0_setup_pptable,
++ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
++ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
++ .check_pptable = smu_v11_0_check_pptable,
++ .parse_pptable = smu_v11_0_parse_pptable,
++ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
++ .check_fw_version = smu_v11_0_check_fw_version,
++ .write_pptable = smu_v11_0_write_pptable,
++ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
++ .set_tool_table_location = smu_v11_0_set_tool_table_location,
++ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
++ .system_features_control = smu_v11_0_system_features_control,
++ .send_smc_msg = smu_v11_0_send_msg,
++ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
++ .read_smc_arg = smu_v11_0_read_arg,
++ .init_display_count = smu_v11_0_init_display_count,
++ .set_allowed_mask = smu_v11_0_set_allowed_mask,
++ .get_enabled_mask = smu_v11_0_get_enabled_mask,
++ .notify_display_change = smu_v11_0_notify_display_change,
++ .set_power_limit = smu_v11_0_set_power_limit,
++ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
++ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
++ .start_thermal_control = smu_v11_0_start_thermal_control,
++ .stop_thermal_control = smu_v11_0_stop_thermal_control,
++ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
++ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
++ .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
++ .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
++ .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
++ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
++ .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
++ .gfx_off_control = smu_v11_0_gfx_off_control,
++ .register_irq_handler = smu_v11_0_register_irq_handler,
++ .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
++ .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
++ .baco_is_support= smu_v11_0_baco_is_support,
++ .baco_get_state = smu_v11_0_baco_get_state,
++ .baco_set_state = smu_v11_0_baco_set_state,
++ .baco_reset = smu_v11_0_baco_reset,
++ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
++ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+
+ void vega20_set_ppt_funcs(struct smu_context *smu)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4269-drm-amdgpu-display-add-dc-feature-mask-for-psr-enabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4269-drm-amdgpu-display-add-dc-feature-mask-for-psr-enabl.patch
new file mode 100644
index 00000000..a65a287e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4269-drm-amdgpu-display-add-dc-feature-mask-for-psr-enabl.patch
@@ -0,0 +1,51 @@
+From 01086a885fa31e3d4a9047d8cdddf21decd987f1 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Tue, 1 Oct 2019 09:45:38 -0400
+Subject: [PATCH 4269/4736] drm/amdgpu/display: add dc feature mask for psr
+ enablement
+
+[Why]
+Adding psr mask to dc features allows selectively disable/enable psr.
+Current psr implementation may not work with non-pageflipping application.
+Until resolved it should be disabled by default.
+
+[How]
+Add dcfeaturemask for psr enablement. Disable by default.
+To enable set amdgpu.dcfeaturemask=0x8 in grub kernel command line.
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
+ drivers/gpu/drm/amd/include/amd_shared.h | 1 +
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 8139cffd5b88..ff89ca40f82c 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2406,7 +2406,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
+ amdgpu_dm_update_connector_after_detect(aconnector);
+ register_backlight_device(dm, link);
+- amdgpu_dm_set_psr_caps(link);
++ if (amdgpu_dc_feature_mask & DC_PSR_MASK)
++ amdgpu_dm_set_psr_caps(link);
+ }
+
+
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index 8889aaceec60..8340ec0ab792 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -143,6 +143,7 @@ enum PP_FEATURE_MASK {
+ enum DC_FEATURE_MASK {
+ DC_FBC_MASK = 0x1,
+ DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
++ DC_PSR_MASK = 0x8,
+ };
+
+ enum amd_dpm_forced_level;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4270-drm-amd-display-Change-Navi14-s-DWB-flag-to-1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4270-drm-amd-display-Change-Navi14-s-DWB-flag-to-1.patch
new file mode 100644
index 00000000..2632fc48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4270-drm-amd-display-Change-Navi14-s-DWB-flag-to-1.patch
@@ -0,0 +1,36 @@
+From b1dc55ff5d1670435b9aadcca3436248bb387ecb Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Tue, 22 Oct 2019 10:50:21 -0400
+Subject: [PATCH 4270/4736] drm/amd/display: Change Navi14's DWB flag to 1
+
+[Why]
+DWB (Display Writeback) flag needs to be enabled as 1, or system
+will throw out a few warnings when creating dcn20 resource pool.
+Also, Navi14's dwb setting needs to match Navi10's,
+which has already been set to 1.
+
+[How]
+Change value of num_dwb from 0 to 1.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index b6ec81096d3a..d1c7e10cb722 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -823,7 +823,7 @@ static const struct resource_caps res_cap_nv14 = {
+ .num_audio = 6,
+ .num_stream_encoder = 5,
+ .num_pll = 5,
+- .num_dwb = 0,
++ .num_dwb = 1,
+ .num_ddc = 5,
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4271-drm-amdkfd-don-t-use-dqm-lock-during-device-reset-su.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4271-drm-amdkfd-don-t-use-dqm-lock-during-device-reset-su.patch
new file mode 100644
index 00000000..6c12980b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4271-drm-amdkfd-don-t-use-dqm-lock-during-device-reset-su.patch
@@ -0,0 +1,264 @@
+From e4339c1a7be1491127ecfb14b1631197e5fdb28b Mon Sep 17 00:00:00 2001
+From: Philip Yang <Philip.Yang@amd.com>
+Date: Fri, 18 Oct 2019 10:15:21 -0400
+Subject: [PATCH 4271/4736] drm/amdkfd: don't use dqm lock during device
+ reset/suspend/resume
+
+If device reset/suspend/resume failed for some reason, dqm lock is
+hold forever and this causes deadlock. Below is a kernel backtrace when
+application open kfd after suspend/resume failed.
+
+Instead of holding dqm lock in pre_reset and releasing dqm lock in
+post_reset, add dqm->sched_running flag which is modified in
+dqm->ops.start and dqm->ops.stop. The flag doesn't need lock protection
+because write/read are all inside dqm lock.
+
+For HWS case, map_queues_cpsch and unmap_queues_cpsch checks
+sched_running flag before sending the updated runlist.
+
+v2: For no-HWS case, when device is stopped, don't call
+load/destroy_mqd for eviction, restore and create queue, and avoid
+debugfs dump hdqs.
+
+Backtrace of dqm lock deadlock:
+
+[Thu Oct 17 16:43:37 2019] INFO: task rocminfo:3024 blocked for more
+than 120 seconds.
+[Thu Oct 17 16:43:37 2019] Not tainted
+5.0.0-rc1-kfd-compute-rocm-dkms-no-npi-1131 #1
+[Thu Oct 17 16:43:37 2019] "echo 0 >
+/proc/sys/kernel/hung_task_timeout_secs" disables this message.
+[Thu Oct 17 16:43:37 2019] rocminfo D 0 3024 2947
+0x80000000
+[Thu Oct 17 16:43:37 2019] Call Trace:
+[Thu Oct 17 16:43:37 2019] ? __schedule+0x3d9/0x8a0
+[Thu Oct 17 16:43:37 2019] schedule+0x32/0x70
+[Thu Oct 17 16:43:37 2019] schedule_preempt_disabled+0xa/0x10
+[Thu Oct 17 16:43:37 2019] __mutex_lock.isra.9+0x1e3/0x4e0
+[Thu Oct 17 16:43:37 2019] ? __call_srcu+0x264/0x3b0
+[Thu Oct 17 16:43:37 2019] ? process_termination_cpsch+0x24/0x2f0
+[amdgpu]
+[Thu Oct 17 16:43:37 2019] process_termination_cpsch+0x24/0x2f0
+[amdgpu]
+[Thu Oct 17 16:43:37 2019]
+kfd_process_dequeue_from_all_devices+0x42/0x60 [amdgpu]
+[Thu Oct 17 16:43:37 2019] kfd_process_notifier_release+0x1be/0x220
+[amdgpu]
+[Thu Oct 17 16:43:37 2019] __mmu_notifier_release+0x3e/0xc0
+[Thu Oct 17 16:43:37 2019] exit_mmap+0x160/0x1a0
+[Thu Oct 17 16:43:37 2019] ? __handle_mm_fault+0xba3/0x1200
+[Thu Oct 17 16:43:37 2019] ? exit_robust_list+0x5a/0x110
+[Thu Oct 17 16:43:37 2019] mmput+0x4a/0x120
+[Thu Oct 17 16:43:37 2019] do_exit+0x284/0xb20
+[Thu Oct 17 16:43:37 2019] ? handle_mm_fault+0xfa/0x200
+[Thu Oct 17 16:43:37 2019] do_group_exit+0x3a/0xa0
+[Thu Oct 17 16:43:37 2019] __x64_sys_exit_group+0x14/0x20
+[Thu Oct 17 16:43:37 2019] do_syscall_64+0x4f/0x100
+[Thu Oct 17 16:43:37 2019] entry_SYSCALL_64_after_hwframe+0x44/0xa9
+
+Change-Id: Iecaa52a3fa406a8b8f219ae800993f42678ceddd
+Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Philip Yang <Philip.Yang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 5 --
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 47 +++++++++++++++++--
+ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 1 +
+ 3 files changed, 43 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index ee9b9a6968bd..eb5eeba8792d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -744,9 +744,6 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+ return 0;
+ kgd2kfd_suspend(kfd);
+
+- /* hold dqm->lock to prevent further execution*/
+- dqm_lock(kfd->dqm);
+-
+ kfd_signal_reset_event(kfd);
+ return 0;
+ }
+@@ -767,8 +764,6 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
+ if (!kfd->init_complete)
+ return 0;
+
+- dqm_unlock(kfd->dqm);
+-
+ ret = kfd_resume(kfd);
+ if (ret)
+ return ret;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 0b63740b4c63..2f0aeb60fe40 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -369,6 +369,10 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm,
+ mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
+ &q->gart_mqd_addr, &q->properties);
+ if (q->properties.is_active) {
++ if (!dqm->sched_running) {
++ WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
++ goto add_queue_to_list;
++ }
+
+ if (WARN(q->process->mm != current->mm,
+ "should only run in user thread"))
+@@ -380,6 +384,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm,
+ goto out_free_mqd;
+ }
+
++add_queue_to_list:
+ list_add(&q->list, &qpd->queues_list);
+ qpd->queue_count++;
+ if (q->properties.is_active)
+@@ -487,6 +492,11 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
+
+ deallocate_doorbell(qpd, q);
+
++ if (!dqm->sched_running) {
++ WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
++ return 0;
++ }
++
+ retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+ KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
+ KFD_UNMAP_LATENCY_MS,
+@@ -568,6 +578,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
+ (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
+ q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+ q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
++
++ if (!dqm->sched_running) {
++ WARN_ONCE(1, "Update non-HWS queue while stopped\n");
++ goto out_unlock;
++ }
++
+ retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+ KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
+ KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
+@@ -719,6 +735,11 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+ q->properties.type)];
+ q->properties.is_active = false;
++ dqm->queue_count--;
++
++ if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
++ continue;
++
+ retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+ KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
+ KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
+@@ -727,7 +748,6 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ * maintain a consistent eviction state
+ */
+ ret = retval;
+- dqm->queue_count--;
+ if (q->properties.is_gws) {
+ dqm->gws_queue_count--;
+ qpd->mapped_gws_queue = false;
+@@ -837,6 +857,11 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+ q->properties.type)];
+ q->properties.is_active = true;
++ dqm->queue_count++;
++
++ if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
++ continue;
++
+ retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
+ q->queue, &q->properties, mm);
+ if (retval && !ret)
+@@ -844,7 +869,6 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ * maintain a consistent eviction state
+ */
+ ret = retval;
+- dqm->queue_count++;
+ if (q->properties.is_gws) {
+ dqm->gws_queue_count++;
+ qpd->mapped_gws_queue = true;
+@@ -1042,7 +1066,8 @@ static int start_nocpsch(struct device_queue_manager *dqm)
+
+ if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
+ return pm_init(&dqm->packets, dqm);
+-
++ dqm->sched_running = true;
++
+ return 0;
+ }
+
+@@ -1050,7 +1075,8 @@ static int stop_nocpsch(struct device_queue_manager *dqm)
+ {
+ if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
+ pm_uninit(&dqm->packets);
+-
++ dqm->sched_running = false;
++
+ return 0;
+ }
+
+@@ -1206,6 +1232,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
+ dqm_lock(dqm);
+ /* clear hang status when driver try to start the hw scheduler */
+ dqm->is_hws_hang = false;
++ dqm->sched_running = true;
+ execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+ USE_DEFAULT_GRACE_PERIOD);
+ dqm_unlock(dqm);
+@@ -1223,6 +1250,7 @@ static int stop_cpsch(struct device_queue_manager *dqm)
+ dqm_lock(dqm);
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
+ USE_DEFAULT_GRACE_PERIOD);
++ dqm->sched_running = false;
+ dqm_unlock(dqm);
+
+ kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
+@@ -1413,9 +1441,10 @@ static int map_queues_cpsch(struct device_queue_manager *dqm)
+ {
+ int retval;
+
++ if (!dqm->sched_running)
++ return 0;
+ if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
+ return 0;
+-
+ if (dqm->active_runlist)
+ return 0;
+
+@@ -1438,6 +1467,8 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm,
+ {
+ int retval = 0;
+
++ if (!dqm->sched_running)
++ return 0;
+ if (dqm->is_hws_hang)
+ return -EIO;
+ if (!dqm->active_runlist)
+@@ -2375,6 +2406,12 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
+ int pipe, queue;
+ int r = 0;
+
++ if (!dqm->sched_running) {
++ seq_printf(m, " Device is stopped\n");
++
++ return 0;
++ }
++
+ r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
+ KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, &dump, &n_regs);
+ if (!r) {
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+index 48e3b89e27c3..a5e045206fb7 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+@@ -205,6 +205,7 @@ struct device_queue_manager {
+ struct work_struct hw_exception_work;
+ struct kfd_mem_obj hiq_sdma_mqd;
+ uint32_t wait_times;
++ bool sched_running;
+ };
+
+ void device_queue_manager_init_cik(
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4272-drm-amdgpu-refine-reboot-debugfs-operation-in-ras-ca.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4272-drm-amdgpu-refine-reboot-debugfs-operation-in-ras-ca.patch
new file mode 100644
index 00000000..e39a8cd2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4272-drm-amdgpu-refine-reboot-debugfs-operation-in-ras-ca.patch
@@ -0,0 +1,85 @@
+From 9b2167f3c47600d84667fb2ee5676035826d288a Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Mon, 21 Oct 2019 16:56:00 +0800
+Subject: [PATCH 4272/4736] drm/amdgpu: refine reboot debugfs operation in ras
+ case (v3)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Ras reboot debugfs node allows user one easy control to avoid
+gpu recovery hang problem and directly reboot system per card
+basis, after ras uncorrectable error happens. However, it is
+one common entry, which should get rid of ras_ctrl node and
+remove ip dependence when inputting by user. So add one new
+auto_reboot node in ras debugfs dir to achieve this.
+
+v2: in commit mssage, add justification why ras reboot debugfs
+node is needed.
+v3: use debugfs_create_bool to create debugfs file for boolean value
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 1ca613014126..5b532cd254cc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -151,8 +151,6 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ op = 1;
+ else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
+ op = 2;
+- else if (sscanf(str, "reboot %32s", block_name) == 1)
+- op = 3;
+ else if (str[0] && str[1] && str[2] && str[3])
+ /* ascii string, but commands are not matched. */
+ return -EINVAL;
+@@ -216,12 +214,11 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+ * value to the address.
+ *
+ * Second member: struct ras_debug_if::op.
+- * It has four kinds of operations.
++ * It has three kinds of operations.
+ *
+ * - 0: disable RAS on the block. Take ::head as its data.
+ * - 1: enable RAS on the block. Take ::head as its data.
+ * - 2: inject errors on the block. Take ::inject as its data.
+- * - 3: reboot on unrecoverable error
+ *
+ * How to use the interface?
+ * programs:
+@@ -303,9 +300,6 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ /* data.inject.address is offset instead of absolute gpu address */
+ ret = amdgpu_ras_error_inject(adev, &data.inject);
+ break;
+- case 3:
+- amdgpu_ras_get_context(adev)->reboot = true;
+- break;
+ default:
+ ret = -EINVAL;
+ break;
+@@ -1035,6 +1029,17 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
+ adev, &amdgpu_ras_debugfs_ctrl_ops);
+ debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
+ adev, &amdgpu_ras_debugfs_eeprom_ops);
++
++ /*
++ * After one uncorrectable error happens, usually GPU recovery will
++ * be scheduled. But due to the known problem in GPU recovery failing
++ * to bring GPU back, below interface provides one direct way to
++ * user to reboot system automatically in such case within
++ * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
++ * will never be called.
++ */
++ debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir,
++ &con->reboot);
+ }
+
+ void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4273-drm-amdgpu-define-macros-for-retire-page-reservation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4273-drm-amdgpu-define-macros-for-retire-page-reservation.patch
new file mode 100644
index 00000000..13606bac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4273-drm-amdgpu-define-macros-for-retire-page-reservation.patch
@@ -0,0 +1,69 @@
+From 1634c0392f40aaa2207a17188be18362f9e07e3b Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Tue, 22 Oct 2019 11:39:25 +0800
+Subject: [PATCH 4273/4736] drm/amdgpu: define macros for retire page
+ reservation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Easy for maintainance.
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 +++++++++++------
+ 1 file changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 5b532cd254cc..ebc3e15eca8b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -66,6 +66,11 @@ const char *ras_block_string[] = {
+ /* inject address is 52 bits */
+ #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
+
++enum amdgpu_ras_retire_page_reservation {
++ AMDGPU_RAS_RETIRE_PAGE_RESERVED,
++ AMDGPU_RAS_RETIRE_PAGE_PENDING,
++ AMDGPU_RAS_RETIRE_PAGE_FAULT,
++};
+
+ atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
+
+@@ -807,11 +812,11 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
+ static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
+ {
+ switch (flags) {
+- case 0:
++ case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
+ return "R";
+- case 1:
++ case AMDGPU_RAS_RETIRE_PAGE_PENDING:
+ return "P";
+- case 2:
++ case AMDGPU_RAS_RETIRE_PAGE_FAULT:
+ default:
+ return "F";
+ };
+@@ -1292,13 +1297,13 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
+ (*bps)[i] = (struct ras_badpage){
+ .bp = data->bps[i].retired_page,
+ .size = AMDGPU_GPU_PAGE_SIZE,
+- .flags = 0,
++ .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
+ };
+
+ if (data->last_reserved <= i)
+- (*bps)[i].flags = 1;
++ (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
+ else if (data->bps_bo[i] == NULL)
+- (*bps)[i].flags = 2;
++ (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
+ }
+
+ *count = data->count;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4274-drm-amdgpu-Fix-SDMA-hang-when-performing-VKexample-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4274-drm-amdgpu-Fix-SDMA-hang-when-performing-VKexample-t.patch
new file mode 100644
index 00000000..579bb56a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4274-drm-amdgpu-Fix-SDMA-hang-when-performing-VKexample-t.patch
@@ -0,0 +1,30 @@
+From 7db3a1e3e1aaa56d8024966c09d2b5480de8703e Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Wed, 23 Oct 2019 13:54:32 +0800
+Subject: [PATCH 4274/4736] drm/amdgpu: Fix SDMA hang when performing VKexample
+ test
+
+VKexample test hang during Occlusion/SDMA/Varia runs.
+Clear XNACK_WATERMK in reg SDMA0_UTCL1_WATERMK to fix this issue.
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 78e21c12c17a..2653d3c6ddd3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -251,6 +251,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
+ };
+
+ static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4275-drm-amdgpu-sdma5-do-not-execute-0-sized-IBs-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4275-drm-amdgpu-sdma5-do-not-execute-0-sized-IBs-v2.patch
new file mode 100644
index 00000000..dcff327b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4275-drm-amdgpu-sdma5-do-not-execute-0-sized-IBs-v2.patch
@@ -0,0 +1,34 @@
+From 99c7a912113644a9ab79ca59b5964473930f962d Mon Sep 17 00:00:00 2001
+From: "Pelloux-prayer, Pierre-eric" <Pierre-eric.Pelloux-prayer@amd.com>
+Date: Tue, 22 Oct 2019 19:22:11 +0200
+Subject: [PATCH 4275/4736] drm/amdgpu/sdma5: do not execute 0-sized IBs (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.
+
+v2: insert a NOP instead of skipping all 0-sized IBs to avoid breaking older hw
+
+Change-Id: I5df87b3e4eb920c645307425f7b72c430704939a
+Signed-off-by: Pelloux-prayer, Pierre-eric <Pierre-eric.Pelloux-prayer@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 6a73e8d95f0a..3b00bce14cfb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -309,6 +309,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+
+ job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
+ job->vm_needs_flush = true;
++ job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
+ amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+ r = amdgpu_job_submit(job, &adev->mman.entity,
+ AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4276-drm-amdgpu-remove-unused-parameter-in-amdgpu_gfx_kiq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4276-drm-amdgpu-remove-unused-parameter-in-amdgpu_gfx_kiq.patch
new file mode 100644
index 00000000..68656313
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4276-drm-amdgpu-remove-unused-parameter-in-amdgpu_gfx_kiq.patch
@@ -0,0 +1,89 @@
+From a74bcb4a1196e59afac59177e6d7982307c552dc Mon Sep 17 00:00:00 2001
+From: Nirmoy Das <nirmoy.das@amd.com>
+Date: Wed, 23 Oct 2019 16:33:52 +0200
+Subject: [PATCH 4276/4736] drm/amdgpu: remove unused parameter in
+ amdgpu_gfx_kiq_free_ring
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
+ 5 files changed, 5 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index 56b31668d551..a492174ef29b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -319,8 +319,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
+ return r;
+ }
+
+-void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
+- struct amdgpu_irq_src *irq)
++void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
+ {
+ amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
+ amdgpu_ring_fini(ring);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 35eff9e6ce16..459aa9059542 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -330,8 +330,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring,
+ struct amdgpu_irq_src *irq);
+
+-void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
+- struct amdgpu_irq_src *irq);
++void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
+
+ void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
+ int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index f93ac8f44a58..38dd30d350a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1439,7 +1439,7 @@ static int gfx_v10_0_sw_fini(void *handle)
+ amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
+
+ amdgpu_gfx_mqd_sw_fini(adev);
+- amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
++ amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
+ amdgpu_gfx_kiq_fini(adev);
+
+ gfx_v10_0_pfp_fini(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 614b8226b9eb..c0bcf5d91f1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -2099,7 +2099,7 @@ static int gfx_v8_0_sw_fini(void *handle)
+ amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
+
+ amdgpu_gfx_mqd_sw_fini(adev);
+- amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
++ amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
+ amdgpu_gfx_kiq_fini(adev);
+
+ gfx_v8_0_mec_fini(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 5e7a01c322ea..2f03bf533d41 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2149,7 +2149,7 @@ static int gfx_v9_0_sw_fini(void *handle)
+ amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
+
+ amdgpu_gfx_mqd_sw_fini(adev);
+- amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
++ amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
+ amdgpu_gfx_kiq_fini(adev);
+
+ gfx_v9_0_mec_fini(adev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4277-drm-amdgpu-Add-DC-feature-mask-to-disable-fractional.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4277-drm-amdgpu-Add-DC-feature-mask-to-disable-fractional.patch
new file mode 100644
index 00000000..b4d6c74c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4277-drm-amdgpu-Add-DC-feature-mask-to-disable-fractional.patch
@@ -0,0 +1,79 @@
+From e6636a3d42b3291d037aa242bbe59cd040ea5caf Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Mon, 21 Oct 2019 14:58:47 -0400
+Subject: [PATCH 4277/4736] drm/amdgpu: Add DC feature mask to disable
+ fractional pwm
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[Why]
+
+Some LED panel drivers might not like fractional PWM. In such cases,
+backlight flickering may be observed.
+
+[How]
+
+Add a DC feature mask to disable fractional PWM, and associate it with
+the preexisting dc_config flag.
+
+The flag is only plumbed through the dmcu firmware, so plumb it through
+the driver path as well.
+
+To disable, add the following to the linux cmdline:
+amdgpu.dcfeaturemask=0x4
+
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Anthony Koo <anthony.koo@amd.com>
+Tested-by: Lukáš Krejčí <lskrejci@gmail.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 4 ++++
+ drivers/gpu/drm/amd/include/amd_shared.h | 1 +
+ 3 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ff89ca40f82c..5a20ce0541c6 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -725,6 +725,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
+ init_data.flags.multi_mon_pp_mclk_switch = true;
+
++ if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
++ init_data.flags.disable_fractional_pwm = true;
++
+ init_data.flags.power_down_display_on_boot = true;
+
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+index 4a22b50bd38a..2946998fe6a4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+@@ -402,6 +402,10 @@ static bool dce_abm_init_backlight(struct abm *abm)
+ /* Enable the backlight output */
+ REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
+
++ /* Disable fractional pwm if configured */
++ REG_UPDATE(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN,
++ abm->ctx->dc->config.disable_fractional_pwm ? 0 : 1);
++
+ /* Unlock group 2 backlight registers */
+ REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
+ BL_PWM_GRP1_REG_LOCK, 0);
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index 8340ec0ab792..dc7eb28f0296 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -143,6 +143,7 @@ enum PP_FEATURE_MASK {
+ enum DC_FEATURE_MASK {
+ DC_FBC_MASK = 0x1,
+ DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
++ DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
+ DC_PSR_MASK = 0x8,
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4278-drm-amd-powerplay-Add-interface-for-I2C-transactions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4278-drm-amd-powerplay-Add-interface-for-I2C-transactions.patch
new file mode 100644
index 00000000..ba17c20f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4278-drm-amd-powerplay-Add-interface-for-I2C-transactions.patch
@@ -0,0 +1,53 @@
+From e1a4c575f55bd3eccc3d1a079b47fe553008e0fd Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 11 Oct 2019 13:48:24 -0400
+Subject: [PATCH 4278/4736] drm/amd/powerplay: Add interface for I2C
+ transactions to SMU.
+
+Will be used by Arcturus support for RAS page retirement.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 402a021f237b..8120e7587585 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -393,6 +393,8 @@ struct smu_context
+
+ };
+
++struct i2c_adapter;
++
+ struct pptable_funcs {
+ int (*alloc_dpm_context)(struct smu_context *smu);
+ int (*store_powerplay_table)(struct smu_context *smu);
+@@ -469,6 +471,8 @@ struct pptable_funcs {
+ uint32_t dpm_level, uint32_t *freq);
+ int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
++ int (*i2c_eeprom_init)(struct i2c_adapter *control);
++ void (*i2c_eeprom_fini)(struct i2c_adapter *control);
+ int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
+ int (*init_microcode)(struct smu_context *smu);
+ int (*load_microcode)(struct smu_context *smu);
+@@ -552,6 +556,11 @@ int smu_check_fw_status(struct smu_context *smu);
+
+ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
+
++#define smu_i2c_eeprom_init(smu, control) \
++ ((smu)->ppt_funcs->i2c_eeprom_init ? (smu)->ppt_funcs->i2c_eeprom_init((control)) : -EINVAL)
++#define smu_i2c_eeprom_fini(smu, control) \
++ ((smu)->ppt_funcs->i2c_eeprom_fini ? (smu)->ppt_funcs->i2c_eeprom_fini((control)) : -EINVAL)
++
+ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+
+ int smu_get_power_limit(struct smu_context *smu,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4279-drm-amd-powerplay-Add-EEPROM-I2C-read-write-support-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4279-drm-amd-powerplay-Add-EEPROM-I2C-read-write-support-.patch
new file mode 100644
index 00000000..44cb5bf3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4279-drm-amd-powerplay-Add-EEPROM-I2C-read-write-support-.patch
@@ -0,0 +1,288 @@
+From 83aaefe84218f05585228130616871b50c75aabf Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 8 Oct 2019 16:27:47 -0400
+Subject: [PATCH 4279/4736] drm/amd/powerplay: Add EEPROM I2C read/write
+ support to Arcturus.
+
+The communication is done through SMU table and hence the code
+is in powerplay.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 229 +++++++++++++++++++
+ 1 file changed, 229 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index ffefa89c295b..fa573c59e813 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -37,6 +37,11 @@
+ #include "smu_v11_0_pptable.h"
+ #include "arcturus_ppsmc.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
++#include <linux/i2c.h>
++#include <linux/pci.h>
++#include "amdgpu_ras.h"
++
++#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
+
+ #define CTF_OFFSET_EDGE 5
+ #define CTF_OFFSET_HOTSPOT 5
+@@ -172,6 +177,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
+ TAB_MAP(SMU_METRICS),
+ TAB_MAP(DRIVER_SMU_CONFIG),
+ TAB_MAP(OVERDRIVE),
++ TAB_MAP(I2C_COMMANDS),
+ };
+
+ static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+@@ -294,6 +300,9 @@ static int arcturus_tables_init(struct smu_context *smu, struct smu_table *table
+ SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+
++ SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
++ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++
+ smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+ if (!smu_table->metrics_table)
+ return -ENOMEM;
+@@ -1925,6 +1934,224 @@ static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ return ret;
+ }
+
++
++static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t *req, bool write,
++ uint8_t address, uint32_t numbytes,
++ uint8_t *data)
++{
++ int i;
++
++ BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
++
++ req->I2CcontrollerPort = 0;
++ req->I2CSpeed = 2;
++ req->SlaveAddress = address;
++ req->NumCmds = numbytes;
++
++ for (i = 0; i < numbytes; i++) {
++ SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
++
++ /* First 2 bytes are always write for lower 2b EEPROM address */
++ if (i < 2)
++ cmd->Cmd = 1;
++ else
++ cmd->Cmd = write;
++
++
++ /* Add RESTART for read after address filled */
++ cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
++
++ /* Add STOP in the end */
++ cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
++
++ /* Fill with data regardless if read or write to simplify code */
++ cmd->RegisterAddr = data[i];
++ }
++}
++
++static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
++ uint8_t address,
++ uint8_t *data,
++ uint32_t numbytes)
++{
++ uint32_t i, ret = 0;
++ SwI2cRequest_t req;
++ struct amdgpu_device *adev = to_amdgpu_device(control);
++ struct smu_table_context *smu_table = &adev->smu.smu_table;
++ struct smu_table *table = &smu_table->tables[SMU_TABLE_I2C_COMMANDS];
++
++ memset(&req, 0, sizeof(req));
++ arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
++
++ mutex_lock(&adev->smu.mutex);
++ /* Now read data starting with that address */
++ ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
++ true);
++ mutex_unlock(&adev->smu.mutex);
++
++ if (!ret) {
++ SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
++
++ /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
++ for (i = 0; i < numbytes; i++)
++ data[i] = res->SwI2cCmds[i].Data;
++
++ pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
++ (uint16_t)address, numbytes);
++
++ print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
++ 8, 1, data, numbytes, false);
++ } else
++ pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
++
++ return ret;
++}
++
++static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
++ uint8_t address,
++ uint8_t *data,
++ uint32_t numbytes)
++{
++ uint32_t ret;
++ SwI2cRequest_t req;
++ struct amdgpu_device *adev = to_amdgpu_device(control);
++
++ memset(&req, 0, sizeof(req));
++ arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
++
++ mutex_lock(&adev->smu.mutex);
++ ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
++ mutex_unlock(&adev->smu.mutex);
++
++ if (!ret) {
++ pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
++ (uint16_t)address, numbytes);
++
++ print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
++ 8, 1, data, numbytes, false);
++ /*
++ * According to EEPROM spec there is a MAX of 10 ms required for
++ * EEPROM to flush internal RX buffer after STOP was issued at the
++ * end of write transaction. During this time the EEPROM will not be
++ * responsive to any more commands - so wait a bit more.
++ */
++ msleep(10);
++
++ } else
++ pr_err("arcturus_i2c_write- error occurred :%x", ret);
++
++ return ret;
++}
++
++static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
++ struct i2c_msg *msgs, int num)
++{
++ uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
++ uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
++
++ for (i = 0; i < num; i++) {
++ /*
++ * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
++ * once and hence the data needs to be spliced into chunks and sent each
++ * chunk separately
++ */
++ data_size = msgs[i].len - 2;
++ data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
++ next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
++ data_ptr = msgs[i].buf + 2;
++
++ for (j = 0; j < data_size / data_chunk_size; j++) {
++ /* Insert the EEPROM dest addess, bits 0-15 */
++ data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
++ data_chunk[1] = (next_eeprom_addr & 0xff);
++
++ if (msgs[i].flags & I2C_M_RD) {
++ ret = arcturus_i2c_eeprom_read_data(i2c_adap,
++ (uint8_t)msgs[i].addr,
++ data_chunk, MAX_SW_I2C_COMMANDS);
++
++ memcpy(data_ptr, data_chunk + 2, data_chunk_size);
++ } else {
++
++ memcpy(data_chunk + 2, data_ptr, data_chunk_size);
++
++ ret = arcturus_i2c_eeprom_write_data(i2c_adap,
++ (uint8_t)msgs[i].addr,
++ data_chunk, MAX_SW_I2C_COMMANDS);
++ }
++
++ if (ret) {
++ num = -EIO;
++ goto fail;
++ }
++
++ next_eeprom_addr += data_chunk_size;
++ data_ptr += data_chunk_size;
++ }
++
++ if (data_size % data_chunk_size) {
++ data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
++ data_chunk[1] = (next_eeprom_addr & 0xff);
++
++ if (msgs[i].flags & I2C_M_RD) {
++ ret = arcturus_i2c_eeprom_read_data(i2c_adap,
++ (uint8_t)msgs[i].addr,
++ data_chunk, (data_size % data_chunk_size) + 2);
++
++ memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
++ } else {
++ memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
++
++ ret = arcturus_i2c_eeprom_write_data(i2c_adap,
++ (uint8_t)msgs[i].addr,
++ data_chunk, (data_size % data_chunk_size) + 2);
++ }
++
++ if (ret) {
++ num = -EIO;
++ goto fail;
++ }
++ }
++ }
++
++fail:
++ return num;
++}
++
++static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
++{
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++
++static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
++ .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
++ .functionality = arcturus_i2c_eeprom_i2c_func,
++};
++
++int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
++{
++ struct amdgpu_device *adev = to_amdgpu_device(control);
++ int res;
++
++ control->owner = THIS_MODULE;
++ control->class = I2C_CLASS_SPD;
++ control->dev.parent = &adev->pdev->dev;
++ control->algo = &arcturus_i2c_eeprom_i2c_algo;
++ snprintf(control->name, sizeof(control->name), "RAS EEPROM");
++
++ res = i2c_add_adapter(control);
++ if (res)
++ DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
++
++ return res;
++}
++
++void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
++{
++ i2c_del_adapter(control);
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+ /* translate smu index into arcturus specific index */
+ .get_smu_msg_index = arcturus_get_smu_msg_index,
+@@ -1964,6 +2191,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ .get_power_limit = arcturus_get_power_limit,
+ .is_dpm_running = arcturus_is_dpm_running,
+ .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
++ .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
++ .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
+ .init_microcode = smu_v11_0_init_microcode,
+ .load_microcode = smu_v11_0_load_microcode,
+ .init_smc_tables = smu_v11_0_init_smc_tables,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4280-drm-amdgpu-Use-ARCTURUS-in-RAS-EEPROM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4280-drm-amdgpu-Use-ARCTURUS-in-RAS-EEPROM.patch
new file mode 100644
index 00000000..7ba171fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4280-drm-amdgpu-Use-ARCTURUS-in-RAS-EEPROM.patch
@@ -0,0 +1,52 @@
+From 31aed3aa3a2b5a604e6282f5c1dadf1e6e56f8b9 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 11 Oct 2019 15:28:19 -0400
+Subject: [PATCH 4280/4736] drm/amdgpu: Use ARCTURUS in RAS EEPROM.
+
+Add Arcturus EEPROM/I2C support in generic EEPROM code.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 20af0a17d00b..7de16c0c2f20 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -216,6 +216,10 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
+ break;
+
++ case CHIP_ARCTURUS:
++ ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
++ break;
++
+ default:
+ return 0;
+ }
+@@ -260,6 +264,9 @@ void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
+ case CHIP_VEGA20:
+ smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
+ break;
++ case CHIP_ARCTURUS:
++ smu_i2c_eeprom_fini(&adev->smu, &control->eeprom_accessor);
++ break;
+
+ default:
+ return;
+@@ -364,7 +371,7 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ struct eeprom_table_record *record;
+ struct amdgpu_device *adev = to_amdgpu_device(control);
+
+- if (adev->asic_type != CHIP_VEGA20)
++ if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
+ return 0;
+
+ buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4281-drm-amdgpu-Move-amdgpu_ras_recovery_init-to-after-SM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4281-drm-amdgpu-Move-amdgpu_ras_recovery_init-to-after-SM.patch
new file mode 100644
index 00000000..7299f949
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4281-drm-amdgpu-Move-amdgpu_ras_recovery_init-to-after-SM.patch
@@ -0,0 +1,68 @@
+From 4247199656c3a7e8b1bed2c1318166bd60636da5 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 18 Oct 2019 16:15:04 -0400
+Subject: [PATCH 4281/4736] drm/amdgpu: Move amdgpu_ras_recovery_init to after
+ SMU ready.
+
+For Arcturus the I2C traffic is done through SMU tables and so
+we must postpone RAS recovery init to after they are ready
+which is in amdgpu_device_ip_hw_init_phase2.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 -----------
+ 2 files changed, 13 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 634b581f96b8..e30e4f8f7df3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1877,6 +1877,19 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
+ if (r)
+ goto init_failed;
+
++ /*
++ * retired pages will be loaded from eeprom and reserved here,
++ * it should be called after amdgpu_device_ip_hw_init_phase2 since
++ * for some ASICs the RAS EEPROM code relies on SMU fully functioning
++ * for I2C communication which only true at this point.
++ * recovery_init may fail, but it can free all resources allocated by
++ * itself and its failure should not stop amdgpu init process.
++ *
++ * Note: theoretically, this should be called before all vram allocations
++ * to protect retired page from abusing
++ */
++ amdgpu_ras_recovery_init(adev);
++
+ if (adev->gmc.xgmi.num_physical_nodes > 1)
+ amdgpu_xgmi_add_device(adev);
+ amdgpu_amdkfd_device_init(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 968595138b32..8bdc1eec496e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2115,17 +2115,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ adev->gmc.visible_vram_size);
+ #endif
+
+- /*
+- * retired pages will be loaded from eeprom and reserved here,
+- * it should be called after ttm init since new bo may be created,
+- * recovery_init may fail, but it can free all resources allocated by
+- * itself and its failure should not stop amdgpu init process.
+- *
+- * Note: theoretically, this should be called before all vram allocations
+- * to protect retired page from abusing
+- */
+- amdgpu_ras_recovery_init(adev);
+-
+ /*
+ *The reserved vram for firmware must be pinned to the specified
+ *place on the VRAM, so reserve it early.
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4282-drm-amdgpu-Allow-reading-more-status-registers-on-si.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4282-drm-amdgpu-Allow-reading-more-status-registers-on-si.patch
new file mode 100644
index 00000000..2b8e4371
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4282-drm-amdgpu-Allow-reading-more-status-registers-on-si.patch
@@ -0,0 +1,119 @@
+From dc7226855bf797ba95a3b5c90bfc06a68b2af5c9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 12 Dec 2019 10:34:08 +0530
+Subject: [PATCH 4282/4736] drm/amdgpu: Allow reading more status registers on
+ si/cik
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Allow userspace to read the same status registers for every family.
+Based on commit c7890fea, added any of these registers if defined in
+the include files of each architecture.
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/cik.c | 19 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/si.c | 11 +++++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
+ 5 files changed, 34 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 699cab407158..131dd2e91bf0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -81,9 +81,10 @@
+ * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
+ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
+ * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
++ * - 3.36.0 - Allow reading more status registers on si/cik
+ */
+ #define KMS_DRIVER_MAJOR 3
+-#define KMS_DRIVER_MINOR 35
++#define KMS_DRIVER_MINOR 36
+ #define KMS_DRIVER_PATCHLEVEL 0
+
+ int amdgpu_vram_limit = 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index e3c524c8926a..cc3d9f91a769 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -965,6 +965,25 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
+
+ static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
+ {mmGRBM_STATUS},
++ {mmGRBM_STATUS2},
++ {mmGRBM_STATUS_SE0},
++ {mmGRBM_STATUS_SE1},
++ {mmGRBM_STATUS_SE2},
++ {mmGRBM_STATUS_SE3},
++ {mmSRBM_STATUS},
++ {mmSRBM_STATUS2},
++ {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
++ {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
++ {mmCP_STAT},
++ {mmCP_STALLED_STAT1},
++ {mmCP_STALLED_STAT2},
++ {mmCP_STALLED_STAT3},
++ {mmCP_CPF_BUSY_STAT},
++ {mmCP_CPF_STALLED_STAT1},
++ {mmCP_CPF_STATUS},
++ {mmCP_CPC_BUSY_STAT},
++ {mmCP_CPC_STALLED_STAT1},
++ {mmCP_CPC_STATUS},
+ {mmGB_ADDR_CONFIG},
+ {mmMC_ARB_RAMCFG},
+ {mmGB_TILE_MODE0},
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 55a6ed09a953..ebbf7712f8c8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -177,6 +177,7 @@ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
+ { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
+diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
+index 0d2533025227..c8d645e45821 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si.c
++++ b/drivers/gpu/drm/amd/amdgpu/si.c
+@@ -974,6 +974,17 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+
+ static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
+ {GRBM_STATUS},
++ {mmGRBM_STATUS2},
++ {mmGRBM_STATUS_SE0},
++ {mmGRBM_STATUS_SE1},
++ {mmSRBM_STATUS},
++ {mmSRBM_STATUS2},
++ {DMA_STATUS_REG + DMA0_REGISTER_OFFSET},
++ {DMA_STATUS_REG + DMA1_REGISTER_OFFSET},
++ {mmCP_STAT},
++ {mmCP_STALLED_STAT1},
++ {mmCP_STALLED_STAT2},
++ {mmCP_STALLED_STAT3},
+ {GB_ADDR_CONFIG},
+ {MC_ARB_RAMCFG},
+ {GB_TILE_MODE0},
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 9457502a9909..d3083bd2c5ae 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -338,6 +338,7 @@ static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
++ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
+ { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4283-drm-amd-powerplay-skip-unsupported-clock-limit-setti.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4283-drm-amd-powerplay-skip-unsupported-clock-limit-setti.patch
new file mode 100644
index 00000000..09178d48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4283-drm-amd-powerplay-skip-unsupported-clock-limit-setti.patch
@@ -0,0 +1,258 @@
+From ea8e41069738393f33d662295b030aebb795cd94 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 22 Oct 2019 21:20:36 +0800
+Subject: [PATCH 4283/4736] drm/amd/powerplay: skip unsupported clock limit
+ settings on Arcturus V2
+
+For Arcturus, clock limit settings on uclk/socclk/fclk domains
+are not supported.
+
+V2: simplify the code to support both SGPU and MGPU cases
+
+Change-Id: I1286289e3770f0421f0d22989437e26d3f7b2ec4
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 13 ++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 142 ++++---------------
+ 2 files changed, 39 insertions(+), 116 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index dd94467a3d5d..07f620938ae4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2828,6 +2828,19 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
+ DRM_ERROR("failed to create device file pp_dpm_sclk\n");
+ return ret;
+ }
++
++ /* Arcturus does not support standalone mclk/socclk/fclk level setting */
++ if (adev->asic_type == CHIP_ARCTURUS) {
++ dev_attr_pp_dpm_mclk.attr.mode &= ~S_IWUGO;
++ dev_attr_pp_dpm_mclk.store = NULL;
++
++ dev_attr_pp_dpm_socclk.attr.mode &= ~S_IWUGO;
++ dev_attr_pp_dpm_socclk.store = NULL;
++
++ dev_attr_pp_dpm_fclk.attr.mode &= ~S_IWUGO;
++ dev_attr_pp_dpm_fclk.store = NULL;
++ }
++
+ ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_dpm_mclk\n");
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index fa573c59e813..48f3ddc065c0 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -37,6 +37,7 @@
+ #include "smu_v11_0_pptable.h"
+ #include "arcturus_ppsmc.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
++#include "amdgpu_xgmi.h"
+ #include <linux/i2c.h>
+ #include <linux/pci.h>
+ #include "amdgpu_ras.h"
+@@ -807,84 +808,13 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
+ break;
+
+ case SMU_MCLK:
+- single_dpm_table = &(dpm_table->mem_table);
+-
+- if (soft_max_level >= single_dpm_table->count) {
+- pr_err("Clock level specified %d is over max allowed %d\n",
+- soft_max_level, single_dpm_table->count - 1);
+- ret = -EINVAL;
+- break;
+- }
+-
+- single_dpm_table->dpm_state.soft_min_level =
+- single_dpm_table->dpm_levels[soft_min_level].value;
+- single_dpm_table->dpm_state.soft_max_level =
+- single_dpm_table->dpm_levels[soft_max_level].value;
+-
+- ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
+- if (ret) {
+- pr_err("Failed to upload boot level to lowest!\n");
+- break;
+- }
+-
+- ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
+- if (ret)
+- pr_err("Failed to upload dpm max level to highest!\n");
+-
+- break;
+-
+ case SMU_SOCCLK:
+- single_dpm_table = &(dpm_table->soc_table);
+-
+- if (soft_max_level >= single_dpm_table->count) {
+- pr_err("Clock level specified %d is over max allowed %d\n",
+- soft_max_level, single_dpm_table->count - 1);
+- ret = -EINVAL;
+- break;
+- }
+-
+- single_dpm_table->dpm_state.soft_min_level =
+- single_dpm_table->dpm_levels[soft_min_level].value;
+- single_dpm_table->dpm_state.soft_max_level =
+- single_dpm_table->dpm_levels[soft_max_level].value;
+-
+- ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
+- if (ret) {
+- pr_err("Failed to upload boot level to lowest!\n");
+- break;
+- }
+-
+- ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
+- if (ret)
+- pr_err("Failed to upload dpm max level to highest!\n");
+-
+- break;
+-
+ case SMU_FCLK:
+- single_dpm_table = &(dpm_table->fclk_table);
+-
+- if (soft_max_level >= single_dpm_table->count) {
+- pr_err("Clock level specified %d is over max allowed %d\n",
+- soft_max_level, single_dpm_table->count - 1);
+- ret = -EINVAL;
+- break;
+- }
+-
+- single_dpm_table->dpm_state.soft_min_level =
+- single_dpm_table->dpm_levels[soft_min_level].value;
+- single_dpm_table->dpm_state.soft_max_level =
+- single_dpm_table->dpm_levels[soft_max_level].value;
+-
+- ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
+- if (ret) {
+- pr_err("Failed to upload boot level to lowest!\n");
+- break;
+- }
+-
+- ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
+- if (ret)
+- pr_err("Failed to upload dpm max level to highest!\n");
+-
++ /*
++ * Should not arrive here since Arcturus does not
++ * support mclk/socclk/fclk softmin/softmax settings
++ */
++ ret = -EINVAL;
+ break;
+
+ default:
+@@ -1200,6 +1130,7 @@ static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ {
+ struct arcturus_dpm_table *dpm_table =
+ (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
++ struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
+ uint32_t soft_level;
+ int ret = 0;
+
+@@ -1213,40 +1144,27 @@ static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ dpm_table->gfx_table.dpm_state.soft_max_level =
+ dpm_table->gfx_table.dpm_levels[soft_level].value;
+
+- /* uclk */
+- if (highest)
+- soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
+- else
+- soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
+-
+- dpm_table->mem_table.dpm_state.soft_min_level =
+- dpm_table->mem_table.dpm_state.soft_max_level =
+- dpm_table->mem_table.dpm_levels[soft_level].value;
+-
+- /* socclk */
+- if (highest)
+- soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
+- else
+- soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
+-
+- dpm_table->soc_table.dpm_state.soft_min_level =
+- dpm_table->soc_table.dpm_state.soft_max_level =
+- dpm_table->soc_table.dpm_levels[soft_level].value;
+-
+- ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
++ ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
+ if (ret) {
+ pr_err("Failed to upload boot level to %s!\n",
+ highest ? "highest" : "lowest");
+ return ret;
+ }
+
+- ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
++ ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
+ if (ret) {
+ pr_err("Failed to upload dpm max level to %s!\n!",
+ highest ? "highest" : "lowest");
+ return ret;
+ }
+
++ if (hive)
++ /*
++ * Force XGMI Pstate to highest or lowest
++ * TODO: revise this when xgmi dpm is functional
++ */
++ ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
++
+ return ret;
+ }
+
+@@ -1254,6 +1172,7 @@ static int arcturus_unforce_dpm_levels(struct smu_context *smu)
+ {
+ struct arcturus_dpm_table *dpm_table =
+ (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
++ struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
+ uint32_t soft_min_level, soft_max_level;
+ int ret = 0;
+
+@@ -1265,34 +1184,25 @@ static int arcturus_unforce_dpm_levels(struct smu_context *smu)
+ dpm_table->gfx_table.dpm_state.soft_max_level =
+ dpm_table->gfx_table.dpm_levels[soft_max_level].value;
+
+- /* uclk */
+- soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
+- soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
+- dpm_table->mem_table.dpm_state.soft_min_level =
+- dpm_table->gfx_table.dpm_levels[soft_min_level].value;
+- dpm_table->mem_table.dpm_state.soft_max_level =
+- dpm_table->gfx_table.dpm_levels[soft_max_level].value;
+-
+- /* socclk */
+- soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
+- soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
+- dpm_table->soc_table.dpm_state.soft_min_level =
+- dpm_table->soc_table.dpm_levels[soft_min_level].value;
+- dpm_table->soc_table.dpm_state.soft_max_level =
+- dpm_table->soc_table.dpm_levels[soft_max_level].value;
+-
+- ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
++ ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
+ if (ret) {
+ pr_err("Failed to upload DPM Bootup Levels!");
+ return ret;
+ }
+
+- ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
++ ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
+ if (ret) {
+ pr_err("Failed to upload DPM Max Levels!");
+ return ret;
+ }
+
++ if (hive)
++ /*
++ * Reset XGMI Pstate back to default
++ * TODO: revise this when xgmi dpm is functional
++ */
++ ret = smu_v11_0_set_xgmi_pstate(smu, 0);
++
+ return ret;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4284-drm-amd-powerplay-correct-current-clock-level-label-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4284-drm-amd-powerplay-correct-current-clock-level-label-.patch
new file mode 100644
index 00000000..9951b6ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4284-drm-amd-powerplay-correct-current-clock-level-label-.patch
@@ -0,0 +1,82 @@
+From e8b3dcadd4f4ad12369d5e4699d028504609c2e0 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 24 Oct 2019 10:01:19 +0800
+Subject: [PATCH 4284/4736] drm/amd/powerplay: correct current clock level
+ label for Arcturus
+
+For dpm disabled case, it's assumed the only one support clock
+level is always current clock level.
+
+Change-Id: I5cc2b7e82af888dc5e8268597ee761e9e1a26855
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 24 +++++++++++++-------
+ 1 file changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 48f3ddc065c0..93633f76989e 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -628,12 +628,17 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ return ret;
+ }
+
++ /*
++ * For DPM disabled case, there will be only one clock level.
++ * And it's safe to assume that is always the current clock.
++ */
+ for (i = 0; i < clocks.num_levels; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n", i,
+ clocks.data[i].clocks_in_khz / 1000,
+- arcturus_freqs_in_same_level(
++ (clocks.num_levels == 1) ? "*" :
++ (arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+- now / 100) ? "*" : "");
++ now / 100) ? "*" : ""));
+ break;
+
+ case SMU_MCLK:
+@@ -653,9 +658,10 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ for (i = 0; i < clocks.num_levels; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i, clocks.data[i].clocks_in_khz / 1000,
+- arcturus_freqs_in_same_level(
++ (clocks.num_levels == 1) ? "*" :
++ (arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+- now / 100) ? "*" : "");
++ now / 100) ? "*" : ""));
+ break;
+
+ case SMU_SOCCLK:
+@@ -675,9 +681,10 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ for (i = 0; i < clocks.num_levels; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i, clocks.data[i].clocks_in_khz / 1000,
+- arcturus_freqs_in_same_level(
++ (clocks.num_levels == 1) ? "*" :
++ (arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+- now / 100) ? "*" : "");
++ now / 100) ? "*" : ""));
+ break;
+
+ case SMU_FCLK:
+@@ -697,9 +704,10 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ for (i = 0; i < single_dpm_table->count; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i, single_dpm_table->dpm_levels[i].value,
+- arcturus_freqs_in_same_level(
++ (clocks.num_levels == 1) ? "*" :
++ (arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+- now / 100) ? "*" : "");
++ now / 100) ? "*" : ""));
+ break;
+
+ default:
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4285-drm-amdgpu-call-amdgpu_vm_prt_fini-before-deleting-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4285-drm-amdgpu-call-amdgpu_vm_prt_fini-before-deleting-t.patch
new file mode 100644
index 00000000..62b17d9b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4285-drm-amdgpu-call-amdgpu_vm_prt_fini-before-deleting-t.patch
@@ -0,0 +1,60 @@
+From 3a6825e8f5dc6c82061e2fc0a4eed682003797e6 Mon Sep 17 00:00:00 2001
+From: "Pelloux-prayer, Pierre-eric" <Pierre-eric.Pelloux-prayer@amd.com>
+Date: Wed, 23 Oct 2019 12:02:45 +0000
+Subject: [PATCH 4285/4736] drm/amdgpu: call amdgpu_vm_prt_fini before deleting
+ the root PD
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+amdgpu_vm_prt_fini uses "vm->root.base.bo" so it must still be valid when
+we call it.
+
+Fixes: b65709a92156 ("drm/amdgpu: reserve the root PD while freeing PASIDs")
+Change-Id: Idd5fef2b9344ab6129a6dcdcce2d0a568ed4dde0
+Signed-off-by: Pelloux-prayer, Pierre-eric <Pierre-eric.Pelloux-prayer@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index c970824b041d..d0604167cd74 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2977,6 +2977,16 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ vm->pasid = 0;
+ }
+
++ list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
++ if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
++ amdgpu_vm_prt_fini(adev, vm);
++ prt_fini_needed = false;
++ }
++
++ list_del(&mapping->list);
++ amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
++ }
++
+ amdgpu_vm_free_pts(adev, vm, NULL);
+ amdgpu_bo_unreserve(root);
+ amdgpu_bo_unref(&root);
+@@ -2996,15 +3006,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ list_del(&mapping->list);
+ kfree(mapping);
+ }
+- list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
+- if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
+- amdgpu_vm_prt_fini(adev, vm);
+- prt_fini_needed = false;
+- }
+-
+- list_del(&mapping->list);
+- amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
+- }
+
+ dma_fence_put(vm->last_update);
+ for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4286-drm-amdgpu-gfx10-update-gfx-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4286-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
new file mode 100644
index 00000000..51f1f5f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4286-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
@@ -0,0 +1,30 @@
+From 750b8d117e88bf57d524ee4b460f63b1836adf01 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 24 Oct 2019 18:03:17 +0800
+Subject: [PATCH 4286/4736] drm/amdgpu/gfx10: update gfx golden settings
+
+update registers: mmCGTT_SPI_CLK_CTRL
+
+Change-Id: Ic64d532c61adfdeb681903f1133d9b353579ac55
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 38dd30d350a3..aea9e8b9b07a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -89,7 +89,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ {
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
+- SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4287-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4287-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..f692264d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4287-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,31 @@
+From 7a16930d26ded51f6ee263a4f73cfd3e11b0fb8b Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 24 Oct 2019 18:04:52 +0800
+Subject: [PATCH 4287/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi14
+
+update registers: mmCGTT_SPI_CLK_CTRL
+
+Change-Id: Ib2539aae1fb0d001278b7f89c90ad6296f9fb85f
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index aea9e8b9b07a..dd879ebca1c1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -136,7 +136,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
+- SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4288-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4288-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..82e9e0c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4288-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,31 @@
+From 50f53882430501e436d0499c322d0d5e6f8b3936 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 24 Oct 2019 18:06:06 +0800
+Subject: [PATCH 4288/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi12
+
+update registers: mmCGTT_SPI_CLK_CTRL
+
+Change-Id: I35fb25be1340d8c062e0e5bfff642009a00d52cf
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index dd879ebca1c1..ef1975a5323a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -175,7 +175,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
+- SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4289-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4289-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
new file mode 100644
index 00000000..71178efc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4289-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
@@ -0,0 +1,43 @@
+From 2d6507e7f7463cc3f1b7736dac45a3a4057a929e Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Fri, 25 Oct 2019 14:26:23 -0400
+Subject: [PATCH 4289/4736] drm/amd/display: setting the DIG_MODE to the
+ correct value.
+
+[Why]
+This patch is for fixing Navi14 HDMI display pink screen issue.
+
+[How]
+Call stream->link->link_enc->funcs->setup twice. This is setting
+the DIG_MODE to the correct value after having been overridden by
+the call to transmitter control.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 84813ef735c1..e87124fe981c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2998,6 +2998,15 @@ void core_link_enable_stream(
+ stream->link->link_enc,
+ pipe_ctx->stream->signal);
+
++ /* This second call is needed to reconfigure the DIG
++ * as a workaround for the incorrect value being applied
++ * from transmitter control.
++ */
++ if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
++ stream->link->link_enc->funcs->setup(
++ stream->link->link_enc,
++ pipe_ctx->stream->signal);
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (pipe_ctx->stream->timing.flags.DSC) {
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4290-drm-amdgpu-powerplay-modify-the-parameters-of-SMU_MS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4290-drm-amdgpu-powerplay-modify-the-parameters-of-SMU_MS.patch
new file mode 100644
index 00000000..3a3cf369
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4290-drm-amdgpu-powerplay-modify-the-parameters-of-SMU_MS.patch
@@ -0,0 +1,30 @@
+From 949a3dda57b99b8fb2ca025e74376802543f3e1d Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Thu, 24 Oct 2019 16:48:40 +0800
+Subject: [PATCH 4290/4736] drm/amdgpu/powerplay: modify the parameters of
+ SMU_MSG_PowerUpVcn to 0
+
+The parameters what SMU_MSG_PowerUpVcn need is 0, not 1
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 45c5f54e60d8..4a9751971a9d 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -282,7 +282,7 @@ static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ if (enable) {
+ /* vcn dpm on is a prerequisite for vcn power gate messages */
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0);
+ if (ret)
+ return ret;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4291-drm-sched-Set-error-to-s_fence-if-HW-job-submission.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4291-drm-sched-Set-error-to-s_fence-if-HW-job-submission.patch
new file mode 100644
index 00000000..92572316
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4291-drm-sched-Set-error-to-s_fence-if-HW-job-submission.patch
@@ -0,0 +1,79 @@
+From a249f6b33e15ee4b699ff10e980ce9de66f7d3e8 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 12 Dec 2019 13:36:40 +0530
+Subject: [PATCH 4291/4736] drm/sched: Set error to s_fence if HW job
+ submission
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Problem:
+When run_job fails and HW fence returned is NULL we still signal
+the s_fence to avoid hangs but the user has no way of knowing if
+the actual HW job was ran and finished.
+
+Fix:
+Allow .run_job implementations to return ERR_PTR in the fence pointer
+returned and then set this error for s_fence->finished fence so whoever
+wait on this fence can inspect the signaled fence for an error.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_main.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index 9f362bb84d48..cef586235eaf 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -481,6 +481,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
+ struct drm_sched_job *s_job, *tmp;
+ uint64_t guilty_context;
+ bool found_guilty = false;
++ struct dma_fence *fence;
+
+ list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
+ struct drm_sched_fence *s_fence = s_job->s_fence;
+@@ -494,7 +495,14 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
+ dma_fence_set_error(&s_fence->finished, -ECANCELED);
+
+ dma_fence_put(s_job->s_fence->parent);
+- s_job->s_fence->parent = sched->ops->run_job(s_job);
++ fence = sched->ops->run_job(s_job);
++
++ if (IS_ERR_OR_NULL(fence)) {
++ s_job->s_fence->parent = NULL;
++ dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
++ } else {
++ s_job->s_fence->parent = fence;
++ }
+ }
+ }
+ EXPORT_SYMBOL(drm_sched_resubmit_jobs);
+@@ -722,7 +730,7 @@ static int drm_sched_main(void *param)
+ fence = sched->ops->run_job(sched_job);
+ drm_sched_fence_scheduled(s_fence);
+
+- if (fence) {
++ if (!IS_ERR_OR_NULL(fence)) {
+ s_fence->parent = dma_fence_get(fence);
+ r = dma_fence_add_callback(fence, &sched_job->cb,
+ drm_sched_process_job);
+@@ -732,8 +740,11 @@ static int drm_sched_main(void *param)
+ DRM_ERROR("fence add callback failed (%d)\n",
+ r);
+ dma_fence_put(fence);
+- } else
++ } else {
++
++ dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+ drm_sched_process_job(NULL, &sched_job->cb);
++ }
+
+ wake_up(&sched->job_scheduled);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4292-drm-amdgpu-If-amdgpu_ib_schedule-fails-return-back-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4292-drm-amdgpu-If-amdgpu_ib_schedule-fails-return-back-t.patch
new file mode 100644
index 00000000..3ef00c6d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4292-drm-amdgpu-If-amdgpu_ib_schedule-fails-return-back-t.patch
@@ -0,0 +1,42 @@
+From 5d97e08483dc2131b8c91b1171edbe40701a6f65 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 24 Oct 2019 15:44:10 -0400
+Subject: [PATCH 4292/4736] drm/amdgpu: If amdgpu_ib_schedule fails return back
+ the error.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use ERR_PTR to return back the error happened during amdgpu_ib_schedule.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+index c043d8f6bb8b..71fd9bb7ead7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -218,7 +218,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
+ struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
+ struct dma_fence *fence = NULL, *finished;
+ struct amdgpu_job *job;
+- int r;
++ int r = 0;
+
+ job = to_amdgpu_job(sched_job);
+ finished = &job->base.s_fence->finished;
+@@ -243,6 +243,8 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
+ job->fence = dma_fence_get(fence);
+
+ amdgpu_job_free_resources(job);
++
++ fence = r ? ERR_PTR(r) : fence;
+ return fence;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4293-drm-amd-display-fix-dcn21-Makefile-for-clang.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4293-drm-amd-display-fix-dcn21-Makefile-for-clang.patch
new file mode 100644
index 00000000..77d796ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4293-drm-amd-display-fix-dcn21-Makefile-for-clang.patch
@@ -0,0 +1,47 @@
+From 903e7f10e44dd02e43a9ff9fcd3f98a934adf422 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 2 Oct 2019 14:01:25 +0200
+Subject: [PATCH 4293/4736] drm/amd/display: fix dcn21 Makefile for clang
+
+Just like all the other variants, this one passes invalid
+compile-time options with clang after the new code got
+merged:
+
+clang: error: unknown argument: '-mpreferred-stack-boundary=4'
+scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.o' failed
+
+Use the same variant that we have for dcn20 to fix compilation.
+
+Fixes: eced51f9babb ("drm/amd/display: Add hubp block for Renoir (v2)")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index b7a9285348fb..4ddd4037c1f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -3,7 +3,17 @@
+
+ DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+
+-CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
++ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
++ cc_stack_align := -mpreferred-stack-boundary=4
++else ifneq ($(call cc-option, -mstack-alignment=16),)
++ cc_stack_align := -mstack-alignment=16
++endif
++
++CFLAGS_dcn21_resource.o := -mhard-float -msse $(cc_stack_align)
++
++ifdef CONFIG_CC_IS_CLANG
++CFLAGS_dcn21_resource.o += -msse2
++endif
+
+ AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4294-drm-amd-display-remove-gcc-warning-Wunused-but-set-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4294-drm-amd-display-remove-gcc-warning-Wunused-but-set-v.patch
new file mode 100644
index 00000000..2c5f9a2b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4294-drm-amd-display-remove-gcc-warning-Wunused-but-set-v.patch
@@ -0,0 +1,56 @@
+From aabeeb1cd6a73dce6930209bfd8db3e27f0013db Mon Sep 17 00:00:00 2001
+From: Chenwandun <chenwandun@huawei.com>
+Date: Sat, 19 Oct 2019 11:23:51 +0800
+Subject: [PATCH 4294/4736] drm/amd/display: remove gcc warning
+ Wunused-but-set-variable
+
+drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: In function dce_aux_configure_timeout:
+drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: warning: variable timeout set but not used [-Wunused-but-set-variable]
+
+Signed-off-by: Chenwandun <chenwandun@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 3c3830f7908f..ca1d076d4184 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -429,7 +429,6 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+ {
+ uint32_t multiplier = 0;
+ uint32_t length = 0;
+- uint32_t timeout = 0;
+ struct ddc *ddc_pin = ddc->ddc_pin;
+ struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+ struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+@@ -443,25 +442,21 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+ length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
+ if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
+ length++;
+- timeout = length * TIME_OUT_MULTIPLIER_8;
+ } else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) {
+ multiplier = 1;
+ length = timeout_in_us/TIME_OUT_MULTIPLIER_16;
+ if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0)
+ length++;
+- timeout = length * TIME_OUT_MULTIPLIER_16;
+ } else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) {
+ multiplier = 2;
+ length = timeout_in_us/TIME_OUT_MULTIPLIER_32;
+ if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0)
+ length++;
+- timeout = length * TIME_OUT_MULTIPLIER_32;
+ } else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) {
+ multiplier = 3;
+ length = timeout_in_us/TIME_OUT_MULTIPLIER_64;
+ if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0)
+ length++;
+- timeout = length * TIME_OUT_MULTIPLIER_64;
+ }
+
+ length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4295-drm-amdgpu-display-fix-mixed-declarations-and-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4295-drm-amdgpu-display-fix-mixed-declarations-and-code.patch
new file mode 100644
index 00000000..93980f7e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4295-drm-amdgpu-display-fix-mixed-declarations-and-code.patch
@@ -0,0 +1,36 @@
+From 7e9737fbdd50afa33a095132729c4a4a4c059b62 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 25 Oct 2019 16:03:17 -0400
+Subject: [PATCH 4295/4736] drm/amdgpu/display: fix mixed declarations and code
+
+Trivial.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index ff32c7380efb..987897748174 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1687,6 +1687,7 @@ static bool construct(
+ struct dc_context *ctx = dc->ctx;
+ struct irq_service_init_data init_data;
+ uint32_t pipe_fuses = read_pipe_fuses(ctx);
++ uint32_t num_pipes;
+
+ ctx->dc_bios->regs = &bios_regs;
+
+@@ -1800,7 +1801,7 @@ static bool construct(
+
+ pool->base.pp_smu = dcn21_pp_smu_create(ctx);
+
+- uint32_t num_pipes = dcn2_1_ip.max_num_dpp;
++ num_pipes = dcn2_1_ip.max_num_dpp;
+
+ for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
+ if (pipe_fuses & 1 << i)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4296-drm-amd-powerplay-Disable-gfx-CGPG-when-suspend-smu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4296-drm-amd-powerplay-Disable-gfx-CGPG-when-suspend-smu.patch
new file mode 100644
index 00000000..8df71bd3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4296-drm-amd-powerplay-Disable-gfx-CGPG-when-suspend-smu.patch
@@ -0,0 +1,39 @@
+From edc76deef950f1305de137efda64eeca6f0ee71a Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Fri, 25 Oct 2019 18:51:23 +0800
+Subject: [PATCH 4296/4736] drm/amd/powerplay: Disable gfx CGPG when suspend
+ smu
+
+if no disable gfx CGPG when suspend smu, enabling gfx CGPG will fail when resume smu.
+
+Platform: Renoir
+dmesg log information:
+
+[ 151.844110 ] amdgpu: [powerplay] SMU is resuming...
+[ 151.844116 ] amdgpu: [powerplay] dpm has been disabled
+[ 151.844604 ] amdgpu: [powerplay] Failed to send message 0x2f,response 0xfffffffb param 0x1
+[ 151.844605 ] amdgpu: [powerplay] SMU is resumed successfully!
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 3ce01e1994fc..cda79f0eb822 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1351,6 +1351,8 @@ static int smu_suspend(void *handle)
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->gfx.rlc.funcs->stop)
+ adev->gfx.rlc.funcs->stop(adev);
++ if (smu->is_apu)
++ smu_set_gfx_cgpg(&adev->smu, false);
+
+ return 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4297-drm-amdgpu-powerplay-vega10-allow-undervolting-in-p7.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4297-drm-amdgpu-powerplay-vega10-allow-undervolting-in-p7.patch
new file mode 100644
index 00000000..8ed36862
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4297-drm-amdgpu-powerplay-vega10-allow-undervolting-in-p7.patch
@@ -0,0 +1,36 @@
+From 21e9e32420338fd825fae8951eec7381232a5d59 Mon Sep 17 00:00:00 2001
+From: Pelle van Gils <pelle@vangils.xyz>
+Date: Thu, 24 Oct 2019 16:04:31 +0200
+Subject: [PATCH 4297/4736] drm/amdgpu/powerplay/vega10: allow undervolting in
+ p7
+
+The vega10_odn_update_soc_table() function does not allow the SCLK
+dependent voltage to be set for power-state 7 to a value below the default
+in pptable. Change the for-loop condition to allow undervolting in the
+highest state.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205277
+Signed-off-by: Pelle van Gils <pelle@vangils.xyz>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index c31ef4262c9e..f62e320ed43d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -5095,9 +5095,7 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
+
+ if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
+ podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
+- for (i = 0; i < podn_vdd_dep->count - 1; i++)
+- od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
+- if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc)
++ for (i = 0; i < podn_vdd_dep->count; i++)
+ od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
+ } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
+ podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4298-drm-amd-powerplay-Make-two-functions-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4298-drm-amd-powerplay-Make-two-functions-static.patch
new file mode 100644
index 00000000..7d864985
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4298-drm-amd-powerplay-Make-two-functions-static.patch
@@ -0,0 +1,44 @@
+From 2f0a3ce21f89ed530c9fbdfdde05b8815cce575c Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 28 Oct 2019 21:36:21 +0800
+Subject: [PATCH 4298/4736] drm/amd/powerplay: Make two functions static
+
+Fix sparse warnings:
+
+drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2050:5:
+ warning: symbol 'arcturus_i2c_eeprom_control_init' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2068:6:
+ warning: symbol 'arcturus_i2c_eeprom_control_fini' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 93633f76989e..4315a887e918 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -2047,7 +2047,7 @@ static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
+ .functionality = arcturus_i2c_eeprom_i2c_func,
+ };
+
+-int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
++static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
+ {
+ struct amdgpu_device *adev = to_amdgpu_device(control);
+ int res;
+@@ -2065,7 +2065,7 @@ int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
+ return res;
+ }
+
+-void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
++static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
+ {
+ i2c_del_adapter(control);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4299-drm-amd-display-Make-calculate_integer_scaling-stati.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4299-drm-amd-display-Make-calculate_integer_scaling-stati.patch
new file mode 100644
index 00000000..41b7d4c7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4299-drm-amd-display-Make-calculate_integer_scaling-stati.patch
@@ -0,0 +1,34 @@
+From 891fb7b5e78dcbadf7f2ccf05f23ff505b32fbf4 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 28 Oct 2019 21:34:36 +0800
+Subject: [PATCH 4299/4736] drm/amd/display: Make calculate_integer_scaling
+ static
+
+Fix sparse warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:963:6:
+ warning: symbol 'calculate_integer_scaling' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index e8b16b4acacc..42c44c05759f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -957,7 +957,7 @@ static bool are_rects_integer_multiples(struct rect src, struct rect dest)
+ return false;
+ }
+
+-void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
++static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
+ {
+ if (!pipe_ctx->plane_state->scaling_quality.integer_scaling)
+ return;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4300-drm-amd-declare-amdgpu_exp_hw_support-in-amdgpu.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4300-drm-amd-declare-amdgpu_exp_hw_support-in-amdgpu.h.patch
new file mode 100644
index 00000000..ca97d02b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4300-drm-amd-declare-amdgpu_exp_hw_support-in-amdgpu.h.patch
@@ -0,0 +1,31 @@
+From 857c235862ef0e14bea15e33a23ebaf9ea7a151f Mon Sep 17 00:00:00 2001
+From: Wambui Karuga <wambui.karugax@gmail.com>
+Date: Mon, 28 Oct 2019 12:20:04 +0300
+Subject: [PATCH 4300/4736] drm/amd: declare amdgpu_exp_hw_support in amdgpu.h
+
+Declare `amdgpu_exp_hw_support` as extern in amdgpu.h to address the
+following sparse warning:
+drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:118:5: warning: symbol 'amdgpu_exp_hw_support' was not declared. Should it be static?
+
+Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
+Suggested-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index f1f258a2790a..ee31b20b0656 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -142,6 +142,7 @@ extern int amdgpu_vm_fragment_size;
+ extern int amdgpu_vm_fault_stop;
+ extern int amdgpu_vm_debug;
+ extern int amdgpu_vm_update_mode;
++extern int amdgpu_exp_hw_support;
+ extern int amdgpu_dc;
+ extern int amdgpu_sched_jobs;
+ extern int amdgpu_sched_hw_submission;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4301-drm-amd-correct-_LENTH-mispelling-in-constant.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4301-drm-amd-correct-_LENTH-mispelling-in-constant.patch
new file mode 100644
index 00000000..bb07daa6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4301-drm-amd-correct-_LENTH-mispelling-in-constant.patch
@@ -0,0 +1,70 @@
+From c9c7c06085f5588971dae06a865d449bcb1d02d4 Mon Sep 17 00:00:00 2001
+From: Wambui Karuga <wambui.karugax@gmail.com>
+Date: Mon, 28 Oct 2019 12:20:05 +0300
+Subject: [PATCH 4301/4736] drm/amd: correct "_LENTH" mispelling in constant
+
+Correct the "_LENTH" mispelling in the AMDGPU_MAX_TIMEOUT_PARAM_LENGTH
+constant.
+
+Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index ee31b20b0656..2eb3a6bcbd6c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -109,7 +109,7 @@ struct amdgpu_mgpu_info
+ uint32_t num_apu;
+ };
+
+-#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
++#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
+
+ /*
+ * Modules parameters.
+@@ -128,7 +128,7 @@ extern int amdgpu_disp_priority;
+ extern int amdgpu_hw_i2c;
+ extern int amdgpu_pcie_gen2;
+ extern int amdgpu_msi;
+-extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
++extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
+ extern int amdgpu_dpm;
+ extern int amdgpu_fw_load_type;
+ extern int amdgpu_aspm;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index e30e4f8f7df3..7d134976492a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2628,9 +2628,9 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
+ else
+ adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
+
+- if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
++ if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
+ while ((timeout_setting = strsep(&input, ",")) &&
+- strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
++ strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
+ ret = kstrtol(timeout_setting, 0, &timeout);
+ if (ret)
+ return ret;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 131dd2e91bf0..97d6103bc023 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -99,7 +99,7 @@ int amdgpu_disp_priority = 0;
+ int amdgpu_hw_i2c = 0;
+ int amdgpu_pcie_gen2 = -1;
+ int amdgpu_msi = -1;
+-char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
++char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
+ int amdgpu_dpm = -1;
+ int amdgpu_fw_load_type = -1;
+ int amdgpu_aspm = -1;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4302-drm-amdgpu-remove-set-but-not-used-variable-adev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4302-drm-amdgpu-remove-set-but-not-used-variable-adev.patch
new file mode 100644
index 00000000..01b47274
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4302-drm-amdgpu-remove-set-but-not-used-variable-adev.patch
@@ -0,0 +1,68 @@
+From 48bce9df3f014a63fd877f3cd651af7bec1a87eb Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Wed, 23 Oct 2019 15:58:31 +0800
+Subject: [PATCH 4302/4736] drm/amdgpu: remove set but not used variable 'adev'
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1221:24: warning: variable adev set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:488:24: warning: variable adev set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:547:24: warning: variable adev set but not used [-Wunused-but-set-variable]
+
+It is never used, so can removed it.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 8bdc1eec496e..9a094e118d96 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -596,15 +596,12 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
+ struct ttm_mem_reg *new_mem)
+ {
+- struct amdgpu_device *adev;
+ struct ttm_mem_reg *old_mem = &bo->mem;
+ struct ttm_mem_reg tmp_mem;
+ struct ttm_place placements;
+ struct ttm_placement placement;
+ int r;
+
+- adev = amdgpu_ttm_adev(bo->bdev);
+-
+ /* create space/pages for new_mem in GTT space */
+ tmp_mem = *new_mem;
+ tmp_mem.mm_node = NULL;
+@@ -655,15 +652,12 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
+ struct ttm_operation_ctx *ctx,
+ struct ttm_mem_reg *new_mem)
+ {
+- struct amdgpu_device *adev;
+ struct ttm_mem_reg *old_mem = &bo->mem;
+ struct ttm_mem_reg tmp_mem;
+ struct ttm_placement placement;
+ struct ttm_place placements;
+ int r;
+
+- adev = amdgpu_ttm_adev(bo->bdev);
+-
+ /* make space in GTT for old_mem buffer */
+ tmp_mem = *new_mem;
+ tmp_mem.mm_node = NULL;
+@@ -1372,11 +1366,8 @@ static struct ttm_backend_func amdgpu_backend_func = {
+ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
+ uint32_t page_flags)
+ {
+- struct amdgpu_device *adev;
+ struct amdgpu_ttm_tt *gtt;
+
+- adev = amdgpu_ttm_adev(bo->bdev);
+-
+ gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
+ if (gtt == NULL) {
+ return NULL;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4303-drm-amdgpu-Remove-superfluous-void-cast-in-debugfs_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4303-drm-amdgpu-Remove-superfluous-void-cast-in-debugfs_c.patch
new file mode 100644
index 00000000..60b99cc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4303-drm-amdgpu-Remove-superfluous-void-cast-in-debugfs_c.patch
@@ -0,0 +1,34 @@
+From 18aa3bbb4b9f2dcd2a215c9cf13f3fb975ffb41c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 21 Oct 2019 16:51:47 +0200
+Subject: [PATCH 4303/4736] drm/amdgpu: Remove superfluous void * cast in
+ debugfs_create_file() call
+
+There is no need to cast a typed pointer to a void pointer when calling
+a function that accepts the latter. Remove it, as the cast prevents
+further compiler checks.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+index f68438e8f092..996cb998dc1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -1086,8 +1086,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
+ {
+ adev->debugfs_preempt =
+ debugfs_create_file("amdgpu_preempt_ib", 0600,
+- adev->ddev->primary->debugfs_root,
+- (void *)adev, &fops_ib_preempt);
++ adev->ddev->primary->debugfs_root, adev,
++ &fops_ib_preempt);
+ if (!(adev->debugfs_preempt)) {
+ DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
+ return -EIO;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4304-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4304-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
new file mode 100644
index 00000000..9c048f9a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4304-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
@@ -0,0 +1,81 @@
+From 7db20f1d3760858814739b32f1e033c809123da6 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 25 Oct 2019 17:09:35 -0400
+Subject: [PATCH 4304/4736] drm/amdkfd: Delete unnecessary pr_fmt switch
+
+Given amdkfd.ko has been merged into amdgpu.ko, this switch is no
+longer useful.
+
+Change-Id: If56b80e086f4ea26f347c70b620b3892afc24ddf
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 3 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ----
+ 4 files changed, 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index 7288810e0df5..b91a9be32317 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -19,10 +19,6 @@
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/module.h>
+ #include <linux/fdtable.h>
+ #include <linux/uaccess.h>
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index b5091e31c83f..5eb289e887b3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -19,9 +19,6 @@
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index dae572c776cc..f1884b3941e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -19,10 +19,6 @@
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 3e13f3e9097a..9ce17867fac7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -19,10 +19,6 @@
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/list.h>
+ #include <linux/pagemap.h>
+ #include <linux/sched/mm.h>
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4305-drm-amdkfd-Delete-duplicated-queue-bit-map-reservati.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4305-drm-amdkfd-Delete-duplicated-queue-bit-map-reservati.patch
new file mode 100644
index 00000000..4aaa981e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4305-drm-amdkfd-Delete-duplicated-queue-bit-map-reservati.patch
@@ -0,0 +1,38 @@
+From bf30bff8f8fbd6e4d4cc1f2329194856fb54cb13 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 24 Oct 2019 17:05:57 -0400
+Subject: [PATCH 4305/4736] drm/amdkfd: Delete duplicated queue bit map
+ reservation
+
+The KIQ is on the second MEC and its reservation is covered in the
+latter logic, so no need to reserve its bit twice.
+
+Change-Id: Ieee390953a60c7d43de5a9aec38803f1f583a4a9
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 1783883e40b6..5ed49096224b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -136,14 +136,6 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
+ adev->gfx.mec.queue_bitmap,
+ KGD_MAX_QUEUES);
+
+- /* remove the KIQ bit as well */
+- if (adev->gfx.kiq.ring.sched.ready)
+- clear_bit(amdgpu_gfx_mec_queue_to_bit(adev,
+- adev->gfx.kiq.ring.me - 1,
+- adev->gfx.kiq.ring.pipe,
+- adev->gfx.kiq.ring.queue),
+- gpu_resources.queue_bitmap);
+-
+ /* According to linux/bitmap.h we shouldn't use bitmap_clear if
+ * nbits is not compile time constant
+ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4306-drm-amdkfd-bug-fix-for-out-of-bounds-mem-on-gpu-cach.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4306-drm-amdkfd-bug-fix-for-out-of-bounds-mem-on-gpu-cach.patch
new file mode 100644
index 00000000..ae9ad4bf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4306-drm-amdkfd-bug-fix-for-out-of-bounds-mem-on-gpu-cach.patch
@@ -0,0 +1,36 @@
+From 75cf0d7a899f1dfdd25b245476ea124c1db17fca Mon Sep 17 00:00:00 2001
+From: Alex Sierra <alex.sierra@amd.com>
+Date: Thu, 24 Oct 2019 13:14:31 -0500
+Subject: [PATCH 4306/4736] drm/amdkfd: bug fix for out of bounds mem on gpu
+ cache filling info
+
+The bitmap in cu_info structure is defined as a 4x4 size array. In
+Acturus, this matrix is initialized as a 4x2. Based on the 8 shaders.
+In the gpu cache filling initialization, the access to the bitmap matrix
+was done as an 8x1 instead of 4x2. Causing an out of bounds memory
+access error.
+Due to this, the number of GPU cache entries was inconsistent.
+
+Change-Id: I20fadd0a12403a8808cf074c0d7160daad6834ee
+Signed-off-by: Alex Sierra <alex.sierra@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index 7655c6a2b184..22fe58971a62 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -710,7 +710,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ pcache_info,
+ cu_info,
+ mem_available,
+- cu_info->cu_bitmap[i][j],
++ cu_info->cu_bitmap[i % 4][j + i / 4],
+ ct,
+ cu_processor_id,
+ k);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4307-drm-amd-display-Add-ENGINE_ID_DIGD-condition-check-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4307-drm-amd-display-Add-ENGINE_ID_DIGD-condition-check-f.patch
new file mode 100644
index 00000000..8445299a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4307-drm-amd-display-Add-ENGINE_ID_DIGD-condition-check-f.patch
@@ -0,0 +1,42 @@
+From e222a82077c62b125dd397a7da2167f63674d7fc Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Fri, 1 Nov 2019 22:42:41 -0400
+Subject: [PATCH 4307/4736] drm/amd/display: Add ENGINE_ID_DIGD condition check
+ for Navi14
+
+[Why]
+Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is
+because there is no ENGINE_ID_DIGD in Navi14. Without
+this patch, many HDMI related issues (e.g. HDMI S3
+resume failure, HDMI pink screen on boot) will be
+observed.
+
+[How]
+If "eng_id" is larger than ENGINE_ID_DIGD, then
+add "eng_id" by 1.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index d1c7e10cb722..ef43faa09eb3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1150,6 +1150,11 @@ struct stream_encoder *dcn20_stream_encoder_create(
+ if (!enc1)
+ return NULL;
+
++ if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
++ if (eng_id >= ENGINE_ID_DIGD)
++ eng_id++;
++ }
++
+ dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
+ &stream_enc_regs[eng_id],
+ &se_shift, &se_mask);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4308-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-Clan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4308-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-Clan.patch
new file mode 100644
index 00000000..5268111d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4308-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-Clan.patch
@@ -0,0 +1,161 @@
+From 0549828354c1707532b672c9e9d08ecc418c1421 Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Wed, 16 Oct 2019 16:02:07 -0700
+Subject: [PATCH 4308/4736] drm/amdgpu: fix stack alignment ABI mismatch for
+ Clang
+
+The x86 kernel is compiled with an 8B stack alignment via
+`-mpreferred-stack-boundary=3` for GCC since 3.6-rc1 via
+commit d9b0cde91c60 ("x86-64, gcc: Use -mpreferred-stack-boundary=3 if supported")
+or `-mstack-alignment=8` for Clang. Parts of the AMDGPU driver are
+compiled with 16B stack alignment.
+
+Generally, the stack alignment is part of the ABI. Linking together two
+different translation units with differing stack alignment is dangerous,
+particularly when the translation unit with the smaller stack alignment
+makes calls into the translation unit with the larger stack alignment.
+While 8B aligned stacks are sometimes also 16B aligned, they are not
+always.
+
+Multiple users have reported General Protection Faults (GPF) when using
+the AMDGPU driver compiled with Clang. Clang is placing objects in stack
+slots assuming the stack is 16B aligned, and selecting instructions that
+require 16B aligned memory operands.
+
+At runtime, syscall handlers with 8B aligned stack call into code that
+assumes 16B stack alignment. When the stack is a multiple of 8B but not
+16B, these instructions result in a GPF.
+
+Remove the code that added compatibility between the differing compiler
+flags, as it will result in runtime GPFs when built with Clang. Cleanups
+for GCC will be sent in later patches in the series.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/735
+Tested-by: Shirish S <shirish.s@amd.com>
+Debugged-by: Yuxuan Shui <yshuiv7@gmail.com>
+Reported-by: Shirish S <shirish.s@amd.com>
+Reported-by: Yuxuan Shui <yshuiv7@gmail.com>
+Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dml/Makefile | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile | 10 ++++------
+ 5 files changed, 20 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+index 16614d73a5fc..ab522ea992d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -24,13 +24,11 @@
+ # It calculates Bandwidth and Watermarks values for HW programming
+ #
+
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+- cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+- cc_stack_align := -mstack-alignment=16
+-endif
++calcs_ccflags := -mhard-float -msse
+
+-calcs_ccflags := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++calcs_ccflags += -mpreferred-stack-boundary=4
++endif
+
+ ifdef CONFIG_CC_IS_CLANG
+ calcs_ccflags += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index f57a3b281408..a02e02980310 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -10,13 +10,11 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DCN20 += dcn20_dsc.o
+ endif
+
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+- cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+- cc_stack_align := -mstack-alignment=16
+-endif
++CFLAGS_dcn20_resource.o := -mhard-float -msse
+
+-CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++CFLAGS_dcn20_resource.o += -mpreferred-stack-boundary=4
++endif
+
+ ifdef CONFIG_CC_IS_CLANG
+ CFLAGS_dcn20_resource.o += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 4ddd4037c1f8..0fa857b69143 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -3,13 +3,11 @@
+
+ DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+- cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+- cc_stack_align := -mstack-alignment=16
+-endif
++CFLAGS_dcn21_resource.o := -mhard-float -msse
+
+-CFLAGS_dcn21_resource.o := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++CFLAGS_dcn21_resource.o += -mpreferred-stack-boundary=4
++endif
+
+ ifdef CONFIG_CC_IS_CLANG
+ CFLAGS_dcn21_resource.o += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index af2a864a6da0..b3db0900b473 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -24,13 +24,11 @@
+ # It provides the general basic services required by other DAL
+ # subcomponents.
+
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+- cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+- cc_stack_align := -mstack-alignment=16
+-endif
++dml_ccflags := -mhard-float -msse
+
+-dml_ccflags := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++dml_ccflags += -mpreferred-stack-boundary=4
++endif
+
+ ifdef CONFIG_CC_IS_CLANG
+ dml_ccflags += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+index 17db603f2d1f..4d18e2b60223 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -1,13 +1,11 @@
+ #
+ # Makefile for the 'dsc' sub-component of DAL.
+
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+- cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+- cc_stack_align := -mstack-alignment=16
+-endif
++dsc_ccflags := -mhard-float -msse
+
+-dsc_ccflags := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++dsc_ccflags += -mpreferred-stack-boundary=4
++endif
+
+ ifdef CONFIG_CC_IS_CLANG
+ dsc_ccflags += -msse2
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4309-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-GCC-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4309-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-GCC-.patch
new file mode 100644
index 00000000..8be7461e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4309-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-GCC-.patch
@@ -0,0 +1,155 @@
+From b7033f0828ca07dbc4e3a8b4f4c91b23e09eb08c Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Wed, 16 Oct 2019 16:02:08 -0700
+Subject: [PATCH 4309/4736] drm/amdgpu: fix stack alignment ABI mismatch for
+ GCC 7.1+
+
+GCC earlier than 7.1 errors when compiling code that makes use of
+`double`s and sets a stack alignment outside of the range of [2^4-2^12]:
+
+$ cat foo.c
+double foo(double x, double y) {
+ return x + y;
+}
+$ gcc-4.9 -mpreferred-stack-boundary=3 foo.c
+error: -mpreferred-stack-boundary=3 is not between 4 and 12
+
+This is likely why the AMDGPU driver was ever compiled with a different
+stack alignment (and thus different ABI) than the rest of the x86
+kernel. The kernel uses 8B stack alignment, while the driver was using
+16B stack alignment in a few places.
+
+Since GCC 7.1+ doesn't error, fix the ABI mismatch for users of newer
+versions of GCC.
+
+There was discussion about whether to mark the driver broken or not for
+users of GCC earlier than 7.1, but since the driver currently is
+working, don't explicitly break the driver for them here.
+
+Relying on differing stack alignment is unspecified behavior, and
+brittle, and may break in the future.
+
+This patch is no functional change for GCC users earlier than 7.1. It's
+been compile tested on GCC 4.9 and 8.3 to check the correct flags. It
+should be boot tested when built with GCC 7.1+.
+
+-mincoming-stack-boundary= or -mstackrealign may help keep this code
+building for pre-GCC 7.1 users.
+
+The version check for GCC is broken into two conditionals, both because
+cc-ifversion is currently GCC specific, and it simplifies a subsequent
+patch.
+
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dml/Makefile | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile | 9 +++++++++
+ 5 files changed, 45 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+index ab522ea992d2..393215ef9f98 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -27,6 +27,15 @@
+ calcs_ccflags := -mhard-float -msse
+
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ calcs_ccflags += -mpreferred-stack-boundary=4
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index a02e02980310..d684cb912d92 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -13,6 +13,15 @@ endif
+ CFLAGS_dcn20_resource.o := -mhard-float -msse
+
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ CFLAGS_dcn20_resource.o += -mpreferred-stack-boundary=4
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 0fa857b69143..72609a40c6a3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -6,6 +6,15 @@ DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_en
+ CFLAGS_dcn21_resource.o := -mhard-float -msse
+
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ CFLAGS_dcn21_resource.o += -mpreferred-stack-boundary=4
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index b3db0900b473..f85f2bb1b0c7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -27,6 +27,15 @@
+ dml_ccflags := -mhard-float -msse
+
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ dml_ccflags += -mpreferred-stack-boundary=4
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+index 4d18e2b60223..ec2ebee0078f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -4,6 +4,15 @@
+ dsc_ccflags := -mhard-float -msse
+
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ dsc_ccflags += -mpreferred-stack-boundary=4
+ endif
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4310-drm-amdgpu-enable-msse2-for-GCC-7.1-users.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4310-drm-amdgpu-enable-msse2-for-GCC-7.1-users.patch
new file mode 100644
index 00000000..2925348d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4310-drm-amdgpu-enable-msse2-for-GCC-7.1-users.patch
@@ -0,0 +1,122 @@
+From 89ebce5861f64bd3fcd1aa17d12e6d181632234e Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Wed, 16 Oct 2019 16:02:09 -0700
+Subject: [PATCH 4310/4736] drm/amdgpu: enable -msse2 for GCC 7.1+ users
+
+A final attempt at enabling sse2 for GCC users.
+
+Orininally attempted in:
+commit 10117450735c ("drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines")
+
+Reverted due to "reported instability" in:
+commit 193392ed9f69 ("Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines"")
+
+Re-added just for Clang in:
+commit 0f0727d971f6 ("drm/amd/display: readd -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines")
+
+The original report didn't have enough information to know if the GPF
+was due to misalignment, but I suspect that it was. (The missing
+information was the disassembly of the function at the bottom of the
+trace, to see if the instruction pointer pointed to an instruction with
+16B alignment memory operand requirements. The stack trace does show
+the stack was only 8B but not 16B aligned though, which makes this a
+strong possibility).
+
+Now that the stack misalignment issue has been fixed for users of GCC
+7.1+, reattempt adding -msse2. This matches Clang.
+
+It will likely never be safe to enable this for pre-GCC 7.1 AND use a
+16B aligned stack in these translation units.
+
+This is only a functional change for GCC 7.1+ users, and should be boot
+tested.
+
+Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 +---
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 +---
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 +---
+ drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 +---
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile | 4 +---
+ 5 files changed, 5 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+index 393215ef9f98..e59a7f356188 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -37,9 +37,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ calcs_ccflags += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ calcs_ccflags += -msse2
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index d684cb912d92..be3a614963c6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -23,9 +23,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ CFLAGS_dcn20_resource.o += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ CFLAGS_dcn20_resource.o += -msse2
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 72609a40c6a3..feb7e705e792 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -16,9 +16,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ CFLAGS_dcn21_resource.o += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ CFLAGS_dcn21_resource.o += -msse2
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index f85f2bb1b0c7..9cc2fe56ed64 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -37,9 +37,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ dml_ccflags += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ dml_ccflags += -msse2
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+index ec2ebee0078f..2fff8c1f1a78 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -14,9 +14,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ dsc_ccflags += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ dsc_ccflags += -msse2
+ endif
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4311-drm-amdgpu-SRIOV-SRIOV-VF-doesn-t-support-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4311-drm-amdgpu-SRIOV-SRIOV-VF-doesn-t-support-BACO.patch
new file mode 100644
index 00000000..af3252c0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4311-drm-amdgpu-SRIOV-SRIOV-VF-doesn-t-support-BACO.patch
@@ -0,0 +1,31 @@
+From 945b8d7e559e3fd6c9a2379318ede76d21febe02 Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Mon, 28 Oct 2019 18:04:14 +0800
+Subject: [PATCH 4311/4736] drm/amdgpu/SRIOV: SRIOV VF doesn't support BACO
+
+SRIOV VF doesn't support BACO.
+
+Only PF with BACO capability can do it.
+
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index ebbf7712f8c8..88e3665f7b09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -298,7 +298,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
+ {
+ struct smu_context *smu = &adev->smu;
+
+- if (smu_baco_is_support(smu))
++ if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
+ return AMD_RESET_METHOD_BACO;
+ else
+ return AMD_RESET_METHOD_MODE1;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4312-drm-amdgpu-clear-UVD-VCPU-buffer-when-err_event_athu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4312-drm-amdgpu-clear-UVD-VCPU-buffer-when-err_event_athu.patch
new file mode 100644
index 00000000..eaa0a0f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4312-drm-amdgpu-clear-UVD-VCPU-buffer-when-err_event_athu.patch
@@ -0,0 +1,46 @@
+From 986adea80905c6b7232acd8b5dc702c39fb40c3e Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 25 Oct 2019 16:50:53 +0800
+Subject: [PATCH 4312/4736] drm/amdgpu: clear UVD VCPU buffer when
+ err_event_athub generated
+
+The err_event_athub error will mess up the buffer and cause UVD resume hang.
+
+Change-Id: If17a2161fb9b1b52eac08de00d2e935191bdbf99
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index 4e5d13e41f6a..d1b10b5583ec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -39,6 +39,8 @@
+ #include "cikd.h"
+ #include "uvd/uvd_4_2_d.h"
+
++#include "amdgpu_ras.h"
++
+ /* 1 second timeout */
+ #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
+
+@@ -372,7 +374,13 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
+ if (!adev->uvd.inst[j].saved_bo)
+ return -ENOMEM;
+
+- memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
++ /* re-write 0 since err_event_athub will corrupt VCPU buffer */
++ if (amdgpu_ras_intr_triggered()) {
++ DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
++ memset(adev->uvd.inst[j].saved_bo, 0, size);
++ } else {
++ memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
++ }
+ }
+ return 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4313-drm-amdgpu-bypass-some-cleanup-work-after-err_event_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4313-drm-amdgpu-bypass-some-cleanup-work-after-err_event_.patch
new file mode 100644
index 00000000..5d876186
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4313-drm-amdgpu-bypass-some-cleanup-work-after-err_event_.patch
@@ -0,0 +1,106 @@
+From 0fc7d72e51896c4a2fbfb0bcf7f83a6fa4a50a3c Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 25 Oct 2019 17:48:52 +0800
+Subject: [PATCH 4313/4736] drm/amdgpu: bypass some cleanup work after
+ err_event_athub
+
+PSP lost connection when err_event_athub occurs. These cleanup work can be
+skipped in BACO reset.
+
+Change-Id: If54a3735edd6ccbb58d40a5f8833392981f8ce37
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 20 +++++++++++---------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++++--
+ 4 files changed, 28 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 7d134976492a..8e35ebdf4e10 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2270,6 +2270,12 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ /* displays are handled in phase1 */
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
+ continue;
++ /* PSP lost connection when err_event_athub occurs */
++ if (amdgpu_ras_intr_triggered() &&
++ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
++ adev->ip_blocks[i].status.hw = false;
++ continue;
++ }
+ /* XXX handle errors */
+ r = adev->ip_blocks[i].version->funcs->suspend(adev);
+ /* XXX handle errors */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index f289a84363c4..4aa21bc1e0b9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -167,6 +167,13 @@ psp_cmd_submit_buf(struct psp_context *psp,
+ while (*((unsigned int *)psp->fence_buf) != index) {
+ if (--timeout == 0)
+ break;
++ /*
++ * Shouldn't wait for timeout when err_event_athub occurs,
++ * because gpu reset thread triggered and lock resource should
++ * be released for psp resume sequence.
++ */
++ if (amdgpu_ras_intr_triggered())
++ break;
+ msleep(1);
+ amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index ebc3e15eca8b..afc3ee47d1b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -556,15 +556,17 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
+ if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
+ return 0;
+
+- ret = psp_ras_enable_features(&adev->psp, &info, enable);
+- if (ret) {
+- DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
+- enable ? "enable":"disable",
+- ras_block_str(head->block),
+- ret);
+- if (ret == TA_RAS_STATUS__RESET_NEEDED)
+- return -EAGAIN;
+- return -EINVAL;
++ if (!amdgpu_ras_intr_triggered()) {
++ ret = psp_ras_enable_features(&adev->psp, &info, enable);
++ if (ret) {
++ DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
++ enable ? "enable":"disable",
++ ras_block_str(head->block),
++ ret);
++ if (ret == TA_RAS_STATUS__RESET_NEEDED)
++ return -EAGAIN;
++ return -EINVAL;
++ }
+ }
+
+ /* setup the obj */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2f03bf533d41..013c1eb990f0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3739,8 +3739,10 @@ static int gfx_v9_0_hw_fini(void *handle)
+ amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
+ amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+
+- /* disable KCQ to avoid CPC touch memory not valid anymore */
+- gfx_v9_0_kcq_disable(adev);
++ /* DF freeze and kcq disable will fail */
++ if (!amdgpu_ras_intr_triggered())
++ /* disable KCQ to avoid CPC touch memory not valid anymore */
++ gfx_v9_0_kcq_disable(adev);
+
+ if (amdgpu_sriov_vf(adev)) {
+ gfx_v9_0_cp_gfx_enable(adev, false);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4314-drm-amdgpu-add-missing-amdgpu_ras.h-header-include.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4314-drm-amdgpu-add-missing-amdgpu_ras.h-header-include.patch
new file mode 100644
index 00000000..2549a07b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4314-drm-amdgpu-add-missing-amdgpu_ras.h-header-include.patch
@@ -0,0 +1,35 @@
+From d4080f0c35aa04fd1fd837071c4beb2c96135913 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 29 Oct 2019 20:39:13 +0800
+Subject: [PATCH 4314/4736] drm/amdgpu: add missing amdgpu_ras.h header include
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix compilation error.
+
+Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
+Signed-off-by: Le Ma <le.ma@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Christian K«Ónig <christian.koenig@amd.com>
+Tested-by: Tom St Denis <tom.stdenis@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 4aa21bc1e0b9..8a1960106004 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -34,6 +34,8 @@
+ #include "psp_v11_0.h"
+ #include "psp_v12_0.h"
+
++#include "amdgpu_ras.h"
++
+ static void psp_set_funcs(struct amdgpu_device *adev);
+
+ static int psp_early_init(void *handle)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4315-drm-amdgpu-fix-gfx-VF-FLR-test-fail-on-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4315-drm-amdgpu-fix-gfx-VF-FLR-test-fail-on-navi.patch
new file mode 100644
index 00000000..33ae4de8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4315-drm-amdgpu-fix-gfx-VF-FLR-test-fail-on-navi.patch
@@ -0,0 +1,30 @@
+From 3f342675d69b28118f84ecf90469545de2b486a0 Mon Sep 17 00:00:00 2001
+From: HaiJun Chang <HaiJun.Chang@amd.com>
+Date: Tue, 29 Oct 2019 15:44:08 +0800
+Subject: [PATCH 4315/4736] drm/amdgpu: fix gfx VF FLR test fail on navi
+
+Cp wptr in wb buffer is outdated after VF FLR.
+The outdated wptr may cause cp to execute unexpected packets.
+Reset cp wptr in wb buffer.
+
+Signed-off-by: HaiJun Chang <HaiJun.Chang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ef1975a5323a..17a5cbfd0024 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3094,6 +3094,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
+ memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
+ /* reset the ring */
+ ring->wptr = 0;
++ adev->wb.wb[ring->wptr_offs] = 0;
+ amdgpu_ring_clear_ring(ring);
+ #ifdef BRING_UP_DEBUG
+ mutex_lock(&adev->srbm_mutex);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4316-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4316-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
new file mode 100644
index 00000000..720913f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4316-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
@@ -0,0 +1,64 @@
+From 28fcbf07bd27326ecd302f1dc316bdd854dae397 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 25 Oct 2019 17:09:35 -0400
+Subject: [PATCH 4316/4736] drm/amdkfd: Delete unnecessary pr_fmt switch
+
+Given amdkfd.ko has been merged into amdgpu.ko, this switch is no
+longer useful.
+
+Change-Id: I3ef93ac4510a1caf37acc1d337afd61a8a241baa
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 4 ----
+ 3 files changed, 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 5ed49096224b..3cccb4b10862 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -20,9 +20,6 @@
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+
+ #include "amdgpu_amdkfd.h"
+ #include <linux/dma-buf.h>
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index 495b15ed28cd..07f14a9f93b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -19,10 +19,6 @@
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index 0118e6f18355..d14e85205bce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -19,10 +19,6 @@
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4317-drm-amdgpu-fix-no-ACK-from-LDS-read-during-stress-te.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4317-drm-amdgpu-fix-no-ACK-from-LDS-read-during-stress-te.patch
new file mode 100644
index 00000000..011bdfb4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4317-drm-amdgpu-fix-no-ACK-from-LDS-read-during-stress-te.patch
@@ -0,0 +1,30 @@
+From a60c3cf2abde5a55177f66cc039ba6f0d7d85e70 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 30 Oct 2019 16:46:32 +0800
+Subject: [PATCH 4317/4736] drm/amdgpu: fix no ACK from LDS read during stress
+ test for Arcturus
+
+Set mmSQ_CONFIG.DISABLE_SMEM_SOFT_CLAUSE as W/R.
+
+Change-Id: I6225909fd62702427fbb807e0c6ba6bafcfa41d5
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 013c1eb990f0..005f4d0d2484 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -699,6 +699,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
+ };
+
+ static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch
new file mode 100644
index 00000000..b0392615
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch
@@ -0,0 +1,62 @@
+From e91ddfb275ca28dc49b511edae9bad77b9c4d132 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 29 Oct 2019 17:14:15 -0400
+Subject: [PATCH 4318/4736] drm/amdgpu/gmc10: properly set BANK_SELECT and
+ FRAGMENT_SIZE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These were not aligned for optimal performance for GPUVM.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Tianci Yin <tianci.yin@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 9 +++++++++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index b601c6740ef5..b4f32d853ca1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -155,6 +155,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
+
+ tmp = mmGCVM_L2_CNTL3_DEFAULT;
++ if (adev->gmc.translate_further) {
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++ } else {
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
++ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++ }
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
+
+ tmp = mmGCVM_L2_CNTL4_DEFAULT;
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 2eea702de8ee..945533634711 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -142,6 +142,15 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
+
+ tmp = mmMMVM_L2_CNTL3_DEFAULT;
++ if (adev->gmc.translate_further) {
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++ } else {
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
++ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++ }
+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
+
+ tmp = mmMMVM_L2_CNTL4_DEFAULT;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4319-drm-amdgpu-arcturus-properly-set-BANK_SELECT-and-FRA.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4319-drm-amdgpu-arcturus-properly-set-BANK_SELECT-and-FRA.patch
new file mode 100644
index 00000000..7d4000bf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4319-drm-amdgpu-arcturus-properly-set-BANK_SELECT-and-FRA.patch
@@ -0,0 +1,40 @@
+From e966a78c81855195a1b694d262a3f95a5efe0594 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 30 Oct 2019 13:29:52 -0400
+Subject: [PATCH 4319/4736] drm/amdgpu/arcturus: properly set BANK_SELECT and
+ FRAGMENT_SIZE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These were not aligned for optimal performance for GPUVM.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 657970f9ebfb..2c5adfe803a2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -219,6 +219,15 @@ static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
+
+ tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
++ if (adev->gmc.translate_further) {
++ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
++ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++ } else {
++ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
++ tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
++ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++ }
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4320-drm-amd-display-remove-redundant-null-pointer-check-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4320-drm-amd-display-remove-redundant-null-pointer-check-.patch
new file mode 100644
index 00000000..b57893e7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4320-drm-amd-display-remove-redundant-null-pointer-check-.patch
@@ -0,0 +1,34 @@
+From 4c4c22b025ba1bbd162e1e845ac29e062e08f6d9 Mon Sep 17 00:00:00 2001
+From: zhong jiang <zhongjiang@huawei.com>
+Date: Wed, 30 Oct 2019 09:57:53 +0800
+Subject: [PATCH 4320/4736] drm/amd/display: remove redundant null pointer
+ check before kfree
+
+kfree has taken null pointer into account. hence it is safe to remove
+the unnecessary check.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: zhong jiang <zhongjiang@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+index cf6ef387e5d2..6f730b5bfe42 100644
+--- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
++++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+@@ -174,9 +174,7 @@ static bool hdmi_14_process_transaction(
+ link->ctx,
+ link,
+ &i2c_command);
+-
+- if (buff)
+- kfree(buff);
++ kfree(buff);
+
+ return result;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4321-drm-amd-display-Add-a-conversion-function-for-transm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4321-drm-amd-display-Add-a-conversion-function-for-transm.patch
new file mode 100644
index 00000000..daa8b2f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4321-drm-amd-display-Add-a-conversion-function-for-transm.patch
@@ -0,0 +1,95 @@
+From 7df7fe47021bfda137254b2bd114e5728b3aa56c Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Tue, 29 Oct 2019 23:04:11 -0700
+Subject: [PATCH 4321/4736] drm/amd/display: Add a conversion function for
+ transmitter and phy_id enums
+
+Clang warns:
+
+../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:2520:42:
+error: implicit conversion from enumeration type 'enum transmitter' to
+different enumeration type 'enum physical_phy_id'
+[-Werror,-Wenum-conversion]
+ psr_context->smuPhyId = link->link_enc->transmitter;
+ ~ ~~~~~~~~~~~~~~~~^~~~~~~~~~~
+1 error generated.
+
+As the comment above this assignment states, this is intentional. To
+match previous warnings of this nature, add a conversion function that
+explicitly converts between the enums and warns when there is a
+mismatch.
+
+See commit 828cfa29093f ("drm/amdgpu: Fix amdgpu ras to ta enums
+conversion") and commit d9ec5cfd5a2e ("drm/amd/display: Use switch table
+for dc_to_smu_clock_type") for previous examples of this.
+
+v2: use PHYLD_UNKNOWN for the default case.
+
+Fixes: e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
+Link: https://github.com/ClangBuiltLinux/linux/issues/758
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 38 ++++++++++++++++++-
+ 1 file changed, 37 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index e87124fe981c..fad7f3b7bc31 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2445,6 +2445,41 @@ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
+ return true;
+ }
+
++static inline enum physical_phy_id
++transmitter_to_phy_id(enum transmitter transmitter_value)
++{
++ switch (transmitter_value) {
++ case TRANSMITTER_UNIPHY_A:
++ return PHYLD_0;
++ case TRANSMITTER_UNIPHY_B:
++ return PHYLD_1;
++ case TRANSMITTER_UNIPHY_C:
++ return PHYLD_2;
++ case TRANSMITTER_UNIPHY_D:
++ return PHYLD_3;
++ case TRANSMITTER_UNIPHY_E:
++ return PHYLD_4;
++ case TRANSMITTER_UNIPHY_F:
++ return PHYLD_5;
++ case TRANSMITTER_NUTMEG_CRT:
++ return PHYLD_6;
++ case TRANSMITTER_TRAVIS_CRT:
++ return PHYLD_7;
++ case TRANSMITTER_TRAVIS_LCD:
++ return PHYLD_8;
++ case TRANSMITTER_UNIPHY_G:
++ return PHYLD_9;
++ case TRANSMITTER_COUNT:
++ return PHYLD_COUNT;
++ case TRANSMITTER_UNKNOWN:
++ return PHYLD_UNKNOWN;
++ default:
++ WARN_ONCE(1, "Unknown transmitter value %d\n",
++ transmitter_value);
++ return PHYLD_UNKNOWN;
++ }
++}
++
+ bool dc_link_setup_psr(struct dc_link *link,
+ const struct dc_stream_state *stream, struct psr_config *psr_config,
+ struct psr_context *psr_context)
+@@ -2515,7 +2550,8 @@ bool dc_link_setup_psr(struct dc_link *link,
+ /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
+ psr_context->phyType = PHY_TYPE_UNIPHY;
+ /*PhyId is associated with the transmitter id*/
+- psr_context->smuPhyId = link->link_enc->transmitter;
++ psr_context->smuPhyId =
++ transmitter_to_phy_id(link->link_enc->transmitter);
+
+ psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
+ psr_context->vsyncRateHz = div64_u64(div64_u64((stream->
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4322-drm-amdgpu-dont-schedule-jobs-while-in-reset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4322-drm-amdgpu-dont-schedule-jobs-while-in-reset.patch
new file mode 100644
index 00000000..78986057
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4322-drm-amdgpu-dont-schedule-jobs-while-in-reset.patch
@@ -0,0 +1,50 @@
+From 70c8d49e2851d253b6d9ea62beb9a2661975b633 Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Wed, 30 Oct 2019 14:20:46 +0530
+Subject: [PATCH 4322/4736] drm/amdgpu: dont schedule jobs while in reset
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[Why]
+
+doing kthread_park()/unpark() from drm_sched_entity_fini
+while GPU reset is in progress defeats all the purpose of
+drm_sched_stop->kthread_park.
+If drm_sched_entity_fini->kthread_unpark() happens AFTER
+drm_sched_stop->kthread_park nothing prevents from another
+(third) thread to keep submitting job to HW which will be
+picked up by the unparked scheduler thread and try to submit
+to HW but fail because the HW ring is deactivated.
+
+[How]
+grab the reset lock before calling drm_sched_entity_fini()
+
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Suggested-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 22097a3a5bc5..0300635f6f63 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -607,8 +607,11 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
+ continue;
+ }
+
+- for (i = 0; i < num_entities; i++)
++ for (i = 0; i < num_entities; i++) {
++ mutex_lock(&ctx->adev->lock_reset);
+ drm_sched_entity_fini(&ctx->entities[0][i].entity);
++ mutex_unlock(&ctx->adev->lock_reset);
++ }
+ }
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch
new file mode 100644
index 00000000..3c934b9a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch
@@ -0,0 +1,96 @@
+From 8d04ab50151f2f903e195a2b0c5d5f6bba03664a Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 22 Oct 2019 13:07:55 -0400
+Subject: [PATCH 4323/4736] drm/amdgpu: Add ucode support for DMCUB
+
+The DMCUB is a secondary DMCU (Display MicroController Unit) that has
+its own separate firmware. It's required for DMCU support on Renoir.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 11 ++++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 9 +++++++++
+ 2 files changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index fce1f71c1cff..86cd75ca39d2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -447,6 +447,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ const struct common_firmware_header *header = NULL;
+ const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
+ const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
++ const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
+
+ if (NULL == ucode->fw)
+ return 0;
+@@ -460,6 +461,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ header = (const struct common_firmware_header *)ucode->fw->data;
+ cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+ dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
++ dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
+
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
+ (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
+@@ -470,7 +472,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
+ ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
+ ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
+- ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {
++ ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
++ ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
+ ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
+
+ memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+@@ -506,6 +509,12 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ le32_to_cpu(header->ucode_array_offset_bytes) +
+ le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
+ ucode->ucode_size);
++ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {
++ ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
++ memcpy(ucode->kaddr,
++ (void *)((uint8_t *)ucode->fw->data +
++ le32_to_cpu(header->ucode_array_offset_bytes)),
++ ucode->ucode_size);
+ } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
+ ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
+ memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+index 410587b950f3..eaf2d5b9c92f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -251,6 +251,13 @@ struct dmcu_firmware_header_v1_0 {
+ uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
+ };
+
++/* version_major=1, version_minor=0 */
++struct dmcub_firmware_header_v1_0 {
++ struct common_firmware_header header;
++ uint32_t inst_const_bytes; /* size of instruction region, in bytes */
++ uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
++};
++
+ /* header is fixed size */
+ union amdgpu_firmware_header {
+ struct common_firmware_header common;
+@@ -268,6 +275,7 @@ union amdgpu_firmware_header {
+ struct sdma_firmware_header_v1_1 sdma_v1_1;
+ struct gpu_info_firmware_header_v1_0 gpu_info;
+ struct dmcu_firmware_header_v1_0 dmcu;
++ struct dmcub_firmware_header_v1_0 dmcub;
+ uint8_t raw[0x100];
+ };
+
+@@ -307,6 +315,7 @@ enum AMDGPU_UCODE_ID {
+ AMDGPU_UCODE_ID_DMCU_INTV,
+ AMDGPU_UCODE_ID_VCN0_RAM,
+ AMDGPU_UCODE_ID_VCN1_RAM,
++ AMDGPU_UCODE_ID_DMCUB,
+ AMDGPU_UCODE_ID_MAXIMUM,
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4324-drm-amdgpu-Add-PSP-loading-support-for-DMCUB-ucode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4324-drm-amdgpu-Add-PSP-loading-support-for-DMCUB-ucode.patch
new file mode 100644
index 00000000..b87dfd62
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4324-drm-amdgpu-Add-PSP-loading-support-for-DMCUB-ucode.patch
@@ -0,0 +1,35 @@
+From 2e1b45470e9e9a97e5036f14f5e912d4c1f1a94b Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 22 Oct 2019 13:24:00 -0400
+Subject: [PATCH 4324/4736] drm/amdgpu: Add PSP loading support for DMCUB ucode
+
+DMCUB ucode requires secure loading through PSP. This is already
+supported in PSP as GFX_FW_TYPE_DMUB, it just needs to be mapped from
+AMDGPU_UCODE_ID_DMCUB to GFX_FW_TYPE_DMUB.
+
+DMUB is a shorthand name for DMCUB and can be used interchangeably.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 8a1960106004..a33d1ed6a096 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1287,6 +1287,9 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
+ case AMDGPU_UCODE_ID_VCN1_RAM:
+ *type = GFX_FW_TYPE_VCN1_RAM;
+ break;
++ case AMDGPU_UCODE_ID_DMCUB:
++ *type = GFX_FW_TYPE_DMUB;
++ break;
+ case AMDGPU_UCODE_ID_MAXIMUM:
+ default:
+ return -EINVAL;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4325-drm-amd-display-Drop-DMCUB-from-DCN21-resources.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4325-drm-amd-display-Drop-DMCUB-from-DCN21-resources.patch
new file mode 100644
index 00000000..ab751029
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4325-drm-amd-display-Drop-DMCUB-from-DCN21-resources.patch
@@ -0,0 +1,80 @@
+From b9e226bd5d43b487569ff550ebdb0d9820b8bf3d Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 12:46:52 -0400
+Subject: [PATCH 4325/4736] drm/amd/display: Drop DMCUB from DCN21 resources
+
+The interface to the DMCUB won't be through DC itself. DC will instead
+call into the DMUB interface introduced with a future change.
+
+The CONFIG_DRM_AMD_DC_DMUB defines will still be used for now but will
+be dropped at the end of the series.
+
+Since this define was never configurable in the first place this code
+wasn't used.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 31 -------------------
+ 1 file changed, 31 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 987897748174..47367446f64c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -373,20 +373,6 @@ static const struct dce_abm_mask abm_mask = {
+ ABM_MASK_SH_LIST_DCN20(_MASK)
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-static const struct dcn21_dmcub_registers dmcub_regs = {
+- DMCUB_REG_LIST_DCN()
+-};
+-
+-static const struct dcn21_dmcub_shift dmcub_shift = {
+- DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+-};
+-
+-static const struct dcn21_dmcub_mask dmcub_mask = {
+- DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK)
+-};
+-#endif
+-
+ #define audio_regs(id)\
+ [id] = {\
+ AUD_COMMON_REG_LIST(id)\
+@@ -970,11 +956,6 @@ static void destruct(struct dcn21_resource_pool *pool)
+ if (pool->base.dmcu != NULL)
+ dce_dmcu_destroy(&pool->base.dmcu);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+- if (pool->base.dmcub != NULL)
+- dcn21_dmcub_destroy(&pool->base.dmcub);
+-#endif
+-
+ if (pool->base.dccg != NULL)
+ dcn_dccg_destroy(&pool->base.dccg);
+
+@@ -1787,18 +1768,6 @@ static bool construct(
+ goto create_fail;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+- pool->base.dmcub = dcn21_dmcub_create(ctx,
+- &dmcub_regs,
+- &dmcub_shift,
+- &dmcub_mask);
+- if (pool->base.dmcub == NULL) {
+- dm_error("DC: failed to create dmcub!\n");
+- BREAK_TO_DEBUGGER();
+- goto create_fail;
+- }
+-#endif
+-
+ pool->base.pp_smu = dcn21_pp_smu_create(ctx);
+
+ num_pipes = dcn2_1_ip.max_num_dpp;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4326-drm-amd-display-Add-the-DMUB-service.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4326-drm-amd-display-Add-the-DMUB-service.patch
new file mode 100644
index 00000000..0ea61b42
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4326-drm-amd-display-Add-the-DMUB-service.patch
@@ -0,0 +1,2227 @@
+From cee54bb1116f95c9283ccb627465db4f030f457f Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 11:28:35 -0400
+Subject: [PATCH 4326/4736] drm/amd/display: Add the DMUB service
+
+The DMUB service is the interface to the DMCUB.
+
+It's required to support Renoir features so it will be enabled and
+compiled automatically when the Renoir display engine is enabled via
+CONFIG_DRM_AMD_DC_DCN2_1.
+
+DMUB code will initially be guarded by CONFIG_DRM_AMD_DC_DMUB and later
+switched to CONFIG_DRM_AMD_DC_DCN2_1 with the config option dropped.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/Kconfig | 6 +
+ drivers/gpu/drm/amd/display/Makefile | 8 +
+ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 256 +++++++++
+ .../gpu/drm/amd/display/dmub/inc/dmub_rb.h | 129 +++++
+ .../gpu/drm/amd/display/dmub/inc/dmub_srv.h | 505 ++++++++++++++++++
+ .../amd/display/dmub/inc/dmub_trace_buffer.h | 51 ++
+ .../gpu/drm/amd/display/dmub/inc/dmub_types.h | 64 +++
+ drivers/gpu/drm/amd/display/dmub/src/Makefile | 29 +
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 137 +++++
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 62 +++
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 126 +++++
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 45 ++
+ .../gpu/drm/amd/display/dmub/src/dmub_reg.c | 109 ++++
+ .../gpu/drm/amd/display/dmub/src/dmub_reg.h | 120 +++++
+ .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 415 ++++++++++++++
+ 15 files changed, 2062 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/Makefile
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index 9eae7c67ceb5..d9ee189aebf0 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -29,6 +29,7 @@ config DRM_AMD_DC_DCN2_1
+ bool "DCN 2.1 family"
+ depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC_DCN2_0
++ select DRM_AMD_DC_DMUB
+ help
+ Choose this option if you want to have
+ Renoir support for display engine
+@@ -51,6 +52,11 @@ config DRM_AMD_DC_HDCP
+ if you want to support
+ HDCP authentication
+
++config DRM_AMD_DC_DMUB
++ def_bool n
++ help
++ DMUB support for display engine
++
+ config DEBUG_KERNEL_DC
+ bool "Enable kgdb break in DC"
+ depends on DRM_AMD_DC
+diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
+index 36b3d6a5d04d..3c7332be4a89 100644
+--- a/drivers/gpu/drm/amd/display/Makefile
++++ b/drivers/gpu/drm/amd/display/Makefile
+@@ -38,6 +38,10 @@ ifdef CONFIG_DRM_AMD_DC_HDCP
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
+ endif
+
++ifdef CONFIG_DRM_AMD_DC_DMUB
++subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
++endif
++
+ #TODO: remove when Timing Sync feature is complete
+ subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
+
+@@ -47,6 +51,10 @@ ifdef CONFIG_DRM_AMD_DC_HDCP
+ DAL_LIBS += modules/hdcp
+ endif
+
++ifdef CONFIG_DRM_AMD_DC_DMUB
++DAL_LIBS += dmub/src
++endif
++
+ AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
+
+ include $(AMD_DAL)
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+new file mode 100644
+index 000000000000..b25f92e3280d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+@@ -0,0 +1,256 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_CMD_H_
++#define _DMUB_CMD_H_
++
++#include "dmub_types.h"
++#include "atomfirmware.h"
++
++#define DMUB_RB_CMD_SIZE 64
++#define DMUB_RB_MAX_ENTRY 128
++#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
++#define REG_SET_MASK 0xFFFF
++
++enum dmub_cmd_type {
++ DMUB_CMD__NULL,
++ DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE,
++ DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ,
++ DMUB_CMD__REG_SEQ_BURST_WRITE,
++ DMUB_CMD__REG_REG_WAIT,
++ DMUB_CMD__DIGX_ENCODER_CONTROL,
++ DMUB_CMD__SET_PIXEL_CLOCK,
++ DMUB_CMD__ENABLE_DISP_POWER_GATING,
++ DMUB_CMD__DPPHY_INIT,
++ DMUB_CMD__DIG1_TRANSMITTER_CONTROL,
++
++ // PSR
++ DMUB_CMD__PSR_ENABLE,
++ DMUB_CMD__PSR_DISABLE,
++ DMUB_CMD__PSR_COPY_SETTINGS,
++ DMUB_CMD__PSR_SET_LEVEL,
++};
++
++#pragma pack(push, 1)
++
++struct dmub_cmd_header {
++ enum dmub_cmd_type type : 8;
++ unsigned int reserved0 : 16;
++ unsigned int payload_bytes : 6; /* up to 60 bytes */
++ unsigned int reserved : 2;
++};
++
++/*
++ * Read modify write
++ *
++ * 60 payload bytes can hold up to 5 sets of read modify writes,
++ * each take 3 dwords.
++ *
++ * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
++ *
++ * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
++ * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
++ */
++struct dmub_cmd_read_modify_write_sequence {
++ uint32_t addr;
++ uint32_t modify_mask;
++ uint32_t modify_value;
++};
++
++#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
++struct dmub_rb_cmd_read_modify_write {
++ struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
++ struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
++};
++
++/*
++ * Update a register with specified masks and values sequeunce
++ *
++ * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
++ *
++ * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
++ *
++ *
++ * USE CASE:
++ * 1. auto-increment register where additional read would update pointer and produce wrong result
++ * 2. toggle a bit without read in the middle
++ */
++
++struct dmub_cmd_reg_field_update_sequence {
++ uint32_t modify_mask; // 0xffff'ffff to skip initial read
++ uint32_t modify_value;
++};
++
++#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
++
++struct dmub_rb_cmd_reg_field_update_sequence {
++ struct dmub_cmd_header header;
++ uint32_t addr;
++ struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
++};
++
++
++/*
++ * Burst write
++ *
++ * support use case such as writing out LUTs.
++ *
++ * 60 payload bytes can hold up to 14 values to write to given address
++ *
++ * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
++ */
++#define DMUB_BURST_WRITE_VALUES__MAX 14
++struct dmub_rb_cmd_burst_write {
++ struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE
++ uint32_t addr;
++ uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
++};
++
++
++struct dmub_rb_cmd_common {
++ struct dmub_cmd_header header;
++ uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
++};
++
++struct dmub_cmd_reg_wait_data {
++ uint32_t addr;
++ uint32_t mask;
++ uint32_t condition_field_value;
++ uint32_t time_out_us;
++};
++
++struct dmub_rb_cmd_reg_wait {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_reg_wait_data reg_wait;
++};
++
++struct dmub_cmd_digx_encoder_control_data {
++ union dig_encoder_control_parameters_v1_5 dig;
++};
++
++struct dmub_rb_cmd_digx_encoder_control {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_digx_encoder_control_data encoder_control;
++};
++
++struct dmub_cmd_set_pixel_clock_data {
++ struct set_pixel_clock_parameter_v1_7 clk;
++};
++
++struct dmub_rb_cmd_set_pixel_clock {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_set_pixel_clock_data pixel_clock;
++};
++
++struct dmub_cmd_enable_disp_power_gating_data {
++ struct enable_disp_power_gating_parameters_v2_1 pwr;
++};
++
++struct dmub_rb_cmd_enable_disp_power_gating {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_enable_disp_power_gating_data power_gating;
++};
++
++struct dmub_cmd_dig1_transmitter_control_data {
++ struct dig_transmitter_control_parameters_v1_6 dig;
++};
++
++struct dmub_rb_cmd_dig1_transmitter_control {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_dig1_transmitter_control_data transmitter_control;
++};
++
++struct dmub_rb_cmd_dpphy_init {
++ struct dmub_cmd_header header;
++ uint8_t reserved[60];
++};
++
++struct dmub_cmd_psr_copy_settings_data {
++ uint32_t reg1;
++ uint32_t reg2;
++ uint32_t reg3;
++};
++
++struct dmub_rb_cmd_psr_copy_settings {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
++};
++
++struct dmub_cmd_psr_set_level_data {
++ uint16_t psr_level;
++};
++
++struct dmub_rb_cmd_psr_set_level {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_psr_set_level_data psr_set_level_data;
++};
++
++struct dmub_rb_cmd_psr_disable {
++ struct dmub_cmd_header header;
++};
++
++struct dmub_rb_cmd_psr_enable {
++ struct dmub_cmd_header header;
++};
++
++struct dmub_cmd_psr_notify_vblank_data {
++ uint32_t vblank_int; // Which vblank interrupt was triggered
++};
++
++struct dmub_rb_cmd_notify_vblank {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_psr_notify_vblank_data psr_notify_vblank_data;
++};
++
++struct dmub_cmd_psr_notify_static_state_data {
++ uint32_t ss_int; // Which static screen interrupt was triggered
++ uint32_t ss_enter; // Enter (1) or exit (0) static screen
++};
++
++struct dmub_rb_cmd_psr_notify_static_state {
++ struct dmub_cmd_header header;
++ struct dmub_cmd_psr_notify_static_state_data psr_notify_static_state_data;
++};
++
++union dmub_rb_cmd {
++ struct dmub_rb_cmd_read_modify_write read_modify_write;
++ struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
++ struct dmub_rb_cmd_burst_write burst_write;
++ struct dmub_rb_cmd_reg_wait reg_wait;
++ struct dmub_rb_cmd_common cmd_common;
++ struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
++ struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
++ struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
++ struct dmub_rb_cmd_dpphy_init dpphy_init;
++ struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
++ struct dmub_rb_cmd_psr_enable psr_enable;
++ struct dmub_rb_cmd_psr_disable psr_disable;
++ struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
++ struct dmub_rb_cmd_psr_set_level psr_set_level;
++};
++
++#pragma pack(pop)
++
++#endif /* _DMUB_CMD_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h
+new file mode 100644
+index 000000000000..ac22744eaa94
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h
+@@ -0,0 +1,129 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_RB_H_
++#define _DMUB_RB_H_
++
++#include "dmub_types.h"
++#include "dmub_cmd.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++struct dmub_cmd_header;
++
++struct dmub_rb_init_params {
++ void *ctx;
++ void *base_address;
++ uint32_t capacity;
++};
++
++struct dmub_rb {
++ void *base_address;
++ uint32_t data_count;
++ uint32_t rptr;
++ uint32_t wrpt;
++ uint32_t capacity;
++
++ void *ctx;
++ void *dmub;
++};
++
++
++static inline bool dmub_rb_empty(struct dmub_rb *rb)
++{
++ return (rb->wrpt == rb->rptr);
++}
++
++static inline bool dmub_rb_full(struct dmub_rb *rb)
++{
++ uint32_t data_count;
++
++ if (rb->wrpt >= rb->rptr)
++ data_count = rb->wrpt - rb->rptr;
++ else
++ data_count = rb->capacity - (rb->rptr - rb->wrpt);
++
++ return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
++}
++
++static inline bool dmub_rb_push_front(struct dmub_rb *rb,
++ const struct dmub_cmd_header *cmd)
++{
++ uint8_t *wt_ptr = (uint8_t *)(rb->base_address) + rb->wrpt;
++
++ if (dmub_rb_full(rb))
++ return false;
++
++ dmub_memcpy(wt_ptr, cmd, DMUB_RB_CMD_SIZE);
++ rb->wrpt += DMUB_RB_CMD_SIZE;
++
++ if (rb->wrpt >= rb->capacity)
++ rb->wrpt %= rb->capacity;
++
++ return true;
++}
++
++static inline bool dmub_rb_front(struct dmub_rb *rb,
++ struct dmub_cmd_header *cmd)
++{
++ uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr;
++
++ if (dmub_rb_empty(rb))
++ return false;
++
++ dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
++
++ return true;
++}
++
++static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
++{
++ if (dmub_rb_empty(rb))
++ return false;
++
++ rb->rptr += DMUB_RB_CMD_SIZE;
++
++ if (rb->rptr >= rb->capacity)
++ rb->rptr %= rb->capacity;
++
++ return true;
++}
++
++static inline void dmub_rb_init(struct dmub_rb *rb,
++ struct dmub_rb_init_params *init_params)
++{
++ rb->base_address = init_params->base_address;
++ rb->capacity = init_params->capacity;
++ rb->rptr = 0;
++ rb->wrpt = 0;
++}
++
++#if defined(__cplusplus)
++}
++#endif
++
++#endif /* _DMUB_RB_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+new file mode 100644
+index 000000000000..aa8f0396616d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -0,0 +1,505 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_SRV_H_
++#define _DMUB_SRV_H_
++
++/**
++ * DOC: DMUB interface and operation
++ *
++ * DMUB is the interface to the display DMCUB microcontroller on DCN hardware.
++ * It delegates hardware initialization and command submission to the
++ * microcontroller. DMUB is the shortname for DMCUB.
++ *
++ * This interface is not thread-safe. Ensure that all access to the interface
++ * is properly synchronized by the caller.
++ *
++ * Initialization and usage of the DMUB service should be done in the
++ * steps given below:
++ *
++ * 1. dmub_srv_create()
++ * 2. dmub_srv_has_hw_support()
++ * 3. dmub_srv_calc_region_info()
++ * 4. dmub_srv_hw_init()
++ *
++ * The call to dmub_srv_create() is required to use the server.
++ *
++ * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info()
++ * are helpers to query cache window size and allocate framebuffer(s)
++ * for the cache windows.
++ *
++ * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare
++ * for command submission. Commands can be queued via dmub_srv_cmd_queue()
++ * and executed via dmub_srv_cmd_execute().
++ *
++ * If the queue is full the dmub_srv_wait_for_idle() call can be used to
++ * wait until the queue has been cleared.
++ *
++ * Destroying the DMUB service can be done by calling dmub_srv_destroy().
++ * This does not clear DMUB hardware state, only software state.
++ *
++ * The interface is intended to be standalone and should not depend on any
++ * other component within DAL.
++ */
++
++#include "dmub_types.h"
++#include "dmub_cmd.h"
++#include "dmub_rb.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++/* Forward declarations */
++struct dmub_srv;
++struct dmub_cmd_header;
++struct dmcu;
++
++/* enum dmub_status - return code for dmcub functions */
++enum dmub_status {
++ DMUB_STATUS_OK = 0,
++ DMUB_STATUS_NO_CTX,
++ DMUB_STATUS_QUEUE_FULL,
++ DMUB_STATUS_TIMEOUT,
++ DMUB_STATUS_INVALID,
++};
++
++/* enum dmub_asic - dmub asic identifier */
++enum dmub_asic {
++ DMUB_ASIC_NONE = 0,
++ DMUB_ASIC_DCN20,
++ DMUB_ASIC_DCN21,
++ DMUB_ASIC_MAX,
++};
++
++/* enum dmub_window_id - dmub window identifier */
++enum dmub_window_id {
++ DMUB_WINDOW_0_INST_CONST = 0,
++ DMUB_WINDOW_1_STACK,
++ DMUB_WINDOW_2_BSS_DATA,
++ DMUB_WINDOW_3_VBIOS,
++ DMUB_WINDOW_4_MAILBOX,
++ DMUB_WINDOW_5_TRACEBUFF,
++ DMUB_WINDOW_6_RESERVED,
++ DMUB_WINDOW_7_RESERVED,
++ DMUB_WINDOW_TOTAL,
++};
++
++/**
++ * struct dmub_region - dmub hw memory region
++ * @base: base address for region, must be 256 byte aligned
++ * @top: top address for region
++ */
++struct dmub_region {
++ uint32_t base;
++ uint32_t top;
++};
++
++/**
++ * struct dmub_window - dmub hw cache window
++ * @off: offset to the fb memory in gpu address space
++ * @r: region in uc address space for cache window
++ */
++struct dmub_window {
++ union dmub_addr offset;
++ struct dmub_region region;
++};
++
++/**
++ * struct dmub_fb - defines a dmub framebuffer memory region
++ * @cpu_addr: cpu virtual address for the region, NULL if invalid
++ * @gpu_addr: gpu virtual address for the region, NULL if invalid
++ * @size: size of the region in bytes, zero if invalid
++ */
++struct dmub_fb {
++ void *cpu_addr;
++ uint64_t gpu_addr;
++ uint32_t size;
++};
++
++/**
++ * struct dmub_srv_region_params - params used for calculating dmub regions
++ * @inst_const_size: size of the fw inst const section
++ * @bss_data_size: size of the fw bss data section
++ * @vbios_size: size of the vbios data
++ */
++struct dmub_srv_region_params {
++ uint32_t inst_const_size;
++ uint32_t bss_data_size;
++ uint32_t vbios_size;
++};
++
++/**
++ * struct dmub_srv_region_info - output region info from the dmub service
++ * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes
++ * @num_regions: number of regions used by the dmub service
++ * @regions: region info
++ *
++ * The regions are aligned such that they can be all placed within the
++ * same framebuffer but they can also be placed into different framebuffers.
++ *
++ * The size of each region can be calculated by the caller:
++ * size = reg.top - reg.base
++ *
++ * Care must be taken when performing custom allocations to ensure that each
++ * region base address is 256 byte aligned.
++ */
++struct dmub_srv_region_info {
++ uint32_t fb_size;
++ uint8_t num_regions;
++ struct dmub_region regions[DMUB_WINDOW_TOTAL];
++};
++
++/**
++ * struct dmub_srv_fb_params - parameters used for driver fb setup
++ * @region_info: region info calculated by dmub service
++ * @cpu_addr: base cpu address for the framebuffer
++ * @gpu_addr: base gpu virtual address for the framebuffer
++ */
++struct dmub_srv_fb_params {
++ const struct dmub_srv_region_info *region_info;
++ void *cpu_addr;
++ uint64_t gpu_addr;
++};
++
++/**
++ * struct dmub_srv_fb_info - output fb info from the dmub service
++ * @num_fbs: number of required dmub framebuffers
++ * @fbs: fb data for each region
++ *
++ * Output from the dmub service helper that can be used by the
++ * driver to prepare dmub_fb that can be passed into the dmub
++ * hw init service.
++ *
++ * Assumes that all regions are within the same framebuffer
++ * and have been setup according to the region_info generated
++ * by the dmub service.
++ */
++struct dmub_srv_fb_info {
++ uint8_t num_fb;
++ struct dmub_fb fb[DMUB_WINDOW_TOTAL];
++};
++
++/**
++ * struct dmub_srv_base_funcs - Driver specific base callbacks
++ */
++struct dmub_srv_base_funcs {
++ /**
++ * @reg_read:
++ *
++ * Hook for reading a register.
++ *
++ * Return: The 32-bit register value from the given address.
++ */
++ uint32_t (*reg_read)(void *ctx, uint32_t address);
++
++ /**
++ * @reg_write:
++ *
++ * Hook for writing a value to the register specified by address.
++ */
++ void (*reg_write)(void *ctx, uint32_t address, uint32_t value);
++};
++
++/**
++ * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub
++ */
++struct dmub_srv_hw_funcs {
++ /* private: internal use only */
++
++ void (*reset)(struct dmub_srv *dmub);
++
++ void (*reset_release)(struct dmub_srv *dmub);
++
++ void (*backdoor_load)(struct dmub_srv *dmub,
++ const struct dmub_window *cw0,
++ const struct dmub_window *cw1);
++
++ void (*setup_windows)(struct dmub_srv *dmub,
++ const struct dmub_window *cw2,
++ const struct dmub_window *cw3,
++ const struct dmub_window *cw4,
++ const struct dmub_window *cw5);
++
++ void (*setup_mailbox)(struct dmub_srv *dmub,
++ const struct dmub_region *inbox1);
++
++ uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);
++
++ void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
++
++ bool (*is_supported)(struct dmub_srv *dmub);
++
++ bool (*is_phy_init)(struct dmub_srv *dmub);
++
++ bool (*is_auto_load_done)(struct dmub_srv *dmub);
++};
++
++/**
++ * struct dmub_srv_create_params - params for dmub service creation
++ * @base_funcs: driver supplied base routines
++ * @hw_funcs: optional overrides for hw funcs
++ * @user_ctx: context data for callback funcs
++ * @asic: driver supplied asic
++ * @is_virtual: false for hw support only
++ */
++struct dmub_srv_create_params {
++ struct dmub_srv_base_funcs funcs;
++ struct dmub_srv_hw_funcs *hw_funcs;
++ void *user_ctx;
++ enum dmub_asic asic;
++ bool is_virtual;
++};
++
++/*
++ * struct dmub_srv_hw_params - params for dmub hardware initialization
++ * @fb: framebuffer info for each region
++ * @fb_base: base of the framebuffer aperture
++ * @fb_offset: offset of the framebuffer aperture
++ * @psp_version: psp version to pass for DMCU init
++ */
++struct dmub_srv_hw_params {
++ struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
++ uint64_t fb_base;
++ uint64_t fb_offset;
++ uint32_t psp_version;
++};
++
++/**
++ * struct dmub_srv - software state for dmcub
++ * @asic: dmub asic identifier
++ * @user_ctx: user provided context for the dmub_srv
++ * @is_virtual: false if hardware support only
++ */
++struct dmub_srv {
++ enum dmub_asic asic;
++ void *user_ctx;
++ bool is_virtual;
++
++ /* private: internal use only */
++ struct dmub_srv_base_funcs funcs;
++ struct dmub_srv_hw_funcs hw_funcs;
++ struct dmub_rb inbox1_rb;
++
++ bool sw_init;
++ bool hw_init;
++
++ uint64_t fb_base;
++ uint64_t fb_offset;
++ uint32_t psp_version;
++};
++
++/**
++ * dmub_srv_create() - creates the DMUB service.
++ * @dmub: the dmub service
++ * @params: creation parameters for the service
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
++ const struct dmub_srv_create_params *params);
++
++/**
++ * dmub_srv_destroy() - destroys the DMUB service.
++ * @dmub: the dmub service
++ */
++void dmub_srv_destroy(struct dmub_srv *dmub);
++
++/**
++ * dmub_srv_calc_region_info() - retreives region info from the dmub service
++ * @dmub: the dmub service
++ * @params: parameters used to calculate region locations
++ * @info_out: the output region info from dmub
++ *
++ * Calculates the base and top address for all relevant dmub regions
++ * using the parameters given (if any).
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status
++dmub_srv_calc_region_info(struct dmub_srv *dmub,
++ const struct dmub_srv_region_params *params,
++ struct dmub_srv_region_info *out);
++
++/**
++ * dmub_srv_calc_region_info() - retreives fb info from the dmub service
++ * @dmub: the dmub service
++ * @params: parameters used to calculate fb locations
++ * @info_out: the output fb info from dmub
++ *
++ * Calculates the base and top address for all relevant dmub regions
++ * using the parameters given (if any).
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
++ const struct dmub_srv_fb_params *params,
++ struct dmub_srv_fb_info *out);
++
++/**
++ * dmub_srv_has_hw_support() - returns hw support state for dmcub
++ * @dmub: the dmub service
++ * @is_supported: hw support state
++ *
++ * Queries the hardware for DMCUB support and returns the result.
++ *
++ * Can be called before dmub_srv_hw_init().
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
++ bool *is_supported);
++
++/**
++ * dmub_srv_hw_init() - initializes the underlying DMUB hardware
++ * @dmub: the dmub service
++ * @params: params for hardware initialization
++ *
++ * Resets the DMUB hardware and performs backdoor loading of the
++ * required cache regions based on the input framebuffer regions.
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_NO_CTX - dmcub context not initialized
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
++ const struct dmub_srv_hw_params *params);
++
++/**
++ * dmub_srv_cmd_queue() - queues a command to the DMUB
++ * @dmub: the dmub service
++ * @cmd: the command to queue
++ *
++ * Queues a command to the DMUB service but does not begin execution
++ * immediately.
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_QUEUE_FULL - no remaining room in queue
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
++ const struct dmub_cmd_header *cmd);
++
++/**
++ * dmub_srv_cmd_execute() - Executes a queued sequence to the dmub
++ * @dmub: the dmub service
++ *
++ * Begins exeuction of queued commands on the dmub.
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub);
++
++/**
++ * dmub_srv_cmd_submit() - submits a command to the DMUB immediately
++ * @dmub: the dmub service
++ * @cmd: the command to submit
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Submits a command to the DMUB with an optional timeout.
++ * If timeout_us is given then the service will attempt to
++ * resubmit for the given number of microseconds.
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_TIMEOUT - wait for submit timed out
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_cmd_submit(struct dmub_srv *dmub,
++ const struct dmub_cmd_header *cmd,
++ uint32_t timeout_us);
++
++/**
++ * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete
++ * @dmub: the dmub service
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Waits until firmware has been autoloaded by the DMCUB. The maximum
++ * wait time is given in microseconds to prevent spinning forever.
++ *
++ * On ASICs without firmware autoload support this function will return
++ * immediately.
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_TIMEOUT - wait for phy init timed out
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
++ uint32_t timeout_us);
++
++/**
++ * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete
++ * @dmub: the dmub service
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Waits until the PHY has been initialized by the DMUB. The maximum
++ * wait time is given in microseconds to prevent spinning forever.
++ *
++ * On ASICs without PHY init support this function will return
++ * immediately.
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_TIMEOUT - wait for phy init timed out
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
++ uint32_t timeout_us);
++
++/**
++ * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle
++ * @dmub: the dmub service
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Waits until the DMUB buffer is empty and all commands have
++ * finished processing. The maximum wait time is given in
++ * microseconds to prevent spinning forever.
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
++ uint32_t timeout_us);
++
++#if defined(__cplusplus)
++}
++#endif
++
++#endif /* _DMUB_SRV_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+new file mode 100644
+index 000000000000..9707706ba8ce
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#ifndef _DMUB_TRACE_BUFFER_H_
++#define _DMUB_TRACE_BUFFER_H_
++
++#include "dmub_types.h"
++
++#define LOAD_DMCU_FW 1
++#define LOAD_PHY_FW 2
++
++struct dmcub_trace_buf_entry {
++ uint32_t trace_code;
++ uint32_t tick_count;
++ uint32_t param0;
++ uint32_t param1;
++};
++
++#define TRACE_BUF_SIZE (1024) //1 kB
++#define PERF_TRACE_MAX_ENTRY ((TRACE_BUF_SIZE - 8)/sizeof(struct dmcub_trace_buf_entry))
++
++struct dmcub_trace_buf {
++ uint32_t entry_count;
++ uint32_t clk_freq;
++ struct dmcub_trace_buf_entry entries[PERF_TRACE_MAX_ENTRY];
++};
++
++
++
++#endif /* _DMUB_TRACE_BUFFER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
+new file mode 100644
+index 000000000000..41d524b0db2f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
+@@ -0,0 +1,64 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_TYPES_H_
++#define _DMUB_TYPES_H_
++
++/* Basic type definitions. */
++#include <asm/byteorder.h>
++#include <linux/types.h>
++#include <linux/string.h>
++#include <linux/delay.h>
++#include <stdarg.h>
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++#ifndef dmub_memcpy
++#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
++#endif
++
++#ifndef dmub_memset
++#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
++#endif
++
++#ifndef dmub_udelay
++#define dmub_udelay(microseconds) udelay(microseconds)
++#endif
++
++union dmub_addr {
++ struct {
++ uint32_t low_part;
++ uint32_t high_part;
++ } u;
++ uint64_t quad_part;
++};
++
++#if defined(__cplusplus)
++}
++#endif
++
++#endif /* _DMUB_TYPES_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+new file mode 100644
+index 000000000000..f3b844f474fd
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+@@ -0,0 +1,29 @@
++#
++# Copyright 2019 Advanced Micro Devices, Inc.
++#
++# Permission is hereby granted, free of charge, to any person obtaining a
++# copy of this software and associated documentation files (the "Software"),
++# to deal in the Software without restriction, including without limitation
++# the rights to use, copy, modify, merge, publish, distribute, sublicense,
++# and/or sell copies of the Software, and to permit persons to whom the
++# Software is furnished to do so, subject to the following conditions:
++#
++# The above copyright notice and this permission notice shall be included in
++# all copies or substantial portions of the Software.
++#
++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++# OTHER DEALINGS IN THE SOFTWARE.
++#
++
++ifdef CONFIG_DRM_AMD_DC_DMUB
++DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
++
++AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_DMUB)
++endif
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+new file mode 100644
+index 000000000000..236a4156bbe1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -0,0 +1,137 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../inc/dmub_srv.h"
++#include "dmub_reg.h"
++
++#include "dcn/dcn_2_0_0_offset.h"
++#include "dcn/dcn_2_0_0_sh_mask.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
++
++#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
++#define CTX dmub
++
++void dmub_dcn20_reset(struct dmub_srv *dmub)
++{
++ REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
++ REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
++}
++
++void dmub_dcn20_reset_release(struct dmub_srv *dmub)
++{
++ REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
++ REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
++ REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
++}
++
++void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, struct dmub_window *cw0,
++ struct dmub_window *cw1)
++{
++ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
++ REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4,
++ DMCUB_MEM_WRITE_SPACE, 0x4);
++
++ REG_WRITE(DMCUB_REGION3_CW0_OFFSET, cw0->offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, cw0->offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
++ REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
++ DMCUB_REGION3_CW0_ENABLE, 1);
++
++ REG_WRITE(DMCUB_REGION3_CW1_OFFSET, cw1->offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, cw1->offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
++ REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
++ DMCUB_REGION3_CW1_ENABLE, 1);
++
++ REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
++ 0x20);
++}
++
++void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
++ const struct dmub_window *cw2,
++ const struct dmub_window *cw3,
++ const struct dmub_window *cw4,
++ const struct dmub_window *cw5)
++{
++ REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
++ REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
++ DMCUB_REGION3_CW2_ENABLE, 1);
++
++ REG_WRITE(DMCUB_REGION3_CW3_OFFSET, cw3->offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, cw3->offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
++ REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
++ DMCUB_REGION3_CW3_ENABLE, 1);
++
++ /* TODO: Move this to CW4. */
++
++ REG_WRITE(DMCUB_REGION4_OFFSET, cw4->offset.u.low_part);
++ REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, cw4->offset.u.high_part);
++ REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
++ cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
++ 1);
++}
++
++void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
++ const struct dmub_region *inbox1)
++{
++ /* TODO: Use CW4 instead of region 4. */
++
++ REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
++ REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
++ REG_WRITE(DMCUB_INBOX1_RPTR, 0);
++ REG_WRITE(DMCUB_INBOX1_WPTR, 0);
++}
++
++uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
++{
++ return REG_READ(DMCUB_INBOX1_RPTR);
++}
++
++void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
++{
++ REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
++}
++
++bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
++{
++ uint32_t supported = 0;
++
++ REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
++
++ return supported;
++}
++
++bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub)
++{
++ return REG_READ(DMCUB_SCRATCH10) != 0;
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+new file mode 100644
+index 000000000000..41269da40363
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -0,0 +1,62 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_DCN20_H_
++#define _DMUB_DCN20_H_
++
++#include "../inc/dmub_types.h"
++
++struct dmub_srv;
++
++/* Hardware functions. */
++
++void dmub_dcn20_init(struct dmub_srv *dmub);
++
++void dmub_dcn20_reset(struct dmub_srv *dmub);
++
++void dmub_dcn20_reset_release(struct dmub_srv *dmub);
++
++void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
++ const struct dmub_window *cw0,
++ const struct dmub_window *cw1);
++
++void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
++ const struct dmub_window *cw2,
++ const struct dmub_window *cw3,
++ const struct dmub_window *cw4,
++ const struct dmub_window *cw5);
++
++void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
++ const struct dmub_region *inbox1);
++
++uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);
++
++void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
++
++bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
++
++bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub);
++
++#endif /* _DMUB_DCN20_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+new file mode 100644
+index 000000000000..d40a808112e7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+@@ -0,0 +1,126 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../inc/dmub_srv.h"
++#include "dmub_reg.h"
++
++#include "dcn/dcn_2_1_0_offset.h"
++#include "dcn/dcn_2_1_0_sh_mask.h"
++#include "renoir_ip_offset.h"
++
++#define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg
++#define CTX dmub
++
++static inline void dmub_dcn21_translate_addr(const union dmub_addr *addr_in,
++ uint64_t fb_base,
++ uint64_t fb_offset,
++ union dmub_addr *addr_out)
++{
++ addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
++}
++
++void dmub_dcn21_backdoor_load(struct dmub_srv *dmub,
++ const struct dmub_window *cw0,
++ const struct dmub_window *cw1)
++{
++ union dmub_addr offset;
++ uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
++
++ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
++ REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
++ DMCUB_MEM_WRITE_SPACE, 0x3);
++
++ dmub_dcn21_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
++
++ REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
++ REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
++ DMCUB_REGION3_CW0_ENABLE, 1);
++
++ dmub_dcn21_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
++
++ REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
++ REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
++ DMCUB_REGION3_CW1_ENABLE, 1);
++
++ REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
++ 0x20);
++}
++
++void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
++ const struct dmub_window *cw2,
++ const struct dmub_window *cw3,
++ const struct dmub_window *cw4,
++ const struct dmub_window *cw5)
++{
++ union dmub_addr offset;
++ uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
++
++ dmub_dcn21_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
++
++ REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
++ REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
++ DMCUB_REGION3_CW2_ENABLE, 1);
++
++ dmub_dcn21_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
++
++ REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
++ REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
++ DMCUB_REGION3_CW3_ENABLE, 1);
++
++ /* TODO: Move this to CW4. */
++ dmub_dcn21_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
++
++ REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
++ REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
++ REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
++ cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
++ 1);
++
++ dmub_dcn21_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
++
++ REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
++ REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
++ DMCUB_REGION3_CW5_ENABLE, 1);
++}
++
++bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
++{
++ return (REG_READ(DMCUB_SCRATCH0) == 3);
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+new file mode 100644
+index 000000000000..f57969d8d56f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+@@ -0,0 +1,45 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_DCN21_H_
++#define _DMUB_DCN21_H_
++
++#include "dmub_dcn20.h"
++
++/* Hardware functions. */
++
++void dmub_dcn21_backdoor_load(struct dmub_srv *dmub,
++ const struct dmub_window *cw0,
++ const struct dmub_window *cw1);
++
++void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
++ const struct dmub_window *cw2,
++ const struct dmub_window *cw3,
++ const struct dmub_window *cw4,
++ const struct dmub_window *cw5);
++
++bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
++
++#endif /* _DMUB_DCN21_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
+new file mode 100644
+index 000000000000..4094eca212f0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
+@@ -0,0 +1,109 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dmub_reg.h"
++#include "../inc/dmub_srv.h"
++
++struct dmub_reg_value_masks {
++ uint32_t value;
++ uint32_t mask;
++};
++
++static inline void
++set_reg_field_value_masks(struct dmub_reg_value_masks *field_value_mask,
++ uint32_t value, uint32_t mask, uint8_t shift)
++{
++ field_value_mask->value =
++ (field_value_mask->value & ~mask) | (mask & (value << shift));
++ field_value_mask->mask = field_value_mask->mask | mask;
++}
++
++static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask,
++ uint32_t addr, int n, uint8_t shift1,
++ uint32_t mask1, uint32_t field_value1,
++ va_list ap)
++{
++ uint32_t shift, mask, field_value;
++ int i = 1;
++
++ /* gather all bits value/mask getting updated in this register */
++ set_reg_field_value_masks(field_value_mask, field_value1, mask1,
++ shift1);
++
++ while (i < n) {
++ shift = va_arg(ap, uint32_t);
++ mask = va_arg(ap, uint32_t);
++ field_value = va_arg(ap, uint32_t);
++
++ set_reg_field_value_masks(field_value_mask, field_value, mask,
++ shift);
++ i++;
++ }
++}
++
++static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask,
++ uint8_t shift)
++{
++ return (mask & reg_value) >> shift;
++}
++
++void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,
++ uint32_t mask1, uint32_t field_value1, ...)
++{
++ struct dmub_reg_value_masks field_value_mask = { 0 };
++ uint32_t reg_val;
++ va_list ap;
++
++ va_start(ap, field_value1);
++ set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
++ field_value1, ap);
++ va_end(ap);
++
++ reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
++ reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
++ srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
++}
++
++void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,
++ uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...)
++{
++ struct dmub_reg_value_masks field_value_mask = { 0 };
++ va_list ap;
++
++ va_start(ap, field_value1);
++ set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
++ field_value1, ap);
++ va_end(ap);
++
++ reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
++ srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
++}
++
++void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,
++ uint32_t mask, uint32_t *field_value)
++{
++ uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
++ *field_value = get_reg_field_value_ex(reg_val, mask, shift);
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
+new file mode 100644
+index 000000000000..bac4ee8f745f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
+@@ -0,0 +1,120 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_REG_H_
++#define _DMUB_REG_H_
++
++#include "../inc/dmub_types.h"
++
++struct dmub_srv;
++
++/* Register offset and field lookup. */
++
++#define BASE(seg) BASE_INNER(seg)
++
++#define REG_OFFSET(base_index, addr) (BASE(base_index) + addr)
++
++#define REG(reg_name) REG_OFFSET(mm ## reg_name ## _BASE_IDX, mm ## reg_name)
++
++#define FD(reg_field) reg_field ## __SHIFT, reg_field ## _MASK
++
++#define FN(reg_name, field) FD(reg_name##__##field)
++
++/* Register reads and writes. */
++
++#define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
++
++#define REG_WRITE(reg, val) \
++ ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
++
++/* Register field setting. */
++
++#define REG_SET_N(reg_name, n, initial_val, ...) \
++ dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
++
++#define REG_SET(reg_name, initial_val, field, val) \
++ REG_SET_N(reg_name, 1, initial_val, \
++ FN(reg_name, field), val)
++
++#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
++ REG_SET_N(reg, 2, init_value, \
++ FN(reg, f1), v1, \
++ FN(reg, f2), v2)
++
++#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
++ REG_SET_N(reg, 3, init_value, \
++ FN(reg, f1), v1, \
++ FN(reg, f2), v2, \
++ FN(reg, f3), v3)
++
++#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
++ REG_SET_N(reg, 4, init_value, \
++ FN(reg, f1), v1, \
++ FN(reg, f2), v2, \
++ FN(reg, f3), v3, \
++ FN(reg, f4), v4)
++
++/* Register field updating. */
++
++#define REG_UPDATE_N(reg_name, n, ...)\
++ dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
++
++#define REG_UPDATE(reg_name, field, val) \
++ REG_UPDATE_N(reg_name, 1, \
++ FN(reg_name, field), val)
++
++#define REG_UPDATE_2(reg, f1, v1, f2, v2) \
++ REG_UPDATE_N(reg, 2,\
++ FN(reg, f1), v1,\
++ FN(reg, f2), v2)
++
++#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
++ REG_UPDATE_N(reg, 3, \
++ FN(reg, f1), v1, \
++ FN(reg, f2), v2, \
++ FN(reg, f3), v3)
++
++#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
++ REG_UPDATE_N(reg, 4, \
++ FN(reg, f1), v1, \
++ FN(reg, f2), v2, \
++ FN(reg, f3), v3, \
++ FN(reg, f4), v4)
++
++/* Register field getting. */
++
++#define REG_GET(reg_name, field, val) \
++ dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
++
++void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,
++ uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
++
++void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,
++ uint32_t mask1, uint32_t field_value1, ...);
++
++void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,
++ uint32_t mask, uint32_t *field_value);
++
++#endif /* _DMUB_REG_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+new file mode 100644
+index 000000000000..229eab7277d1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -0,0 +1,415 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../inc/dmub_srv.h"
++#include "dmub_dcn20.h"
++#include "dmub_dcn21.h"
++/*
++ * Note: the DMUB service is standalone. No additional headers should be
++ * added below or above this line unless they reside within the DMUB
++ * folder.
++ */
++
++/* Alignment for framebuffer memory. */
++#define DMUB_FB_ALIGNMENT (1024 * 1024)
++
++/* Stack size. */
++#define DMUB_STACK_SIZE (128 * 1024)
++
++/* Context size. */
++#define DMUB_CONTEXT_SIZE (512 * 1024)
++
++/* Mailbox size */
++#define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
++
++/* Tracebuffer size */
++#define DMUB_TRACEBUFF_SIZE (1024) //1kB buffer
++
++/* Number of windows in use. */
++#define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1)
++/* Base addresses. */
++
++#define DMUB_CW0_BASE (0x60000000)
++#define DMUB_CW1_BASE (0x61000000)
++#define DMUB_CW5_BASE (0x65000000)
++
++static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
++{
++ return (val + factor - 1) / factor * factor;
++}
++
++static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
++{
++ struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
++
++ switch (asic) {
++ case DMUB_ASIC_DCN20:
++ case DMUB_ASIC_DCN21:
++ funcs->reset = dmub_dcn20_reset;
++ funcs->reset_release = dmub_dcn20_reset_release;
++ funcs->backdoor_load = dmub_dcn20_backdoor_load;
++ funcs->setup_windows = dmub_dcn20_setup_windows;
++ funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
++ funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
++ funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
++ funcs->is_supported = dmub_dcn20_is_supported;
++ funcs->is_phy_init = dmub_dcn20_is_phy_init;
++
++ if (asic == DMUB_ASIC_DCN21) {
++ funcs->backdoor_load = dmub_dcn21_backdoor_load;
++ funcs->setup_windows = dmub_dcn21_setup_windows;
++ funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
++ }
++ break;
++
++ default:
++ return false;
++ }
++
++ return true;
++}
++
++enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
++ const struct dmub_srv_create_params *params)
++{
++ enum dmub_status status = DMUB_STATUS_OK;
++
++ dmub_memset(dmub, 0, sizeof(*dmub));
++
++ dmub->funcs = params->funcs;
++ dmub->user_ctx = params->user_ctx;
++ dmub->asic = params->asic;
++ dmub->is_virtual = params->is_virtual;
++
++ /* Setup asic dependent hardware funcs. */
++ if (!dmub_srv_hw_setup(dmub, params->asic)) {
++ status = DMUB_STATUS_INVALID;
++ goto cleanup;
++ }
++
++ /* Override (some) hardware funcs based on user params. */
++ if (params->hw_funcs) {
++ if (params->hw_funcs->get_inbox1_rptr)
++ dmub->hw_funcs.get_inbox1_rptr =
++ params->hw_funcs->get_inbox1_rptr;
++
++ if (params->hw_funcs->set_inbox1_wptr)
++ dmub->hw_funcs.set_inbox1_wptr =
++ params->hw_funcs->set_inbox1_wptr;
++
++ if (params->hw_funcs->is_supported)
++ dmub->hw_funcs.is_supported =
++ params->hw_funcs->is_supported;
++ }
++
++ /* Sanity checks for required hw func pointers. */
++ if (!dmub->hw_funcs.get_inbox1_rptr ||
++ !dmub->hw_funcs.set_inbox1_wptr) {
++ status = DMUB_STATUS_INVALID;
++ goto cleanup;
++ }
++
++cleanup:
++ if (status == DMUB_STATUS_OK)
++ dmub->sw_init = true;
++ else
++ dmub_srv_destroy(dmub);
++
++ return status;
++}
++
++void dmub_srv_destroy(struct dmub_srv *dmub)
++{
++ dmub_memset(dmub, 0, sizeof(*dmub));
++}
++
++enum dmub_status
++dmub_srv_calc_region_info(struct dmub_srv *dmub,
++ const struct dmub_srv_region_params *params,
++ struct dmub_srv_region_info *out)
++{
++ struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
++ struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
++ struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
++ struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
++ struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
++ struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
++
++ if (!dmub->sw_init)
++ return DMUB_STATUS_INVALID;
++
++ memset(out, 0, sizeof(*out));
++
++ out->num_regions = DMUB_NUM_WINDOWS;
++
++ inst->base = 0x0;
++ inst->top = inst->base + params->inst_const_size;
++
++ data->base = dmub_align(inst->top, 256);
++ data->top = data->base + params->bss_data_size;
++
++ stack->base = dmub_align(data->top, 256);
++ stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
++
++ bios->base = dmub_align(stack->top, 256);
++ bios->top = bios->base + params->vbios_size;
++
++ mail->base = dmub_align(bios->top, 256);
++ mail->top = mail->base + DMUB_MAILBOX_SIZE;
++
++ trace_buff->base = dmub_align(mail->top, 256);
++ trace_buff->top = trace_buff->base + DMUB_TRACEBUFF_SIZE;
++
++ out->fb_size = dmub_align(trace_buff->top, 4096);
++
++ return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
++ const struct dmub_srv_fb_params *params,
++ struct dmub_srv_fb_info *out)
++{
++ uint8_t *cpu_base;
++ uint64_t gpu_base;
++ uint32_t i;
++
++ if (!dmub->sw_init)
++ return DMUB_STATUS_INVALID;
++
++ memset(out, 0, sizeof(*out));
++
++ if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
++ return DMUB_STATUS_INVALID;
++
++ cpu_base = (uint8_t *)params->cpu_addr;
++ gpu_base = params->gpu_addr;
++
++ for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
++ const struct dmub_region *reg =
++ &params->region_info->regions[i];
++
++ out->fb[i].cpu_addr = cpu_base + reg->base;
++ out->fb[i].gpu_addr = gpu_base + reg->base;
++ out->fb[i].size = reg->top - reg->base;
++ }
++
++ out->num_fb = DMUB_NUM_WINDOWS;
++
++ return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
++ bool *is_supported)
++{
++ *is_supported = false;
++
++ if (!dmub->sw_init)
++ return DMUB_STATUS_INVALID;
++
++ if (dmub->hw_funcs.is_supported)
++ *is_supported = dmub->hw_funcs.is_supported(dmub);
++
++ return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
++ const struct dmub_srv_hw_params *params)
++{
++ struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
++ struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
++ struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
++ struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
++ struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
++ struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
++
++ struct dmub_rb_init_params rb_params;
++ struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5;
++ struct dmub_region inbox1;
++
++ if (!dmub->sw_init)
++ return DMUB_STATUS_INVALID;
++
++ dmub->fb_base = params->fb_base;
++ dmub->fb_offset = params->fb_offset;
++ dmub->psp_version = params->psp_version;
++
++ if (inst_fb && data_fb) {
++ cw0.offset.quad_part = inst_fb->gpu_addr;
++ cw0.region.base = DMUB_CW0_BASE;
++ cw0.region.top = cw0.region.base + inst_fb->size - 1;
++
++ cw1.offset.quad_part = stack_fb->gpu_addr;
++ cw1.region.base = DMUB_CW1_BASE;
++ cw1.region.top = cw1.region.base + stack_fb->size - 1;
++
++ if (dmub->hw_funcs.backdoor_load)
++ dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
++ }
++
++ if (dmub->hw_funcs.reset)
++ dmub->hw_funcs.reset(dmub);
++
++ if (inst_fb && data_fb && bios_fb && mail_fb) {
++ cw2.offset.quad_part = data_fb->gpu_addr;
++ cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
++ cw2.region.top = cw2.region.base + data_fb->size;
++
++ cw3.offset.quad_part = bios_fb->gpu_addr;
++ cw3.region.base = DMUB_CW1_BASE + stack_fb->size;
++ cw3.region.top = cw3.region.base + bios_fb->size;
++
++ cw4.offset.quad_part = mail_fb->gpu_addr;
++ cw4.region.base = cw3.region.top + 1;
++ cw4.region.top = cw4.region.base + mail_fb->size;
++
++ inbox1.base = cw4.region.base;
++ inbox1.top = cw4.region.top;
++
++ cw5.offset.quad_part = tracebuff_fb->gpu_addr;
++ cw5.region.base = DMUB_CW5_BASE;
++ cw5.region.top = cw5.region.base + tracebuff_fb->size;
++
++ if (dmub->hw_funcs.setup_windows)
++ dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5);
++
++ if (dmub->hw_funcs.setup_mailbox)
++ dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
++ }
++
++ if (mail_fb) {
++ dmub_memset(&rb_params, 0, sizeof(rb_params));
++ rb_params.ctx = dmub;
++ rb_params.base_address = mail_fb->cpu_addr;
++ rb_params.capacity = DMUB_RB_SIZE;
++
++ dmub_rb_init(&dmub->inbox1_rb, &rb_params);
++ }
++
++ if (dmub->hw_funcs.reset_release)
++ dmub->hw_funcs.reset_release(dmub);
++
++ dmub->hw_init = true;
++
++ return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
++ const struct dmub_cmd_header *cmd)
++{
++ if (!dmub->hw_init)
++ return DMUB_STATUS_INVALID;
++
++ if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
++ return DMUB_STATUS_OK;
++
++ return DMUB_STATUS_QUEUE_FULL;
++}
++
++enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
++{
++ if (!dmub->hw_init)
++ return DMUB_STATUS_INVALID;
++
++ dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
++ return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_cmd_submit(struct dmub_srv *dmub,
++ const struct dmub_cmd_header *cmd,
++ uint32_t timeout_us)
++{
++ uint32_t i = 0;
++
++ if (!dmub->hw_init)
++ return DMUB_STATUS_INVALID;
++
++ for (i = 0; i <= timeout_us; ++i) {
++ dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
++ if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) {
++ dmub->hw_funcs.set_inbox1_wptr(dmub,
++ dmub->inbox1_rb.wrpt);
++ return DMUB_STATUS_OK;
++ }
++
++ udelay(1);
++ }
++
++ return DMUB_STATUS_TIMEOUT;
++}
++
++enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
++ uint32_t timeout_us)
++{
++ uint32_t i;
++
++ if (!dmub->hw_init || !dmub->hw_funcs.is_auto_load_done)
++ return DMUB_STATUS_INVALID;
++
++ for (i = 0; i <= timeout_us; i += 100) {
++ if (dmub->hw_funcs.is_auto_load_done(dmub))
++ return DMUB_STATUS_OK;
++
++ udelay(100);
++ }
++
++ return DMUB_STATUS_TIMEOUT;
++}
++
++enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
++ uint32_t timeout_us)
++{
++ uint32_t i;
++
++ if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
++ return DMUB_STATUS_INVALID;
++
++ for (i = 0; i <= timeout_us; i += 10) {
++ if (dmub->hw_funcs.is_phy_init(dmub))
++ return DMUB_STATUS_OK;
++
++ udelay(10);
++ }
++
++ return DMUB_STATUS_TIMEOUT;
++}
++
++enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
++ uint32_t timeout_us)
++{
++ uint32_t i;
++
++ if (!dmub->hw_init)
++ return DMUB_STATUS_INVALID;
++
++ for (i = 0; i <= timeout_us; ++i) {
++ dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
++ if (dmub_rb_empty(&dmub->inbox1_rb))
++ return DMUB_STATUS_OK;
++
++ udelay(1);
++ }
++
++ return DMUB_STATUS_TIMEOUT;
++}
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4327-drm-amd-display-Change-dmcu-init-sequence-for-dmcub-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4327-drm-amd-display-Change-dmcu-init-sequence-for-dmcub-.patch
new file mode 100644
index 00000000..c644d5b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4327-drm-amd-display-Change-dmcu-init-sequence-for-dmcub-.patch
@@ -0,0 +1,243 @@
+From 803d95182f195a176ca0ac6d7a99baeeace7225d Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Sat, 12 Oct 2019 16:06:19 -0400
+Subject: [PATCH 4327/4736] drm/amd/display: Change dmcu init sequence for
+ dmcub loading dmcu FW.
+
+[Why]
+DMCU isn't intiliazed properly by dmcub loading due to dmcub initialize
+sequence.
+
+[How]
+Change dmcu init sequece to meet dmcub initilize.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 79 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 13 +++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 2 +
+ 5 files changed, 97 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+index f86ad9865a48..66925c8f10d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+@@ -56,6 +56,12 @@
+ #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */
+ #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
+
++// PSP FW version
++#define mmMP0_SMN_C2PMSG_58 0x1607A
++
++//Register access policy version
++#define mmMP0_SMN_C2PMSG_91 0x1609B
++
+ static bool dce_dmcu_init(struct dmcu *dmcu)
+ {
+ // Do nothing
+@@ -370,6 +376,7 @@ static bool dcn10_dmcu_init(struct dmcu *dmcu)
+ const struct dc_config *config = &dmcu->ctx->dc->config;
+ bool status = false;
+
++ PERF_TRACE();
+ /* Definition of DC_DMCU_SCRATCH
+ * 0 : firmare not loaded
+ * 1 : PSP load DMCU FW but not initialized
+@@ -426,9 +433,23 @@ static bool dcn10_dmcu_init(struct dmcu *dmcu)
+ break;
+ }
+
++ PERF_TRACE();
+ return status;
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++static bool dcn21_dmcu_init(struct dmcu *dmcu)
++{
++ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
++ uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);
++
++ if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) {
++ return false;
++ }
++
++ return dcn10_dmcu_init(dmcu);
++}
++#endif
+
+ static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
+ unsigned int start_offset,
+@@ -815,6 +836,21 @@ static const struct dmcu_funcs dcn20_funcs = {
+ };
+ #endif
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++static const struct dmcu_funcs dcn21_funcs = {
++ .dmcu_init = dcn21_dmcu_init,
++ .load_iram = dcn10_dmcu_load_iram,
++ .set_psr_enable = dcn10_dmcu_set_psr_enable,
++ .setup_psr = dcn10_dmcu_setup_psr,
++ .get_psr_state = dcn10_get_dmcu_psr_state,
++ .set_psr_wait_loop = dcn10_psr_wait_loop,
++ .get_psr_wait_loop = dcn10_get_psr_wait_loop,
++ .is_dmcu_initialized = dcn10_is_dmcu_initialized,
++ .lock_phy = dcn20_lock_phy,
++ .unlock_phy = dcn20_unlock_phy
++};
++#endif
++
+ static void dce_dmcu_construct(
+ struct dce_dmcu *dmcu_dce,
+ struct dc_context *ctx,
+@@ -833,6 +869,26 @@ static void dce_dmcu_construct(
+ dmcu_dce->dmcu_mask = dmcu_mask;
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++static void dcn21_dmcu_construct(
++ struct dce_dmcu *dmcu_dce,
++ struct dc_context *ctx,
++ const struct dce_dmcu_registers *regs,
++ const struct dce_dmcu_shift *dmcu_shift,
++ const struct dce_dmcu_mask *dmcu_mask)
++{
++ uint32_t psp_version = 0;
++
++ dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
++
++ if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++ psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
++ dmcu_dce->base.auto_load_dmcu = (psp_version > 0x00110029);
++ dmcu_dce->base.psp_version = psp_version;
++ }
++}
++#endif
++
+ struct dmcu *dce_dmcu_create(
+ struct dc_context *ctx,
+ const struct dce_dmcu_registers *regs,
+@@ -900,6 +956,29 @@ struct dmcu *dcn20_dmcu_create(
+ }
+ #endif
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++struct dmcu *dcn21_dmcu_create(
++ struct dc_context *ctx,
++ const struct dce_dmcu_registers *regs,
++ const struct dce_dmcu_shift *dmcu_shift,
++ const struct dce_dmcu_mask *dmcu_mask)
++{
++ struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
++
++ if (dmcu_dce == NULL) {
++ BREAK_TO_DEBUGGER();
++ return NULL;
++ }
++
++ dcn21_dmcu_construct(
++ dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
++
++ dmcu_dce->base.funcs = &dcn21_funcs;
++
++ return &dmcu_dce->base;
++}
++#endif
++
+ void dce_dmcu_destroy(struct dmcu **dmcu)
+ {
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+index cc8587683b4b..1a42b2cbb21b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+@@ -71,6 +71,10 @@
+ DMCU_COMMON_REG_LIST_DCE_BASE(), \
+ SR(DMU_MEM_PWR_CNTL)
+
++#define DMCU_DCN20_REG_LIST()\
++ DMCU_DCN10_REG_LIST(), \
++ SR(DMCUB_SCRATCH15)
++
+ #define DMCU_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+@@ -175,6 +179,7 @@ struct dce_dmcu_registers {
+ uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
+ uint32_t SMU_INTERRUPT_CONTROL;
+ uint32_t DC_DMCU_SCRATCH;
++ uint32_t DMCUB_SCRATCH15;
+ };
+
+ struct dce_dmcu {
+@@ -269,6 +274,14 @@ struct dmcu *dcn20_dmcu_create(
+ const struct dce_dmcu_mask *dmcu_mask);
+ #endif
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++struct dmcu *dcn21_dmcu_create(
++ struct dc_context *ctx,
++ const struct dce_dmcu_registers *regs,
++ const struct dce_dmcu_shift *dmcu_shift,
++ const struct dce_dmcu_mask *dmcu_mask);
++#endif
++
+ void dce_dmcu_destroy(struct dmcu **dmcu);
+
+ static const uint32_t abm_gain_stepsize = 0x0060;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index b61cc211e659..6d84239af593 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1284,7 +1284,7 @@ static void dcn10_init_hw(struct dc *dc)
+ abm->funcs->abm_init(abm);
+ }
+
+- if (dmcu != NULL)
++ if (dmcu != NULL && !dmcu->auto_load_dmcu)
+ dmcu->funcs->dmcu_init(dmcu);
+
+ if (abm != NULL && dmcu != NULL)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 47367446f64c..0792b1c2e673 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -350,7 +350,7 @@ static const struct bios_registers bios_regs = {
+ };
+
+ static const struct dce_dmcu_registers dmcu_regs = {
+- DMCU_DCN10_REG_LIST()
++ DMCU_DCN20_REG_LIST()
+ };
+
+ static const struct dce_dmcu_shift dmcu_shift = {
+@@ -1748,7 +1748,7 @@ static bool construct(
+ goto create_fail;
+ }
+
+- pool->base.dmcu = dcn20_dmcu_create(ctx,
++ pool->base.dmcu = dcn21_dmcu_create(ctx,
+ &dmcu_regs,
+ &dmcu_shift,
+ &dmcu_mask);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+index c68f0ce346c7..5315f1f86b21 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+@@ -52,6 +52,8 @@ struct dmcu {
+ enum dmcu_state dmcu_state;
+ struct dmcu_version dmcu_version;
+ unsigned int cached_wait_loop_number;
++ uint32_t psp_version;
++ bool auto_load_dmcu;
+ };
+
+ struct dmcu_funcs {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4328-drm-amd-display-Add-PSP-FW-version-mask.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4328-drm-amd-display-Add-PSP-FW-version-mask.patch
new file mode 100644
index 00000000..acba3c0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4328-drm-amd-display-Add-PSP-FW-version-mask.patch
@@ -0,0 +1,39 @@
+From 2261a74af63845b23ae8b85ae95a285de019eedb Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Thu, 17 Oct 2019 21:44:50 -0400
+Subject: [PATCH 4328/4736] drm/amd/display: Add PSP FW version mask.
+
+[Why]
+PSP version format is AB.CD.EF.GH, where CD and GH is the main version.
+current psp version check for dmcub loading dmcu check 0x00110029, in
+case of some psp version eg: 0x00110227 which main version should be
+0x00110027, will result in unexpeceted dmcub loading dmcu FW.
+
+[How]
+Add psp version mask 0x00FF00FF for checking version.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+index 66925c8f10d9..da9a07edcb06 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+@@ -883,7 +883,7 @@ static void dcn21_dmcu_construct(
+
+ if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
+- dmcu_dce->base.auto_load_dmcu = (psp_version > 0x00110029);
++ dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029);
+ dmcu_dce->base.psp_version = psp_version;
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4329-drm-amd-display-Hook-up-the-DMUB-service-in-DM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4329-drm-amd-display-Hook-up-the-DMUB-service-in-DM.patch
new file mode 100644
index 00000000..1fd4fee1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4329-drm-amd-display-Hook-up-the-DMUB-service-in-DM.patch
@@ -0,0 +1,436 @@
+From 99fcf29399a7463d48952b81e2616f6ca5bed1ef Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 24 Oct 2019 20:38:48 -0400
+Subject: [PATCH 4329/4736] drm/amd/display: Hook up the DMUB service in DM
+
+[Why]
+We need DMCUB on Renoir to support DMCU and PHY initialization.
+The DMUB service provides a mechanism to load the DMCUB.
+
+[How]
+Include the DMUB service in amdgpu_dm.
+
+Frontdoor loading of the DMCUB firmware needs to happen via PSP. To
+pass the firmware to PSP we need to hand it off to the firmware list
+in the base driver during software initialization.
+
+Most of the DMUB service can technically be initialized at this point
+in time, but we don't want to be allocating framebuffer memory for
+hardware that doesn't support the DMCUB and in order to check that we
+need to be able to read registers - something DM helpers aren't setup
+to do in software initialization.
+
+So everything but the service creation itself will get deferred to
+hardware initialization.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 270 ++++++++++++++++++
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 50 ++++
+ 2 files changed, 320 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 5a20ce0541c6..e226e526c4df 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -30,6 +30,11 @@
+ #include "dc.h"
+ #include "dc/inc/core_types.h"
+ #include "dal_asic_id.h"
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dmub/inc/dmub_srv.h"
++#include "dc/inc/hw/dmcu.h"
++#include "dc/inc/hw/abm.h"
++#endif
+
+ #include "vid.h"
+ #include "amdgpu.h"
+@@ -84,6 +89,10 @@
+ #include "modules/power/power_helpers.h"
+ #include "modules/inc/mod_info_packet.h"
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
++MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
++#endif
+ #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
+ MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
+
+@@ -665,11 +674,151 @@ void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
+ }
+ }
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static int dm_dmub_hw_init(struct amdgpu_device *adev)
++{
++ const unsigned int psp_header_bytes = 0x100;
++ const unsigned int psp_footer_bytes = 0x100;
++ const struct dmcub_firmware_header_v1_0 *hdr;
++ struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
++ const struct firmware *dmub_fw = adev->dm.dmub_fw;
++ struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
++ struct abm *abm = adev->dm.dc->res_pool->abm;
++ struct dmub_srv_region_params region_params;
++ struct dmub_srv_region_info region_info;
++ struct dmub_srv_fb_params fb_params;
++ struct dmub_srv_fb_info fb_info;
++ struct dmub_srv_hw_params hw_params;
++ enum dmub_status status;
++ const unsigned char *fw_inst_const, *fw_bss_data;
++ uint32_t i;
++ int r;
++ bool has_hw_support;
++
++ if (!dmub_srv)
++ /* DMUB isn't supported on the ASIC. */
++ return 0;
++
++ if (!dmub_fw) {
++ /* Firmware required for DMUB support. */
++ DRM_ERROR("No firmware provided for DMUB.\n");
++ return -EINVAL;
++ }
++
++ status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
++ if (status != DMUB_STATUS_OK) {
++ DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
++ return -EINVAL;
++ }
++
++ if (!has_hw_support) {
++ DRM_INFO("DMUB unsupported on ASIC\n");
++ return 0;
++ }
++
++ hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
++
++ /* Calculate the size of all the regions for the DMUB service. */
++ memset(&region_params, 0, sizeof(region_params));
++
++ region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
++ psp_header_bytes - psp_footer_bytes;
++ region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
++ region_params.vbios_size = adev->dm.dc->ctx->dc_bios->bios_size;
++
++ status = dmub_srv_calc_region_info(dmub_srv, &region_params,
++ &region_info);
++
++ if (status != DMUB_STATUS_OK) {
++ DRM_ERROR("Error calculating DMUB region info: %d\n", status);
++ return -EINVAL;
++ }
++
++ /*
++ * Allocate a framebuffer based on the total size of all the regions.
++ * TODO: Move this into GART.
++ */
++ r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
++ AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
++ &adev->dm.dmub_bo_gpu_addr,
++ &adev->dm.dmub_bo_cpu_addr);
++ if (r)
++ return r;
++
++ /* Rebase the regions on the framebuffer address. */
++ memset(&fb_params, 0, sizeof(fb_params));
++ fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
++ fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
++ fb_params.region_info = &region_info;
++
++ status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, &fb_info);
++ if (status != DMUB_STATUS_OK) {
++ DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
++ return -EINVAL;
++ }
++
++ fw_inst_const = dmub_fw->data +
++ le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
++ psp_header_bytes;
++
++ fw_bss_data = dmub_fw->data +
++ le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
++ le32_to_cpu(hdr->inst_const_bytes);
++
++ /* Copy firmware and bios info into FB memory. */
++ memcpy(fb_info.fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
++ region_params.inst_const_size);
++ memcpy(fb_info.fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, fw_bss_data,
++ region_params.bss_data_size);
++ memcpy(fb_info.fb[DMUB_WINDOW_3_VBIOS].cpu_addr,
++ adev->dm.dc->ctx->dc_bios->bios, region_params.vbios_size);
++
++ /* Initialize hardware. */
++ memset(&hw_params, 0, sizeof(hw_params));
++ hw_params.fb_base = adev->gmc.fb_start;
++ hw_params.fb_offset = adev->gmc.aper_base;
++
++ if (dmcu)
++ hw_params.psp_version = dmcu->psp_version;
++
++ for (i = 0; i < fb_info.num_fb; ++i)
++ hw_params.fb[i] = &fb_info.fb[i];
++
++ status = dmub_srv_hw_init(dmub_srv, &hw_params);
++ if (status != DMUB_STATUS_OK) {
++ DRM_ERROR("Error initializing DMUB HW: %d\n", status);
++ return -EINVAL;
++ }
++
++ /* Wait for firmware load to finish. */
++ status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
++ if (status != DMUB_STATUS_OK)
++ DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
++
++ /* Init DMCU and ABM if available. */
++ if (dmcu && abm) {
++ dmcu->funcs->dmcu_init(dmcu);
++ abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
++ }
++
++ DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
++ adev->dm.dmcub_fw_version);
++
++ return 0;
++}
++
++#endif
++
++
++
+ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ {
+ struct dc_init_data init_data;
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ struct dc_callback_init init_params;
++#endif
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ int r;
+ #endif
+ adev->dm.ddev = adev->ddev;
+ adev->dm.adev = adev;
+@@ -746,6 +895,14 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+
+ dc_hardware_init(adev->dm.dc);
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ r = dm_dmub_hw_init(adev);
++ if (r) {
++ DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
++ goto error;
++ }
++
++#endif
+ adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
+ if (!adev->dm.freesync_module) {
+ DRM_ERROR(
+@@ -781,6 +938,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ if (dtn_debugfs_init(adev))
+ DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
+ #endif
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (adev->dm.dmub_bo)
++ amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
++ &adev->dm.dmub_bo_gpu_addr,
++ &adev->dm.dmub_bo_cpu_addr);
++#endif
+
+ DRM_DEBUG_DRIVER("KMS initialized.\n");
+
+@@ -914,9 +1077,104 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
+ return 0;
+ }
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
++{
++ struct amdgpu_device *adev = ctx;
++
++ return dm_read_reg(adev->dm.dc->ctx, address);
++}
++
++static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
++ uint32_t value)
++{
++ struct amdgpu_device *adev = ctx;
++
++ return dm_write_reg(adev->dm.dc->ctx, address, value);
++}
++
++static int dm_dmub_sw_init(struct amdgpu_device *adev)
++{
++ struct dmub_srv_create_params create_params;
++ const struct dmcub_firmware_header_v1_0 *hdr;
++ const char *fw_name_dmub;
++ enum dmub_asic dmub_asic;
++ enum dmub_status status;
++ int r;
++
++ switch (adev->asic_type) {
++ case CHIP_RENOIR:
++ dmub_asic = DMUB_ASIC_DCN21;
++ fw_name_dmub = FIRMWARE_RENOIR_DMUB;
++ break;
++
++ default:
++ /* ASIC doesn't support DMUB. */
++ return 0;
++ }
++
++ adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
++ if (!adev->dm.dmub_srv) {
++ DRM_ERROR("Failed to allocate DMUB service!\n");
++ return -ENOMEM;
++ }
++
++ memset(&create_params, 0, sizeof(create_params));
++ create_params.user_ctx = adev;
++ create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
++ create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
++ create_params.asic = dmub_asic;
++
++ status = dmub_srv_create(adev->dm.dmub_srv, &create_params);
++ if (status != DMUB_STATUS_OK) {
++ DRM_ERROR("Error creating DMUB service: %d\n", status);
++ return -EINVAL;
++ }
++
++ r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
++ if (r) {
++ DRM_ERROR("DMUB firmware loading failed: %d\n", r);
++ return 0;
++ }
++
++ r = amdgpu_ucode_validate(adev->dm.dmub_fw);
++ if (r) {
++ DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
++ return 0;
++ }
++
++ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
++ DRM_WARN("Only PSP firmware loading is supported for DMUB\n");
++ return 0;
++ }
++
++ hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
++ adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
++ AMDGPU_UCODE_ID_DMCUB;
++ adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = adev->dm.dmub_fw;
++ adev->firmware.fw_size +=
++ ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
++
++ adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
++
++ DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
++ adev->dm.dmcub_fw_version);
++
++ return 0;
++}
++
++#endif
+ static int dm_sw_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ int r;
++
++ r = dm_dmub_sw_init(adev);
++ if (r)
++ return r;
++
++#endif
+
+ return load_dmcu_fw(adev);
+ }
+@@ -925,6 +1183,18 @@ static int dm_sw_fini(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (adev->dm.dmub_srv) {
++ dmub_srv_destroy(adev->dm.dmub_srv);
++ adev->dm.dmub_srv = NULL;
++ }
++
++ if (adev->dm.dmub_fw) {
++ release_firmware(adev->dm.dmub_fw);
++ adev->dm.dmub_fw = NULL;
++ }
++
++#endif
+ if(adev->dm.fw_dmcu) {
+ release_firmware(adev->dm.fw_dmcu);
+ adev->dm.fw_dmcu = NULL;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 1aba070477b9..27167d2bd654 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -54,6 +54,10 @@ struct amdgpu_device;
+ struct drm_device;
+ struct amdgpu_dm_irq_handler_data;
+ struct dc;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct amdgpu_bo;
++struct dmub_srv;
++#endif
+
+ struct common_irq_params {
+ struct amdgpu_device *adev;
+@@ -145,6 +149,52 @@ struct amdgpu_display_manager {
+ */
+ struct mutex dc_lock;
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ /**
++ * @dmub_srv:
++ *
++ * DMUB service, used for controlling the DMUB on hardware
++ * that supports it. The pointer to the dmub_srv will be
++ * NULL on hardware that does not support it.
++ */
++ struct dmub_srv *dmub_srv;
++
++ /**
++ * @dmub_fw:
++ *
++ * DMUB firmware, required on hardware that has DMUB support.
++ */
++ const struct firmware *dmub_fw;
++
++ /**
++ * @dmub_bo:
++ *
++ * Buffer object for the DMUB.
++ */
++ struct amdgpu_bo *dmub_bo;
++
++ /**
++ * @dmub_bo_gpu_addr:
++ *
++ * GPU virtual address for the DMUB buffer object.
++ */
++ u64 dmub_bo_gpu_addr;
++
++ /**
++ * @dmub_bo_cpu_addr:
++ *
++ * CPU address for the DMUB buffer object.
++ */
++ void *dmub_bo_cpu_addr;
++
++ /**
++ * @dmcub_fw_version:
++ *
++ * DMCUB firmware version.
++ */
++ uint32_t dmcub_fw_version;
++
++#endif
+ /**
+ *@irq_handler_list_low_tab:
+ *
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4330-drm-amdgpu-Add-DMCUB-to-firmware-query-interface.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4330-drm-amdgpu-Add-DMCUB-to-firmware-query-interface.patch
new file mode 100644
index 00000000..1075e944
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4330-drm-amdgpu-Add-DMCUB-to-firmware-query-interface.patch
@@ -0,0 +1,64 @@
+From 3faf3e71dc5db6f489cf30ec23cdd265f69f7935 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 14:15:08 -0400
+Subject: [PATCH 4330/4736] drm/amdgpu: Add DMCUB to firmware query interface
+
+The DMCUB firmware version can be read using the AMDGPU_INFO ioctl
+or the amdgpu_firmware_info debugfs entry.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++++++++++++
+ include/uapi/drm/amdgpu_drm.h | 3 +++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index ff47dd26e35a..5abbfc488022 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -291,6 +291,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
+ fw_info->ver = adev->dm.dmcu_fw_version;
+ fw_info->feature = 0;
+ break;
++ case AMDGPU_INFO_FW_DMCUB:
++ fw_info->ver = adev->dm.dmcub_fw_version;
++ fw_info->feature = 0;
++ break;
+ default:
+ return -EINVAL;
+ }
+@@ -1430,6 +1434,14 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
+ seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
+ fw_info.feature, fw_info.ver);
+
++ /* DMCUB */
++ query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
++ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
++ if (ret)
++ return ret;
++ seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
++ fw_info.feature, fw_info.ver);
++
+
+ seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 2de868bf8266..989afacefb92 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -770,6 +770,9 @@ struct drm_amdgpu_cs_chunk_data {
+ /* Subquery id: Query DMCU firmware version */
+ #define AMDGPU_INFO_FW_DMCU 0x12
+ #define AMDGPU_INFO_FW_TA 0x13
++ /* Subquery id: Query DMCUB firmware version */
++ #define AMDGPU_INFO_FW_DMCUB 0x14
++
+ /* number of bytes moved for TTM migration */
+ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
+ /* the used VRAM size */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4331-drm-amd-display-Add-DMUB-support-to-DC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4331-drm-amd-display-Add-DMUB-support-to-DC.patch
new file mode 100644
index 00000000..1580bb36
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4331-drm-amd-display-Add-DMUB-support-to-DC.patch
@@ -0,0 +1,968 @@
+From 23983b55e0d07ee00b2331b9c67f643281542f59 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 15:03:58 -0400
+Subject: [PATCH 4331/4736] drm/amd/display: Add DMUB support to DC
+
+DC will use DMUB for command submission and flow control during
+initialization.
+
+Register offloading as well as submitting some BIOS commands are part
+of the DC internal interface but are guarded behind debug options.
+
+It won't be functional in amdgpu_dm yet since we don't pass the
+DMUB service to DC for use.
+
+Change-Id: Ib341af1d0d5569271cb1964de5b6ef6ba8e9d8f3
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/Makefile | 6 +-
+ .../drm/amd/display/dc/bios/command_table2.c | 91 ++++++
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +
+ drivers/gpu/drm/amd/display/dc/dc.h | 12 +
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 119 ++++++++
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 60 ++++
+ drivers/gpu/drm/amd/display/dc/dc_helper.c | 273 ++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc_types.h | 6 +
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 7 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 11 +
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 3 +
+ drivers/gpu/drm/amd/display/dc/dm_services.h | 14 +
+ .../gpu/drm/amd/display/dc/inc/reg_helper.h | 22 ++
+ drivers/gpu/drm/amd/display/dc/os_types.h | 2 +
+ 14 files changed, 633 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index a160512a2f04..6fe39f6392c7 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -70,5 +70,9 @@ AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)
+ AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
+ AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)
+
+-
++ifdef CONFIG_DRM_AMD_DC_DMUB
++DC_DMUB += dc_dmub_srv.o
++AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
++AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB)
++endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+index bb2e8105e6ab..a3d890050e39 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+@@ -37,6 +37,10 @@
+ #include "bios_parser_types_internal2.h"
+ #include "amdgpu.h"
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dc_dmub_srv.h"
++#include "dc.h"
++#endif
+
+ #define DC_LOGGER \
+ bp->base.ctx->logger
+@@ -103,6 +107,21 @@ static void init_dig_encoder_control(struct bios_parser *bp)
+ }
+ }
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void encoder_control_dmcub(
++ struct dc_dmub_srv *dmcub,
++ struct dig_encoder_stream_setup_parameters_v1_5 *dig)
++{
++ struct dmub_rb_cmd_digx_encoder_control encoder_control = { 0 };
++
++ encoder_control.header.type = DMUB_CMD__DIGX_ENCODER_CONTROL;
++ encoder_control.encoder_control.dig.stream_param = *dig;
++
++ dc_dmub_srv_cmd_queue(dmcub, &encoder_control.header);
++ dc_dmub_srv_cmd_execute(dmcub);
++ dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+ static enum bp_result encoder_control_digx_v1_5(
+ struct bios_parser *bp,
+ struct bp_encoder_control *cntl)
+@@ -154,6 +173,13 @@ static enum bp_result encoder_control_digx_v1_5(
+ default:
+ break;
+ }
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (bp->base.ctx->dc->ctx->dmub_srv &&
++ bp->base.ctx->dc->debug.dmub_command_table) {
++ encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
++ return BP_RESULT_OK;
++ }
++#endif
+
+ if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
+ result = BP_RESULT_OK;
+@@ -190,7 +216,21 @@ static void init_transmitter_control(struct bios_parser *bp)
+ break;
+ }
+ }
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void transmitter_control_dmcub(
++ struct dc_dmub_srv *dmcub,
++ struct dig_transmitter_control_parameters_v1_6 *dig)
++{
++ struct dmub_rb_cmd_dig1_transmitter_control transmitter_control;
++
++ transmitter_control.header.type = DMUB_CMD__DIG1_TRANSMITTER_CONTROL;
++ transmitter_control.transmitter_control.dig = *dig;
+
++ dc_dmub_srv_cmd_queue(dmcub, &transmitter_control.header);
++ dc_dmub_srv_cmd_execute(dmcub);
++ dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+ static enum bp_result transmitter_control_v1_6(
+ struct bios_parser *bp,
+ struct bp_transmitter_control *cntl)
+@@ -223,6 +263,14 @@ static enum bp_result transmitter_control_v1_6(
+ }
+
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (bp->base.ctx->dc->ctx->dmub_srv &&
++ bp->base.ctx->dc->debug.dmub_command_table) {
++ transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
++ return BP_RESULT_OK;
++ }
++#endif
++
+ /*color_depth not used any more, driver has deep color factor in the Phyclk*/
+ if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
+ result = BP_RESULT_OK;
+@@ -255,7 +303,21 @@ static void init_set_pixel_clock(struct bios_parser *bp)
+ }
+ }
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void set_pixel_clock_dmcub(
++ struct dc_dmub_srv *dmcub,
++ struct set_pixel_clock_parameter_v1_7 *clk)
++{
++ struct dmub_rb_cmd_set_pixel_clock pixel_clock = { 0 };
+
++ pixel_clock.header.type = DMUB_CMD__SET_PIXEL_CLOCK;
++ pixel_clock.pixel_clock.clk = *clk;
++
++ dc_dmub_srv_cmd_queue(dmcub, &pixel_clock.header);
++ dc_dmub_srv_cmd_execute(dmcub);
++ dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+
+ static enum bp_result set_pixel_clock_v7(
+ struct bios_parser *bp,
+@@ -331,6 +393,13 @@ static enum bp_result set_pixel_clock_v7(
+ if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
+ clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (bp->base.ctx->dc->ctx->dmub_srv &&
++ bp->base.ctx->dc->debug.dmub_command_table) {
++ set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
++ return BP_RESULT_OK;
++ }
++#endif
+ if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
+ result = BP_RESULT_OK;
+ }
+@@ -584,7 +653,21 @@ static void init_enable_disp_power_gating(
+ break;
+ }
+ }
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void enable_disp_power_gating_dmcub(
++ struct dc_dmub_srv *dmcub,
++ struct enable_disp_power_gating_parameters_v2_1 *pwr)
++{
++ struct dmub_rb_cmd_enable_disp_power_gating power_gating;
++
++ power_gating.header.type = DMUB_CMD__ENABLE_DISP_POWER_GATING;
++ power_gating.power_gating.pwr = *pwr;
+
++ dc_dmub_srv_cmd_queue(dmcub, &power_gating.header);
++ dc_dmub_srv_cmd_execute(dmcub);
++ dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+ static enum bp_result enable_disp_power_gating_v2_1(
+ struct bios_parser *bp,
+ enum controller_id crtc_id,
+@@ -604,6 +687,14 @@ static enum bp_result enable_disp_power_gating_v2_1(
+ ps.param.enable =
+ bp->cmd_helper->disp_power_gating_action_to_atom(action);
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (bp->base.ctx->dc->ctx->dmub_srv &&
++ bp->base.ctx->dc->debug.dmub_command_table) {
++ enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
++ &ps.param);
++ return BP_RESULT_OK;
++ }
++#endif
+ if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
+ result = BP_RESULT_OK;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 3d38e7e071a4..9ddc0124cda1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -56,6 +56,10 @@
+
+ #include "dc_link_dp.h"
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dc_dmub_srv.h"
++#endif
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+ #endif
+@@ -2399,6 +2403,10 @@ void dc_set_power_state(
+ switch (power_state) {
+ case DC_ACPI_CM_POWER_STATE_D0:
+ dc_resource_state_construct(dc, dc->current_state);
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (dc->ctx->dmub_srv)
++ dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
++#endif
+
+ dc->hwss.init_hw(dc);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 0416a17b0897..33828f03fe9e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -112,6 +112,9 @@ struct dc_caps {
+ bool disable_dp_clk_share;
+ bool psp_setup_panel_mode;
+ bool extended_aux_timeout_support;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ bool dmcub_support;
++#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hw_3d_lut;
+ #endif
+@@ -401,6 +404,11 @@ struct dc_debug_options {
+ unsigned int force_odm_combine; //bit vector based on otg inst
+ unsigned int force_fclk_khz;
+ bool disable_tri_buf;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ bool dmub_offload_enabled;
++ bool dmcub_emulation;
++ bool dmub_command_table; /* for testing only */
++#endif
+ struct dc_bw_validation_profile bw_val_profile;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool disable_fec;
+@@ -558,6 +566,10 @@ struct dc_init_data {
+ struct dc_bios *vbios_override;
+ enum dce_environment dce_environment;
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ struct dmub_offload_funcs *dmub_if;
++ struct dc_reg_helper_state *dmub_offload;
++#endif
+ struct dc_config flags;
+ uint32_t log_mask;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+new file mode 100644
+index 000000000000..61cefe0a3790
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+@@ -0,0 +1,119 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dc.h"
++#include "dc_dmub_srv.h"
++#include "../dmub/inc/dmub_srv.h"
++
++static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
++ struct dmub_srv *dmub)
++{
++ dc_srv->dmub = dmub;
++ dc_srv->ctx = dc->ctx;
++}
++
++struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
++{
++ struct dc_dmub_srv *dc_srv =
++ kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
++
++ if (dc_srv == NULL) {
++ BREAK_TO_DEBUGGER();
++ return NULL;
++ }
++
++ dc_dmub_srv_construct(dc_srv, dc, dmub);
++
++ return dc_srv;
++}
++
++void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
++{
++ if (*dmub_srv) {
++ kfree(*dmub_srv);
++ *dmub_srv = NULL;
++ }
++}
++
++void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
++ struct dmub_cmd_header *cmd)
++{
++ struct dmub_srv *dmub = dc_dmub_srv->dmub;
++ struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++ enum dmub_status status;
++
++ status = dmub_srv_cmd_queue(dmub, cmd);
++ if (status == DMUB_STATUS_OK)
++ return;
++
++ if (status != DMUB_STATUS_QUEUE_FULL)
++ goto error;
++
++ /* Execute and wait for queue to become empty again. */
++ dc_dmub_srv_cmd_execute(dc_dmub_srv);
++ dc_dmub_srv_wait_idle(dc_dmub_srv);
++
++ /* Requeue the command. */
++ status = dmub_srv_cmd_queue(dmub, cmd);
++ if (status == DMUB_STATUS_OK)
++ return;
++
++error:
++ DC_ERROR("Error queuing DMUB command: status=%d\n", status);
++}
++
++void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
++{
++ struct dmub_srv *dmub = dc_dmub_srv->dmub;
++ struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++ enum dmub_status status;
++
++ status = dmub_srv_cmd_execute(dmub);
++ if (status != DMUB_STATUS_OK)
++ DC_ERROR("Error starting DMUB exeuction: status=%d\n", status);
++}
++
++void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
++{
++ struct dmub_srv *dmub = dc_dmub_srv->dmub;
++ struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++ enum dmub_status status;
++
++ status = dmub_srv_wait_for_idle(dmub, 100000);
++ if (status != DMUB_STATUS_OK)
++ DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
++}
++
++void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
++{
++ struct dmub_srv *dmub = dc_dmub_srv->dmub;
++ struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++ enum dmub_status status;
++
++ status = dmub_srv_wait_for_phy_init(dmub, 1000000);
++ if (status != DMUB_STATUS_OK)
++ DC_ERROR("Error waiting for DMUB phy init: status=%d\n",
++ status);
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+new file mode 100644
+index 000000000000..754b6077539c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+@@ -0,0 +1,60 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_DC_SRV_H_
++#define _DMUB_DC_SRV_H_
++
++#include "os_types.h"
++#include "../dmub/inc/dmub_cmd.h"
++
++struct dmub_srv;
++struct dmub_cmd_header;
++
++struct dc_reg_helper_state {
++ bool gather_in_progress;
++ uint32_t same_addr_count;
++ bool should_burst_write;
++ union dmub_rb_cmd cmd_data;
++ unsigned int reg_seq_count;
++};
++
++struct dc_dmub_srv {
++ struct dmub_srv *dmub;
++ struct dc_reg_helper_state reg_helper_offload;
++
++ struct dc_context *ctx;
++ void *dm;
++};
++
++void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
++ struct dmub_cmd_header *cmd);
++
++void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv);
++
++void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
++
++void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv);
++
++#endif /* _DMUB_DC_SRV_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index 2d0acf109360..adfc6e9b59b1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -29,6 +29,76 @@
+ #include "dm_services.h"
+ #include <stdarg.h>
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dc.h"
++#include "dc_dmub_srv.h"
++
++static inline void submit_dmub_read_modify_write(
++ struct dc_reg_helper_state *offload,
++ const struct dc_context *ctx)
++{
++ struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
++ bool gather = false;
++
++ offload->should_burst_write =
++ (offload->same_addr_count == (DMUB_READ_MODIFY_WRITE_SEQ__MAX - 1));
++ cmd_buf->header.payload_bytes =
++ sizeof(struct dmub_cmd_read_modify_write_sequence) * offload->reg_seq_count;
++
++ gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
++
++ dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header);
++
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
++
++ memset(cmd_buf, 0, sizeof(*cmd_buf));
++
++ offload->reg_seq_count = 0;
++ offload->same_addr_count = 0;
++}
++
++static inline void submit_dmub_burst_write(
++ struct dc_reg_helper_state *offload,
++ const struct dc_context *ctx)
++{
++ struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
++ bool gather = false;
++
++ cmd_buf->header.payload_bytes =
++ sizeof(uint32_t) * offload->reg_seq_count;
++
++ gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
++
++ dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header);
++
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
++
++ memset(cmd_buf, 0, sizeof(*cmd_buf));
++
++ offload->reg_seq_count = 0;
++}
++
++static inline void submit_dmub_reg_wait(
++ struct dc_reg_helper_state *offload,
++ const struct dc_context *ctx)
++{
++ struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
++ bool gather = false;
++
++ gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
++
++ dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header);
++
++ memset(cmd_buf, 0, sizeof(*cmd_buf));
++ offload->reg_seq_count = 0;
++
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
++}
++#endif
++
+ struct dc_reg_value_masks {
+ uint32_t value;
+ uint32_t mask;
+@@ -74,6 +144,100 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
+ }
+ }
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void dmub_flush_buffer_execute(
++ struct dc_reg_helper_state *offload,
++ const struct dc_context *ctx)
++{
++ submit_dmub_read_modify_write(offload, ctx);
++ dc_dmub_srv_cmd_execute(ctx->dmub_srv);
++}
++
++static void dmub_flush_burst_write_buffer_execute(
++ struct dc_reg_helper_state *offload,
++ const struct dc_context *ctx)
++{
++ submit_dmub_burst_write(offload, ctx);
++ dc_dmub_srv_cmd_execute(ctx->dmub_srv);
++}
++
++static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr,
++ uint32_t reg_val)
++{
++ struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
++ struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
++
++ /* flush command if buffer is full */
++ if (offload->reg_seq_count == DMUB_BURST_WRITE_VALUES__MAX)
++ dmub_flush_burst_write_buffer_execute(offload, ctx);
++
++ if (offload->cmd_data.cmd_common.header.type == DMUB_CMD__REG_SEQ_BURST_WRITE &&
++ addr != cmd_buf->addr) {
++ dmub_flush_burst_write_buffer_execute(offload, ctx);
++ return false;
++ }
++
++ cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE;
++ cmd_buf->addr = addr;
++ cmd_buf->write_values[offload->reg_seq_count] = reg_val;
++ offload->reg_seq_count++;
++
++ return true;
++}
++
++static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,
++ struct dc_reg_value_masks *field_value_mask)
++{
++ struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
++ struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
++ struct dmub_cmd_read_modify_write_sequence *seq;
++
++ /* flush command if buffer is full */
++ if (offload->cmd_data.cmd_common.header.type != DMUB_CMD__REG_SEQ_BURST_WRITE &&
++ offload->reg_seq_count == DMUB_READ_MODIFY_WRITE_SEQ__MAX)
++ dmub_flush_buffer_execute(offload, ctx);
++
++ if (offload->should_burst_write) {
++ if (dmub_reg_value_burst_set_pack(ctx, addr, field_value_mask->value))
++ return field_value_mask->value;
++ else
++ offload->should_burst_write = false;
++ }
++
++ /* pack commands */
++ cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
++ seq = &cmd_buf->seq[offload->reg_seq_count];
++
++ if (offload->reg_seq_count) {
++ if (cmd_buf->seq[offload->reg_seq_count - 1].addr == addr)
++ offload->same_addr_count++;
++ else
++ offload->same_addr_count = 0;
++ }
++
++ seq->addr = addr;
++ seq->modify_mask = field_value_mask->mask;
++ seq->modify_value = field_value_mask->value;
++ offload->reg_seq_count++;
++
++ return field_value_mask->value;
++}
++
++static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
++ uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us)
++{
++ struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
++ struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
++
++ cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT;
++ cmd_buf->reg_wait.addr = addr;
++ cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);
++ cmd_buf->reg_wait.mask = mask;
++ cmd_buf->reg_wait.time_out_us = time_out_us;
++}
++
++#endif
++
+ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ uint32_t addr, int n,
+ uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+@@ -90,6 +254,13 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+
+ va_end(ap);
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (ctx->dmub_srv &&
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress)
++ return dmub_reg_value_pack(ctx, addr, &field_value_mask);
++ /* todo: return void so we can decouple code running in driver from register states */
++#endif
++
+ /* mmio write directly */
+ reg_val = dm_read_reg(ctx, addr);
+ reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
+@@ -115,6 +286,13 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
+
+ /* mmio write directly */
+ reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (ctx->dmub_srv &&
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
++ return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
++ /* todo: return void so we can decouple code running in driver from register states */
++ }
++#endif
+ dm_write_reg(ctx, addr, reg_val);
+ return reg_val;
+ }
+@@ -131,6 +309,16 @@ uint32_t dm_read_reg_func(
+ return 0;
+ }
+ #endif
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (ctx->dmub_srv &&
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
++ !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
++ ASSERT(false);
++ return 0;
++ }
++#endif
++
+ value = cgs_read_register(ctx->cgs_device, address);
+ trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
+
+@@ -296,6 +484,15 @@ void generic_reg_wait(const struct dc_context *ctx,
+ uint32_t reg_val;
+ int i;
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (ctx->dmub_srv &&
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
++ dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
++ delay_between_poll_us * time_out_num_tries);
++ return;
++ }
++#endif
++
+ /* something is terribly wrong if time out is > 200ms. (5Hz) */
+ ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
+
+@@ -342,6 +539,13 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
+ uint32_t index)
+ {
+ uint32_t value = 0;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ // when reg read, there should not be any offload.
++ if (ctx->dmub_srv &&
++ ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
++ ASSERT(false);
++ }
++#endif
+
+ dm_write_reg(ctx, addr_index, index);
+ value = dm_read_reg(ctx, addr_data);
+@@ -379,3 +583,72 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+
+ return reg_val;
+ }
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++void reg_sequence_start_gather(const struct dc_context *ctx)
++{
++ /* if reg sequence is supported and enabled, set flag to
++ * indicate we want to have REG_SET, REG_UPDATE macro build
++ * reg sequence command buffer rather than MMIO directly.
++ */
++
++ if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {
++ struct dc_reg_helper_state *offload =
++ &ctx->dmub_srv->reg_helper_offload;
++
++ /* caller sequence mismatch. need to debug caller. offload will not work!!! */
++ ASSERT(!offload->gather_in_progress);
++
++ offload->gather_in_progress = true;
++ }
++}
++
++void reg_sequence_start_execute(const struct dc_context *ctx)
++{
++ struct dc_reg_helper_state *offload;
++
++ if (!ctx->dmub_srv)
++ return;
++
++ offload = &ctx->dmub_srv->reg_helper_offload;
++
++ if (offload && offload->gather_in_progress) {
++ offload->gather_in_progress = false;
++ offload->should_burst_write = false;
++ switch (offload->cmd_data.cmd_common.header.type) {
++ case DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE:
++ submit_dmub_read_modify_write(offload, ctx);
++ break;
++ case DMUB_CMD__REG_REG_WAIT:
++ submit_dmub_reg_wait(offload, ctx);
++ break;
++ case DMUB_CMD__REG_SEQ_BURST_WRITE:
++ submit_dmub_burst_write(offload, ctx);
++ break;
++ default:
++ return;
++ }
++
++ dc_dmub_srv_cmd_execute(ctx->dmub_srv);
++ }
++}
++
++void reg_sequence_wait_done(const struct dc_context *ctx)
++{
++ /* callback to DM to poll for last submission done*/
++ struct dc_reg_helper_state *offload;
++
++ if (!ctx->dmub_srv)
++ return;
++
++ offload = &ctx->dmub_srv->reg_helper_offload;
++
++ if (offload &&
++ ctx->dc->debug.dmub_offload_enabled &&
++ !ctx->dc->debug.dmcub_emulation) {
++ dc_dmub_srv_wait_idle(ctx->dmub_srv);
++ }
++}
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index d9be8fc3889f..fb70ed9b351f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -48,6 +48,9 @@ struct dc_stream_state;
+ struct dc_link;
+ struct dc_sink;
+ struct dal;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct dc_dmub_srv;
++#endif
+
+ /********************************
+ * Environment definitions
+@@ -109,6 +112,9 @@ struct dc_context {
+ uint32_t dc_sink_id_count;
+ uint32_t dc_stream_id_count;
+ uint64_t fbc_gpu_addr;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ struct dc_dmub_srv *dmub_srv;
++#endif
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ struct cp_psp cp_psp;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index aa0c7a7d13a0..41a0e53d2ba4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -352,6 +352,9 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
+ uint32_t i;
+ struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ REG_SEQ_START();
++#endif
+ for (i = 0 ; i < num; i++) {
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
+@@ -630,6 +633,10 @@ void dpp1_set_degamma(
+ BREAK_TO_DEBUGGER();
+ break;
+ }
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ REG_SEQ_SUBMIT();
++ REG_SEQ_WAIT_DONE();
++#endif
+ }
+
+ void dpp1_degamma_ram_select(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 5a188b2bc033..2417d933ef2b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -345,6 +345,11 @@ static void mpc20_program_ogam_pwl(
+ uint32_t i;
+ struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ PERF_TRACE();
++ REG_SEQ_START();
++#endif
++
+ for (i = 0 ; i < num; i++) {
+ REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
+ REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);
+@@ -463,6 +468,12 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
+ ASSERT(!mpc_disabled);
+ ASSERT(!mpc_idle);
+ }
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ REG_SEQ_SUBMIT();
++ PERF_TRACE();
++ REG_SEQ_WAIT_DONE();
++ PERF_TRACE();
++#endif
+ }
+
+ static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 0792b1c2e673..30a246ebe842 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1699,6 +1699,9 @@ static bool construct(
+ dc->caps.post_blend_color_processing = true;
+ dc->caps.force_dp_tps4_for_cp2520 = true;
+ dc->caps.extended_aux_timeout_support = true;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++ dc->caps.dmcub_support = true;
++#endif
+
+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
+index 1a0429744630..0a3891edfd94 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
+@@ -40,6 +40,11 @@
+
+ #undef DEPRECATED
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct dmub_srv;
++struct dc_dmub_srv;
++
++#endif
+ irq_handler_idx dm_register_interrupt(
+ struct dc_context *ctx,
+ struct dc_interrupt_params *int_params,
+@@ -139,6 +144,15 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ uint32_t addr, int n,
+ uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
+
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
++void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
++
++void reg_sequence_start_gather(const struct dc_context *ctx);
++void reg_sequence_start_execute(const struct dc_context *ctx);
++void reg_sequence_wait_done(const struct dc_context *ctx);
++#endif
++
+ #define FD(reg_field) reg_field ## __SHIFT, \
+ reg_field ## _MASK
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+index 8503d9cc4763..a9a9657c095a 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+@@ -485,4 +485,26 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+ ...);
+
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++/* register offload macros
++ *
++ * instead of MMIO to register directly, in some cases we want
++ * to gather register sequence and execute the register sequence
++ * from another thread so we optimize time required for lengthy ops
++ */
++
++/* start gathering register sequence */
++#define REG_SEQ_START() \
++ reg_sequence_start_gather(CTX)
++
++/* start execution of register sequence gathered since REG_SEQ_START */
++#define REG_SEQ_SUBMIT() \
++ reg_sequence_start_execute(CTX)
++
++/* wait for the last REG_SEQ_SUBMIT to finish */
++#define REG_SEQ_WAIT_DONE() \
++ reg_sequence_wait_done(CTX)
++#endif
++
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
+index f20996e71274..77b97559e847 100644
+--- a/drivers/gpu/drm/amd/display/dc/os_types.h
++++ b/drivers/gpu/drm/amd/display/dc/os_types.h
+@@ -26,6 +26,8 @@
+ #ifndef _OS_TYPES_H_
+ #define _OS_TYPES_H_
+
++#include <linux/slab.h>
++
+ #include <asm/byteorder.h>
+ #include <linux/types.h>
+ #include <drm/drmP.h>
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4332-drm-amd-display-Register-DMUB-service-with-DC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4332-drm-amd-display-Register-DMUB-service-with-DC.patch
new file mode 100644
index 00000000..40b9de21
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4332-drm-amd-display-Register-DMUB-service-with-DC.patch
@@ -0,0 +1,61 @@
+From 5f8b8c91bfa83debf11fe47831bc49973942349f Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 28 Oct 2019 09:07:30 -0400
+Subject: [PATCH 4332/4736] drm/amd/display: Register DMUB service with DC
+
+[Why]
+DC can utilize the DMUB server to send commands to the DMUB but it's
+the DM responsibility to pass it the service to use.
+
+[How]
+Create the dc_dmub_srv after we finish initializing the dmub_srv.
+Cleanup the dc_dmub_srv before destroying the dmub_srv or dc.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index e226e526c4df..f47761a2ec9b 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -34,6 +34,7 @@
+ #include "dmub/inc/dmub_srv.h"
+ #include "dc/inc/hw/dmcu.h"
+ #include "dc/inc/hw/abm.h"
++#include "dc/dc_dmub_srv.h"
+ #endif
+
+ #include "vid.h"
+@@ -801,6 +802,12 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
+ abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
+ }
+
++ adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
++ if (!adev->dm.dc->ctx->dmub_srv) {
++ DRM_ERROR("Couldn't allocate DC DMUB server!\n");
++ return -ENOMEM;
++ }
++
+ DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
+ adev->dm.dmcub_fw_version);
+
+@@ -939,6 +946,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
+ #endif
+ #ifdef CONFIG_DRM_AMD_DC_DMUB
++ if (adev->dm.dc->ctx->dmub_srv) {
++ dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
++ adev->dm.dc->ctx->dmub_srv = NULL;
++ }
++
+ if (adev->dm.dmub_bo)
+ amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
+ &adev->dm.dmub_bo_gpu_addr,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4333-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DMUB-guards.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4333-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DMUB-guards.patch
new file mode 100644
index 00000000..8d9838b6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4333-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DMUB-guards.patch
@@ -0,0 +1,794 @@
+From b24c998450cfa186de1a9efd0f3366841577f526 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 28 Oct 2019 09:22:34 -0400
+Subject: [PATCH 4333/4736] drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards
+
+[Why]
+Support for DMUB only depends on support for DC. It doesn't use floating
+point so we don't need to guard it by any specific DCN revision.
+
+[How]
+Drop the guards and cleanup the newlines around each one.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/Kconfig | 6 -----
+ drivers/gpu/drm/amd/display/Makefile | 12 +++------
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +-------------
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ---
+ drivers/gpu/drm/amd/display/dc/Makefile | 3 ---
+ .../drm/amd/display/dc/bios/command_table2.c | 27 ++++++-------------
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +----
+ drivers/gpu/drm/amd/display/dc/dc.h | 7 +----
+ drivers/gpu/drm/amd/display/dc/dc_helper.c | 22 +++------------
+ drivers/gpu/drm/amd/display/dc/dc_types.h | 5 +---
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 6 ++---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 5 +---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 5 +---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 --
+ drivers/gpu/drm/amd/display/dc/dm_services.h | 4 ---
+ .../gpu/drm/amd/display/dc/inc/reg_helper.h | 3 ---
+ drivers/gpu/drm/amd/display/dmub/src/Makefile | 2 --
+ 17 files changed, 22 insertions(+), 117 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index d9ee189aebf0..9eae7c67ceb5 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -29,7 +29,6 @@ config DRM_AMD_DC_DCN2_1
+ bool "DCN 2.1 family"
+ depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC_DCN2_0
+- select DRM_AMD_DC_DMUB
+ help
+ Choose this option if you want to have
+ Renoir support for display engine
+@@ -52,11 +51,6 @@ config DRM_AMD_DC_HDCP
+ if you want to support
+ HDCP authentication
+
+-config DRM_AMD_DC_DMUB
+- def_bool n
+- help
+- DMUB support for display engine
+-
+ config DEBUG_KERNEL_DC
+ bool "Enable kgdb break in DC"
+ depends on DRM_AMD_DC
+diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
+index 3c7332be4a89..2633de77de5e 100644
+--- a/drivers/gpu/drm/amd/display/Makefile
++++ b/drivers/gpu/drm/amd/display/Makefile
+@@ -34,27 +34,21 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/info_packet
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/power
++subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
++
+ ifdef CONFIG_DRM_AMD_DC_HDCP
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
+ endif
+
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+-subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
+-endif
+-
+ #TODO: remove when Timing Sync feature is complete
+ subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
+
+-DAL_LIBS = amdgpu_dm dc modules/freesync modules/color modules/info_packet modules/power
++DAL_LIBS = amdgpu_dm dc modules/freesync modules/color modules/info_packet modules/power dmub/src
+
+ ifdef CONFIG_DRM_AMD_DC_HDCP
+ DAL_LIBS += modules/hdcp
+ endif
+
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+-DAL_LIBS += dmub/src
+-endif
+-
+ AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
+
+ include $(AMD_DAL)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index f47761a2ec9b..5ef3b7e842e4 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -30,12 +30,10 @@
+ #include "dc.h"
+ #include "dc/inc/core_types.h"
+ #include "dal_asic_id.h"
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dmub/inc/dmub_srv.h"
+ #include "dc/inc/hw/dmcu.h"
+ #include "dc/inc/hw/abm.h"
+ #include "dc/dc_dmub_srv.h"
+-#endif
+
+ #include "vid.h"
+ #include "amdgpu.h"
+@@ -90,10 +88,9 @@
+ #include "modules/power/power_helpers.h"
+ #include "modules/inc/mod_info_packet.h"
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
+ MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
+-#endif
++
+ #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
+ MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
+
+@@ -675,7 +672,6 @@ void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static int dm_dmub_hw_init(struct amdgpu_device *adev)
+ {
+ const unsigned int psp_header_bytes = 0x100;
+@@ -814,7 +810,6 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-#endif
+
+
+
+@@ -824,9 +819,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ struct dc_callback_init init_params;
+ #endif
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ int r;
+-#endif
+ adev->dm.ddev = adev->ddev;
+ adev->dm.adev = adev;
+
+@@ -902,14 +895,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+
+ dc_hardware_init(adev->dm.dc);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ r = dm_dmub_hw_init(adev);
+ if (r) {
+ DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
+ goto error;
+ }
+
+-#endif
+ adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
+ if (!adev->dm.freesync_module) {
+ DRM_ERROR(
+@@ -945,7 +936,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ if (dtn_debugfs_init(adev))
+ DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
+ #endif
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (adev->dm.dc->ctx->dmub_srv) {
+ dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
+ adev->dm.dc->ctx->dmub_srv = NULL;
+@@ -955,7 +945,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
+ &adev->dm.dmub_bo_gpu_addr,
+ &adev->dm.dmub_bo_cpu_addr);
+-#endif
+
+ DRM_DEBUG_DRIVER("KMS initialized.\n");
+
+@@ -1089,7 +1078,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
+ {
+ struct amdgpu_device *adev = ctx;
+@@ -1175,19 +1163,15 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-#endif
+ static int dm_sw_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ int r;
+
+ r = dm_dmub_sw_init(adev);
+ if (r)
+ return r;
+
+-#endif
+-
+ return load_dmcu_fw(adev);
+ }
+
+@@ -1195,7 +1179,6 @@ static int dm_sw_fini(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (adev->dm.dmub_srv) {
+ dmub_srv_destroy(adev->dm.dmub_srv);
+ adev->dm.dmub_srv = NULL;
+@@ -1206,7 +1189,6 @@ static int dm_sw_fini(void *handle)
+ adev->dm.dmub_fw = NULL;
+ }
+
+-#endif
+ if(adev->dm.fw_dmcu) {
+ release_firmware(adev->dm.fw_dmcu);
+ adev->dm.fw_dmcu = NULL;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 27167d2bd654..1fc810bf02af 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -54,10 +54,8 @@ struct amdgpu_device;
+ struct drm_device;
+ struct amdgpu_dm_irq_handler_data;
+ struct dc;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct amdgpu_bo;
+ struct dmub_srv;
+-#endif
+
+ struct common_irq_params {
+ struct amdgpu_device *adev;
+@@ -149,7 +147,6 @@ struct amdgpu_display_manager {
+ */
+ struct mutex dc_lock;
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ /**
+ * @dmub_srv:
+ *
+@@ -194,7 +191,6 @@ struct amdgpu_display_manager {
+ */
+ uint32_t dmcub_fw_version;
+
+-#endif
+ /**
+ *@irq_handler_list_low_tab:
+ *
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 6fe39f6392c7..90482b158283 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -70,9 +70,6 @@ AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)
+ AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
+ AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)
+
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+ DC_DMUB += dc_dmub_srv.o
+ AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
+ AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB)
+-endif
+-
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+index a3d890050e39..1836f16bb7fe 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+@@ -37,10 +37,8 @@
+ #include "bios_parser_types_internal2.h"
+ #include "amdgpu.h"
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dc_dmub_srv.h"
+ #include "dc.h"
+-#endif
+
+ #define DC_LOGGER \
+ bp->base.ctx->logger
+@@ -107,7 +105,6 @@ static void init_dig_encoder_control(struct bios_parser *bp)
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static void encoder_control_dmcub(
+ struct dc_dmub_srv *dmcub,
+ struct dig_encoder_stream_setup_parameters_v1_5 *dig)
+@@ -121,7 +118,7 @@ static void encoder_control_dmcub(
+ dc_dmub_srv_cmd_execute(dmcub);
+ dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
++
+ static enum bp_result encoder_control_digx_v1_5(
+ struct bios_parser *bp,
+ struct bp_encoder_control *cntl)
+@@ -173,13 +170,12 @@ static enum bp_result encoder_control_digx_v1_5(
+ default:
+ break;
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ if (bp->base.ctx->dc->ctx->dmub_srv &&
+ bp->base.ctx->dc->debug.dmub_command_table) {
+ encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
+ return BP_RESULT_OK;
+ }
+-#endif
+
+ if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
+ result = BP_RESULT_OK;
+@@ -216,7 +212,7 @@ static void init_transmitter_control(struct bios_parser *bp)
+ break;
+ }
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ static void transmitter_control_dmcub(
+ struct dc_dmub_srv *dmcub,
+ struct dig_transmitter_control_parameters_v1_6 *dig)
+@@ -230,7 +226,7 @@ static void transmitter_control_dmcub(
+ dc_dmub_srv_cmd_execute(dmcub);
+ dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
++
+ static enum bp_result transmitter_control_v1_6(
+ struct bios_parser *bp,
+ struct bp_transmitter_control *cntl)
+@@ -262,14 +258,11 @@ static enum bp_result transmitter_control_v1_6(
+ __func__, ps.param.symclk_10khz);
+ }
+
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (bp->base.ctx->dc->ctx->dmub_srv &&
+ bp->base.ctx->dc->debug.dmub_command_table) {
+ transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
+ return BP_RESULT_OK;
+ }
+-#endif
+
+ /*color_depth not used any more, driver has deep color factor in the Phyclk*/
+ if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
+@@ -303,7 +296,6 @@ static void init_set_pixel_clock(struct bios_parser *bp)
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static void set_pixel_clock_dmcub(
+ struct dc_dmub_srv *dmcub,
+ struct set_pixel_clock_parameter_v1_7 *clk)
+@@ -317,7 +309,6 @@ static void set_pixel_clock_dmcub(
+ dc_dmub_srv_cmd_execute(dmcub);
+ dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
+
+ static enum bp_result set_pixel_clock_v7(
+ struct bios_parser *bp,
+@@ -393,13 +384,12 @@ static enum bp_result set_pixel_clock_v7(
+ if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
+ clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (bp->base.ctx->dc->ctx->dmub_srv &&
+ bp->base.ctx->dc->debug.dmub_command_table) {
+ set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
+ return BP_RESULT_OK;
+ }
+-#endif
++
+ if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
+ result = BP_RESULT_OK;
+ }
+@@ -653,7 +643,7 @@ static void init_enable_disp_power_gating(
+ break;
+ }
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ static void enable_disp_power_gating_dmcub(
+ struct dc_dmub_srv *dmcub,
+ struct enable_disp_power_gating_parameters_v2_1 *pwr)
+@@ -667,7 +657,7 @@ static void enable_disp_power_gating_dmcub(
+ dc_dmub_srv_cmd_execute(dmcub);
+ dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
++
+ static enum bp_result enable_disp_power_gating_v2_1(
+ struct bios_parser *bp,
+ enum controller_id crtc_id,
+@@ -687,14 +677,13 @@ static enum bp_result enable_disp_power_gating_v2_1(
+ ps.param.enable =
+ bp->cmd_helper->disp_power_gating_action_to_atom(action);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (bp->base.ctx->dc->ctx->dmub_srv &&
+ bp->base.ctx->dc->debug.dmub_command_table) {
+ enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
+ &ps.param);
+ return BP_RESULT_OK;
+ }
+-#endif
++
+ if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
+ result = BP_RESULT_OK;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 9ddc0124cda1..82d8b4aff88f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -55,10 +55,7 @@
+ #include "hubp.h"
+
+ #include "dc_link_dp.h"
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dc_dmub_srv.h"
+-#endif
+
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+@@ -2403,10 +2400,9 @@ void dc_set_power_state(
+ switch (power_state) {
+ case DC_ACPI_CM_POWER_STATE_D0:
+ dc_resource_state_construct(dc, dc->current_state);
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ if (dc->ctx->dmub_srv)
+ dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
+-#endif
+
+ dc->hwss.init_hw(dc);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 33828f03fe9e..30a2783881d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -112,9 +112,7 @@ struct dc_caps {
+ bool disable_dp_clk_share;
+ bool psp_setup_panel_mode;
+ bool extended_aux_timeout_support;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ bool dmcub_support;
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hw_3d_lut;
+ #endif
+@@ -404,11 +402,9 @@ struct dc_debug_options {
+ unsigned int force_odm_combine; //bit vector based on otg inst
+ unsigned int force_fclk_khz;
+ bool disable_tri_buf;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ bool dmub_offload_enabled;
+ bool dmcub_emulation;
+ bool dmub_command_table; /* for testing only */
+-#endif
+ struct dc_bw_validation_profile bw_val_profile;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool disable_fec;
+@@ -566,10 +562,9 @@ struct dc_init_data {
+ struct dc_bios *vbios_override;
+ enum dce_environment dce_environment;
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dmub_offload_funcs *dmub_if;
+ struct dc_reg_helper_state *dmub_offload;
+-#endif
++
+ struct dc_config flags;
+ uint32_t log_mask;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index adfc6e9b59b1..24e4684034f5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -29,7 +29,6 @@
+ #include "dm_services.h"
+ #include <stdarg.h>
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dc.h"
+ #include "dc_dmub_srv.h"
+
+@@ -97,7 +96,6 @@ static inline void submit_dmub_reg_wait(
+
+ ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
+ }
+-#endif
+
+ struct dc_reg_value_masks {
+ uint32_t value;
+@@ -144,7 +142,6 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static void dmub_flush_buffer_execute(
+ struct dc_reg_helper_state *offload,
+ const struct dc_context *ctx)
+@@ -236,8 +233,6 @@ static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
+ cmd_buf->reg_wait.time_out_us = time_out_us;
+ }
+
+-#endif
+-
+ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ uint32_t addr, int n,
+ uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+@@ -254,12 +249,10 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+
+ va_end(ap);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (ctx->dmub_srv &&
+ ctx->dmub_srv->reg_helper_offload.gather_in_progress)
+ return dmub_reg_value_pack(ctx, addr, &field_value_mask);
+ /* todo: return void so we can decouple code running in driver from register states */
+-#endif
+
+ /* mmio write directly */
+ reg_val = dm_read_reg(ctx, addr);
+@@ -286,13 +279,13 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
+
+ /* mmio write directly */
+ reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ if (ctx->dmub_srv &&
+ ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
+ return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
+ /* todo: return void so we can decouple code running in driver from register states */
+ }
+-#endif
++
+ dm_write_reg(ctx, addr, reg_val);
+ return reg_val;
+ }
+@@ -310,14 +303,12 @@ uint32_t dm_read_reg_func(
+ }
+ #endif
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (ctx->dmub_srv &&
+ ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
+ !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
+ ASSERT(false);
+ return 0;
+ }
+-#endif
+
+ value = cgs_read_register(ctx->cgs_device, address);
+ trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
+@@ -484,14 +475,12 @@ void generic_reg_wait(const struct dc_context *ctx,
+ uint32_t reg_val;
+ int i;
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ if (ctx->dmub_srv &&
+ ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
+ dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
+ delay_between_poll_us * time_out_num_tries);
+ return;
+ }
+-#endif
+
+ /* something is terribly wrong if time out is > 200ms. (5Hz) */
+ ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
+@@ -539,13 +528,12 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
+ uint32_t index)
+ {
+ uint32_t value = 0;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ // when reg read, there should not be any offload.
+ if (ctx->dmub_srv &&
+ ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
+ ASSERT(false);
+ }
+-#endif
+
+ dm_write_reg(ctx, addr_index, index);
+ value = dm_read_reg(ctx, addr_data);
+@@ -584,7 +572,6 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ return reg_val;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ void reg_sequence_start_gather(const struct dc_context *ctx)
+ {
+ /* if reg sequence is supported and enabled, set flag to
+@@ -649,6 +636,3 @@ void reg_sequence_wait_done(const struct dc_context *ctx)
+ dc_dmub_srv_wait_idle(ctx->dmub_srv);
+ }
+ }
+-
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index fb70ed9b351f..7ab7644458e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -48,9 +48,7 @@ struct dc_stream_state;
+ struct dc_link;
+ struct dc_sink;
+ struct dal;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dc_dmub_srv;
+-#endif
+
+ /********************************
+ * Environment definitions
+@@ -112,9 +110,8 @@ struct dc_context {
+ uint32_t dc_sink_id_count;
+ uint32_t dc_stream_id_count;
+ uint64_t fbc_gpu_addr;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dc_dmub_srv *dmub_srv;
+-#endif
++
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ struct cp_psp cp_psp;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index 41a0e53d2ba4..6f1a312c6a5a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -352,9 +352,8 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
+ uint32_t i;
+ struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ REG_SEQ_START();
+-#endif
++
+ for (i = 0 ; i < num; i++) {
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
+@@ -633,10 +632,9 @@ void dpp1_set_degamma(
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ REG_SEQ_SUBMIT();
+ REG_SEQ_WAIT_DONE();
+-#endif
+ }
+
+ void dpp1_degamma_ram_select(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index 8710f3ac2abf..30c025918568 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -457,18 +457,15 @@ static bool optc1_enable_crtc(struct timing_generator *optc)
+ REG_UPDATE(CONTROL,
+ VTG0_ENABLE, 1);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ REG_SEQ_START();
+-#endif
++
+ /* Enable CRTC */
+ REG_UPDATE_2(OTG_CONTROL,
+ OTG_DISABLE_POINT_CNTL, 3,
+ OTG_MASTER_EN, 1);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ REG_SEQ_SUBMIT();
+ REG_SEQ_WAIT_DONE();
+-#endif
+
+ return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 2417d933ef2b..f90031ed58a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -345,10 +345,8 @@ static void mpc20_program_ogam_pwl(
+ uint32_t i;
+ struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ PERF_TRACE();
+ REG_SEQ_START();
+-#endif
+
+ for (i = 0 ; i < num; i++) {
+ REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
+@@ -468,12 +466,11 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
+ ASSERT(!mpc_disabled);
+ ASSERT(!mpc_idle);
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ REG_SEQ_SUBMIT();
+ PERF_TRACE();
+ REG_SEQ_WAIT_DONE();
+ PERF_TRACE();
+-#endif
+ }
+
+ static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 30a246ebe842..5f731c8a6fe1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1699,9 +1699,7 @@ static bool construct(
+ dc->caps.post_blend_color_processing = true;
+ dc->caps.force_dp_tps4_for_cp2520 = true;
+ dc->caps.extended_aux_timeout_support = true;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ dc->caps.dmcub_support = true;
+-#endif
+
+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
+index 0a3891edfd94..968ff1fef486 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
+@@ -40,11 +40,9 @@
+
+ #undef DEPRECATED
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dmub_srv;
+ struct dc_dmub_srv;
+
+-#endif
+ irq_handler_idx dm_register_interrupt(
+ struct dc_context *ctx,
+ struct dc_interrupt_params *int_params,
+@@ -144,14 +142,12 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ uint32_t addr, int n,
+ uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
+
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
+ void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
+
+ void reg_sequence_start_gather(const struct dc_context *ctx);
+ void reg_sequence_start_execute(const struct dc_context *ctx);
+ void reg_sequence_wait_done(const struct dc_context *ctx);
+-#endif
+
+ #define FD(reg_field) reg_field ## __SHIFT, \
+ reg_field ## _MASK
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+index a9a9657c095a..47e307388581 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+@@ -485,8 +485,6 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+ ...);
+
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ /* register offload macros
+ *
+ * instead of MMIO to register directly, in some cases we want
+@@ -505,6 +503,5 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ /* wait for the last REG_SEQ_SUBMIT to finish */
+ #define REG_SEQ_WAIT_DONE() \
+ reg_sequence_wait_done(CTX)
+-#endif
+
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+index f3b844f474fd..e08dfeea24b0 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
++++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+@@ -20,10 +20,8 @@
+ # OTHER DEALINGS IN THE SOFTWARE.
+ #
+
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+ DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
+
+ AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
+
+ AMD_DISPLAY_FILES += $(AMD_DAL_DMUB)
+-endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4334-drm-ttm-bug-fix-for-sproadic-hard-hang-during-closin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4334-drm-ttm-bug-fix-for-sproadic-hard-hang-during-closin.patch
new file mode 100644
index 00000000..a89a6272
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4334-drm-ttm-bug-fix-for-sproadic-hard-hang-during-closin.patch
@@ -0,0 +1,35 @@
+From 5fd1009b6b0a57a3b40f0d4e45f0849be9016772 Mon Sep 17 00:00:00 2001
+From: Rahul Kumar <rahul.kumar1@amd.com>
+Date: Thu, 12 Dec 2019 17:14:08 +0530
+Subject: [PATCH 4334/4736] drm/ttm: bug fix for sproadic hard hang during
+ closing(cttl+c) video playback
+
+Added reservation object as shared resource before adding reservation
+object to fence.
+
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/ttm/ttm_execbuf_util.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c
+index e73ae0d22897..41a8dcaa1163 100644
+--- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c
++++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c
+@@ -202,7 +202,13 @@ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket,
+ list_for_each_entry(entry, list, head) {
+ bo = entry->bo;
+ if (entry->shared)
++ {
++ int r;
++ r = reservation_object_reserve_shared(bo->resv);
++ if (r)
++ return;
+ reservation_object_add_shared_fence(bo->resv, fence);
++ }
+ else
+ reservation_object_add_excl_fence(bo->resv, fence);
+ ttm_bo_add_to_lru(bo);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4335-drm-amdgpu-change-pstate-only-after-all-XGMI-device-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4335-drm-amdgpu-change-pstate-only-after-all-XGMI-device-.patch
new file mode 100644
index 00000000..57eebf50
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4335-drm-amdgpu-change-pstate-only-after-all-XGMI-device-.patch
@@ -0,0 +1,52 @@
+From 911f01258c9fe327b6f6afbf77c693ad5c143505 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 14:10:27 +0800
+Subject: [PATCH 4335/4736] drm/amdgpu: change pstate only after all XGMI
+ device initialized
+
+Pstate settings should be performed after all device of the
+XGMI setup get initialized.
+
+Change-Id: I5c4b3f79fbd60a5ccfb4dc6f94d9e1db6faec694
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 8e35ebdf4e10..beeae2573cb0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2082,9 +2082,6 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
+ if (r)
+ DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
+- /* set to low pstate by default */
+- amdgpu_xgmi_set_pstate(adev, 0);
+-
+ return 0;
+ }
+
+@@ -2196,6 +2193,18 @@ static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
+ r = amdgpu_ib_ring_tests(adev);
+ if (r)
+ DRM_ERROR("ib ring test failed (%d).\n", r);
++
++ /*
++ * set to low pstate by default
++ * This should be performed after all devices from
++ * XGMI finish their initializations. Thus it's moved
++ * to here.
++ * The time delay is 2S. TODO: confirm whether that
++ * is enough for all possible XGMI setups.
++ */
++ r = amdgpu_xgmi_set_pstate(adev, 0);
++ if (r)
++ DRM_ERROR("pstate setting failed (%d).\n", r);
+ }
+
+ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4336-drm-amd-powerplay-update-is_sw_smu_xgmi-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4336-drm-amd-powerplay-update-is_sw_smu_xgmi-check.patch
new file mode 100644
index 00000000..a29b2647
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4336-drm-amd-powerplay-update-is_sw_smu_xgmi-check.patch
@@ -0,0 +1,31 @@
+From 157b0af597dc993edad883b1aa397d73b27fbe81 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 14:29:48 +0800
+Subject: [PATCH 4336/4736] drm/amd/powerplay: update is_sw_smu_xgmi check
+
+Add check for is_sw_smu routine and drop check
+for amdgpu_dpm which seems non-sense.
+
+Change-Id: I2b694a6255a76d35305fc64ca39625730e3463db
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index cda79f0eb822..facc19cae7e5 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -526,7 +526,7 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
+
+ bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
+ {
+- if (amdgpu_dpm != 1)
++ if (!is_support_sw_smu(adev))
+ return false;
+
+ if (adev->asic_type == CHIP_VEGA20)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4337-drm-amd-powerplay-support-xgmi-pstate-setting-on-pow.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4337-drm-amd-powerplay-support-xgmi-pstate-setting-on-pow.patch
new file mode 100644
index 00000000..e92c2cad
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4337-drm-amd-powerplay-support-xgmi-pstate-setting-on-pow.patch
@@ -0,0 +1,164 @@
+From caa363053b29f60ba1174395f0d73f08a10c224a Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 09:41:19 +0800
+Subject: [PATCH 4337/4736] drm/amd/powerplay: support xgmi pstate setting on
+ powerplay routine V2
+
+Add xgmi pstate setting on powerplay routine.
+
+V2: split the change of is_support_sw_smu_xgmi into a separate patch
+
+Change-Id: If1a49aa14c16f133e43ac1298c6b14eaeb44d79d
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 5 +++++
+ drivers/gpu/drm/amd/include/kgd_pp_interface.h | 4 ++++
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 15 +++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 +----
+ 6 files changed, 44 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index ba88acdf87ec..44a0ee91b42d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -285,6 +285,11 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+
+ if (is_support_sw_smu_xgmi(adev))
+ ret = smu_set_xgmi_pstate(&adev->smu, pstate);
++ else if (adev->powerplay.pp_funcs &&
++ adev->powerplay.pp_funcs->set_xgmi_pstate)
++ ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
++ pstate);
++
+ if (ret)
+ dev_err(adev->dev,
+ "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 5902f80d1fce..a7f92d0b3a90 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -220,6 +220,9 @@ enum pp_df_cstate {
+ ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
+ (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
+
++#define XGMI_MODE_PSTATE_D3 0
++#define XGMI_MODE_PSTATE_D0 1
++
+ struct seq_file;
+ enum amd_pp_clock_type;
+ struct amd_pp_simple_clock_info;
+@@ -318,6 +321,7 @@ struct amd_pm_funcs {
+ int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
+ int (*asic_reset_mode_2)(void *handle);
+ int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
++ int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
+ };
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index f4ff15378e61..031447675203 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1566,6 +1566,23 @@ static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
+ return 0;
+ }
+
++static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
++{
++ struct pp_hwmgr *hwmgr = handle;
++
++ if (!hwmgr)
++ return -EINVAL;
++
++ if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
++ return 0;
++
++ mutex_lock(&hwmgr->smu_lock);
++ hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
++ mutex_unlock(&hwmgr->smu_lock);
++
++ return 0;
++}
++
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+ .load_firmware = pp_dpm_load_fw,
+ .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+@@ -1625,4 +1642,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ .asic_reset_mode_2 = pp_asic_reset_mode_2,
+ .smu_i2c_bus_access = pp_smu_i2c_bus_access,
+ .set_df_cstate = pp_set_df_cstate,
++ .set_xgmi_pstate = pp_set_xgmi_pstate,
+ };
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 9295bd90b792..5bcf0d684151 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -4176,6 +4176,20 @@ static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
+ return ret;
+ }
+
++static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
++ uint32_t pstate)
++{
++ int ret;
++
++ ret = smum_send_msg_to_smc_with_parameter(hwmgr,
++ PPSMC_MSG_SetXgmiMode,
++ pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
++ if (ret)
++ pr_err("SetXgmiPstate failed!\n");
++
++ return ret;
++}
++
+ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ /* init/fini related */
+ .backend_init = vega20_hwmgr_backend_init,
+@@ -4245,6 +4259,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ .set_mp1_state = vega20_set_mp1_state,
+ .smu_i2c_bus_access = vega20_smu_i2c_bus_access,
+ .set_df_cstate = vega20_set_df_cstate,
++ .set_xgmi_pstate = vega20_set_xgmi_pstate,
+ };
+
+ int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index bd8c922dfd3e..40403bc76f1b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -356,6 +356,7 @@ struct pp_hwmgr_func {
+ int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
+ int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
+ int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
++ int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
+ };
+
+ struct pp_table_func {
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 7e882999abad..5877857760be 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1463,16 +1463,13 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ return ret;
+ }
+
+-#define XGMI_STATE_D0 1
+-#define XGMI_STATE_D3 0
+-
+ int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+ uint32_t pstate)
+ {
+ int ret = 0;
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetXgmiMode,
+- pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
++ pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
+ return ret;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4338-drm-amdgpu-add-navi14-PCI-ID-for-new-work-station-SK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4338-drm-amdgpu-add-navi14-PCI-ID-for-new-work-station-SK.patch
new file mode 100644
index 00000000..31c79b3a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4338-drm-amdgpu-add-navi14-PCI-ID-for-new-work-station-SK.patch
@@ -0,0 +1,30 @@
+From cd9db8495c22cdb3dea759ed1de45279d0d8b7d3 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Tue, 8 Oct 2019 17:57:00 +0800
+Subject: [PATCH 4338/4736] drm/amdgpu: add navi14 PCI ID for new work station
+ SKU
+
+Add the navi14 PCI device id.
+
+Change-Id: I05ca1343c38f635b7c20341d09e2baf7f28a4a4b
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 97d6103bc023..298f78947048 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1046,6 +1046,7 @@ static const struct pci_device_id pciidlist[] = {
+ {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
++ {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+
+ /* Renoir */
+ {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4339-drm-amdgpu-gpuvm-add-some-additional-comments-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4339-drm-amdgpu-gpuvm-add-some-additional-comments-in-amd.patch
new file mode 100644
index 00000000..1fa8121e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4339-drm-amdgpu-gpuvm-add-some-additional-comments-in-amd.patch
@@ -0,0 +1,48 @@
+From 440816a0d5fc263273fe9fb85d862ea964f99222 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 30 Oct 2019 13:53:27 -0400
+Subject: [PATCH 4339/4736] drm/amdgpu/gpuvm: add some additional comments in
+ amdgpu_vm_update_ptes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+To better clarify what is happening in this function.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index d0604167cd74..7c5d9891d89a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1408,6 +1408,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
+ uint64_t incr, entry_end, pe_start;
+ struct amdgpu_bo *pt;
+
++ /* make sure that the page tables covering the address range are
++ * actually allocated
++ */
+ r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor,
+ params->direct);
+ if (r)
+@@ -1481,7 +1484,12 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
+ } while (frag_start < entry_end);
+
+ if (amdgpu_vm_pt_descendant(adev, &cursor)) {
+- /* Free all child entries */
++ /* Free all child entries.
++ * Update the tables with the flags and addresses and free up subsequent
++ * tables in the case of huge pages or freed up areas.
++ * This is the maximum you can free, because all other page tables are not
++ * completely covered by the range and so potentially still in use.
++ */
+ while (cursor.pfn < frag_start) {
+ amdgpu_vm_free_pts(adev, params->vm, &cursor);
+ amdgpu_vm_pt_next(adev, &cursor);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4340-drm-amdgpu-Show-resolution-correctly-in-mode-validat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4340-drm-amdgpu-Show-resolution-correctly-in-mode-validat.patch
new file mode 100644
index 00000000..e576cc29
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4340-drm-amdgpu-Show-resolution-correctly-in-mode-validat.patch
@@ -0,0 +1,29 @@
+From 7aed231f572bee5c39f28d1002fd490bda296dbf Mon Sep 17 00:00:00 2001
+From: Neil Mayhew <neil@neil.mayhew.name>
+Date: Wed, 30 Oct 2019 12:58:37 -0600
+Subject: [PATCH 4340/4736] drm/amdgpu: Show resolution correctly in mode
+ validation debug output
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Neil Mayhew <neil@neil.mayhew.name>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 5ef3b7e842e4..687d3ea76d4b 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4589,8 +4589,8 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec
+ result = MODE_OK;
+ else
+ DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
+- mode->vdisplay,
+ mode->hdisplay,
++ mode->vdisplay,
+ mode->clock,
+ dc_result);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4341-drm-amd-powerplay-print-the-pptable-provider.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4341-drm-amd-powerplay-print-the-pptable-provider.patch
new file mode 100644
index 00000000..8ab6524d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4341-drm-amd-powerplay-print-the-pptable-provider.patch
@@ -0,0 +1,34 @@
+From 1c03af3ae1ca41e2b70a71aca1c9a0fc0be4eb09 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 30 Oct 2019 11:38:53 +0800
+Subject: [PATCH 4341/4736] drm/amd/powerplay: print the pptable provider
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 5877857760be..9ebc00a97096 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -368,6 +368,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
+ version_major = le16_to_cpu(hdr->header.header_version_major);
+ version_minor = le16_to_cpu(hdr->header.header_version_minor);
+ if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
++ pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
+ switch (version_minor) {
+ case 0:
+ ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
+@@ -384,6 +385,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
+ return ret;
+
+ } else {
++ pr_info("use vbios provided pptable\n");
+ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ powerplayinfo);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4342-drm-amdgpu-discovery-Need-to-free-discovery-memory.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4342-drm-amdgpu-discovery-Need-to-free-discovery-memory.patch
new file mode 100644
index 00000000..463690cf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4342-drm-amdgpu-discovery-Need-to-free-discovery-memory.patch
@@ -0,0 +1,41 @@
+From 9c80bfb3b3f3e6cc8a69b9abc5b6e245653ebe0d Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Mon, 4 Nov 2019 12:45:09 +0800
+Subject: [PATCH 4342/4736] drm/amdgpu/discovery: Need to free discovery memory
+
+When unloading driver, need to free discovery memory.
+
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 9a094e118d96..b5028af50cc2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2216,9 +2216,6 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
+ void *stolen_vga_buf;
+ /* return the VGA stolen memory (if any) back to VRAM */
+ amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
+-
+- /* return the IP Discovery TMR memory back to VRAM */
+- amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
+ }
+
+ /**
+@@ -2231,7 +2228,10 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
+
+ amdgpu_ttm_debugfs_fini(adev);
+ amdgpu_ttm_training_reserve_vram_fini(adev);
++ /* return the IP Discovery TMR memory back to VRAM */
++ amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
+ amdgpu_ttm_fw_reserve_vram_fini(adev);
++
+ if (adev->mman.aper_base_kaddr)
+ iounmap(adev->mman.aper_base_kaddr);
+ adev->mman.aper_base_kaddr = NULL;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4343-drm-sched-Fix-passing-zero-to-PTR_ERR-warning-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4343-drm-sched-Fix-passing-zero-to-PTR_ERR-warning-v2.patch
new file mode 100644
index 00000000..b2642b1a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4343-drm-sched-Fix-passing-zero-to-PTR_ERR-warning-v2.patch
@@ -0,0 +1,49 @@
+From 3bd1ff177e6034a99a519cb3a215576de34b049f Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 29 Oct 2019 11:03:05 -0400
+Subject: [PATCH 4343/4736] drm/sched: Fix passing zero to 'PTR_ERR' warning v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix a static code checker warning.
+
+v2: Drop PTR_ERR_OR_ZERO.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_main.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index cef586235eaf..007abab5dae6 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -498,8 +498,10 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
+ fence = sched->ops->run_job(s_job);
+
+ if (IS_ERR_OR_NULL(fence)) {
++ if (IS_ERR(fence))
++ dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
++
+ s_job->s_fence->parent = NULL;
+- dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+ } else {
+ s_job->s_fence->parent = fence;
+ }
+@@ -741,8 +743,9 @@ static int drm_sched_main(void *param)
+ r);
+ dma_fence_put(fence);
+ } else {
++ if (IS_ERR(fence))
++ dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+
+- dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+ drm_sched_process_job(NULL, &sched_job->cb);
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4344-Revert-drm-amd-display-setting-the-DIG_MODE-to-the-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4344-Revert-drm-amd-display-setting-the-DIG_MODE-to-the-c.patch
new file mode 100644
index 00000000..ebc20c34
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4344-Revert-drm-amd-display-setting-the-DIG_MODE-to-the-c.patch
@@ -0,0 +1,49 @@
+From 7ee3c33cd19d48803b9e88e5bcc787005c06bf41 Mon Sep 17 00:00:00 2001
+From: Zhan Liu <Zhan.Liu@amd.com>
+Date: Mon, 4 Nov 2019 15:46:56 -0400
+Subject: [PATCH 4344/4736] Revert "drm/amd/display: setting the DIG_MODE to
+ the correct value."
+
+This reverts commit 6966609de439ac6ddd4438a468f83ab0a2f36de0.
+
+Reason for revert: Root cause of this issue is found. The workaround is not needed anymore.
+
+Change-Id: I193ea994b8ce5c2828dfc09b36c009546443c7d5
+Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index fad7f3b7bc31..8780020d4f6a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -3025,24 +3025,6 @@ void core_link_enable_stream(
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ COLOR_DEPTH_UNDEFINED);
+
+- /* This second call is needed to reconfigure the DIG
+- * as a workaround for the incorrect value being applied
+- * from transmitter control.
+- */
+- if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+- stream->link->link_enc->funcs->setup(
+- stream->link->link_enc,
+- pipe_ctx->stream->signal);
+-
+- /* This second call is needed to reconfigure the DIG
+- * as a workaround for the incorrect value being applied
+- * from transmitter control.
+- */
+- if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+- stream->link->link_enc->funcs->setup(
+- stream->link->link_enc,
+- pipe_ctx->stream->signal);
+-
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (pipe_ctx->stream->timing.flags.DSC) {
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4345-drm-amdgpu-disallow-direct-upload-save-restore-list-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4345-drm-amdgpu-disallow-direct-upload-save-restore-list-.patch
new file mode 100644
index 00000000..538b953e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4345-drm-amdgpu-disallow-direct-upload-save-restore-list-.patch
@@ -0,0 +1,41 @@
+From d20cea67111506f14662640c257bf93c30900acf Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 4 Nov 2019 16:20:06 +0800
+Subject: [PATCH 4345/4736] drm/amdgpu: disallow direct upload save restore
+ list from gfx driver
+
+Direct uploading save/restore list via mmio register writes breaks the security
+policy. Instead, the driver should pass s&r list to psp.
+
+For all the ASICs that use rlc v2_1 headers, the driver actually upload s&r list
+twice, in non-psp ucode front door loading phase and gfx pg initialization phase.
+The latter is not allowed.
+
+VG12 is the only exception where the driver still keeps legacy approach for S&R
+list uploading. In theory, this can be elimnated if we have valid srcntl ucode
+for VG12.
+
+Change-Id: I8cc8e0126f746aae43b9114e05bc111ee7b23531
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Candice Li <Candice.Li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 005f4d0d2484..d521facadf59 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2728,7 +2728,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
+ * And it's needed by gfxoff feature.
+ */
+ if (adev->gfx.rlc.is_rlc_v2_1) {
+- gfx_v9_1_init_rlc_save_restore_list(adev);
++ if (adev->asic_type == CHIP_VEGA12)
++ gfx_v9_1_init_rlc_save_restore_list(adev);
+ gfx_v9_0_enable_save_restore_machine(adev);
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4346-drm-amd-display-3.2.57.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4346-drm-amd-display-3.2.57.patch
new file mode 100644
index 00000000..072cd612
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4346-drm-amd-display-3.2.57.patch
@@ -0,0 +1,27 @@
+From 4cf028e5c339b1d23e391f098dc237241745d6e3 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Tue, 15 Oct 2019 08:35:14 -0400
+Subject: [PATCH 4346/4736] drm/amd/display: 3.2.57
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 30a2783881d9..d37818730960 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.56"
++#define DC_VER "3.2.57"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4347-drm-amd-display-Fix-assert-observed-when-performing-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4347-drm-amd-display-Fix-assert-observed-when-performing-.patch
new file mode 100644
index 00000000..180f8cfc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4347-drm-amd-display-Fix-assert-observed-when-performing-.patch
@@ -0,0 +1,65 @@
+From 740352c8b0207bd25979c556b1a720e21816f41e Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Sat, 12 Oct 2019 16:18:32 -0400
+Subject: [PATCH 4347/4736] drm/amd/display: Fix assert observed when
+ performing dummy p-state check
+
+[WHY]
+V.Active dram clock change workaround need a small modification for DMLv2
+to ensure that the dummy p-state check doesn't fail.
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 ++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 +
+ 3 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 3c70dd577292..d63ca4ccf7cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2611,9 +2611,13 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ mode_lib->vba.MinActiveDRAMClockChangeMargin
+ + mode_lib->vba.DRAMClockChangeLatency;
+
++
+ if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+ mode_lib->vba.DRAMClockChangeWatermark += 25;
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
++ } else if (mode_lib->vba.DummyPStateCheck &&
++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else {
+ if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 7f9a5621922f..81db8517a690 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -222,6 +222,8 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
+ mode_lib->vba.SRExitTime = soc->sr_exit_time_us;
+ mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
+ mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
++ mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
++
+ mode_lib->vba.Downspreading = soc->downspread_percent;
+ mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes; // new!
+ mode_lib->vba.FabricDatapathToDCNDataReturn = soc->fabric_datapath_to_dcn_data_return_bytes; // new!
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 1540ffbe3979..6c59a332093a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -155,6 +155,7 @@ struct vba_vars_st {
+ double UrgentLatencySupportUsChroma;
+ unsigned int DSCFormatFactor;
+
++ bool DummyPStateCheck;
+ bool PrefetchModeSupported;
+ enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
+ double XFCRemoteSurfaceFlipDelay;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4348-drm-amd-display-Renoir-chroma-viewport-WA.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4348-drm-amd-display-Renoir-chroma-viewport-WA.patch
new file mode 100644
index 00000000..fd823e27
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4348-drm-amd-display-Renoir-chroma-viewport-WA.patch
@@ -0,0 +1,135 @@
+From 4c0ce6590a0b47c2976de8115fafc98bb2fcc375 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Fri, 11 Oct 2019 15:34:20 -0400
+Subject: [PATCH 4348/4736] drm/amd/display: Renoir chroma viewport WA
+
+[Why]
+For unknown reason, immediate flip with host VM translation on NV12
+surface will underflow on last row of PTE.
+
+[How]
+Hack chroma viewport height to make fetch one more row of PTE.
+Note that this will cause hubp underflow on all video underlay
+cases, but the underflow is not user visible since it is in
+blank region.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 65 ++++++++++++++++++-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
+ 3 files changed, 67 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index d37818730960..5d47871ff19c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -421,6 +421,8 @@ struct dc_debug_options {
+ bool cm_in_bypass;
+ #endif
+ int force_clock_mode;/*every mode change.*/
++
++ bool nv12_iflip_vm_wa;
+ };
+
+ struct dc_debug_data {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 2f5a5867e674..1ddd6ae22155 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -164,6 +164,69 @@ static void hubp21_setup(
+
+ }
+
++void hubp21_set_viewport(
++ struct hubp *hubp,
++ const struct rect *viewport,
++ const struct rect *viewport_c)
++{
++ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++ int patched_viewport_height = 0;
++ struct dc_debug_options *debug = &hubp->ctx->dc->debug;
++
++ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
++ PRI_VIEWPORT_WIDTH, viewport->width,
++ PRI_VIEWPORT_HEIGHT, viewport->height);
++
++ REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
++ PRI_VIEWPORT_X_START, viewport->x,
++ PRI_VIEWPORT_Y_START, viewport->y);
++
++ /*for stereo*/
++ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
++ SEC_VIEWPORT_WIDTH, viewport->width,
++ SEC_VIEWPORT_HEIGHT, viewport->height);
++
++ REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
++ SEC_VIEWPORT_X_START, viewport->x,
++ SEC_VIEWPORT_Y_START, viewport->y);
++
++ /*
++ * Work around for underflow issue with NV12 + rIOMMU translation
++ * + immediate flip. This will cause hubp underflow, but will not
++ * be user visible since underflow is in blank region
++ */
++ patched_viewport_height = viewport_c->height;
++ if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) {
++ int pte_row_height = 0;
++ int pte_rows = 0;
++
++ REG_GET(DCHUBP_REQ_SIZE_CONFIG,
++ PTE_ROW_HEIGHT_LINEAR, &pte_row_height);
++
++ pte_row_height = 1 << (pte_row_height + 3);
++ pte_rows = (viewport_c->height + pte_row_height - 1) / pte_row_height;
++ patched_viewport_height = pte_rows * pte_row_height + 3;
++ }
++
++
++ /* DC supports NV12 only at the moment */
++ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
++ PRI_VIEWPORT_WIDTH_C, viewport_c->width,
++ PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);
++
++ REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
++ PRI_VIEWPORT_X_START_C, viewport_c->x,
++ PRI_VIEWPORT_Y_START_C, viewport_c->y);
++
++ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
++ SEC_VIEWPORT_WIDTH_C, viewport_c->width,
++ SEC_VIEWPORT_HEIGHT_C, patched_viewport_height);
++
++ REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
++ SEC_VIEWPORT_X_START_C, viewport_c->x,
++ SEC_VIEWPORT_Y_START_C, viewport_c->y);
++}
++
+ void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
+ struct vm_system_aperture_param *apt)
+ {
+@@ -211,7 +274,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
+ .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
+ .set_blank = hubp1_set_blank,
+ .dcc_control = hubp1_dcc_control,
+- .mem_program_viewport = min_set_viewport,
++ .mem_program_viewport = hubp21_set_viewport,
+ .set_cursor_attributes = hubp2_cursor_set_attributes,
+ .set_cursor_position = hubp1_cursor_set_position,
+ .hubp_clk_cntl = hubp1_clk_cntl,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 5f731c8a6fe1..e9db35c24073 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -831,6 +831,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ .scl_reset_length10 = true,
+ .sanity_checks = true,
+ .disable_48mhz_pwrdwn = false,
++ .nv12_iflip_vm_wa = true
+ };
+
+ static const struct dc_debug_options debug_defaults_diags = {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4349-drm-amd-display-Use-SIGNAL_TYPE_NONE-in-disable_outp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4349-drm-amd-display-Use-SIGNAL_TYPE_NONE-in-disable_outp.patch
new file mode 100644
index 00000000..6bb117e3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4349-drm-amd-display-Use-SIGNAL_TYPE_NONE-in-disable_outp.patch
@@ -0,0 +1,39 @@
+From cd43ff2a1e13dbf27001284939bbe66f75cd5c73 Mon Sep 17 00:00:00 2001
+From: Sung Lee <sung.lee@amd.com>
+Date: Wed, 16 Oct 2019 10:24:01 -0400
+Subject: [PATCH 4349/4736] drm/amd/display: Use SIGNAL_TYPE_NONE in
+ disable_output unless eDP
+
+[WHY]
+Currently made a change where disable_output is called using signal_type.
+Using actual signal_type when calilng disable_output in power_down_encoders
+would make DP to HDMI dongle not light up on boot. As it would have signal_type
+SIGNAL_TYPE_DISPLAY_PORT.
+
+[HOW]
+Set signal_type to SIGNAL_TYPE_NONE unless it is eDP.
+
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 0d171874ef4e..050634926263 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1435,6 +1435,9 @@ static void power_down_encoders(struct dc *dc)
+ if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
+ dp_receiver_power_ctrl(dc->links[i], false);
+
++ if (signal != SIGNAL_TYPE_EDP)
++ signal = SIGNAL_TYPE_NONE;
++
+ dc->links[i]->link_enc->funcs->disable_output(
+ dc->links[i]->link_enc, signal);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4350-drm-amd-display-Add-a-sanity-check-for-DSC-already-e.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4350-drm-amd-display-Add-a-sanity-check-for-DSC-already-e.patch
new file mode 100644
index 00000000..3c3c7009
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4350-drm-amd-display-Add-a-sanity-check-for-DSC-already-e.patch
@@ -0,0 +1,71 @@
+From 37d0bb62a1186bd5e2141900ad1431e93f2823d5 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Wed, 16 Oct 2019 14:34:15 -0400
+Subject: [PATCH 4350/4736] drm/amd/display: Add a sanity check for DSC already
+ enabled/disabled
+
+[why]
+If acquire/release DSC resource sequence is affected by a regression,
+it can happen that the already-in-use DSC HW block is being wrongly
+re-used for a different pipe. The reverse is also possible, i.e.
+already-disabled DSC HW block could be disabled from other context.
+
+[how]
+Read back the enable state of DSC HW and report an error if duplicate
+enable or disable was attempted.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 25 ++++++++++++++++---
+ 1 file changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index 63eb377ed9c0..dc9944427d2f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -222,9 +222,18 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
+ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
+ {
+ struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
++ int dsc_clock_en;
++ int dsc_fw_config;
++ int enabled_opp_pipe;
+
+- /* TODO Check if DSC alreay in use? */
+- DC_LOG_DSC("enable DSC at opp pipe %d", opp_pipe);
++ DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
++
++ REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
++ REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
++ if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
++ DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
++ ASSERT(0);
++ }
+
+ REG_UPDATE(DSC_TOP_CONTROL,
+ DSC_CLOCK_EN, 1);
+@@ -238,8 +247,18 @@ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
+ static void dsc2_disable(struct display_stream_compressor *dsc)
+ {
+ struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
++ int dsc_clock_en;
++ int dsc_fw_config;
++ int enabled_opp_pipe;
+
+- DC_LOG_DSC("disable DSC");
++ DC_LOG_DSC("disable DSC %d", dsc->inst);
++
++ REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
++ REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
++ if (!dsc_clock_en || !dsc_fw_config) {
++ DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe);
++ ASSERT(0);
++ }
+
+ REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
+ DSCRM_DSC_FORWARD_EN, 0);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4351-drm-amd-display-set-MSA-MISC1-bit-6-while-sending-co.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4351-drm-amd-display-set-MSA-MISC1-bit-6-while-sending-co.patch
new file mode 100644
index 00000000..ea3cb010
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4351-drm-amd-display-set-MSA-MISC1-bit-6-while-sending-co.patch
@@ -0,0 +1,322 @@
+From d8379d6b42cb6e6610e4dbbf643c1ea87666dd42 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Wed, 16 Oct 2019 23:44:55 -0400
+Subject: [PATCH 4351/4736] drm/amd/display: set MSA MISC1 bit 6 while sending
+ colorimetry in VSC SDP
+
+[Why]
+It is confusing to sinks if we send VSC SDP only on some format. Today we
+signal colorimetry format using MSA while in formats like sRGB.
+But when we switch to BT2020 we set the bit to ignore MSA colorimetry and
+instead use the colorimetry information in the VSC SDP.
+
+But if sink supports signaling of colorimetry via VSC SDP we should always
+set the MSA MISC1 bit 6, instead of doing so selectively.
+
+[How]
+If sink supports signaling of colorimetry via VSC SDP, and we are sending
+the colorimetry info via VSC SDP with packet revision 05h, then always
+set MSA MISC1 bit 6.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 +
+ .../amd/display/dc/dce/dce_stream_encoder.c | 1 +
+ .../display/dc/dcn10/dcn10_stream_encoder.c | 6 +--
+ .../display/dc/dcn10/dcn10_stream_encoder.h | 1 +
+ .../display/dc/dcn20/dcn20_stream_encoder.c | 7 ++-
+ .../display/dc/dcn20/dcn20_stream_encoder.h | 1 +
+ .../amd/display/dc/inc/hw/stream_encoder.h | 1 +
+ .../dc/virtual/virtual_stream_encoder.c | 1 +
+ .../amd/display/modules/inc/mod_info_packet.h | 4 +-
+ .../display/modules/info_packet/info_packet.c | 46 +++++++++++++++----
+ 12 files changed, 57 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 687d3ea76d4b..2f31cbd164d9 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4081,7 +4081,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ struct dmcu *dmcu = core_dc->res_pool->dmcu;
+
+ stream->psr_version = dmcu->dmcu_version.psr_version;
+- mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
++ mod_build_vsc_infopacket(stream,
++ &stream->vsc_infopacket,
++ &stream->use_vsc_sdp_for_colorimetry);
+ }
+ }
+ finish:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 8780020d4f6a..a014d47f0f37 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2944,6 +2944,7 @@ void core_link_enable_stream(
+ pipe_ctx->stream_res.stream_enc,
+ &stream->timing,
+ stream->output_color_space,
++ stream->use_vsc_sdp_for_colorimetry,
+ stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
+
+ if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index fdb6adc37857..f8c07d5a4054 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -164,6 +164,7 @@ struct dc_stream_state {
+
+ enum view_3d_format view_format;
+
++ bool use_vsc_sdp_for_colorimetry;
+ bool ignore_msa_timing_param;
+ bool converter_disable_audio;
+ uint8_t qs_bit;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+index 9205fb2e08bd..544a13f2d368 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+@@ -273,6 +273,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
++ bool use_vsc_sdp_for_colorimetry,
+ uint32_t enable_sdp_splitting)
+ {
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index f10c1554ec01..5b4e5b6bfa41 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -246,6 +246,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
++ bool use_vsc_sdp_for_colorimetry,
+ uint32_t enable_sdp_splitting)
+ {
+ uint32_t h_active_start;
+@@ -311,10 +312,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
+ * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
+ * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
+ */
+- if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
+- (output_color_space == COLOR_SPACE_2020_YCBCR) ||
+- (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
+- (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
++ if (use_vsc_sdp_for_colorimetry)
+ misc1 = misc1 | 0x40;
+ else
+ misc1 = misc1 & ~0x40;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index c9cbc21d121e..2f00f2389e40 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -526,6 +526,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
++ bool use_vsc_sdp_for_colorimetry,
+ uint32_t enable_sdp_splitting);
+
+ void enc1_stream_encoder_hdmi_set_stream_attribute(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 412d3032e4ef..d60d072848ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -531,11 +531,16 @@ void enc2_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
++ bool use_vsc_sdp_for_colorimetry,
+ uint32_t enable_sdp_splitting)
+ {
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+- enc1_stream_encoder_dp_set_stream_attribute(enc, crtc_timing, output_color_space, enable_sdp_splitting);
++ enc1_stream_encoder_dp_set_stream_attribute(enc,
++ crtc_timing,
++ output_color_space,
++ use_vsc_sdp_for_colorimetry,
++ enable_sdp_splitting);
+
+ REG_UPDATE(DP_SEC_FRAMING4,
+ DP_SST_SDP_SPLITTING, enable_sdp_splitting);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+index 3f94a9f13c4a..d2a805bd4573 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+@@ -98,6 +98,7 @@ void enc2_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
++ bool use_vsc_sdp_for_colorimetry,
+ uint32_t enable_sdp_splitting);
+
+ void enc2_stream_encoder_dp_unblank(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index 6305e388612a..c0b93d51ca8d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -126,6 +126,7 @@ struct stream_encoder_funcs {
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
++ bool use_vsc_sdp_for_colorimetry,
+ uint32_t enable_sdp_splitting);
+
+ void (*hdmi_set_stream_attribute)(
+diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+index 0c6d502da8a6..b37db73478eb 100644
+--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+@@ -30,6 +30,7 @@ static void virtual_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
++ bool use_vsc_sdp_for_colorimetry,
+ uint32_t enable_sdp_splitting) {}
+
+ static void virtual_stream_encoder_hdmi_set_stream_attribute(
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+index ca8ce3c55337..42cbeffac640 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+@@ -26,6 +26,7 @@
+ #ifndef MOD_INFO_PACKET_H_
+ #define MOD_INFO_PACKET_H_
+
++#include "dm_services.h"
+ #include "mod_shared.h"
+ //Forward Declarations
+ struct dc_stream_state;
+@@ -33,7 +34,8 @@ struct dc_info_packet;
+ struct mod_vrr_params;
+
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+- struct dc_info_packet *info_packet);
++ struct dc_info_packet *info_packet,
++ bool *use_vsc_sdp_for_colorimetry);
+
+ void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
+ struct dc_info_packet *info_packet, int ALLMEnabled, int ALLMValue);
+diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+index db6b08f6d093..6a8a056424b8 100644
+--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
++++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+@@ -30,6 +30,20 @@
+ #include "mod_freesync.h"
+ #include "dc.h"
+
++enum vsc_packet_revision {
++ vsc_packet_undefined = 0,
++ //01h = VSC SDP supports only 3D stereo.
++ vsc_packet_rev1 = 1,
++ //02h = 3D stereo + PSR.
++ vsc_packet_rev2 = 2,
++ //03h = 3D stereo + PSR2.
++ vsc_packet_rev3 = 3,
++ //04h = 3D stereo + PSR/PSR2 + Y-coordinate.
++ vsc_packet_rev4 = 4,
++ //05h = 3D stereo + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format
++ vsc_packet_rev5 = 5,
++};
++
+ #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
+ #define HF_VSIF_VERSION 1
+
+@@ -116,35 +130,41 @@ enum ColorimetryYCCDP {
+ };
+
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+- struct dc_info_packet *info_packet)
++ struct dc_info_packet *info_packet,
++ bool *use_vsc_sdp_for_colorimetry)
+ {
+- unsigned int vscPacketRevision = 0;
++ unsigned int vsc_packet_revision = vsc_packet_undefined;
+ unsigned int i;
+ unsigned int pixelEncoding = 0;
+ unsigned int colorimetryFormat = 0;
+ bool stereo3dSupport = false;
+
++ /* Initialize first, later if infopacket is valid determine if VSC SDP
++ * should be used to signal colorimetry format and pixel encoding.
++ */
++ *use_vsc_sdp_for_colorimetry = false;
++
+ if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {
+- vscPacketRevision = 1;
++ vsc_packet_revision = vsc_packet_rev1;
+ stereo3dSupport = true;
+ }
+
+ /*VSC packet set to 2 when DP revision >= 1.2*/
+ if (stream->psr_version != 0)
+- vscPacketRevision = 2;
++ vsc_packet_revision = vsc_packet_rev2;
+
+ /* Update to revision 5 for extended colorimetry support for DPCD 1.4+ */
+ if (stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
+ stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
+- vscPacketRevision = 5;
++ vsc_packet_revision = vsc_packet_rev5;
+
+ /* VSC packet not needed based on the features
+ * supported by this DP display
+ */
+- if (vscPacketRevision == 0)
++ if (vsc_packet_revision == vsc_packet_undefined)
+ return;
+
+- if (vscPacketRevision == 0x2) {
++ if (vsc_packet_revision == vsc_packet_rev2) {
+ /* Secondary-data Packet ID = 0*/
+ info_packet->hb0 = 0x00;
+ /* 07h - Packet Type Value indicating Video
+@@ -166,7 +186,7 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ info_packet->valid = true;
+ }
+
+- if (vscPacketRevision == 0x1) {
++ if (vsc_packet_revision == vsc_packet_rev1) {
+
+ info_packet->hb0 = 0x00; // Secondary-data Packet ID = 0
+ info_packet->hb1 = 0x07; // 07h = Packet Type Value indicating Video Stream Configuration packet
+@@ -237,7 +257,7 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ * the Pixel Encoding/Colorimetry Format and that a Sink device must ignore MISC1, bit 7, and
+ * MISC0, bits 7:1 (MISC1, bit 7. and MISC0, bits 7:1 become "don't care").)
+ */
+- if (vscPacketRevision == 0x5) {
++ if (vsc_packet_revision == vsc_packet_rev5) {
+ /* Secondary-data Packet ID = 0 */
+ info_packet->hb0 = 0x00;
+ /* 07h - Packet Type Value indicating Video Stream Configuration packet */
+@@ -249,6 +269,13 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+
+ info_packet->valid = true;
+
++ /* If we are using VSC SDP revision 05h, use this to signal for
++ * colorimetry format and pixel encoding. HW should later be
++ * programmed to set MSA MISC1 bit 6 to indicate ignore
++ * colorimetry format and pixel encoding in the MSA.
++ */
++ *use_vsc_sdp_for_colorimetry = true;
++
+ /* Set VSC SDP fields for pixel encoding and colorimetry format from DP 1.3 specs
+ * Data Bytes DB 18~16
+ * Bits 3:0 (Colorimetry Format) | Bits 7:4 (Pixel Encoding)
+@@ -393,7 +420,6 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ */
+ info_packet->sb[18] = 0;
+ }
+-
+ }
+
+ /**
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4352-drm-amd-display-Create-debug-option-to-disable-v.act.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4352-drm-amd-display-Create-debug-option-to-disable-v.act.patch
new file mode 100644
index 00000000..28390086
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4352-drm-amd-display-Create-debug-option-to-disable-v.act.patch
@@ -0,0 +1,126 @@
+From 1125f87a7e9aa35f7a84916c067faf57784eca38 Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Tue, 1 Oct 2019 18:29:56 -0400
+Subject: [PATCH 4352/4736] drm/amd/display: Create debug option to disable
+ v.active clock change policy.
+
+[WHY]
+It has been a useful option in debugging GFXOFF and P.State Change issues.
+May be required as for platform specific workaround.
+
+[HOW]
+Create option in enum dc_debug_options, "disable_vactive_clock_change".
+When it is set, dm_dram_clock_change_vactive, will translate into
+p_state_change_support: false.
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ++-
+ .../drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 6 +++---
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 ++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 +
+ 7 files changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 5d47871ff19c..cc45d77a3b0d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -423,6 +423,7 @@ struct dc_debug_options {
+ int force_clock_mode;/*every mode change.*/
+
+ bool nv12_iflip_vm_wa;
++ bool disable_dram_clock_change_vactive_support;
+ };
+
+ struct dc_debug_data {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index ef43faa09eb3..19a4838b1ac2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2848,6 +2848,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ bool full_pstate_supported = false;
+ bool dummy_pstate_supported = false;
+ double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
++ context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = dc->debug.disable_dram_clock_change_vactive_support;
+
+ if (fast_validate)
+ return dcn20_validate_bandwidth_internal(dc, context, true);
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+index 6c6c486b774a..77b7574c63cb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+@@ -2577,7 +2577,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
+ mode_lib->vba.MinActiveDRAMClockChangeMargin
+ + mode_lib->vba.DRAMClockChangeLatency;
+
+- if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++ if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+ mode_lib->vba.DRAMClockChangeWatermark += 25;
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index d63ca4ccf7cf..62dfd36d830a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2611,12 +2611,12 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ mode_lib->vba.MinActiveDRAMClockChangeMargin
+ + mode_lib->vba.DRAMClockChangeLatency;
+
+-
+- if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++ if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+ mode_lib->vba.DRAMClockChangeWatermark += 25;
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else if (mode_lib->vba.DummyPStateCheck &&
+- mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else {
+ if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index cfacd6027467..19356180cbb6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -112,6 +112,7 @@ struct _vcs_dpi_soc_bounding_box_st {
+ bool do_urgent_latency_adjustment;
+ double urgent_latency_adjustment_fabric_clock_component_us;
+ double urgent_latency_adjustment_fabric_clock_reference_mhz;
++ bool disable_dram_clock_change_vactive_support;
+ };
+
+ struct _vcs_dpi_ip_params_st {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 81db8517a690..da5e9d2fd6b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -223,6 +223,8 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
+ mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
+ mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
+ mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
++ mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
++ mode_lib->vba.DummyPStateCheck;
+
+ mode_lib->vba.Downspreading = soc->downspread_percent;
+ mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes; // new!
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 6c59a332093a..6d8b5c61de68 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -156,6 +156,7 @@ struct vba_vars_st {
+ unsigned int DSCFormatFactor;
+
+ bool DummyPStateCheck;
++ bool DRAMClockChangeSupportsVActive;
+ bool PrefetchModeSupported;
+ enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
+ double XFCRemoteSurfaceFlipDelay;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4353-drm-amd-display-optimize-bandwidth-after-commit-stre.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4353-drm-amd-display-optimize-bandwidth-after-commit-stre.patch
new file mode 100644
index 00000000..9e03049e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4353-drm-amd-display-optimize-bandwidth-after-commit-stre.patch
@@ -0,0 +1,43 @@
+From a61b8b1bfca590518f760c50ff81a31421e080d3 Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Fri, 18 Oct 2019 18:24:59 -0400
+Subject: [PATCH 4353/4736] drm/amd/display: optimize bandwidth after commit
+ streams.
+
+[Why]
+System is unable to enter S0i3 due to DISPLAY_OFF_MASK not asserted
+in SMU.
+
+[How]
+Optimized bandwidth should be called paired and to resolve unplug
+display underflow issue, optimize bandwidth after commit streams is
+moved to next page flip, in case of S0i3, there is a change for no
+flip coming causing display count is 1 in SMU side.
+Add optimize bandwidth after commit stream.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 82d8b4aff88f..0c7925c2faf2 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1239,6 +1239,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+
+ dc_enable_stereo(dc, context, dc_streams, context->stream_count);
+
++ if (!dc->optimize_seamless_boot)
++ /* pplib is notified if disp_num changed */
++ dc->hwss.optimize_bandwidth(dc, context);
++
+ for (i = 0; i < context->stream_count; i++)
+ context->streams[i]->mode_changed = false;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4354-drm-amd-powerplay-fix-deadlock-on-setting-power_dpm_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4354-drm-amd-powerplay-fix-deadlock-on-setting-power_dpm_.patch
new file mode 100644
index 00000000..7a99a798
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4354-drm-amd-powerplay-fix-deadlock-on-setting-power_dpm_.patch
@@ -0,0 +1,62 @@
+From 78141a8d63f703a2b0cfd29654c6a884f971fb92 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 6 Nov 2019 12:40:12 +0800
+Subject: [PATCH 4354/4736] drm/amd/powerplay: fix deadlock on setting
+ power_dpm_force_performance_level
+
+smu_enable_umd_pstate() will try to get the smu->mutex which was already
+hold by its parent API smu_force_performance_level() on the call path.
+Thus deadlock happens.
+
+Change-Id: Ic4d3c7d06eb47eab2ea42b98f399cd95ab320f0c
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 ++++++++++++++-----
+ 1 file changed, 14 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index facc19cae7e5..c21fe7ac5df8 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -383,14 +383,25 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
+ return true;
+ }
+
+-
++/**
++ * smu_dpm_set_power_gate - power gate/ungate the specific IP block
++ *
++ * @smu: smu_context pointer
++ * @block_type: the IP block to power gate/ungate
++ * @gate: to power gate if true, ungate otherwise
++ *
++ * This API uses no smu->mutex lock protection due to:
++ * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
++ * This is guarded to be race condition free by the caller.
++ * 2. Or get called on user setting request of power_dpm_force_performance_level.
++ * Under this case, the smu->mutex lock protection is already enforced on
++ * the parent API smu_force_performance_level of the call path.
++ */
+ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ bool gate)
+ {
+ int ret = 0;
+
+- mutex_lock(&smu->mutex);
+-
+ switch (block_type) {
+ case AMD_IP_BLOCK_TYPE_UVD:
+ ret = smu_dpm_set_uvd_enable(smu, gate);
+@@ -408,8 +419,6 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ break;
+ }
+
+- mutex_unlock(&smu->mutex);
+-
+ return ret;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4355-drm-amd-display-3.2.58.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4355-drm-amd-display-3.2.58.patch
new file mode 100644
index 00000000..37485b70
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4355-drm-amd-display-3.2.58.patch
@@ -0,0 +1,27 @@
+From e93daa22dd3f9d8d7a86d3e3854769b0e5c0749b Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 21 Oct 2019 08:16:22 -0400
+Subject: [PATCH 4355/4736] drm/amd/display: 3.2.58
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index cc45d77a3b0d..f12ad4b17781 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.57"
++#define DC_VER "3.2.58"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch
new file mode 100644
index 00000000..e42c4852
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch
@@ -0,0 +1,221 @@
+From e2e1baab88fd4354ab464cfe6ed1c5097b8ce421 Mon Sep 17 00:00:00 2001
+From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
+Date: Fri, 6 Sep 2019 09:49:19 -0400
+Subject: [PATCH 4356/4736] drm/amd/display: Add some hardware status in DTN
+ log debugfs
+
+[Why]
+For debug purpose, we need to check the following hardware status
+in DTN log debugfs:
+1.dpp & hubp clock enable;
+2.crtc blank enable;
+3.link phy status;
+
+[How]
+Add the upper information in the amdgpu_dm_dtn_log debugfs.
+
+For CRTC blanked status, since DCN2 and greater reports it on the OPP
+instead of OTG, we patch it in after calling optc1_read_otg_states.
+Ideally, this should be done in the DCN version specific function hooks.
+It has been left as a TODO item.
+
+Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
+Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 ++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 1 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 43 +++++++++++++------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 1 +
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 1 +
+ .../amd/display/dc/dcn20/dcn20_link_encoder.c | 1 +
+ .../drm/amd/display/dc/inc/hw/link_encoder.h | 1 +
+ 7 files changed, 37 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 14d1be6c66e6..5aeee938605a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -1014,6 +1014,9 @@ void hubp1_read_state_common(struct hubp *hubp)
+ HUBP_TTU_DISABLE, &s->ttu_disable,
+ HUBP_UNDERFLOW_STATUS, &s->underflow_status);
+
++ REG_GET(HUBP_CLK_CNTL,
++ HUBP_CLOCK_ENABLE, &s->clock_en);
++
+ REG_GET(DCN_GLOBAL_TTU_CNTL,
+ MIN_TTU_VBLANK, &s->min_ttu_vblank);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index ae70d9c0aa1d..e65e76f018e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -670,6 +670,7 @@ struct dcn_hubp_state {
+ uint32_t sw_mode;
+ uint32_t dcc_en;
+ uint32_t blank_en;
++ uint32_t clock_en;
+ uint32_t underflow_status;
+ uint32_t ttu_disable;
+ uint32_t min_ttu_vblank;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 6d84239af593..4b6213d3ecbf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -128,9 +128,8 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
+ struct resource_pool *pool = dc->res_pool;
+ int i;
+
+- DTN_INFO("HUBP: format addr_hi width height"
+- " rot mir sw_mode dcc_en blank_en ttu_dis underflow"
+- " min_ttu_vblank qos_low_wm qos_high_wm\n");
++ DTN_INFO(
++ "HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en clock_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm\n");
+ for (i = 0; i < pool->pipe_count; i++) {
+ struct hubp *hubp = pool->hubps[i];
+ struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
+@@ -138,8 +137,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
+ hubp->funcs->hubp_read_state(hubp);
+
+ if (!s->blank_en) {
+- DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
+- " %6d %8d %7d %8xh",
++ DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh %6d %8d %8d %7d %8xh",
+ hubp->inst,
+ s->pixel_format,
+ s->inuse_addr_hi,
+@@ -150,6 +148,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
+ s->sw_mode,
+ s->dcc_en,
+ s->blank_en,
++ s->clock_en,
+ s->ttu_disable,
+ s->underflow_status);
+ DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
+@@ -307,21 +306,35 @@ void dcn10_log_hw_state(struct dc *dc,
+ }
+ DTN_INFO("\n");
+
+- DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
+- " h_bs h_be h_ss h_se hpol htot vtot underflow\n");
++ DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel h_bs h_be h_ss h_se hpol htot vtot underflow blank_en\n");
+
+ for (i = 0; i < pool->timing_generator_count; i++) {
+ struct timing_generator *tg = pool->timing_generators[i];
+ struct dcn_otg_state s = {0};
+-
++ /* Read shared OTG state registers for all DCNx */
+ optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ /*
++ * For DCN2 and greater, a register on the OPP is used to
++ * determine if the CRTC is blanked instead of the OTG. So use
++ * dpg_is_blanked() if exists, otherwise fallback on otg.
++ *
++ * TODO: Implement DCN-specific read_otg_state hooks.
++ */
++ if (pool->opps[i]->funcs->dpg_is_blanked)
++ s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);
++ else
++ s.blank_enabled = tg->funcs->is_blanked(tg);
++#else
++ s.blank_enabled = tg->funcs->is_blanked(tg);
++#endif
++
+ //only print if OTG master is enabled
+ if ((s.otg_enabled & 1) == 0)
+ continue;
+
+- DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
+- " %5d %5d %5d %5d %9d\n",
++ DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d %5d %5d %5d %5d %9d %8d\n",
+ tg->inst,
+ s.v_blank_start,
+ s.v_blank_end,
+@@ -339,7 +352,8 @@ void dcn10_log_hw_state(struct dc *dc,
+ s.h_sync_a_pol,
+ s.h_total,
+ s.v_total,
+- s.underflow_occurred_status);
++ s.underflow_occurred_status,
++ s.blank_enabled);
+
+ // Clear underflow for debug purposes
+ // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
+@@ -386,7 +400,7 @@ void dcn10_log_hw_state(struct dc *dc,
+ }
+ DTN_INFO("\n");
+
+- DTN_INFO("L_ENC: DPHY_FEC_EN DPHY_FEC_READY_SHADOW DPHY_FEC_ACTIVE_STATUS\n");
++ DTN_INFO("L_ENC: DPHY_FEC_EN DPHY_FEC_READY_SHADOW DPHY_FEC_ACTIVE_STATUS DP_LINK_TRAINING_COMPLETE\n");
+ for (i = 0; i < dc->link_count; i++) {
+ struct link_encoder *lenc = dc->links[i]->link_enc;
+
+@@ -394,11 +408,12 @@ void dcn10_log_hw_state(struct dc *dc,
+
+ if (lenc->funcs->read_state) {
+ lenc->funcs->read_state(lenc, &s);
+- DTN_INFO("[%-3d]: %-12d %-22d %-22d\n",
++ DTN_INFO("[%-3d]: %-12d %-22d %-22d %-25d\n",
+ i,
+ s.dphy_fec_en,
+ s.dphy_fec_ready_shadow,
+- s.dphy_fec_active_status);
++ s.dphy_fec_active_status,
++ s.dp_link_training_complete);
+ DTN_INFO("\n");
+ }
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index 5be042acf9fa..8249b4429186 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -404,6 +404,7 @@ static const struct opp_funcs dcn10_opp_funcs = {
+ .opp_pipe_clock_control = opp1_pipe_clock_control,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .opp_set_disp_pattern_generator = NULL,
++ .dpg_is_blanked = NULL,
+ #endif
+ .opp_destroy = opp1_destroy
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index c8d795b335ba..4476bc8cdb4d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -542,6 +542,7 @@ struct dcn_otg_state {
+ uint32_t h_total;
+ uint32_t underflow_occurred_status;
+ uint32_t otg_enabled;
++ uint32_t blank_enabled;
+ };
+
+ void optc1_read_otg_state(struct optc *optc1,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+index e476f27aa3a9..0e0306d84cd8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+@@ -203,6 +203,7 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
+ REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
+ REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
+ REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
++ REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
+ }
+ #endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+index b21909216fb6..af57751ed8a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+@@ -124,6 +124,7 @@ struct link_enc_state {
+ uint32_t dphy_fec_en;
+ uint32_t dphy_fec_ready_shadow;
+ uint32_t dphy_fec_active_status;
++ uint32_t dp_link_training_complete;
+
+ };
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4357-drm-amd-display-add-oem-i2c-implemenation-in-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4357-drm-amd-display-add-oem-i2c-implemenation-in-dc.patch
new file mode 100644
index 00000000..0c38cf27
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4357-drm-amd-display-add-oem-i2c-implemenation-in-dc.patch
@@ -0,0 +1,413 @@
+From 58809698c7d678019f04e162634cf3750c3cb60b Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Fri, 2 Aug 2019 17:22:57 -0400
+Subject: [PATCH 4357/4736] drm/amd/display: add oem i2c implemenation in dc
+
+[why]
+Need it for some OEM I2C devices in Nv10
+
+[how]
+Link up code to parse OEM table and expose DC interface
+to access the pins
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../drm/amd/display/dc/bios/bios_parser2.c | 63 ++++++++++++-------
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 11 ++++
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 5 +-
+ drivers/gpu/drm/amd/display/dc/dc_link.h | 4 ++
+ drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c | 19 +++---
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_sw.c | 43 -------------
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_sw.h | 6 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 15 +++++
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.c | 12 ++++
+ .../gpu/drm/amd/display/dc/inc/core_types.h | 2 +
+ .../display/include/grph_object_ctrl_defs.h | 3 +-
+ 11 files changed, 100 insertions(+), 83 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index b4bbfb7bde12..3e2f21af2be7 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -292,11 +292,21 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
+ struct atom_display_object_path_v2 *object;
+ struct atom_common_record_header *header;
+ struct atom_i2c_record *record;
++ struct atom_i2c_record dummy_record = {0};
+ struct bios_parser *bp = BP_FROM_DCB(dcb);
+
+ if (!info)
+ return BP_RESULT_BADINPUT;
+
++ if (id.type == OBJECT_TYPE_GENERIC) {
++ dummy_record.i2c_id = id.id;
++
++ if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
++ return BP_RESULT_OK;
++ else
++ return BP_RESULT_NORECORD;
++ }
++
+ object = get_bios_object(bp, id);
+
+ if (!object)
+@@ -339,6 +349,7 @@ static enum bp_result get_gpio_i2c_info(
+ struct atom_gpio_pin_lut_v2_1 *header;
+ uint32_t count = 0;
+ unsigned int table_index = 0;
++ bool find_valid = false;
+
+ if (!info)
+ return BP_RESULT_BADINPUT;
+@@ -366,33 +377,28 @@ static enum bp_result get_gpio_i2c_info(
+ - sizeof(struct atom_common_table_header))
+ / sizeof(struct atom_gpio_pin_assignment);
+
+- table_index = record->i2c_id & I2C_HW_LANE_MUX;
+-
+- if (count < table_index) {
+- bool find_valid = false;
+-
+- for (table_index = 0; table_index < count; table_index++) {
+- if (((record->i2c_id & I2C_HW_CAP) == (
+- header->gpio_pin[table_index].gpio_id &
+- I2C_HW_CAP)) &&
+- ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
+- (header->gpio_pin[table_index].gpio_id &
+- I2C_HW_ENGINE_ID_MASK)) &&
+- ((record->i2c_id & I2C_HW_LANE_MUX) ==
+- (header->gpio_pin[table_index].gpio_id &
+- I2C_HW_LANE_MUX))) {
+- /* still valid */
+- find_valid = true;
+- break;
+- }
++ for (table_index = 0; table_index < count; table_index++) {
++ if (((record->i2c_id & I2C_HW_CAP) == (
++ header->gpio_pin[table_index].gpio_id &
++ I2C_HW_CAP)) &&
++ ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) ==
++ (header->gpio_pin[table_index].gpio_id &
++ I2C_HW_ENGINE_ID_MASK)) &&
++ ((record->i2c_id & I2C_HW_LANE_MUX) ==
++ (header->gpio_pin[table_index].gpio_id &
++ I2C_HW_LANE_MUX))) {
++ /* still valid */
++ find_valid = true;
++ break;
+ }
+- /* If we don't find the entry that we are looking for then
+- * we will return BP_Result_BadBiosTable.
+- */
+- if (find_valid == false)
+- return BP_RESULT_BADBIOSTABLE;
+ }
+
++ /* If we don't find the entry that we are looking for then
++ * we will return BP_Result_BadBiosTable.
++ */
++ if (find_valid == false)
++ return BP_RESULT_BADBIOSTABLE;
++
+ /* get the GPIO_I2C_INFO */
+ info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
+ info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
+@@ -1203,6 +1209,8 @@ static enum bp_result get_firmware_info_v3_1(
+ bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
+ }
+
++ info->oem_i2c_present = false;
++
+ return BP_RESULT_OK;
+ }
+
+@@ -1281,6 +1289,13 @@ static enum bp_result get_firmware_info_v3_2(
+ bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
+ }
+
++ if (firmware_info->board_i2c_feature_id == 0x2) {
++ info->oem_i2c_present = true;
++ info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
++ } else {
++ info->oem_i2c_present = false;
++ }
++
+ return BP_RESULT_OK;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 0c7925c2faf2..a652ebd77f7a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2495,6 +2495,17 @@ bool dc_submit_i2c(
+ cmd);
+ }
+
++bool dc_submit_i2c_oem(
++ struct dc *dc,
++ struct i2c_command *cmd)
++{
++ struct ddc_service *ddc = dc->res_pool->oem_device;
++ return dce_i2c_submit_command(
++ dc->res_pool,
++ ddc->ddc_pin,
++ cmd);
++}
++
+ static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
+ {
+ if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index d98640f49874..747cd0fbe571 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -204,7 +204,10 @@ static void construct(
+ ddc_service->ddc_pin = NULL;
+ } else {
+ hw_info.ddc_channel = i2c_info.i2c_line;
+- hw_info.hw_supported = i2c_info.i2c_hw_assist;
++ if (ddc_service->link != NULL)
++ hw_info.hw_supported = i2c_info.i2c_hw_assist;
++ else
++ hw_info.hw_supported = false;
+
+ ddc_service->ddc_pin = dal_gpio_create_ddc(
+ gpio_service,
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index f24fd19ed93d..9270e43cd5bb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -305,6 +305,10 @@ bool dc_submit_i2c(
+ uint32_t link_index,
+ struct i2c_command *cmd);
+
++bool dc_submit_i2c_oem(
++ struct dc *dc,
++ struct i2c_command *cmd);
++
+ uint32_t dc_bandwidth_in_kbps_from_timing(
+ const struct dc_crtc_timing *timing);
+ #endif /* DC_LINK_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
+index 35a75398fcb4..dd41736bb5c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
+@@ -31,7 +31,7 @@ bool dce_i2c_submit_command(
+ struct i2c_command *cmd)
+ {
+ struct dce_i2c_hw *dce_i2c_hw;
+- struct dce_i2c_sw *dce_i2c_sw;
++ struct dce_i2c_sw dce_i2c_sw = {0};
+
+ if (!ddc) {
+ BREAK_TO_DEBUGGER();
+@@ -43,18 +43,15 @@ bool dce_i2c_submit_command(
+ return false;
+ }
+
+- /* The software engine is only available on dce8 */
+- dce_i2c_sw = dce_i2c_acquire_i2c_sw_engine(pool, ddc);
+-
+- if (!dce_i2c_sw) {
+- dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc);
+-
+- if (!dce_i2c_hw)
+- return false;
++ dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc);
+
++ if (dce_i2c_hw)
+ return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw);
+- }
+
+- return dce_i2c_submit_command_sw(pool, ddc, cmd, dce_i2c_sw);
++ dce_i2c_sw.ctx = ddc->ctx;
++ if (dce_i2c_engine_acquire_sw(&dce_i2c_sw, ddc)) {
++ return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw);
++ }
+
++ return false;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
+index f0266694cb56..f48dbeb75e80 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
+@@ -70,31 +70,6 @@ static void release_engine_dce_sw(
+ dce_i2c_sw->ddc = NULL;
+ }
+
+-static bool get_hw_supported_ddc_line(
+- struct ddc *ddc,
+- enum gpio_ddc_line *line)
+-{
+- enum gpio_ddc_line line_found;
+-
+- *line = GPIO_DDC_LINE_UNKNOWN;
+-
+- if (!ddc) {
+- BREAK_TO_DEBUGGER();
+- return false;
+- }
+-
+- if (!ddc->hw_info.hw_supported)
+- return false;
+-
+- line_found = dal_ddc_get_line(ddc);
+-
+- if (line_found >= GPIO_DDC_LINE_COUNT)
+- return false;
+-
+- *line = line_found;
+-
+- return true;
+-}
+ static bool wait_for_scl_high_sw(
+ struct dc_context *ctx,
+ struct ddc *ddc,
+@@ -521,21 +496,3 @@ bool dce_i2c_submit_command_sw(
+
+ return result;
+ }
+-struct dce_i2c_sw *dce_i2c_acquire_i2c_sw_engine(
+- struct resource_pool *pool,
+- struct ddc *ddc)
+-{
+- enum gpio_ddc_line line;
+- struct dce_i2c_sw *engine = NULL;
+-
+- if (get_hw_supported_ddc_line(ddc, &line))
+- engine = pool->sw_i2cs[line];
+-
+- if (!engine)
+- return NULL;
+-
+- if (!dce_i2c_engine_acquire_sw(engine, ddc))
+- return NULL;
+-
+- return engine;
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h
+index 5bbcdd455614..019fc47bb767 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h
+@@ -49,9 +49,9 @@ bool dce_i2c_submit_command_sw(
+ struct i2c_command *cmd,
+ struct dce_i2c_sw *dce_i2c_sw);
+
+-struct dce_i2c_sw *dce_i2c_acquire_i2c_sw_engine(
+- struct resource_pool *pool,
+- struct ddc *ddc);
++bool dce_i2c_engine_acquire_sw(
++ struct dce_i2c_sw *dce_i2c_sw,
++ struct ddc *ddc_handle);
+
+ #endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 19a4838b1ac2..454d30bbfd20 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -57,6 +57,7 @@
+ #include "dml/display_mode_vba.h"
+ #include "dcn20_dccg.h"
+ #include "dcn20_vmid.h"
++#include "dc_link_ddc.h"
+
+ #include "navi10_ip_offset.h"
+
+@@ -1344,6 +1345,8 @@ static void destruct(struct dcn20_resource_pool *pool)
+ if (pool->base.pp_smu != NULL)
+ dcn20_pp_smu_destroy(&pool->base.pp_smu);
+
++ if (pool->base.oem_device != NULL)
++ dal_ddc_service_destroy(&pool->base.oem_device);
+ }
+
+ struct hubp *dcn20_hubp_create(
+@@ -3389,6 +3392,7 @@ static bool construct(
+ int i;
+ struct dc_context *ctx = dc->ctx;
+ struct irq_service_init_data init_data;
++ struct ddc_service_init_data ddc_init_data;
+ struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
+ get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
+ struct _vcs_dpi_ip_params_st *loaded_ip =
+@@ -3684,6 +3688,17 @@ static bool construct(
+
+ dc->cap_funcs = cap_funcs;
+
++ if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
++ ddc_init_data.ctx = dc->ctx;
++ ddc_init_data.link = NULL;
++ ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
++ ddc_init_data.id.enum_id = 0;
++ ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
++ pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
++ } else {
++ pool->base.oem_device = NULL;
++ }
++
+ return true;
+
+ create_fail:
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+index 43a440385b43..2664cb22dfe7 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+@@ -110,6 +110,12 @@ static const struct ddc_registers ddc_data_regs_dcn[] = {
+ ddc_data_regs_dcn2(4),
+ ddc_data_regs_dcn2(5),
+ ddc_data_regs_dcn2(6),
++ {
++ DDC_GPIO_VGA_REG_LIST(DATA),
++ .ddc_setup = 0,
++ .phy_aux_cntl = 0,
++ .dc_gpio_aux_ctrl_5 = 0
++ }
+ };
+
+ static const struct ddc_registers ddc_clk_regs_dcn[] = {
+@@ -119,6 +125,12 @@ static const struct ddc_registers ddc_clk_regs_dcn[] = {
+ ddc_clk_regs_dcn2(4),
+ ddc_clk_regs_dcn2(5),
+ ddc_clk_regs_dcn2(6),
++ {
++ DDC_GPIO_VGA_REG_LIST(CLK),
++ .ddc_setup = 0,
++ .phy_aux_cntl = 0,
++ .dc_gpio_aux_ctrl_5 = 0
++ }
+ };
+
+ static const struct ddc_sh_mask ddc_shift[] = {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index a831079607cd..fc9decc0a8fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -229,6 +229,8 @@ struct resource_pool {
+
+ const struct resource_funcs *funcs;
+ const struct resource_caps *res_cap;
++
++ struct ddc_service *oem_device;
+ };
+
+ struct dcn_fe_bandwidth {
+diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+index f312834fef50..d51de94e4bc3 100644
+--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
++++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+@@ -178,7 +178,8 @@ struct dc_firmware_info {
+ uint32_t default_engine_clk; /* in KHz */
+ uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
+ uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
+-
++ bool oem_i2c_present;
++ uint8_t oem_i2c_obj_id;
+
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4358-drm-amd-display-Unify-all-scaling-when-Integer-Scali.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4358-drm-amd-display-Unify-all-scaling-when-Integer-Scali.patch
new file mode 100644
index 00000000..6444cf87
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4358-drm-amd-display-Unify-all-scaling-when-Integer-Scali.patch
@@ -0,0 +1,109 @@
+From 9e82c03526a0875547dde5bfbcc0a68132a14b84 Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Thu, 17 Oct 2019 16:40:02 -0400
+Subject: [PATCH 4358/4736] drm/amd/display: Unify all scaling when Integer
+ Scaling enabled
+
+[why]
+We want to guarantee integer ratio scaling for all scaling modes.
+
+[how]
+Treat centered, fullscreen, preserve aspect ratio the same: scale
+the view as many times as possible, and fill in the rest with a black
+border.
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++++--
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++++---------------
+ drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 +
+ 3 files changed, 11 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index a652ebd77f7a..a0ad1796af08 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1545,7 +1545,10 @@ static enum surface_update_type get_scaling_info_update_type(
+ if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
+ || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
+ || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
+- || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
++ || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
++ || u->scaling_info->scaling_quality.integer_scaling !=
++ u->surface->scaling_quality.integer_scaling
++ ) {
+ update_flags->bits.scaling_change = 1;
+
+ if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
+@@ -1666,7 +1669,8 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ union stream_update_flags *su_flags = &stream_update->stream->update_flags;
+
+ if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
+- (stream_update->dst.height != 0 && stream_update->dst.width != 0))
++ (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
++ stream_update->integer_scaling_update)
+ su_flags->bits.scaling = 1;
+
+ if (stream_update->out_transfer_func)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 42c44c05759f..2acfaa9a24cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -948,25 +948,14 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
+ data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
+
+ }
+-static bool are_rects_integer_multiples(struct rect src, struct rect dest)
+-{
+- if (dest.width >= src.width && dest.width % src.width == 0 &&
+- dest.height >= src.height && dest.height % src.height == 0)
+- return true;
+-
+- return false;
+-}
+
+ static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
+ {
+- if (!pipe_ctx->plane_state->scaling_quality.integer_scaling)
+- return;
++ unsigned int integer_multiple = 1;
+
+- //for Centered Mode
+- if (pipe_ctx->stream->dst.width == pipe_ctx->stream->src.width &&
+- pipe_ctx->stream->dst.height == pipe_ctx->stream->src.height) {
++ if (pipe_ctx->plane_state->scaling_quality.integer_scaling) {
+ // calculate maximum # of replication of src onto addressable
+- unsigned int integer_multiple = min(
++ integer_multiple = min(
+ pipe_ctx->stream->timing.h_addressable / pipe_ctx->stream->src.width,
+ pipe_ctx->stream->timing.v_addressable / pipe_ctx->stream->src.height);
+
+@@ -977,10 +966,8 @@ static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
+ //center dst onto addressable
+ pipe_ctx->stream->dst.x = (pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
+ pipe_ctx->stream->dst.y = (pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
+- }
+
+- //disable taps if src & dst are integer ratio
+- if (are_rects_integer_multiples(pipe_ctx->stream->src, pipe_ctx->stream->dst)) {
++ //We are guaranteed that we are scaling in integer ratio
+ pipe_ctx->plane_state->scaling_quality.v_taps = 1;
+ pipe_ctx->plane_state->scaling_quality.h_taps = 1;
+ pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index f8c07d5a4054..70274fc43a72 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -252,6 +252,7 @@ struct dc_stream_update {
+ struct dc_info_packet *vsp_infopacket;
+
+ bool *dpms_off;
++ bool integer_scaling_update;
+
+ struct colorspace_transform *gamut_remap;
+ enum dc_color_space *output_color_space;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4359-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4359-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
new file mode 100644
index 00000000..91a432ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4359-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
@@ -0,0 +1,46 @@
+From bf1946e10b4db9759ecf426cbeee8b09b5597049 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 5 Nov 2019 16:13:05 +0800
+Subject: [PATCH 4359/4736] drm/amd/powerplay: update Arcturus driver-smu
+ interface header
+
+To fit the latest SMU firmware.
+
+Change-Id: Ib197e6186127121b4ae276639fa66677094a7d01
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h | 2 +-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index 886b9a21ebd8..a886f0644d24 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -159,7 +159,7 @@
+ //FIXME need updating
+ // Debug Overrides Bitmask
+ #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000001
+-#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK 0x00000002
++#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000002
+
+ // I2C Config Bit Defines
+ #define I2C_CONTROLLER_ENABLED 1
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 88ee66683271..36028e9d1011 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,7 +27,7 @@
+
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+-#define SMU11_DRIVER_IF_VERSION_ARCT 0x0F
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x10
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x34
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4360-drm-amd-swSMU-fix-smu-workload-bit-map-error.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4360-drm-amd-swSMU-fix-smu-workload-bit-map-error.patch
new file mode 100644
index 00000000..1188e489
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4360-drm-amd-swSMU-fix-smu-workload-bit-map-error.patch
@@ -0,0 +1,47 @@
+From 39bb749823ebf64f5e2a7b9d1eaeb66a57a53c51 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 5 Nov 2019 18:16:38 +0800
+Subject: [PATCH 4360/4736] drm/amd/swSMU: fix smu workload bit map error
+
+fix workload bit (WORKLOAD_PPLIB_COMPUTE_BIT) map error
+on vega20 and navi asic.
+
+fix commit:
+drm/amd/powerplay: add function get_workload_type_map for swsmu
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 34390656a03e..010be21bee5b 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -206,7 +206,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
+- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
++ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
+ };
+
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 7125406c6256..e00ffbbde791 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -221,7 +221,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
+- WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
++ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4361-drm-amdgpu-register-gpu-instance-before-fan-boost-fe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4361-drm-amdgpu-register-gpu-instance-before-fan-boost-fe.patch
new file mode 100644
index 00000000..2593c094
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4361-drm-amdgpu-register-gpu-instance-before-fan-boost-fe.patch
@@ -0,0 +1,50 @@
+From e284bbcf32d1b56f3a271dedf13859f0d66e5208 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 5 Nov 2019 18:13:49 +0800
+Subject: [PATCH 4361/4736] drm/amdgpu: register gpu instance before fan boost
+ feature enablment
+
+Otherwise, the feature enablement will be skipped due to wrong count.
+Caused by "drm/amdgpu: fix a race in GPU reset with IB test (v2)".
+
+Change-Id: Id576090d7ce7645a5c98ac160e0af730a51526b0
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 -
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index beeae2573cb0..edc11fb2bf24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3036,6 +3036,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
+ }
+
++ /*
++ * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
++ * Otherwise the mgpu fan boost feature will be skipped due to the
++ * gpu instance is counted less.
++ */
++ amdgpu_register_gpu_instance(adev);
++
+ /* enable clockgating, etc. after ib tests, etc. since some blocks require
+ * explicit gating rather than handling it automatically.
+ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 5abbfc488022..488258f1138d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -187,7 +187,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ pm_runtime_put_autosuspend(dev->dev);
+ }
+
+- amdgpu_register_gpu_instance(adev);
+ out:
+ if (r) {
+ /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4362-drm-amdgpu-fix-possible-pstate-switch-race-condition.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4362-drm-amdgpu-fix-possible-pstate-switch-race-condition.patch
new file mode 100644
index 00000000..0d8de457
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4362-drm-amdgpu-fix-possible-pstate-switch-race-condition.patch
@@ -0,0 +1,104 @@
+From 4f712c43a25f97247ad8b2aaa32c255b09704004 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 14:15:29 +0800
+Subject: [PATCH 4362/4736] drm/amdgpu: fix possible pstate switch race
+ condition
+
+Added lock protection so that the p-state switch will
+be guarded to be sequential. Also update the hive
+pstate only all device from the hive are in the same
+state.
+
+Change-Id: I165a6f44e8aec1e6da56eefa0fc49d36670e56fe
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 34 ++++++++++++++++++++++--
+ 2 files changed, 35 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 2eb3a6bcbd6c..715739799383 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1025,6 +1025,9 @@ struct amdgpu_device {
+
+ uint64_t unique_id;
+ uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
++
++ /* device pstate */
++ int pstate;
+ };
+
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index 44a0ee91b42d..e58bad7f64c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -274,12 +274,18 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ {
+ int ret = 0;
+ struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
++ struct amdgpu_device *tmp_adev;
++ bool update_hive_pstate = true;
+
+ if (!hive)
+ return 0;
+
+- if (hive->pstate == pstate)
++ mutex_lock(&hive->hive_lock);
++
++ if (hive->pstate == pstate) {
++ mutex_unlock(&hive->hive_lock);
+ return 0;
++ }
+
+ dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
+
+@@ -290,11 +296,32 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
+ pstate);
+
+- if (ret)
++ if (ret) {
+ dev_err(adev->dev,
+ "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
+ adev->gmc.xgmi.node_id,
+ adev->gmc.xgmi.hive_id, ret);
++ goto out;
++ }
++
++ /* Update device pstate */
++ adev->pstate = pstate;
++
++ /*
++ * Update the hive pstate only all devices of the hive
++ * are in the same pstate
++ */
++ list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
++ if (tmp_adev->pstate != adev->pstate) {
++ update_hive_pstate = false;
++ break;
++ }
++ }
++ if (update_hive_pstate)
++ hive->pstate = pstate;
++
++out:
++ mutex_unlock(&hive->hive_lock);
+
+ return ret;
+ }
+@@ -369,6 +396,9 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
+ goto exit;
+ }
+
++ /* Set default device pstate */
++ adev->pstate = -1;
++
+ top_info = &adev->psp.xgmi_context.top_info;
+
+ list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4363-drm-amdgpu-perform-p-state-switch-after-the-whole-hi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4363-drm-amdgpu-perform-p-state-switch-after-the-whole-hi.patch
new file mode 100644
index 00000000..f96d7ef2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4363-drm-amdgpu-perform-p-state-switch-after-the-whole-hi.patch
@@ -0,0 +1,92 @@
+From aa69b8c4902268b4cc26a99362ff758d03c2710c Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 5 Nov 2019 15:15:33 +0800
+Subject: [PATCH 4363/4736] drm/amdgpu: perform p-state switch after the whole
+ hive initialized
+
+P-state switch should be performed after all devices from the hive
+get initialized.
+
+Change-Id: Ifc7cac9ef0cf250447d2a412da35d601e2ac79ec
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Jonathan Kim <Jonathan.Kim at amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 47 ++++++++++++++++------
+ 1 file changed, 35 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index edc11fb2bf24..21ff9f6da355 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2057,6 +2057,7 @@ static int amdgpu_device_enable_mgpu_fan_boost(void)
+ */
+ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
+ {
++ struct amdgpu_gpu_instance *gpu_instance;
+ int i = 0, r;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+@@ -2082,6 +2083,40 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
+ if (r)
+ DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
++
++ if (adev->gmc.xgmi.num_physical_nodes > 1) {
++ mutex_lock(&mgpu_info.mutex);
++
++ /*
++ * Reset device p-state to low as this was booted with high.
++ *
++ * This should be performed only after all devices from the same
++ * hive get initialized.
++ *
++ * However, it's unknown how many device in the hive in advance.
++ * As this is counted one by one during devices initializations.
++ *
++ * So, we wait for all XGMI interlinked devices initialized.
++ * This may bring some delays as those devices may come from
++ * different hives. But that should be OK.
++ */
++ if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
++ for (i = 0; i < mgpu_info.num_gpu; i++) {
++ gpu_instance = &(mgpu_info.gpu_ins[i]);
++ if (gpu_instance->adev->flags & AMD_IS_APU)
++ continue;
++
++ r = amdgpu_xgmi_set_pstate(gpu_instance->adev, 0);
++ if (r) {
++ DRM_ERROR("pstate setting failed (%d).\n", r);
++ break;
++ }
++ }
++ }
++
++ mutex_unlock(&mgpu_info.mutex);
++ }
++
+ return 0;
+ }
+
+@@ -2193,18 +2228,6 @@ static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
+ r = amdgpu_ib_ring_tests(adev);
+ if (r)
+ DRM_ERROR("ib ring test failed (%d).\n", r);
+-
+- /*
+- * set to low pstate by default
+- * This should be performed after all devices from
+- * XGMI finish their initializations. Thus it's moved
+- * to here.
+- * The time delay is 2S. TODO: confirm whether that
+- * is enough for all possible XGMI setups.
+- */
+- r = amdgpu_xgmi_set_pstate(adev, 0);
+- if (r)
+- DRM_ERROR("pstate setting failed (%d).\n", r);
+ }
+
+ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4364-drm-amdgpu-add-dummy-read-by-engines-for-some-GCVM-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4364-drm-amdgpu-add-dummy-read-by-engines-for-some-GCVM-s.patch
new file mode 100644
index 00000000..225b7964
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4364-drm-amdgpu-add-dummy-read-by-engines-for-some-GCVM-s.patch
@@ -0,0 +1,201 @@
+From 9ec6a9973b1007b2aba9d1b28088629819859837 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Thu, 10 Oct 2019 11:02:33 +0800
+Subject: [PATCH 4364/4736] drm/amdgpu: add dummy read by engines for some GCVM
+ status registers in gfx10
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The GRBM register interface is now capable of bursting 1 cycle per
+register wr->wr, wr->rd much faster than previous muticycle per
+transaction done interface. This has caused a problem where
+status registers requiring HW to update have a 1 cycle delay, due
+to the register update having to go through GRBM.
+
+For cp ucode, it has realized dummy read in cp firmware.It covers
+the use of WAIT_REG_MEM operation 1 case only.So it needs to call
+gfx_v10_0_wait_reg_mem in gfx10. Besides it also needs to add warning to
+update firmware in case firmware is too old to have function to realize
+dummy read in cp firmware.
+
+For sdma ucode, it hasn't realized dummy read in sdma firmware. sdma is
+moved to gfxhub in gfx10. So it needs to add dummy read in driver
+between amdgpu_ring_emit_wreg and amdgpu_ring_emit_reg_wait for sdma_v5_0.
+
+Change-Id: Ie028f37eb789966d4593984bd661b248ebeb1ac3
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 48 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 8 ++---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++-
+ 4 files changed, 64 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 459aa9059542..a74ecd449775 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -267,6 +267,7 @@ struct amdgpu_gfx {
+ uint32_t mec2_feature_version;
+ bool mec_fw_write_wait;
+ bool me_fw_write_wait;
++ bool cp_fw_write_wait;
+ struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
+ unsigned num_gfx_rings;
+ struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 17a5cbfd0024..c7a6f98bf6b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -561,6 +561,32 @@ static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
+ kfree(adev->gfx.rlc.register_list_format);
+ }
+
++static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
++{
++ adev->gfx.cp_fw_write_wait = false;
++
++ switch (adev->asic_type) {
++ case CHIP_NAVI10:
++ case CHIP_NAVI12:
++ case CHIP_NAVI14:
++ if ((adev->gfx.me_fw_version >= 0x00000046) &&
++ (adev->gfx.me_feature_version >= 27) &&
++ (adev->gfx.pfp_fw_version >= 0x00000068) &&
++ (adev->gfx.pfp_feature_version >= 27) &&
++ (adev->gfx.mec_fw_version >= 0x0000005b) &&
++ (adev->gfx.mec_feature_version >= 27))
++ adev->gfx.cp_fw_write_wait = true;
++ break;
++ default:
++ break;
++ }
++
++ if (adev->gfx.cp_fw_write_wait == false)
++ DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \
++ GRBM requires 1-cycle delay in cp firmware\n");
++}
++
++
+ static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
+ {
+ const struct rlc_firmware_header_v2_1 *rlc_hdr;
+@@ -829,6 +855,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ }
+ }
+
++ gfx_v10_0_check_fw_write_wait(adev);
+ out:
+ if (err) {
+ dev_err(adev->dev,
+@@ -4768,6 +4795,24 @@ static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
+ }
+
++static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
++ uint32_t reg0, uint32_t reg1,
++ uint32_t ref, uint32_t mask)
++{
++ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
++ struct amdgpu_device *adev = ring->adev;
++ bool fw_version_ok = false;
++
++ fw_version_ok = adev->gfx.cp_fw_write_wait;
++
++ if (fw_version_ok)
++ gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
++ ref, mask, 0x20);
++ else
++ amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
++ ref, mask);
++}
++
+ static void
+ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
+ uint32_t me, uint32_t pipe,
+@@ -5158,6 +5203,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
+ .emit_tmz = gfx_v10_0_ring_emit_tmz,
+ .emit_wreg = gfx_v10_0_ring_emit_wreg,
+ .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
++ .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
+ };
+
+ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
+@@ -5191,6 +5237,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .emit_wreg = gfx_v10_0_ring_emit_wreg,
+ .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
++ .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
+ };
+
+ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
+@@ -5221,6 +5268,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
+ .emit_rreg = gfx_v10_0_ring_emit_rreg,
+ .emit_wreg = gfx_v10_0_ring_emit_wreg,
+ .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
++ .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
+ };
+
+ static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 3b00bce14cfb..af2615ba52aa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -344,11 +344,9 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
+ upper_32_bits(pd_addr));
+
+- amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
+-
+- /* wait for the invalidate to complete */
+- amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
+- 1 << vmid, 1 << vmid);
++ amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
++ hub->vm_inv_eng0_ack + eng,
++ req, 1 << vmid);
+
+ return pd_addr;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 3460c00f3eaa..ec47542e21b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1170,6 +1170,16 @@ static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
+ }
+
++static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
++ uint32_t reg0, uint32_t reg1,
++ uint32_t ref, uint32_t mask)
++{
++ amdgpu_ring_emit_wreg(ring, reg0, ref);
++ /* wait for a cycle to reset vm_inv_eng*_ack */
++ amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
++ amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
++}
++
+ static int sdma_v5_0_early_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -1585,7 +1595,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
+ 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
+ /* sdma_v5_0_ring_emit_vm_flush */
+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+- SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
++ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
+ 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
+ .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */
+ .emit_ib = sdma_v5_0_ring_emit_ib,
+@@ -1599,6 +1609,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
+ .pad_ib = sdma_v5_0_ring_pad_ib,
+ .emit_wreg = sdma_v5_0_ring_emit_wreg,
+ .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
++ .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
+ .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
+ .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
+ .preempt_ib = sdma_v5_0_ring_preempt_ib,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4365-drm-amdgpu-add-warning-for-GRBM-1-cycle-delay-issue-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4365-drm-amdgpu-add-warning-for-GRBM-1-cycle-delay-issue-.patch
new file mode 100644
index 00000000..85257463
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4365-drm-amdgpu-add-warning-for-GRBM-1-cycle-delay-issue-.patch
@@ -0,0 +1,41 @@
+From e5c5504c64389201bec2377de804e4277bb18fc8 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Tue, 5 Nov 2019 18:29:12 +0800
+Subject: [PATCH 4365/4736] drm/amdgpu: add warning for GRBM 1-cycle delay
+ issue in gfx9
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It needs to add warning to update firmware in gfx9
+in case that firmware is too old to have function to
+realize dummy read in cp firmware.
+
+Change-Id: I6aef94f0823138f244f1eedb62fde833dd697023
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index d521facadf59..a3bb662acb1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -982,6 +982,13 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
+ adev->gfx.me_fw_write_wait = false;
+ adev->gfx.mec_fw_write_wait = false;
+
++ if ((adev->gfx.mec_fw_version < 0x000001a5) ||
++ (adev->gfx.mec_feature_version < 46) ||
++ (adev->gfx.pfp_fw_version < 0x000000b7) ||
++ (adev->gfx.pfp_feature_version < 46))
++ DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \
++ GRBM requires 1-cycle delay in cp firmware\n");
++
+ switch (adev->asic_type) {
+ case CHIP_VEGA10:
+ if ((adev->gfx.me_fw_version >= 0x0000009c) &&
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch
new file mode 100644
index 00000000..47afacc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch
@@ -0,0 +1,48 @@
+From d471a8a8f117b852f6aa081443747ed8e4b66aa7 Mon Sep 17 00:00:00 2001
+From: Eric Huang <JinhuiEric.Huang@amd.com>
+Date: Tue, 5 Nov 2019 16:29:57 -0500
+Subject: [PATCH 4366/4736] drm/amdgpu: change read of GPU clock counter on
+ Vega10 VF
+
+Using unified VBIOS has performance drop in sriov environment.
+The fix is switching to another register instead.
+
+Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index a3bb662acb1f..4fe3c5ebaf58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3887,9 +3887,22 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
+ uint64_t clock;
+
+ mutex_lock(&adev->gfx.gpu_clock_mutex);
+- WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
+- clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
+- ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++ if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
++ uint32_t tmp, lsb, msb, i = 0;
++ do {
++ if (i != 0)
++ udelay(1);
++ tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
++ lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
++ msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
++ i++;
++ } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
++ clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
++ } else {
++ WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
++ clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
++ ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++ }
+ mutex_unlock(&adev->gfx.gpu_clock_mutex);
+ return clock;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4367-drm-amdgpu-remove-4-set-but-not-used-variable-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4367-drm-amdgpu-remove-4-set-but-not-used-variable-in-amd.patch
new file mode 100644
index 00000000..cc8fb954
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4367-drm-amdgpu-remove-4-set-but-not-used-variable-in-amd.patch
@@ -0,0 +1,70 @@
+From cec4fa968f7c75f23a84007aa104f5816771ae6b Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:20 +0800
+Subject: [PATCH 4367/4736] drm/amdgpu: remove 4 set but not used variable in
+ amdgpu_atombios_get_connector_info_from_object_table
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c: In function
+'amdgpu_atombios_get_connector_info_from_object_table':
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:376:26: warning: variable
+'grph_obj_num' set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:376:13: warning: variable
+'grph_obj_id' set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:341:37: warning: variable
+'con_obj_type' set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:341:24: warning: variable
+'con_obj_num' set but not used [-Wunused-but-set-variable]
+
+They are never used, so can be removed.
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 19 ++-----------------
+ 1 file changed, 2 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+index a0d582a1e8c6..7d941b3802a6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+@@ -338,17 +338,9 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
+ path_size += le16_to_cpu(path->usSize);
+
+ if (device_support & le16_to_cpu(path->usDeviceTag)) {
+- uint8_t con_obj_id, con_obj_num, con_obj_type;
+-
+- con_obj_id =
++ uint8_t con_obj_id =
+ (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
+ >> OBJECT_ID_SHIFT;
+- con_obj_num =
+- (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
+- >> ENUM_ID_SHIFT;
+- con_obj_type =
+- (le16_to_cpu(path->usConnObjectId) &
+- OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+
+ /* Skip TV/CV support */
+ if ((le16_to_cpu(path->usDeviceTag) ==
+@@ -373,14 +365,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
+ router.ddc_valid = false;
+ router.cd_valid = false;
+ for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
+- uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
+-
+- grph_obj_id =
+- (le16_to_cpu(path->usGraphicObjIds[j]) &
+- OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+- grph_obj_num =
+- (le16_to_cpu(path->usGraphicObjIds[j]) &
+- ENUM_ID_MASK) >> ENUM_ID_SHIFT;
++ uint8_t grph_obj_type=
+ grph_obj_type =
+ (le16_to_cpu(path->usGraphicObjIds[j]) &
+ OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4368-drm-amdgpu-add-function-parameter-description-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4368-drm-amdgpu-add-function-parameter-description-in-amd.patch
new file mode 100644
index 00000000..1b657d43
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4368-drm-amdgpu-add-function-parameter-description-in-amd.patch
@@ -0,0 +1,33 @@
+From da40b874e2cd1fd83846f38d27f240dc467c1bfc Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:21 +0800
+Subject: [PATCH 4368/4736] drm/amdgpu: add function parameter description in
+ 'amdgpu_device_set_cg_state'
+
+Fixes gcc warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1954: warning: Function
+parameter or member 'state' not described in 'amdgpu_device_set_cg_state'
+
+Fixes: e3ecdffac9cc ("drm/amdgpu: add documentation for amdgpu_device.c")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 21ff9f6da355..09ef0eaf1abc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1938,6 +1938,7 @@ static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
+ * amdgpu_device_set_cg_state - set clockgating for amdgpu device
+ *
+ * @adev: amdgpu_device pointer
++ * @state: clockgating state (gate or ungate)
+ *
+ * The list of all the hardware IPs that make up the asic is walked and the
+ * set_clockgating_state callbacks are run.
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4369-drm-amdgpu-add-function-parameter-description-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4369-drm-amdgpu-add-function-parameter-description-in-amd.patch
new file mode 100644
index 00000000..d70b6a16
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4369-drm-amdgpu-add-function-parameter-description-in-amd.patch
@@ -0,0 +1,33 @@
+From fe9f281a14d18acee19a82c9843c6d53de630ac9 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:22 +0800
+Subject: [PATCH 4369/4736] drm/amdgpu: add function parameter description in
+ 'amdgpu_gart_bind'
+
+Fixes gcc warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c:313: warning: Function
+parameter or member 'flags' not described in 'amdgpu_gart_bind'
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+index 83f4dcb7926c..f6ded1268d94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -297,6 +297,7 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
+ * @pages: number of pages to bind
+ * @pagelist: pages to bind
+ * @dma_addr: DMA addresses of pages
++ * @flags: page table entry flags
+ *
+ * Binds the requested pages to the gart page table
+ * (all asics).
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4370-drm-amdgpu-remove-set-but-not-used-variable-dig_conn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4370-drm-amdgpu-remove-set-but-not-used-variable-dig_conn.patch
new file mode 100644
index 00000000..05633a30
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4370-drm-amdgpu-remove-set-but-not-used-variable-dig_conn.patch
@@ -0,0 +1,49 @@
+From 00891ae85afb4ed6db6b4b091f324ac39062dc38 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:23 +0800
+Subject: [PATCH 4370/4736] drm/amdgpu: remove set but not used variable
+ 'dig_connector'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c: In function
+‘amdgpu_atombios_dp_get_panel_mode’:
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c:364:36: warning: variable
+‘dig_connector’ set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+index f81068ba4cc6..d712dee89254 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -361,7 +361,6 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
+ struct drm_connector *connector)
+ {
+ struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+- struct amdgpu_connector_atom_dig *dig_connector;
+ int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+ u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
+ u8 tmp;
+@@ -369,8 +368,6 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
+ if (!amdgpu_connector->con_priv)
+ return panel_mode;
+
+- dig_connector = amdgpu_connector->con_priv;
+-
+ if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
+ /* DP bridge chips */
+ if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4371-drm-amdgpu-remove-set-but-not-used-variable-dig.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4371-drm-amdgpu-remove-set-but-not-used-variable-dig.patch
new file mode 100644
index 00000000..530e16c5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4371-drm-amdgpu-remove-set-but-not-used-variable-dig.patch
@@ -0,0 +1,45 @@
+From c52fd8d3f5d9da3621ce4caef26378ae4381f402 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:24 +0800
+Subject: [PATCH 4371/4736] drm/amdgpu: remove set but not used variable 'dig'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c: In function
+‘amdgpu_atombios_dp_link_train’:
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c:716:34: warning: variable ‘dig’
+set but not used [-Wunused-but-set-variable]
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+index d712dee89254..8abe9beab034 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -710,7 +710,6 @@ void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
+ struct drm_device *dev = encoder->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+ struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+- struct amdgpu_encoder_atom_dig *dig;
+ struct amdgpu_connector *amdgpu_connector;
+ struct amdgpu_connector_atom_dig *dig_connector;
+ struct amdgpu_atombios_dp_link_train_info dp_info;
+@@ -718,7 +717,6 @@ void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
+
+ if (!amdgpu_encoder->enc_priv)
+ return;
+- dig = amdgpu_encoder->enc_priv;
+
+ amdgpu_connector = to_amdgpu_connector(connector);
+ if (!amdgpu_connector->con_priv)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4372-drm-amdgpu-remove-always-false-comparison-in-amdgpu_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4372-drm-amdgpu-remove-always-false-comparison-in-amdgpu_.patch
new file mode 100644
index 00000000..b072100d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4372-drm-amdgpu-remove-always-false-comparison-in-amdgpu_.patch
@@ -0,0 +1,45 @@
+From 937e4c99390453264af0907239da7c6adf76a477 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:25 +0800
+Subject: [PATCH 4372/4736] drm/amdgpu: remove always false comparison in
+ 'amdgpu_atombios_i2c_process_i2c_ch'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wtype-limits' warning:
+
+drivers/gpu/drm/amd/amdgpu/atombios_i2c.c: In function
+‘amdgpu_atombios_i2c_process_i2c_ch’:
+drivers/gpu/drm/amd/amdgpu/atombios_i2c.c:79:11: warning: comparison is
+always false due to limited range of data type [-Wtype-limits]
+
+'num' is 'u8', so it will never be greater than 'TOM_MAX_HW_I2C_READ',
+which is defined as 255. Therefore, the comparison can be removed.
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+index f9b2ce9a98f3..9c7d0bf6712a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+@@ -76,11 +76,6 @@ static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan,
+ }
+ args.lpI2CDataOut = cpu_to_le16(out);
+ } else {
+- if (num > ATOM_MAX_HW_I2C_READ) {
+- DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num);
+- r = -EINVAL;
+- goto done;
+- }
+ args.ucRegIndex = 0;
+ args.lpI2CDataOut = 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4373-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4373-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
new file mode 100644
index 00000000..b51d17fe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4373-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
@@ -0,0 +1,47 @@
+From cfbff3407485e3af6c75b81c0aa39d8724600869 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:26 +0800
+Subject: [PATCH 4373/4736] drm/amdgpu: remove set but not used variable
+ 'mc_shared_chmap'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function
+‘gfx_v8_0_gpu_early_init’:
+drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:1713:6: warning: variable
+‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
+
+Fixes: 0bde3a95eaa9 ("drm/amdgpu: split gfx8 gpu init into sw and hw parts")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index c0bcf5d91f1f..1f4f7c05e269 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -1706,7 +1706,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
+ {
+ u32 gb_addr_config;
+- u32 mc_shared_chmap, mc_arb_ramcfg;
++ u32 mc_arb_ramcfg;
+ u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
+ u32 tmp;
+ int ret;
+@@ -1846,7 +1846,6 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
+ break;
+ }
+
+- mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
+ adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
+ mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4374-drm-amdgpu-fix-potential-double-drop-fence-reference.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4374-drm-amdgpu-fix-potential-double-drop-fence-reference.patch
new file mode 100644
index 00000000..b17f6413
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4374-drm-amdgpu-fix-potential-double-drop-fence-reference.patch
@@ -0,0 +1,44 @@
+From 08d4288d57725c283f2c0272870ee3e95788eb54 Mon Sep 17 00:00:00 2001
+From: Pan Bian <bianpan2016@163.com>
+Date: Wed, 6 Nov 2019 17:14:45 +0800
+Subject: [PATCH 4374/4736] drm/amdgpu: fix potential double drop fence
+ reference
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The object fence is not set to NULL after its reference is dropped. As a
+result, its reference may be dropped again if error occurs after that,
+which may lead to a use after free bug. To avoid the issue, fence is
+explicitly set to NULL after dropping its reference.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Pan Bian <bianpan2016@163.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+index 8904e62dca7a..41d3142ef3cf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+@@ -138,6 +138,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ }
+
+ dma_fence_put(fence);
++ fence = NULL;
+
+ r = amdgpu_bo_kmap(vram_obj, &vram_map);
+ if (r) {
+@@ -183,6 +184,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ }
+
+ dma_fence_put(fence);
++ fence = NULL;
+
+ r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
+ if (r) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4375-drm-amd-powerplay-fix-struct-init-in-renoir_print_cl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4375-drm-amd-powerplay-fix-struct-init-in-renoir_print_cl.patch
new file mode 100644
index 00000000..f8cd8c6f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4375-drm-amd-powerplay-fix-struct-init-in-renoir_print_cl.patch
@@ -0,0 +1,41 @@
+From 8122c6fe1715d14e7faf9acb35c113c3a90ede43 Mon Sep 17 00:00:00 2001
+From: Raul E Rangel <rrangel@chromium.org>
+Date: Tue, 5 Nov 2019 15:58:02 -0700
+Subject: [PATCH 4375/4736] drm/amd/powerplay: fix struct init in
+ renoir_print_clk_levels
+
+drivers/gpu/drm/amd/powerplay/renoir_ppt.c:186:2: error: missing braces
+around initializer [-Werror=missing-braces]
+ SmuMetrics_t metrics = {0};
+ ^
+
+Fixes: 8b8031703bd7 ("drm/amd/powerplay: implement sysfs for getting dpm clock")
+
+Signed-off-by: Raul E Rangel <rrangel@chromium.org>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 4a9751971a9d..04daf7e9fe05 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -180,11 +180,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
+ int i, size = 0, ret = 0;
+ uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
+ DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+- SmuMetrics_t metrics = {0};
++ SmuMetrics_t metrics;
+
+ if (!clk_table || clk_type >= SMU_CLK_COUNT)
+ return -EINVAL;
+
++ memset(&metrics, 0, sizeof(metrics));
++
+ ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ (void *)&metrics, false);
+ if (ret)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4376-drm-amdgpu-fix-double-reference-dropping.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4376-drm-amdgpu-fix-double-reference-dropping.patch
new file mode 100644
index 00000000..87c3fcc0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4376-drm-amdgpu-fix-double-reference-dropping.patch
@@ -0,0 +1,54 @@
+From 2885f3f5fb34f6e6f89821501c30491e125b4b0f Mon Sep 17 00:00:00 2001
+From: Pan Bian <bianpan2016@163.com>
+Date: Wed, 6 Nov 2019 19:35:43 +0800
+Subject: [PATCH 4376/4736] drm/amdgpu: fix double reference dropping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The reference to object fence is dropped at the end of the loop.
+However, it is dropped again outside the loop. The reference can be
+dropped immediately after calling dma_fence_wait() in the loop and
+thus the dropping operation outside the loop can be removed.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Pan Bian <bianpan2016@163.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+index 3079ea8523c5..0f2aeb41e5c8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+@@ -33,7 +33,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
+ {
+ unsigned long start_jiffies;
+ unsigned long end_jiffies;
+- struct dma_fence *fence = NULL;
++ struct dma_fence *fence;
+ int i, r;
+
+ start_jiffies = jiffies;
+@@ -44,16 +44,14 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
+ if (r)
+ goto exit_do_move;
+ r = dma_fence_wait(fence, false);
++ dma_fence_put(fence);
+ if (r)
+ goto exit_do_move;
+- dma_fence_put(fence);
+ }
+ end_jiffies = jiffies;
+ r = jiffies_to_msecs(end_jiffies - start_jiffies);
+
+ exit_do_move:
+- if (fence)
+- dma_fence_put(fence);
+ return r;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4377-drm-amdgpu-renoir-move-gfxoff-handling-into-gfx9-mod.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4377-drm-amdgpu-renoir-move-gfxoff-handling-into-gfx9-mod.patch
new file mode 100644
index 00000000..aeb89f2d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4377-drm-amdgpu-renoir-move-gfxoff-handling-into-gfx9-mod.patch
@@ -0,0 +1,51 @@
+From 35d085067b21003e3c56a102d765a045ff547628 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 29 Oct 2019 10:36:22 -0400
+Subject: [PATCH 4377/4736] drm/amdgpu/renoir: move gfxoff handling into gfx9
+ module
+
+To properly handle the option parsing ordering.
+
+Reviewed-by: Yong Zhao <yong.zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 5 -----
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 4fe3c5ebaf58..b7ce3217fcf8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1055,6 +1055,12 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+ !adev->gfx.rlc.is_rlc_v2_1))
+ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+
++ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++ adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
++ AMD_PG_SUPPORT_CP |
++ AMD_PG_SUPPORT_RLC_SMU_HS;
++ break;
++ case CHIP_RENOIR:
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+ AMD_PG_SUPPORT_CP |
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index d3083bd2c5ae..e12cdbdd9aed 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1232,11 +1232,6 @@ static int soc15_common_early_init(void *handle)
+ AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_VCN_DPG;
+ adev->external_rev_id = adev->rev_id + 0x91;
+-
+- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+- adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+- AMD_PG_SUPPORT_CP |
+- AMD_PG_SUPPORT_RLC_SMU_HS;
+ break;
+ default:
+ /* FIXME: not supported yet */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4378-drm-amdgpu-Improve-RAS-documentation-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4378-drm-amdgpu-Improve-RAS-documentation-v2.patch
new file mode 100644
index 00000000..9960cf92
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4378-drm-amdgpu-Improve-RAS-documentation-v2.patch
@@ -0,0 +1,171 @@
+From 3bdc8244e734cff375c70e51b03220787da61eed Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 30 Oct 2019 14:40:09 -0400
+Subject: [PATCH 4378/4736] drm/amdgpu: Improve RAS documentation (v2)
+
+Clarify some areas, clean up formatting, add section for
+unrecoverable error handling.
+
+v2: fix grammatical errors
+
+Reviewed-by: Yong Zhao <yong.zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ Documentation/gpu/amdgpu.rst | 35 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 40 ++++++++++++++++++++-----
+ 2 files changed, 68 insertions(+), 7 deletions(-)
+
+diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
+index 5b9eaf23558e..0efede580039 100644
+--- a/Documentation/gpu/amdgpu.rst
++++ b/Documentation/gpu/amdgpu.rst
+@@ -82,12 +82,21 @@ AMDGPU XGMI Support
+ AMDGPU RAS Support
+ ==================
+
++The AMDGPU RAS interfaces are exposed via sysfs (for informational queries) and
++debugfs (for error injection).
++
+ RAS debugfs/sysfs Control and Error Injection Interfaces
+ --------------------------------------------------------
+
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+ :doc: AMDGPU RAS debugfs control interface
+
++RAS Reboot Behavior for Unrecoverable Errors
++--------------------------------------------------------
++
++.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++ :doc: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
++
+ RAS Error Count sysfs Interface
+ -------------------------------
+
+@@ -109,6 +118,32 @@ RAS VRAM Bad Pages sysfs Interface
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+ :internal:
+
++Sample Code
++-----------
++Sample code for testing error injection can be found here:
++https://cgit.freedesktop.org/mesa/drm/tree/tests/amdgpu/ras_tests.c
++
++This is part of the libdrm amdgpu unit tests which cover several areas of the GPU.
++There are four sets of tests:
++
++RAS Basic Test
++
++The test verifies the RAS feature enabled status and makes sure the necessary sysfs and debugfs files
++are present.
++
++RAS Query Test
++
++This test checks the RAS availability and enablement status for each supported IP block as well as
++the error counts.
++
++RAS Inject Test
++
++This test injects errors for each IP.
++
++RAS Disable Test
++
++This test tests disabling of RAS features for each IP block.
++
+
+ GPU Power/Thermal Controls and Monitoring
+ =========================================
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index afc3ee47d1b2..399617932427 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -218,7 +218,7 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+ * As their names indicate, inject operation will write the
+ * value to the address.
+ *
+- * Second member: struct ras_debug_if::op.
++ * The second member: struct ras_debug_if::op.
+ * It has three kinds of operations.
+ *
+ * - 0: disable RAS on the block. Take ::head as its data.
+@@ -226,14 +226,20 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+ * - 2: inject errors on the block. Take ::inject as its data.
+ *
+ * How to use the interface?
+- * programs:
+- * copy the struct ras_debug_if in your codes and initialize it.
+- * write the struct to the control node.
++ *
++ * Programs
++ *
++ * Copy the struct ras_debug_if in your codes and initialize it.
++ * Write the struct to the control node.
++ *
++ * Shells
+ *
+ * .. code-block:: bash
+ *
+ * echo op block [error [sub_block address value]] > .../ras/ras_ctrl
+ *
++ * Parameters:
++ *
+ * op: disable, enable, inject
+ * disable: only block is needed
+ * enable: block and error are needed
+@@ -263,8 +269,10 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+ * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
+ *
+ * .. note::
+- * Operation is only allowed on blocks which are supported.
++ * Operations are only allowed on blocks which are supported.
+ * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
++ * to see which blocks support RAS on a particular asic.
++ *
+ */
+ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+@@ -320,7 +328,7 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ * DOC: AMDGPU RAS debugfs EEPROM table reset interface
+ *
+ * Some boards contain an EEPROM which is used to persistently store a list of
+- * bad pages containing ECC errors detected in vram. This interface provides
++ * bad pages which experiences ECC errors in vram. This interface provides
+ * a way to reset the EEPROM, e.g., after testing error injection.
+ *
+ * Usage:
+@@ -360,7 +368,7 @@ static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
+ /**
+ * DOC: AMDGPU RAS sysfs Error Count Interface
+ *
+- * It allows user to read the error count for each IP block on the gpu through
++ * It allows the user to read the error count for each IP block on the gpu through
+ * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
+ *
+ * It outputs the multiple lines which report the uncorrected (ue) and corrected
+@@ -1025,6 +1033,24 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
+ }
+ /* sysfs end */
+
++/**
++ * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
++ *
++ * Normally when there is an uncorrectable error, the driver will reset
++ * the GPU to recover. However, in the event of an unrecoverable error,
++ * the driver provides an interface to reboot the system automatically
++ * in that event.
++ *
++ * The following file in debugfs provides that interface:
++ * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
++ *
++ * Usage:
++ *
++ * .. code-block:: bash
++ *
++ * echo true > .../ras/auto_reboot
++ *
++ */
+ /* debugfs begin */
+ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4379-drm-amd-display-Send-vblank-and-user-events-at-vsart.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4379-drm-amd-display-Send-vblank-and-user-events-at-vsart.patch
new file mode 100644
index 00000000..25dde459
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4379-drm-amd-display-Send-vblank-and-user-events-at-vsart.patch
@@ -0,0 +1,126 @@
+From d7fcb28750038aca16cae24cf87bba005eb688cc Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Mon, 4 Nov 2019 09:22:23 -0500
+Subject: [PATCH 4379/4736] drm/amd/display: Send vblank and user events at
+ vsartup for DCN
+
+[Why]
+
+For DCN hardware, the crtc_high_irq handler is assigned to the vstartup
+interrupt. This is different from DCE, which has it assigned to vblank
+start.
+
+We'd like to send vblank and user events at vstartup because:
+
+* It happens close enough to vupdate - the point of no return for HW.
+
+* It is programmed as lines relative to vblank end - i.e. it is not in
+ the variable portion when VRR is enabled. We should signal user
+ events here.
+
+* The pflip interrupt responsible for sending user events today only
+ fires if the DCH HUBP component is not clock gated. In situations
+ where planes are disabled - but the CRTC is enabled - user events won't
+ be sent out, leading to flip done timeouts.
+
+Consequently, this makes vupdate on DCN hardware redundant. It will be
+removed in the next change.
+
+[How]
+
+Add a DCN-specific crtc_high_irq handler, and hook it to the VStartup
+signal. Inside the DCN handler, we send off user events if the pflip
+handler hasn't already done so.
+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 65 ++++++++++++++++++-
+ 1 file changed, 64 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 2f31cbd164d9..1d9fcaeda025 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -483,6 +483,69 @@ static void dm_crtc_high_irq(void *interrupt_params)
+ }
+ }
+
++
++/**
++ * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
++ * @interrupt params - interrupt parameters
++ *
++ * Notify DRM's vblank event handler at VSTARTUP
++ *
++ * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which:
++ * * We are close enough to VUPDATE - the point of no return for hw
++ * * We are in the fixed portion of variable front porch when vrr is enabled
++ * * We are before VUPDATE, where double-buffered vrr registers are swapped
++ *
++ * It is therefore the correct place to signal vblank, send user flip events,
++ * and update VRR.
++ */
++static void dm_dcn_crtc_high_irq(void *interrupt_params)
++{
++ struct common_irq_params *irq_params = interrupt_params;
++ struct amdgpu_device *adev = irq_params->adev;
++ struct amdgpu_crtc *acrtc;
++ struct dm_crtc_state *acrtc_state;
++ unsigned long flags;
++
++ acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
++
++ if (!acrtc)
++ return;
++
++ acrtc_state = to_dm_crtc_state(acrtc->base.state);
++
++ DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
++ amdgpu_dm_vrr_active(acrtc_state));
++
++ amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
++ drm_crtc_handle_vblank(&acrtc->base);
++
++ spin_lock_irqsave(&adev->ddev->event_lock, flags);
++
++ if (acrtc_state->vrr_params.supported &&
++ acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
++ mod_freesync_handle_v_update(
++ adev->dm.freesync_module,
++ acrtc_state->stream,
++ &acrtc_state->vrr_params);
++
++ dc_stream_adjust_vmin_vmax(
++ adev->dm.dc,
++ acrtc_state->stream,
++ &acrtc_state->vrr_params.adjust);
++ }
++
++ if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
++ if (acrtc->event) {
++ drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
++ acrtc->event = NULL;
++ drm_crtc_vblank_put(&acrtc->base);
++ }
++ acrtc->pflip_status = AMDGPU_FLIP_NONE;
++ }
++
++ spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++}
++
+ static int dm_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+ {
+@@ -2158,7 +2221,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
+ c_irq_params->irq_src = int_params.irq_source;
+
+ amdgpu_dm_irq_register_interrupt(adev, &int_params,
+- dm_crtc_high_irq, c_irq_params);
++ dm_dcn_crtc_high_irq, c_irq_params);
+ }
+
+ /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4380-drm-amd-display-Disable-VUpdate-interrupt-for-DCN-ha.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4380-drm-amd-display-Disable-VUpdate-interrupt-for-DCN-ha.patch
new file mode 100644
index 00000000..0cac6ec1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4380-drm-amd-display-Disable-VUpdate-interrupt-for-DCN-ha.patch
@@ -0,0 +1,86 @@
+From cade2f046bd2675034117695433d20e5027e5952 Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Mon, 4 Nov 2019 14:08:05 -0500
+Subject: [PATCH 4380/4736] drm/amd/display: Disable VUpdate interrupt for DCN
+ hardware
+
+[Why]
+
+On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
+handler redundant.
+
+All the vupdate handler does is handle vblank events, and update vrr
+for DCE hw (excluding VEGA, more on that later). As far as usermode is
+concerned. vstartup happens close enough to vupdate on DCN that it can
+be considered the "same". Handling vblank and updating vrr at vstartup
+effectively replaces vupdate on DCN.
+
+Vega is a bit special. Like DCN, the VRR registers on Vega are
+double-buffered, and swapped at vupdate. But Unlike DCN, it lacks a
+vstartup interrupt. This means we can't quite remove the vupdate handler
+for it, since delayed user events due to vrr are sent off there.
+
+[How]
+
+Remove registration of vupdate interrupt handler for DCN. Disable
+vupdate interrupt if asic family DCN, enable otherwise.
+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +++----------------
+ 1 file changed, 4 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 1d9fcaeda025..95cfe4213362 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2224,34 +2224,6 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
+ dm_dcn_crtc_high_irq, c_irq_params);
+ }
+
+- /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
+- * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
+- * to trigger at end of each vblank, regardless of state of the lock,
+- * matching DCE behaviour.
+- */
+- for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
+- i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
+- i++) {
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
+-
+- if (r) {
+- DRM_ERROR("Failed to add vupdate irq id!\n");
+- return r;
+- }
+-
+- int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+- int_params.irq_source =
+- dc_interrupt_to_irq_source(dc, i, 0);
+-
+- c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
+-
+- c_irq_params->adev = adev;
+- c_irq_params->irq_src = int_params.irq_source;
+-
+- amdgpu_dm_irq_register_interrupt(adev, &int_params,
+- dm_vupdate_high_irq, c_irq_params);
+- }
+-
+ /* Use GRPH_PFLIP interrupt */
+ for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
+ i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
+@@ -4237,6 +4209,10 @@ static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
+ struct amdgpu_device *adev = crtc->dev->dev_private;
+ int rc;
+
++ /* Do not set vupdate for DCN hardware */
++ if (adev->family > AMDGPU_FAMILY_AI)
++ return 0;
++
+ irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
+
+ rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4381-drm-amdgpu-Add-comments-to-gmc-structure.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4381-drm-amdgpu-Add-comments-to-gmc-structure.patch
new file mode 100644
index 00000000..ac2d0272
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4381-drm-amdgpu-Add-comments-to-gmc-structure.patch
@@ -0,0 +1,72 @@
+From e8aa9bdf6b3194b24b75fda36504eb93c82f0f0c Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Wed, 6 Nov 2019 11:18:54 -0600
+Subject: [PATCH 4381/4736] drm/amdgpu: Add comments to gmc structure
+
+Explain fields like aper_base, agp_start etc. The definition
+of those fields are confusing as they are from different view
+(CPU or GPU). Add comments for easier understand.
+
+Change-Id: I02c2a27cd0dbc205498eb86aafa722f2e0c25fe6
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Alex Deucher <Alex.Deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 30 +++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index f9d62e80a64e..02bbb571756a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -127,18 +127,48 @@ struct amdgpu_xgmi {
+ };
+
+ struct amdgpu_gmc {
++ /* FB's physical address in MMIO space (for CPU to
++ * map FB). This is different compared to the agp/
++ * gart/vram_start/end field as the later is from
++ * GPU's view and aper_base is from CPU's view.
++ */
+ resource_size_t aper_size;
+ resource_size_t aper_base;
+ /* for some chips with <= 32MB we need to lie
+ * about vram size near mc fb location */
+ u64 mc_vram_size;
+ u64 visible_vram_size;
++ /* AGP aperture start and end in MC address space
++ * Driver find a hole in the MC address space
++ * to place AGP by setting MC_VM_AGP_BOT/TOP registers
++ * Under VMID0, logical address == MC address. AGP
++ * aperture maps to physical bus or IOVA addressed.
++ * AGP aperture is used to simulate FB in ZFB case.
++ * AGP aperture is also used for page table in system
++ * memory (mainly for APU).
++ *
++ */
+ u64 agp_size;
+ u64 agp_start;
+ u64 agp_end;
++ /* GART aperture start and end in MC address space
++ * Driver find a hole in the MC address space
++ * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
++ * registers
++ * Under VMID0, logical address inside GART aperture will
++ * be translated through gpuvm gart page table to access
++ * paged system memory
++ */
+ u64 gart_size;
+ u64 gart_start;
+ u64 gart_end;
++ /* Frame buffer aperture of this GPU device. Different from
++ * fb_start (see below), this only covers the local GPU device.
++ * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios)
++ * and calculate vram_start of this local device by adding an
++ * offset inside the XGMI hive.
++ * Under VMID0, logical address == MC address
++ */
+ u64 vram_start;
+ u64 vram_end;
+ /* FB region , it's same as local vram region in single GPU, in XGMI
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4382-drm-amd-include-Add-gfx10-debugger-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4382-drm-amd-include-Add-gfx10-debugger-registers.patch
new file mode 100644
index 00000000..f71d66ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4382-drm-amd-include-Add-gfx10-debugger-registers.patch
@@ -0,0 +1,148 @@
+From cc5c59647d0ced3f36d32ea1142806c376e3ab72 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 16 Oct 2019 07:12:32 -0400
+Subject: [PATCH 4382/4736] drm/amd/include: Add gfx10 debugger registers
+
+Add kfd debugger registers:
+ mmSPI_GDBG_WAVE_CNTL
+ mmSPI_GDBG_TRAP_CONFIG
+ mmSPI_GDBG_TRAP_MASK
+ mmSPI_GDBG_WAVE_CNTL2
+ mmSPI_GDBG_WAVE_CNTL3
+ mmSPI_GDBG_TRAP_DATA0
+ mmSPI_GDBG_TRAP_DATA1
+
+Change-Id: Idd2f0260e6801cf1785c33c0667c4332320fcd2d
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ .../include/asic_reg/gc/gc_10_1_0_default.h | 7 ++
+ .../include/asic_reg/gc/gc_10_1_0_offset.h | 14 ++++
+ .../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 69 +++++++++++++++++++
+ 3 files changed, 90 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
+index 320e1ee5df1a..2050888f7ec6 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
+@@ -2616,6 +2616,13 @@
+ #define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f
+ #define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f
+ #define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f
++#define mmSPI_GDBG_WAVE_CNTL_DEFAULT 0x00000000
++#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT 0x00000000
++#define mmSPI_GDBG_TRAP_MASK_DEFAULT 0x00000000
++#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT 0x00000000
++#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT 0x00000000
++#define mmSPI_GDBG_TRAP_DATA0_DEFAULT 0x00000000
++#define mmSPI_GDBG_TRAP_DATA1_DEFAULT 0x00000000
+ #define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000
+ #define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000
+ #define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+index 075867d4b1da..7dd32b10d23f 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+@@ -5187,6 +5187,20 @@
+ #define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0
+ #define mmSPI_WCL_PIPE_PERCENT_CS7 0x1f70
+ #define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0
++#define mmSPI_GDBG_WAVE_CNTL 0x11d1
++#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0
++#define mmSPI_GDBG_TRAP_CONFIG 0x11d2
++#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0
++#define mmSPI_GDBG_TRAP_MASK 0x11d3
++#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0
++#define mmSPI_GDBG_WAVE_CNTL2 0x11d4
++#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0
++#define mmSPI_GDBG_WAVE_CNTL3 0x11d5
++#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0
++#define mmSPI_GDBG_TRAP_DATA0 0x11d8
++#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0
++#define mmSPI_GDBG_TRAP_DATA1 0x11d9
++#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0
+ #define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b
+ #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0
+ #define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+index e7db6f9f9c86..c81cfa018738 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+@@ -19642,6 +19642,75 @@
+ //SPI_WCL_PIPE_PERCENT_CS7
+ #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
+ #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
++//SPI_GDBG_WAVE_CNTL
++#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
++#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
++#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L
++#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL
++//SPI_GDBG_TRAP_CONFIG
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L
++//SPI_GDBG_TRAP_MASK
++#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
++#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
++#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL
++#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L
++//SPI_GDBG_WAVE_CNTL2
++#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0
++#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10
++#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL
++#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L
++//SPI_GDBG_WAVE_CNTL3
++#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0
++#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1
++#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2
++#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3
++#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc
++#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd
++#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c
++#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L
++#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L
++#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L
++#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L
++#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L
++#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L
++//SPI_GDBG_TRAP_DATA0
++#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
++#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL
++//SPI_GDBG_TRAP_DATA1
++#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
++#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL
+ //SPI_COMPUTE_QUEUE_RESET
+ #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
+ #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4383-drm-amdkfd-Add-kfd-debugger-support-for-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4383-drm-amdkfd-Add-kfd-debugger-support-for-gfx10.patch
new file mode 100644
index 00000000..60c5babc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4383-drm-amdkfd-Add-kfd-debugger-support-for-gfx10.patch
@@ -0,0 +1,322 @@
+From 600b8f93502e13d7600caa9ae38edf398c42f566 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Thu, 5 Sep 2019 09:08:57 -0400
+Subject: [PATCH 4383/4736] drm/amdkfd: Add kfd debugger support for gfx10
+
+Adding code to the gfx10 code path to support the kfd debugger
+functionality.
+
+Change-Id: Ifc822fa877ffdabb7b8e3ad167515aaaddbc6e98
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 147 ++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16 ++
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c | 72 +++++++--
+ 3 files changed, 219 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 5eb289e887b3..d8fc3ba71628 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -813,6 +813,147 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+ }
+
++uint32_t kgd_gfx_v10_enable_debug_trap(struct kgd_dev *kgd,
++ uint32_t trap_debug_wave_launch_mode,
++ uint32_t vmid)
++{
++ struct amdgpu_device *adev = get_amdgpu_device(kgd);
++ uint32_t data = 0;
++ uint32_t orig_wave_cntl_value;
++ uint32_t orig_stall_vmid;
++
++ mutex_lock(&adev->grbm_idx_mutex);
++
++ orig_wave_cntl_value = RREG32(SOC15_REG_OFFSET(GC,
++ 0,
++ mmSPI_GDBG_WAVE_CNTL));
++ orig_stall_vmid = REG_GET_FIELD(orig_wave_cntl_value,
++ SPI_GDBG_WAVE_CNTL,
++ STALL_VMID);
++
++ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++ data = 0;
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
++
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), orig_stall_vmid);
++
++ mutex_unlock(&adev->grbm_idx_mutex);
++
++ return 0;
++}
++
++uint32_t kgd_gfx_v10_disable_debug_trap(struct kgd_dev *kgd)
++{
++ struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++ mutex_lock(&adev->grbm_idx_mutex);
++
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
++
++ mutex_unlock(&adev->grbm_idx_mutex);
++
++ return 0;
++}
++
++uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct kgd_dev *kgd,
++ uint32_t trap_override,
++ uint32_t trap_mask)
++{
++ struct amdgpu_device *adev = get_amdgpu_device(kgd);
++ uint32_t data = 0;
++
++ mutex_lock(&adev->grbm_idx_mutex);
++
++ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
++ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++ data = 0;
++ data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
++ EXCP_EN, trap_mask);
++ data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
++ REPLACE, trap_override);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
++
++ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
++ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 0);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++ mutex_unlock(&adev->grbm_idx_mutex);
++
++ return 0;
++}
++
++uint32_t kgd_gfx_v10_set_wave_launch_mode(struct kgd_dev *kgd,
++ uint8_t wave_launch_mode,
++ uint32_t vmid)
++{
++ struct amdgpu_device *adev = get_amdgpu_device(kgd);
++ uint32_t data = 0;
++ bool is_stall_mode;
++ bool is_mode_set;
++
++ is_stall_mode = (wave_launch_mode == 4);
++ is_mode_set = (wave_launch_mode != 0 && wave_launch_mode != 4);
++
++ mutex_lock(&adev->grbm_idx_mutex);
++
++ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
++ VMID_MASK, is_mode_set ? 1 << vmid : 0);
++ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
++ MODE, is_mode_set ? wave_launch_mode : 0);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
++
++ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
++ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
++ STALL_VMID, is_stall_mode ? 1 << vmid : 0);
++ data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
++ STALL_RA, is_stall_mode ? 1 : 0);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++ mutex_unlock(&adev->grbm_idx_mutex);
++
++ return 0;
++}
++
++/* kgd_get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values
++ * The values read are:
++ * ib_offload_wait_time -- Wait Count for Indirect Buffer Offloads.
++ * atomic_offload_wait_time -- Wait Count for L2 and GDS Atomics Offloads.
++ * wrm_offload_wait_time -- Wait Count for WAIT_REG_MEM Offloads.
++ * gws_wait_time -- Wait Count for Global Wave Syncs.
++ * que_sleep_wait_time -- Wait Count for Dequeue Retry.
++ * sch_wave_wait_time -- Wait Count for Scheduling Wave Message.
++ * sem_rearm_wait_time -- Wait Count for Semaphore re-arm.
++ * deq_retry_wait_time -- Wait Count for Global Wave Syncs.
++ */
++void kgd_gfx_v10_get_iq_wait_times(struct kgd_dev *kgd,
++ uint32_t *wait_times)
++
++{
++ struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++ *wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
++}
++
++void kgd_gfx_v10_build_grace_period_packet_info(struct kgd_dev *kgd,
++ uint32_t wait_times,
++ uint32_t grace_period,
++ uint32_t *reg_offset,
++ uint32_t *reg_data)
++{
++ *reg_data = wait_times;
++
++ *reg_data = REG_SET_FIELD(*reg_data,
++ CP_IQ_WAIT_TIME2,
++ SCH_WAVE,
++ grace_period);
++
++ *reg_offset = mmCP_IQ_WAIT_TIME2;
++}
++
+ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
+ .program_sh_mem_settings = kgd_program_sh_mem_settings,
+ .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+@@ -836,4 +977,10 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
+ .invalidate_tlbs = invalidate_tlbs,
+ .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+ .get_hive_id = amdgpu_amdkfd_get_hive_id,
++ .enable_debug_trap = kgd_gfx_v10_enable_debug_trap,
++ .disable_debug_trap = kgd_gfx_v10_disable_debug_trap,
++ .set_wave_launch_trap_override = kgd_gfx_v10_set_wave_launch_trap_override,
++ .set_wave_launch_mode = kgd_gfx_v10_set_wave_launch_mode,
++ .get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,
++ .build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index c7a6f98bf6b8..e4b4f4b09329 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1597,6 +1597,8 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
+ {
+ int i;
+ uint32_t sh_mem_bases;
++ uint32_t trap_config_vmid_mask = 0;
++ uint32_t data;
+
+ /*
+ * Configure apertures:
+@@ -1612,9 +1614,23 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
+ /* CP and shaders */
+ WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
+ WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
++
++ /* Calculate trap config vmid mask */
++ trap_config_vmid_mask |= (1 << i);
+ }
+ nv_grbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
++
++ data = 0;
++ data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
++ VMID_SEL, trap_config_vmid_mask);
++ data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
++ TRAP_EN, 1);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
++
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
+ }
+
+ static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+index efc6c37ec37e..7a695b9a2bcd 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+@@ -73,6 +73,7 @@ static int pm_map_process_v10(struct packet_manager *pm,
+ {
+ struct pm4_mes_map_process *packet;
+ uint64_t vm_page_table_base_addr = qpd->page_table_base;
++ struct kfd_dev *kfd = pm->dqm->dev;
+
+ packet = (struct pm4_mes_map_process *)buffer;
+ memset(buffer, 0, sizeof(struct pm4_mes_map_process));
+@@ -89,6 +90,11 @@ static int pm_map_process_v10(struct packet_manager *pm,
+
+ packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
+
++ if (kfd->dqm->trap_debug_vmid) {
++ packet->bitfields2.debug_vmid = kfd->dqm->trap_debug_vmid;
++ packet->bitfields2.new_debug = 1;
++ }
++
+ packet->sh_mem_config = qpd->sh_mem_config;
+ packet->sh_mem_bases = qpd->sh_mem_bases;
+ if (qpd->tba_addr) {
+@@ -206,6 +212,40 @@ static int pm_map_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+ return 0;
+ }
+
++static int pm_set_grace_period_v10(struct packet_manager *pm,
++ uint32_t *buffer,
++ uint32_t grace_period)
++{
++ struct pm4_mec_write_data_mmio *packet;
++ uint32_t reg_offset = 0;
++ uint32_t reg_data = 0;
++
++ pm->dqm->dev->kfd2kgd->build_grace_period_packet_info(
++ pm->dqm->dev->kgd,
++ pm->dqm->wait_times,
++ grace_period,
++ &reg_offset,
++ &reg_data);
++
++ if (grace_period == USE_DEFAULT_GRACE_PERIOD)
++ reg_data = pm->dqm->wait_times;
++
++ packet = (struct pm4_mec_write_data_mmio *)buffer;
++ memset(buffer, 0, sizeof(struct pm4_mec_write_data_mmio));
++
++ packet->header.u32All = pm_build_pm4_header(IT_WRITE_DATA,
++ sizeof(struct pm4_mec_write_data_mmio));
++
++ packet->bitfields2.dst_sel = dst_sel___write_data__mem_mapped_register;
++ packet->bitfields2.addr_incr =
++ addr_incr___write_data__do_not_increment_address;
++
++ packet->bitfields3.dst_mmreg_addr = reg_offset;
++
++ packet->data = reg_data;
++
++ return 0;
++}
+ static int pm_unmap_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+ enum kfd_queue_type type,
+ enum kfd_unmap_queues_filter filter,
+@@ -330,21 +370,21 @@ static int pm_release_mem_v10(uint64_t gpu_addr, uint32_t *buffer)
+ }
+
+ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+- .map_process = pm_map_process_v10,
+- .runlist = pm_runlist_v10,
+- .set_resources = pm_set_resources_vi,
+- .map_queues = pm_map_queues_v10,
+- .unmap_queues = pm_unmap_queues_v10,
+- .set_grace_period = NULL,
+- .query_status = pm_query_status_v10,
+- .release_mem = pm_release_mem_v10,
+- .map_process_size = sizeof(struct pm4_mes_map_process),
+- .runlist_size = sizeof(struct pm4_mes_runlist),
+- .set_resources_size = sizeof(struct pm4_mes_set_resources),
+- .map_queues_size = sizeof(struct pm4_mes_map_queues),
+- .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
+- .set_grace_period_size = 0,
+- .query_status_size = sizeof(struct pm4_mes_query_status),
+- .release_mem_size = sizeof(struct pm4_mec_release_mem)
++ .map_process = pm_map_process_v10,
++ .runlist = pm_runlist_v10,
++ .set_resources = pm_set_resources_vi,
++ .map_queues = pm_map_queues_v10,
++ .unmap_queues = pm_unmap_queues_v10,
++ .set_grace_period = pm_set_grace_period_v10,
++ .query_status = pm_query_status_v10,
++ .release_mem = pm_release_mem_v10,
++ .map_process_size = sizeof(struct pm4_mes_map_process),
++ .runlist_size = sizeof(struct pm4_mes_runlist),
++ .set_resources_size = sizeof(struct pm4_mes_set_resources),
++ .map_queues_size = sizeof(struct pm4_mes_map_queues),
++ .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
++ .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio),
++ .query_status_size = sizeof(struct pm4_mes_query_status),
++ .release_mem_size = sizeof(struct pm4_mec_release_mem)
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4384-drm-amdgpu-Need-to-disable-msix-when-unloading-drive.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4384-drm-amdgpu-Need-to-disable-msix-when-unloading-drive.patch
new file mode 100644
index 00000000..cee2d210
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4384-drm-amdgpu-Need-to-disable-msix-when-unloading-drive.patch
@@ -0,0 +1,32 @@
+From 744eb07f86356f4d3efc1a87c71742de310f35c0 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Thu, 7 Nov 2019 10:26:43 +0800
+Subject: [PATCH 4384/4736] drm/amdgpu: Need to disable msix when unloading
+ driver
+
+For driver reload test, it will report "can't enable
+MSI (MSI-X already enabled)".
+
+Change-Id: I939294f06c74a6bb998ce3c7bb55d1d4e8555faf
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 22edda8ad261..931c9744937a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -308,7 +308,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
+ drm_irq_uninstall(adev->ddev);
+ adev->irq.installed = false;
+ if (adev->irq.msi_enabled)
+- pci_disable_msi(adev->pdev);
++ pci_free_irq_vectors(adev->pdev);
+ if (!amdgpu_device_has_dc_support(adev))
+ flush_work(&adev->hotplug_work);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4385-drm-amdgpu-fix-sysfs-interface-pcie_replay_count-err.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4385-drm-amdgpu-fix-sysfs-interface-pcie_replay_count-err.patch
new file mode 100644
index 00000000..f6b6ff49
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4385-drm-amdgpu-fix-sysfs-interface-pcie_replay_count-err.patch
@@ -0,0 +1,47 @@
+From 6f110828854e327b49da8fd84846facc3d2e87f8 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 5 Nov 2019 18:53:30 +0800
+Subject: [PATCH 4385/4736] drm/amdgpu: fix sysfs interface pcie_replay_count
+ error on navi asic
+
+the asic callback function of get_pcie_replay_count is not implement on navi asic,
+it will cause null pinter error when read this interface.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kent Russell <kent.russell@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 88e3665f7b09..b33da33214eb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -538,6 +538,16 @@ static bool nv_need_reset_on_init(struct amdgpu_device *adev)
+ return false;
+ }
+
++static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
++{
++
++ /* TODO
++ * dummy implement for pcie_replay_count sysfs interface
++ * */
++
++ return 0;
++}
++
+ static void nv_init_doorbell_index(struct amdgpu_device *adev)
+ {
+ adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
+@@ -585,6 +595,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+ .need_full_reset = &nv_need_full_reset,
+ .get_pcie_usage = &nv_get_pcie_usage,
+ .need_reset_on_init = &nv_need_reset_on_init,
++ .get_pcie_replay_count = &nv_get_pcie_replay_count,
+ };
+
+ static int nv_common_early_init(void *handle)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4386-Revert-drm-amdgpu-Need-to-disable-msix-when-unloadin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4386-Revert-drm-amdgpu-Need-to-disable-msix-when-unloadin.patch
new file mode 100644
index 00000000..401f25ef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4386-Revert-drm-amdgpu-Need-to-disable-msix-when-unloadin.patch
@@ -0,0 +1,29 @@
+From 946c7cdb630ad0e8ab58ac963419c42b27ad2b77 Mon Sep 17 00:00:00 2001
+From: "Stanley.Yang" <Stanley.Yang@amd.com>
+Date: Thu, 7 Nov 2019 17:47:47 +0800
+Subject: [PATCH 4386/4736] Revert "drm/amdgpu: Need to disable msix when
+ unloading driver"
+
+This reverts commit 18bd755c29f993a0b206bbe084aadace5c8a1ad3.
+
+Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 931c9744937a..22edda8ad261 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -308,7 +308,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
+ drm_irq_uninstall(adev->ddev);
+ adev->irq.installed = false;
+ if (adev->irq.msi_enabled)
+- pci_free_irq_vectors(adev->pdev);
++ pci_disable_msi(adev->pdev);
+ if (!amdgpu_device_has_dc_support(adev))
+ flush_work(&adev->hotplug_work);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4387-SWDEV-210749-drm-amdgpu-Need-to-disable-msix-when-un.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4387-SWDEV-210749-drm-amdgpu-Need-to-disable-msix-when-un.patch
new file mode 100644
index 00000000..d29d88a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4387-SWDEV-210749-drm-amdgpu-Need-to-disable-msix-when-un.patch
@@ -0,0 +1,34 @@
+From 36073510926d28de485708510ca5574fc8df0d09 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Wed, 6 Nov 2019 16:20:54 +0800
+Subject: [PATCH 4387/4736] SWDEV-210749 drm/amdgpu: Need to disable msix when
+ unloading driver
+
+For driver reload test, it will report "can't enable
+MSI (MSI-X already enabled)".
+
+Change-Id: Id98a33e8404d8d803f20d9694f2f04a6e5251fb7
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 22edda8ad261..48af4830a74f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -308,7 +308,11 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
+ drm_irq_uninstall(adev->ddev);
+ adev->irq.installed = false;
+ if (adev->irq.msi_enabled)
++#ifdef PCI_IRQ_MSI
++ pci_free_irq_vectors(adev->pdev);
++#else
+ pci_disable_msi(adev->pdev);
++#endif
+ if (!amdgpu_device_has_dc_support(adev))
+ flush_work(&adev->hotplug_work);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4388-drm-amdgpu-allow-direct-upload-save-restore-list-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4388-drm-amdgpu-allow-direct-upload-save-restore-list-for.patch
new file mode 100644
index 00000000..5acb9b86
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4388-drm-amdgpu-allow-direct-upload-save-restore-list-for.patch
@@ -0,0 +1,36 @@
+From 333f6da2575dc2c88bf5355e4dd4038c997e445d Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Thu, 7 Nov 2019 14:09:27 +0800
+Subject: [PATCH 4388/4736] drm/amdgpu: allow direct upload save restore list
+ for raven2
+
+It will cause modprobe atombios stuck problem in raven2 if it doesn't
+allow direct upload save restore list from gfx driver.
+So it needs to allow direct upload save restore list for raven2
+temporarily.
+
+Change-Id: I1fece1b9c61f7a13eec948f34eb60a9120046bc2
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index b7ce3217fcf8..79cc4b95423b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2741,7 +2741,9 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
+ * And it's needed by gfxoff feature.
+ */
+ if (adev->gfx.rlc.is_rlc_v2_1) {
+- if (adev->asic_type == CHIP_VEGA12)
++ if (adev->asic_type == CHIP_VEGA12 ||
++ (adev->asic_type == CHIP_RAVEN &&
++ adev->rev_id >= 8))
+ gfx_v9_1_init_rlc_save_restore_list(adev);
+ gfx_v9_0_enable_save_restore_machine(adev);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4389-drm-amd-amdgpu-finish-delay-works-before-release-res.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4389-drm-amd-amdgpu-finish-delay-works-before-release-res.patch
new file mode 100644
index 00000000..2e6ac402
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4389-drm-amd-amdgpu-finish-delay-works-before-release-res.patch
@@ -0,0 +1,62 @@
+From 54629ccae746e54a45eb3ab21782716af37ea1b1 Mon Sep 17 00:00:00 2001
+From: Jesse Zhang <zhexi.zhang@amd.com>
+Date: Fri, 8 Nov 2019 18:06:07 +0800
+Subject: [PATCH 4389/4736] drm/amd/amdgpu: finish delay works before release
+ resources
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+flush/cancel delayed works before doing finalization
+to avoid concurrently requests.
+
+Change-Id: I85b7ffbb34875af1c734cb4573a6ecc71d39d652
+Signed-off-by: Jesse Zhang <zhexi.zhang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 1 +
+ 3 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 09ef0eaf1abc..8bfbcbcb7f2e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3118,6 +3118,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+
+ DRM_INFO("amdgpu: finishing device.\n");
+ adev->shutdown = true;
++
++ flush_delayed_work(&adev->delayed_init_work);
++
+ /* disable all interrupts */
+ amdgpu_irq_disable_all(adev);
+ if (adev->mode_info.mode_config_initialized){
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index d1b10b5583ec..32128e982e4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -299,6 +299,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
+ {
+ int i, j;
+
++ cancel_delayed_work_sync(&adev->uvd.idle_work);
+ drm_sched_entity_destroy(&adev->uvd.entity);
+
+ for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index 92aa3b1b34ce..f70b55f9d904 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -216,6 +216,7 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
+ if (adev->vce.vcpu_bo == NULL)
+ return 0;
+
++ cancel_delayed_work_sync(&adev->vce.idle_work);
+ drm_sched_entity_destroy(&adev->vce.entity);
+
+ amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4390-drm-amdgpu-fix-vega20-pstate-status-change.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4390-drm-amdgpu-fix-vega20-pstate-status-change.patch
new file mode 100644
index 00000000..712100ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4390-drm-amdgpu-fix-vega20-pstate-status-change.patch
@@ -0,0 +1,50 @@
+From 99e982dad30772ca6c977f5c5bc2e2ba6f89fb04 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Wed, 6 Nov 2019 08:20:21 -0500
+Subject: [PATCH 4390/4736] drm/amdgpu: fix vega20 pstate status change
+
+vega20 only requires all devices be set to same pstate level for low
+pstate and not high.
+
+Change-Id: I399c84a47f6e24abca937ce950685c0c7f0e3279
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Evan Quan <Evan.Quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index e58bad7f64c6..6c6893b94114 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -276,6 +276,7 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
+ struct amdgpu_device *tmp_adev;
+ bool update_hive_pstate = true;
++ bool is_high_pstate = pstate && adev->asic_type == CHIP_VEGA20;
+
+ if (!hive)
+ return 0;
+@@ -283,8 +284,8 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ mutex_lock(&hive->hive_lock);
+
+ if (hive->pstate == pstate) {
+- mutex_unlock(&hive->hive_lock);
+- return 0;
++ adev->pstate = is_high_pstate ? pstate : adev->pstate;
++ goto out;
+ }
+
+ dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
+@@ -317,7 +318,7 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ break;
+ }
+ }
+- if (update_hive_pstate)
++ if (update_hive_pstate || is_high_pstate)
+ hive->pstate = pstate;
+
+ out:
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4391-drm-sched-Use-completion-to-wait-for-sched-thread-id.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4391-drm-sched-Use-completion-to-wait-for-sched-thread-id.patch
new file mode 100644
index 00000000..59b768c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4391-drm-sched-Use-completion-to-wait-for-sched-thread-id.patch
@@ -0,0 +1,133 @@
+From f9cb85904d432a3edfa96931060e86ed1c06c741 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 4 Nov 2019 16:30:05 -0500
+Subject: [PATCH 4391/4736] drm/sched: Use completion to wait for sched->thread
+ idle v2.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Removes thread park/unpark hack from drm_sched_entity_fini and
+by this fixes reactivation of scheduler thread while the thread
+is supposed to be stopped.
+
+v2: Per sched entity completion.
+
+Change-Id: I9d1eca2ddcfaf3c1e4ed455e02358a0a396d822d
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Suggested-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_entity.c | 12 ++++++++----
+ drivers/gpu/drm/scheduler/sched_main.c | 6 ++++++
+ include/drm/gpu_scheduler.h | 3 +++
+ 3 files changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c
+index 671c90f34ede..797e8ba9bafb 100644
+--- a/drivers/gpu/drm/scheduler/sched_entity.c
++++ b/drivers/gpu/drm/scheduler/sched_entity.c
+@@ -22,6 +22,7 @@
+ */
+
+ #include <linux/kthread.h>
++#include <linux/completion.h>
+ #include <drm/gpu_scheduler.h>
+
+ #include "gpu_scheduler_trace.h"
+@@ -65,6 +66,8 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
+ if (!entity->rq_list)
+ return -ENOMEM;
+
++ init_completion(&entity->entity_idle);
++
+ for (i = 0; i < num_rq_list; ++i)
+ entity->rq_list[i] = rq_list[i];
+
+@@ -283,11 +286,12 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
+ */
+ if (spsc_queue_count(&entity->job_queue)) {
+ if (sched) {
+- /* Park the kernel for a moment to make sure it isn't processing
+- * our enity.
++ /*
++ * Wait for thread to idle to make sure it isn't processing
++ * this entity.
+ */
+- kthread_park(sched->thread);
+- kthread_unpark(sched->thread);
++ wait_for_completion(&entity->entity_idle);
++
+ }
+ if (entity->dependency) {
+ dma_fence_remove_callback(entity->dependency,
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index 007abab5dae6..108bac88dedb 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -47,6 +47,7 @@
+ #include <linux/kthread.h>
+ #include <linux/wait.h>
+ #include <linux/sched.h>
++#include <linux/completion.h>
+ #include <uapi/linux/sched/types.h>
+ #include <drm/drmP.h>
+ #include <drm/gpu_scheduler.h>
+@@ -135,6 +136,7 @@ drm_sched_rq_select_entity(struct drm_sched_rq *rq)
+ list_for_each_entry_continue(entity, &rq->entities, list) {
+ if (drm_sched_entity_is_ready(entity)) {
+ rq->current_entity = entity;
++ reinit_completion(&entity->entity_idle);
+ spin_unlock(&rq->lock);
+ return entity;
+ }
+@@ -145,6 +147,7 @@ drm_sched_rq_select_entity(struct drm_sched_rq *rq)
+
+ if (drm_sched_entity_is_ready(entity)) {
+ rq->current_entity = entity;
++ reinit_completion(&entity->entity_idle);
+ spin_unlock(&rq->lock);
+ return entity;
+ }
+@@ -721,6 +724,9 @@ static int drm_sched_main(void *param)
+ continue;
+
+ sched_job = drm_sched_entity_pop_job(entity);
++
++ complete(&entity->entity_idle);
++
+ if (!sched_job)
+ continue;
+
+diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
+index 4d877441145e..3dca3c8bced6 100644
+--- a/include/drm/gpu_scheduler.h
++++ b/include/drm/gpu_scheduler.h
+@@ -26,6 +26,7 @@
+
+ #include <drm/spsc_queue.h>
+ #include <linux/dma-fence.h>
++#include <linux/completion.h>
+
+ #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
+
+@@ -68,6 +69,7 @@ enum drm_sched_priority {
+ * @last_scheduled: points to the finished fence of the last scheduled job.
+ * @last_user: last group leader pushing a job into the entity.
+ * @stopped: Marks the enity as removed from rq and destined for termination.
++ * @entity_idle: Signals when enityt is not in use
+ *
+ * Entities will emit jobs in order to their corresponding hardware
+ * ring, and the scheduler will alternate between entities based on
+@@ -91,6 +93,7 @@ struct drm_sched_entity {
+ struct dma_fence *last_scheduled;
+ struct task_struct *last_user;
+ bool stopped;
++ struct completion entity_idle;
+ };
+
+ /**
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4392-drm-amdgpu-Avoid-accidental-thread-thread-reactivati.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4392-drm-amdgpu-Avoid-accidental-thread-thread-reactivati.patch
new file mode 100644
index 00000000..1ecb69e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4392-drm-amdgpu-Avoid-accidental-thread-thread-reactivati.patch
@@ -0,0 +1,70 @@
+From ebe29fddda96d8c4cde06852ea93e34b4c03ceed Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 6 Nov 2019 12:36:29 -0500
+Subject: [PATCH 4392/4736] drm/amdgpu: Avoid accidental thread thread
+ reactivation.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Problem:
+During GPU reset we call the GPU scheduler to suspend it's
+thread, those two functions in amdgpu also suspend and resume
+the sceduler for their needs but this can collide with GPU
+reset in progress and accidently restart a suspended thread
+before time.
+
+Fix:
+Serialize with GPU reset.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+index 996cb998dc1f..f448b45ad802 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -856,6 +856,9 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
+ struct amdgpu_device *adev = dev->dev_private;
+ int r = 0, i;
+
++ /* Avoid accidently unparking the sched thread during GPU reset */
++ mutex_lock(&adev->lock_reset);
++
+ /* hold on the scheduler */
+ for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+ struct amdgpu_ring *ring = adev->rings[i];
+@@ -881,6 +884,8 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
+ kthread_unpark(ring->sched.thread);
+ }
+
++ mutex_unlock(&adev->lock_reset);
++
+ return 0;
+ }
+
+@@ -1033,6 +1038,9 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
+ if (!fences)
+ return -ENOMEM;
+
++ /* Avoid accidently unparking the sched thread during GPU reset */
++ mutex_lock(&adev->lock_reset);
++
+ /* stop the scheduler */
+ kthread_park(ring->sched.thread);
+
+@@ -1072,6 +1080,8 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
+ /* restart the scheduler */
+ kthread_unpark(ring->sched.thread);
+
++ mutex_unlock(&adev->lock_reset);
++
+ ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
+
+ kfree(fences);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4393-drm-amdkfd-Adjust-function-sequences-to-avoid-unnece.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4393-drm-amdkfd-Adjust-function-sequences-to-avoid-unnece.patch
new file mode 100644
index 00000000..f6da318e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4393-drm-amdkfd-Adjust-function-sequences-to-avoid-unnece.patch
@@ -0,0 +1,55 @@
+From b3fe14e57b9058a079e5b8314a8411a1fcdb7f35 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 30 Oct 2019 18:07:20 -0400
+Subject: [PATCH 4393/4736] drm/amdkfd: Adjust function sequences to avoid
+ unnecessary declarations
+
+This is cleaner.
+
+Change-Id: I8cdecad387d8c547a088c6050f77385ee1135be1
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 19 +++++++------------
+ 1 file changed, 7 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index f7d9dac26485..b5c077b50d1a 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -26,18 +26,6 @@
+ #include "kfd_pm4_headers_ai.h"
+ #include "kfd_pm4_opcodes.h"
+
+-static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_v9(struct kernel_queue *kq);
+-static void submit_packet_v9(struct kernel_queue *kq);
+-
+-void kernel_queue_init_v9(struct kernel_queue_ops *ops)
+-{
+- ops->initialize = initialize_v9;
+- ops->uninitialize = uninitialize_v9;
+- ops->submit_packet = submit_packet_v9;
+-}
+-
+ static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+ enum kfd_queue_type type, unsigned int queue_size)
+ {
+@@ -67,6 +55,13 @@ static void submit_packet_v9(struct kernel_queue *kq)
+ kq->pending_wptr64);
+ }
+
++void kernel_queue_init_v9(struct kernel_queue_ops *ops)
++{
++ ops->initialize = initialize_v9;
++ ops->uninitialize = uninitialize_v9;
++ ops->submit_packet = submit_packet_v9;
++}
++
+ static int pm_map_process_v9(struct packet_manager *pm,
+ uint32_t *buffer, struct qcm_process_device *qpd)
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4394-drm-amdkfd-Only-keep-release_mem-function-for-Hawaii.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4394-drm-amdkfd-Only-keep-release_mem-function-for-Hawaii.patch
new file mode 100644
index 00000000..5b31dfde
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4394-drm-amdkfd-Only-keep-release_mem-function-for-Hawaii.patch
@@ -0,0 +1,136 @@
+From ac6b4c83d151966d129fd5eea92087da0d02702b Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 30 Oct 2019 19:22:11 -0400
+Subject: [PATCH 4394/4736] drm/amdkfd: Only keep release_mem function for
+ Hawaii
+
+release_mem is only used for Hawaii, but because GFX7 and GFX8 share the
+same function pointer structure, so we only delete release_mem for GFX9
+and GFX10.
+
+Change-Id: I13787a8a29b83e7516c582a7401f2e14721edf5f
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c | 35 ++-----------------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 33 ++---------------
+ 2 files changed, 4 insertions(+), 64 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+index 7a695b9a2bcd..5ee593ba3137 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+@@ -338,37 +338,6 @@ static int pm_query_status_v10(struct packet_manager *pm, uint32_t *buffer,
+ return 0;
+ }
+
+-
+-static int pm_release_mem_v10(uint64_t gpu_addr, uint32_t *buffer)
+-{
+- struct pm4_mec_release_mem *packet;
+-
+- WARN_ON(!buffer);
+-
+- packet = (struct pm4_mec_release_mem *)buffer;
+- memset(buffer, 0, sizeof(struct pm4_mec_release_mem));
+-
+- packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
+- sizeof(struct pm4_mec_release_mem));
+-
+- packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
+- packet->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe;
+- packet->bitfields2.tcl1_action_ena = 1;
+- packet->bitfields2.tc_action_ena = 1;
+- packet->bitfields2.cache_policy = cache_policy__mec_release_mem__lru;
+-
+- packet->bitfields3.data_sel = data_sel__mec_release_mem__send_32_bit_low;
+- packet->bitfields3.int_sel =
+- int_sel__mec_release_mem__send_interrupt_after_write_confirm;
+-
+- packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
+- packet->address_hi = upper_32_bits(gpu_addr);
+-
+- packet->data_lo = 0;
+-
+- return sizeof(struct pm4_mec_release_mem) / sizeof(unsigned int);
+-}
+-
+ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+ .map_process = pm_map_process_v10,
+ .runlist = pm_runlist_v10,
+@@ -377,7 +346,7 @@ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+ .unmap_queues = pm_unmap_queues_v10,
+ .set_grace_period = pm_set_grace_period_v10,
+ .query_status = pm_query_status_v10,
+- .release_mem = pm_release_mem_v10,
++ .release_mem = NULL,
+ .map_process_size = sizeof(struct pm4_mes_map_process),
+ .runlist_size = sizeof(struct pm4_mes_runlist),
+ .set_resources_size = sizeof(struct pm4_mes_set_resources),
+@@ -385,6 +354,6 @@ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+ .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
+ .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio),
+ .query_status_size = sizeof(struct pm4_mes_query_status),
+- .release_mem_size = sizeof(struct pm4_mec_release_mem)
++ .release_mem_size = 0,
+ };
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index b5c077b50d1a..42aefc976838 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -377,35 +377,6 @@ static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,
+ return 0;
+ }
+
+-
+-static int pm_release_mem_v9(uint64_t gpu_addr, uint32_t *buffer)
+-{
+- struct pm4_mec_release_mem *packet;
+-
+- packet = (struct pm4_mec_release_mem *)buffer;
+- memset(buffer, 0, sizeof(struct pm4_mec_release_mem));
+-
+- packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
+- sizeof(struct pm4_mec_release_mem));
+-
+- packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
+- packet->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe;
+- packet->bitfields2.tcl1_action_ena = 1;
+- packet->bitfields2.tc_action_ena = 1;
+- packet->bitfields2.cache_policy = cache_policy__mec_release_mem__lru;
+-
+- packet->bitfields3.data_sel = data_sel__mec_release_mem__send_32_bit_low;
+- packet->bitfields3.int_sel =
+- int_sel__mec_release_mem__send_interrupt_after_write_confirm;
+-
+- packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
+- packet->address_hi = upper_32_bits(gpu_addr);
+-
+- packet->data_lo = 0;
+-
+- return 0;
+-}
+-
+ const struct packet_manager_funcs kfd_v9_pm_funcs = {
+ .map_process = pm_map_process_v9,
+ .runlist = pm_runlist_v9,
+@@ -414,7 +385,7 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = {
+ .unmap_queues = pm_unmap_queues_v9,
+ .set_grace_period = pm_set_grace_period_v9,
+ .query_status = pm_query_status_v9,
+- .release_mem = pm_release_mem_v9,
++ .release_mem = NULL,
+ .map_process_size = sizeof(struct pm4_mes_map_process),
+ .runlist_size = sizeof(struct pm4_mes_runlist),
+ .set_resources_size = sizeof(struct pm4_mes_set_resources),
+@@ -422,5 +393,5 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = {
+ .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
+ .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio),
+ .query_status_size = sizeof(struct pm4_mes_query_status),
+- .release_mem_size = sizeof(struct pm4_mec_release_mem)
++ .release_mem_size = 0,
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4395-drm-amd-display-initialize-lttpr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4395-drm-amd-display-initialize-lttpr.patch
new file mode 100644
index 00000000..8cc3f49f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4395-drm-amd-display-initialize-lttpr.patch
@@ -0,0 +1,184 @@
+From 78a856ebb3735507182f57303745004582b06d9d Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Fri, 19 Jul 2019 10:25:39 -0400
+Subject: [PATCH 4395/4736] drm/amd/display: initialize lttpr
+
+[Description]
+When reading link, update the procedure as follows:
+1-Set aux timeout to extended: 3.2ms
+2-Start with reading lttpr caps
+3-Determine if lttpr support should be enabled. Reset aux timeout to
+400us if no repeater is found.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 56 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +
+ drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
+ drivers/gpu/drm/amd/display/dc/dc_types.h | 36 ++++++++++++
+ 4 files changed, 95 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 0f59b68aa4c2..2a89f90ef7a7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -21,6 +21,9 @@
+ #define DC_LOGGER \
+ link->ctx->logger
+
++
++#define DP_REPEATER_CONFIGURATION_AND_STATUS_OFFSET 0x50
++
+ /* maximum pre emphasis level allowed for each voltage swing level*/
+ static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
+ PRE_EMPHASIS_LEVEL3,
+@@ -2753,6 +2756,14 @@ static bool retrieve_link_cap(struct dc_link *link)
+ int i;
+ struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+
++ /* Set default timeout to 3.2ms and read LTTPR capabilities */
++ bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
++ !link->dc->config.disable_extended_timeout_support;
++ if (ext_timeout_support) {
++ status = dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
++ link->is_lttpr_mode_transparent = true;
++ }
++
+ memset(dpcd_data, '\0', sizeof(dpcd_data));
+ memset(&down_strm_port_count,
+ '\0', sizeof(union down_stream_port_count));
+@@ -2785,6 +2796,51 @@ static bool retrieve_link_cap(struct dc_link *link)
+ return false;
+ }
+
++ if (ext_timeout_support) {
++ status = core_link_read_dpcd(
++ link,
++ DP_PHY_REPEATER_CNT,
++ &link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
++ sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
++
++ if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0) {
++
++ link->is_lttpr_mode_transparent = false;
++
++ status = core_link_read_dpcd(
++ link,
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
++ (uint8_t *)&link->dpcd_caps.lttpr_caps.revision,
++ sizeof(link->dpcd_caps.lttpr_caps.revision));
++
++ status = core_link_read_dpcd(
++ link,
++ DP_MAX_LINK_RATE_PHY_REPEATER,
++ &link->dpcd_caps.lttpr_caps.max_link_rate,
++ sizeof(link->dpcd_caps.lttpr_caps.max_link_rate));
++
++ status = core_link_read_dpcd(
++ link,
++ DP_PHY_REPEATER_MODE,
++ (uint8_t *)&link->dpcd_caps.lttpr_caps.mode,
++ sizeof(link->dpcd_caps.lttpr_caps.mode));
++
++ status = core_link_read_dpcd(
++ link,
++ DP_MAX_LANE_COUNT_PHY_REPEATER,
++ &link->dpcd_caps.lttpr_caps.max_lane_count,
++ sizeof(link->dpcd_caps.lttpr_caps.max_lane_count));
++
++ status = core_link_read_dpcd(
++ link,
++ DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
++ &link->dpcd_caps.lttpr_caps.max_ext_timeout,
++ sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
++ } else {
++ dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
++ }
++ }
++
+ {
+ union training_aux_rd_interval aux_rd_interval;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index f12ad4b17781..8ff7556eb2c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -994,6 +994,8 @@ struct dpcd_caps {
+ union dpcd_fec_capability fec_cap;
+ struct dpcd_dsc_capabilities dsc_caps;
+ #endif
++ struct dc_lttpr_caps lttpr_caps;
++
+ };
+
+ #include "dc_link.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 9270e43cd5bb..67ba6666a324 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -85,6 +85,7 @@ struct dc_link {
+ bool link_state_valid;
+ bool aux_access_disabled;
+ bool sync_lt_in_progress;
++ bool is_lttpr_mode_transparent;
+
+ /* caps is the same as reported_link_cap. link_traing use
+ * reported_link_cap. Will clean up. TODO
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 7ab7644458e7..837859e65e45 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -122,6 +122,7 @@ struct dc_context {
+ #define DC_EDID_BLOCK_SIZE 128
+ #define MAX_SURFACE_NUM 4
+ #define NUM_PIXEL_FORMATS 10
++#define MAX_REPEATER_CNT 8
+
+ #include "dc_ddc_types.h"
+
+@@ -405,6 +406,41 @@ enum dpcd_downstream_port_max_bpc {
+ DOWN_STREAM_MAX_12BPC,
+ DOWN_STREAM_MAX_16BPC
+ };
++
++
++enum link_training_offset {
++ DPRX = 0,
++ LTTPR_PHY_REPEATER1 = 1,
++ LTTPR_PHY_REPEATER2 = 2,
++ LTTPR_PHY_REPEATER3 = 3,
++ LTTPR_PHY_REPEATER4 = 4,
++ LTTPR_PHY_REPEATER5 = 5,
++ LTTPR_PHY_REPEATER6 = 6,
++ LTTPR_PHY_REPEATER7 = 7,
++ LTTPR_PHY_REPEATER8 = 8
++};
++
++enum lttpr_mode {
++ phy_repeater_mode_transparent = 0x55,
++ phy_repeater_mode_non_transparent = 0xAA
++};
++
++enum lttpr_rev {
++ lttpr_rev_unknown = 0x0,
++ lttpr_rev_14 = 0x14,
++ lttpr_rev_max = 0x20
++};
++
++struct dc_lttpr_caps {
++ enum lttpr_rev revision;
++ enum lttpr_mode mode;
++ uint8_t max_lane_count;
++ uint8_t max_link_rate;
++ uint8_t phy_repeater_cnt;
++ uint8_t max_ext_timeout;
++ uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
++};
++
+ struct dc_dongle_caps {
+ /* dongle type (DP converter, CV smart dongle) */
+ enum display_dongle_type dongle_type;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4396-drm-amd-display-check-for-dp-rev-before-reading-lttp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4396-drm-amd-display-check-for-dp-rev-before-reading-lttp.patch
new file mode 100644
index 00000000..12fcd76a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4396-drm-amd-display-check-for-dp-rev-before-reading-lttp.patch
@@ -0,0 +1,47 @@
+From 92a6ea98405ccb7b2c47b2480a1e43bbc7e5d1a1 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Wed, 18 Sep 2019 11:57:47 -0400
+Subject: [PATCH 4396/4736] drm/amd/display: check for dp rev before reading
+ lttpr regs
+
+[Why]
+LTTPR was introduced after DP1.2. Reading LTTPR registers 0xFXXXX
+on some DP 1.2 display is causing an unexpected behavior.
+
+[How]
+Make sure that we don't read any lttpr registers on 1.2 displays.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 2a89f90ef7a7..1e4480f3bd3c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2759,9 +2759,10 @@ static bool retrieve_link_cap(struct dc_link *link)
+ /* Set default timeout to 3.2ms and read LTTPR capabilities */
+ bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
+ !link->dc->config.disable_extended_timeout_support;
++ link->is_lttpr_mode_transparent = true;
++
+ if (ext_timeout_support) {
+ status = dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
+- link->is_lttpr_mode_transparent = true;
+ }
+
+ memset(dpcd_data, '\0', sizeof(dpcd_data));
+@@ -2796,7 +2797,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ return false;
+ }
+
+- if (ext_timeout_support) {
++ if (ext_timeout_support && link->dpcd_caps.dpcd_rev.raw >= 0x14) {
+ status = core_link_read_dpcd(
+ link,
+ DP_PHY_REPEATER_CNT,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4397-drm-amd-display-configure-lttpr-mode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4397-drm-amd-display-configure-lttpr-mode.patch
new file mode 100644
index 00000000..d50e4f90
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4397-drm-amd-display-configure-lttpr-mode.patch
@@ -0,0 +1,100 @@
+From e56d9800bac89178bca2adae9ce2f4775f561262 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Fri, 19 Jul 2019 10:43:42 -0400
+Subject: [PATCH 4397/4736] drm/amd/display: configure lttpr mode
+
+[Description]
+1-Grant extended timeout request. Done once after detection
+2-Configure lttpr mode based on lttpr support before LT
+3-Account for lttpr cap when determining max link settings
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 1e4480f3bd3c..94d5a0ac308f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1057,6 +1057,26 @@ static void initialize_training_settings(
+ lt_settings->enhanced_framing = 1;
+ }
+
++static void configure_lttpr_mode(struct dc_link *link)
++{
++ /* aux timeout is already set to extended */
++ /* RESET/SET lttpr mode to enable non transparent mode */
++ enum lttpr_mode repeater_mode = phy_repeater_mode_transparent;
++
++ core_link_write_dpcd(link,
++ DP_PHY_REPEATER_MODE,
++ (uint8_t *)&repeater_mode,
++ sizeof(repeater_mode));
++
++ if (!link->is_lttpr_mode_transparent) {
++ repeater_mode = phy_repeater_mode_non_transparent;
++ core_link_write_dpcd(link,
++ DP_PHY_REPEATER_MODE,
++ (uint8_t *)&repeater_mode,
++ sizeof(repeater_mode));
++ }
++}
++
+ static void print_status_message(
+ struct dc_link *link,
+ const struct link_training_settings *lt_settings,
+@@ -1210,6 +1230,9 @@ enum link_training_result dc_link_dp_perform_link_training(
+ dp_set_fec_ready(link, fec_enable);
+ #endif
+
++ /* Configure lttpr mode */
++ if (!link->is_lttpr_mode_transparent)
++ configure_lttpr_mode(link);
+
+ /* 2. perform link training (set link training done
+ * to false is done as well)
+@@ -1426,6 +1449,17 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
+ max_link_cap.link_spread)
+ max_link_cap.link_spread =
+ link->reported_link_cap.link_spread;
++ /*
++ * account for lttpr repeaters cap
++ * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
++ */
++ if (!link->is_lttpr_mode_transparent) {
++ if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
++ max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
++
++ if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
++ max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
++ }
+ return max_link_cap;
+ }
+
+@@ -1571,6 +1605,13 @@ bool dp_verify_link_cap(
+
+ max_link_cap = get_max_link_cap(link);
+
++ /* Grant extended timeout request */
++ if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
++ uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
++
++ core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
++ }
++
+ /* TODO implement override and monitor patch later */
+
+ /* try to train the link from high to low to
+@@ -2759,6 +2800,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ /* Set default timeout to 3.2ms and read LTTPR capabilities */
+ bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
+ !link->dc->config.disable_extended_timeout_support;
++
+ link->is_lttpr_mode_transparent = true;
+
+ if (ext_timeout_support) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4398-drm-amd-display-implement-lttpr-logic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4398-drm-amd-display-implement-lttpr-logic.patch
new file mode 100644
index 00000000..556dee89
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4398-drm-amd-display-implement-lttpr-logic.patch
@@ -0,0 +1,729 @@
+From b8a60f6929135d3786e37046d7e736a6b975237d Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Wed, 24 Jul 2019 11:01:44 -0400
+Subject: [PATCH 4398/4736] drm/amd/display: implement lttpr logic
+
+1-If at least one repeater is present in the link and we are in non
+transparent mode, perform clock recovery then channel equalization
+with all repeaters one by one before training DPRX.
+
+2-Mark the end of LT with a repeater by setting training pattern 0
+at the end of channel equalization with each repeater.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 319 ++++++++++++++----
+ .../drm/amd/display/dc/core/dc_link_hwss.c | 39 ++-
+ .../gpu/drm/amd/display/dc/inc/link_hwss.h | 6 +-
+ 3 files changed, 292 insertions(+), 72 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 94d5a0ac308f..11b6e14b345e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -22,7 +22,7 @@
+ link->ctx->logger
+
+
+-#define DP_REPEATER_CONFIGURATION_AND_STATUS_OFFSET 0x50
++#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
+
+ /* maximum pre emphasis level allowed for each voltage swing level*/
+ static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
+@@ -224,19 +224,31 @@ static enum dpcd_training_patterns
+ return dpcd_tr_pattern;
+ }
+
++static inline bool is_repeater(struct dc_link *link, uint32_t offset)
++{
++ return (!link->is_lttpr_mode_transparent && offset != 0);
++}
++
+ static void dpcd_set_lt_pattern_and_lane_settings(
+ struct dc_link *link,
+ const struct link_training_settings *lt_settings,
+- enum dc_dp_training_pattern pattern)
++ enum dc_dp_training_pattern pattern,
++ uint32_t offset)
+ {
+ union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
+- const uint32_t dpcd_base_lt_offset =
+- DP_TRAINING_PATTERN_SET;
++
++ uint32_t dpcd_base_lt_offset;
++
+ uint8_t dpcd_lt_buffer[5] = {0};
+ union dpcd_training_pattern dpcd_pattern = { {0} };
+ uint32_t lane;
+ uint32_t size_in_bytes;
+ bool edp_workaround = false; /* TODO link_prop.INTERNAL */
++ dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
++
++ if (is_repeater(link, offset))
++ dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
++ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+
+ /*****************************************************************
+ * DpcdAddress_TrainingPatternSet
+@@ -244,12 +256,12 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
+ dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
+
+- dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
++ dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
+ = dpcd_pattern.raw;
+
+- DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
++ DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
+ __func__,
+- DP_TRAINING_PATTERN_SET,
++ dpcd_base_lt_offset,
+ dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
+
+ /*****************************************************************
+@@ -271,19 +283,19 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
+ }
+
+- /* concatinate everything into one buffer*/
++ /* concatenate everything into one buffer*/
+
+ size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
+
+ // 0x00103 - 0x00102
+ memmove(
+- &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
++ &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
+ dpcd_lane,
+ size_in_bytes);
+
+- DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
++ DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
+ __func__,
+- DP_TRAINING_LANE0_SET,
++ dpcd_base_lt_offset,
+ dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+ dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+ dpcd_lane[0].bits.MAX_SWING_REACHED,
+@@ -498,8 +510,12 @@ static void get_lane_status_and_drive_settings(
+ const struct link_training_settings *link_training_setting,
+ union lane_status *ln_status,
+ union lane_align_status_updated *ln_status_updated,
+- struct link_training_settings *req_settings)
++ struct link_training_settings *req_settings,
++ uint32_t offset)
+ {
++ unsigned int lane01_status_address = DP_LANE0_1_STATUS;
++ uint8_t lane_adjust_offset = 4;
++ unsigned int lane01_adjust_address;
+ uint8_t dpcd_buf[6] = {0};
+ union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+ struct link_training_settings request_settings = { {0} };
+@@ -507,9 +523,16 @@ static void get_lane_status_and_drive_settings(
+
+ memset(req_settings, '\0', sizeof(struct link_training_settings));
+
++ if (is_repeater(link, offset)) {
++ lane01_status_address =
++ DP_LANE0_1_STATUS_PHY_REPEATER1 +
++ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
++ lane_adjust_offset = 3;
++ }
++
+ core_link_read_dpcd(
+ link,
+- DP_LANE0_1_STATUS,
++ lane01_status_address,
+ (uint8_t *)(dpcd_buf),
+ sizeof(dpcd_buf));
+
+@@ -520,22 +543,28 @@ static void get_lane_status_and_drive_settings(
+ ln_status[lane].raw =
+ get_nibble_at_index(&dpcd_buf[0], lane);
+ dpcd_lane_adjust[lane].raw =
+- get_nibble_at_index(&dpcd_buf[4], lane);
++ get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
+ }
+
+ ln_status_updated->raw = dpcd_buf[2];
+
+- DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
++ DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
+ __func__,
+- DP_LANE0_1_STATUS, dpcd_buf[0],
+- DP_LANE2_3_STATUS, dpcd_buf[1]);
++ lane01_status_address, dpcd_buf[0],
++ lane01_status_address + 1, dpcd_buf[1]);
++
++ lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
++
++ if (is_repeater(link, offset))
++ lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
++ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+
+- DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
++ DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
+ __func__,
+- DP_ADJUST_REQUEST_LANE0_1,
+- dpcd_buf[4],
+- DP_ADJUST_REQUEST_LANE2_3,
+- dpcd_buf[5]);
++ lane01_adjust_address,
++ dpcd_buf[lane_adjust_offset],
++ lane01_adjust_address + 1,
++ dpcd_buf[lane_adjust_offset + 1]);
+
+ /*copy to req_settings*/
+ request_settings.link_settings.lane_count =
+@@ -574,10 +603,18 @@ static void get_lane_status_and_drive_settings(
+
+ static void dpcd_set_lane_settings(
+ struct dc_link *link,
+- const struct link_training_settings *link_training_setting)
++ const struct link_training_settings *link_training_setting,
++ uint32_t offset)
+ {
+ union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
+ uint32_t lane;
++ unsigned int lane0_set_address;
++
++ lane0_set_address = DP_TRAINING_LANE0_SET;
++
++ if (is_repeater(link, offset))
++ lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
++ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+
+ for (lane = 0; lane <
+ (uint32_t)(link_training_setting->
+@@ -600,7 +637,7 @@ static void dpcd_set_lane_settings(
+ }
+
+ core_link_write_dpcd(link,
+- DP_TRAINING_LANE0_SET,
++ lane0_set_address,
+ (uint8_t *)(dpcd_lane),
+ link_training_setting->link_settings.lane_count);
+
+@@ -623,9 +660,9 @@ static void dpcd_set_lane_settings(
+ }
+ */
+
+- DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
++ DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
+ __func__,
+- DP_TRAINING_LANE0_SET,
++ lane0_set_address,
+ dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+ dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+ dpcd_lane[0].bits.MAX_SWING_REACHED,
+@@ -650,17 +687,6 @@ static bool is_max_vs_reached(
+
+ }
+
+-void dc_link_dp_set_drive_settings(
+- struct dc_link *link,
+- struct link_training_settings *lt_settings)
+-{
+- /* program ASIC PHY settings*/
+- dp_set_hw_lane_settings(link, lt_settings);
+-
+- /* Notify DP sink the PHY settings from source */
+- dpcd_set_lane_settings(link, lt_settings);
+-}
+-
+ static bool perform_post_lt_adj_req_sequence(
+ struct dc_link *link,
+ struct link_training_settings *lt_settings)
+@@ -693,7 +719,8 @@ static bool perform_post_lt_adj_req_sequence(
+ lt_settings,
+ dpcd_lane_status,
+ &dpcd_lane_status_updated,
+- &req_settings);
++ &req_settings,
++ DPRX);
+
+ if (dpcd_lane_status_updated.bits.
+ POST_LT_ADJ_REQ_IN_PROGRESS == 0)
+@@ -750,6 +777,31 @@ static bool perform_post_lt_adj_req_sequence(
+
+ }
+
++/* Only used for channel equalization */
++static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
++{
++ unsigned int aux_rd_interval_us = 400;
++
++ switch (dpcd_aux_read_interval) {
++ case 0x01:
++ aux_rd_interval_us = 400;
++ break;
++ case 0x02:
++ aux_rd_interval_us = 4000;
++ break;
++ case 0x03:
++ aux_rd_interval_us = 8000;
++ break;
++ case 0x04:
++ aux_rd_interval_us = 16000;
++ break;
++ default:
++ break;
++ }
++
++ return aux_rd_interval_us;
++}
++
+ static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
+ union lane_status *dpcd_lane_status)
+ {
+@@ -768,37 +820,55 @@ static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
+
+ static enum link_training_result perform_channel_equalization_sequence(
+ struct dc_link *link,
+- struct link_training_settings *lt_settings)
++ struct link_training_settings *lt_settings,
++ uint32_t offset)
+ {
+ struct link_training_settings req_settings;
+ enum dc_dp_training_pattern tr_pattern;
+ uint32_t retries_ch_eq;
++ uint32_t wait_time_microsec;
+ enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
+ union lane_align_status_updated dpcd_lane_status_updated = { {0} };
+ union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+
++ /* Note: also check that TPS4 is a supported feature*/
++
+ tr_pattern = lt_settings->pattern_for_eq;
+
+- dp_set_hw_training_pattern(link, tr_pattern);
++ if (is_repeater(link, offset))
++ tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
++
++ dp_set_hw_training_pattern(link, tr_pattern, offset);
+
+ for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
+ retries_ch_eq++) {
+
+- dp_set_hw_lane_settings(link, lt_settings);
++ dp_set_hw_lane_settings(link, lt_settings, offset);
+
+ /* 2. update DPCD*/
+ if (!retries_ch_eq)
+ /* EPR #361076 - write as a 5-byte burst,
+- * but only for the 1-st iteration*/
++ * but only for the 1-st iteration
++ */
++
+ dpcd_set_lt_pattern_and_lane_settings(
+ link,
+ lt_settings,
+- tr_pattern);
++ tr_pattern, offset);
+ else
+- dpcd_set_lane_settings(link, lt_settings);
++ dpcd_set_lane_settings(link, lt_settings, offset);
+
+ /* 3. wait for receiver to lock-on*/
+- wait_for_training_aux_rd_interval(link, lt_settings->eq_pattern_time);
++ wait_time_microsec = lt_settings->eq_pattern_time;
++
++ if (!link->is_lttpr_mode_transparent)
++ wait_time_microsec =
++ translate_training_aux_read_interval(
++ link->dpcd_caps.lttpr_caps.aux_rd_interval[offset]);
++
++ wait_for_training_aux_rd_interval(
++ link,
++ wait_time_microsec);
+
+ /* 4. Read lane status and requested
+ * drive settings as set by the sink*/
+@@ -808,7 +878,8 @@ static enum link_training_result perform_channel_equalization_sequence(
+ lt_settings,
+ dpcd_lane_status,
+ &dpcd_lane_status_updated,
+- &req_settings);
++ &req_settings,
++ offset);
+
+ /* 5. check CR done*/
+ if (!is_cr_done(lane_count, dpcd_lane_status))
+@@ -827,13 +898,16 @@ static enum link_training_result perform_channel_equalization_sequence(
+ return LINK_TRAINING_EQ_FAIL_EQ;
+
+ }
++#define TRAINING_AUX_RD_INTERVAL 100 //us
+
+ static enum link_training_result perform_clock_recovery_sequence(
+ struct dc_link *link,
+- struct link_training_settings *lt_settings)
++ struct link_training_settings *lt_settings,
++ uint32_t offset)
+ {
+ uint32_t retries_cr;
+ uint32_t retry_count;
++ uint32_t wait_time_microsec;
+ struct link_training_settings req_settings;
+ enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
+ enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
+@@ -843,7 +917,7 @@ static enum link_training_result perform_clock_recovery_sequence(
+ retries_cr = 0;
+ retry_count = 0;
+
+- dp_set_hw_training_pattern(link, tr_pattern);
++ dp_set_hw_training_pattern(link, tr_pattern, offset);
+
+ /* najeeb - The synaptics MST hub can put the LT in
+ * infinite loop by switching the VS
+@@ -860,7 +934,8 @@ static enum link_training_result perform_clock_recovery_sequence(
+ /* 1. call HWSS to set lane settings*/
+ dp_set_hw_lane_settings(
+ link,
+- lt_settings);
++ lt_settings,
++ offset);
+
+ /* 2. update DPCD of the receiver*/
+ if (!retries_cr)
+@@ -869,16 +944,23 @@ static enum link_training_result perform_clock_recovery_sequence(
+ dpcd_set_lt_pattern_and_lane_settings(
+ link,
+ lt_settings,
+- tr_pattern);
++ tr_pattern,
++ offset);
+ else
+ dpcd_set_lane_settings(
+ link,
+- lt_settings);
++ lt_settings,
++ offset);
+
+ /* 3. wait receiver to lock-on*/
++ wait_time_microsec = lt_settings->cr_pattern_time;
++
++ if (!link->is_lttpr_mode_transparent)
++ wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
++
+ wait_for_training_aux_rd_interval(
+ link,
+- lt_settings->cr_pattern_time);
++ wait_time_microsec);
+
+ /* 4. Read lane status and requested drive
+ * settings as set by the sink
+@@ -888,7 +970,8 @@ static enum link_training_result perform_clock_recovery_sequence(
+ lt_settings,
+ dpcd_lane_status,
+ &dpcd_lane_status_updated,
+- &req_settings);
++ &req_settings,
++ offset);
+
+ /* 5. check CR done*/
+ if (is_cr_done(lane_count, dpcd_lane_status))
+@@ -1057,10 +1140,38 @@ static void initialize_training_settings(
+ lt_settings->enhanced_framing = 1;
+ }
+
++static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
++{
++ switch (lttpr_repeater_count) {
++ case 0x80: // 1 lttpr repeater
++ return 1;
++ case 0x40: // 2 lttpr repeaters
++ return 2;
++ case 0x20: // 3 lttpr repeaters
++ return 3;
++ case 0x10: // 4 lttpr repeaters
++ return 4;
++ case 0x08: // 5 lttpr repeaters
++ return 5;
++ case 0x04: // 6 lttpr repeaters
++ return 6;
++ case 0x02: // 7 lttpr repeaters
++ return 7;
++ case 0x01: // 8 lttpr repeaters
++ return 8;
++ default:
++ break;
++ }
++ return 0; // invalid value
++}
++
+ static void configure_lttpr_mode(struct dc_link *link)
+ {
+ /* aux timeout is already set to extended */
+ /* RESET/SET lttpr mode to enable non transparent mode */
++ uint8_t repeater_cnt;
++ uint32_t aux_interval_address;
++ uint8_t repeater_id;
+ enum lttpr_mode repeater_mode = phy_repeater_mode_transparent;
+
+ core_link_write_dpcd(link,
+@@ -1074,9 +1185,43 @@ static void configure_lttpr_mode(struct dc_link *link)
+ DP_PHY_REPEATER_MODE,
+ (uint8_t *)&repeater_mode,
+ sizeof(repeater_mode));
++
++ repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
++ for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
++ aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
++ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
++ core_link_read_dpcd(
++ link,
++ aux_interval_address,
++ (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
++ sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
++ link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
++ }
+ }
+ }
+
++static void repeater_training_done(struct dc_link *link, uint32_t offset)
++{
++ union dpcd_training_pattern dpcd_pattern = { {0} };
++
++ const uint32_t dpcd_base_lt_offset =
++ DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
++ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
++ /* Set training not in progress*/
++ dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
++
++ core_link_write_dpcd(
++ link,
++ dpcd_base_lt_offset,
++ &dpcd_pattern.raw,
++ 1);
++
++ DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
++ __func__,
++ dpcd_base_lt_offset,
++ dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
++}
++
+ static void print_status_message(
+ struct dc_link *link,
+ const struct link_training_settings *lt_settings,
+@@ -1156,6 +1301,17 @@ static void print_status_message(
+ lt_spread);
+ }
+
++void dc_link_dp_set_drive_settings(
++ struct dc_link *link,
++ struct link_training_settings *lt_settings)
++{
++ /* program ASIC PHY settings*/
++ dp_set_hw_lane_settings(link, lt_settings, DPRX);
++
++ /* Notify DP sink the PHY settings from source */
++ dpcd_set_lane_settings(link, lt_settings, DPRX);
++}
++
+ bool dc_link_dp_perform_link_training_skip_aux(
+ struct dc_link *link,
+ const struct dc_link_settings *link_setting)
+@@ -1172,10 +1328,10 @@ bool dc_link_dp_perform_link_training_skip_aux(
+ /* 1. Perform_clock_recovery_sequence. */
+
+ /* transmit training pattern for clock recovery */
+- dp_set_hw_training_pattern(link, pattern_for_cr);
++ dp_set_hw_training_pattern(link, pattern_for_cr, DPRX);
+
+ /* call HWSS to set lane settings*/
+- dp_set_hw_lane_settings(link, &lt_settings);
++ dp_set_hw_lane_settings(link, &lt_settings, DPRX);
+
+ /* wait receiver to lock-on*/
+ wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
+@@ -1183,10 +1339,10 @@ bool dc_link_dp_perform_link_training_skip_aux(
+ /* 2. Perform_channel_equalization_sequence. */
+
+ /* transmit training pattern for channel equalization. */
+- dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq);
++ dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
+
+ /* call HWSS to set lane settings*/
+- dp_set_hw_lane_settings(link, &lt_settings);
++ dp_set_hw_lane_settings(link, &lt_settings, DPRX);
+
+ /* wait receiver to lock-on. */
+ wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
+@@ -1208,9 +1364,12 @@ enum link_training_result dc_link_dp_perform_link_training(
+ {
+ enum link_training_result status = LINK_TRAINING_SUCCESS;
+ struct link_training_settings lt_settings;
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool fec_enable;
+ #endif
++ uint8_t repeater_cnt;
++ uint8_t repeater_id;
+
+ initialize_training_settings(
+ link,
+@@ -1230,17 +1389,40 @@ enum link_training_result dc_link_dp_perform_link_training(
+ dp_set_fec_ready(link, fec_enable);
+ #endif
+
+- /* Configure lttpr mode */
+- if (!link->is_lttpr_mode_transparent)
++ if (!link->is_lttpr_mode_transparent) {
++ /* Configure lttpr mode */
+ configure_lttpr_mode(link);
+
+- /* 2. perform link training (set link training done
+- * to false is done as well)
+- */
+- status = perform_clock_recovery_sequence(link, &lt_settings);
++ /* 2. perform link training (set link training done
++ * to false is done as well)
++ */
++ repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
++
++ for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
++ repeater_id--) {
++ status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
++
++ if (status != LINK_TRAINING_SUCCESS)
++ break;
++
++ status = perform_channel_equalization_sequence(link,
++ &lt_settings,
++ repeater_id);
++
++ if (status != LINK_TRAINING_SUCCESS)
++ break;
++
++ repeater_training_done(link, repeater_id);
++ }
++ }
++
++ if (status == LINK_TRAINING_SUCCESS) {
++ status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
+ if (status == LINK_TRAINING_SUCCESS) {
+ status = perform_channel_equalization_sequence(link,
+- &lt_settings);
++ &lt_settings,
++ DPRX);
++ }
+ }
+
+ if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
+@@ -1393,10 +1575,11 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
+ /* 2. perform link training (set link training done
+ * to false is done as well)
+ */
+- lt_status = perform_clock_recovery_sequence(link, &lt_settings);
++ lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
+ if (lt_status == LINK_TRAINING_SUCCESS) {
+ lt_status = perform_channel_equalization_sequence(link,
+- &lt_settings);
++ &lt_settings,
++ DPRX);
+ }
+
+ /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
+@@ -3355,8 +3538,8 @@ bool dc_link_dp_set_test_pattern(
+ if (is_dp_phy_pattern(test_pattern)) {
+ /* Set DPCD Lane Settings before running test pattern */
+ if (p_link_settings != NULL) {
+- dp_set_hw_lane_settings(link, p_link_settings);
+- dpcd_set_lane_settings(link, p_link_settings);
++ dp_set_hw_lane_settings(link, p_link_settings, DPRX);
++ dpcd_set_lane_settings(link, p_link_settings, DPRX);
+ }
+
+ /* Blank stream if running test pattern */
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index a519dbc5ecb6..5efbdc1eb173 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -19,6 +19,36 @@
+ #include "resource.h"
+ #endif
+
++static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
++{
++ switch (lttpr_repeater_count) {
++ case 0x80: // 1 lttpr repeater
++ return 1;
++ case 0x40: // 2 lttpr repeaters
++ return 2;
++ case 0x20: // 3 lttpr repeaters
++ return 3;
++ case 0x10: // 4 lttpr repeaters
++ return 4;
++ case 0x08: // 5 lttpr repeaters
++ return 5;
++ case 0x04: // 6 lttpr repeaters
++ return 6;
++ case 0x02: // 7 lttpr repeaters
++ return 7;
++ case 0x01: // 8 lttpr repeaters
++ return 8;
++ default:
++ break;
++ }
++ return 0; // invalid value
++}
++
++static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)
++{
++ return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);
++}
++
+ enum dc_status core_link_read_dpcd(
+ struct dc_link *link,
+ uint32_t address,
+@@ -212,7 +242,8 @@ void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
+
+ bool dp_set_hw_training_pattern(
+ struct dc_link *link,
+- enum dc_dp_training_pattern pattern)
++ enum dc_dp_training_pattern pattern,
++ uint32_t offset)
+ {
+ enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
+
+@@ -240,10 +271,14 @@ bool dp_set_hw_training_pattern(
+
+ void dp_set_hw_lane_settings(
+ struct dc_link *link,
+- const struct link_training_settings *link_settings)
++ const struct link_training_settings *link_settings,
++ uint32_t offset)
+ {
+ struct link_encoder *encoder = link->link_enc;
+
++ if (!link->is_lttpr_mode_transparent && !is_immediate_downstream(link, offset))
++ return;
++
+ /* call Encoder to set lane settings */
+ encoder->funcs->dp_set_lane_settings(encoder, link_settings);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+index 4eff5d38a2f9..9af7ee5bc8ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+@@ -60,11 +60,13 @@ void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
+
+ bool dp_set_hw_training_pattern(
+ struct dc_link *link,
+- enum dc_dp_training_pattern pattern);
++ enum dc_dp_training_pattern pattern,
++ uint32_t offset);
+
+ void dp_set_hw_lane_settings(
+ struct dc_link *link,
+- const struct link_training_settings *link_settings);
++ const struct link_training_settings *link_settings,
++ uint32_t offset);
+
+ void dp_set_hw_test_pattern(
+ struct dc_link *link,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4399-drm-amd-display-use-previous-aux-timeout-val-if-no-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4399-drm-amd-display-use-previous-aux-timeout-val-if-no-r.patch
new file mode 100644
index 00000000..52fe368b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4399-drm-amd-display-use-previous-aux-timeout-val-if-no-r.patch
@@ -0,0 +1,221 @@
+From 562af0eb8901f71ee602299a46b13ae29c18a860 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Thu, 19 Sep 2019 15:51:00 -0400
+Subject: [PATCH 4399/4736] drm/amd/display: use previous aux timeout val if no
+ repeater.
+
+[Why]
+The aux timeout value is not default before reading link cap.
+Setting it to default when lttpr is not enabled causes some monitor
+not to light up.
+
+[How]
+Read the aux engine timeout value before setting it to extended.
+Set the aux engine timeout to its previous value if no lttpr.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 13 +++---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++--
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 46 +++++++++++++++----
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 2 +-
+ .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 2 +-
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +-
+ 6 files changed, 52 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 747cd0fbe571..68c0cf85deb7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -648,17 +648,16 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ }
+
+
+-enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
+ uint32_t timeout)
+ {
+- enum dc_status status = DC_OK;
++ uint32_t prev_timeout = 0;
+ struct ddc *ddc_pin = ddc->ddc_pin;
+
+- if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout == NULL)
+- return DC_ERROR_UNEXPECTED;
+- if (!ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout))
+- status = DC_ERROR_UNEXPECTED;
+- return status;
++ if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
++ prev_timeout =
++ ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
++ return prev_timeout;
+ }
+
+ /*test only function*/
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 11b6e14b345e..6e1f00ab6646 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2977,6 +2977,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ union dp_downstream_port_present ds_port = { 0 };
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+ uint32_t read_dpcd_retry_cnt = 3;
++ uint32_t prev_timeout_val;
+ int i;
+ struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+
+@@ -2987,7 +2988,9 @@ static bool retrieve_link_cap(struct dc_link *link)
+ link->is_lttpr_mode_transparent = true;
+
+ if (ext_timeout_support) {
+- status = dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
++ prev_timeout_val =
++ dc_link_aux_configure_timeout(link->ddc,
++ LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
+ }
+
+ memset(dpcd_data, '\0', sizeof(dpcd_data));
+@@ -3022,7 +3025,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ return false;
+ }
+
+- if (ext_timeout_support && link->dpcd_caps.dpcd_rev.raw >= 0x14) {
++ if (ext_timeout_support) {
+ status = core_link_read_dpcd(
+ link,
+ DP_PHY_REPEATER_CNT,
+@@ -3063,7 +3066,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ &link->dpcd_caps.lttpr_caps.max_ext_timeout,
+ sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
+ } else {
+- dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
++ dc_link_aux_configure_timeout(link->ddc, prev_timeout_val);
+ }
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index ca1d076d4184..0b9d8c5b9323 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -57,12 +57,14 @@ enum {
+ AUX_DEFER_RETRY_COUNTER = 6
+ };
+
+-#define TIME_OUT_INCREMENT 1016
+-#define TIME_OUT_MULTIPLIER_8 8
+-#define TIME_OUT_MULTIPLIER_16 16
+-#define TIME_OUT_MULTIPLIER_32 32
+-#define TIME_OUT_MULTIPLIER_64 64
+-#define MAX_TIMEOUT_LENGTH 127
++#define TIME_OUT_INCREMENT 1016
++#define TIME_OUT_MULTIPLIER_8 8
++#define TIME_OUT_MULTIPLIER_16 16
++#define TIME_OUT_MULTIPLIER_32 32
++#define TIME_OUT_MULTIPLIER_64 64
++#define MAX_TIMEOUT_LENGTH 127
++#define DEFAULT_AUX_ENGINE_MULT 0
++#define DEFAULT_AUX_ENGINE_LENGTH 69
+
+ static void release_engine(
+ struct dce_aux *engine)
+@@ -424,11 +426,14 @@ void dce110_engine_destroy(struct dce_aux **engine)
+
+ }
+
+-static bool dce_aux_configure_timeout(struct ddc_service *ddc,
++static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,
+ uint32_t timeout_in_us)
+ {
+ uint32_t multiplier = 0;
+ uint32_t length = 0;
++ uint32_t prev_length = 0;
++ uint32_t prev_mult = 0;
++ uint32_t prev_timeout_val = 0;
+ struct ddc *ddc_pin = ddc->ddc_pin;
+ struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+ struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+@@ -437,7 +442,10 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+ aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER;
+
+ /* 2-Update aux timeout period length and multiplier */
+- if (timeout_in_us <= TIME_OUT_INCREMENT) {
++ if (timeout_in_us == 0) {
++ multiplier = DEFAULT_AUX_ENGINE_MULT;
++ length = DEFAULT_AUX_ENGINE_LENGTH;
++ } else if (timeout_in_us <= TIME_OUT_INCREMENT) {
+ multiplier = 0;
+ length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
+ if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
+@@ -461,9 +469,29 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+
+ length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
+
++ REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
++
++ switch (prev_mult) {
++ case 0:
++ prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_8;
++ break;
++ case 1:
++ prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_16;
++ break;
++ case 2:
++ prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_32;
++ break;
++ case 3:
++ prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_64;
++ break;
++ default:
++ prev_timeout_val = DEFAULT_AUX_ENGINE_LENGTH * TIME_OUT_MULTIPLIER_8;
++ break;
++ }
++
+ REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier);
+
+- return true;
++ return prev_timeout_val;
+ }
+
+ static struct dce_aux_funcs aux_functions = {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index b4b2c79a8073..2e2e925a506b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -311,7 +311,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ struct aux_payload *cmd);
+
+ struct dce_aux_funcs {
+- bool (*configure_timeout)
++ uint32_t (*configure_timeout)
+ (struct ddc_service *ddc,
+ uint32_t timeout);
+ void (*destroy)
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+index 14716ba35662..de2d160114db 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+@@ -105,7 +105,7 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
+ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ struct aux_payload *payload);
+
+-enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
+ uint32_t timeout);
+
+ void dal_ddc_service_write_scdc_data(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 045138dbdccb..a6500b98fe0d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -28,7 +28,7 @@
+
+ #define LINK_TRAINING_ATTEMPTS 4
+ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
+-#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 32000 /*us*/
++#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 3200 /*us*/
+ #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
+
+ struct dc_link;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4400-drm-amd-display-disable-lttpr-for-invalid-lttpr-caps.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4400-drm-amd-display-disable-lttpr-for-invalid-lttpr-caps.patch
new file mode 100644
index 00000000..5765daa6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4400-drm-amd-display-disable-lttpr-for-invalid-lttpr-caps.patch
@@ -0,0 +1,222 @@
+From 1e75247d954914c51e84fac13a6b3cfe31670c24 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Thu, 10 Oct 2019 16:41:52 -0400
+Subject: [PATCH 4400/4736] drm/amd/display: disable lttpr for invalid lttpr
+ caps.
+
+1-Read lttpr caps in 5-bytes
+2-Parse caps
+3-Validate caps and set lttpr_mode
+4-Use hw default timeout when lttpr is disabled.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 90 ++++++++++---------
+ drivers/gpu/drm/amd/display/dc/dc_types.h | 15 +---
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +-
+ include/drm/drm_dp_helper.h | 4 +
+ 4 files changed, 53 insertions(+), 58 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 6e1f00ab6646..7d18fc1e68c6 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1172,7 +1172,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+ uint8_t repeater_cnt;
+ uint32_t aux_interval_address;
+ uint8_t repeater_id;
+- enum lttpr_mode repeater_mode = phy_repeater_mode_transparent;
++ uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
+
+ core_link_write_dpcd(link,
+ DP_PHY_REPEATER_MODE,
+@@ -1180,7 +1180,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+ sizeof(repeater_mode));
+
+ if (!link->is_lttpr_mode_transparent) {
+- repeater_mode = phy_repeater_mode_non_transparent;
++ repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
+ core_link_write_dpcd(link,
+ DP_PHY_REPEATER_MODE,
+ (uint8_t *)&repeater_mode,
+@@ -2964,7 +2964,11 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+
+ static bool retrieve_link_cap(struct dc_link *link)
+ {
+- uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
++ /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
++ * which means size 16 will be good for both of those DPCD register block reads
++ */
++ uint8_t dpcd_data[16];
++ uint8_t lttpr_dpcd_data[6];
+
+ /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
+ */
+@@ -2977,7 +2981,6 @@ static bool retrieve_link_cap(struct dc_link *link)
+ union dp_downstream_port_present ds_port = { 0 };
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+ uint32_t read_dpcd_retry_cnt = 3;
+- uint32_t prev_timeout_val;
+ int i;
+ struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+
+@@ -2988,12 +2991,12 @@ static bool retrieve_link_cap(struct dc_link *link)
+ link->is_lttpr_mode_transparent = true;
+
+ if (ext_timeout_support) {
+- prev_timeout_val =
+- dc_link_aux_configure_timeout(link->ddc,
+- LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
++ dc_link_aux_configure_timeout(link->ddc,
++ LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
+ }
+
+ memset(dpcd_data, '\0', sizeof(dpcd_data));
++ memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
+ memset(&down_strm_port_count,
+ '\0', sizeof(union down_stream_port_count));
+ memset(&edp_config_cap, '\0',
+@@ -3026,47 +3029,46 @@ static bool retrieve_link_cap(struct dc_link *link)
+ }
+
+ if (ext_timeout_support) {
++
+ status = core_link_read_dpcd(
+ link,
+- DP_PHY_REPEATER_CNT,
+- &link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
+- sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
+-
+- if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0) {
+-
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
++ lttpr_dpcd_data,
++ sizeof(lttpr_dpcd_data));
++
++ link->dpcd_caps.lttpr_caps.revision.raw =
++ lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++ link->dpcd_caps.lttpr_caps.max_link_rate =
++ lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++ link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
++ lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++ link->dpcd_caps.lttpr_caps.max_lane_count =
++ lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++ link->dpcd_caps.lttpr_caps.mode =
++ lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++ link->dpcd_caps.lttpr_caps.max_ext_timeout =
++ lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
++ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++ if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
++ link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
++ link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
++ link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) {
+ link->is_lttpr_mode_transparent = false;
+-
+- status = core_link_read_dpcd(
+- link,
+- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+- (uint8_t *)&link->dpcd_caps.lttpr_caps.revision,
+- sizeof(link->dpcd_caps.lttpr_caps.revision));
+-
+- status = core_link_read_dpcd(
+- link,
+- DP_MAX_LINK_RATE_PHY_REPEATER,
+- &link->dpcd_caps.lttpr_caps.max_link_rate,
+- sizeof(link->dpcd_caps.lttpr_caps.max_link_rate));
+-
+- status = core_link_read_dpcd(
+- link,
+- DP_PHY_REPEATER_MODE,
+- (uint8_t *)&link->dpcd_caps.lttpr_caps.mode,
+- sizeof(link->dpcd_caps.lttpr_caps.mode));
+-
+- status = core_link_read_dpcd(
+- link,
+- DP_MAX_LANE_COUNT_PHY_REPEATER,
+- &link->dpcd_caps.lttpr_caps.max_lane_count,
+- sizeof(link->dpcd_caps.lttpr_caps.max_lane_count));
+-
+- status = core_link_read_dpcd(
+- link,
+- DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
+- &link->dpcd_caps.lttpr_caps.max_ext_timeout,
+- sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
+ } else {
+- dc_link_aux_configure_timeout(link->ddc, prev_timeout_val);
++ /*No lttpr reset timeout to its default value*/
++ link->is_lttpr_mode_transparent = true;
++ dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
+ }
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 837859e65e45..45dfed8bcaf7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -420,20 +420,9 @@ enum link_training_offset {
+ LTTPR_PHY_REPEATER8 = 8
+ };
+
+-enum lttpr_mode {
+- phy_repeater_mode_transparent = 0x55,
+- phy_repeater_mode_non_transparent = 0xAA
+-};
+-
+-enum lttpr_rev {
+- lttpr_rev_unknown = 0x0,
+- lttpr_rev_14 = 0x14,
+- lttpr_rev_max = 0x20
+-};
+-
+ struct dc_lttpr_caps {
+- enum lttpr_rev revision;
+- enum lttpr_mode mode;
++ union dpcd_rev revision;
++ uint8_t mode;
+ uint8_t max_lane_count;
+ uint8_t max_link_rate;
+ uint8_t phy_repeater_cnt;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index a6500b98fe0d..1e6ff6eb5bfc 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -29,7 +29,7 @@
+ #define LINK_TRAINING_ATTEMPTS 4
+ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
+ #define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 3200 /*us*/
+-#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
++#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
+
+ struct dc_link;
+ struct dc_stream_state;
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index b2a2c92ac67c..4f9184a238dd 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -967,6 +967,10 @@
+ #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
+ #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
+
++/* Repeater modes */
++#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
++#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
++
+ /* DP HDCP message start offsets in DPCD address space */
+ #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
+ #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4401-drm-amd-powerplay-correct-Arcturus-OD-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4401-drm-amd-powerplay-correct-Arcturus-OD-support.patch
new file mode 100644
index 00000000..ab0bc3fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4401-drm-amd-powerplay-correct-Arcturus-OD-support.patch
@@ -0,0 +1,52 @@
+From 8a8679854d41641f7aec1706e1c2770445a65b86 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 7 Nov 2019 15:33:50 +0800
+Subject: [PATCH 4401/4736] drm/amd/powerplay: correct Arcturus OD support
+
+OD is not supported on Arcturus. Thus the
+pp_od_clk_voltage sysfs interface is also not supported.
+
+Change-Id: Ib70632a55a0980cf04c3432d43dbcf869cd1b4bf
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index c21fe7ac5df8..76a4154b3be2 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -714,6 +714,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ {
+ struct smu_context *smu = &adev->smu;
+
++ if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
++ smu->od_enabled = true;
++
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ vega20_set_ppt_funcs(smu);
+@@ -725,6 +728,8 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ break;
+ case CHIP_ARCTURUS:
+ arcturus_set_ppt_funcs(smu);
++ /* OD is not supported on Arcturus */
++ smu->od_enabled =false;
+ break;
+ case CHIP_RENOIR:
+ renoir_set_ppt_funcs(smu);
+@@ -733,9 +738,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ return -EINVAL;
+ }
+
+- if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+- smu->od_enabled = true;
+-
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4402-drm-amdkfd-Use-kernel-queue-v9-functions-for-v10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4402-drm-amdkfd-Use-kernel-queue-v9-functions-for-v10.patch
new file mode 100644
index 00000000..5450fb3c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4402-drm-amdkfd-Use-kernel-queue-v9-functions-for-v10.patch
@@ -0,0 +1,508 @@
+From 96cdd7e6717e0d16d6f0c546976e2149f0dbfd15 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 30 Oct 2019 19:22:11 -0400
+Subject: [PATCH 4402/4736] drm/amdkfd: Use kernel queue v9 functions for v10
+
+The kernel queue functions for v9 and v10 are the same except
+pm_map_process_v* which have small difference, so they should be reused.
+This eliminates the need of reapplying several patches which were
+applied on v9 but not on v10, such as bigger GWS and more than 2
+SDMA engine support which were introduced on Arcturus.
+
+Change-Id: I2d385961e3c884db14e30b5afc98d0d9e4cb1802
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 4 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 1 -
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c | 359 ------------------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 16 +-
+ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 -
+ 7 files changed, 14 insertions(+), 374 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index aa951107a895..c2c125156a62 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -41,7 +41,6 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \
+ $(AMDKFD_PATH)/kfd_kernel_queue_cik.o \
+ $(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
+ $(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
+- $(AMDKFD_PATH)/kfd_kernel_queue_v10.o \
+ $(AMDKFD_PATH)/kfd_packet_manager.o \
+ $(AMDKFD_PATH)/kfd_process_queue_manager.o \
+ $(AMDKFD_PATH)/kfd_device_queue_manager.o \
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index 5e2d75ca2b62..04041bab42a8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -367,12 +367,10 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ case CHIP_RAVEN:
+ case CHIP_RENOIR:
+ case CHIP_ARCTURUS:
+- kernel_queue_init_v9(&kq->ops_asic_specific);
+- break;
+ case CHIP_NAVI10:
+ case CHIP_NAVI12:
+ case CHIP_NAVI14:
+- kernel_queue_init_v10(&kq->ops_asic_specific);
++ kernel_queue_init_v9(&kq->ops_asic_specific);
+ break;
+ default:
+ WARN(1, "Unexpected ASIC family %u",
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index a23927d809c7..384d7a37b343 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -112,6 +112,5 @@ struct kernel_queue {
+ void kernel_queue_init_cik(struct kernel_queue_ops *ops);
+ void kernel_queue_init_vi(struct kernel_queue_ops *ops);
+ void kernel_queue_init_v9(struct kernel_queue_ops *ops);
+-void kernel_queue_init_v10(struct kernel_queue_ops *ops);
+
+ #endif /* KFD_KERNEL_QUEUE_H_ */
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+deleted file mode 100644
+index 5ee593ba3137..000000000000
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
++++ /dev/null
+@@ -1,359 +0,0 @@
+-/*
+- * Copyright 2018 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- */
+-
+-#include "kfd_kernel_queue.h"
+-#include "kfd_device_queue_manager.h"
+-#include "kfd_pm4_headers_ai.h"
+-#include "kfd_pm4_opcodes.h"
+-#include "gc/gc_10_1_0_sh_mask.h"
+-
+-static bool initialize_v10(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_v10(struct kernel_queue *kq);
+-static void submit_packet_v10(struct kernel_queue *kq);
+-
+-void kernel_queue_init_v10(struct kernel_queue_ops *ops)
+-{
+- ops->initialize = initialize_v10;
+- ops->uninitialize = uninitialize_v10;
+- ops->submit_packet = submit_packet_v10;
+-}
+-
+-static bool initialize_v10(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size)
+-{
+- int retval;
+-
+- retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+- if (retval != 0)
+- return false;
+-
+- kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
+- kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
+-
+- memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+-
+- return true;
+-}
+-
+-static void uninitialize_v10(struct kernel_queue *kq)
+-{
+- kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+-}
+-
+-static void submit_packet_v10(struct kernel_queue *kq)
+-{
+- *kq->wptr64_kernel = kq->pending_wptr64;
+- write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
+- kq->pending_wptr64);
+-}
+-
+-static int pm_map_process_v10(struct packet_manager *pm,
+- uint32_t *buffer, struct qcm_process_device *qpd)
+-{
+- struct pm4_mes_map_process *packet;
+- uint64_t vm_page_table_base_addr = qpd->page_table_base;
+- struct kfd_dev *kfd = pm->dqm->dev;
+-
+- packet = (struct pm4_mes_map_process *)buffer;
+- memset(buffer, 0, sizeof(struct pm4_mes_map_process));
+-
+- packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
+- sizeof(struct pm4_mes_map_process));
+- packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
+- packet->bitfields2.process_quantum = 1;
+- packet->bitfields2.pasid = qpd->pqm->process->pasid;
+- packet->bitfields14.gds_size = qpd->gds_size;
+- packet->bitfields14.num_gws = qpd->num_gws;
+- packet->bitfields14.num_oac = qpd->num_oac;
+- packet->bitfields14.sdma_enable = 1;
+-
+- packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
+-
+- if (kfd->dqm->trap_debug_vmid) {
+- packet->bitfields2.debug_vmid = kfd->dqm->trap_debug_vmid;
+- packet->bitfields2.new_debug = 1;
+- }
+-
+- packet->sh_mem_config = qpd->sh_mem_config;
+- packet->sh_mem_bases = qpd->sh_mem_bases;
+- if (qpd->tba_addr) {
+- packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
+- packet->sq_shader_tba_hi = (1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT) |
+- upper_32_bits(qpd->tba_addr >> 8);
+- packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
+- packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
+- }
+-
+- packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
+- packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
+-
+- packet->vm_context_page_table_base_addr_lo32 =
+- lower_32_bits(vm_page_table_base_addr);
+- packet->vm_context_page_table_base_addr_hi32 =
+- upper_32_bits(vm_page_table_base_addr);
+-
+- return 0;
+-}
+-
+-static int pm_runlist_v10(struct packet_manager *pm, uint32_t *buffer,
+- uint64_t ib, size_t ib_size_in_dwords, bool chain)
+-{
+- struct pm4_mes_runlist *packet;
+-
+- int concurrent_proc_cnt = 0;
+- struct kfd_dev *kfd = pm->dqm->dev;
+-
+- /* Determine the number of processes to map together to HW:
+- * it can not exceed the number of VMIDs available to the
+- * scheduler, and it is determined by the smaller of the number
+- * of processes in the runlist and kfd module parameter
+- * hws_max_conc_proc.
+- * Note: the arbitration between the number of VMIDs and
+- * hws_max_conc_proc has been done in
+- * kgd2kfd_device_init().
+- */
+- concurrent_proc_cnt = min(pm->dqm->processes_count,
+- kfd->max_proc_per_quantum);
+-
+-
+- packet = (struct pm4_mes_runlist *)buffer;
+-
+- memset(buffer, 0, sizeof(struct pm4_mes_runlist));
+- packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
+- sizeof(struct pm4_mes_runlist));
+-
+- packet->bitfields4.ib_size = ib_size_in_dwords;
+- packet->bitfields4.chain = chain ? 1 : 0;
+- packet->bitfields4.offload_polling = 0;
+- packet->bitfields4.valid = 1;
+- packet->bitfields4.process_cnt = concurrent_proc_cnt;
+- packet->ordinal2 = lower_32_bits(ib);
+- packet->ib_base_hi = upper_32_bits(ib);
+-
+- return 0;
+-}
+-
+-static int pm_map_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+- struct queue *q, bool is_static)
+-{
+- struct pm4_mes_map_queues *packet;
+- bool use_static = is_static;
+-
+- packet = (struct pm4_mes_map_queues *)buffer;
+- memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
+-
+- packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
+- sizeof(struct pm4_mes_map_queues));
+- packet->bitfields2.num_queues = 1;
+- packet->bitfields2.queue_sel =
+- queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
+-
+- packet->bitfields2.engine_sel =
+- engine_sel__mes_map_queues__compute_vi;
+- packet->bitfields2.queue_type =
+- queue_type__mes_map_queues__normal_compute_vi;
+-
+- switch (q->properties.type) {
+- case KFD_QUEUE_TYPE_COMPUTE:
+- if (use_static)
+- packet->bitfields2.queue_type =
+- queue_type__mes_map_queues__normal_latency_static_queue_vi;
+- break;
+- case KFD_QUEUE_TYPE_DIQ:
+- packet->bitfields2.queue_type =
+- queue_type__mes_map_queues__debug_interface_queue_vi;
+- break;
+- case KFD_QUEUE_TYPE_SDMA:
+- case KFD_QUEUE_TYPE_SDMA_XGMI:
+- packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
+- engine_sel__mes_map_queues__sdma0_vi;
+- use_static = false; /* no static queues under SDMA */
+- break;
+- default:
+- WARN(1, "queue type %d\n", q->properties.type);
+- return -EINVAL;
+- }
+- packet->bitfields3.doorbell_offset =
+- q->properties.doorbell_off;
+-
+- packet->mqd_addr_lo =
+- lower_32_bits(q->gart_mqd_addr);
+-
+- packet->mqd_addr_hi =
+- upper_32_bits(q->gart_mqd_addr);
+-
+- packet->wptr_addr_lo =
+- lower_32_bits((uint64_t)q->properties.write_ptr);
+-
+- packet->wptr_addr_hi =
+- upper_32_bits((uint64_t)q->properties.write_ptr);
+-
+- return 0;
+-}
+-
+-static int pm_set_grace_period_v10(struct packet_manager *pm,
+- uint32_t *buffer,
+- uint32_t grace_period)
+-{
+- struct pm4_mec_write_data_mmio *packet;
+- uint32_t reg_offset = 0;
+- uint32_t reg_data = 0;
+-
+- pm->dqm->dev->kfd2kgd->build_grace_period_packet_info(
+- pm->dqm->dev->kgd,
+- pm->dqm->wait_times,
+- grace_period,
+- &reg_offset,
+- &reg_data);
+-
+- if (grace_period == USE_DEFAULT_GRACE_PERIOD)
+- reg_data = pm->dqm->wait_times;
+-
+- packet = (struct pm4_mec_write_data_mmio *)buffer;
+- memset(buffer, 0, sizeof(struct pm4_mec_write_data_mmio));
+-
+- packet->header.u32All = pm_build_pm4_header(IT_WRITE_DATA,
+- sizeof(struct pm4_mec_write_data_mmio));
+-
+- packet->bitfields2.dst_sel = dst_sel___write_data__mem_mapped_register;
+- packet->bitfields2.addr_incr =
+- addr_incr___write_data__do_not_increment_address;
+-
+- packet->bitfields3.dst_mmreg_addr = reg_offset;
+-
+- packet->data = reg_data;
+-
+- return 0;
+-}
+-static int pm_unmap_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+- enum kfd_queue_type type,
+- enum kfd_unmap_queues_filter filter,
+- uint32_t filter_param, bool reset,
+- unsigned int sdma_engine)
+-{
+- struct pm4_mes_unmap_queues *packet;
+-
+- packet = (struct pm4_mes_unmap_queues *)buffer;
+- memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
+-
+- packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
+- sizeof(struct pm4_mes_unmap_queues));
+- switch (type) {
+- case KFD_QUEUE_TYPE_COMPUTE:
+- case KFD_QUEUE_TYPE_DIQ:
+- packet->bitfields2.engine_sel =
+- engine_sel__mes_unmap_queues__compute;
+- break;
+- case KFD_QUEUE_TYPE_SDMA:
+- case KFD_QUEUE_TYPE_SDMA_XGMI:
+- packet->bitfields2.engine_sel =
+- engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
+- break;
+- default:
+- WARN(1, "queue type %d\n", type);
+- break;
+- }
+-
+- if (reset)
+- packet->bitfields2.action =
+- action__mes_unmap_queues__reset_queues;
+- else
+- packet->bitfields2.action =
+- action__mes_unmap_queues__preempt_queues;
+-
+- switch (filter) {
+- case KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE:
+- packet->bitfields2.queue_sel =
+- queue_sel__mes_unmap_queues__perform_request_on_specified_queues;
+- packet->bitfields2.num_queues = 1;
+- packet->bitfields3b.doorbell_offset0 = filter_param;
+- break;
+- case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
+- packet->bitfields2.queue_sel =
+- queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
+- packet->bitfields3a.pasid = filter_param;
+- break;
+- case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
+- packet->bitfields2.queue_sel =
+- queue_sel__mes_unmap_queues__unmap_all_queues;
+- break;
+- case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
+- /* in this case, we do not preempt static queues */
+- packet->bitfields2.queue_sel =
+- queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
+- break;
+- default:
+- WARN(1, "filter %d\n", filter);
+- break;
+- }
+-
+- return 0;
+-
+-}
+-
+-static int pm_query_status_v10(struct packet_manager *pm, uint32_t *buffer,
+- uint64_t fence_address, uint32_t fence_value)
+-{
+- struct pm4_mes_query_status *packet;
+-
+- packet = (struct pm4_mes_query_status *)buffer;
+- memset(buffer, 0, sizeof(struct pm4_mes_query_status));
+-
+-
+- packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
+- sizeof(struct pm4_mes_query_status));
+-
+- packet->bitfields2.context_id = 0;
+- packet->bitfields2.interrupt_sel =
+- interrupt_sel__mes_query_status__completion_status;
+- packet->bitfields2.command =
+- command__mes_query_status__fence_only_after_write_ack;
+-
+- packet->addr_hi = upper_32_bits((uint64_t)fence_address);
+- packet->addr_lo = lower_32_bits((uint64_t)fence_address);
+- packet->data_hi = upper_32_bits((uint64_t)fence_value);
+- packet->data_lo = lower_32_bits((uint64_t)fence_value);
+-
+- return 0;
+-}
+-
+-const struct packet_manager_funcs kfd_v10_pm_funcs = {
+- .map_process = pm_map_process_v10,
+- .runlist = pm_runlist_v10,
+- .set_resources = pm_set_resources_vi,
+- .map_queues = pm_map_queues_v10,
+- .unmap_queues = pm_unmap_queues_v10,
+- .set_grace_period = pm_set_grace_period_v10,
+- .query_status = pm_query_status_v10,
+- .release_mem = NULL,
+- .map_process_size = sizeof(struct pm4_mes_map_process),
+- .runlist_size = sizeof(struct pm4_mes_runlist),
+- .set_resources_size = sizeof(struct pm4_mes_set_resources),
+- .map_queues_size = sizeof(struct pm4_mes_map_queues),
+- .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
+- .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio),
+- .query_status_size = sizeof(struct pm4_mes_query_status),
+- .release_mem_size = 0,
+-};
+-
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index 42aefc976838..a3d0b4cf16c6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -25,6 +25,7 @@
+ #include "kfd_device_queue_manager.h"
+ #include "kfd_pm4_headers_ai.h"
+ #include "kfd_pm4_opcodes.h"
++#include "gc/gc_10_1_0_sh_mask.h"
+
+ static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+ enum kfd_queue_type type, unsigned int queue_size)
+@@ -91,10 +92,17 @@ static int pm_map_process_v9(struct packet_manager *pm,
+
+ packet->sh_mem_config = qpd->sh_mem_config;
+ packet->sh_mem_bases = qpd->sh_mem_bases;
+- packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
+- packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8);
+- packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
+- packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
++ if (qpd->tba_addr) {
++ packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
++ /* On GFX9, unlike GFX10, bit TRAP_EN of SQ_SHADER_TBA_HI is
++ * not defined, so setting it won't do any harm.
++ */
++ packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)
++ | 1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT;
++
++ packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
++ packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
++ }
+
+ packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
+ packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index 13bd55a92fd6..cbf83ed96dad 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -243,12 +243,10 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
+ case CHIP_RAVEN:
+ case CHIP_RENOIR:
+ case CHIP_ARCTURUS:
+- pm->pmf = &kfd_v9_pm_funcs;
+- break;
+ case CHIP_NAVI10:
+ case CHIP_NAVI12:
+ case CHIP_NAVI14:
+- pm->pmf = &kfd_v10_pm_funcs;
++ pm->pmf = &kfd_v9_pm_funcs;
+ break;
+ default:
+ WARN(1, "Unexpected ASIC family %u",
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index e7913212c1f6..829c7506539d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -1125,7 +1125,6 @@ struct packet_manager_funcs {
+
+ extern const struct packet_manager_funcs kfd_vi_pm_funcs;
+ extern const struct packet_manager_funcs kfd_v9_pm_funcs;
+-extern const struct packet_manager_funcs kfd_v10_pm_funcs;
+
+ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
+ void pm_uninit(struct packet_manager *pm);
+@@ -1146,8 +1145,6 @@ int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period);
+
+ /* Following PM funcs can be shared among VI and AI */
+ unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);
+-int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer,
+- struct scheduling_resources *res);
+ void kfd_pm_func_init_v10(struct packet_manager *pm, uint16_t fw_ver);
+
+ uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4403-drm-amdkfd-Simplify-the-mmap-offset-related-bit-oper.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4403-drm-amdkfd-Simplify-the-mmap-offset-related-bit-oper.patch
new file mode 100644
index 00000000..e778fb85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4403-drm-amdkfd-Simplify-the-mmap-offset-related-bit-oper.patch
@@ -0,0 +1,130 @@
+From b5e2e678c6ca3126e8f9fdf7b1d2a1ceb58438d5 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 18:11:32 -0500
+Subject: [PATCH 4403/4736] drm/amdkfd: Simplify the mmap offset related bit
+ operations
+
+The new code uses straightforward bit shifts and thus has better readability.
+
+Change-Id: I0c1f7cca7e24ddb7b4ffe1cb0fa71943828ae373
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 17 +++++++----------
+ drivers/gpu/drm/amd/amdkfd/kfd_events.c | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 +++------
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 3 +--
+ 4 files changed, 11 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 22f7aa576c7e..59bfbed3c000 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -320,7 +320,6 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ /* Return gpu_id as doorbell offset for mmap usage */
+ args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
+ args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
+- args->doorbell_offset <<= PAGE_SHIFT;
+ if (KFD_IS_SOC15(dev->device_info->asic_family))
+ /* On SOC15 ASICs, doorbell allocation must be
+ * per-device, and independent from the per-process
+@@ -1348,10 +1347,9 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
+ /* MMIO is mapped through kfd device
+ * Generate a kfd mmap offset
+ */
+- if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
+- args->mmap_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(args->gpu_id);
+- args->mmap_offset <<= PAGE_SHIFT;
+- }
++ if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
++ args->mmap_offset = KFD_MMAP_TYPE_MMIO
++ | KFD_MMAP_GPU_ID(args->gpu_id);
+
+ return 0;
+
+@@ -3094,20 +3092,19 @@ static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
+ {
+ struct kfd_process *process;
+ struct kfd_dev *dev = NULL;
+- unsigned long vm_pgoff;
++ unsigned long mmap_offset;
+ unsigned int gpu_id;
+
+ process = kfd_get_process(current);
+ if (IS_ERR(process))
+ return PTR_ERR(process);
+
+- vm_pgoff = vma->vm_pgoff;
+- vma->vm_pgoff = KFD_MMAP_OFFSET_VALUE_GET(vm_pgoff);
+- gpu_id = KFD_MMAP_GPU_ID_GET(vm_pgoff);
++ mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
++ gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
+ if (gpu_id)
+ dev = kfd_device_by_id(gpu_id);
+
+- switch (vm_pgoff & KFD_MMAP_TYPE_MASK) {
++ switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
+ case KFD_MMAP_TYPE_DOORBELL:
+ if (!dev)
+ return -ENODEV;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+index 6baf78c9245f..ebab277c9814 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+@@ -346,7 +346,6 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p,
+ ret = create_signal_event(devkfd, p, ev);
+ if (!ret) {
+ *event_page_offset = KFD_MMAP_TYPE_EVENTS;
+- *event_page_offset <<= PAGE_SHIFT;
+ *event_slot_index = ev->event_id;
+ }
+ break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 829c7506539d..107b23187009 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -62,24 +62,21 @@
+ * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
+ * defines are w.r.t to PAGE_SIZE
+ */
+-#define KFD_MMAP_TYPE_SHIFT (62 - PAGE_SHIFT)
++#define KFD_MMAP_TYPE_SHIFT 62
+ #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT)
+
+-#define KFD_MMAP_GPU_ID_SHIFT (46 - PAGE_SHIFT)
++#define KFD_MMAP_GPU_ID_SHIFT 46
+ #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \
+ << KFD_MMAP_GPU_ID_SHIFT)
+ #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\
+ & KFD_MMAP_GPU_ID_MASK)
+-#define KFD_MMAP_GPU_ID_GET(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \
++#define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \
+ >> KFD_MMAP_GPU_ID_SHIFT)
+
+-#define KFD_MMAP_OFFSET_VALUE_MASK (0x3FFFFFFFFFFFULL >> PAGE_SHIFT)
+-#define KFD_MMAP_OFFSET_VALUE_GET(offset) (offset & KFD_MMAP_OFFSET_VALUE_MASK)
+-
+ /*
+ * When working with cp scheduler we should assign the HIQ manually or via
+ * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index 3f061264bae9..d78c36ba54e3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -616,8 +616,7 @@ static int kfd_process_init_cwsr_apu(struct kfd_process *p, struct file *filep)
+ if (!dev->cwsr_enabled || qpd->cwsr_kaddr || qpd->cwsr_base)
+ continue;
+
+- offset = (KFD_MMAP_TYPE_RESERVED_MEM | KFD_MMAP_GPU_ID(dev->id))
+- << PAGE_SHIFT;
++ offset = KFD_MMAP_TYPE_RESERVED_MEM | KFD_MMAP_GPU_ID(dev->id);
+ qpd->tba_addr = (int64_t)vm_mmap(filep, 0,
+ KFD_CWSR_TBA_TMA_SIZE, PROT_READ | PROT_EXEC,
+ MAP_SHARED, offset);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch
new file mode 100644
index 00000000..d01a6942
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch
@@ -0,0 +1,130 @@
+From 502b21ae7fe7e687739a5a14b15e738565a061ce Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Fri, 8 Nov 2019 13:20:30 +0800
+Subject: [PATCH 4404/4736] drm/amd/powerplay: dynamically disable ds and ulv
+ for compute
+
+This is to improve the performance in the compute mode
+for vega10. For example, the original performance for a rocm
+bandwidth test: 2G internal GPU copy, is about 99GB/s.
+With the idle power features disabled dynamically, the porformance
+is promoted to about 215GB/s.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 8 +++
+ .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 55 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +
+ 3 files changed, 65 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 031447675203..7932eb163a00 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -969,6 +969,14 @@ static int pp_dpm_switch_power_profile(void *handle,
+ workload = hwmgr->workload_setting[index];
+ }
+
++ if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
++ hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
++ if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) {
++ mutex_unlock(&hwmgr->smu_lock);
++ return -EINVAL;
++ }
++ }
++
+ if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+ hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
+ mutex_unlock(&hwmgr->smu_lock);
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index f62e320ed43d..8d933cb7e451 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -5262,6 +5262,59 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
+ return 0;
+ }
+
++static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
++{
++ struct vega10_hwmgr *data = hwmgr->backend;
++ uint32_t feature_mask = 0;
++
++ if (disable) {
++ feature_mask |= data->smu_features[GNLD_ULV].enabled ?
++ data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
++ feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
++ data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
++ feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
++ data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
++ feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
++ data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
++ feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
++ data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
++ } else {
++ feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
++ data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
++ feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
++ data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
++ feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
++ data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
++ feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
++ data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
++ feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
++ data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
++ }
++
++ if (feature_mask)
++ PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
++ !disable, feature_mask),
++ "enable/disable power features for compute performance Failed!",
++ return -EINVAL);
++
++ if (disable) {
++ data->smu_features[GNLD_ULV].enabled = false;
++ data->smu_features[GNLD_DS_GFXCLK].enabled = false;
++ data->smu_features[GNLD_DS_SOCCLK].enabled = false;
++ data->smu_features[GNLD_DS_LCLK].enabled = false;
++ data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
++ } else {
++ data->smu_features[GNLD_ULV].enabled = true;
++ data->smu_features[GNLD_DS_GFXCLK].enabled = true;
++ data->smu_features[GNLD_DS_SOCCLK].enabled = true;
++ data->smu_features[GNLD_DS_LCLK].enabled = true;
++ data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
++ }
++
++ return 0;
++
++}
++
+ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
+ .backend_init = vega10_hwmgr_backend_init,
+ .backend_fini = vega10_hwmgr_backend_fini,
+@@ -5328,6 +5381,8 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
+ .get_ppfeature_status = vega10_get_ppfeature_status,
+ .set_ppfeature_status = vega10_set_ppfeature_status,
+ .set_mp1_state = vega10_set_mp1_state,
++ .disable_power_features_for_compute_performance =
++ vega10_disable_power_features_for_compute_performance,
+ };
+
+ int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index 40403bc76f1b..af977675fd33 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -357,6 +357,8 @@ struct pp_hwmgr_func {
+ int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
+ int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
+ int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
++ int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
++ bool disable);
+ };
+
+ struct pp_table_func {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4405-drm-amdgpu-powerplay-fix-AVFS-handling-with-custom-p.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4405-drm-amdgpu-powerplay-fix-AVFS-handling-with-custom-p.patch
new file mode 100644
index 00000000..eda0baf2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4405-drm-amdgpu-powerplay-fix-AVFS-handling-with-custom-p.patch
@@ -0,0 +1,37 @@
+From 4c9392cb5170440181dddc15d057ef54dd416735 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 7 Nov 2019 09:50:18 -0500
+Subject: [PATCH 4405/4736] drm/amdgpu/powerplay: fix AVFS handling with custom
+ powerplay table
+
+When a custom powerplay table is provided, we need to update
+the OD VDDC flag to avoid AVFS being enabled when it shouldn't be.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index 8d933cb7e451..1f82c1f91247 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -3688,6 +3688,13 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
+ PP_ASSERT_WITH_CODE(!result,
+ "Failed to upload PPtable!", return result);
+
++ /*
++ * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
++ * That effectively disables AVFS feature.
++ */
++ if(hwmgr->hardcode_pp_table != NULL)
++ data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
++
+ vega10_update_avfs(hwmgr);
+
+ /*
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4406-drm-amd-display-remove-duplicated-assignment-to-grph.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4406-drm-amd-display-remove-duplicated-assignment-to-grph.patch
new file mode 100644
index 00000000..9e18b30b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4406-drm-amd-display-remove-duplicated-assignment-to-grph.patch
@@ -0,0 +1,33 @@
+From 243643406675ec9c987f47c9f6a4e0b946a75e59 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 8 Nov 2019 14:45:27 +0000
+Subject: [PATCH 4406/4736] drm/amd/display: remove duplicated assignment to
+ grph_obj_type
+
+Variable grph_obj_type is being assigned twice, one of these is
+redundant so remove it.
+
+Addresses-Coverity: ("Evaluation order violation")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+index 7d941b3802a6..6d5774144054 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+@@ -365,8 +365,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
+ router.ddc_valid = false;
+ router.cd_valid = false;
+ for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
+- uint8_t grph_obj_type=
+- grph_obj_type =
++ uint8_t grph_obj_type =
+ (le16_to_cpu(path->usGraphicObjIds[j]) &
+ OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4407-drm-amd-display-remove-redundant-variable-status.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4407-drm-amd-display-remove-redundant-variable-status.patch
new file mode 100644
index 00000000..2b163284
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4407-drm-amd-display-remove-redundant-variable-status.patch
@@ -0,0 +1,43 @@
+From 11b697a279f0db35ec688c84d49573b70c8183f6 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 8 Nov 2019 16:29:45 +0000
+Subject: [PATCH 4407/4736] drm/amd/display: remove redundant variable status
+
+Variable status is redundant, it is being initialized with a value
+that is over-written later and this is being returned immediately
+after the assignment. Clean up the code by removing status and
+just returning the value returned from the call to function
+dc->hwss.dmdata_status_done.
+
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 4431cc6000a1..2e03a1120bee 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -567,7 +567,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ {
+- bool status = true;
+ struct pipe_ctx *pipe = NULL;
+ int i;
+
+@@ -583,8 +582,7 @@ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ if (i == MAX_PIPES)
+ return true;
+
+- status = dc->hwss.dmdata_status_done(pipe);
+- return status;
++ return dc->hwss.dmdata_status_done(pipe);
+ }
+
+ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4408-drm-amdgpu-avoid-upload-corrupted-ta-ucode-to-psp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4408-drm-amdgpu-avoid-upload-corrupted-ta-ucode-to-psp.patch
new file mode 100644
index 00000000..03af0fcd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4408-drm-amdgpu-avoid-upload-corrupted-ta-ucode-to-psp.patch
@@ -0,0 +1,79 @@
+From 90813900c001e61af7a8f453168cb74114aba154 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 11 Nov 2019 12:26:36 +0800
+Subject: [PATCH 4408/4736] drm/amdgpu: avoid upload corrupted ta ucode to psp
+
+xgmi, ras, hdcp and dtm ta are actually separated ucode and
+need to handled case by case to upload to psp.
+
+We support the case that ta binary have one or multiple of
+them built-in. As a result, the driver should check each ta
+binariy's availablity before decide to upload them to psp.
+
+In the terminate (unload) case, the driver will check the
+context readiness before perform unload activity. It's fine
+to keep it as is.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 22 +++++++++++++++++++++-
+ 1 file changed, 21 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index a33d1ed6a096..2b513e41ed3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -569,7 +569,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
+ struct ta_xgmi_shared_memory *xgmi_cmd;
+ int ret;
+
+- if (!psp->adev->psp.ta_fw)
++ if (!psp->adev->psp.ta_fw ||
++ !psp->adev->psp.ta_xgmi_ucode_size ||
++ !psp->adev->psp.ta_xgmi_start_addr)
+ return -ENOENT;
+
+ if (!psp->xgmi_context.initialized) {
+@@ -779,6 +781,12 @@ static int psp_ras_initialize(struct psp_context *psp)
+ {
+ int ret;
+
++ if (!psp->adev->psp.ta_ras_ucode_size ||
++ !psp->adev->psp.ta_ras_start_addr) {
++ dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
++ return 0;
++ }
++
+ if (!psp->ras.ras_initialized) {
+ ret = psp_ras_init_shared_buf(psp);
+ if (ret)
+@@ -868,6 +876,12 @@ static int psp_hdcp_initialize(struct psp_context *psp)
+ {
+ int ret;
+
++ if (!psp->adev->psp.ta_hdcp_ucode_size ||
++ !psp->adev->psp.ta_hdcp_start_addr) {
++ dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
++ return 0;
++ }
++
+ if (!psp->hdcp_context.hdcp_initialized) {
+ ret = psp_hdcp_init_shared_buf(psp);
+ if (ret)
+@@ -1041,6 +1055,12 @@ static int psp_dtm_initialize(struct psp_context *psp)
+ {
+ int ret;
+
++ if (!psp->adev->psp.ta_dtm_ucode_size ||
++ !psp->adev->psp.ta_dtm_start_addr) {
++ dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
++ return 0;
++ }
++
+ if (!psp->dtm_context.dtm_initialized) {
+ ret = psp_dtm_init_shared_buf(psp);
+ if (ret)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4409-drm-amdgpu-powerplay-smu7-fix-AVFS-handling-with-cus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4409-drm-amdgpu-powerplay-smu7-fix-AVFS-handling-with-cus.patch
new file mode 100644
index 00000000..193572a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4409-drm-amdgpu-powerplay-smu7-fix-AVFS-handling-with-cus.patch
@@ -0,0 +1,37 @@
+From ae65cef2826c909d5652a4afe102a5075a2f97c8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 8 Nov 2019 11:15:17 -0500
+Subject: [PATCH 4409/4736] drm/amdgpu/powerplay/smu7: fix AVFS handling with
+ custom powerplay table
+
+When a custom powerplay table is provided, we need to update
+the OD VDDC flag to avoid AVFS being enabled when it shouldn't be.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 80bfdf178892..570625efce9d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -3968,6 +3968,13 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+ "Failed to populate and upload SCLK MCLK DPM levels!",
+ result = tmp_result);
+
++ /*
++ * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
++ * That effectively disables AVFS feature.
++ */
++ if (hwmgr->hardcode_pp_table != NULL)
++ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
++
+ tmp_result = smu7_update_avfs(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == tmp_result),
+ "Failed to update avfs voltages!",
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4410-drm-amd-display-remove-duplicated-comparison-express.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4410-drm-amd-display-remove-duplicated-comparison-express.patch
new file mode 100644
index 00000000..827e9eab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4410-drm-amd-display-remove-duplicated-comparison-express.patch
@@ -0,0 +1,33 @@
+From 72e75e071d23d87d981018d655abcd81b24881b5 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Sat, 9 Nov 2019 15:49:21 +0000
+Subject: [PATCH 4410/4736] drm/amd/display: remove duplicated comparison
+ expression
+
+There is comparison expression that is duplicated and hence one
+of the expressions can be removed. Remove it.
+
+Addresses-Coverity: ("Same on both sides")
+Fixes: 12e2b2d4c65f ("drm/amd/display: add dcc programming for dual plane")
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index a0ad1796af08..eda0d04f6ae5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1506,7 +1506,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
+ }
+
+ if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
+- || u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
+ || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
+ update_flags->bits.plane_size_change = 1;
+ elevate_update_type(&update_type, UPDATE_TYPE_MED);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4411-drm-amd-powerplay-remove-set-but-not-used-variable-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4411-drm-amd-powerplay-remove-set-but-not-used-variable-v.patch
new file mode 100644
index 00000000..0ba4f0d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4411-drm-amd-powerplay-remove-set-but-not-used-variable-v.patch
@@ -0,0 +1,66 @@
+From 096b7d05ab990ded5a3aca08430cbd3274c23c5e Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 11:45:55 +0800
+Subject: [PATCH 4411/4736] drm/amd/powerplay: remove set but not used variable
+ 'vbios_version', 'data'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c: In function smu7_check_mc_firmware:
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:4215:11: warning: variable vbios_version set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c: In function smu7_get_performance_level:
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:5054:21: warning: variable data set but not used [-Wunused-but-set-variable]
+
+'vbios_version' is introduced by commit 599a7e9fe1b6 ("drm/amd/powerplay:
+implement smu7 hwmgr to manager asics with smu ip version 7."),
+but never used, so remove it.
+
+'data' is introduced by commit f688b614b643 ("drm/amd/pp:
+Implement get_performance_level for legacy dgpu"), but never used,
+so remove it.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 570625efce9d..d3c3b3512a16 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -4224,7 +4224,6 @@ static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
+ {
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+- uint32_t vbios_version;
+ uint32_t tmp;
+
+ /* Read MC indirect register offset 0x9F bits [3:0] to see
+@@ -4233,7 +4232,6 @@ static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
+ */
+
+ smu7_get_mc_microcode_version(hwmgr);
+- vbios_version = hwmgr->microcode_version_info.MC & 0xf;
+
+ data->need_long_memory_training = false;
+
+@@ -5063,13 +5061,11 @@ static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw
+ PHM_PerformanceLevel *level)
+ {
+ const struct smu7_power_state *ps;
+- struct smu7_hwmgr *data;
+ uint32_t i;
+
+ if (level == NULL || hwmgr == NULL || state == NULL)
+ return -EINVAL;
+
+- data = hwmgr->backend;
+ ps = cast_const_phw_smu7_power_state(state);
+
+ i = index > ps->performance_level_count - 1 ?
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4412-drm-amd-powerplay-remove-set-but-not-used-variable-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4412-drm-amd-powerplay-remove-set-but-not-used-variable-d.patch
new file mode 100644
index 00000000..d58156f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4412-drm-amd-powerplay-remove-set-but-not-used-variable-d.patch
@@ -0,0 +1,44 @@
+From a4d708c33bb4375b21b13c9765fe9c8d82946d1d Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 11:45:56 +0800
+Subject: [PATCH 4412/4736] drm/amd/powerplay: remove set but not used variable
+ 'data'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c: In function vega10_get_performance_level:
+drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c:5217:23: warning: variable data set but not used [-Wunused-but-set-variable]
+
+'data' is introduced by commit f688b614b643 ("drm/amd/pp:
+Implement get_performance_level for legacy dgpu"), but never used,
+so remove it.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index 1f82c1f91247..b8cb492102ff 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -5251,13 +5251,11 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
+ PHM_PerformanceLevel *level)
+ {
+ const struct vega10_power_state *ps;
+- struct vega10_hwmgr *data;
+ uint32_t i;
+
+ if (level == NULL || hwmgr == NULL || state == NULL)
+ return -EINVAL;
+
+- data = hwmgr->backend;
+ ps = cast_const_phw_vega10_power_state(state);
+
+ i = index > ps->performance_level_count - 1 ?
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4413-drm-amd-display-Use-static-const-not-const-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4413-drm-amd-display-Use-static-const-not-const-static.patch
new file mode 100644
index 00000000..9619d40c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4413-drm-amd-display-Use-static-const-not-const-static.patch
@@ -0,0 +1,30 @@
+From 8b238f08483fbae1b1c97c50c5af4362efab2527 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 17:33:13 +0800
+Subject: [PATCH 4413/4736] drm/amd/display: Use static const, not const static
+
+Move the static keyword to the front of declarations.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index eda0d04f6ae5..9e600d3e2fd8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -70,7 +70,7 @@
+ #define DC_LOGGER \
+ dc->ctx->logger
+
+-const static char DC_BUILD_ID[] = "production-build";
++static const char DC_BUILD_ID[] = "production-build";
+
+ /**
+ * DOC: Overview
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4414-drm-amd-powerplay-remove-set-but-not-used-variable-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4414-drm-amd-powerplay-remove-set-but-not-used-variable-t.patch
new file mode 100644
index 00000000..5278b331
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4414-drm-amd-powerplay-remove-set-but-not-used-variable-t.patch
@@ -0,0 +1,66 @@
+From b4bb7137fa42f4188a897f985455cb46f7b7c9df Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 12:09:28 +0800
+Subject: [PATCH 4414/4736] drm/amd/powerplay: remove set but not used variable
+ 'threshold', 'state'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c: In function fiji_populate_single_graphic_level:
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c:943:11: warning: variable threshold set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c: In function fiji_populate_memory_timing_parameters:
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c:1504:8: warning: variable state set but not used [-Wunused-but-set-variable]
+
+They are introduced by commit 2e112b4ae3ba ("drm/amd/pp:
+remove fiji_smc/smumgr split."), but never used,
+so remove it.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+index da025b1d302d..32ebb383c456 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+@@ -940,7 +940,7 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ {
+ int result;
+ /* PP_Clocks minClocks; */
+- uint32_t threshold, mvdd;
++ uint32_t mvdd;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+@@ -973,8 +973,6 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ level->VoltageDownHyst = 0;
+ level->PowerThrottle = 0;
+
+- threshold = clock * data->fast_watermark_threshold / 100;
+-
+ data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
+@@ -1501,7 +1499,7 @@ static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
+ uint32_t dram_timing;
+ uint32_t dram_timing2;
+ uint32_t burstTime;
+- ULONG state, trrds, trrdl;
++ ULONG trrds, trrdl;
+ int result;
+
+ result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
+@@ -1513,7 +1511,6 @@ static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
+ dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
+ burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
+
+- state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
+ trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
+ trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4415-drm-amd-display-remove-set-but-not-used-variable-ds_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4415-drm-amd-display-remove-set-but-not-used-variable-ds_.patch
new file mode 100644
index 00000000..26094873
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4415-drm-amd-display-remove-set-but-not-used-variable-ds_.patch
@@ -0,0 +1,45 @@
+From 5f27eada534da5d39a176e609504dc3776c6d827 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Sat, 9 Nov 2019 17:37:25 +0800
+Subject: [PATCH 4415/4736] drm/amd/display: remove set but not used variable
+ 'ds_port'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c: In function dp_wa_power_up_0010FA:
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:2320:35: warning:
+ variable ds_port set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 7d18fc1e68c6..66f59058b56d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2924,7 +2924,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+ int length)
+ {
+ int retry = 0;
+- union dp_downstream_port_present ds_port = { 0 };
+
+ if (!link->dpcd_caps.dpcd_rev.raw) {
+ do {
+@@ -2937,9 +2936,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+ } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
+ }
+
+- ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
+- DP_DPCD_REV];
+-
+ if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
+ switch (link->dpcd_caps.branch_dev_id) {
+ /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4416-drm-amdgpu-navi10-implement-sclk-mclk-OD-via-pp_od_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4416-drm-amdgpu-navi10-implement-sclk-mclk-OD-via-pp_od_c.patch
new file mode 100644
index 00000000..55d0d6bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4416-drm-amdgpu-navi10-implement-sclk-mclk-OD-via-pp_od_c.patch
@@ -0,0 +1,274 @@
+From a3047065b91b159276dfcb41c6477fd27916c5d0 Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Fri, 8 Nov 2019 14:28:06 -0700
+Subject: [PATCH 4416/4736] drm/amdgpu/navi10: implement sclk/mclk OD via
+ pp_od_clk_voltage
+
+[Why]
+Before this patch, there was no way to use pp_od_clk_voltage on navi
+
+[How]
+Similar to the vega20 implementation, but using the common smc_v11_0
+headers, implemented the pp_od_clk_voltage API for navi10's pptable
+implementation
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 180 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 27 +++
+ 3 files changed, 209 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 36028e9d1011..0ec6ed0456e0 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -251,4 +251,6 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
+
+ int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
+
++int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 010be21bee5b..5c4c1f416f3e 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1648,10 +1648,188 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ SMU_MSG_OverridePcieParameters,
+ smu_pcie_arg);
+ }
++ return ret;
++}
++
++static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
++ pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
++ pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
++ pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
++ pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
++ pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
++ pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
++}
++
++static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
++{
++ return od_table->cap[feature];
++}
++
++static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
++{
++ if (value < od_table->min[setting]) {
++ pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
++ return -EINVAL;
++ }
++ if (value > od_table->max[setting]) {
++ pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static int navi10_setup_od_limits(struct smu_context *smu) {
++ struct smu_11_0_overdrive_table *overdrive_table = NULL;
++ struct smu_11_0_powerplay_table *powerplay_table = NULL;
++
++ if (!smu->smu_table.power_play_table) {
++ pr_err("powerplay table uninitialized!\n");
++ return -ENOENT;
++ }
++ powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
++ overdrive_table = &powerplay_table->overdrive_table;
++ if (!smu->od_settings) {
++ smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
++ } else {
++ memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
++ }
++ return 0;
++}
++
++static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
++ OverDriveTable_t *od_table;
++ int ret = 0;
++
++ ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
++ if (ret)
++ return ret;
++
++ if (initialize) {
++ ret = navi10_setup_od_limits(smu);
++ if (ret) {
++ pr_err("Failed to retrieve board OD limits\n");
++ return ret;
++ }
++
++ }
++
++ od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
++ if (od_table) {
++ navi10_dump_od_table(od_table);
++ }
+
+ return ret;
+ }
+
++static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
++ int i;
++ int ret = 0;
++ struct smu_table_context *table_context = &smu->smu_table;
++ OverDriveTable_t *od_table;
++ struct smu_11_0_overdrive_table *od_settings;
++ od_table = (OverDriveTable_t *)table_context->overdrive_table;
++
++ if (!smu->od_enabled) {
++ pr_warn("OverDrive is not enabled!\n");
++ return -EINVAL;
++ }
++
++ if (!smu->od_settings) {
++ pr_err("OD board limits are not set!\n");
++ return -ENOENT;
++ }
++
++ od_settings = smu->od_settings;
++
++ switch (type) {
++ case PP_OD_EDIT_SCLK_VDDC_TABLE:
++ if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
++ pr_warn("GFXCLK_LIMITS not supported!\n");
++ return -ENOTSUPP;
++ }
++ if (!table_context->overdrive_table) {
++ pr_err("Overdrive is not initialized\n");
++ return -EINVAL;
++ }
++ for (i = 0; i < size; i += 2) {
++ if (i + 2 > size) {
++ pr_info("invalid number of input parameters %d\n", size);
++ return -EINVAL;
++ }
++ switch (input[i]) {
++ case 0:
++ freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
++ freq_ptr = &od_table->GfxclkFmin;
++ if (input[i + 1] > od_table->GfxclkFmax) {
++ pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
++ input[i + 1],
++ od_table->GfxclkFmin);
++ return -EINVAL;
++ }
++ break;
++ case 1:
++ freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
++ freq_ptr = &od_table->GfxclkFmax;
++ if (input[i + 1] < od_table->GfxclkFmin) {
++ pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
++ input[i + 1],
++ od_table->GfxclkFmax);
++ return -EINVAL;
++ }
++ break;
++ default:
++ pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
++ pr_info("Supported indices: [0:min,1:max]\n");
++ return -EINVAL;
++ }
++ ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
++ if (ret)
++ return ret;
++ *freq_ptr = input[i + 1];
++ }
++ break;
++ case PP_OD_EDIT_MCLK_VDDC_TABLE:
++ if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
++ pr_warn("UCLK_MAX not supported!\n");
++ return -ENOTSUPP;
++ }
++ if (size < 2) {
++ pr_info("invalid number of parameters: %d\n", size);
++ return -EINVAL;
++ }
++ if (input[0] != 1) {
++ pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
++ pr_info("Supported indices: [1:max]\n");
++ return -EINVAL;
++ }
++ ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
++ if (ret)
++ return ret;
++ od_table->UclkFmax = input[1];
++ break;
++ case PP_OD_COMMIT_DPM_TABLE:
++ navi10_dump_od_table(od_table);
++ ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
++ if (ret) {
++ pr_err("Failed to import overdrive table!\n");
++ return ret;
++ }
++ // no lock needed because smu_od_edit_dpm_table has it
++ ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
++ AMD_PP_TASK_READJUST_POWER_STATE,
++ false);
++ if (ret) {
++ return ret;
++ }
++ break;
++ case PP_OD_EDIT_VDDC_CURVE:
++ // TODO: implement
++ return -ENOSYS;
++ default:
++ return -ENOSYS;
++ }
++ return ret;
++}
+
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ .tables_init = navi10_tables_init,
+@@ -1741,6 +1919,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
++ .set_default_od_settings = navi10_set_default_od_settings,
++ .od_edit_dpm_table = navi10_od_edit_dpm_table,
+ };
+
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 9ebc00a97096..13ae44ca3504 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1778,3 +1778,30 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+ return ret;
+
+ }
++
++int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
++{
++ struct smu_table_context *table_context = &smu->smu_table;
++ int ret = 0;
++
++ if (initialize) {
++ if (table_context->overdrive_table) {
++ return -EINVAL;
++ }
++ table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
++ if (!table_context->overdrive_table) {
++ return -ENOMEM;
++ }
++ ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
++ if (ret) {
++ pr_err("Failed to export overdrive table!\n");
++ return ret;
++ }
++ }
++ ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
++ if (ret) {
++ pr_err("Failed to import overdrive table!\n");
++ return ret;
++ }
++ return ret;
++}
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4417-drm-amdgpu-navi10-implement-GFXCLK_CURVE-overdrive.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4417-drm-amdgpu-navi10-implement-GFXCLK_CURVE-overdrive.patch
new file mode 100644
index 00000000..47b4cb82
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4417-drm-amdgpu-navi10-implement-GFXCLK_CURVE-overdrive.patch
@@ -0,0 +1,115 @@
+From 7151dd70272d2a08a36e518aaa4c3553567cbb0c Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Fri, 8 Nov 2019 14:28:07 -0700
+Subject: [PATCH 4417/4736] drm/amdgpu/navi10: implement GFXCLK_CURVE overdrive
+
+[Why]
+Before this patch, there was no way to set the gfxclk voltage curve in
+the overdrive settings for navi10 through pp_od_clk_voltage
+
+[How]
+Add the required implementation to navi10's ppt dpm table editing
+implementation, similar to the vega20 implementation and interface.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 60 +++++++++++++++++++++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 2 +
+ 2 files changed, 60 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 5c4c1f416f3e..c1690052538f 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1727,6 +1727,8 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
+ struct smu_table_context *table_context = &smu->smu_table;
+ OverDriveTable_t *od_table;
+ struct smu_11_0_overdrive_table *od_settings;
++ enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
++ uint16_t *freq_ptr, *voltage_ptr;
+ od_table = (OverDriveTable_t *)table_context->overdrive_table;
+
+ if (!smu->od_enabled) {
+@@ -1823,8 +1825,62 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
+ }
+ break;
+ case PP_OD_EDIT_VDDC_CURVE:
+- // TODO: implement
+- return -ENOSYS;
++ if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
++ pr_warn("GFXCLK_CURVE not supported!\n");
++ return -ENOTSUPP;
++ }
++ if (size < 3) {
++ pr_info("invalid number of parameters: %d\n", size);
++ return -EINVAL;
++ }
++ if (!od_table) {
++ pr_info("Overdrive is not initialized\n");
++ return -EINVAL;
++ }
++
++ switch (input[0]) {
++ case 0:
++ freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
++ voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
++ freq_ptr = &od_table->GfxclkFreq1;
++ voltage_ptr = &od_table->GfxclkVolt1;
++ break;
++ case 1:
++ freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
++ voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
++ freq_ptr = &od_table->GfxclkFreq2;
++ voltage_ptr = &od_table->GfxclkVolt2;
++ break;
++ case 2:
++ freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
++ voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
++ freq_ptr = &od_table->GfxclkFreq3;
++ voltage_ptr = &od_table->GfxclkVolt3;
++ break;
++ default:
++ pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
++ pr_info("Supported indices: [0, 1, 2]\n");
++ return -EINVAL;
++ }
++ ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
++ if (ret)
++ return ret;
++ // Allow setting zero to disable the OverDrive VDDC curve
++ if (input[2] != 0) {
++ ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
++ if (ret)
++ return ret;
++ *freq_ptr = input[1];
++ *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
++ pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
++ } else {
++ // If setting 0, disable all voltage curve settings
++ od_table->GfxclkVolt1 = 0;
++ od_table->GfxclkVolt2 = 0;
++ od_table->GfxclkVolt3 = 0;
++ }
++ navi10_dump_od_table(od_table);
++ break;
+ default:
+ return -ENOSYS;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index a37e37c5f105..fd6dda1a67a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -33,6 +33,8 @@
+ #define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK (1717)
+ #define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK (1448)
+
++#define NAVI10_VOLTAGE_SCALE (4)
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4418-drm-amdgpu-navi10-Implement-od-clk-printing.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4418-drm-amdgpu-navi10-Implement-od-clk-printing.patch
new file mode 100644
index 00000000..7762cefb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4418-drm-amdgpu-navi10-Implement-od-clk-printing.patch
@@ -0,0 +1,115 @@
+From db1efd8ead62db29d93e7ef8b8bb24069b0395b6 Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Fri, 8 Nov 2019 14:28:08 -0700
+Subject: [PATCH 4418/4736] drm/amdgpu/navi10: Implement od clk printing
+
+[Why]
+Before this patch, navi10 overdrive settings could not be printed via
+pp_od_clk_voltage
+
+[How]
+Implement printing for the overdrive settings for the following clocks
+in navi10's ppt print_clk_levels implementation:
+
+* SMU_OD_SCLK
+* SMU_OD_MCLK
+* SMU_OD_VDDC_CURVE
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 56 ++++++++++++++++++++--
+ 1 file changed, 51 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index c1690052538f..5c6ffbd0d884 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -690,13 +690,25 @@ static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu
+ return dpm_desc->SnapToDiscrete == 0 ? true : false;
+ }
+
++static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
++{
++ return od_table->cap[feature];
++}
++
++
+ static int navi10_print_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type, char *buf)
+ {
++ OverDriveTable_t *od_table;
++ struct smu_11_0_overdrive_table *od_settings;
++ uint16_t *curve_settings;
+ int i, size = 0, ret = 0;
+ uint32_t cur_value = 0, value = 0, count = 0;
+ uint32_t freq_values[3] = {0};
+ uint32_t mark_index = 0;
++ struct smu_table_context *table_context = &smu->smu_table;
++ od_table = (OverDriveTable_t *)table_context->overdrive_table;
++ od_settings = smu->od_settings;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+@@ -747,6 +759,45 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+
+ }
+ break;
++ case SMU_OD_SCLK:
++ if (!smu->od_enabled || !od_table || !od_settings)
++ break;
++ if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
++ break;
++ size += sprintf(buf + size, "OD_SCLK:\n");
++ size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
++ break;
++ case SMU_OD_MCLK:
++ if (!smu->od_enabled || !od_table || !od_settings)
++ break;
++ if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
++ break;
++ size += sprintf(buf + size, "OD_MCLK:\n");
++ size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax);
++ break;
++ case SMU_OD_VDDC_CURVE:
++ if (!smu->od_enabled || !od_table || !od_settings)
++ break;
++ if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
++ break;
++ size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
++ for (i = 0; i < 3; i++) {
++ switch (i) {
++ case 0:
++ curve_settings = &od_table->GfxclkFreq1;
++ break;
++ case 1:
++ curve_settings = &od_table->GfxclkFreq2;
++ break;
++ case 2:
++ curve_settings = &od_table->GfxclkFreq3;
++ break;
++ default:
++ break;
++ }
++ size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
++ }
++ break;
+ default:
+ break;
+ }
+@@ -1660,11 +1711,6 @@ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+ pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
+ }
+
+-static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
+-{
+- return od_table->cap[feature];
+-}
+-
+ static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
+ {
+ if (value < od_table->min[setting]) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4419-drm-amdgpu-smu_v11-Unify-and-fix-power-limits.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4419-drm-amdgpu-smu_v11-Unify-and-fix-power-limits.patch
new file mode 100644
index 00000000..5ab66eeb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4419-drm-amdgpu-smu_v11-Unify-and-fix-power-limits.patch
@@ -0,0 +1,318 @@
+From bded65628b641bb8cb50be6190abf36500a91624 Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Mon, 11 Nov 2019 11:36:31 -0700
+Subject: [PATCH 4419/4736] drm/amdgpu/smu_v11: Unify and fix power limits
+
+[Why]
+On Navi10, and presumably arcterus, updating pp_table via sysfs would
+not re-scale the maximum possible power limit one can set. On navi10,
+the SMU code ignored the power percentage overdrive setting entirely,
+and would not allow you to exceed the default power limit at all.
+
+[How]
+Adding a function to the SMU interface to get the pptable version of the
+default power limit allows ASIC-specific code to provide the correct
+maximum-settable power limit for the current pptable.
+
+v3: fix spelling (Alex)
+
+Change-Id: Idfa0d2ec64da34520e2928e5011ac3c54bf60a4d
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 12 +++++-
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 23 ++++++-----
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +
+ .../drm/amd/powerplay/inc/smu_v11_0_pptable.h | 2 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 22 +++++-----
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 40 +++++++++++++++++--
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 -
+ 8 files changed, 78 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 76a4154b3be2..df5487fae20a 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1109,7 +1109,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ if (ret)
+ return ret;
+
+- ret = smu_get_power_limit(smu, &smu->default_power_limit, true, false);
++ ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
+ if (ret)
+ return ret;
+ }
+@@ -2511,3 +2511,13 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
+
+ return ret;
+ }
++
++uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
++{
++ uint32_t ret = 0;
++
++ if (smu->ppt_funcs->get_pptable_power_limit)
++ ret = smu->ppt_funcs->get_pptable_power_limit(smu);
++
++ return ret;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 4315a887e918..6d1401b30aaf 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1261,15 +1261,14 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
+
+ static int arcturus_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+- bool asic_default)
++ bool cap)
+ {
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ uint32_t asic_default_power_limit = 0;
+ int ret = 0;
+ int power_src;
+
+- if (!smu->default_power_limit ||
+- !smu->power_limit) {
++ if (!smu->power_limit) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
+ if (power_src < 0)
+@@ -1292,17 +1291,11 @@ static int arcturus_get_power_limit(struct smu_context *smu,
+ pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+ }
+
+- if (smu->od_enabled) {
+- asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
+- asic_default_power_limit /= 100;
+- }
+-
+- smu->default_power_limit = asic_default_power_limit;
+ smu->power_limit = asic_default_power_limit;
+ }
+
+- if (asic_default)
+- *limit = smu->default_power_limit;
++ if (cap)
++ *limit = smu_v11_0_get_max_power_limit(smu);
+ else
+ *limit = smu->power_limit;
+
+@@ -2070,6 +2063,13 @@ static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
+ i2c_del_adapter(control);
+ }
+
++static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
++{
++ PPTable_t *pptable = smu->smu_table.driver_pptable;
++
++ return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+ /* translate smu index into arcturus specific index */
+ .get_smu_msg_index = arcturus_get_smu_msg_index,
+@@ -2160,6 +2160,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
++ .get_pptable_power_limit = arcturus_get_pptable_power_limit,
+ };
+
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 8120e7587585..999445c5c010 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -261,7 +261,6 @@ struct smu_table_context
+ struct smu_table *tables;
+ struct smu_table memory_pool;
+ uint8_t thermal_controller_type;
+- uint16_t TDPODLimit;
+
+ void *overdrive_table;
+ };
+@@ -548,6 +547,7 @@ struct pptable_funcs {
+ int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
+ int (*override_pcie_parameters)(struct smu_context *smu);
++ uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
+ };
+
+ int smu_load_microcode(struct smu_context *smu);
+@@ -717,4 +717,6 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
+ int smu_get_dpm_clock_table(struct smu_context *smu,
+ struct dpm_clocks *clock_table);
+
++uint32_t smu_get_pptable_power_limit(struct smu_context *smu);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 0ec6ed0456e0..0269fac1a77b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -253,4 +253,6 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
+
+ int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size);
+
++uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
+index 86cdc3393eac..b2f96a101124 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
+@@ -141,7 +141,9 @@ struct smu_11_0_powerplay_table
+ struct smu_11_0_power_saving_clock_table power_saving_clock;
+ struct smu_11_0_overdrive_table overdrive_table;
+
++#ifndef SMU_11_0_PARTIAL_PPTABLE
+ PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
++#endif
+ } __attribute__((packed));
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 5c6ffbd0d884..17ccdb74f4e2 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1632,17 +1632,22 @@ static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
+ return ret;
+ }
+
++static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
++{
++ PPTable_t *pptable = smu->smu_table.driver_pptable;
++ return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
++}
++
+ static int navi10_get_power_limit(struct smu_context *smu,
+ uint32_t *limit,
+- bool asic_default)
++ bool cap)
+ {
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ uint32_t asic_default_power_limit = 0;
+ int ret = 0;
+ int power_src;
+
+- if (!smu->default_power_limit ||
+- !smu->power_limit) {
++ if (!smu->power_limit) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
+ if (power_src < 0)
+@@ -1665,17 +1670,11 @@ static int navi10_get_power_limit(struct smu_context *smu,
+ pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+ }
+
+- if (smu->od_enabled) {
+- asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
+- asic_default_power_limit /= 100;
+- }
+-
+- smu->default_power_limit = asic_default_power_limit;
+ smu->power_limit = asic_default_power_limit;
+ }
+
+- if (asic_default)
+- *limit = smu->default_power_limit;
++ if (cap)
++ *limit = smu_v11_0_get_max_power_limit(smu);
+ else
+ *limit = smu->power_limit;
+
+@@ -2023,6 +2022,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ .set_default_od_settings = navi10_set_default_od_settings,
+ .od_edit_dpm_table = navi10_od_edit_dpm_table,
++ .get_pptable_power_limit = navi10_get_pptable_power_limit,
+ };
+
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 13ae44ca3504..928877f73dfd 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -20,6 +20,8 @@
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
++#define SMU_11_0_PARTIAL_PPTABLE
++
+ #include "pp_debug.h"
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+@@ -28,6 +30,7 @@
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
++#include "smu_v11_0_pptable.h"
+ #include "soc15_common.h"
+ #include "atom.h"
+ #include "amd_pcie.h"
+@@ -1045,13 +1048,44 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+ return 0;
+ }
+
++uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
++ uint32_t od_limit, max_power_limit;
++ struct smu_11_0_powerplay_table *powerplay_table = NULL;
++ struct smu_table_context *table_context = &smu->smu_table;
++ powerplay_table = table_context->power_play_table;
++
++ max_power_limit = smu_get_pptable_power_limit(smu);
++
++ if (!max_power_limit) {
++ // If we couldn't get the table limit, fall back on first-read value
++ if (!smu->default_power_limit)
++ smu->default_power_limit = smu->power_limit;
++ max_power_limit = smu->default_power_limit;
++ }
++
++ if (smu->od_enabled) {
++ od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
++
++ pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
++
++ max_power_limit *= (100 + od_limit);
++ max_power_limit /= 100;
++ }
++
++ return max_power_limit;
++}
++
+ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ {
+ int ret = 0;
++ uint32_t max_power_limit;
++
++ max_power_limit = smu_v11_0_get_max_power_limit(smu);
+
+- if (n > smu->default_power_limit) {
+- pr_err("New power limit is over the max allowed %d\n",
+- smu->default_power_limit);
++ if (n > max_power_limit) {
++ pr_err("New power limit (%d) is over the max allowed %d\n",
++ n,
++ max_power_limit);
+ return -EINVAL;
+ }
+
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index e00ffbbde791..399697a2ad7f 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -466,7 +466,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
+ sizeof(PPTable_t));
+
+ table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
+- table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
+
+ return 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4420-drm-amdkfd-Use-better-name-to-indicate-the-offset-is.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4420-drm-amdkfd-Use-better-name-to-indicate-the-offset-is.patch
new file mode 100644
index 00000000..3c91bc67
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4420-drm-amdkfd-Use-better-name-to-indicate-the-offset-is.patch
@@ -0,0 +1,117 @@
+From 1997547bbbc45a9e1b616819ce3dfe998a51bb0b Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 13:16:34 -0500
+Subject: [PATCH 4420/4736] drm/amdkfd: Use better name to indicate the offset
+ is in dwords
+
+The doorbell offset could mean the byte offset or the dword offset,
+and the 0 offset place is also different, sometimes the start of PCI
+doorbell bar or the start of process doorbell pages. Use better name
+to avoid confusion.
+
+Change-Id: I75da23bba90231762cf58da3170f5bb77ece45ed
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 14 +++++++-------
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 +++++----
+ 3 files changed, 13 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 2f0aeb60fe40..0ec9370976d9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -199,7 +199,7 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
+ }
+
+ q->properties.doorbell_off =
+- kfd_doorbell_id_to_offset(dev, q->process,
++ kfd_get_doorbell_dw_offset_in_bar(dev, q->process,
+ q->doorbell_id);
+
+ return 0;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+index 9f5024bce095..d2be603f9e88 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+@@ -91,7 +91,7 @@ int kfd_doorbell_init(struct kfd_dev *kfd)
+ kfd->doorbell_base = kfd->shared_resources.doorbell_physical_address +
+ doorbell_start_offset;
+
+- kfd->doorbell_id_offset = doorbell_start_offset / sizeof(u32);
++ kfd->doorbell_base_dw_offset = doorbell_start_offset / sizeof(u32);
+
+ kfd->doorbell_kernel_ptr = ioremap(kfd->doorbell_base,
+ kfd_doorbell_process_slice(kfd));
+@@ -103,8 +103,8 @@ int kfd_doorbell_init(struct kfd_dev *kfd)
+ pr_debug("doorbell base == 0x%08lX\n",
+ (uintptr_t)kfd->doorbell_base);
+
+- pr_debug("doorbell_id_offset == 0x%08lX\n",
+- kfd->doorbell_id_offset);
++ pr_debug("doorbell_base_dw_offset == 0x%08lX\n",
++ kfd->doorbell_base_dw_offset);
+
+ pr_debug("doorbell_process_limit == 0x%08lX\n",
+ doorbell_process_limit);
+@@ -320,7 +320,7 @@ void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
+ * Calculating the kernel doorbell offset using the first
+ * doorbell page.
+ */
+- *doorbell_off = kfd->doorbell_id_offset + inx;
++ *doorbell_off = kfd->doorbell_base_dw_offset + inx;
+
+ pr_debug("Get kernel queue doorbell\n"
+ " doorbell offset == 0x%08X\n"
+@@ -360,17 +360,17 @@ void write_kernel_doorbell64(void __iomem *db, u64 value)
+ }
+ }
+
+-unsigned int kfd_doorbell_id_to_offset(struct kfd_dev *kfd,
++unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
+ struct kfd_process *process,
+ unsigned int doorbell_id)
+ {
+ /*
+- * doorbell_id_offset accounts for doorbells taken by KGD.
++ * doorbell_base_dw_offset accounts for doorbells taken by KGD.
+ * index * kfd_doorbell_process_slice/sizeof(u32) adjusts to
+ * the process's doorbells. The offset returned is in dword
+ * units regardless of the ASIC-dependent doorbell size.
+ */
+- return kfd->doorbell_id_offset +
++ return kfd->doorbell_base_dw_offset +
+ process->doorbell_index
+ * kfd_doorbell_process_slice(kfd) / sizeof(u32) +
+ doorbell_id * kfd->device_info->doorbell_size / sizeof(u32);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 107b23187009..ff60fb75f224 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -248,9 +248,10 @@ struct kfd_dev {
+ * KFD. It is aligned for mapping
+ * into user mode
+ */
+- size_t doorbell_id_offset; /* Doorbell offset (from KFD doorbell
+- * to HW doorbell, GFX reserved some
+- * at the start)
++ size_t doorbell_base_dw_offset; /* Offset from the start of the PCI
++ * doorbell BAR to the first KFD
++ * doorbell in dwords. GFX reserves
++ * the segment before this offset.
+ */
+ u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
+ * page used by kernel queue
+@@ -958,7 +959,7 @@ void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr);
+ u32 read_kernel_doorbell(u32 __iomem *db);
+ void write_kernel_doorbell(void __iomem *db, u32 value);
+ void write_kernel_doorbell64(void __iomem *db, u64 value);
+-unsigned int kfd_doorbell_id_to_offset(struct kfd_dev *kfd,
++unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
+ struct kfd_process *process,
+ unsigned int doorbell_id);
+ phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4421-drm-amdkfd-Avoid-using-doorbell_off-as-offset-in-pro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4421-drm-amdkfd-Avoid-using-doorbell_off-as-offset-in-pro.patch
new file mode 100644
index 00000000..c3440c11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4421-drm-amdkfd-Avoid-using-doorbell_off-as-offset-in-pro.patch
@@ -0,0 +1,120 @@
+From b1ccb6a03bc794d974bb99fda908e3bc23c36a8e Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 13:58:57 -0500
+Subject: [PATCH 4421/4736] drm/amdkfd: Avoid using doorbell_off as offset in
+ process doorbell pages
+
+dorbell_off in the queue properties is mainly used for the doorbell dw
+offset in pci bar. We should not set it to the doorbell byte offset in
+process doorbell pages. This makes the code much easier to read.
+
+Change-Id: I553045ff9fcb3676900c92d10426f2ceb3660005
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 ++++++------
+ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++-
+ .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 10 +++++++---
+ 4 files changed, 16 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 59bfbed3c000..d9cdb25974f9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -282,6 +282,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ unsigned int queue_id;
+ struct kfd_process_device *pdd;
+ struct queue_properties q_properties;
++ uint32_t doorbell_offset_in_process = 0;
+
+ memset(&q_properties, 0, sizeof(struct queue_properties));
+
+@@ -310,7 +311,8 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ p->pasid,
+ dev->id);
+
+- err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id);
++ err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id,
++ &doorbell_offset_in_process);
+ if (err != 0)
+ goto err_create_queue;
+
+@@ -321,12 +323,10 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
+ args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
+ if (KFD_IS_SOC15(dev->device_info->asic_family))
+- /* On SOC15 ASICs, doorbell allocation must be
+- * per-device, and independent from the per-process
+- * queue_id. Return the doorbell offset within the
+- * doorbell aperture to user mode.
++ /* On SOC15 ASICs, include the doorbell offset within the
++ * process doorbell frame, which is 2 pages.
+ */
+- args->doorbell_offset |= q_properties.doorbell_off;
++ args->doorbell_offset |= doorbell_offset_in_process;
+
+ mutex_unlock(&p->mutex);
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+index 1eb0c2bedcd9..142ac7954032 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+@@ -192,7 +192,7 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev)
+ properties.type = KFD_QUEUE_TYPE_DIQ;
+
+ status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL,
+- &properties, &qid);
++ &properties, &qid, NULL);
+
+ if (status) {
+ pr_err("Failed to create DIQ\n");
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index ff60fb75f224..e937679f8ca1 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -1045,7 +1045,8 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ struct kfd_dev *dev,
+ struct file *f,
+ struct queue_properties *properties,
+- unsigned int *qid);
++ unsigned int *qid,
++ uint32_t *p_doorbell_offset_in_process);
+ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
+ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid,
+ struct queue_properties *p);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index 227fb0ec8115..591b5d05ab53 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -192,7 +192,8 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ struct kfd_dev *dev,
+ struct file *f,
+ struct queue_properties *properties,
+- unsigned int *qid)
++ unsigned int *qid,
++ uint32_t *p_doorbell_offset_in_process)
+ {
+ int retval;
+ struct kfd_process_device *pdd;
+@@ -303,12 +304,15 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ goto err_create_queue;
+ }
+
+- if (q)
++ if (q && p_doorbell_offset_in_process)
+ /* Return the doorbell offset within the doorbell page
+ * to the caller so it can be passed up to user mode
+ * (in bytes).
++ * There are always 1024 doorbells per process, so in case
++ * of 8-byte doorbells, there are two doorbell pages per
++ * process.
+ */
+- properties->doorbell_off =
++ *p_doorbell_offset_in_process =
+ (q->properties.doorbell_off * sizeof(uint32_t)) &
+ (kfd_doorbell_process_slice(dev) - 1);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4422-drm-amdkfd-Rename-create_cp_queue-to-init_user_queue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4422-drm-amdkfd-Rename-create_cp_queue-to-init_user_queue.patch
new file mode 100644
index 00000000..a7c3727a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4422-drm-amdkfd-Rename-create_cp_queue-to-init_user_queue.patch
@@ -0,0 +1,50 @@
+From edd7f06fc4a2eb254e4c7c23786ecf0ae3b3634d Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 19:23:16 -0500
+Subject: [PATCH 4422/4736] drm/amdkfd: Rename create_cp_queue() to
+ init_user_queue()
+
+create_cp_queue() could also work with SDMA queues, so we should rename
+it. It only initialize the data values rather than creating queues.
+
+Change-Id: I76cbaed8fa95dd9062d786cbc1dd037ff041da9d
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index 591b5d05ab53..93a349f9c205 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -162,7 +162,7 @@ void pqm_uninit(struct process_queue_manager *pqm)
+ pqm->queue_slot_bitmap = NULL;
+ }
+
+-static int create_cp_queue(struct process_queue_manager *pqm,
++static int init_user_queue(struct process_queue_manager *pqm,
+ struct kfd_dev *dev, struct queue **q,
+ struct queue_properties *q_properties,
+ struct file *f, unsigned int qid)
+@@ -251,7 +251,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ goto err_create_queue;
+ }
+
+- retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
++ retval = init_user_queue(pqm, dev, &q, properties, f, *qid);
+ if (retval != 0)
+ goto err_create_queue;
+ pqn->q = q;
+@@ -272,7 +272,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ goto err_create_queue;
+ }
+
+- retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
++ retval = init_user_queue(pqm, dev, &q, properties, f, *qid);
+ if (retval != 0)
+ goto err_create_queue;
+ pqn->q = q;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4423-drm-amd-powerplay-read-pcie-speed-width-info.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4423-drm-amd-powerplay-read-pcie-speed-width-info.patch
new file mode 100644
index 00000000..666b47d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4423-drm-amd-powerplay-read-pcie-speed-width-info.patch
@@ -0,0 +1,198 @@
+From e77465f75d251394f25f39784cec338ef492f443 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Tue, 12 Nov 2019 16:27:11 +0800
+Subject: [PATCH 4423/4736] drm/amd/powerplay: read pcie speed/width info
+
+sysfs interface to read pcie speed&width info on navi1x.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 50 ++++++++++++++++++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 3 ++
+ 4 files changed, 66 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index df5487fae20a..18da3b393f96 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ return ret;
+
+ if (adev->asic_type != CHIP_ARCTURUS) {
+- ret = smu_override_pcie_parameters(smu);
+- if (ret)
+- return ret;
+-
+ ret = smu_notify_display_change(smu);
+ if (ret)
+ return ret;
+@@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ return ret;
+ }
+
++ if (adev->asic_type != CHIP_ARCTURUS) {
++ ret = smu_override_pcie_parameters(smu);
++ if (ret)
++ return ret;
++ }
++
+ ret = smu_set_default_od_settings(smu, initialize);
+ if (ret)
+ return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 0269fac1a77b..e71445548c6f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -49,6 +49,8 @@
+
+ #define SMU11_TOOL_SIZE 0x19000
+
++#define MAX_PCIE_CONF 2
++
+ #define CLK_MAP(clk, index) \
+ [SMU_##clk] = {1, (index)}
+
+@@ -89,6 +91,11 @@ struct smu_11_0_dpm_table {
+ uint32_t max; /* MHz */
+ };
+
++struct smu_11_0_pcie_table {
++ uint8_t pcie_gen[MAX_PCIE_CONF];
++ uint8_t pcie_lane[MAX_PCIE_CONF];
++};
++
+ struct smu_11_0_dpm_tables {
+ struct smu_11_0_dpm_table soc_table;
+ struct smu_11_0_dpm_table gfx_table;
+@@ -101,6 +108,7 @@ struct smu_11_0_dpm_tables {
+ struct smu_11_0_dpm_table display_table;
+ struct smu_11_0_dpm_table phy_table;
+ struct smu_11_0_dpm_table fclk_table;
++ struct smu_11_0_pcie_table pcie_table;
+ };
+
+ struct smu_11_0_dpm_context {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 17ccdb74f4e2..6fd808312d4e 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -35,6 +35,7 @@
+ #include "navi10_ppt.h"
+ #include "smu_v11_0_pptable.h"
+ #include "smu_v11_0_ppsmc.h"
++#include "nbio/nbio_7_4_sh_mask.h"
+
+ #include "asic_reg/mp/mp_11_0_sh_mask.h"
+
+@@ -598,6 +599,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ PPTable_t *driver_ppt = NULL;
++ int i;
+
+ driver_ppt = table_context->driver_pptable;
+
+@@ -628,6 +630,11 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+ dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+
++ for (i = 0; i < MAX_PCIE_CONF; i++) {
++ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
++ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
++ }
++
+ return 0;
+ }
+
+@@ -709,6 +716,11 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ struct smu_table_context *table_context = &smu->smu_table;
+ od_table = (OverDriveTable_t *)table_context->overdrive_table;
+ od_settings = smu->od_settings;
++ uint32_t gen_speed, lane_width;
++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++ struct amdgpu_device *adev = smu->adev;
++ PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+@@ -759,6 +771,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+
+ }
+ break;
++ case SMU_PCIE:
++ gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
++ PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
++ >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
++ lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
++ PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
++ >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
++ for (i = 0; i < NUM_LINK_LEVELS; i++)
++ size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
++ pptable->LclkFreq[i],
++ (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
++ (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
++ "*" : "");
++ break;
+ case SMU_OD_SCLK:
+ if (!smu->od_enabled || !od_table || !od_settings)
+ break;
+@@ -1689,6 +1725,9 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ int ret, i;
+ uint32_t smu_pcie_arg;
+
++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++
+ for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ smu_pcie_arg = (i << 16) |
+ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
+@@ -1697,8 +1736,17 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_OverridePcieParameters,
+ smu_pcie_arg);
++
++ if (ret)
++ return ret;
++
++ if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
++ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
++ if (pptable->PcieLaneCount[i] > pcie_width_cap)
++ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
+ }
+- return ret;
++
++ return 0;
+ }
+
+ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index fd6dda1a67a1..ec03c7992f6d 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -35,6 +35,9 @@
+
+ #define NAVI10_VOLTAGE_SCALE (4)
+
++#define smnPCIE_LC_SPEED_CNTL 0x11140290
++#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4424-drm-amdgpu-vcn-finish-delay-work-before-release-reso.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4424-drm-amdgpu-vcn-finish-delay-work-before-release-reso.patch
new file mode 100644
index 00000000..d3af7de5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4424-drm-amdgpu-vcn-finish-delay-work-before-release-reso.patch
@@ -0,0 +1,34 @@
+From 7aa8812dc7edd5dacf23c87d175bd7508004163f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 11 Nov 2019 15:48:48 -0500
+Subject: [PATCH 4424/4736] drm/amdgpu/vcn: finish delay work before release
+ resources
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+flush/cancel delayed works before doing finalization
+to avoid concurrently requests.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 6b31410a5ff9..c72819d55502 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -192,6 +192,8 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+ {
+ int i, j;
+
++ cancel_delayed_work_sync(&adev->vcn.idle_work);
++
+ if (adev->vcn.indirect_sram) {
+ amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
+ &adev->vcn.dpg_sram_gpu_addr,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4425-drm-amd-display-remove-set-but-not-used-variable-bpc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4425-drm-amd-display-remove-set-but-not-used-variable-bpc.patch
new file mode 100644
index 00000000..1eed3575
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4425-drm-amd-display-remove-set-but-not-used-variable-bpc.patch
@@ -0,0 +1,58 @@
+From ba1a475025810b4ab5555f93eb3700db5f44dbdc Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Tue, 12 Nov 2019 10:10:50 +0800
+Subject: [PATCH 4425/4736] drm/amd/display: remove set but not used variable
+ 'bpc'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c: In function get_pbn_from_timing:
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:2364:11: warning:
+ variable bpc set but not used [-Wunused-but-set-variable]
+
+It is not used since commit e49f69363adf ("drm/amd/display: use
+proper formula to calculate bandwidth from timing"), this also
+remove get_color_depth(), which is only used here.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 ---------------
+ 1 file changed, 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index a014d47f0f37..7fab34ce0591 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2642,28 +2642,13 @@ static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
+ return dc_fixpt_div_int(mbytes_per_sec, 54);
+ }
+
+-static int get_color_depth(enum dc_color_depth color_depth)
+-{
+- switch (color_depth) {
+- case COLOR_DEPTH_666: return 6;
+- case COLOR_DEPTH_888: return 8;
+- case COLOR_DEPTH_101010: return 10;
+- case COLOR_DEPTH_121212: return 12;
+- case COLOR_DEPTH_141414: return 14;
+- case COLOR_DEPTH_161616: return 16;
+- default: return 0;
+- }
+-}
+-
+ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
+ {
+- uint32_t bpc;
+ uint64_t kbps;
+ struct fixed31_32 peak_kbps;
+ uint32_t numerator;
+ uint32_t denominator;
+
+- bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
+ kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
+
+ /*
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4426-drm-amdkfd-Implement-queue-priority-controls-for-gfx.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4426-drm-amdkfd-Implement-queue-priority-controls-for-gfx.patch
new file mode 100644
index 00000000..74923291
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4426-drm-amdkfd-Implement-queue-priority-controls-for-gfx.patch
@@ -0,0 +1,53 @@
+From ff581b5b65390250d5438649963bb79983377070 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 21:15:48 -0500
+Subject: [PATCH 4426/4736] drm/amdkfd: Implement queue priority controls for
+ gfx10
+
+Ported from gfx9.
+
+Change-Id: I388dc7c609ed724a6d600840f8e7317d9c2c877d
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index e2fb76247f47..79827017ea45 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -66,6 +66,12 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,
+ m->compute_static_thread_mgmt_se3);
+ }
+
++static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q)
++{
++ m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
++ m->cp_hqd_queue_priority = q->priority;
++}
++
+ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
+ struct queue_properties *q)
+ {
+@@ -109,9 +115,6 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
+ 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
+ 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
+
+- m->cp_hqd_pipe_priority = 1;
+- m->cp_hqd_queue_priority = 15;
+-
+ if (q->format == KFD_QUEUE_FORMAT_AQL) {
+ m->cp_hqd_aql_control =
+ 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
+@@ -208,6 +211,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
+ m->cp_hqd_ctx_save_control = 0;
+
+ update_cu_mask(mm, mqd, q);
++ set_priority(m, q);
+
+ q->is_active = (q->queue_size > 0 &&
+ q->queue_address != 0 &&
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4427-drm-amdkfd-Update-get_wave_state-for-GFX10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4427-drm-amdkfd-Update-get_wave_state-for-GFX10.patch
new file mode 100644
index 00000000..28b21ed9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4427-drm-amdkfd-Update-get_wave_state-for-GFX10.patch
@@ -0,0 +1,50 @@
+From 748b3ec8dd68824402757dac7c4e6d270c34da28 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 22:54:07 -0500
+Subject: [PATCH 4427/4736] drm/amdkfd: Update get_wave_state() for GFX10
+
+Given control stack is now in the userspace context save restore area
+on GFX10, the same as GFX8, it is not needed to copy it back to userspace.
+
+Change-Id: I063ddc3026eefa57713ec47b466a90f9bf9d49b8
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 14 +++++++++-----
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 79827017ea45..4cb7c226d4e0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -251,18 +251,22 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd,
+ {
+ struct v10_compute_mqd *m;
+
+- /* Control stack is located one page after MQD. */
+- void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
+-
+ m = get_mqd(mqd);
+
++ /* Control stack is written backwards, while workgroup context data
++ * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
++ * Current position is at m->cp_hqd_cntl_stack_offset and
++ * m->cp_hqd_wg_state_offset, respectively.
++ */
+ *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
+ m->cp_hqd_cntl_stack_offset;
+ *save_area_used_size = m->cp_hqd_wg_state_offset -
+ m->cp_hqd_cntl_stack_size;
+
+- if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size))
+- return -EFAULT;
++ /* Control stack is not copied to user mode for GFXv10 because
++ * it's part of the context save area that is already
++ * accessible to user mode
++ */
+
+ return 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4428-drm-amdkfd-Use-QUEUE_IS_ACTIVE-macro-in-mqd-v10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4428-drm-amdkfd-Use-QUEUE_IS_ACTIVE-macro-in-mqd-v10.patch
new file mode 100644
index 00000000..90a156d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4428-drm-amdkfd-Use-QUEUE_IS_ACTIVE-macro-in-mqd-v10.patch
@@ -0,0 +1,46 @@
+From a00e64b5598bf290b71fb6e6e72cbc71cfdcb6a1 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 21:52:55 -0500
+Subject: [PATCH 4428/4736] drm/amdkfd: Use QUEUE_IS_ACTIVE macro in mqd v10
+
+This is done for other GFX in commit bb2d2128a54c4. Port it to GFX10.
+
+Change-Id: I9e04872be3af0e90f5f6930226896b1ea545f3d9
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 4cb7c226d4e0..55f1cda095d1 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -213,10 +213,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
+ update_cu_mask(mm, mqd, q);
+ set_priority(m, q);
+
+- q->is_active = (q->queue_size > 0 &&
+- q->queue_address != 0 &&
+- q->queue_percent > 0 &&
+- !q->is_evicted);
++ q->is_active = QUEUE_IS_ACTIVE(*q);
+ }
+
+ static int destroy_mqd(struct mqd_manager *mm, void *mqd,
+@@ -348,11 +345,7 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
+ m->sdma_queue_id = q->sdma_queue_id;
+ m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
+
+-
+- q->is_active = (q->queue_size > 0 &&
+- q->queue_address != 0 &&
+- q->queue_percent > 0 &&
+- !q->is_evicted);
++ q->is_active = QUEUE_IS_ACTIVE(*q);
+ }
+
+ /*
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4429-drm-amdkfd-Stop-using-GFP_NOIO-explicitly-for-two-pl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4429-drm-amdkfd-Stop-using-GFP_NOIO-explicitly-for-two-pl.patch
new file mode 100644
index 00000000..395d11f1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4429-drm-amdkfd-Stop-using-GFP_NOIO-explicitly-for-two-pl.patch
@@ -0,0 +1,52 @@
+From 156064982ff08f441f5473b23eb760b5476d710f Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 22:06:37 -0500
+Subject: [PATCH 4429/4736] drm/amdkfd: Stop using GFP_NOIO explicitly for two
+ places
+
+Adapt the change from 1cd106ecfc1f04
+
+The change is:
+
+ drm/amdkfd: Stop using GFP_NOIO explicitly
+
+ This is no longer needed with the memalloc_nofs_save/restore in
+ dqm_lock/unlock
+
+Change-Id: I42450b2c149d2b1842be99a8f355c829a0079e7c
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 55f1cda095d1..65a03d1d79db 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -393,7 +393,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
+ return NULL;
+
+- mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
++ mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
+ if (!mqd)
+ return NULL;
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 785ceda52c94..822747377c28 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -135,7 +135,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
+ * instead of sub-allocation function.
+ */
+ if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
+- mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
++ mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
+ if (!mqd_mem_obj)
+ return NULL;
+ retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4430-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4430-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
new file mode 100644
index 00000000..312bfb11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4430-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
@@ -0,0 +1,75 @@
+From fd2dee5bbe8c1c3611b892ff64a76a82208e8e42 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:28 +0800
+Subject: [PATCH 4430/4736] drm/amdgpu: remove set but not used variable
+ 'mc_shared_chmap' from 'gfx_v6_0.c' and 'gfx_v7_0.c'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c: In function
+‘gfx_v6_0_constants_init’:
+drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:1579:6: warning: variable
+‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
+
+drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c: In function
+‘gfx_v7_0_gpu_early_init’:
+drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:4262:6: warning: variable
+‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
+
+Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8")
+Fixes: d93f3ca706b8 ("drm/amdgpu/gfx7: rework gpu_init()")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +--
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+index b4af1b55f852..954fe40eacd5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+@@ -1574,7 +1574,7 @@ static void gfx_v6_0_config_init(struct amdgpu_device *adev)
+ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
+ {
+ u32 gb_addr_config = 0;
+- u32 mc_shared_chmap, mc_arb_ramcfg;
++ u32 mc_arb_ramcfg;
+ u32 sx_debug_1;
+ u32 hdp_host_path_cntl;
+ u32 tmp;
+@@ -1676,7 +1676,6 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
+
+ WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
+
+- mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
+ adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
+ mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index c08f5c53dcb4..b8c2e9d9c711 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -4248,7 +4248,7 @@ static int gfx_v7_0_late_init(void *handle)
+ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
+ {
+ u32 gb_addr_config;
+- u32 mc_shared_chmap, mc_arb_ramcfg;
++ u32 mc_arb_ramcfg;
+ u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
+ u32 tmp;
+
+@@ -4325,7 +4325,6 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
+ break;
+ }
+
+- mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
+ adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
+ mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4431-drm-amdgpu-remove-set-but-not-used-variable-amdgpu_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4431-drm-amdgpu-remove-set-but-not-used-variable-amdgpu_c.patch
new file mode 100644
index 00000000..8b24dd14
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4431-drm-amdgpu-remove-set-but-not-used-variable-amdgpu_c.patch
@@ -0,0 +1,46 @@
+From f76a6a1084d78d3883c1342d5ba1c64213007217 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:29 +0800
+Subject: [PATCH 4431/4736] drm/amdgpu: remove set but not used variable
+ 'amdgpu_connector'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_display.c: In function
+‘amdgpu_display_crtc_scaling_mode_fixup’:
+drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:693:27: warning: variable
+‘amdgpu_connector’ set but not used [-Wunused-but-set-variable]
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index aad642e660b2..dcabe24e4dc3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -722,7 +722,6 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
+ struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+ struct amdgpu_encoder *amdgpu_encoder;
+ struct drm_connector *connector;
+- struct amdgpu_connector *amdgpu_connector;
+ u32 src_v = 1, dst_v = 1;
+ u32 src_h = 1, dst_h = 1;
+
+@@ -734,7 +733,6 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
+ continue;
+ amdgpu_encoder = to_amdgpu_encoder(encoder);
+ connector = amdgpu_get_connector_for_encoder(encoder);
+- amdgpu_connector = to_amdgpu_connector(connector);
+
+ /* set scaling */
+ if (amdgpu_encoder->rmx_type == RMX_OFF)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4432-drm-amdgpu-remove-set-but-not-used-variable-count.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4432-drm-amdgpu-remove-set-but-not-used-variable-count.patch
new file mode 100644
index 00000000..f62a8d1d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4432-drm-amdgpu-remove-set-but-not-used-variable-count.patch
@@ -0,0 +1,52 @@
+From b743e01c90ccb4a6f7c412d3e2bb19791266c3b9 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:30 +0800
+Subject: [PATCH 4432/4736] drm/amdgpu: remove set but not used variable
+ 'count'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdkfd/kfd_device.c: In function
+‘kgd2kfd_post_reset’:
+drivers/gpu/drm/amd/amdkfd/kfd_device.c:745:11: warning:
+variable ‘count’ set but not used [-Wunused-but-set-variable]
+
+'count' is never used, so can be removed. Thus 'atomic_dec_return'
+can be replaced as 'atomic_dec'
+
+Fixes: e42051d2133b ("drm/amdkfd: Implement GPU reset handlers in KFD")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index eb5eeba8792d..3827ace06f9b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -759,7 +759,7 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
+ if (kfd_flag_for_rv2)
+ return 0;
+
+- int ret, count;
++ int ret;
+
+ if (!kfd->init_complete)
+ return 0;
+@@ -767,7 +767,7 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
+ ret = kfd_resume(kfd);
+ if (ret)
+ return ret;
+- count = atomic_dec_return(&kfd_locked);
++ atomic_dec(&kfd_locked);
+
+ atomic_set(&kfd->sram_ecc_flag, 0);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4433-drm-amdgpu-remove-set-but-not-used-variable-invalid.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4433-drm-amdgpu-remove-set-but-not-used-variable-invalid.patch
new file mode 100644
index 00000000..294e404b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4433-drm-amdgpu-remove-set-but-not-used-variable-invalid.patch
@@ -0,0 +1,47 @@
+From fa007cd9d867f24f8d412ac40245f8ba7b2fbfdc Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:31 +0800
+Subject: [PATCH 4433/4736] drm/amdgpu: remove set but not used variable
+ 'invalid'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c: In function
+‘amdgpu_amdkfd_evict_userptr’:
+drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1665:6: warning:
+variable ‘invalid’ set but not used [-Wunused-but-set-variable]
+
+'invalid' is never used, so can be removed. Thus 'atomic_inc_return'
+can be replaced as 'atomic_inc'
+
+Fixes: 5ae0283e831a ("drm/amdgpu: Add userptr support for KFD")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 9ce17867fac7..083bd8fe8057 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -1926,10 +1926,10 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
+ return 0;
+
+ struct amdkfd_process_info *process_info = mem->process_info;
+- int invalid, evicted_bos;
++ int evicted_bos;
+ int r = 0;
+
+- invalid = atomic_inc_return(&mem->invalid);
++ atomic_inc(&mem->invalid);
+ evicted_bos = atomic_inc_return(&process_info->evicted_bos);
+ if (evicted_bos == 1) {
+ /* First eviction, stop the queues */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4434-drm-amd-powerplay-remove-set-but-not-used-variable-u.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4434-drm-amd-powerplay-remove-set-but-not-used-variable-u.patch
new file mode 100644
index 00000000..d880e5d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4434-drm-amd-powerplay-remove-set-but-not-used-variable-u.patch
@@ -0,0 +1,58 @@
+From 4084f72fb6be8940786655c472117d293f44d2db Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:34 +0800
+Subject: [PATCH 4434/4736] drm/amd/powerplay: remove set but not used variable
+ 'us_mvdd'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c: In
+function ‘vegam_populate_smc_acpi_level’:
+drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c:1117:11:
+warning: variable 'us_mvdd' set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Fixes: ac7822b0026f ("drm/amd/powerplay: add smumgr support for VEGAM (v2)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index ae18fbcb26fb..2068eb00d2f8 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -1114,7 +1114,6 @@ static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ SMIO_Pattern vol_level;
+ uint32_t mvdd;
+- uint16_t us_mvdd;
+
+ table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
+
+@@ -1168,17 +1167,6 @@ static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ "in Clock Dependency Table",
+ );
+
+- us_mvdd = 0;
+- if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
+- (data->mclk_dpm_key_disabled))
+- us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
+- else {
+- if (!vegam_populate_mvdd_value(hwmgr,
+- data->dpm_table.mclk_table.dpm_levels[0].value,
+- &vol_level))
+- us_mvdd = vol_level.Voltage;
+- }
+-
+ if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
+ table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
+ else
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4435-drm-amdkfd-Merge-CIK-kernel-queue-functions-into-VI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4435-drm-amdkfd-Merge-CIK-kernel-queue-functions-into-VI.patch
new file mode 100644
index 00000000..67599335
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4435-drm-amdkfd-Merge-CIK-kernel-queue-functions-into-VI.patch
@@ -0,0 +1,158 @@
+From 51ef2756d9b88b590d80b2fc552a7ea54e65aaa4 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 7 Nov 2019 23:18:04 -0500
+Subject: [PATCH 4435/4736] drm/amdkfd: Merge CIK kernel queue functions into
+ VI
+
+The only difference that CIK kernel queue functions are different from
+VI is avoid allocating eop_mem. We can achieve that by using a if
+condition.
+
+Change-Id: Iea9cbc82f603ff008a906c5ee32325ddcd02d963
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 7 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 1 -
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c | 53 -------------------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 7 +++
+ 5 files changed, 9 insertions(+), 60 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index c2c125156a62..a34a4a65970f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -38,7 +38,6 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \
+ $(AMDKFD_PATH)/kfd_mqd_manager_v9.o \
+ $(AMDKFD_PATH)/kfd_mqd_manager_v10.o \
+ $(AMDKFD_PATH)/kfd_kernel_queue.o \
+- $(AMDKFD_PATH)/kfd_kernel_queue_cik.o \
+ $(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
+ $(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
+ $(AMDKFD_PATH)/kfd_packet_manager.o \
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index 04041bab42a8..f3a08145d067 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -346,6 +346,8 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ kq->ops.rollback_packet = rollback_packet;
+
+ switch (dev->device_info->asic_family) {
++ case CHIP_KAVERI:
++ case CHIP_HAWAII:
+ case CHIP_CARRIZO:
+ case CHIP_TONGA:
+ case CHIP_FIJI:
+@@ -356,11 +358,6 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ kernel_queue_init_vi(&kq->ops_asic_specific);
+ break;
+
+- case CHIP_KAVERI:
+- case CHIP_HAWAII:
+- kernel_queue_init_cik(&kq->ops_asic_specific);
+- break;
+-
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index 384d7a37b343..b22ff0fb40fe 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -109,7 +109,6 @@ struct kernel_queue {
+ struct list_head list;
+ };
+
+-void kernel_queue_init_cik(struct kernel_queue_ops *ops);
+ void kernel_queue_init_vi(struct kernel_queue_ops *ops);
+ void kernel_queue_init_v9(struct kernel_queue_ops *ops);
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
+deleted file mode 100644
+index 19e54acb4125..000000000000
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
++++ /dev/null
+@@ -1,53 +0,0 @@
+-/*
+- * Copyright 2014 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- */
+-
+-#include "kfd_kernel_queue.h"
+-
+-static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_cik(struct kernel_queue *kq);
+-static void submit_packet_cik(struct kernel_queue *kq);
+-
+-void kernel_queue_init_cik(struct kernel_queue_ops *ops)
+-{
+- ops->initialize = initialize_cik;
+- ops->uninitialize = uninitialize_cik;
+- ops->submit_packet = submit_packet_cik;
+-}
+-
+-static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size)
+-{
+- return true;
+-}
+-
+-static void uninitialize_cik(struct kernel_queue *kq)
+-{
+-}
+-
+-static void submit_packet_cik(struct kernel_queue *kq)
+-{
+- *kq->wptr_kernel = kq->pending_wptr;
+- write_kernel_doorbell(kq->queue->properties.doorbell_ptr,
+- kq->pending_wptr);
+-}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+index 7047f4c5a7dc..9b0380d91bfb 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+@@ -43,6 +43,10 @@ static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+ {
+ int retval;
+
++ /*For CIK family asics, kq->eop_mem is not needed */
++ if (dev->device_info->asic_family <= CHIP_MULLINS)
++ return true;
++
+ retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+ if (retval != 0)
+ return false;
+@@ -57,6 +61,9 @@ static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+
+ static void uninitialize_vi(struct kernel_queue *kq)
+ {
++ /* For CIK family asics, kq->eop_mem is Null, kfd_gtt_sa_free()
++ * is able to handle NULL properly.
++ */
+ kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4436-drm-amdkfd-Eliminate-ops_asic_specific-in-kernel-que.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4436-drm-amdkfd-Eliminate-ops_asic_specific-in-kernel-que.patch
new file mode 100644
index 00000000..55d6d9ff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4436-drm-amdkfd-Eliminate-ops_asic_specific-in-kernel-que.patch
@@ -0,0 +1,248 @@
+From 2aaa285d69d0e973d7da89cae6d77232cae25267 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 7 Nov 2019 23:59:43 -0500
+Subject: [PATCH 4436/4736] drm/amdkfd: Eliminate ops_asic_specific in kernel
+ queue
+
+The ops_asic_specific function pointers are actually quite generic after
+using a simple if condition. Eliminate it by code refactoring.
+
+Change-Id: Icb891289cca31acdbe2d2eea76a426f1738b9c08
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 63 ++++++++-----------
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 4 --
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 36 -----------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 48 --------------
+ 4 files changed, 26 insertions(+), 125 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index f3a08145d067..ca7e8d299c8b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -87,9 +87,17 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ kq->pq_kernel_addr = kq->pq->cpu_ptr;
+ kq->pq_gpu_addr = kq->pq->gpu_addr;
+
+- retval = kq->ops_asic_specific.initialize(kq, dev, type, queue_size);
+- if (!retval)
+- goto err_eop_allocate_vidmem;
++ /* For CIK family asics, kq->eop_mem is not needed */
++ if (dev->device_info->asic_family > CHIP_HAWAII) {
++ retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
++ if (retval != 0)
++ goto err_eop_allocate_vidmem;
++
++ kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
++ kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
++
++ memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
++ }
+
+ retval = kfd_gtt_sa_allocate(dev, sizeof(*kq->rptr_kernel),
+ &kq->rptr_mem);
+@@ -201,7 +209,12 @@ static void uninitialize(struct kernel_queue *kq)
+
+ kfd_gtt_sa_free(kq->dev, kq->rptr_mem);
+ kfd_gtt_sa_free(kq->dev, kq->wptr_mem);
+- kq->ops_asic_specific.uninitialize(kq);
++
++ /* For CIK family asics, kq->eop_mem is Null, kfd_gtt_sa_free()
++ * is able to handle NULL properly.
++ */
++ kfd_gtt_sa_free(kq->dev, kq->eop_mem);
++
+ kfd_gtt_sa_free(kq->dev, kq->pq);
+ kfd_release_kernel_doorbell(kq->dev,
+ kq->queue->properties.doorbell_ptr);
+@@ -314,8 +327,15 @@ static void submit_packet(struct kernel_queue *kq)
+ }
+ pr_debug("\n");
+ #endif
+-
+- kq->ops_asic_specific.submit_packet(kq);
++ if (kq->dev->device_info->doorbell_size == 8) {
++ *kq->wptr64_kernel = kq->pending_wptr64;
++ write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
++ kq->pending_wptr64);
++ } else {
++ *kq->wptr_kernel = kq->pending_wptr;
++ write_kernel_doorbell(kq->queue->properties.doorbell_ptr,
++ kq->pending_wptr);
++ }
+ }
+
+ static void rollback_packet(struct kernel_queue *kq)
+@@ -345,42 +365,11 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ kq->ops.submit_packet = submit_packet;
+ kq->ops.rollback_packet = rollback_packet;
+
+- switch (dev->device_info->asic_family) {
+- case CHIP_KAVERI:
+- case CHIP_HAWAII:
+- case CHIP_CARRIZO:
+- case CHIP_TONGA:
+- case CHIP_FIJI:
+- case CHIP_POLARIS10:
+- case CHIP_POLARIS11:
+- case CHIP_POLARIS12:
+- case CHIP_VEGAM:
+- kernel_queue_init_vi(&kq->ops_asic_specific);
+- break;
+-
+- case CHIP_VEGA10:
+- case CHIP_VEGA12:
+- case CHIP_VEGA20:
+- case CHIP_RAVEN:
+- case CHIP_RENOIR:
+- case CHIP_ARCTURUS:
+- case CHIP_NAVI10:
+- case CHIP_NAVI12:
+- case CHIP_NAVI14:
+- kernel_queue_init_v9(&kq->ops_asic_specific);
+- break;
+- default:
+- WARN(1, "Unexpected ASIC family %u",
+- dev->device_info->asic_family);
+- goto out_free;
+- }
+-
+ if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
+ return kq;
+
+ pr_err("Failed to init kernel queue\n");
+
+-out_free:
+ kfree(kq);
+ return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index b22ff0fb40fe..852de7466cc4 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -76,7 +76,6 @@ struct kernel_queue_ops {
+
+ struct kernel_queue {
+ struct kernel_queue_ops ops;
+- struct kernel_queue_ops ops_asic_specific;
+
+ /* data */
+ struct kfd_dev *dev;
+@@ -109,7 +108,4 @@ struct kernel_queue {
+ struct list_head list;
+ };
+
+-void kernel_queue_init_vi(struct kernel_queue_ops *ops);
+-void kernel_queue_init_v9(struct kernel_queue_ops *ops);
+-
+ #endif /* KFD_KERNEL_QUEUE_H_ */
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index a3d0b4cf16c6..11c2d85fd614 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -27,42 +27,6 @@
+ #include "kfd_pm4_opcodes.h"
+ #include "gc/gc_10_1_0_sh_mask.h"
+
+-static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size)
+-{
+- int retval;
+-
+- retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+- if (retval)
+- return false;
+-
+- kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
+- kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
+-
+- memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+-
+- return true;
+-}
+-
+-static void uninitialize_v9(struct kernel_queue *kq)
+-{
+- kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+-}
+-
+-static void submit_packet_v9(struct kernel_queue *kq)
+-{
+- *kq->wptr64_kernel = kq->pending_wptr64;
+- write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
+- kq->pending_wptr64);
+-}
+-
+-void kernel_queue_init_v9(struct kernel_queue_ops *ops)
+-{
+- ops->initialize = initialize_v9;
+- ops->uninitialize = uninitialize_v9;
+- ops->submit_packet = submit_packet_v9;
+-}
+-
+ static int pm_map_process_v9(struct packet_manager *pm,
+ uint32_t *buffer, struct qcm_process_device *qpd)
+ {
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+index 9b0380d91bfb..faf0bae8223b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+@@ -26,54 +26,6 @@
+ #include "kfd_pm4_headers_vi.h"
+ #include "kfd_pm4_opcodes.h"
+
+-static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_vi(struct kernel_queue *kq);
+-static void submit_packet_vi(struct kernel_queue *kq);
+-
+-void kernel_queue_init_vi(struct kernel_queue_ops *ops)
+-{
+- ops->initialize = initialize_vi;
+- ops->uninitialize = uninitialize_vi;
+- ops->submit_packet = submit_packet_vi;
+-}
+-
+-static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size)
+-{
+- int retval;
+-
+- /*For CIK family asics, kq->eop_mem is not needed */
+- if (dev->device_info->asic_family <= CHIP_MULLINS)
+- return true;
+-
+- retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+- if (retval != 0)
+- return false;
+-
+- kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
+- kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
+-
+- memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+-
+- return true;
+-}
+-
+-static void uninitialize_vi(struct kernel_queue *kq)
+-{
+- /* For CIK family asics, kq->eop_mem is Null, kfd_gtt_sa_free()
+- * is able to handle NULL properly.
+- */
+- kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+-}
+-
+-static void submit_packet_vi(struct kernel_queue *kq)
+-{
+- *kq->wptr_kernel = kq->pending_wptr;
+- write_kernel_doorbell(kq->queue->properties.doorbell_ptr,
+- kq->pending_wptr);
+-}
+-
+ unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size)
+ {
+ union PM4_MES_TYPE_3_HEADER header;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4437-drm-amdkfd-Rename-kfd_kernel_queue_-.c-to-kfd_packet.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4437-drm-amdkfd-Rename-kfd_kernel_queue_-.c-to-kfd_packet.patch
new file mode 100644
index 00000000..ac106e1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4437-drm-amdkfd-Rename-kfd_kernel_queue_-.c-to-kfd_packet.patch
@@ -0,0 +1,48 @@
+From 257a195bdb74fd055882e998963f155812ac2d3a Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 13 Nov 2019 17:03:11 -0500
+Subject: [PATCH 4437/4736] drm/amdkfd: Rename kfd_kernel_queue_*.c to
+ kfd_packet_manager_*.c
+
+After the recent cleanup, the functionalities provided by the previous
+kfd_kernel_queue_*.c are actually all packet manager related. So rename
+them to reflect that.
+
+Change-Id: I6544ccb38da827c747544c0787aa949df20edbb0
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile | 4 ++--
+ .../amdkfd/{kfd_kernel_queue_v9.c => kfd_packet_manager_v9.c} | 0
+ .../amdkfd/{kfd_kernel_queue_vi.c => kfd_packet_manager_vi.c} | 0
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+ rename drivers/gpu/drm/amd/amdkfd/{kfd_kernel_queue_v9.c => kfd_packet_manager_v9.c} (100%)
+ rename drivers/gpu/drm/amd/amdkfd/{kfd_kernel_queue_vi.c => kfd_packet_manager_vi.c} (100%)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index a34a4a65970f..a09e4a5d754f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -38,9 +38,9 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \
+ $(AMDKFD_PATH)/kfd_mqd_manager_v9.o \
+ $(AMDKFD_PATH)/kfd_mqd_manager_v10.o \
+ $(AMDKFD_PATH)/kfd_kernel_queue.o \
+- $(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
+- $(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
+ $(AMDKFD_PATH)/kfd_packet_manager.o \
++ $(AMDKFD_PATH)/kfd_packet_manager_vi.o \
++ $(AMDKFD_PATH)/kfd_packet_manager_v9.o \
+ $(AMDKFD_PATH)/kfd_process_queue_manager.o \
+ $(AMDKFD_PATH)/kfd_device_queue_manager.o \
+ $(AMDKFD_PATH)/kfd_device_queue_manager_cik.o \
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+similarity index 100%
+rename from drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+rename to drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c
+similarity index 100%
+rename from drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+rename to drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4438-drm-amdgpu-powerplay-properly-set-PP_GFXOFF_MASK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4438-drm-amdgpu-powerplay-properly-set-PP_GFXOFF_MASK.patch
new file mode 100644
index 00000000..cae549dc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4438-drm-amdgpu-powerplay-properly-set-PP_GFXOFF_MASK.patch
@@ -0,0 +1,91 @@
+From e801571aa584fe7f275becec8aee71ace73288ed Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 13 Nov 2019 11:08:35 -0500
+Subject: [PATCH 4438/4736] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
+
+So that the setting reflects what the hw supports. This will
+be used in a subsequent patch so needs to be correct.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
+ drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++++++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 18da3b393f96..f4bb804acbeb 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -719,6 +719,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ vega20_set_ppt_funcs(smu);
+ break;
+ case CHIP_NAVI10:
+@@ -727,6 +728,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ navi10_set_ppt_funcs(smu);
+ break;
+ case CHIP_ARCTURUS:
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ arcturus_set_ppt_funcs(smu);
+ /* OD is not supported on Arcturus */
+ smu->od_enabled =false;
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+index e8d4292bc4f0..72f2b09195dc 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+@@ -81,6 +81,8 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
+
+ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ {
++ struct amdgpu_device *adev = hwmgr->adev;
++
+ if (!hwmgr)
+ return -EINVAL;
+
+@@ -96,6 +98,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+
+ switch (hwmgr->chip_family) {
+ case AMDGPU_FAMILY_CI:
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ hwmgr->smumgr_funcs = &ci_smu_funcs;
+ ci_set_asic_special_caps(hwmgr);
+ hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
+@@ -106,12 +109,14 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ smu7_init_function_pointers(hwmgr);
+ break;
+ case AMDGPU_FAMILY_CZ:
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ hwmgr->od_enabled = false;
+ hwmgr->smumgr_funcs = &smu8_smu_funcs;
+ hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ smu8_init_function_pointers(hwmgr);
+ break;
+ case AMDGPU_FAMILY_VI:
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ switch (hwmgr->chip_id) {
+ case CHIP_TOPAZ:
+@@ -153,6 +158,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ case AMDGPU_FAMILY_AI:
+ switch (hwmgr->chip_id) {
+ case CHIP_VEGA10:
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ hwmgr->smumgr_funcs = &vega10_smu_funcs;
+ vega10_hwmgr_init(hwmgr);
+@@ -162,6 +168,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ vega12_hwmgr_init(hwmgr);
+ break;
+ case CHIP_VEGA20:
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ hwmgr->smumgr_funcs = &vega20_smu_funcs;
+ vega20_hwmgr_init(hwmgr);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4439-drm-amdgpu-don-t-read-registers-if-gfxoff-is-enabled.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4439-drm-amdgpu-don-t-read-registers-if-gfxoff-is-enabled.patch
new file mode 100644
index 00000000..1aba1752
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4439-drm-amdgpu-don-t-read-registers-if-gfxoff-is-enabled.patch
@@ -0,0 +1,126 @@
+From 3aaf57ff28015d3d07f80b8c1540d75b2d20f288 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 12 Nov 2019 09:46:54 -0500
+Subject: [PATCH 4439/4736] drm/amdgpu: don't read registers if gfxoff is
+ enabled (v2)
+
+When gfxoff is enabled, accessing gfx registers via MMIO
+can lead to a hang.
+
+v2: return cached registers properly.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 27 ++++++++++++++++----------
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++++++++------------
+ 2 files changed, 36 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index b33da33214eb..be761785b2a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -200,17 +200,25 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
+ return val;
+ }
+
+-static uint32_t nv_get_register_value(struct amdgpu_device *adev,
++static int nv_get_register_value(struct amdgpu_device *adev,
+ bool indexed, u32 se_num,
+- u32 sh_num, u32 reg_offset)
++ u32 sh_num, u32 reg_offset,
++ u32 *value)
+ {
+ if (indexed) {
+- return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
++ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++ return -EINVAL;
++ *value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ } else {
+- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
+- return adev->gfx.config.gb_addr_config;
+- return RREG32(reg_offset);
++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
++ *value = adev->gfx.config.gb_addr_config;
++ } else {
++ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++ return -EINVAL;
++ *value = RREG32(reg_offset);
++ }
+ }
++ return 0;
+ }
+
+ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -226,10 +234,9 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+ (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
+ continue;
+
+- *value = nv_get_register_value(adev,
+- nv_allowed_read_registers[i].grbm_indexed,
+- se_num, sh_num, reg_offset);
+- return 0;
++ return nv_get_register_value(adev,
++ nv_allowed_read_registers[i].grbm_indexed,
++ se_num, sh_num, reg_offset, value);
+ }
+ return -EINVAL;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index e12cdbdd9aed..836a34c10db2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -362,19 +362,27 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
+ return val;
+ }
+
+-static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
++static int soc15_get_register_value(struct amdgpu_device *adev,
+ bool indexed, u32 se_num,
+- u32 sh_num, u32 reg_offset)
++ u32 sh_num, u32 reg_offset,
++ u32 *value)
+ {
+ if (indexed) {
+- return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
++ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++ return -EINVAL;
++ *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ } else {
+- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
+- return adev->gfx.config.gb_addr_config;
+- else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
+- return adev->gfx.config.db_debug2;
+- return RREG32(reg_offset);
++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
++ *value = adev->gfx.config.gb_addr_config;
++ } else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
++ *value = adev->gfx.config.db_debug2;
++ } else {
++ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++ return -EINVAL;
++ *value = RREG32(reg_offset);
++ }
+ }
++ return 0;
+ }
+
+ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -390,10 +398,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+ + en->reg_offset))
+ continue;
+
+- *value = soc15_get_register_value(adev,
+- soc15_allowed_read_registers[i].grbm_indexed,
+- se_num, sh_num, reg_offset);
+- return 0;
++ return soc15_get_register_value(adev,
++ soc15_allowed_read_registers[i].grbm_indexed,
++ se_num, sh_num, reg_offset, value);
+ }
+ return -EINVAL;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4440-drm-amdgpu-enable-ras-capablity-check-on-arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4440-drm-amdgpu-enable-ras-capablity-check-on-arcturus.patch
new file mode 100644
index 00000000..e64d58fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4440-drm-amdgpu-enable-ras-capablity-check-on-arcturus.patch
@@ -0,0 +1,31 @@
+From feda5cc8a0337d8922decc724ccad100cc3a1294 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 13 Nov 2019 22:24:12 +0800
+Subject: [PATCH 4440/4736] drm/amdgpu: enable ras capablity check on arcturus
+
+check hw ras capablity via atomfirmware
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: John Clements <John.Clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 399617932427..bbd4fd5d7850 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1685,7 +1685,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
+ *supported = 0;
+
+ if (amdgpu_sriov_vf(adev) ||
+- adev->asic_type != CHIP_VEGA20)
++ (adev->asic_type != CHIP_VEGA20 &&
++ adev->asic_type != CHIP_ARCTURUS))
+ return;
+
+ if (adev->is_atom_fw &&
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4441-drm-amdgpu-init-umc-functions-for-arcturus-umc-ras.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4441-drm-amdgpu-init-umc-functions-for-arcturus-umc-ras.patch
new file mode 100644
index 00000000..651dd29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4441-drm-amdgpu-init-umc-functions-for-arcturus-umc-ras.patch
@@ -0,0 +1,37 @@
+From 26767064660a45a4b91a1eed997a360bb6fe723e Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 13 Nov 2019 22:26:22 +0800
+Subject: [PATCH 4441/4736] drm/amdgpu: init umc functions for arcturus umc ras
+
+reuse vg20 umc functions for arcturus umc ras
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: John Clements <John.Clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 6ddb8bdf77cc..db4582925b8d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -635,6 +635,7 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ adev->umc.funcs = &umc_v6_0_funcs;
+ break;
+ case CHIP_VEGA20:
++ case CHIP_ARCTURUS:
+ adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
+ adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
+ adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
+@@ -748,6 +749,7 @@ static int gmc_v9_0_late_init(void *handle)
+ switch (adev->asic_type) {
+ case CHIP_VEGA10:
+ case CHIP_VEGA20:
++ case CHIP_ARCTURUS:
+ r = amdgpu_atomfirmware_mem_ecc_supported(adev);
+ if (!r) {
+ DRM_INFO("ECC is not present.\n");
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4442-drm-amdgpu-gfx10-fix-mqd-backup-restore-for-gfx-ring.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4442-drm-amdgpu-gfx10-fix-mqd-backup-restore-for-gfx-ring.patch
new file mode 100644
index 00000000..dbcee19c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4442-drm-amdgpu-gfx10-fix-mqd-backup-restore-for-gfx-ring.patch
@@ -0,0 +1,61 @@
+From fcba8e7d0b5d92ad1455239d3f4f1ca4f973f888 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 29 Oct 2019 16:59:09 +0800
+Subject: [PATCH 4442/4736] drm/amdgpu/gfx10: fix mqd backup/restore for gfx
+ rings
+
+1. no need to allocate an extra member for 'mqd_backup' array
+2. backup/restore mqd to/from the correct 'mqd_backup' array slot
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +++++----
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index a74ecd449775..0ae0a2715b0d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -225,7 +225,7 @@ struct amdgpu_me {
+ uint32_t num_me;
+ uint32_t num_pipe_per_me;
+ uint32_t num_queue_per_pipe;
+- void *mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
++ void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
+
+ /* These are the resources for which amdgpu takes ownership */
+ DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index e4b4f4b09329..9274bd4b6c68 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3118,6 +3118,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
+ {
+ struct amdgpu_device *adev = ring->adev;
+ struct v10_gfx_mqd *mqd = ring->mqd_ptr;
++ int mqd_idx = ring - &adev->gfx.gfx_ring[0];
+
+ if (!adev->in_gpu_reset && !adev->in_suspend) {
+ memset((void *)mqd, 0, sizeof(*mqd));
+@@ -3129,12 +3130,12 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
+ #endif
+ nv_grbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
+- if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
+- memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd));
++ if (adev->gfx.me.mqd_backup[mqd_idx])
++ memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
+ } else if (adev->in_gpu_reset) {
+ /* reset mqd with the backup copy */
+- if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
+- memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
++ if (adev->gfx.me.mqd_backup[mqd_idx])
++ memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
+ /* reset the ring */
+ ring->wptr = 0;
+ adev->wb.wb[ring->wptr_offs] = 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4443-drm-amdgpu-add-JPEG-HW-IP-and-SW-structures.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4443-drm-amdgpu-add-JPEG-HW-IP-and-SW-structures.patch
new file mode 100644
index 00000000..8e58ca5f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4443-drm-amdgpu-add-JPEG-HW-IP-and-SW-structures.patch
@@ -0,0 +1,100 @@
+From cec3b16f457e14003559707bd0bb5c2f40953630 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:00:24 -0500
+Subject: [PATCH 4443/4736] drm/amdgpu: add JPEG HW IP and SW structures
+
+It will be used for JPEG IP 1.0, 2.0, 2.5 and later.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 46 ++++++++++++++++++++++++
+ 2 files changed, 51 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 715739799383..9915f0472611 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -70,6 +70,7 @@
+ #include "amdgpu_uvd.h"
+ #include "amdgpu_vce.h"
+ #include "amdgpu_vcn.h"
++#include "amdgpu_jpeg.h"
+ #include "amdgpu_mn.h"
+ #include "amdgpu_gmc.h"
+ #include "amdgpu_gfx.h"
+@@ -724,6 +725,7 @@ enum amd_hw_ip_block_type {
+ MP1_HWIP,
+ UVD_HWIP,
+ VCN_HWIP = UVD_HWIP,
++ JPEG_HWIP = VCN_HWIP,
+ VCE_HWIP,
+ DF_HWIP,
+ DCE_HWIP,
+@@ -944,6 +946,9 @@ struct amdgpu_device {
+ /* vcn */
+ struct amdgpu_vcn vcn;
+
++ /* jpeg */
++ struct amdgpu_jpeg jpeg;
++
+ /* firmwares */
+ struct amdgpu_firmware firmware;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+new file mode 100644
+index 000000000000..36e2b7340c97
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -0,0 +1,46 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_JPEG_H__
++#define __AMDGPU_JPEG_H__
++
++#define AMDGPU_MAX_JPEG_INSTANCES 2
++
++struct amdgpu_jpeg_reg{
++ unsigned jpeg_pitch;
++};
++
++struct amdgpu_jpeg_inst {
++ struct amdgpu_ring ring_dec;
++ struct amdgpu_irq_src irq;
++ struct amdgpu_jpeg_reg external;
++};
++
++struct amdgpu_jpeg {
++ uint8_t num_jpeg_inst;
++ struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
++ struct amdgpu_jpeg_reg internal;
++ unsigned harvest_config;
++};
++
++#endif /*__AMDGPU_JPEG_H__*/
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4444-drm-amdgpu-add-amdgpu_jpeg-and-JPEG-tests.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4444-drm-amdgpu-add-amdgpu_jpeg-and-JPEG-tests.patch
new file mode 100644
index 00000000..5e0114d3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4444-drm-amdgpu-add-amdgpu_jpeg-and-JPEG-tests.patch
@@ -0,0 +1,194 @@
+From c444d485db6eb0a248933b19d714d86030a2183e Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:07:56 -0500
+Subject: [PATCH 4444/4736] drm/amdgpu: add amdgpu_jpeg and JPEG tests
+
+It will be used for all versions of JPEG eventually. Previous
+JPEG tests will be removed later since they are still used by
+JPEG2.x.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 5 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 135 +++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 3 +
+ 3 files changed, 141 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index d2fa7313c876..e73f71bd99c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -148,12 +148,13 @@ amdgpu-y += \
+ vce_v3_0.o \
+ vce_v4_0.o
+
+-# add VCN block
++# add VCN and JPEG block
+ amdgpu-y += \
+ amdgpu_vcn.o \
+ vcn_v1_0.o \
+ vcn_v2_0.o \
+- vcn_v2_5.o
++ vcn_v2_5.o \
++ amdgpu_jpeg.o
+
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+new file mode 100644
+index 000000000000..d9a547d4d3b2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+@@ -0,0 +1,135 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "soc15d.h"
++#include "soc15_common.h"
++
++int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++ uint32_t tmp = 0;
++ unsigned i;
++ int r;
++
++ WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
++ r = amdgpu_ring_alloc(ring, 3);
++ if (r)
++ return r;
++
++ amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
++ amdgpu_ring_write(ring, 0xDEADBEEF);
++ amdgpu_ring_commit(ring);
++
++ for (i = 0; i < adev->usec_timeout; i++) {
++ tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
++ if (tmp == 0xDEADBEEF)
++ break;
++ udelay(1);
++ }
++
++ if (i >= adev->usec_timeout)
++ r = -ETIMEDOUT;
++
++ return r;
++}
++
++static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
++ struct dma_fence **fence)
++{
++ struct amdgpu_device *adev = ring->adev;
++ struct amdgpu_job *job;
++ struct amdgpu_ib *ib;
++ struct dma_fence *f = NULL;
++ const unsigned ib_size_dw = 16;
++ int i, r;
++
++ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
++ if (r)
++ return r;
++
++ ib = &job->ibs[0];
++
++ ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
++ ib->ptr[1] = 0xDEADBEEF;
++ for (i = 2; i < 16; i += 2) {
++ ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
++ ib->ptr[i+1] = 0;
++ }
++ ib->length_dw = 16;
++
++ r = amdgpu_job_submit_direct(job, ring, &f);
++ if (r)
++ goto err;
++
++ if (fence)
++ *fence = dma_fence_get(f);
++ dma_fence_put(f);
++
++ return 0;
++
++err:
++ amdgpu_job_free(job);
++ return r;
++}
++
++int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
++{
++ struct amdgpu_device *adev = ring->adev;
++ uint32_t tmp = 0;
++ unsigned i;
++ struct dma_fence *fence = NULL;
++ long r = 0;
++
++ r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
++ if (r)
++ goto error;
++
++ r = dma_fence_wait_timeout(fence, false, timeout);
++ if (r == 0) {
++ r = -ETIMEDOUT;
++ goto error;
++ } else if (r < 0) {
++ goto error;
++ } else {
++ r = 0;
++ }
++
++ for (i = 0; i < adev->usec_timeout; i++) {
++ tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
++ if (tmp == 0xDEADBEEF)
++ break;
++ udelay(1);
++ }
++
++ if (i >= adev->usec_timeout)
++ r = -ETIMEDOUT;
++
++ dma_fence_put(fence);
++error:
++ return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+index 36e2b7340c97..a8d988c25f45 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -43,4 +43,7 @@ struct amdgpu_jpeg {
+ unsigned harvest_config;
+ };
+
++int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
++int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
++
+ #endif /*__AMDGPU_JPEG_H__*/
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4445-drm-amdgpu-separate-JPEG1.0-code-out-from-VCN1.0.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4445-drm-amdgpu-separate-JPEG1.0-code-out-from-VCN1.0.patch
new file mode 100644
index 00000000..0cf4e9ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4445-drm-amdgpu-separate-JPEG1.0-code-out-from-VCN1.0.patch
@@ -0,0 +1,1252 @@
+From 61fef67dd52e80e895970d745aff4fdec783ad80 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:17:06 -0500
+Subject: [PATCH 4445/4736] drm/amdgpu: separate JPEG1.0 code out from VCN1.0
+
+For VCN1.0, the separation is just in code wise, JPEG1.0 HW is still
+included in the VCN1.0 HW.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
+ drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 584 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h | 32 ++
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +-------------------
+ 4 files changed, 630 insertions(+), 470 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index e73f71bd99c2..62ef3d7955d9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -154,7 +154,8 @@ amdgpu-y += \
+ vcn_v1_0.o \
+ vcn_v2_0.o \
+ vcn_v2_5.o \
+- amdgpu_jpeg.o
++ amdgpu_jpeg.o \
++ jpeg_v1_0.o
+
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+new file mode 100644
+index 000000000000..553506df077d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+@@ -0,0 +1,584 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "soc15.h"
++#include "soc15d.h"
++
++#include "vcn/vcn_1_0_offset.h"
++#include "vcn/vcn_1_0_sh_mask.h"
++
++static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
++static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
++
++static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
++{
++ struct amdgpu_device *adev = ring->adev;
++ ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
++ if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++ ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++ ring->ring[(*ptr)++] = 0;
++ ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
++ } else {
++ ring->ring[(*ptr)++] = reg_offset;
++ ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
++ }
++ ring->ring[(*ptr)++] = val;
++}
++
++static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ uint32_t reg, reg_offset, val, mask, i;
++
++ // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
++ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
++ reg_offset = (reg << 2);
++ val = lower_32_bits(ring->gpu_addr);
++ jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++ // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
++ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
++ reg_offset = (reg << 2);
++ val = upper_32_bits(ring->gpu_addr);
++ jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++ // 3rd to 5th: issue MEM_READ commands
++ for (i = 0; i <= 2; i++) {
++ ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
++ ring->ring[ptr++] = 0;
++ }
++
++ // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
++ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
++ reg_offset = (reg << 2);
++ val = 0x13;
++ jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++ // 7th: program mmUVD_JRBC_RB_REF_DATA
++ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA);
++ reg_offset = (reg << 2);
++ val = 0x1;
++ jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++ // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
++ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
++ reg_offset = (reg << 2);
++ val = 0x1;
++ mask = 0x1;
++
++ ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
++ ring->ring[ptr++] = 0x01400200;
++ ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
++ ring->ring[ptr++] = val;
++ ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
++ if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++ ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++ ring->ring[ptr++] = 0;
++ ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
++ } else {
++ ring->ring[ptr++] = reg_offset;
++ ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
++ }
++ ring->ring[ptr++] = mask;
++
++ //9th to 21st: insert no-op
++ for (i = 0; i <= 12; i++) {
++ ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
++ ring->ring[ptr++] = 0;
++ }
++
++ //22nd: reset mmUVD_JRBC_RB_RPTR
++ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR);
++ reg_offset = (reg << 2);
++ val = 0;
++ jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++ //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
++ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
++ reg_offset = (reg << 2);
++ val = 0x12;
++ jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t jpeg_v1_0_decode_ring_get_rptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t jpeg_v1_0_decode_ring_get_wptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void jpeg_v1_0_decode_ring_set_wptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++}
++
++/**
++ * jpeg_v1_0_decode_ring_insert_start - insert a start command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a start command to the ring.
++ */
++static void jpeg_v1_0_decode_ring_insert_start(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x68e04);
++
++ amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x80010000);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_insert_end - insert a end command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a end command to the ring.
++ */
++static void jpeg_v1_0_decode_ring_insert_end(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x68e04);
++
++ amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x00010000);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_emit_fence - emit an fence & trap command
++ *
++ * @ring: amdgpu_ring pointer
++ * @fence: fence to emit
++ *
++ * Write a fence and a trap command to the ring.
++ */
++static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++ unsigned flags)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, seq);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, seq);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, lower_32_bits(addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, upper_32_bits(addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x8);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
++ amdgpu_ring_write(ring, 0);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x01400200);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, seq);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, lower_32_bits(addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, upper_32_bits(addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
++ amdgpu_ring_write(ring, 0xffffffff);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x3fbc);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x1);
++
++ /* emit trap */
++ amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
++ amdgpu_ring_write(ring, 0);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: amdgpu_ring pointer
++ * @ib: indirect buffer to execute
++ *
++ * Write ring commands to execute the indirect buffer.
++ */
++static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring,
++ struct amdgpu_job *job,
++ struct amdgpu_ib *ib,
++ uint32_t flags)
++{
++ struct amdgpu_device *adev = ring->adev;
++ unsigned vmid = AMDGPU_JOB_GET_VMID(job);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, ib->length_dw);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
++
++ amdgpu_ring_write(ring,
++ PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
++ amdgpu_ring_write(ring, 0);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x01400200);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x2);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
++ amdgpu_ring_write(ring, 0x2);
++}
++
++static void jpeg_v1_0_decode_ring_emit_reg_wait(struct amdgpu_ring *ring,
++ uint32_t reg, uint32_t val,
++ uint32_t mask)
++{
++ struct amdgpu_device *adev = ring->adev;
++ uint32_t reg_offset = (reg << 2);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x01400200);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, val);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++ if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++ ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++ amdgpu_ring_write(ring, 0);
++ amdgpu_ring_write(ring,
++ PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
++ } else {
++ amdgpu_ring_write(ring, reg_offset);
++ amdgpu_ring_write(ring,
++ PACKETJ(0, 0, 0, PACKETJ_TYPE3));
++ }
++ amdgpu_ring_write(ring, mask);
++}
++
++static void jpeg_v1_0_decode_ring_emit_vm_flush(struct amdgpu_ring *ring,
++ unsigned vmid, uint64_t pd_addr)
++{
++ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
++ uint32_t data0, data1, mask;
++
++ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
++
++ /* wait for register write */
++ data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
++ data1 = lower_32_bits(pd_addr);
++ mask = 0xffffffff;
++ jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);
++}
++
++static void jpeg_v1_0_decode_ring_emit_wreg(struct amdgpu_ring *ring,
++ uint32_t reg, uint32_t val)
++{
++ struct amdgpu_device *adev = ring->adev;
++ uint32_t reg_offset = (reg << 2);
++
++ amdgpu_ring_write(ring,
++ PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++ if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++ ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++ amdgpu_ring_write(ring, 0);
++ amdgpu_ring_write(ring,
++ PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
++ } else {
++ amdgpu_ring_write(ring, reg_offset);
++ amdgpu_ring_write(ring,
++ PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++ }
++ amdgpu_ring_write(ring, val);
++}
++
++static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count)
++{
++ int i;
++
++ WARN_ON(ring->wptr % 2 || count % 2);
++
++ for (i = 0; i < count / 2; i++) {
++ amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
++ amdgpu_ring_write(ring, 0);
++ }
++}
++
++static int jpeg_v1_0_set_interrupt_state(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ unsigned type,
++ enum amdgpu_interrupt_state state)
++{
++ return 0;
++}
++
++static int jpeg_v1_0_process_interrupt(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ struct amdgpu_iv_entry *entry)
++{
++ DRM_DEBUG("IH: JPEG decode TRAP\n");
++
++ switch (entry->src_id) {
++ case 126:
++ amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
++ break;
++ default:
++ DRM_ERROR("Unhandled interrupt: %d %d\n",
++ entry->src_id, entry->src_data[0]);
++ break;
++ }
++
++ return 0;
++}
++
++/**
++ * jpeg_v1_0_early_init - set function pointers
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Set ring and irq function pointers
++ */
++int jpeg_v1_0_early_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ adev->jpeg.num_jpeg_inst = 1;
++
++ jpeg_v1_0_set_dec_ring_funcs(adev);
++ jpeg_v1_0_set_irq_funcs(adev);
++
++ return 0;
++}
++
++/**
++ * jpeg_v1_0_sw_init - sw init for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ */
++int jpeg_v1_0_sw_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ struct amdgpu_ring *ring;
++ int r;
++
++ /* JPEG TRAP */
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq);
++ if (r)
++ return r;
++
++ ring = &adev->jpeg.inst->ring_dec;
++ sprintf(ring->name, "jpeg_dec");
++ r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0);
++ if (r)
++ return r;
++
++ adev->jpeg.internal.jpeg_pitch = adev->jpeg.inst->external.jpeg_pitch =
++ SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
++
++ return 0;
++}
++
++/**
++ * jpeg_v1_0_sw_fini - sw fini for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * JPEG free up sw allocation
++ */
++void jpeg_v1_0_sw_fini(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ amdgpu_ring_fini(&adev->jpeg.inst[0].ring_dec);
++}
++
++/**
++ * jpeg_v1_0_start - start JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the JPEG block
++ */
++void jpeg_v1_0_start(struct amdgpu_device *adev, int mode)
++{
++ struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++
++ if (mode == 0) {
++ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
++ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
++ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
++ } WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++
++ /* initialize wptr */
++ ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++
++ /* copy patch commands to the jpeg ring */
++ jpeg_v1_0_decode_ring_set_patch_ring(ring,
++ (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
++}
++
++static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = {
++ .type = AMDGPU_RING_TYPE_VCN_JPEG,
++ .align_mask = 0xf,
++ .nop = PACKET0(0x81ff, 0),
++ .support_64bit_ptrs = false,
++ .no_user_fence = true,
++ .vmhub = AMDGPU_MMHUB_0,
++ .extra_dw = 64,
++ .get_rptr = jpeg_v1_0_decode_ring_get_rptr,
++ .get_wptr = jpeg_v1_0_decode_ring_get_wptr,
++ .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
++ .emit_frame_size =
++ 6 + 6 + /* hdp invalidate / flush */
++ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++ 8 + /* jpeg_v1_0_decode_ring_emit_vm_flush */
++ 26 + 26 + /* jpeg_v1_0_decode_ring_emit_fence x2 vm fence */
++ 6,
++ .emit_ib_size = 22, /* jpeg_v1_0_decode_ring_emit_ib */
++ .emit_ib = jpeg_v1_0_decode_ring_emit_ib,
++ .emit_fence = jpeg_v1_0_decode_ring_emit_fence,
++ .emit_vm_flush = jpeg_v1_0_decode_ring_emit_vm_flush,
++ .test_ring = amdgpu_jpeg_dec_ring_test_ring,
++ .test_ib = amdgpu_jpeg_dec_ring_test_ib,
++ .insert_nop = jpeg_v1_0_decode_ring_nop,
++ .insert_start = jpeg_v1_0_decode_ring_insert_start,
++ .insert_end = jpeg_v1_0_decode_ring_insert_end,
++ .pad_ib = amdgpu_ring_generic_pad_ib,
++ .begin_use = amdgpu_vcn_ring_begin_use,
++ .end_use = amdgpu_vcn_ring_end_use,
++ .emit_wreg = jpeg_v1_0_decode_ring_emit_wreg,
++ .emit_reg_wait = jpeg_v1_0_decode_ring_emit_reg_wait,
++ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
++static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
++{
++ adev->jpeg.inst->ring_dec.funcs = &jpeg_v1_0_decode_ring_vm_funcs;
++ DRM_INFO("JPEG decode is enabled in VM mode\n");
++}
++
++static const struct amdgpu_irq_src_funcs jpeg_v1_0_irq_funcs = {
++ .set = jpeg_v1_0_set_interrupt_state,
++ .process = jpeg_v1_0_process_interrupt,
++};
++
++static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++ adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
+new file mode 100644
+index 000000000000..bbf33a6a3972
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __JPEG_V1_0_H__
++#define __JPEG_V1_0_H__
++
++int jpeg_v1_0_early_init(void *handle);
++int jpeg_v1_0_sw_init(void *handle);
++void jpeg_v1_0_sw_fini(void *handle);
++void jpeg_v1_0_start(struct amdgpu_device *adev, int mode);
++
++#endif /*__JPEG_V1_0_H__*/
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+index b23362102e51..ef3cc37802ff 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+@@ -36,6 +36,7 @@
+ #include "mmhub/mmhub_9_1_sh_mask.h"
+
+ #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
++#include "jpeg_v1_0.h"
+
+ #define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab
+ #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
+@@ -45,9 +46,7 @@
+ static int vcn_v1_0_stop(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+-static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
+-static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
+ static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
+ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
+ struct dpg_pause_state *new_state);
+@@ -68,9 +67,10 @@ static int vcn_v1_0_early_init(void *handle)
+
+ vcn_v1_0_set_dec_ring_funcs(adev);
+ vcn_v1_0_set_enc_ring_funcs(adev);
+- vcn_v1_0_set_jpeg_ring_funcs(adev);
+ vcn_v1_0_set_irq_funcs(adev);
+
++ jpeg_v1_0_early_init(handle);
++
+ return 0;
+ }
+
+@@ -101,11 +101,6 @@ static int vcn_v1_0_sw_init(void *handle)
+ return r;
+ }
+
+- /* VCN JPEG TRAP */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.inst->irq);
+- if (r)
+- return r;
+-
+ r = amdgpu_vcn_sw_init(adev);
+ if (r)
+ return r;
+@@ -149,17 +144,11 @@ static int vcn_v1_0_sw_init(void *handle)
+ return r;
+ }
+
+- ring = &adev->vcn.inst->ring_jpeg;
+- sprintf(ring->name, "vcn_jpeg");
+- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+- if (r)
+- return r;
+-
+ adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
+- adev->vcn.internal.jpeg_pitch = adev->vcn.inst->external.jpeg_pitch =
+- SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
+
+- return 0;
++ r = jpeg_v1_0_sw_init(handle);
++
++ return r;
+ }
+
+ /**
+@@ -178,6 +167,8 @@ static int vcn_v1_0_sw_fini(void *handle)
+ if (r)
+ return r;
+
++ jpeg_v1_0_sw_fini(handle);
++
+ r = amdgpu_vcn_sw_fini(adev);
+
+ return r;
+@@ -207,7 +198,7 @@ static int vcn_v1_0_hw_init(void *handle)
+ goto done;
+ }
+
+- ring = &adev->vcn.inst->ring_jpeg;
++ ring = &adev->jpeg.inst->ring_dec;
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+@@ -947,22 +938,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+
+- ring = &adev->vcn.inst->ring_jpeg;
+- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+- UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
+- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
+- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
+-
+- /* initialize wptr */
+- ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-
+- /* copy patch commands to the jpeg ring */
+- vcn_v1_0_jpeg_ring_set_patch_ring(ring,
+- (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
++ jpeg_v1_0_start(adev, 0);
+
+ return 0;
+ }
+@@ -1106,13 +1082,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
+ ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
+
+- /* initialize JPEG wptr */
+- ring = &adev->vcn.inst->ring_jpeg;
+- ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-
+- /* copy patch commands to the jpeg ring */
+- vcn_v1_0_jpeg_ring_set_patch_ring(ring,
+- (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
++ jpeg_v1_0_start(adev, 1);
+
+ return 0;
+ }
+@@ -1316,7 +1286,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
+ UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);
+
+ /* Restore */
+- ring = &adev->vcn.inst->ring_jpeg;
++ ring = &adev->jpeg.inst->ring_dec;
+ WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+@@ -1716,389 +1686,6 @@ static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
+ amdgpu_ring_write(ring, val);
+ }
+
+-
+-/**
+- * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware read pointer
+- */
+-static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware write pointer
+- */
+-static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Commits the write pointer to the hardware
+- */
+-static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_insert_start - insert a start command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a start command to the ring.
+- */
+-static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x68e04);
+-
+- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x80010000);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_insert_end - insert a end command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a end command to the ring.
+- */
+-static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x68e04);
+-
+- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x00010000);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
+- *
+- * @ring: amdgpu_ring pointer
+- * @fence: fence to emit
+- *
+- * Write a fence and a trap command to the ring.
+- */
+-static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+- unsigned flags)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, seq);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, seq);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, lower_32_bits(addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, upper_32_bits(addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x8);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
+- amdgpu_ring_write(ring, 0);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x01400200);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, seq);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, lower_32_bits(addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, upper_32_bits(addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
+- amdgpu_ring_write(ring, 0xffffffff);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x3fbc);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x1);
+-
+- /* emit trap */
+- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
+- amdgpu_ring_write(ring, 0);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
+- *
+- * @ring: amdgpu_ring pointer
+- * @ib: indirect buffer to execute
+- *
+- * Write ring commands to execute the indirect buffer.
+- */
+-static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
+- struct amdgpu_job *job,
+- struct amdgpu_ib *ib,
+- uint32_t flags)
+-{
+- struct amdgpu_device *adev = ring->adev;
+- unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, ib->length_dw);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
+- amdgpu_ring_write(ring, 0);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x01400200);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x2);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
+- amdgpu_ring_write(ring, 0x2);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
+- uint32_t reg, uint32_t val,
+- uint32_t mask)
+-{
+- struct amdgpu_device *adev = ring->adev;
+- uint32_t reg_offset = (reg << 2);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x01400200);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, val);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring,
+- PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
+- } else {
+- amdgpu_ring_write(ring, reg_offset);
+- amdgpu_ring_write(ring,
+- PACKETJ(0, 0, 0, PACKETJ_TYPE3));
+- }
+- amdgpu_ring_write(ring, mask);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, uint64_t pd_addr)
+-{
+- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+- uint32_t data0, data1, mask;
+-
+- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+-
+- /* wait for register write */
+- data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
+- data1 = lower_32_bits(pd_addr);
+- mask = 0xffffffff;
+- vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
+- uint32_t reg, uint32_t val)
+-{
+- struct amdgpu_device *adev = ring->adev;
+- uint32_t reg_offset = (reg << 2);
+-
+- amdgpu_ring_write(ring,
+- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring,
+- PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
+- } else {
+- amdgpu_ring_write(ring, reg_offset);
+- amdgpu_ring_write(ring,
+- PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+- }
+- amdgpu_ring_write(ring, val);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
+-{
+- int i;
+-
+- WARN_ON(ring->wptr % 2 || count % 2);
+-
+- for (i = 0; i < count / 2; i++) {
+- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+- amdgpu_ring_write(ring, 0);
+- }
+-}
+-
+-static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
+-{
+- struct amdgpu_device *adev = ring->adev;
+- ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
+- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+- ring->ring[(*ptr)++] = 0;
+- ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
+- } else {
+- ring->ring[(*ptr)++] = reg_offset;
+- ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
+- }
+- ring->ring[(*ptr)++] = val;
+-}
+-
+-static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- uint32_t reg, reg_offset, val, mask, i;
+-
+- // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
+- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
+- reg_offset = (reg << 2);
+- val = lower_32_bits(ring->gpu_addr);
+- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+- // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
+- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
+- reg_offset = (reg << 2);
+- val = upper_32_bits(ring->gpu_addr);
+- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+- // 3rd to 5th: issue MEM_READ commands
+- for (i = 0; i <= 2; i++) {
+- ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
+- ring->ring[ptr++] = 0;
+- }
+-
+- // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
+- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+- reg_offset = (reg << 2);
+- val = 0x13;
+- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+- // 7th: program mmUVD_JRBC_RB_REF_DATA
+- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
+- reg_offset = (reg << 2);
+- val = 0x1;
+- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+- // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
+- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+- reg_offset = (reg << 2);
+- val = 0x1;
+- mask = 0x1;
+-
+- ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
+- ring->ring[ptr++] = 0x01400200;
+- ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
+- ring->ring[ptr++] = val;
+- ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
+- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+- ring->ring[ptr++] = 0;
+- ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
+- } else {
+- ring->ring[ptr++] = reg_offset;
+- ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
+- }
+- ring->ring[ptr++] = mask;
+-
+- //9th to 21st: insert no-op
+- for (i = 0; i <= 12; i++) {
+- ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
+- ring->ring[ptr++] = 0;
+- }
+-
+- //22nd: reset mmUVD_JRBC_RB_RPTR
+- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
+- reg_offset = (reg << 2);
+- val = 0;
+- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+- //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
+- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+- reg_offset = (reg << 2);
+- val = 0x12;
+- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-}
+-
+ static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned type,
+@@ -2123,9 +1710,6 @@ static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
+ case 120:
+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
+ break;
+- case 126:
+- amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
+- break;
+ default:
+ DRM_ERROR("Unhandled interrupt: %d %d\n",
+ entry->src_id, entry->src_data[0]);
+@@ -2259,41 +1843,6 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+
+-static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
+- .type = AMDGPU_RING_TYPE_VCN_JPEG,
+- .align_mask = 0xf,
+- .nop = PACKET0(0x81ff, 0),
+- .support_64bit_ptrs = false,
+- .no_user_fence = true,
+- .vmhub = AMDGPU_MMHUB_0,
+- .extra_dw = 64,
+- .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
+- .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
+- .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
+- .emit_frame_size =
+- 6 + 6 + /* hdp invalidate / flush */
+- SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+- SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+- 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */
+- 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */
+- 6,
+- .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */
+- .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
+- .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
+- .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
+- .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
+- .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
+- .insert_nop = vcn_v1_0_jpeg_ring_nop,
+- .insert_start = vcn_v1_0_jpeg_ring_insert_start,
+- .insert_end = vcn_v1_0_jpeg_ring_insert_end,
+- .pad_ib = amdgpu_ring_generic_pad_ib,
+- .begin_use = amdgpu_vcn_ring_begin_use,
+- .end_use = amdgpu_vcn_ring_end_use,
+- .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
+- .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
+- .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+-};
+-
+ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
+@@ -2310,12 +1859,6 @@ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+ DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+
+-static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+-{
+- adev->vcn.inst->ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
+- DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+-}
+-
+ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
+ .set = vcn_v1_0_set_interrupt_state,
+ .process = vcn_v1_0_process_interrupt,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4446-drm-amdgpu-use-the-JPEG-structure-for-general-driver.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4446-drm-amdgpu-use-the-JPEG-structure-for-general-driver.patch
new file mode 100644
index 00000000..ffcbfd8a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4446-drm-amdgpu-use-the-JPEG-structure-for-general-driver.patch
@@ -0,0 +1,95 @@
+From acacc1b13681b090b5ccc01dc76706436fd659a4 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:23:14 -0500
+Subject: [PATCH 4446/4736] drm/amdgpu: use the JPEG structure for general
+ driver support
+
+JPEG1.0 will be functional along with VCN1.0
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +++-----
+ 3 files changed, 8 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 0300635f6f63..3ad8ccc6630b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -172,10 +172,10 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ }
+ break;
+ case AMDGPU_HW_IP_VCN_JPEG:
+- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++ for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
+ if (adev->vcn.harvest_config & (1 << j))
+ continue;
+- rings[num_rings++] = &adev->vcn.inst[j].ring_jpeg;
++ rings[num_rings++] = &adev->jpeg.inst[j].ring_dec;
+ }
+ break;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 488258f1138d..ab6e0fc5800f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -398,11 +398,11 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ break;
+ case AMDGPU_HW_IP_VCN_JPEG:
+ type = AMD_IP_BLOCK_TYPE_VCN;
+- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+- if (adev->uvd.harvest_config & (1 << i))
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
++ if (adev->jpeg.harvest_config & (1 << i))
+ continue;
+
+- if (adev->vcn.inst[i].ring_jpeg.sched.ready)
++ if (adev->jpeg.inst[i].ring_dec.sched.ready)
+ ++num_rings;
+ }
+ ib_start_alignment = 16;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index c72819d55502..9daa42f03886 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -213,8 +213,6 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
+-
+- amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg);
+ }
+
+ release_firmware(adev->vcn.fw);
+@@ -307,7 +305,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ else
+ new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+
+- if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg))
++ if (amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec))
+ new_state.jpeg = VCN_DPG_STATE__PAUSE;
+ else
+ new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+@@ -315,7 +313,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ adev->vcn.pause_dpg_mode(adev, &new_state);
+ }
+
+- fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg);
++ fence[j] += amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec);
+ fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
+ fences += fence[j];
+ }
+@@ -359,7 +357,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
+ else
+ new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+
+- if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg))
++ if (amdgpu_fence_count_emitted(&adev->jpeg.inst[ring->me].ring_dec))
+ new_state.jpeg = VCN_DPG_STATE__PAUSE;
+ else
+ new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4447-drm-amdgpu-add-JPEG-IP-block-type.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4447-drm-amdgpu-add-JPEG-IP-block-type.patch
new file mode 100644
index 00000000..a80318a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4447-drm-amdgpu-add-JPEG-IP-block-type.patch
@@ -0,0 +1,30 @@
+From 247de6849ea43686a357b2a5fe2784f9170d4711 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 12:44:54 -0500
+Subject: [PATCH 4447/4736] drm/amdgpu: add JPEG IP block type
+
+From VCN2.0, JPEG2.0 is a separated IP block.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/amd_shared.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index dc7eb28f0296..d5bc8be4d70c 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -53,7 +53,8 @@ enum amd_ip_block_type {
+ AMD_IP_BLOCK_TYPE_VCE,
+ AMD_IP_BLOCK_TYPE_ACP,
+ AMD_IP_BLOCK_TYPE_VCN,
+- AMD_IP_BLOCK_TYPE_MES
++ AMD_IP_BLOCK_TYPE_MES,
++ AMD_IP_BLOCK_TYPE_JPEG
+ };
+
+ enum amd_clockgating_state {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4448-drm-amdgpu-add-JPEG-common-functions-to-amdgpu_jpeg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4448-drm-amdgpu-add-JPEG-common-functions-to-amdgpu_jpeg.patch
new file mode 100644
index 00000000..aac3870f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4448-drm-amdgpu-add-JPEG-common-functions-to-amdgpu_jpeg.patch
@@ -0,0 +1,131 @@
+From c3341685e454cee5c72b56d69b02f50e03b1f077 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:12:05 -0500
+Subject: [PATCH 4448/4736] drm/amdgpu: add JPEG common functions to
+ amdgpu_jpeg
+
+They will be used for JPEG2.0 and later.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 76 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 10 ++++
+ 2 files changed, 86 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+index d9a547d4d3b2..5727f00afc8e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+@@ -26,9 +26,85 @@
+
+ #include "amdgpu.h"
+ #include "amdgpu_jpeg.h"
++#include "amdgpu_pm.h"
+ #include "soc15d.h"
+ #include "soc15_common.h"
+
++#define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
++
++static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
++
++int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
++{
++ INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
++
++ return 0;
++}
++
++int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
++{
++ int i;
++
++ cancel_delayed_work_sync(&adev->jpeg.idle_work);
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec);
++ }
++
++ return 0;
++}
++
++int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
++{
++ cancel_delayed_work_sync(&adev->jpeg.idle_work);
++
++ return 0;
++}
++
++int amdgpu_jpeg_resume(struct amdgpu_device *adev)
++{
++ return 0;
++}
++
++static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
++{
++ struct amdgpu_device *adev =
++ container_of(work, struct amdgpu_device, jpeg.idle_work.work);
++ unsigned int fences = 0;
++ unsigned int i;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec);
++ }
++
++ if (fences == 0)
++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
++ AMD_PG_STATE_GATE);
++ else
++ schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
++}
++
++void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++ bool set_clocks = !cancel_delayed_work_sync(&adev->jpeg.idle_work);
++
++ if (set_clocks)
++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
++ AMD_PG_STATE_UNGATE);
++}
++
++void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
++{
++ schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
++}
++
+ int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
+ {
+ struct amdgpu_device *adev = ring->adev;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+index a8d988c25f45..5e2e06ec13df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -41,8 +41,18 @@ struct amdgpu_jpeg {
+ struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
+ struct amdgpu_jpeg_reg internal;
+ unsigned harvest_config;
++ struct delayed_work idle_work;
++ enum amd_powergating_state cur_state;
+ };
+
++int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
++int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev);
++int amdgpu_jpeg_suspend(struct amdgpu_device *adev);
++int amdgpu_jpeg_resume(struct amdgpu_device *adev);
++
++void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring);
++void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring);
++
+ int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
+ int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4449-drm-amdgpu-add-JPEG-v2.0-function-supports.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4449-drm-amdgpu-add-JPEG-v2.0-function-supports.patch
new file mode 100644
index 00000000..026bb3b4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4449-drm-amdgpu-add-JPEG-v2.0-function-supports.patch
@@ -0,0 +1,897 @@
+From 7cc43910abfb193dd38b61119bf30459551aa4a7 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:26:46 -0500
+Subject: [PATCH 4449/4736] drm/amdgpu: add JPEG v2.0 function supports
+
+It got separated from VCN2.0 with a new jpeg_v2_0_ip_block
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 809 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 42 ++
+ 3 files changed, 853 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 62ef3d7955d9..7cbe646d1ae1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -155,7 +155,8 @@ amdgpu-y += \
+ vcn_v2_0.o \
+ vcn_v2_5.o \
+ amdgpu_jpeg.o \
+- jpeg_v1_0.o
++ jpeg_v1_0.o \
++ jpeg_v2_0.o
+
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+new file mode 100644
+index 000000000000..4143ef6905b8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+@@ -0,0 +1,809 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "amdgpu_pm.h"
++#include "soc15.h"
++#include "soc15d.h"
++
++#include "vcn/vcn_2_0_0_offset.h"
++#include "vcn/vcn_2_0_0_sh_mask.h"
++#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
++
++#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
++#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
++#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
++#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
++#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
++#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
++#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
++#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
++#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec
++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed
++#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085
++#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
++#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
++#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
++
++#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
++
++static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
++static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
++static int jpeg_v2_0_set_powergating_state(void *handle,
++ enum amd_powergating_state state);
++
++/**
++ * jpeg_v2_0_early_init - set function pointers
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Set ring and irq function pointers
++ */
++static int jpeg_v2_0_early_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ adev->jpeg.num_jpeg_inst = 1;
++
++ jpeg_v2_0_set_dec_ring_funcs(adev);
++ jpeg_v2_0_set_irq_funcs(adev);
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_0_sw_init - sw init for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Load firmware and sw initialization
++ */
++static int jpeg_v2_0_sw_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ struct amdgpu_ring *ring;
++ int r;
++
++ /* JPEG TRAP */
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
++ VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
++ if (r)
++ return r;
++
++ r = amdgpu_jpeg_sw_init(adev);
++ if (r)
++ return r;
++
++ r = amdgpu_jpeg_resume(adev);
++ if (r)
++ return r;
++
++ ring = &adev->jpeg.inst->ring_dec;
++ ring->use_doorbell = true;
++ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
++ sprintf(ring->name, "jpeg_dec");
++ r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0);
++ if (r)
++ return r;
++
++ adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
++ adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_0_sw_fini - sw fini for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * JPEG suspend and free up sw allocation
++ */
++static int jpeg_v2_0_sw_fini(void *handle)
++{
++ int r;
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ r = amdgpu_jpeg_suspend(adev);
++ if (r)
++ return r;
++
++ r = amdgpu_jpeg_sw_fini(adev);
++
++ return r;
++}
++
++/**
++ * jpeg_v2_0_hw_init - start and test JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ */
++static int jpeg_v2_0_hw_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++ int r;
++
++ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++ (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
++
++ r = amdgpu_ring_test_helper(ring);
++ if (!r)
++ DRM_INFO("JPEG decode initialized successfully.\n");
++
++ return r;
++}
++
++/**
++ * jpeg_v2_0_hw_fini - stop the hardware block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Stop the JPEG block, mark ring as not ready any more
++ */
++static int jpeg_v2_0_hw_fini(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++
++ if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
++ RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
++ jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
++
++ ring->sched.ready = false;
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_0_suspend - suspend JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * HW fini and suspend JPEG block
++ */
++static int jpeg_v2_0_suspend(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int r;
++
++ r = jpeg_v2_0_hw_fini(adev);
++ if (r)
++ return r;
++
++ r = amdgpu_jpeg_suspend(adev);
++
++ return r;
++}
++
++/**
++ * jpeg_v2_0_resume - resume JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Resume firmware and hw init JPEG block
++ */
++static int jpeg_v2_0_resume(void *handle)
++{
++ int r;
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ r = amdgpu_jpeg_resume(adev);
++ if (r)
++ return r;
++
++ r = jpeg_v2_0_hw_init(adev);
++
++ return r;
++}
++
++static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
++{
++ uint32_t data;
++ int r = 0;
++
++ data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++
++ SOC15_WAIT_ON_RREG(JPEG, 0,
++ mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
++ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++
++ if (r) {
++ DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
++ return r;
++ }
++
++ /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
++ data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
++
++ return 0;
++}
++
++static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
++{
++ uint32_t data;
++ int r = 0;
++
++ data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
++ data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
++ data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
++
++ data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++
++ SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
++ (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
++ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++
++ if (r) {
++ DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
++ return r;
++ }
++
++ return 0;
++}
++
++static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev)
++{
++ uint32_t data;
++
++ data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
++ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++
++ data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++ data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++ WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
++
++ data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
++ data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
++ | JPEG_CGC_GATE__JPEG2_DEC_MASK
++ | JPEG_CGC_GATE__JPEG_ENC_MASK
++ | JPEG_CGC_GATE__JMCIF_MASK
++ | JPEG_CGC_GATE__JRBBM_MASK);
++ WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
++}
++
++static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev)
++{
++ uint32_t data;
++
++ data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
++ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++
++ data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++ data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++ WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
++
++ data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
++ data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
++ |JPEG_CGC_GATE__JPEG2_DEC_MASK
++ |JPEG_CGC_GATE__JPEG_ENC_MASK
++ |JPEG_CGC_GATE__JMCIF_MASK
++ |JPEG_CGC_GATE__JRBBM_MASK);
++ WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
++}
++
++/**
++ * jpeg_v2_0_start - start JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the JPEG block
++ */
++static int jpeg_v2_0_start(struct amdgpu_device *adev)
++{
++ struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++ int r;
++
++ /* disable power gating */
++ r = jpeg_v2_0_disable_power_gating(adev);
++ if (r)
++ return r;
++
++ /* JPEG disable CGC */
++ jpeg_v2_0_disable_clock_gating(adev);
++
++ WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
++
++ /* enable JMI channel */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
++ ~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++ /* enable System Interrupt for JRBC */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
++ JPEG_SYS_INT_EN__DJRBC_MASK,
++ ~JPEG_SYS_INT_EN__DJRBC_MASK);
++
++ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
++ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
++ lower_32_bits(ring->gpu_addr));
++ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
++ upper_32_bits(ring->gpu_addr));
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
++ ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_0_stop - stop JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the JPEG block
++ */
++static int jpeg_v2_0_stop(struct amdgpu_device *adev)
++{
++ int r;
++
++ /* reset JMI */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
++ UVD_JMI_CNTL__SOFT_RESET_MASK,
++ ~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++ /* enable JPEG CGC */
++ jpeg_v2_0_enable_clock_gating(adev);
++
++ /* enable power gating */
++ r = jpeg_v2_0_enable_power_gating(adev);
++
++ return r;
++}
++
++/**
++ * jpeg_v2_0_dec_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ if (ring->use_doorbell)
++ return adev->wb.wb[ring->wptr_offs];
++ else
++ return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ if (ring->use_doorbell) {
++ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++ } else {
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++ }
++}
++
++/**
++ * jpeg_v2_0_dec_ring_insert_start - insert a start command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a start command to the ring.
++ */
++void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
++{
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x68e04);
++
++ amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x80010000);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_insert_end - insert a end command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a end command to the ring.
++ */
++void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
++{
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x68e04);
++
++ amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x00010000);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
++ *
++ * @ring: amdgpu_ring pointer
++ * @fence: fence to emit
++ *
++ * Write a fence and a trap command to the ring.
++ */
++void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++ unsigned flags)
++{
++ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, seq);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, seq);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, lower_32_bits(addr));
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, upper_32_bits(addr));
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x8);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
++ 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
++ amdgpu_ring_write(ring, 0);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x3fbc);
++
++ amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x1);
++
++ amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
++ amdgpu_ring_write(ring, 0);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: amdgpu_ring pointer
++ * @ib: indirect buffer to execute
++ *
++ * Write ring commands to execute the indirect buffer.
++ */
++void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
++ struct amdgpu_job *job,
++ struct amdgpu_ib *ib,
++ uint32_t flags)
++{
++ unsigned vmid = AMDGPU_JOB_GET_VMID(job);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, ib->length_dw);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
++
++ amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
++ amdgpu_ring_write(ring, 0);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x01400200);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x2);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
++ 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
++ amdgpu_ring_write(ring, 0x2);
++}
++
++void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
++ uint32_t val, uint32_t mask)
++{
++ uint32_t reg_offset = (reg << 2);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, 0x01400200);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ amdgpu_ring_write(ring, val);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
++ amdgpu_ring_write(ring, 0);
++ amdgpu_ring_write(ring,
++ PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
++ } else {
++ amdgpu_ring_write(ring, reg_offset);
++ amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++ 0, 0, PACKETJ_TYPE3));
++ }
++ amdgpu_ring_write(ring, mask);
++}
++
++void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
++ unsigned vmid, uint64_t pd_addr)
++{
++ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
++ uint32_t data0, data1, mask;
++
++ pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
++
++ /* wait for register write */
++ data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
++ data1 = lower_32_bits(pd_addr);
++ mask = 0xffffffff;
++ jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
++}
++
++void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
++{
++ uint32_t reg_offset = (reg << 2);
++
++ amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++ 0, 0, PACKETJ_TYPE0));
++ if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
++ amdgpu_ring_write(ring, 0);
++ amdgpu_ring_write(ring,
++ PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
++ } else {
++ amdgpu_ring_write(ring, reg_offset);
++ amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++ 0, 0, PACKETJ_TYPE0));
++ }
++ amdgpu_ring_write(ring, val);
++}
++
++void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
++{
++ int i;
++
++ WARN_ON(ring->wptr % 2 || count % 2);
++
++ for (i = 0; i < count / 2; i++) {
++ amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
++ amdgpu_ring_write(ring, 0);
++ }
++}
++
++static bool jpeg_v2_0_is_idle(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
++ UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
++ UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
++}
++
++static int jpeg_v2_0_wait_for_idle(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int ret = 0;
++
++ SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
++ UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
++
++ return ret;
++}
++
++static int jpeg_v2_0_set_clockgating_state(void *handle,
++ enum amd_clockgating_state state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
++
++ if (enable) {
++ if (jpeg_v2_0_is_idle(handle))
++ return -EBUSY;
++ jpeg_v2_0_enable_clock_gating(adev);
++ } else {
++ jpeg_v2_0_disable_clock_gating(adev);
++ }
++
++ return 0;
++}
++
++static int jpeg_v2_0_set_powergating_state(void *handle,
++ enum amd_powergating_state state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int ret;
++
++ if (state == adev->jpeg.cur_state)
++ return 0;
++
++ if (state == AMD_PG_STATE_GATE)
++ ret = jpeg_v2_0_stop(adev);
++ else
++ ret = jpeg_v2_0_start(adev);
++
++ if (!ret)
++ adev->jpeg.cur_state = state;
++
++ return ret;
++}
++
++static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ unsigned type,
++ enum amdgpu_interrupt_state state)
++{
++ return 0;
++}
++
++static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ struct amdgpu_iv_entry *entry)
++{
++ DRM_DEBUG("IH: JPEG TRAP\n");
++
++ switch (entry->src_id) {
++ case VCN_2_0__SRCID__JPEG_DECODE:
++ amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
++ break;
++ default:
++ DRM_ERROR("Unhandled interrupt: %d %d\n",
++ entry->src_id, entry->src_data[0]);
++ break;
++ }
++
++ return 0;
++}
++
++static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
++ .name = "jpeg_v2_0",
++ .early_init = jpeg_v2_0_early_init,
++ .late_init = NULL,
++ .sw_init = jpeg_v2_0_sw_init,
++ .sw_fini = jpeg_v2_0_sw_fini,
++ .hw_init = jpeg_v2_0_hw_init,
++ .hw_fini = jpeg_v2_0_hw_fini,
++ .suspend = jpeg_v2_0_suspend,
++ .resume = jpeg_v2_0_resume,
++ .is_idle = jpeg_v2_0_is_idle,
++ .wait_for_idle = jpeg_v2_0_wait_for_idle,
++ .check_soft_reset = NULL,
++ .pre_soft_reset = NULL,
++ .soft_reset = NULL,
++ .post_soft_reset = NULL,
++ .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
++ .set_powergating_state = jpeg_v2_0_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
++ .type = AMDGPU_RING_TYPE_VCN_JPEG,
++ .align_mask = 0xf,
++ .vmhub = AMDGPU_MMHUB_0,
++ .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
++ .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
++ .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
++ .emit_frame_size =
++ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++ 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
++ 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
++ 8 + 16,
++ .emit_ib_size = 22, /* jpeg_v2_0_dec_ring_emit_ib */
++ .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
++ .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
++ .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
++ .test_ring = amdgpu_jpeg_dec_ring_test_ring,
++ .test_ib = amdgpu_jpeg_dec_ring_test_ib,
++ .insert_nop = jpeg_v2_0_dec_ring_nop,
++ .insert_start = jpeg_v2_0_dec_ring_insert_start,
++ .insert_end = jpeg_v2_0_dec_ring_insert_end,
++ .pad_ib = amdgpu_ring_generic_pad_ib,
++ .begin_use = amdgpu_jpeg_ring_begin_use,
++ .end_use = amdgpu_jpeg_ring_end_use,
++ .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
++ .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
++ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
++static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
++{
++ adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs;
++ DRM_INFO("JPEG decode is enabled in VM mode\n");
++}
++
++static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
++ .set = jpeg_v2_0_set_interrupt_state,
++ .process = jpeg_v2_0_process_interrupt,
++};
++
++static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++ adev->jpeg.inst->irq.num_types = 1;
++ adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
++}
++
++const struct amdgpu_ip_block_version jpeg_v2_0_ip_block =
++{
++ .type = AMD_IP_BLOCK_TYPE_JPEG,
++ .major = 2,
++ .minor = 0,
++ .rev = 0,
++ .funcs = &jpeg_v2_0_ip_funcs,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+new file mode 100644
+index 000000000000..15a344ed340f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __JPEG_V2_0_H__
++#define __JPEG_V2_0_H__
++
++void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
++void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
++void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++ unsigned flags);
++void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
++ struct amdgpu_ib *ib, uint32_t flags);
++void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
++ uint32_t val, uint32_t mask);
++void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
++ unsigned vmid, uint64_t pd_addr);
++void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
++void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
++
++extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;
++
++#endif /* __JPEG_V2_0_H__ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4450-drm-amdgpu-remove-unnecessary-JPEG2.0-code-from-VCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4450-drm-amdgpu-remove-unnecessary-JPEG2.0-code-from-VCN2.patch
new file mode 100644
index 00000000..d5615b6c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4450-drm-amdgpu-remove-unnecessary-JPEG2.0-code-from-VCN2.patch
@@ -0,0 +1,395 @@
+From f2e6cb77cc722e76f1d89851d55c6eb4fd84b288 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:30:15 -0500
+Subject: [PATCH 4450/4736] drm/amdgpu: remove unnecessary JPEG2.0 code from
+ VCN2.0
+
+They are no longer needed, using from JPEG2.0 instead.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 260 +-------------------------
+ 1 file changed, 3 insertions(+), 257 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 16f192f6c967..4e0c3467deb2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -74,7 +74,6 @@
+
+ static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+-static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
+ static int vcn_v2_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state);
+@@ -97,7 +96,6 @@ static int vcn_v2_0_early_init(void *handle)
+
+ vcn_v2_0_set_dec_ring_funcs(adev);
+ vcn_v2_0_set_enc_ring_funcs(adev);
+- vcn_v2_0_set_jpeg_ring_funcs(adev);
+ vcn_v2_0_set_irq_funcs(adev);
+
+ return 0;
+@@ -132,12 +130,6 @@ static int vcn_v2_0_sw_init(void *handle)
+ return r;
+ }
+
+- /* VCN JPEG TRAP */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+- VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq);
+- if (r)
+- return r;
+-
+ r = amdgpu_vcn_sw_init(adev);
+ if (r)
+ return r;
+@@ -194,19 +186,8 @@ static int vcn_v2_0_sw_init(void *handle)
+ return r;
+ }
+
+- ring = &adev->vcn.inst->ring_jpeg;
+- ring->use_doorbell = true;
+- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
+- sprintf(ring->name, "vcn_jpeg");
+- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+- if (r)
+- return r;
+-
+ adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
+
+- adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+- adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
+-
+ return 0;
+ }
+
+@@ -258,11 +239,6 @@ static int vcn_v2_0_hw_init(void *handle)
+ goto done;
+ }
+
+- ring = &adev->vcn.inst->ring_jpeg;
+- r = amdgpu_ring_test_helper(ring);
+- if (r)
+- goto done;
+-
+ done:
+ if (!r)
+ DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
+@@ -296,9 +272,6 @@ static int vcn_v2_0_hw_fini(void *handle)
+ ring->sched.ready = false;
+ }
+
+- ring = &adev->vcn.inst->ring_jpeg;
+- ring->sched.ready = false;
+-
+ return 0;
+ }
+
+@@ -393,7 +366,6 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
+ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+
+ WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+- WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+ }
+
+ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
+@@ -647,129 +619,6 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
+ UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
+ }
+
+-/**
+- * jpeg_v2_0_start - start JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * Setup and start the JPEG block
+- */
+-static int jpeg_v2_0_start(struct amdgpu_device *adev)
+-{
+- struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg;
+- uint32_t tmp;
+- int r = 0;
+-
+- /* disable power gating */
+- tmp = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
+-
+- SOC15_WAIT_ON_RREG(VCN, 0,
+- mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
+- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+-
+- if (r) {
+- DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
+- return r;
+- }
+-
+- /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
+- tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
+- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
+-
+- /* JPEG disable CGC */
+- tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
+- tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+- tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+- tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+- WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
+-
+- tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
+- tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
+- | JPEG_CGC_GATE__JPEG2_DEC_MASK
+- | JPEG_CGC_GATE__JPEG_ENC_MASK
+- | JPEG_CGC_GATE__JMCIF_MASK
+- | JPEG_CGC_GATE__JRBBM_MASK);
+- WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
+-
+- /* enable JMI channel */
+- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
+- ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+- /* enable System Interrupt for JRBC */
+- WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
+- JPEG_SYS_INT_EN__DJRBC_MASK,
+- ~JPEG_SYS_INT_EN__DJRBC_MASK);
+-
+- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
+- lower_32_bits(ring->gpu_addr));
+- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
+- upper_32_bits(ring->gpu_addr));
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
+- ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-
+- return 0;
+-}
+-
+-/**
+- * jpeg_v2_0_stop - stop JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * stop the JPEG block
+- */
+-static int jpeg_v2_0_stop(struct amdgpu_device *adev)
+-{
+- uint32_t tmp;
+- int r = 0;
+-
+- /* reset JMI */
+- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL),
+- UVD_JMI_CNTL__SOFT_RESET_MASK,
+- ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+- /* enable JPEG CGC */
+- tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
+- tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+- tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+- tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+- WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
+-
+-
+- tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
+- tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
+- |JPEG_CGC_GATE__JPEG2_DEC_MASK
+- |JPEG_CGC_GATE__JPEG_ENC_MASK
+- |JPEG_CGC_GATE__JMCIF_MASK
+- |JPEG_CGC_GATE__JRBBM_MASK);
+- WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
+-
+- /* enable power gating */
+- tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS));
+- tmp &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
+- tmp |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
+- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
+-
+- tmp = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
+-
+- SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
+- (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
+- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+-
+- if (r) {
+- DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
+- return r;
+- }
+-
+- return r;
+-}
+-
+ /**
+ * vcn_v2_0_enable_clock_gating - enable VCN clock gating
+ *
+@@ -1052,12 +901,8 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_uvd(adev, true);
+
+- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+- r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
+- if (r)
+- return r;
+- goto jpeg;
+- }
++ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
++ return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
+
+ vcn_v2_0_disable_static_power_gating(adev);
+
+@@ -1209,10 +1054,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+
+-jpeg:
+- r = jpeg_v2_0_start(adev);
+-
+- return r;
++ return 0;
+ }
+
+ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
+@@ -1231,9 +1073,6 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
+ tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
+
+- tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+- SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+-
+ tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+
+@@ -1252,10 +1091,6 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
+ uint32_t tmp;
+ int r;
+
+- r = jpeg_v2_0_stop(adev);
+- if (r)
+- return r;
+-
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v2_0_stop_dpg_mode(adev);
+ if (r)
+@@ -1781,56 +1616,6 @@ void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_
+ amdgpu_ring_write(ring, val);
+ }
+
+-/**
+- * vcn_v2_0_jpeg_ring_get_rptr - get read pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware read pointer
+- */
+-static uint64_t vcn_v2_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_get_wptr - get write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware write pointer
+- */
+-static uint64_t vcn_v2_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- if (ring->use_doorbell)
+- return adev->wb.wb[ring->wptr_offs];
+- else
+- return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_set_wptr - set write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Commits the write pointer to the hardware
+- */
+-static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- if (ring->use_doorbell) {
+- adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+- WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+- } else {
+- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+- }
+-}
+-
+ /**
+ * vcn_v2_0_jpeg_ring_insert_start - insert a start command
+ *
+@@ -2071,9 +1856,6 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
+ case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
+ break;
+- case VCN_2_0__SRCID__JPEG_DECODE:
+- amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
+- break;
+ default:
+ DRM_ERROR("Unhandled interrupt: %d %d\n",
+ entry->src_id, entry->src_data[0]);
+@@ -2219,36 +2001,6 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+
+-static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
+- .type = AMDGPU_RING_TYPE_VCN_JPEG,
+- .align_mask = 0xf,
+- .vmhub = AMDGPU_MMHUB_0,
+- .get_rptr = vcn_v2_0_jpeg_ring_get_rptr,
+- .get_wptr = vcn_v2_0_jpeg_ring_get_wptr,
+- .set_wptr = vcn_v2_0_jpeg_ring_set_wptr,
+- .emit_frame_size =
+- SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+- SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+- 8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
+- 18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
+- 8 + 16,
+- .emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
+- .emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
+- .emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
+- .emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
+- .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
+- .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
+- .insert_nop = vcn_v2_0_jpeg_ring_nop,
+- .insert_start = vcn_v2_0_jpeg_ring_insert_start,
+- .insert_end = vcn_v2_0_jpeg_ring_insert_end,
+- .pad_ib = amdgpu_ring_generic_pad_ib,
+- .begin_use = amdgpu_vcn_ring_begin_use,
+- .end_use = amdgpu_vcn_ring_end_use,
+- .emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
+- .emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
+- .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+-};
+-
+ static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
+@@ -2265,12 +2017,6 @@ static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+ DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+
+-static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+-{
+- adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
+- DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+-}
+-
+ static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
+ .set = vcn_v2_0_set_interrupt_state,
+ .process = vcn_v2_0_process_interrupt,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4451-drm-amdgpu-add-JPEG-PG-and-CG-interface.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4451-drm-amdgpu-add-JPEG-PG-and-CG-interface.patch
new file mode 100644
index 00000000..411357a7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4451-drm-amdgpu-add-JPEG-PG-and-CG-interface.patch
@@ -0,0 +1,36 @@
+From 0a6773cfa2f7e7619ca1dd38a0fa8880a1b4909d Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:17:52 -0500
+Subject: [PATCH 4451/4736] drm/amdgpu: add JPEG PG and CG interface
+
+From JPEG2.0, it will use its own PG/CG
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index d5bc8be4d70c..d655a76bedc6 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -100,6 +100,7 @@ enum amd_powergating_state {
+ #define AMD_CG_SUPPORT_IH_CG (1 << 27)
+ #define AMD_CG_SUPPORT_ATHUB_LS (1 << 28)
+ #define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29)
++#define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30)
+ /* PG flags */
+ #define AMD_PG_SUPPORT_GFX_PG (1 << 0)
+ #define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
+@@ -118,6 +119,7 @@ enum amd_powergating_state {
+ #define AMD_PG_SUPPORT_VCN (1 << 14)
+ #define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
+ #define AMD_PG_SUPPORT_ATHUB (1 << 16)
++#define AMD_PG_SUPPORT_JPEG (1 << 17)
+
+ enum PP_FEATURE_MASK {
+ PP_SCLK_DPM_MASK = 0x1,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch
new file mode 100644
index 00000000..1d3c19c2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch
@@ -0,0 +1,177 @@
+From fd3e1f0031707e8ae09a39c90519d483c1e1ffce Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 15:09:25 -0500
+Subject: [PATCH 4452/4736] drm/amdgpu: add PG and CG for JPEG2.0
+
+And enable them for Navi1x and Renoir
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 62 +++++++++++++++-----------
+ drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++-
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +
+ 3 files changed, 45 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+index 4143ef6905b8..3869730b2331 100644
+--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+@@ -227,16 +227,18 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
+ uint32_t data;
+ int r = 0;
+
+- data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
+-
+- SOC15_WAIT_ON_RREG(JPEG, 0,
+- mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
+- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+-
+- if (r) {
+- DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
+- return r;
++ if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
++ data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++
++ SOC15_WAIT_ON_RREG(JPEG, 0,
++ mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
++ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++
++ if (r) {
++ DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
++ return r;
++ }
+ }
+
+ /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
+@@ -248,24 +250,26 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
+
+ static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
+ {
+- uint32_t data;
+- int r = 0;
++ if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
++ uint32_t data;
++ int r = 0;
+
+- data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
+- data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
+- data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
+- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
++ data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
++ data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
++ data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
+
+- data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++ data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
+
+- SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
+- (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
+- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++ SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
++ (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
++ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+
+- if (r) {
+- DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
+- return r;
++ if (r) {
++ DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
++ return r;
++ }
+ }
+
+ return 0;
+@@ -276,7 +280,10 @@ static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev)
+ uint32_t data;
+
+ data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
+- data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++ if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
++ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++ else
++ data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+
+ data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+@@ -296,7 +303,10 @@ static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev)
+ uint32_t data;
+
+ data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
+- data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++ if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
++ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++ else
++ data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+
+ data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index be761785b2a8..0b8aedfe1b67 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -642,10 +642,12 @@ static int nv_common_early_init(void *handle)
+ AMD_CG_SUPPORT_ATHUB_MGCG |
+ AMD_CG_SUPPORT_ATHUB_LS |
+ AMD_CG_SUPPORT_VCN_MGCG |
++ AMD_CG_SUPPORT_JPEG_MGCG |
+ AMD_CG_SUPPORT_BIF_MGCG |
+ AMD_CG_SUPPORT_BIF_LS;
+ adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_VCN_DPG |
++ AMD_PG_SUPPORT_JPEG |
+ AMD_PG_SUPPORT_ATHUB;
+ adev->external_rev_id = adev->rev_id + 0x1;
+ break;
+@@ -662,9 +664,11 @@ static int nv_common_early_init(void *handle)
+ AMD_CG_SUPPORT_ATHUB_MGCG |
+ AMD_CG_SUPPORT_ATHUB_LS |
+ AMD_CG_SUPPORT_VCN_MGCG |
++ AMD_CG_SUPPORT_JPEG_MGCG |
+ AMD_CG_SUPPORT_BIF_MGCG |
+ AMD_CG_SUPPORT_BIF_LS;
+ adev->pg_flags = AMD_PG_SUPPORT_VCN |
++ AMD_PG_SUPPORT_JPEG |
+ AMD_PG_SUPPORT_VCN_DPG;
+ adev->external_rev_id = adev->rev_id + 20;
+ break;
+@@ -683,9 +687,11 @@ static int nv_common_early_init(void *handle)
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_ATHUB_MGCG |
+ AMD_CG_SUPPORT_ATHUB_LS |
+- AMD_CG_SUPPORT_VCN_MGCG;
++ AMD_CG_SUPPORT_VCN_MGCG |
++ AMD_CG_SUPPORT_JPEG_MGCG;
+ adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_VCN_DPG |
++ AMD_PG_SUPPORT_JPEG |
+ AMD_PG_SUPPORT_ATHUB;
+ adev->external_rev_id = adev->rev_id + 0xa;
+ break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 836a34c10db2..233d3850789e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1231,12 +1231,14 @@ static int soc15_common_early_init(void *handle)
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_ROM_MGCG |
+ AMD_CG_SUPPORT_VCN_MGCG |
++ AMD_CG_SUPPORT_JPEG_MGCG |
+ AMD_CG_SUPPORT_IH_CG |
+ AMD_CG_SUPPORT_ATHUB_LS |
+ AMD_CG_SUPPORT_ATHUB_MGCG |
+ AMD_CG_SUPPORT_DF_MGCG;
+ adev->pg_flags = AMD_PG_SUPPORT_SDMA |
+ AMD_PG_SUPPORT_VCN |
++ AMD_PG_SUPPORT_JPEG |
+ AMD_PG_SUPPORT_VCN_DPG;
+ adev->external_rev_id = adev->rev_id + 0x91;
+ break;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4453-drm-amd-powerplay-add-JPEG-Powerplay-interface.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4453-drm-amd-powerplay-add-JPEG-Powerplay-interface.patch
new file mode 100644
index 00000000..54c042a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4453-drm-amd-powerplay-add-JPEG-Powerplay-interface.patch
@@ -0,0 +1,44 @@
+From 978731660cf99a39b47f5d0c80ec6cd4286354af Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:54:33 -0500
+Subject: [PATCH 4453/4736] drm/amd/powerplay: add JPEG Powerplay interface
+
+It will be used for different SMU specific to HW
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 999445c5c010..cdd46cdaffb8 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -282,6 +282,7 @@ struct smu_power_gate {
+ bool uvd_gated;
+ bool vce_gated;
+ bool vcn_gated;
++ bool jpeg_gated;
+ };
+
+ struct smu_power_context {
+@@ -435,6 +436,7 @@ struct pptable_funcs {
+ int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
+ int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
+ int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
++ int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
+ int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
+ int (*pre_display_config_changed)(struct smu_context *smu);
+@@ -489,6 +491,7 @@ struct pptable_funcs {
+ int (*check_fw_version)(struct smu_context *smu);
+ int (*powergate_sdma)(struct smu_context *smu, bool gate);
+ int (*powergate_vcn)(struct smu_context *smu, bool gate);
++ int (*powergate_jpeg)(struct smu_context *smu, bool gate);
+ int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
+ int (*write_pptable)(struct smu_context *smu);
+ int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4454-drm-amd-powerplay-add-JPEG-power-control-for-Navi1x.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4454-drm-amd-powerplay-add-JPEG-power-control-for-Navi1x.patch
new file mode 100644
index 00000000..5b70052c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4454-drm-amd-powerplay-add-JPEG-power-control-for-Navi1x.patch
@@ -0,0 +1,77 @@
+From 6f400e9b6048209875131ea15013028e5a3babc1 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:11:01 -0500
+Subject: [PATCH 4454/4736] drm/amd/powerplay: add JPEG power control for
+ Navi1x
+
+By separating the JPEG power feature, and using its
+own PowerUp and PowerDown messages
+
+v2: remove PowerUpJpeg message argument
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 ++++++++++++++++++++--
+ 1 file changed, 30 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 6fd808312d4e..1efe243119dd 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -383,8 +383,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+
+ if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
+- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
+- | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
++
++ if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
++ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+
+ /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
+ if (is_asic_secure(smu)) {
+@@ -664,6 +666,31 @@ static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ return ret;
+ }
+
++static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
++{
++ struct smu_power_context *smu_power = &smu->smu_power;
++ struct smu_power_gate *power_gate = &smu_power->power_gate;
++ int ret = 0;
++
++ if (enable) {
++ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++ ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
++ if (ret)
++ return ret;
++ }
++ power_gate->jpeg_gated = false;
++ } else {
++ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
++ if (ret)
++ return ret;
++ }
++ power_gate->jpeg_gated = true;
++ }
++
++ return ret;
++}
++
+ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value)
+@@ -1995,6 +2022,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
+ .set_default_dpm_table = navi10_set_default_dpm_table,
+ .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
++ .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
+ .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
+ .print_clk_levels = navi10_print_clk_levels,
+ .force_clk_levels = navi10_force_clk_levels,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4455-drm-amd-powerplay-add-Powergate-JPEG-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4455-drm-amd-powerplay-add-Powergate-JPEG-for-Renoir.patch
new file mode 100644
index 00000000..67b1ae12
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4455-drm-amd-powerplay-add-Powergate-JPEG-for-Renoir.patch
@@ -0,0 +1,102 @@
+From 50d48dd469a08fa771cf82602133304e1bcebba9 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:22:06 -0500
+Subject: [PATCH 4455/4736] drm/amd/powerplay: add Powergate JPEG for Renoir
+
+Similar to SDMA, VCN etc.
+
+v2: add argument to both PowerUpJpeg and PowerDownJpeg messages
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 ++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 ++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 +++++++++++
+ 5 files changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index f4bb804acbeb..defd083127f3 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1231,6 +1231,7 @@ static int smu_hw_init(void *handle)
+ if (adev->flags & AMD_IS_APU) {
+ smu_powergate_sdma(&adev->smu, false);
+ smu_powergate_vcn(&adev->smu, false);
++ smu_powergate_jpeg(&adev->smu, false);
+ smu_set_gfx_cgpg(&adev->smu, true);
+ }
+
+@@ -1289,6 +1290,7 @@ static int smu_hw_fini(void *handle)
+ if (adev->flags & AMD_IS_APU) {
+ smu_powergate_sdma(&adev->smu, true);
+ smu_powergate_vcn(&adev->smu, true);
++ smu_powergate_jpeg(&adev->smu, true);
+ }
+
+ ret = smu_stop_thermal_control(smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 9b9f5df0911c..1745e0146fba 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -58,6 +58,8 @@ int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
+
+ int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
+
++int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
++
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 04daf7e9fe05..492a201554e8 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -697,6 +697,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .check_fw_version = smu_v12_0_check_fw_version,
+ .powergate_sdma = smu_v12_0_powergate_sdma,
+ .powergate_vcn = smu_v12_0_powergate_vcn,
++ .powergate_jpeg = smu_v12_0_powergate_jpeg,
+ .send_smc_msg = smu_v12_0_send_msg,
+ .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ .read_smc_arg = smu_v12_0_read_arg,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index 8bcda7871309..70c4d66721cd 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -42,6 +42,8 @@
+ ((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_powergate_vcn(smu, gate) \
+ ((smu)->ppt_funcs->powergate_vcn ? (smu)->ppt_funcs->powergate_vcn((smu), (gate)) : 0)
++#define smu_powergate_jpeg(smu, gate) \
++ ((smu)->ppt_funcs->powergate_jpeg ? (smu)->ppt_funcs->powergate_jpeg((smu), (gate)) : 0)
+
+ #define smu_get_vbios_bootup_values(smu) \
+ ((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 139dd737eaa5..18b24f954380 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -203,6 +203,17 @@ int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+ return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
+ }
+
++int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate)
++{
++ if (!(smu->adev->flags & AMD_IS_APU))
++ return 0;
++
++ if (gate)
++ return smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0);
++ else
++ return smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0);
++}
++
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ {
+ if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4456-drm-amd-powerplay-add-JPEG-power-control-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4456-drm-amd-powerplay-add-JPEG-power-control-for-Renoir.patch
new file mode 100644
index 00000000..7ee8da30
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4456-drm-amd-powerplay-add-JPEG-power-control-for-Renoir.patch
@@ -0,0 +1,63 @@
+From 01eccfd69b33683292bb0c806ae62ea264bfae0b Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:33:10 -0500
+Subject: [PATCH 4456/4736] drm/amd/powerplay: add JPEG power control for
+ Renoir
+
+By using its own JPEG PowerUp and PowerDown messages
+
+v2: add argument to PowerDownJpeg message
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 26 ++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 492a201554e8..784903a313b7 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -301,6 +301,31 @@ static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ return ret;
+ }
+
++static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
++{
++ struct smu_power_context *smu_power = &smu->smu_power;
++ struct smu_power_gate *power_gate = &smu_power->power_gate;
++ int ret = 0;
++
++ if (enable) {
++ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0);
++ if (ret)
++ return ret;
++ }
++ power_gate->jpeg_gated = false;
++ } else {
++ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0);
++ if (ret)
++ return ret;
++ }
++ power_gate->jpeg_gated = true;
++ }
++
++ return ret;
++}
++
+ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ {
+ int ret = 0, i = 0;
+@@ -683,6 +708,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .print_clk_levels = renoir_print_clk_levels,
+ .get_current_power_state = renoir_get_current_power_state,
+ .dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
++ .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
+ .force_dpm_limit_value = renoir_force_dpm_limit_value,
+ .unforce_dpm_levels = renoir_unforce_dpm_levels,
+ .get_workload_type = renoir_get_workload_type,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4457-drm-amd-powerplay-set-JPEG-to-SMU-dpm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4457-drm-amd-powerplay-set-JPEG-to-SMU-dpm.patch
new file mode 100644
index 00000000..fe5f9caa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4457-drm-amd-powerplay-set-JPEG-to-SMU-dpm.patch
@@ -0,0 +1,44 @@
+From 905a3b89e3cfc064843a3c5271e2b852cbe3d7e4 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:38:08 -0500
+Subject: [PATCH 4457/4736] drm/amd/powerplay: set JPEG to SMU dpm
+
+By using its own IP block type.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
+ drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index defd083127f3..d66db86836a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -415,6 +415,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ case AMD_IP_BLOCK_TYPE_SDMA:
+ ret = smu_powergate_sdma(smu, gate);
+ break;
++ case AMD_IP_BLOCK_TYPE_JPEG:
++ ret = smu_dpm_set_jpeg_enable(smu, gate);
++ break;
+ default:
+ break;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index 70c4d66721cd..b2d81d3490cd 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -172,6 +172,8 @@
+ ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+ #define smu_dpm_set_vce_enable(smu, enable) \
+ ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
++#define smu_dpm_set_jpeg_enable(smu, enable) \
++ ((smu)->ppt_funcs->dpm_set_jpeg_enable ? (smu)->ppt_funcs->dpm_set_jpeg_enable((smu), (enable)) : 0)
+
+ #define smu_set_watermarks_table(smu, tab, clock_ranges) \
+ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4458-drm-amdgpu-enable-JPEG2.0-dpm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4458-drm-amdgpu-enable-JPEG2.0-dpm.patch
new file mode 100644
index 00000000..513e29a8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4458-drm-amdgpu-enable-JPEG2.0-dpm.patch
@@ -0,0 +1,81 @@
+From 826c350371077f7c2450fdf3e66a8431268e01f0 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 12 Nov 2019 11:57:36 -0500
+Subject: [PATCH 4458/4736] drm/amdgpu: enable JPEG2.0 dpm
+
+By using its own enabling function
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 10 +++++++++-
+ 3 files changed, 22 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 07f620938ae4..b4746dbe93a6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2715,6 +2715,18 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
+
+ }
+
++void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
++{
++ int ret = 0;
++
++ if (is_support_sw_smu(adev)) {
++ ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_JPEG, enable);
++ if (ret)
++ DRM_ERROR("[SW SMU]: dpm enable jpeg failed, state = %s, ret = %d. \n",
++ enable ? "true" : "false", ret);
++ }
++}
++
+ int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
+ {
+ int ret = 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+index ef31448ee8d8..3da1da277805 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+@@ -41,5 +41,6 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
+ void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
+ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
+ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
++void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+index 3869730b2331..a78292d84854 100644
+--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+@@ -333,6 +333,9 @@ static int jpeg_v2_0_start(struct amdgpu_device *adev)
+ struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
+ int r;
+
++ if (adev->pm.dpm_enabled)
++ amdgpu_dpm_enable_jpeg(adev, true);
++
+ /* disable power gating */
+ r = jpeg_v2_0_disable_power_gating(adev);
+ if (r)
+@@ -388,8 +391,13 @@ static int jpeg_v2_0_stop(struct amdgpu_device *adev)
+
+ /* enable power gating */
+ r = jpeg_v2_0_enable_power_gating(adev);
++ if (r)
++ return r;
+
+- return r;
++ if (adev->pm.dpm_enabled)
++ amdgpu_dpm_enable_jpeg(adev, false);
++
++ return 0;
+ }
+
+ /**
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4459-drm-amdgpu-add-driver-support-for-JPEG2.0-and-above.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4459-drm-amdgpu-add-driver-support-for-JPEG2.0-and-above.patch
new file mode 100644
index 00000000..f79285f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4459-drm-amdgpu-add-driver-support-for-JPEG2.0-and-above.patch
@@ -0,0 +1,67 @@
+From dda67852f76e087cf094ea0bed8610f27a6adbfc Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 15:00:58 -0500
+Subject: [PATCH 4459/4736] drm/amdgpu: add driver support for JPEG2.0 and
+ above
+
+By using JPEG IP block type
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++--
+ 2 files changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 8bfbcbcb7f2e..7ccc9518c173 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1963,6 +1963,7 @@ static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
+ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
++ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
+ adev->ip_blocks[i].version->funcs->set_clockgating_state) {
+ /* enable clockgating to save power */
+ r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
+@@ -1993,6 +1994,7 @@ static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_power
+ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
++ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
+ adev->ip_blocks[i].version->funcs->set_powergating_state) {
+ /* enable powergating to save power */
+ r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index ab6e0fc5800f..3a7ea8e953f8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -397,7 +397,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ ib_size_alignment = 1;
+ break;
+ case AMDGPU_HW_IP_VCN_JPEG:
+- type = AMD_IP_BLOCK_TYPE_VCN;
++ type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
++ AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
++
+ for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
+ if (adev->jpeg.harvest_config & (1 << i))
+ continue;
+@@ -535,9 +537,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ break;
+ case AMDGPU_HW_IP_VCN_DEC:
+ case AMDGPU_HW_IP_VCN_ENC:
+- case AMDGPU_HW_IP_VCN_JPEG:
+ type = AMD_IP_BLOCK_TYPE_VCN;
+ break;
++ case AMDGPU_HW_IP_VCN_JPEG:
++ type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
++ AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
++ break;
+ default:
+ return -EINVAL;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4460-drm-amdgpu-enable-JPEG2.0-for-Navi1x-and-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4460-drm-amdgpu-enable-JPEG2.0-for-Navi1x-and-Renoir.patch
new file mode 100644
index 00000000..e051b4ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4460-drm-amdgpu-enable-JPEG2.0-for-Navi1x-and-Renoir.patch
@@ -0,0 +1,65 @@
+From 8c9df10650bba97673ede035c1e5fcaba9053c87 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 15:01:42 -0500
+Subject: [PATCH 4460/4736] drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir
+
+By adding JPEG IP block to the family
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 0b8aedfe1b67..9163f3507a84 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -51,6 +51,7 @@
+ #include "gfx_v10_0.h"
+ #include "sdma_v5_0.h"
+ #include "vcn_v2_0.h"
++#include "jpeg_v2_0.h"
+ #include "dce_virtual.h"
+ #include "mes_v10_1.h"
+ #include "mxgpu_nv.h"
+@@ -462,6 +463,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ if (adev->enable_mes)
+ amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
+ break;
+@@ -485,6 +487,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 233d3850789e..46741aefc52d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -66,6 +66,7 @@
+ #include "vce_v4_0.h"
+ #include "vcn_v1_0.h"
+ #include "vcn_v2_0.h"
++#include "jpeg_v2_0.h"
+ #include "vcn_v2_5.h"
+ #include "dce_virtual.h"
+ #include "mxgpu_ai.h"
+@@ -827,6 +828,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ #endif
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ break;
+ default:
+ return -EINVAL;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4461-drm-amdgpu-move-JPEG2.5-out-from-VCN2.5.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4461-drm-amdgpu-move-JPEG2.5-out-from-VCN2.5.patch
new file mode 100644
index 00000000..7ad116bf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4461-drm-amdgpu-move-JPEG2.5-out-from-VCN2.5.patch
@@ -0,0 +1,1500 @@
+From d078a2b7be1e7ff51af6940b0dac75ff90480c7b Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 09:56:32 -0500
+Subject: [PATCH 4461/4736] drm/amdgpu: move JPEG2.5 out from VCN2.5
+
+And clean up the duplicated stuff
+
+Change-Id: Ia5502c8d4a5e1431bdd04e2392efe41f81b5ef7a
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 3 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 105 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 -
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 641 +++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h | 29 +
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 236 ---------
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 -
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +--------
+ 9 files changed, 679 insertions(+), 602 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 7cbe646d1ae1..bfcc29fdced7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -156,7 +156,8 @@ amdgpu-y += \
+ vcn_v2_5.o \
+ amdgpu_jpeg.o \
+ jpeg_v1_0.o \
+- jpeg_v2_0.o
++ jpeg_v2_0.o \
++ jpeg_v2_5.o
+
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+index 5e2e06ec13df..5131a0a1bc8a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -26,6 +26,9 @@
+
+ #define AMDGPU_MAX_JPEG_INSTANCES 2
+
++#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
++#define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)
++
+ struct amdgpu_jpeg_reg{
+ unsigned jpeg_pitch;
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 9daa42f03886..2b9ae7725f42 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -705,108 +705,3 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ amdgpu_bo_unref(&bo);
+ return r;
+ }
+-
+-int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+- uint32_t tmp = 0;
+- unsigned i;
+- int r;
+-
+- WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
+- r = amdgpu_ring_alloc(ring, 3);
+- if (r)
+- return r;
+-
+- amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0));
+- amdgpu_ring_write(ring, 0xDEADBEEF);
+- amdgpu_ring_commit(ring);
+-
+- for (i = 0; i < adev->usec_timeout; i++) {
+- tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
+- if (tmp == 0xDEADBEEF)
+- break;
+- DRM_UDELAY(1);
+- }
+-
+- if (i >= adev->usec_timeout)
+- r = -ETIMEDOUT;
+-
+- return r;
+-}
+-
+-static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
+- struct dma_fence **fence)
+-{
+- struct amdgpu_device *adev = ring->adev;
+- struct amdgpu_job *job;
+- struct amdgpu_ib *ib;
+- struct dma_fence *f = NULL;
+- const unsigned ib_size_dw = 16;
+- int i, r;
+-
+- r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+- if (r)
+- return r;
+-
+- ib = &job->ibs[0];
+-
+- ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
+- ib->ptr[1] = 0xDEADBEEF;
+- for (i = 2; i < 16; i += 2) {
+- ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
+- ib->ptr[i+1] = 0;
+- }
+- ib->length_dw = 16;
+-
+- r = amdgpu_job_submit_direct(job, ring, &f);
+- if (r)
+- goto err;
+-
+- if (fence)
+- *fence = dma_fence_get(f);
+- dma_fence_put(f);
+-
+- return 0;
+-
+-err:
+- amdgpu_job_free(job);
+- return r;
+-}
+-
+-int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+-{
+- struct amdgpu_device *adev = ring->adev;
+- uint32_t tmp = 0;
+- unsigned i;
+- struct dma_fence *fence = NULL;
+- long r = 0;
+-
+- r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
+- if (r)
+- goto error;
+-
+- r = dma_fence_wait_timeout(fence, false, timeout);
+- if (r == 0) {
+- r = -ETIMEDOUT;
+- goto error;
+- } else if (r < 0) {
+- goto error;
+- } else {
+- r = 0;
+- }
+-
+- for (i = 0; i < adev->usec_timeout; i++) {
+- tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
+- if (tmp == 0xDEADBEEF)
+- break;
+- DRM_UDELAY(1);
+- }
+-
+- if (i >= adev->usec_timeout)
+- r = -ETIMEDOUT;
+-
+- dma_fence_put(fence);
+-error:
+- return r;
+-}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+index dface275c81a..402a5046b985 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+@@ -158,7 +158,6 @@ struct amdgpu_vcn_reg{
+ unsigned ib_size;
+ unsigned gp_scratch8;
+ unsigned scratch9;
+- unsigned jpeg_pitch;
+ };
+
+ struct amdgpu_vcn_inst {
+@@ -168,7 +167,6 @@ struct amdgpu_vcn_inst {
+ void *saved_bo;
+ struct amdgpu_ring ring_dec;
+ struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+- struct amdgpu_ring ring_jpeg;
+ struct amdgpu_irq_src irq;
+ struct amdgpu_vcn_reg external;
+ };
+@@ -209,7 +207,4 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
+ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+
+-int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
+-int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+-
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+new file mode 100644
+index 000000000000..2c58939e6ad0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+@@ -0,0 +1,641 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "soc15.h"
++#include "soc15d.h"
++#include "jpeg_v2_0.h"
++
++#include "vcn/vcn_2_5_offset.h"
++#include "vcn/vcn_2_5_sh_mask.h"
++#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
++
++#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
++
++#define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2
++
++static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
++static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
++static int jpeg_v2_5_set_powergating_state(void *handle,
++ enum amd_powergating_state state);
++
++static int amdgpu_ih_clientid_jpeg[] = {
++ SOC15_IH_CLIENTID_VCN,
++ SOC15_IH_CLIENTID_VCN1
++};
++
++/**
++ * jpeg_v2_5_early_init - set function pointers
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Set ring and irq function pointers
++ */
++static int jpeg_v2_5_early_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ if (adev->asic_type == CHIP_ARCTURUS) {
++ u32 harvest;
++ int i;
++
++ adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
++ harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
++ if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
++ adev->jpeg.harvest_config |= 1 << i;
++ }
++
++ if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
++ AMDGPU_JPEG_HARVEST_JPEG1))
++ return -ENOENT;
++ } else
++ adev->jpeg.num_jpeg_inst = 1;
++
++ jpeg_v2_5_set_dec_ring_funcs(adev);
++ jpeg_v2_5_set_irq_funcs(adev);
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_5_sw_init - sw init for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Load firmware and sw initialization
++ */
++static int jpeg_v2_5_sw_init(void *handle)
++{
++ struct amdgpu_ring *ring;
++ int i, r;
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ /* JPEG TRAP */
++ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
++ VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
++ if (r)
++ return r;
++ }
++
++ r = amdgpu_jpeg_sw_init(adev);
++ if (r)
++ return r;
++
++ r = amdgpu_jpeg_resume(adev);
++ if (r)
++ return r;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ ring = &adev->jpeg.inst[i].ring_dec;
++ ring->use_doorbell = true;
++ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
++ sprintf(ring->name, "jpeg_dec_%d", i);
++ r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 0);
++ if (r)
++ return r;
++
++ adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
++ adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
++ }
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_5_sw_fini - sw fini for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * JPEG suspend and free up sw allocation
++ */
++static int jpeg_v2_5_sw_fini(void *handle)
++{
++ int r;
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++ r = amdgpu_jpeg_suspend(adev);
++ if (r)
++ return r;
++
++ r = amdgpu_jpeg_sw_fini(adev);
++
++ return r;
++}
++
++/**
++ * jpeg_v2_5_hw_init - start and test JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ */
++static int jpeg_v2_5_hw_init(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ struct amdgpu_ring *ring;
++ int i, r;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ ring = &adev->jpeg.inst[i].ring_dec;
++ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
++
++ r = amdgpu_ring_test_helper(ring);
++ if (r)
++ return r;
++ }
++
++ DRM_INFO("JPEG decode initialized successfully.\n");
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_5_hw_fini - stop the hardware block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Stop the JPEG block, mark ring as not ready any more
++ */
++static int jpeg_v2_5_hw_fini(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ struct amdgpu_ring *ring;
++ int i;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ ring = &adev->jpeg.inst[i].ring_dec;
++ if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
++ RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
++ jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
++
++ ring->sched.ready = false;
++ }
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_5_suspend - suspend JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * HW fini and suspend JPEG block
++ */
++static int jpeg_v2_5_suspend(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int r;
++
++ r = jpeg_v2_5_hw_fini(adev);
++ if (r)
++ return r;
++
++ r = amdgpu_jpeg_suspend(adev);
++
++ return r;
++}
++
++/**
++ * jpeg_v2_5_resume - resume JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Resume firmware and hw init JPEG block
++ */
++static int jpeg_v2_5_resume(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int r;
++
++ r = amdgpu_jpeg_resume(adev);
++ if (r)
++ return r;
++
++ r = jpeg_v2_5_hw_init(adev);
++
++ return r;
++}
++
++static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device* adev, int inst)
++{
++ uint32_t data;
++
++ data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
++ if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
++ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++ else
++ data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++
++ data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++ data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++ WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
++
++ data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
++ data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
++ | JPEG_CGC_GATE__JPEG2_DEC_MASK
++ | JPEG_CGC_GATE__JPEG_ENC_MASK
++ | JPEG_CGC_GATE__JMCIF_MASK
++ | JPEG_CGC_GATE__JRBBM_MASK);
++ WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
++
++ data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
++ data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
++ | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
++ | JPEG_CGC_CTRL__JMCIF_MODE_MASK
++ | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
++ WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
++}
++
++static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device* adev, int inst)
++{
++ uint32_t data;
++
++ data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
++ data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
++ |JPEG_CGC_GATE__JPEG2_DEC_MASK
++ |JPEG_CGC_GATE__JPEG_ENC_MASK
++ |JPEG_CGC_GATE__JMCIF_MASK
++ |JPEG_CGC_GATE__JRBBM_MASK);
++ WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
++}
++
++/**
++ * jpeg_v2_5_start - start JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the JPEG block
++ */
++static int jpeg_v2_5_start(struct amdgpu_device *adev)
++{
++ struct amdgpu_ring *ring;
++ int i;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ ring = &adev->jpeg.inst[i].ring_dec;
++ /* disable anti hang mechanism */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
++ ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++
++ /* JPEG disable CGC */
++ jpeg_v2_5_disable_clock_gating(adev, i);
++
++ /* MJPEG global tiling registers */
++ WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
++ adev->gfx.config.gb_addr_config);
++ WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
++ adev->gfx.config.gb_addr_config);
++
++ /* enable JMI channel */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
++ ~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++ /* enable System Interrupt for JRBC */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
++ JPEG_SYS_INT_EN__DJRBC_MASK,
++ ~JPEG_SYS_INT_EN__DJRBC_MASK);
++
++ WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
++ WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
++ WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
++ lower_32_bits(ring->gpu_addr));
++ WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
++ upper_32_bits(ring->gpu_addr));
++ WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
++ WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
++ WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
++ WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
++ ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
++ }
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_5_stop - stop JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the JPEG block
++ */
++static int jpeg_v2_5_stop(struct amdgpu_device *adev)
++{
++ int i;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ /* reset JMI */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
++ UVD_JMI_CNTL__SOFT_RESET_MASK,
++ ~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++ jpeg_v2_5_enable_clock_gating(adev, i);
++
++ /* enable anti hang mechanism */
++ WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
++ UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
++ ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++ }
++
++ return 0;
++}
++
++/**
++ * jpeg_v2_5_dec_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
++}
++
++/**
++ * jpeg_v2_5_dec_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ if (ring->use_doorbell)
++ return adev->wb.wb[ring->wptr_offs];
++ else
++ return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
++}
++
++/**
++ * jpeg_v2_5_dec_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
++{
++ struct amdgpu_device *adev = ring->adev;
++
++ if (ring->use_doorbell) {
++ adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++ WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++ } else {
++ WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++ }
++}
++
++static bool jpeg_v2_5_is_idle(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int i, ret = 1;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
++ UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
++ UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
++ }
++
++ return ret;
++}
++
++static int jpeg_v2_5_wait_for_idle(void *handle)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int i, ret = 0;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
++ UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
++ UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
++ if (ret)
++ return ret;
++ }
++
++ return ret;
++}
++
++static int jpeg_v2_5_set_clockgating_state(void *handle,
++ enum amd_clockgating_state state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
++ int i;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ if (enable) {
++ if (jpeg_v2_5_is_idle(handle))
++ return -EBUSY;
++ jpeg_v2_5_enable_clock_gating(adev, i);
++ } else {
++ jpeg_v2_5_disable_clock_gating(adev, i);
++ }
++ }
++
++ return 0;
++}
++
++static int jpeg_v2_5_set_powergating_state(void *handle,
++ enum amd_powergating_state state)
++{
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int ret;
++
++ if(state == adev->jpeg.cur_state)
++ return 0;
++
++ if (state == AMD_PG_STATE_GATE)
++ ret = jpeg_v2_5_stop(adev);
++ else
++ ret = jpeg_v2_5_start(adev);
++
++ if(!ret)
++ adev->jpeg.cur_state = state;
++
++ return ret;
++}
++
++static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ unsigned type,
++ enum amdgpu_interrupt_state state)
++{
++ return 0;
++}
++
++static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ struct amdgpu_iv_entry *entry)
++{
++ uint32_t ip_instance;
++
++ switch (entry->client_id) {
++ case SOC15_IH_CLIENTID_VCN:
++ ip_instance = 0;
++ break;
++ case SOC15_IH_CLIENTID_VCN1:
++ ip_instance = 1;
++ break;
++ default:
++ DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
++ return 0;
++ }
++
++ DRM_DEBUG("IH: JPEG TRAP\n");
++
++ switch (entry->src_id) {
++ case VCN_2_0__SRCID__JPEG_DECODE:
++ amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec);
++ break;
++ default:
++ DRM_ERROR("Unhandled interrupt: %d %d\n",
++ entry->src_id, entry->src_data[0]);
++ break;
++ }
++
++ return 0;
++}
++
++static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
++ .name = "jpeg_v2_5",
++ .early_init = jpeg_v2_5_early_init,
++ .late_init = NULL,
++ .sw_init = jpeg_v2_5_sw_init,
++ .sw_fini = jpeg_v2_5_sw_fini,
++ .hw_init = jpeg_v2_5_hw_init,
++ .hw_fini = jpeg_v2_5_hw_fini,
++ .suspend = jpeg_v2_5_suspend,
++ .resume = jpeg_v2_5_resume,
++ .is_idle = jpeg_v2_5_is_idle,
++ .wait_for_idle = jpeg_v2_5_wait_for_idle,
++ .check_soft_reset = NULL,
++ .pre_soft_reset = NULL,
++ .soft_reset = NULL,
++ .post_soft_reset = NULL,
++ .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
++ .set_powergating_state = jpeg_v2_5_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
++ .type = AMDGPU_RING_TYPE_VCN_JPEG,
++ .align_mask = 0xf,
++ .vmhub = AMDGPU_MMHUB_1,
++ .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
++ .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
++ .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
++ .emit_frame_size =
++ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++ 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
++ 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
++ 8 + 16,
++ .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
++ .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
++ .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
++ .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
++ .test_ring = amdgpu_jpeg_dec_ring_test_ring,
++ .test_ib = amdgpu_jpeg_dec_ring_test_ib,
++ .insert_nop = jpeg_v2_0_dec_ring_nop,
++ .insert_start = jpeg_v2_0_dec_ring_insert_start,
++ .insert_end = jpeg_v2_0_dec_ring_insert_end,
++ .pad_ib = amdgpu_ring_generic_pad_ib,
++ .begin_use = amdgpu_jpeg_ring_begin_use,
++ .end_use = amdgpu_jpeg_ring_end_use,
++ .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
++ .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
++ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
++static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
++{
++ int i;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
++ adev->jpeg.inst[i].ring_dec.me = i;
++ DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
++ }
++}
++
++static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
++ .set = jpeg_v2_5_set_interrupt_state,
++ .process = jpeg_v2_5_process_interrupt,
++};
++
++static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
++{
++ int i;
++
++ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++ if (adev->jpeg.harvest_config & (1 << i))
++ continue;
++
++ adev->jpeg.inst[i].irq.num_types = 1;
++ adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
++ }
++}
++
++const struct amdgpu_ip_block_version jpeg_v2_5_ip_block =
++{
++ .type = AMD_IP_BLOCK_TYPE_JPEG,
++ .major = 2,
++ .minor = 5,
++ .rev = 0,
++ .funcs = &jpeg_v2_5_ip_funcs,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+new file mode 100644
+index 000000000000..2b4087c02620
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __JPEG_V2_5_H__
++#define __JPEG_V2_5_H__
++
++extern const struct amdgpu_ip_block_version jpeg_v2_5_ip_block;
++
++#endif /* __JPEG_V2_5_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 4e0c3467deb2..7aba5a3ff3f7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -47,26 +47,6 @@
+ #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
+ #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
+
+-#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
+-#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
+-#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
+-#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
+-#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
+-#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
+-#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
+-#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
+-#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
+-#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
+-#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
+-#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec
+-#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed
+-#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085
+-#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
+-#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
+-#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
+-
+-#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
+-
+ #define mmUVD_RBC_XX_IB_REG_CHECK 0x026b
+ #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
+ #define mmUVD_REG_XX_MASK 0x026c
+@@ -1616,222 +1596,6 @@ void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_
+ amdgpu_ring_write(ring, val);
+ }
+
+-/**
+- * vcn_v2_0_jpeg_ring_insert_start - insert a start command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a start command to the ring.
+- */
+-void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
+-{
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x68e04);
+-
+- amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x80010000);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_insert_end - insert a end command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a end command to the ring.
+- */
+-void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
+-{
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x68e04);
+-
+- amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x00010000);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_emit_fence - emit an fence & trap command
+- *
+- * @ring: amdgpu_ring pointer
+- * @fence: fence to emit
+- *
+- * Write a fence and a trap command to the ring.
+- */
+-void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+- unsigned flags)
+-{
+- WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, seq);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, seq);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, lower_32_bits(addr));
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, upper_32_bits(addr));
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x8);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
+- 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
+- amdgpu_ring_write(ring, 0);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x3fbc);
+-
+- amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x1);
+-
+- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
+- amdgpu_ring_write(ring, 0);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_emit_ib - execute indirect buffer
+- *
+- * @ring: amdgpu_ring pointer
+- * @ib: indirect buffer to execute
+- *
+- * Write ring commands to execute the indirect buffer.
+- */
+-void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
+- struct amdgpu_job *job,
+- struct amdgpu_ib *ib,
+- uint32_t flags)
+-{
+- unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, ib->length_dw);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
+-
+- amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
+- amdgpu_ring_write(ring, 0);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x01400200);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x2);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
+- 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
+- amdgpu_ring_write(ring, 0x2);
+-}
+-
+-void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+- uint32_t val, uint32_t mask)
+-{
+- uint32_t reg_offset = (reg << 2);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, 0x01400200);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- amdgpu_ring_write(ring, val);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring,
+- PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
+- } else {
+- amdgpu_ring_write(ring, reg_offset);
+- amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+- 0, 0, PACKETJ_TYPE3));
+- }
+- amdgpu_ring_write(ring, mask);
+-}
+-
+-void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, uint64_t pd_addr)
+-{
+- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+- uint32_t data0, data1, mask;
+-
+- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+-
+- /* wait for register write */
+- data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
+- data1 = lower_32_bits(pd_addr);
+- mask = 0xffffffff;
+- vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
+-}
+-
+-void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
+-{
+- uint32_t reg_offset = (reg << 2);
+-
+- amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+- 0, 0, PACKETJ_TYPE0));
+- if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
+- amdgpu_ring_write(ring, 0);
+- amdgpu_ring_write(ring,
+- PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
+- } else {
+- amdgpu_ring_write(ring, reg_offset);
+- amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+- 0, 0, PACKETJ_TYPE0));
+- }
+- amdgpu_ring_write(ring, val);
+-}
+-
+-void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
+-{
+- int i;
+-
+- WARN_ON(ring->wptr % 2 || count % 2);
+-
+- for (i = 0; i < count / 2; i++) {
+- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+- amdgpu_ring_write(ring, 0);
+- }
+-}
+-
+ static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned type,
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
+index 8467292f32e5..ef749b02ded9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
+@@ -49,19 +49,6 @@ extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ unsigned int vmid, uint64_t pd_addr);
+ extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+
+-extern void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring);
+-extern void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring);
+-extern void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+- unsigned flags);
+-extern void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
+- struct amdgpu_ib *ib, uint32_t flags);
+-extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+- uint32_t val, uint32_t mask);
+-extern void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+- unsigned vmid, uint64_t pd_addr);
+-extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+-extern void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count);
+-
+ extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block;
+
+ #endif /* __VCN_V2_0_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index ff6cc77ad0b0..98f423f30d2f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -47,13 +47,10 @@
+ #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
+ #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
+
+-#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
+-
+-#define VCN25_MAX_HW_INSTANCES_ARCTURUS 2
++#define VCN25_MAX_HW_INSTANCES_ARCTURUS 2
+
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
+-static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
+ static int vcn_v2_5_set_powergating_state(void *handle,
+ enum amd_powergating_state state);
+@@ -95,7 +92,6 @@ static int vcn_v2_5_early_init(void *handle)
+
+ vcn_v2_5_set_dec_ring_funcs(adev);
+ vcn_v2_5_set_enc_ring_funcs(adev);
+- vcn_v2_5_set_jpeg_ring_funcs(adev);
+ vcn_v2_5_set_irq_funcs(adev);
+
+ return 0;
+@@ -130,12 +126,6 @@ static int vcn_v2_5_sw_init(void *handle)
+ if (r)
+ return r;
+ }
+-
+- /* VCN JPEG TRAP */
+- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
+- VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[j].irq);
+- if (r)
+- return r;
+ }
+
+ r = amdgpu_vcn_sw_init(adev);
+@@ -184,9 +174,6 @@ static int vcn_v2_5_sw_init(void *handle)
+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
+
+- adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+- adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH);
+-
+ ring = &adev->vcn.inst[j].ring_dec;
+ ring->use_doorbell = true;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8*j;
+@@ -204,14 +191,6 @@ static int vcn_v2_5_sw_init(void *handle)
+ if (r)
+ return r;
+ }
+-
+- ring = &adev->vcn.inst[j].ring_jpeg;
+- ring->use_doorbell = true;
+- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8*j;
+- sprintf(ring->name, "vcn_jpeg_%d", j);
+- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
+- if (r)
+- return r;
+ }
+
+ return 0;
+@@ -269,12 +248,8 @@ static int vcn_v2_5_hw_init(void *handle)
+ if (r)
+ goto done;
+ }
+-
+- ring = &adev->vcn.inst[j].ring_jpeg;
+- r = amdgpu_ring_test_helper(ring);
+- if (r)
+- goto done;
+ }
++
+ done:
+ if (!r)
+ DRM_INFO("VCN decode and encode initialized successfully.\n");
+@@ -309,9 +284,6 @@ static int vcn_v2_5_hw_fini(void *handle)
+ ring = &adev->vcn.inst[i].ring_enc[i];
+ ring->sched.ready = false;
+ }
+-
+- ring = &adev->vcn.inst[i].ring_jpeg;
+- ring->sched.ready = false;
+ }
+
+ return 0;
+@@ -592,115 +564,6 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+ }
+ }
+
+-/**
+- * jpeg_v2_5_start - start JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * Setup and start the JPEG block
+- */
+-static int jpeg_v2_5_start(struct amdgpu_device *adev)
+-{
+- struct amdgpu_ring *ring;
+- uint32_t tmp;
+- int i;
+-
+- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+- if (adev->vcn.harvest_config & (1 << i))
+- continue;
+- ring = &adev->vcn.inst[i].ring_jpeg;
+- /* disable anti hang mechanism */
+- WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0,
+- ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+-
+- /* JPEG disable CGC */
+- tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
+- tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+- tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+- tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+- WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
+-
+- tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
+- tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
+- | JPEG_CGC_GATE__JPEG2_DEC_MASK
+- | JPEG_CGC_GATE__JMCIF_MASK
+- | JPEG_CGC_GATE__JRBBM_MASK);
+- WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
+-
+- tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
+- tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
+- | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
+- | JPEG_CGC_CTRL__JMCIF_MODE_MASK
+- | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
+- WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
+-
+- /* MJPEG global tiling registers */
+- WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
+- adev->gfx.config.gb_addr_config);
+- WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
+- adev->gfx.config.gb_addr_config);
+-
+- /* enable JMI channel */
+- WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0,
+- ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+- /* enable System Interrupt for JRBC */
+- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN),
+- JPEG_SYS_INT_EN__DJRBC_MASK,
+- ~JPEG_SYS_INT_EN__DJRBC_MASK);
+-
+- WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_VMID, 0);
+- WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+- WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
+- lower_32_bits(ring->gpu_addr));
+- WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
+- upper_32_bits(ring->gpu_addr));
+- WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0);
+- WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0);
+- WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+- WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
+- ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR);
+- }
+-
+- return 0;
+-}
+-
+-/**
+- * jpeg_v2_5_stop - stop JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * stop the JPEG block
+- */
+-static int jpeg_v2_5_stop(struct amdgpu_device *adev)
+-{
+- uint32_t tmp;
+- int i;
+-
+- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+- if (adev->vcn.harvest_config & (1 << i))
+- continue;
+- /* reset JMI */
+- WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL),
+- UVD_JMI_CNTL__SOFT_RESET_MASK,
+- ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+- tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
+- tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
+- |JPEG_CGC_GATE__JPEG2_DEC_MASK
+- |JPEG_CGC_GATE__JMCIF_MASK
+- |JPEG_CGC_GATE__JRBBM_MASK);
+- WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
+-
+- /* enable anti hang mechanism */
+- WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS),
+- UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
+- ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+- }
+-
+- return 0;
+-}
+-
+ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ {
+ struct amdgpu_ring *ring;
+@@ -874,19 +737,14 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ }
+- r = jpeg_v2_5_start(adev);
+
+- return r;
++ return 0;
+ }
+
+ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ {
+ uint32_t tmp;
+- int i, r;
+-
+- r = jpeg_v2_5_stop(adev);
+- if (r)
+- return r;
++ int i, r = 0;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+@@ -1125,86 +983,6 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+
+-/**
+- * vcn_v2_5_jpeg_ring_get_rptr - get read pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware read pointer
+- */
+-static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR);
+-}
+-
+-/**
+- * vcn_v2_5_jpeg_ring_get_wptr - get write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware write pointer
+- */
+-static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- if (ring->use_doorbell)
+- return adev->wb.wb[ring->wptr_offs];
+- else
+- return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR);
+-}
+-
+-/**
+- * vcn_v2_5_jpeg_ring_set_wptr - set write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Commits the write pointer to the hardware
+- */
+-static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+-{
+- struct amdgpu_device *adev = ring->adev;
+-
+- if (ring->use_doorbell) {
+- adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+- WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+- } else {
+- WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+- }
+-}
+-
+-static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
+- .type = AMDGPU_RING_TYPE_VCN_JPEG,
+- .align_mask = 0xf,
+- .vmhub = AMDGPU_MMHUB_1,
+- .get_rptr = vcn_v2_5_jpeg_ring_get_rptr,
+- .get_wptr = vcn_v2_5_jpeg_ring_get_wptr,
+- .set_wptr = vcn_v2_5_jpeg_ring_set_wptr,
+- .emit_frame_size =
+- SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+- SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+- 8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
+- 18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
+- 8 + 16,
+- .emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
+- .emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
+- .emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
+- .emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
+- .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
+- .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
+- .insert_nop = vcn_v2_0_jpeg_ring_nop,
+- .insert_start = vcn_v2_0_jpeg_ring_insert_start,
+- .insert_end = vcn_v2_0_jpeg_ring_insert_end,
+- .pad_ib = amdgpu_ring_generic_pad_ib,
+- .begin_use = amdgpu_vcn_ring_begin_use,
+- .end_use = amdgpu_vcn_ring_end_use,
+- .emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
+- .emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
+- .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+-};
+-
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ int i;
+@@ -1233,19 +1011,6 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+ }
+ }
+
+-static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+-{
+- int i;
+-
+- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+- if (adev->vcn.harvest_config & (1 << i))
+- continue;
+- adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
+- adev->vcn.inst[i].ring_jpeg.me = i;
+- DRM_INFO("VCN(%d) jpeg decode is enabled in VM mode\n", i);
+- }
+-}
+-
+ static bool vcn_v2_5_is_idle(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -1352,9 +1117,6 @@ static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
+ case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+ amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
+ break;
+- case VCN_2_0__SRCID__JPEG_DECODE:
+- amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_jpeg);
+- break;
+ default:
+ DRM_ERROR("Unhandled interrupt: %d %d\n",
+ entry->src_id, entry->src_data[0]);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4462-drm-amdgpu-enable-Arcturus-CG-for-VCN-and-JPEG-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4462-drm-amdgpu-enable-Arcturus-CG-for-VCN-and-JPEG-block.patch
new file mode 100644
index 00000000..a0721f24
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4462-drm-amdgpu-enable-Arcturus-CG-for-VCN-and-JPEG-block.patch
@@ -0,0 +1,32 @@
+From c3574eb989136807e0d18af9751a29899aba2370 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 10:27:03 -0500
+Subject: [PATCH 4462/4736] drm/amdgpu: enable Arcturus CG for VCN and JPEG
+ blocks
+
+Arcturus VCN and JPEG only got CG support, and no PG support
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 46741aefc52d..bfe82966626f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1212,7 +1212,9 @@ static int soc15_common_early_init(void *handle)
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS |
+- AMD_CG_SUPPORT_IH_CG;
++ AMD_CG_SUPPORT_IH_CG |
++ AMD_CG_SUPPORT_VCN_MGCG |
++ AMD_CG_SUPPORT_JPEG_MGCG;
+ adev->pg_flags = 0;
+ adev->external_rev_id = adev->rev_id + 0x32;
+ break;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4463-drm-amdgpu-enable-Arcturus-JPEG2.5-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4463-drm-amdgpu-enable-Arcturus-JPEG2.5-block.patch
new file mode 100644
index 00000000..2d3135ff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4463-drm-amdgpu-enable-Arcturus-JPEG2.5-block.patch
@@ -0,0 +1,36 @@
+From d2f79333dd34c1cbb736976a6c46ea12aab53b70 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 10:33:57 -0500
+Subject: [PATCH 4463/4736] drm/amdgpu: enable Arcturus JPEG2.5 block
+
+It also doen't care about FW loading type, so enabling it directly.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index bfe82966626f..fea3222c40bc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -68,6 +68,7 @@
+ #include "vcn_v2_0.h"
+ #include "jpeg_v2_0.h"
+ #include "vcn_v2_5.h"
++#include "jpeg_v2_5.h"
+ #include "dce_virtual.h"
+ #include "mxgpu_ai.h"
+ #include "amdgpu_smu.h"
+@@ -810,6 +811,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+
+ if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
+ amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
++ amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
+ break;
+ case CHIP_RENOIR:
+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4464-drm-amd-display-remove-set-but-not-used-variable-old.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4464-drm-amd-display-remove-set-but-not-used-variable-old.patch
new file mode 100644
index 00000000..42fd019e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4464-drm-amd-display-remove-set-but-not-used-variable-old.patch
@@ -0,0 +1,48 @@
+From 4aaf0fc347483a6dabdf6f101ea5efff193d53b4 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:24 +0800
+Subject: [PATCH 4464/4736] drm/amd/display: remove set but not used variable
+ 'old_plane_crtc'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function dm_determine_update_type_for_commit:
+drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6516:36: warning: variable old_plane_crtc set but not used [-Wunused-but-set-variable]
+
+It is introduced by commit a87fa9938749 ("drm/amd/display:
+Build stream update and plane updates in dm"), but never used,
+so remove it.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 95cfe4213362..ec9fac7d4559 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -7495,7 +7495,7 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
+ int i, j, num_plane, ret = 0;
+ struct drm_plane_state *old_plane_state, *new_plane_state;
+ struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
+- struct drm_crtc *new_plane_crtc, *old_plane_crtc;
++ struct drm_crtc *new_plane_crtc;
+ struct drm_plane *plane;
+
+ struct drm_crtc *crtc;
+@@ -7541,7 +7541,6 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
+ uint64_t tiling_flags;
+
+ new_plane_crtc = new_plane_state->crtc;
+- old_plane_crtc = old_plane_state->crtc;
+ new_dm_plane_state = to_dm_plane_state(new_plane_state);
+ old_dm_plane_state = to_dm_plane_state(old_plane_state);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4465-drm-amd-display-remove-set-but-not-used-variable-bp-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4465-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
new file mode 100644
index 00000000..303ae0d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4465-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
@@ -0,0 +1,46 @@
+From d893e6ec4d584cc6f51cd1607ecbb7a02e2d2e2b Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:25 +0800
+Subject: [PATCH 4465/4736] drm/amd/display: remove set but not used variable
+ 'bp' in bios_parser2.c
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c: In function bios_get_board_layout_info:
+drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c:1826:22: warning: variable bp set but not used [-Wunused-but-set-variable]
+
+It is introduced by commit 1eeedbcc20d6 ("drm/amd/display:
+get board layout for edid emulation"), but never used,
+so remove it.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 3e2f21af2be7..884b07774f6d 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1838,7 +1838,6 @@ static enum bp_result bios_get_board_layout_info(
+ struct board_layout_info *board_layout_info)
+ {
+ unsigned int i;
+- struct bios_parser *bp;
+ enum bp_result record_result;
+
+ const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
+@@ -1847,7 +1846,6 @@ static enum bp_result bios_get_board_layout_info(
+ 0, 0
+ };
+
+- bp = BP_FROM_DCB(dcb);
+ if (board_layout_info == NULL) {
+ DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
+ return BP_RESULT_BADINPUT;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4466-drm-amd-display-remove-set-but-not-used-variable-bp-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4466-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
new file mode 100644
index 00000000..6d2afeb6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4466-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
@@ -0,0 +1,46 @@
+From f897d81ca52f3e03b453d47479292471a55a9191 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:26 +0800
+Subject: [PATCH 4466/4736] drm/amd/display: remove set but not used variable
+ 'bp' in bios_parser.c
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser.c: In function bios_get_board_layout_info:
+drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2743:22: warning: variable bp set but not used [-Wunused-but-set-variable]
+
+It is introduced by commit 1eeedbcc20d6 ("drm/amd/display:
+get board layout for edid emulation"), but never used,
+so remove it.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 7466e6332299..0d4993691199 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2737,7 +2737,6 @@ static enum bp_result bios_get_board_layout_info(
+ struct board_layout_info *board_layout_info)
+ {
+ unsigned int i;
+- struct bios_parser *bp;
+ enum bp_result record_result;
+
+ const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
+@@ -2746,7 +2745,6 @@ static enum bp_result bios_get_board_layout_info(
+ 0, 0
+ };
+
+- bp = BP_FROM_DCB(dcb);
+ if (board_layout_info == NULL) {
+ DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
+ return BP_RESULT_BADINPUT;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4467-drm-amd-display-remove-set-but-not-used-variable-min.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4467-drm-amd-display-remove-set-but-not-used-variable-min.patch
new file mode 100644
index 00000000..73eb40d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4467-drm-amd-display-remove-set-but-not-used-variable-min.patch
@@ -0,0 +1,45 @@
+From 8f25ee16ced424a3d2bd8af0a3513a0feeb372d4 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:27 +0800
+Subject: [PATCH 4467/4736] drm/amd/display: remove set but not used variable
+ 'min_content'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/modules/color/color_gamma.c: In function build_freesync_hdr:
+drivers/gpu/drm/amd/display/modules/color/color_gamma.c:830:20: warning: variable min_content set but not used [-Wunused-but-set-variable]
+
+It is not used since commit 50575eb5b339 ("drm/amd/display:
+Only use EETF when maxCL > max display")
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 962a57f75e12..3f467c98b02f 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -934,7 +934,6 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ struct fixed31_32 max_display;
+ struct fixed31_32 min_display;
+ struct fixed31_32 max_content;
+- struct fixed31_32 min_content;
+ struct fixed31_32 clip = dc_fixpt_one;
+ struct fixed31_32 output;
+ bool use_eetf = false;
+@@ -948,7 +947,6 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ max_display = dc_fixpt_from_int(fs_params->max_display);
+ min_display = dc_fixpt_from_fraction(fs_params->min_display, 10000);
+ max_content = dc_fixpt_from_int(fs_params->max_content);
+- min_content = dc_fixpt_from_fraction(fs_params->min_content, 10000);
+ sdr_white_level = dc_fixpt_from_int(fs_params->sdr_white_level);
+
+ if (fs_params->min_display > 1000) // cap at 0.1 at the bottom
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4468-drm-amdgpu-dm-Do-not-throw-an-error-for-a-display-wi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4468-drm-amdgpu-dm-Do-not-throw-an-error-for-a-display-wi.patch
new file mode 100644
index 00000000..6150b42b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4468-drm-amdgpu-dm-Do-not-throw-an-error-for-a-display-wi.patch
@@ -0,0 +1,38 @@
+From 9ab22e7215390717598165b675ef41eb105eeb91 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Thu, 14 Nov 2019 20:44:13 +0000
+Subject: [PATCH 4468/4736] drm/amdgpu/dm: Do not throw an error for a display
+ with no audio
+
+An old display with no audio may not have an EDID with a CEA block, or
+it may simply be too old to support audio. This is not a driver error,
+so don't flag it as such.
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112140
+References: ae2a3495973e ("drm/amd: be quiet when no SAD block is found")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Jean Delvare <jdelvare@suse.de>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index d14284602ced..92ba7ca84d7c 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -98,8 +98,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
+ (struct edid *) edid->raw_edid);
+
+ sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
+- if (sad_count < 0)
+- DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
+ if (sad_count <= 0)
+ return result;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch
new file mode 100644
index 00000000..9e104fd6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch
@@ -0,0 +1,90 @@
+From a1a63a29b5717b05ea6b8e9a9a3982adfade96d4 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 11 Nov 2019 17:15:02 +0800
+Subject: [PATCH 4469/4736] drm/amd/powerplay: avoid DPM reenable process on
+ Navi1x ASICs V2
+
+Otherwise, without RLC reinitialization, the DPM reenablement
+will fail. That affects the custom pptable uploading.
+
+V2: setting/clearing uploading_custom_pp_table in
+ smu_sys_set_pp_table()
+
+Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
+Reported-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Tested-by: Matt Coffin <mcoffin13@gmail.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 31 ++++++++++++++++---
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
+ 2 files changed, 28 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d66db86836a1..9483f5ff64e7 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -594,10 +594,18 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
+ smu_table->power_play_table = smu_table->hardcode_pptable;
+ smu_table->power_play_table_size = size;
+
++ /*
++ * Special hw_fini action(for Navi1x, the DPMs disablement will be
++ * skipped) may be needed for custom pptable uploading.
++ */
++ smu->uploading_custom_pp_table = true;
++
+ ret = smu_reset(smu);
+ if (ret)
+ pr_info("smu reset failed, ret = %d\n", ret);
+
++ smu->uploading_custom_pp_table = false;
++
+ failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
+@@ -1302,10 +1310,25 @@ static int smu_hw_fini(void *handle)
+ return ret;
+ }
+
+- ret = smu_stop_dpms(smu);
+- if (ret) {
+- pr_warn("Fail to stop Dpms!\n");
+- return ret;
++ /*
++ * For custom pptable uploading, skip the DPM features
++ * disable process on Navi1x ASICs.
++ * - As the gfx related features are under control of
++ * RLC on those ASICs. RLC reinitialization will be
++ * needed to reenable them. That will cost much more
++ * efforts.
++ *
++ * - SMU firmware can handle the DPM reenablement
++ * properly.
++ */
++ if (!smu->uploading_custom_pp_table ||
++ !((adev->asic_type >= CHIP_NAVI10) &&
++ (adev->asic_type <= CHIP_NAVI12))) {
++ ret = smu_stop_dpms(smu);
++ if (ret) {
++ pr_warn("Fail to stop Dpms!\n");
++ return ret;
++ }
+ }
+
+ kfree(table_context->driver_pptable);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index cdd46cdaffb8..5bac7efcd6ee 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -391,6 +391,7 @@ struct smu_context
+
+ uint32_t smc_if_version;
+
++ bool uploading_custom_pp_table;
+ };
+
+ struct i2c_adapter;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4470-drm-amd-powerplay-issue-BTC-on-Navi-during-SMU-setup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4470-drm-amd-powerplay-issue-BTC-on-Navi-during-SMU-setup.patch
new file mode 100644
index 00000000..6dbab59a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4470-drm-amd-powerplay-issue-BTC-on-Navi-during-SMU-setup.patch
@@ -0,0 +1,48 @@
+From ce9a49c741e9182e8ae23a9c7b774408aa33d942 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 12 Nov 2019 14:18:54 +0800
+Subject: [PATCH 4470/4736] drm/amd/powerplay: issue BTC on Navi during SMU
+ setup
+
+RunBTC is added for Navi ASIC on hardware setup.
+
+Change-Id: I1c04b481ed14d5f12c20b7b0d592b62a65889e4a
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 1efe243119dd..e0bc4f73dae9 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -2007,6 +2007,17 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
+ return ret;
+ }
+
++static int navi10_run_btc(struct smu_context *smu)
++{
++ int ret = 0;
++
++ ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc);
++ if (ret)
++ pr_err("RunBtc failed!\n");
++
++ return ret;
++}
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ .tables_init = navi10_tables_init,
+ .alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -2099,6 +2110,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .set_default_od_settings = navi10_set_default_od_settings,
+ .od_edit_dpm_table = navi10_od_edit_dpm_table,
+ .get_pptable_power_limit = navi10_get_pptable_power_limit,
++ .run_btc = navi10_run_btc,
+ };
+
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4471-drm-amd-powerplay-issue-no-PPSMC_MSG_GetCurrPkgPwr-o.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4471-drm-amd-powerplay-issue-no-PPSMC_MSG_GetCurrPkgPwr-o.patch
new file mode 100644
index 00000000..a840d469
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4471-drm-amd-powerplay-issue-no-PPSMC_MSG_GetCurrPkgPwr-o.patch
@@ -0,0 +1,59 @@
+From d1cfc704affbbc82579adff6d3a769b38d9f6500 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 14 Nov 2019 15:30:39 +0800
+Subject: [PATCH 4471/4736] drm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr
+ on unsupported ASICs
+
+Otherwise, the error message prompted will confuse user.
+
+Change-Id: I44b9f870a8663714d715a1d5bf2aa24abe75bb8e
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 23 +++++++++++++++----
+ 1 file changed, 18 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index d3c3b3512a16..5c6b71b356e7 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -3476,18 +3476,31 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
+
+ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
+ {
++ struct amdgpu_device *adev = hwmgr->adev;
+ int i;
+ u32 tmp = 0;
+
+ if (!query)
+ return -EINVAL;
+
+- smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
+- tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+- *query = tmp;
++ /*
++ * PPSMC_MSG_GetCurrPkgPwr is not supported on:
++ * - Hawaii
++ * - Bonaire
++ * - Fiji
++ * - Tonga
++ */
++ if ((adev->asic_type != CHIP_HAWAII) &&
++ (adev->asic_type != CHIP_BONAIRE) &&
++ (adev->asic_type != CHIP_FIJI) &&
++ (adev->asic_type != CHIP_TONGA)) {
++ smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
++ tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
++ *query = tmp;
+
+- if (tmp != 0)
+- return 0;
++ if (tmp != 0)
++ return 0;
++ }
+
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
+ cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4472-drm-amd-powerplay-correct-fine-grained-dpm-force-lev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4472-drm-amd-powerplay-correct-fine-grained-dpm-force-lev.patch
new file mode 100644
index 00000000..b9de8740
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4472-drm-amd-powerplay-correct-fine-grained-dpm-force-lev.patch
@@ -0,0 +1,38 @@
+From 1572e7a9f2a2906fb27b0f79b0a64fbf2eaa9e01 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 14 Nov 2019 16:58:31 +0800
+Subject: [PATCH 4472/4736] drm/amd/powerplay: correct fine grained dpm force
+ level setting
+
+For fine grained dpm, there is only two levels supported. However
+to reflect correctly the current clock frequency, there is an
+intermediate level faked. Thus on forcing level setting, we
+need to treat level 2 correctly as level 1.
+
+Change-Id: I32f936636f27eb8d8d9002bedd701f2bb0d3060a
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index e0bc4f73dae9..8d5f33baaa77 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -886,6 +886,12 @@ static int navi10_force_clk_levels(struct smu_context *smu,
+ case SMU_UCLK:
+ case SMU_DCEFCLK:
+ case SMU_FCLK:
++ /* There is only 2 levels for fine grained DPM */
++ if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
++ soft_max_level = (soft_max_level >= 1 ? 1 : 0);
++ soft_min_level = (soft_min_level >= 1 ? 1 : 0);
++ }
++
+ ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
+ if (ret)
+ return size;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4473-drm-amd-display-Renoir-chroma-viewport-WA-change-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4473-drm-amd-display-Renoir-chroma-viewport-WA-change-for.patch
new file mode 100644
index 00000000..5e7d191a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4473-drm-amd-display-Renoir-chroma-viewport-WA-change-for.patch
@@ -0,0 +1,41 @@
+From 5ba99cdaa75b41227f78ad74625b07a686bc0279 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Thu, 17 Oct 2019 11:56:34 -0400
+Subject: [PATCH 4473/4736] drm/amd/display: Renoir chroma viewport WA change
+ formula
+
+[why]
+we want to increase the pte row plus 1 line if chroma viewport
+height is integer multiple of the pte row height
+
+[how]
+instead of ceiling viewport height, we floor it. this allows
+us to accommodate both cases: those where the chroma viewport
+height is integer multiple of the pte row height and those where
+it is not
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 1ddd6ae22155..d86b6b6211bc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -204,8 +204,8 @@ void hubp21_set_viewport(
+ PTE_ROW_HEIGHT_LINEAR, &pte_row_height);
+
+ pte_row_height = 1 << (pte_row_height + 3);
+- pte_rows = (viewport_c->height + pte_row_height - 1) / pte_row_height;
+- patched_viewport_height = pte_rows * pte_row_height + 3;
++ pte_rows = (viewport_c->height / pte_row_height) + 1;
++ patched_viewport_height = pte_rows * pte_row_height + 1;
+ }
+
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4474-drm-amd-display-Renoir-chroma-viewport-WA-Read-the-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4474-drm-amd-display-Renoir-chroma-viewport-WA-Read-the-c.patch
new file mode 100644
index 00000000..9efd8311
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4474-drm-amd-display-Renoir-chroma-viewport-WA-Read-the-c.patch
@@ -0,0 +1,40 @@
+From bf8935938a1e4b88d9c1edea7ff93957b2d096e7 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Thu, 24 Oct 2019 13:55:10 -0400
+Subject: [PATCH 4474/4736] drm/amd/display: Renoir chroma viewport WA Read the
+ correct register
+
+[why]
+Before we were reading registers specific to luma size, which caused a black line
+to appear on the screen from time to time, as although the luma row height
+is generally the same as the chroma row height for the video case, it will sometimes
+be one more
+
+[how]
+Read the register specific for the chroma size
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index d86b6b6211bc..32e8b589aeb5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -200,8 +200,8 @@ void hubp21_set_viewport(
+ int pte_row_height = 0;
+ int pte_rows = 0;
+
+- REG_GET(DCHUBP_REQ_SIZE_CONFIG,
+- PTE_ROW_HEIGHT_LINEAR, &pte_row_height);
++ REG_GET(DCHUBP_REQ_SIZE_CONFIG_C,
++ PTE_ROW_HEIGHT_LINEAR_C, &pte_row_height);
+
+ pte_row_height = 1 << (pte_row_height + 3);
+ pte_rows = (viewport_c->height / pte_row_height) + 1;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4475-drm-amd-display-Add-hubp-clock-status-in-DTN-log-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4475-drm-amd-display-Add-hubp-clock-status-in-DTN-log-for.patch
new file mode 100644
index 00000000..2e708fec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4475-drm-amd-display-Add-hubp-clock-status-in-DTN-log-for.patch
@@ -0,0 +1,37 @@
+From d6aad171628f54a3c309e4007e94fa31cb6bfae9 Mon Sep 17 00:00:00 2001
+From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
+Date: Fri, 25 Oct 2019 09:40:13 -0400
+Subject: [PATCH 4475/4736] drm/amd/display: Add hubp clock status in DTN log
+ for Navi
+
+[Why]
+For debug purpose, we need to check HUBP_CLOCK_ENABLE in DTN
+log debugfs on Navi.
+
+[How]
+Add related register read in dcn20_hubp.c.
+
+Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 69e2aae42394..391f0629b955 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -1204,6 +1204,9 @@ void hubp2_read_state_common(struct hubp *hubp)
+ HUBP_TTU_DISABLE, &s->ttu_disable,
+ HUBP_UNDERFLOW_STATUS, &s->underflow_status);
+
++ REG_GET(HUBP_CLK_CNTL,
++ HUBP_CLOCK_ENABLE, &s->clock_en);
++
+ REG_GET(DCN_GLOBAL_TTU_CNTL,
+ MIN_TTU_VBLANK, &s->min_ttu_vblank);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4476-drm-amd-display-Update-background-color-in-bottommos.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4476-drm-amd-display-Update-background-color-in-bottommos.patch
new file mode 100644
index 00000000..1cbacf38
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4476-drm-amd-display-Update-background-color-in-bottommos.patch
@@ -0,0 +1,60 @@
+From 005868d633f371451d5954e6ad62e5be20745f9f Mon Sep 17 00:00:00 2001
+From: Hugo Hu <hugo.hu@amd.com>
+Date: Fri, 25 Oct 2019 15:33:15 +0800
+Subject: [PATCH 4476/4736] drm/amd/display: Update background color in
+ bottommost mpcc
+
+[Why]
+Background color only takes effect in bottommost mpcc.
+
+[How]
+Update background color in bottommost mpcc.
+
+Signed-off-by: Hugo Hu <hugo.hu@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+index 8b2f29f6dabd..b3f66e1de15d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+@@ -42,20 +42,27 @@ void mpc1_set_bg_color(struct mpc *mpc,
+ int mpcc_id)
+ {
+ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
++ struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
++ uint32_t bg_r_cr, bg_g_y, bg_b_cb;
++
++ /* find bottommost mpcc. */
++ while (bottommost_mpcc->mpcc_bot) {
++ bottommost_mpcc = bottommost_mpcc->mpcc_bot;
++ }
+
+ /* mpc color is 12 bit. tg_color is 10 bit */
+ /* todo: might want to use 16 bit to represent color and have each
+ * hw block translate to correct color depth.
+ */
+- uint32_t bg_r_cr = bg_color->color_r_cr << 2;
+- uint32_t bg_g_y = bg_color->color_g_y << 2;
+- uint32_t bg_b_cb = bg_color->color_b_cb << 2;
++ bg_r_cr = bg_color->color_r_cr << 2;
++ bg_g_y = bg_color->color_g_y << 2;
++ bg_b_cb = bg_color->color_b_cb << 2;
+
+- REG_SET(MPCC_BG_R_CR[mpcc_id], 0,
++ REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
+ MPCC_BG_R_CR, bg_r_cr);
+- REG_SET(MPCC_BG_G_Y[mpcc_id], 0,
++ REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
+ MPCC_BG_G_Y, bg_g_y);
+- REG_SET(MPCC_BG_B_CB[mpcc_id], 0,
++ REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
+ MPCC_BG_B_CB, bg_b_cb);
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4477-drm-amd-display-3.2.59.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4477-drm-amd-display-3.2.59.patch
new file mode 100644
index 00000000..b67d4c6b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4477-drm-amd-display-3.2.59.patch
@@ -0,0 +1,28 @@
+From f586a397a67b59604c7e8a21218906739f13c80a Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 28 Oct 2019 08:50:33 -0400
+Subject: [PATCH 4477/4736] drm/amd/display: 3.2.59
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 8ff7556eb2c4..b107d6fab972 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.58"
++#define DC_VER "3.2.59"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4478-drm-amd-display-Fix-stereo-with-DCC-enabled.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4478-drm-amd-display-Fix-stereo-with-DCC-enabled.patch
new file mode 100644
index 00000000..2f7c0d11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4478-drm-amd-display-Fix-stereo-with-DCC-enabled.patch
@@ -0,0 +1,81 @@
+From 385499bca1590635946ebbfe750900f92baaf8b5 Mon Sep 17 00:00:00 2001
+From: Samson Tam <Samson.Tam@amd.com>
+Date: Wed, 23 Oct 2019 21:36:29 -0400
+Subject: [PATCH 4478/4736] drm/amd/display: Fix stereo with DCC enabled
+
+[Why]
+When sending DCC with Stereo, DCC gets enabled but the meta addresses
+are 0. This happens momentarily before the meta addresses are populated
+with a valid address.
+
+[How]
+Add call validate_dcc_with_meta_address() in
+copy_surface_update_to_plane() to check for surface address and DCC
+change.
+When DCC has changed, check if DCC enable is true but meta address is 0.
+If so, we turn DCC enable to false. When surface address has changed, we
+check if DCC enable is false but meta address is not 0. If so, we turn
+DCC enable back to true. This will restore DCC enable to the proper
+setting once the meta address is valid.
+
+Signed-off-by: Samson Tam <Samson.Tam@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 27 ++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 9e600d3e2fd8..7a2cdf21ca34 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1764,12 +1764,37 @@ static struct dc_stream_status *stream_get_status(
+
+ static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
+
++static void validate_dcc_with_meta_address(
++ struct dc_plane_dcc_param *dcc,
++ struct dc_plane_address *address)
++{
++ if ((address->grph.meta_addr.quad_part == 0) &&
++ dcc->enable) {
++ ASSERT(!dcc->enable);
++ dcc->enable = false;
++ } else if ((address->grph.meta_addr.quad_part != 0) &&
++ !dcc->enable)
++ dcc->enable = true;
++
++ if (address->type != PLN_ADDR_TYPE_GRAPHICS) {
++ if ((address->grph_stereo.right_meta_addr.quad_part == 0) &&
++ dcc->enable) {
++ ASSERT(!dcc->enable);
++ dcc->enable = false;
++ } else if ((address->grph_stereo.right_meta_addr.quad_part != 0) &&
++ !dcc->enable)
++ dcc->enable = true;
++ }
++}
++
+ static void copy_surface_update_to_plane(
+ struct dc_plane_state *surface,
+ struct dc_surface_update *srf_update)
+ {
+ if (srf_update->flip_addr) {
+ surface->address = srf_update->flip_addr->address;
++ validate_dcc_with_meta_address(&surface->dcc, &surface->address);
++
+ surface->flip_immediate =
+ srf_update->flip_addr->flip_immediate;
+ surface->time.time_elapsed_in_us[surface->time.index] =
+@@ -1818,6 +1843,8 @@ static void copy_surface_update_to_plane(
+ srf_update->plane_info->global_alpha_value;
+ surface->dcc =
+ srf_update->plane_info->dcc;
++ validate_dcc_with_meta_address(&surface->dcc, &surface->address);
++
+ surface->sdr_white_level =
+ srf_update->plane_info->sdr_white_level;
+ surface->layer_index =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4479-drm-amd-display-Changes-in-dc-to-allow-full-update-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4479-drm-amd-display-Changes-in-dc-to-allow-full-update-i.patch
new file mode 100644
index 00000000..c5ce8120
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4479-drm-amd-display-Changes-in-dc-to-allow-full-update-i.patch
@@ -0,0 +1,177 @@
+From 6b206971916027e93ec19a4c70ab10c36b25510a Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Thu, 24 Oct 2019 15:45:44 -0400
+Subject: [PATCH 4479/4736] drm/amd/display: Changes in dc to allow full update
+ in some cases
+
+Changes in dc to allow for different cases where full update is
+required.
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 22 +++++++++++--------
+ .../drm/amd/display/dc/dcn20/dcn20_resource.h | 2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 11 +++++-----
+ .../gpu/drm/amd/display/dc/inc/core_types.h | 2 +-
+ 4 files changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 454d30bbfd20..d437be449edb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1799,10 +1799,11 @@ void dcn20_populate_dml_writeback_from_context(
+ }
+
+ int dcn20_populate_dml_pipes_from_context(
+- struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
++ struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
+ {
+ int pipe_cnt, i;
+ bool synchronized_vblank = true;
++ struct resource_context *res_ctx = &context->res_ctx;
+
+ for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
+ if (!res_ctx->pipe_ctx[i].stream)
+@@ -1822,10 +1823,13 @@ int dcn20_populate_dml_pipes_from_context(
+
+ for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+ struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
++ unsigned int v_total;
+ int output_bpc;
+
+ if (!res_ctx->pipe_ctx[i].stream)
+ continue;
++
++ v_total = timing->v_total;
+ /* todo:
+ pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
+ pipes[pipe_cnt].pipe.src.dcc = 0;
+@@ -1840,7 +1844,7 @@ int dcn20_populate_dml_pipes_from_context(
+ pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
+ /* 1/2 vblank */
+ pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
+- (timing->v_total - timing->v_addressable
++ (v_total - timing->v_addressable
+ - timing->v_border_top - timing->v_border_bottom) / 2;
+ /* 36 bytes dp, 32 hdmi */
+ pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
+@@ -1854,13 +1858,13 @@ int dcn20_populate_dml_pipes_from_context(
+ - timing->h_addressable
+ - timing->h_border_left
+ - timing->h_border_right;
+- pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
++ pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch;
+ pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
+ - timing->v_addressable
+ - timing->v_border_top
+ - timing->v_border_bottom;
+ pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
+- pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
++ pipes[pipe_cnt].pipe.dest.vtotal = v_total;
+ pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
+ pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
+ pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
+@@ -1999,8 +2003,8 @@ int dcn20_populate_dml_pipes_from_context(
+ pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
+ pipes[pipe_cnt].pipe.src.is_hsplit = 0;
+ pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+- pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
+- pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
++ pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
++ pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
+ } else {
+ struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
+ struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
+@@ -2466,7 +2470,7 @@ bool dcn20_fast_validate_bw(
+
+ dcn20_merge_pipes_for_validate(dc, context);
+
+- pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, &context->res_ctx, pipes);
++ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
+
+ *pipe_cnt_out = pipe_cnt;
+
+@@ -2614,10 +2618,10 @@ static void dcn20_calculate_wm(
+ if (pipe_cnt != pipe_idx) {
+ if (dc->res_pool->funcs->populate_dml_pipes)
+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+- &context->res_ctx, pipes);
++ context, pipes);
+ else
+ pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+- &context->res_ctx, pipes);
++ context, pipes);
+ }
+
+ *out_pipe_cnt = pipe_cnt;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index fef473d68a4a..7187e0f8eb28 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -50,7 +50,7 @@ unsigned int dcn20_calc_max_scaled_time(
+ enum mmhubbub_wbif_mode mode,
+ unsigned int urgent_watermark);
+ int dcn20_populate_dml_pipes_from_context(
+- struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
++ struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
+ struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
+ struct dc_state *state,
+ const struct resource_pool *pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index e9db35c24073..de3ffefbf1f4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -656,7 +656,7 @@ static const struct dcn10_stream_encoder_mask se_mask = {
+ static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+
+ static int dcn21_populate_dml_pipes_from_context(
+- struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
++ struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
+
+ static struct input_pixel_processor *dcn21_ipp_create(
+ struct dc_context *ctx, uint32_t inst)
+@@ -1067,10 +1067,10 @@ void dcn21_calculate_wm(
+ if (pipe_cnt != pipe_idx) {
+ if (dc->res_pool->funcs->populate_dml_pipes)
+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+- &context->res_ctx, pipes);
++ context, pipes);
+ else
+ pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
+- &context->res_ctx, pipes);
++ context, pipes);
+ }
+
+ *out_pipe_cnt = pipe_cnt;
+@@ -1628,10 +1628,11 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ }
+
+ static int dcn21_populate_dml_pipes_from_context(
+- struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
++ struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
+ {
+- uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, pipes);
++ uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
+ int i;
++ struct resource_context *res_ctx = &context->res_ctx;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index fc9decc0a8fc..67efc8094ae7 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -105,7 +105,7 @@ struct resource_funcs {
+
+ int (*populate_dml_pipes)(
+ struct dc *dc,
+- struct resource_context *res_ctx,
++ struct dc_state *context,
+ display_e2e_pipe_params_st *pipes);
+
+ enum dc_status (*validate_global)(
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4480-drm-amd-display-Add-DMUB-service-function-check-if-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4480-drm-amd-display-Add-DMUB-service-function-check-if-h.patch
new file mode 100644
index 00000000..491b8909
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4480-drm-amd-display-Add-DMUB-service-function-check-if-h.patch
@@ -0,0 +1,123 @@
+From c5f567be2f430aa3e888240f0fab5b90fac832bf Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 29 Oct 2019 14:23:55 -0400
+Subject: [PATCH 4480/4736] drm/amd/display: Add DMUB service function check if
+ hw initialized
+
+[Why]
+We want to avoid reprogramming the cache window when possible.
+
+We don't need to worry about it for S3 but we *do* need to worry about
+it for S4 resume.
+
+DM can check whether hardware should be reinitialized or store software
+state when going to S4 to know whether we need to reprogram hardware.
+
+[How]
+Add helpers to the DMUB service to check hardware initialization state.
+
+DM will hook it up later.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h | 11 +++++++++++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 5 +++++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 2 ++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 14 ++++++++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+index aa8f0396616d..76e80138303b 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -252,6 +252,8 @@ struct dmub_srv_hw_funcs {
+
+ bool (*is_supported)(struct dmub_srv *dmub);
+
++ bool (*is_hw_init)(struct dmub_srv *dmub);
++
+ bool (*is_phy_init)(struct dmub_srv *dmub);
+
+ bool (*is_auto_load_done)(struct dmub_srv *dmub);
+@@ -380,6 +382,15 @@ enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
+ enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
+ bool *is_supported);
+
++/**
++ * dmub_srv_is_hw_init() - returns hardware init state
++ *
++ * Return:
++ * DMUB_STATUS_OK - success
++ * DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init);
++
+ /**
+ * dmub_srv_hw_init() - initializes the underlying DMUB hardware
+ * @dmub: the dmub service
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 236a4156bbe1..89fd27758dd5 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -122,6 +122,11 @@ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
+ REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
+ }
+
++bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
++{
++ return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
++}
++
+ bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
+ {
+ uint32_t supported = 0;
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+index 41269da40363..e1ba748ca594 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -55,6 +55,8 @@ uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);
+
+ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
+
++bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);
++
+ bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
+
+ bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub);
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 229eab7277d1..2d63ae80bda9 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -76,6 +76,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
+ funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
+ funcs->is_supported = dmub_dcn20_is_supported;
+ funcs->is_phy_init = dmub_dcn20_is_phy_init;
++ funcs->is_hw_init = dmub_dcn20_is_hw_init;
+
+ if (asic == DMUB_ASIC_DCN21) {
+ funcs->backdoor_load = dmub_dcn21_backdoor_load;
+@@ -234,6 +235,19 @@ enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
+ return DMUB_STATUS_OK;
+ }
+
++enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
++{
++ *is_hw_init = false;
++
++ if (!dmub->sw_init)
++ return DMUB_STATUS_INVALID;
++
++ if (dmub->hw_funcs.is_hw_init)
++ *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
++
++ return DMUB_STATUS_OK;
++}
++
+ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ const struct dmub_srv_hw_params *params)
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4481-drm-amd-display-Add-DMUB-param-to-load-inst-const-fr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4481-drm-amd-display-Add-DMUB-param-to-load-inst-const-fr.patch
new file mode 100644
index 00000000..12d5f350
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4481-drm-amd-display-Add-DMUB-param-to-load-inst-const-fr.patch
@@ -0,0 +1,57 @@
+From 8ed5f2e4b245c014046beb1f7e978dbabe6c855b Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Wed, 30 Oct 2019 09:02:39 -0400
+Subject: [PATCH 4481/4736] drm/amd/display: Add DMUB param to load inst const
+ from driver
+
+[Why]
+By default we shouldn't be trying to write secure registers during
+DMUB hardware init.
+
+[How]
+Add a parameter to control whether we put the DMCUB into secure reset
+and attempt to load CW0/CW1.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h | 2 ++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+index 76e80138303b..046885940dba 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -281,12 +281,14 @@ struct dmub_srv_create_params {
+ * @fb_base: base of the framebuffer aperture
+ * @fb_offset: offset of the framebuffer aperture
+ * @psp_version: psp version to pass for DMCU init
++ * @load_inst_const: true if DMUB should load inst const fw
+ */
+ struct dmub_srv_hw_params {
+ struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
+ uint64_t fb_base;
+ uint64_t fb_offset;
+ uint32_t psp_version;
++ bool load_inst_const;
+ };
+
+ /**
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 2d63ae80bda9..0dd32edbbcb3 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -278,7 +278,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ cw1.region.base = DMUB_CW1_BASE;
+ cw1.region.top = cw1.region.base + stack_fb->size - 1;
+
+- if (dmub->hw_funcs.backdoor_load)
++ if (params->load_inst_const && dmub->hw_funcs.backdoor_load)
+ dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4482-drm-amd-display-Add-debugfs-initalization-on-mst-con.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4482-drm-amd-display-Add-debugfs-initalization-on-mst-con.patch
new file mode 100644
index 00000000..02b4d572
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4482-drm-amd-display-Add-debugfs-initalization-on-mst-con.patch
@@ -0,0 +1,66 @@
+From 617e750370536c817d600bc504ed48f82ef95b6c Mon Sep 17 00:00:00 2001
+From: Mikita Lipski <mikita.lipski@amd.com>
+Date: Tue, 29 Oct 2019 11:43:05 -0400
+Subject: [PATCH 4482/4736] drm/amd/display: Add debugfs initalization on mst
+ connectors
+
+[why]
+We were missing debugfs files on MST connectors as the files
+weren't initialized.
+
+[how]
+Move connector debugfs initialization into connoctor's
+init helper function so it will be called by both SST and MST
+connectors. Also move connector registration so it will be
+registered before we create the entries.
+
+Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ec9fac7d4559..54a2b65dfcc1 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5480,6 +5480,12 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ drm_connector_attach_content_protection_property(&aconnector->base, false);
+ #endif
+ }
++
++#if defined(CONFIG_DEBUG_FS)
++ connector_debugfs_init(aconnector);
++ aconnector->debugfs_dpcd_address = 0;
++ aconnector->debugfs_dpcd_size = 0;
++#endif
+ }
+
+ static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
+@@ -5602,6 +5608,8 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ &aconnector->base,
+ &amdgpu_dm_connector_helper_funcs);
+
++ drm_connector_register(&aconnector->base);
++
+ amdgpu_dm_connector_init_helper(
+ dm,
+ aconnector,
+@@ -5612,13 +5620,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ drm_connector_attach_encoder(
+ &aconnector->base, &aencoder->base);
+
+- drm_connector_register(&aconnector->base);
+-#if defined(CONFIG_DEBUG_FS)
+- connector_debugfs_init(aconnector);
+- aconnector->debugfs_dpcd_address = 0;
+- aconnector->debugfs_dpcd_size = 0;
+-#endif
+-
+ if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
+ || connector_type == DRM_MODE_CONNECTOR_eDP)
+ amdgpu_dm_initialize_dp_connector(dm, aconnector);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4483-drm-amd-display-Connect-DIG-FE-to-its-BE-before-link.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4483-drm-amd-display-Connect-DIG-FE-to-its-BE-before-link.patch
new file mode 100644
index 00000000..59dc9fe1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4483-drm-amd-display-Connect-DIG-FE-to-its-BE-before-link.patch
@@ -0,0 +1,35 @@
+From d9e8bbbc6fffd210c026fa011ed1b556d00eaea0 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Tue, 29 Oct 2019 15:49:28 -0400
+Subject: [PATCH 4483/4736] drm/amd/display: Connect DIG FE to its BE before
+ link training starts
+
+[why]
+In SST mode no idle pattern will be generated after link training if
+DIG FE is not connected to DIG BE.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 7fab34ce0591..58b63612c926 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1546,6 +1546,10 @@ static enum dc_status enable_link_dp(
+ panel_mode = dp_get_panel_mode(link);
+ dp_set_panel_mode(link, panel_mode);
+
++ /* We need to do this before the link training to ensure the idle pattern in SST
++ * mode will be sent right after the link training */
++ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
++ pipe_ctx->stream_res.stream_enc->id, true);
+ skip_video_pattern = true;
+
+ if (link_settings.link_rate == LINK_RATE_LOW)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4484-drm-amd-display-Clean-up-some-code-with-unused-regis.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4484-drm-amd-display-Clean-up-some-code-with-unused-regis.patch
new file mode 100644
index 00000000..fdbdf164
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4484-drm-amd-display-Clean-up-some-code-with-unused-regis.patch
@@ -0,0 +1,36 @@
+From 91b762a11983428a235016d132e59d4812c44875 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Mon, 28 Oct 2019 11:45:14 -0400
+Subject: [PATCH 4484/4736] drm/amd/display: Clean up some code with unused
+ registers
+
+[Why]
+Unused register in the code
+
+[How]
+Remove unused register
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 32d145a0d6fc..a0d1c3b811a9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -800,8 +800,7 @@ struct dce_hwseq_registers {
+ type D2VGA_MODE_ENABLE; \
+ type D3VGA_MODE_ENABLE; \
+ type D4VGA_MODE_ENABLE; \
+- type AZALIA_AUDIO_DTO_MODULE;\
+- type HPO_HDMISTREAMCLK_GATE_DIS;
++ type AZALIA_AUDIO_DTO_MODULE;
+
+ struct dce_hwseq_shift {
+ HWSEQ_REG_FIELD_LIST(uint8_t)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4485-drm-amd-display-revert-change-causing-DTN-hang-for-R.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4485-drm-amd-display-revert-change-causing-DTN-hang-for-R.patch
new file mode 100644
index 00000000..1138441e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4485-drm-amd-display-revert-change-causing-DTN-hang-for-R.patch
@@ -0,0 +1,73 @@
+From 7db83a80e428a864b3d117da7d28c901a0703574 Mon Sep 17 00:00:00 2001
+From: Samson Tam <Samson.Tam@amd.com>
+Date: Thu, 31 Oct 2019 15:27:28 -0400
+Subject: [PATCH 4485/4736] drm/amd/display: revert change causing DTN hang for
+ RV
+
+[Why]
+Hanging on RV for DTN driver verifier
+
+[How]
+Roll back change and investigate further
+
+Signed-off-by: Samson Tam <Samson.Tam@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 27 ------------------------
+ 1 file changed, 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 7a2cdf21ca34..9e600d3e2fd8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1764,37 +1764,12 @@ static struct dc_stream_status *stream_get_status(
+
+ static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
+
+-static void validate_dcc_with_meta_address(
+- struct dc_plane_dcc_param *dcc,
+- struct dc_plane_address *address)
+-{
+- if ((address->grph.meta_addr.quad_part == 0) &&
+- dcc->enable) {
+- ASSERT(!dcc->enable);
+- dcc->enable = false;
+- } else if ((address->grph.meta_addr.quad_part != 0) &&
+- !dcc->enable)
+- dcc->enable = true;
+-
+- if (address->type != PLN_ADDR_TYPE_GRAPHICS) {
+- if ((address->grph_stereo.right_meta_addr.quad_part == 0) &&
+- dcc->enable) {
+- ASSERT(!dcc->enable);
+- dcc->enable = false;
+- } else if ((address->grph_stereo.right_meta_addr.quad_part != 0) &&
+- !dcc->enable)
+- dcc->enable = true;
+- }
+-}
+-
+ static void copy_surface_update_to_plane(
+ struct dc_plane_state *surface,
+ struct dc_surface_update *srf_update)
+ {
+ if (srf_update->flip_addr) {
+ surface->address = srf_update->flip_addr->address;
+- validate_dcc_with_meta_address(&surface->dcc, &surface->address);
+-
+ surface->flip_immediate =
+ srf_update->flip_addr->flip_immediate;
+ surface->time.time_elapsed_in_us[surface->time.index] =
+@@ -1843,8 +1818,6 @@ static void copy_surface_update_to_plane(
+ srf_update->plane_info->global_alpha_value;
+ surface->dcc =
+ srf_update->plane_info->dcc;
+- validate_dcc_with_meta_address(&surface->dcc, &surface->address);
+-
+ surface->sdr_white_level =
+ srf_update->plane_info->sdr_white_level;
+ surface->layer_index =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4486-drm-amd-display-Fix-debugfs-on-MST-connectors.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4486-drm-amd-display-Fix-debugfs-on-MST-connectors.patch
new file mode 100644
index 00000000..288726c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4486-drm-amd-display-Fix-debugfs-on-MST-connectors.patch
@@ -0,0 +1,96 @@
+From 298e853d52b57d8e2e929adac65ed27a6b184e49 Mon Sep 17 00:00:00 2001
+From: Mikita Lipski <mikita.lipski@amd.com>
+Date: Thu, 31 Oct 2019 16:09:01 -0400
+Subject: [PATCH 4486/4736] drm/amd/display: Fix debugfs on MST connectors
+
+[why]
+Previous patch allowed to initialize debugfs entries on both MST
+and SST connectors, but MST connectors get registered much later
+which exposed an issue of debugfs entries being initialized in the
+same folder.
+
+[how]
+Return SST debugfs entries' initialization back to where it was.
+For MST connectors we should initialize debugfs entries in connector
+register function after the connector is registered.
+
+Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++++--------
+ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 10 +++++++++-
+ 2 files changed, 16 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 54a2b65dfcc1..ec9fac7d4559 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5480,12 +5480,6 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ drm_connector_attach_content_protection_property(&aconnector->base, false);
+ #endif
+ }
+-
+-#if defined(CONFIG_DEBUG_FS)
+- connector_debugfs_init(aconnector);
+- aconnector->debugfs_dpcd_address = 0;
+- aconnector->debugfs_dpcd_size = 0;
+-#endif
+ }
+
+ static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
+@@ -5608,8 +5602,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ &aconnector->base,
+ &amdgpu_dm_connector_helper_funcs);
+
+- drm_connector_register(&aconnector->base);
+-
+ amdgpu_dm_connector_init_helper(
+ dm,
+ aconnector,
+@@ -5620,6 +5612,13 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ drm_connector_attach_encoder(
+ &aconnector->base, &aencoder->base);
+
++ drm_connector_register(&aconnector->base);
++#if defined(CONFIG_DEBUG_FS)
++ connector_debugfs_init(aconnector);
++ aconnector->debugfs_dpcd_address = 0;
++ aconnector->debugfs_dpcd_size = 0;
++#endif
++
+ if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
+ || connector_type == DRM_MODE_CONNECTOR_eDP)
+ amdgpu_dm_initialize_dp_connector(dm, aconnector);
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index c765fcbd1386..74cadc8b4801 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -36,7 +36,9 @@
+ #include "dc_link_ddc.h"
+
+ #include "i2caux_interface.h"
+-
++#if defined(CONFIG_DEBUG_FS)
++#include "amdgpu_dm_debugfs.h"
++#endif
+ /* #define TRACE_DPCD */
+
+ #ifdef TRACE_DPCD
+@@ -161,6 +163,12 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
+ to_amdgpu_dm_connector(connector);
+ struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
+
++#if defined(CONFIG_DEBUG_FS)
++ connector_debugfs_init(amdgpu_dm_connector);
++ amdgpu_dm_connector->debugfs_dpcd_address = 0;
++ amdgpu_dm_connector->debugfs_dpcd_size = 0;
++#endif
++
+ return drm_dp_mst_connector_late_register(connector, port);
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4487-drm-amd-display-cleanup-of-construct-and-destruct-fu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4487-drm-amd-display-cleanup-of-construct-and-destruct-fu.patch
new file mode 100644
index 00000000..8fbd65ce
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4487-drm-amd-display-cleanup-of-construct-and-destruct-fu.patch
@@ -0,0 +1,1071 @@
+From a476c483cb70b9fb28ee2336785d225a0f920330 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Thu, 31 Oct 2019 21:39:39 -0400
+Subject: [PATCH 4487/4736] drm/amd/display: cleanup of construct and destruct
+ funcs
+
+[Why]
+Too many construct functions which makes searching
+difficult, especially on some debuggers.
+
+[How]
+Append all construct and destruct functions with dcn
+number and object type to make each construct function
+name unique
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../gpu/drm/amd/display/dc/bios/bios_parser.c | 4 +--
+ .../drm/amd/display/dc/bios/bios_parser2.c | 8 ++---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +++---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 ++---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 8 ++---
+ drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 8 ++---
+ .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ++---
+ .../gpu/drm/amd/display/dc/core/dc_surface.c | 8 ++---
+ .../amd/display/dc/dce100/dce100_resource.c | 10 +++---
+ .../amd/display/dc/dce110/dce110_resource.c | 10 +++---
+ .../amd/display/dc/dce112/dce112_resource.c | 10 +++---
+ .../amd/display/dc/dce120/dce120_resource.c | 10 +++---
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 10 +++---
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 10 +++---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 10 +++---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 10 +++---
+ drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 12 +++----
+ .../gpu/drm/amd/display/dc/gpio/hw_generic.c | 23 ++++---------
+ drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 32 +++++--------------
+ .../dc/irq/dce110/irq_service_dce110.c | 4 +--
+ .../dc/irq/dce120/irq_service_dce120.c | 4 +--
+ .../display/dc/irq/dce80/irq_service_dce80.c | 4 +--
+ .../display/dc/irq/dcn10/irq_service_dcn10.c | 4 +--
+ .../display/dc/irq/dcn20/irq_service_dcn20.c | 4 +--
+ .../display/dc/irq/dcn21/irq_service_dcn21.c | 4 +--
+ 25 files changed, 104 insertions(+), 129 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 0d4993691199..714a862e7321 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -109,7 +109,7 @@ struct dc_bios *bios_parser_create(
+ return NULL;
+ }
+
+-static void destruct(struct bios_parser *bp)
++static void bios_parser_destruct(struct bios_parser *bp)
+ {
+ kfree(bp->base.bios_local_image);
+ kfree(bp->base.integrated_info);
+@@ -124,7 +124,7 @@ static void bios_parser_destroy(struct dc_bios **dcb)
+ return;
+ }
+
+- destruct(bp);
++ bios_parser_destruct(bp);
+
+ kfree(bp);
+ *dcb = NULL;
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 884b07774f6d..03a5e82a7b2d 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -109,7 +109,7 @@ static struct atom_encoder_caps_record *get_encoder_cap_record(
+
+ #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
+
+-static void destruct(struct bios_parser *bp)
++static void bios_parser2_destruct(struct bios_parser *bp)
+ {
+ kfree(bp->base.bios_local_image);
+ kfree(bp->base.integrated_info);
+@@ -124,7 +124,7 @@ static void firmware_parser_destroy(struct dc_bios **dcb)
+ return;
+ }
+
+- destruct(bp);
++ bios_parser2_destruct(bp);
+
+ kfree(bp);
+ *dcb = NULL;
+@@ -1925,7 +1925,7 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ .get_board_layout_info = bios_get_board_layout_info,
+ };
+
+-static bool bios_parser_construct(
++static bool bios_parser2_construct(
+ struct bios_parser *bp,
+ struct bp_init_data *init,
+ enum dce_version dce_version)
+@@ -2018,7 +2018,7 @@ struct dc_bios *firmware_parser_create(
+ if (!bp)
+ return NULL;
+
+- if (bios_parser_construct(bp, init, dce_version))
++ if (bios_parser2_construct(bp, init, dce_version))
+ return &bp->base;
+
+ kfree(bp);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 9e600d3e2fd8..7539c3accd59 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -534,7 +534,7 @@ void dc_stream_set_static_screen_events(struct dc *dc,
+ dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
+ }
+
+-static void destruct(struct dc *dc)
++static void dc_destruct(struct dc *dc)
+ {
+ if (dc->current_state) {
+ dc_release_state(dc->current_state);
+@@ -582,7 +582,7 @@ static void destruct(struct dc *dc)
+ #endif
+ }
+
+-static bool construct(struct dc *dc,
++static bool dc_construct(struct dc *dc,
+ const struct dc_init_data *init_params)
+ {
+ struct dc_context *dc_ctx;
+@@ -734,7 +734,7 @@ static bool construct(struct dc *dc,
+
+ fail:
+
+- destruct(dc);
++ dc_destruct(dc);
+ return false;
+ }
+
+@@ -806,7 +806,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
+ if (NULL == dc)
+ goto alloc_fail;
+
+- if (false == construct(dc, init_params))
++ if (false == dc_construct(dc, init_params))
+ goto construct_fail;
+
+ full_pipe_count = dc->res_pool->pipe_count;
+@@ -863,7 +863,7 @@ void dc_deinit_callbacks(struct dc *dc)
+
+ void dc_destroy(struct dc **dc)
+ {
+- destruct(*dc);
++ dc_destruct(*dc);
+ kfree(*dc);
+ *dc = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 58b63612c926..014cb7cf9cba 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -72,7 +72,7 @@ enum {
+ /*******************************************************************************
+ * Private functions
+ ******************************************************************************/
+-static void destruct(struct dc_link *link)
++static void dc_link_destruct(struct dc_link *link)
+ {
+ int i;
+
+@@ -1242,7 +1242,7 @@ static enum transmitter translate_encoder_to_transmitter(
+ }
+ }
+
+-static bool construct(
++static bool dc_link_construct(
+ struct dc_link *link,
+ const struct link_init_data *init_params)
+ {
+@@ -1444,7 +1444,7 @@ struct dc_link *link_create(const struct link_init_data *init_params)
+ if (NULL == link)
+ goto alloc_fail;
+
+- if (false == construct(link, init_params))
++ if (false == dc_link_construct(link, init_params))
+ goto construct_fail;
+
+ return link;
+@@ -1458,7 +1458,7 @@ struct dc_link *link_create(const struct link_init_data *init_params)
+
+ void link_destroy(struct dc_link **link)
+ {
+- destruct(*link);
++ dc_link_destruct(*link);
+ kfree(*link);
+ *link = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 68c0cf85deb7..60d3c164495d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -185,7 +185,7 @@ void dal_ddc_i2c_payloads_add(
+
+ }
+
+-static void construct(
++static void ddc_service_construct(
+ struct ddc_service *ddc_service,
+ struct ddc_service_init_data *init_data)
+ {
+@@ -237,11 +237,11 @@ struct ddc_service *dal_ddc_service_create(
+ if (!ddc_service)
+ return NULL;
+
+- construct(ddc_service, init_data);
++ ddc_service_construct(ddc_service, init_data);
+ return ddc_service;
+ }
+
+-static void destruct(struct ddc_service *ddc)
++static void ddc_service_destruct(struct ddc_service *ddc)
+ {
+ if (ddc->ddc_pin)
+ dal_gpio_destroy_ddc(&ddc->ddc_pin);
+@@ -253,7 +253,7 @@ void dal_ddc_service_destroy(struct ddc_service **ddc)
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+- destruct(*ddc);
++ ddc_service_destruct(*ddc);
+ kfree(*ddc);
+ *ddc = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+index 9971b515c3eb..a3fa001ef585 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+@@ -31,7 +31,7 @@
+ * Private functions
+ ******************************************************************************/
+
+-static void destruct(struct dc_sink *sink)
++static void dc_sink_destruct(struct dc_sink *sink)
+ {
+ if (sink->dc_container_id) {
+ kfree(sink->dc_container_id);
+@@ -39,7 +39,7 @@ static void destruct(struct dc_sink *sink)
+ }
+ }
+
+-static bool construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params)
++static bool dc_sink_construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params)
+ {
+
+ struct dc_link *link = init_params->link;
+@@ -73,7 +73,7 @@ void dc_sink_retain(struct dc_sink *sink)
+ static void dc_sink_free(struct kref *kref)
+ {
+ struct dc_sink *sink = container_of(kref, struct dc_sink, refcount);
+- destruct(sink);
++ dc_sink_destruct(sink);
+ kfree(sink);
+ }
+
+@@ -89,7 +89,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
+ if (NULL == sink)
+ goto alloc_fail;
+
+- if (false == construct(sink, init_params))
++ if (false == dc_sink_construct(sink, init_params))
+ goto construct_fail;
+
+ kref_init(&sink->refcount);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 2e03a1120bee..ae7cbb6d7847 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -55,7 +55,7 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
+ }
+ }
+
+-static void construct(struct dc_stream_state *stream,
++static void dc_stream_construct(struct dc_stream_state *stream,
+ struct dc_sink *dc_sink_data)
+ {
+ uint32_t i = 0;
+@@ -126,7 +126,7 @@ static void construct(struct dc_stream_state *stream,
+ stream->ctx->dc_stream_id_count++;
+ }
+
+-static void destruct(struct dc_stream_state *stream)
++static void dc_stream_destruct(struct dc_stream_state *stream)
+ {
+ dc_sink_release(stream->sink);
+ if (stream->out_transfer_func != NULL) {
+@@ -144,7 +144,7 @@ static void dc_stream_free(struct kref *kref)
+ {
+ struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
+
+- destruct(stream);
++ dc_stream_destruct(stream);
+ kfree(stream);
+ }
+
+@@ -167,7 +167,7 @@ struct dc_stream_state *dc_create_stream_for_sink(
+ if (stream == NULL)
+ return NULL;
+
+- construct(stream, sink);
++ dc_stream_construct(stream, sink);
+
+ kref_init(&stream->refcount);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index 9184f877f537..d534ac166512 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -35,7 +35,7 @@
+ /*******************************************************************************
+ * Private functions
+ ******************************************************************************/
+-static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
++static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
+ {
+ plane_state->ctx = ctx;
+
+@@ -68,7 +68,7 @@ static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state
+ #endif
+ }
+
+-static void destruct(struct dc_plane_state *plane_state)
++static void dc_plane_destruct(struct dc_plane_state *plane_state)
+ {
+ if (plane_state->gamma_correction != NULL) {
+ dc_gamma_release(&plane_state->gamma_correction);
+@@ -119,7 +119,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
+ return NULL;
+
+ kref_init(&plane_state->refcount);
+- construct(core_dc->ctx, plane_state);
++ dc_plane_construct(core_dc->ctx, plane_state);
+
+ return plane_state;
+ }
+@@ -189,7 +189,7 @@ void dc_plane_state_retain(struct dc_plane_state *plane_state)
+ static void dc_plane_state_free(struct kref *kref)
+ {
+ struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
+- destruct(plane_state);
++ dc_plane_destruct(plane_state);
+ kvfree(plane_state);
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 8ec9b4639fe7..2a5ad50ba454 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -722,7 +722,7 @@ void dce100_clock_source_destroy(struct clock_source **clk_src)
+ *clk_src = NULL;
+ }
+
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce100_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -882,7 +882,7 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+
+- destruct(dce110_pool);
++ dce100_resource_destruct(dce110_pool);
+ kfree(dce110_pool);
+ *pool = NULL;
+ }
+@@ -947,7 +947,7 @@ static const struct resource_funcs dce100_res_pool_funcs = {
+ .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
+ };
+
+-static bool construct(
++static bool dce100_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dce110_resource_pool *pool)
+@@ -1119,7 +1119,7 @@ static bool construct(
+ return true;
+
+ res_create_fail:
+- destruct(pool);
++ dce100_resource_destruct(pool);
+
+ return false;
+ }
+@@ -1134,7 +1134,7 @@ struct resource_pool *dce100_create_resource_pool(
+ if (!pool)
+ return NULL;
+
+- if (construct(num_virtual_links, dc, pool))
++ if (dce100_resource_construct(num_virtual_links, dc, pool))
+ return &pool->base;
+
+ kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 377fa9193ce1..762f97b48f0f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -780,7 +780,7 @@ void dce110_clock_source_destroy(struct clock_source **clk_src)
+ *clk_src = NULL;
+ }
+
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce110_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -1159,7 +1159,7 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+
+- destruct(dce110_pool);
++ dce110_resource_destruct(dce110_pool);
+ kfree(dce110_pool);
+ *pool = NULL;
+ }
+@@ -1311,7 +1311,7 @@ const struct resource_caps *dce110_resource_cap(
+ return &carrizo_resource_cap;
+ }
+
+-static bool construct(
++static bool dce110_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dce110_resource_pool *pool,
+@@ -1490,7 +1490,7 @@ static bool construct(
+ return true;
+
+ res_create_fail:
+- destruct(pool);
++ dce110_resource_destruct(pool);
+ return false;
+ }
+
+@@ -1505,7 +1505,7 @@ struct resource_pool *dce110_create_resource_pool(
+ if (!pool)
+ return NULL;
+
+- if (construct(num_virtual_links, dc, pool, asic_id))
++ if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
+ return &pool->base;
+
+ kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 5bde6ac2fa7e..b2f127bd85ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -742,7 +742,7 @@ void dce112_clock_source_destroy(struct clock_source **clk_src)
+ *clk_src = NULL;
+ }
+
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce112_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -1011,7 +1011,7 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+
+- destruct(dce110_pool);
++ dce112_resource_destruct(dce110_pool);
+ kfree(dce110_pool);
+ *pool = NULL;
+ }
+@@ -1184,7 +1184,7 @@ const struct resource_caps *dce112_resource_cap(
+ return &polaris_10_resource_cap;
+ }
+
+-static bool construct(
++static bool dce112_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dce110_resource_pool *pool)
+@@ -1370,7 +1370,7 @@ static bool construct(
+ return true;
+
+ res_create_fail:
+- destruct(pool);
++ dce112_resource_destruct(pool);
+ return false;
+ }
+
+@@ -1384,7 +1384,7 @@ struct resource_pool *dce112_create_resource_pool(
+ if (!pool)
+ return NULL;
+
+- if (construct(num_virtual_links, dc, pool))
++ if (dce112_resource_construct(num_virtual_links, dc, pool))
+ return &pool->base;
+
+ kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index c982fd336cae..e9157583817f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -585,7 +585,7 @@ static void dce120_transform_destroy(struct transform **xfm)
+ *xfm = NULL;
+ }
+
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce120_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -870,7 +870,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+
+- destruct(dce110_pool);
++ dce120_resource_destruct(dce110_pool);
+ kfree(dce110_pool);
+ *pool = NULL;
+ }
+@@ -1022,7 +1022,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ return value;
+ }
+
+-static bool construct(
++static bool dce120_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dce110_resource_pool *pool)
+@@ -1235,7 +1235,7 @@ static bool construct(
+ clk_src_create_fail:
+ res_create_fail:
+
+- destruct(pool);
++ dce120_resource_destruct(pool);
+
+ return false;
+ }
+@@ -1250,7 +1250,7 @@ struct resource_pool *dce120_create_resource_pool(
+ if (!pool)
+ return NULL;
+
+- if (construct(num_virtual_links, dc, pool))
++ if (dce120_resource_construct(num_virtual_links, dc, pool))
+ return &pool->base;
+
+ kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 6a9efa3bb93e..fd7acdb561b3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -771,7 +771,7 @@ static struct input_pixel_processor *dce80_ipp_create(
+ return &ipp->base;
+ }
+
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce80_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -899,7 +899,7 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+
+- destruct(dce110_pool);
++ dce80_resource_destruct(dce110_pool);
+ kfree(dce110_pool);
+ *pool = NULL;
+ }
+@@ -1091,7 +1091,7 @@ static bool dce80_construct(
+ return true;
+
+ res_create_fail:
+- destruct(pool);
++ dce80_resource_destruct(pool);
+ return false;
+ }
+
+@@ -1288,7 +1288,7 @@ static bool dce81_construct(
+ return true;
+
+ res_create_fail:
+- destruct(pool);
++ dce80_resource_destruct(pool);
+ return false;
+ }
+
+@@ -1481,7 +1481,7 @@ static bool dce83_construct(
+ return true;
+
+ res_create_fail:
+- destruct(pool);
++ dce80_resource_destruct(pool);
+ return false;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index a38c83c6aa5c..c4129e21e643 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -917,7 +917,7 @@ static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
+ return pp_smu;
+ }
+
+-static void destruct(struct dcn10_resource_pool *pool)
++static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -1164,7 +1164,7 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
+
+- destruct(dcn10_pool);
++ dcn10_resource_destruct(dcn10_pool);
+ kfree(dcn10_pool);
+ *pool = NULL;
+ }
+@@ -1303,7 +1303,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ return value;
+ }
+
+-static bool construct(
++static bool dcn10_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dcn10_resource_pool *pool)
+@@ -1590,7 +1590,7 @@ static bool construct(
+
+ fail:
+
+- destruct(pool);
++ dcn10_resource_destruct(pool);
+
+ return false;
+ }
+@@ -1605,7 +1605,7 @@ struct resource_pool *dcn10_create_resource_pool(
+ if (!pool)
+ return NULL;
+
+- if (construct(init_data->num_virtual_links, dc, pool))
++ if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
+ return &pool->base;
+
+ kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index d437be449edb..3119714586dd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1236,7 +1236,7 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
+
+ #endif
+
+-static void destruct(struct dcn20_resource_pool *pool)
++static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -2932,7 +2932,7 @@ static void dcn20_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
+
+- destruct(dcn20_pool);
++ dcn20_resource_destruct(dcn20_pool);
+ kfree(dcn20_pool);
+ *pool = NULL;
+ }
+@@ -3388,7 +3388,7 @@ static bool init_soc_bounding_box(struct dc *dc,
+ return true;
+ }
+
+-static bool construct(
++static bool dcn20_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dcn20_resource_pool *pool)
+@@ -3707,7 +3707,7 @@ static bool construct(
+
+ create_fail:
+
+- destruct(pool);
++ dcn20_resource_destruct(pool);
+
+ return false;
+ }
+@@ -3722,7 +3722,7 @@ struct resource_pool *dcn20_create_resource_pool(
+ if (!pool)
+ return NULL;
+
+- if (construct(init_data->num_virtual_links, dc, pool))
++ if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
+ return &pool->base;
+
+ BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index de3ffefbf1f4..9ec73b513488 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -854,7 +854,7 @@ enum dcn20_clk_src_array_id {
+ DCN20_CLK_SRC_TOTAL_DCN21
+ };
+
+-static void destruct(struct dcn21_resource_pool *pool)
++static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
+ {
+ unsigned int i;
+
+@@ -1160,7 +1160,7 @@ static void dcn21_destroy_resource_pool(struct resource_pool **pool)
+ {
+ struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
+
+- destruct(dcn21_pool);
++ dcn21_resource_destruct(dcn21_pool);
+ kfree(dcn21_pool);
+ *pool = NULL;
+ }
+@@ -1661,7 +1661,7 @@ static struct resource_funcs dcn21_res_pool_funcs = {
+ .update_bw_bounding_box = update_bw_bounding_box
+ };
+
+-static bool construct(
++static bool dcn21_resource_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dcn21_resource_pool *pool)
+@@ -1915,7 +1915,7 @@ static bool construct(
+
+ create_fail:
+
+- destruct(pool);
++ dcn21_resource_destruct(pool);
+
+ return false;
+ }
+@@ -1930,7 +1930,7 @@ struct resource_pool *dcn21_create_resource_pool(
+ if (!pool)
+ return NULL;
+
+- if (construct(init_data->num_virtual_links, dc, pool))
++ if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
+ return &pool->base;
+
+ BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+index e1c84a2f7298..95d1c44a1d47 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+@@ -45,18 +45,18 @@
+
+ struct gpio;
+
+-static void destruct(
++static void dal_hw_ddc_destruct(
+ struct hw_ddc *pin)
+ {
+ dal_hw_gpio_destruct(&pin->base);
+ }
+
+-static void destroy(
++static void dal_hw_ddc_destroy(
+ struct hw_gpio_pin **ptr)
+ {
+ struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr);
+
+- destruct(pin);
++ dal_hw_ddc_destruct(pin);
+
+ kfree(pin);
+
+@@ -208,7 +208,7 @@ static enum gpio_result set_config(
+ }
+
+ static const struct hw_gpio_pin_funcs funcs = {
+- .destroy = destroy,
++ .destroy = dal_hw_ddc_destroy,
+ .open = dal_hw_gpio_open,
+ .get_value = dal_hw_gpio_get_value,
+ .set_value = dal_hw_gpio_set_value,
+@@ -217,7 +217,7 @@ static const struct hw_gpio_pin_funcs funcs = {
+ .close = dal_hw_gpio_close,
+ };
+
+-static void construct(
++static void dal_hw_ddc_construct(
+ struct hw_ddc *ddc,
+ enum gpio_id id,
+ uint32_t en,
+@@ -244,7 +244,7 @@ void dal_hw_ddc_init(
+ return;
+ }
+
+- construct(*hw_ddc, id, en, ctx);
++ dal_hw_ddc_construct(*hw_ddc, id, en, ctx);
+ }
+
+ struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio)
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+index f039c5982ac8..e41f60b23749 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+@@ -44,22 +44,13 @@
+
+ struct gpio;
+
+-static void dal_hw_generic_construct(
+- struct hw_generic *pin,
+- enum gpio_id id,
+- uint32_t en,
+- struct dc_context *ctx)
+-{
+- dal_hw_gpio_construct(&pin->base, id, en, ctx);
+-}
+-
+ static void dal_hw_generic_destruct(
+ struct hw_generic *pin)
+ {
+ dal_hw_gpio_destruct(&pin->base);
+ }
+
+-static void destroy(
++static void dal_hw_generic_destroy(
+ struct hw_gpio_pin **ptr)
+ {
+ struct hw_generic *generic = HW_GENERIC_FROM_BASE(*ptr);
+@@ -88,7 +79,7 @@ static enum gpio_result set_config(
+ }
+
+ static const struct hw_gpio_pin_funcs funcs = {
+- .destroy = destroy,
++ .destroy = dal_hw_generic_destroy,
+ .open = dal_hw_gpio_open,
+ .get_value = dal_hw_gpio_get_value,
+ .set_value = dal_hw_gpio_set_value,
+@@ -97,14 +88,14 @@ static const struct hw_gpio_pin_funcs funcs = {
+ .close = dal_hw_gpio_close,
+ };
+
+-static void construct(
+- struct hw_generic *generic,
++static void dal_hw_generic_construct(
++ struct hw_generic *pin,
+ enum gpio_id id,
+ uint32_t en,
+ struct dc_context *ctx)
+ {
+- dal_hw_generic_construct(generic, id, en, ctx);
+- generic->base.base.funcs = &funcs;
++ dal_hw_gpio_construct(&pin->base, id, en, ctx);
++ pin->base.base.funcs = &funcs;
+ }
+
+ void dal_hw_generic_init(
+@@ -124,7 +115,7 @@ void dal_hw_generic_init(
+ return;
+ }
+
+- construct(*hw_generic, id, en, ctx);
++ dal_hw_generic_construct(*hw_generic, id, en, ctx);
+ }
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+index 88798cf3965e..1489fdfaf0e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+@@ -44,34 +44,18 @@
+
+ struct gpio;
+
+-static void dal_hw_hpd_construct(
+- struct hw_hpd *pin,
+- enum gpio_id id,
+- uint32_t en,
+- struct dc_context *ctx)
+-{
+- dal_hw_gpio_construct(&pin->base, id, en, ctx);
+-}
+-
+ static void dal_hw_hpd_destruct(
+ struct hw_hpd *pin)
+ {
+ dal_hw_gpio_destruct(&pin->base);
+ }
+
+-
+-static void destruct(
+- struct hw_hpd *hpd)
+-{
+- dal_hw_hpd_destruct(hpd);
+-}
+-
+-static void destroy(
++static void dal_hw_hpd_destroy(
+ struct hw_gpio_pin **ptr)
+ {
+ struct hw_hpd *hpd = HW_HPD_FROM_BASE(*ptr);
+
+- destruct(hpd);
++ dal_hw_hpd_destruct(hpd);
+
+ kfree(hpd);
+
+@@ -118,7 +102,7 @@ static enum gpio_result set_config(
+ }
+
+ static const struct hw_gpio_pin_funcs funcs = {
+- .destroy = destroy,
++ .destroy = dal_hw_hpd_destroy,
+ .open = dal_hw_gpio_open,
+ .get_value = get_value,
+ .set_value = dal_hw_gpio_set_value,
+@@ -127,14 +111,14 @@ static const struct hw_gpio_pin_funcs funcs = {
+ .close = dal_hw_gpio_close,
+ };
+
+-static void construct(
+- struct hw_hpd *hpd,
++static void dal_hw_hpd_construct(
++ struct hw_hpd *pin,
+ enum gpio_id id,
+ uint32_t en,
+ struct dc_context *ctx)
+ {
+- dal_hw_hpd_construct(hpd, id, en, ctx);
+- hpd->base.base.funcs = &funcs;
++ dal_hw_gpio_construct(&pin->base, id, en, ctx);
++ pin->base.base.funcs = &funcs;
+ }
+
+ void dal_hw_hpd_init(
+@@ -154,7 +138,7 @@ void dal_hw_hpd_init(
+ return;
+ }
+
+- construct(*hw_hpd, id, en, ctx);
++ dal_hw_hpd_construct(*hw_hpd, id, en, ctx);
+ }
+
+ struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio)
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+index 86987f5e8bd5..80603e18ecd6 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+@@ -401,7 +401,7 @@ static const struct irq_service_funcs irq_service_funcs_dce110 = {
+ .to_dal_irq_source = to_dal_irq_source_dce110
+ };
+
+-static void construct(struct irq_service *irq_service,
++static void dce110_irq_construct(struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+ {
+ dal_irq_service_construct(irq_service, init_data);
+@@ -419,6 +419,6 @@ dal_irq_service_dce110_create(struct irq_service_init_data *init_data)
+ if (!irq_service)
+ return NULL;
+
+- construct(irq_service, init_data);
++ dce110_irq_construct(irq_service, init_data);
+ return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+index 750ba0ab4106..0a5e1a2a3c61 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+@@ -271,7 +271,7 @@ static const struct irq_service_funcs irq_service_funcs_dce120 = {
+ .to_dal_irq_source = to_dal_irq_source_dce110
+ };
+
+-static void construct(
++static void dce120_irq_construct(
+ struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+ {
+@@ -290,6 +290,6 @@ struct irq_service *dal_irq_service_dce120_create(
+ if (!irq_service)
+ return NULL;
+
+- construct(irq_service, init_data);
++ dce120_irq_construct(irq_service, init_data);
+ return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+index de218fe84a43..85f63b4a8b90 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+@@ -281,7 +281,7 @@ static const struct irq_service_funcs irq_service_funcs_dce80 = {
+ .to_dal_irq_source = to_dal_irq_source_dce110
+ };
+
+-static void construct(
++static void dce80_irq_construct(
+ struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+ {
+@@ -300,7 +300,7 @@ struct irq_service *dal_irq_service_dce80_create(
+ if (!irq_service)
+ return NULL;
+
+- construct(irq_service, init_data);
++ dce80_irq_construct(irq_service, init_data);
+ return irq_service;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+index d179e4d8c485..f86eb50ac461 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+@@ -353,7 +353,7 @@ static const struct irq_service_funcs irq_service_funcs_dcn10 = {
+ .to_dal_irq_source = to_dal_irq_source_dcn10
+ };
+
+-static void construct(
++static void dcn10_irq_construct(
+ struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+ {
+@@ -372,6 +372,6 @@ struct irq_service *dal_irq_service_dcn10_create(
+ if (!irq_service)
+ return NULL;
+
+- construct(irq_service, init_data);
++ dcn10_irq_construct(irq_service, init_data);
+ return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+index 1fdbc9e5f7bc..4711ea6f43e3 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+@@ -357,7 +357,7 @@ static const struct irq_service_funcs irq_service_funcs_dcn20 = {
+ .to_dal_irq_source = to_dal_irq_source_dcn20
+ };
+
+-static void construct(
++static void dcn20_irq_construct(
+ struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+ {
+@@ -376,6 +376,6 @@ struct irq_service *dal_irq_service_dcn20_create(
+ if (!irq_service)
+ return NULL;
+
+- construct(irq_service, init_data);
++ dcn20_irq_construct(irq_service, init_data);
+ return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+index 2794c0598f1e..8ec1f8f592ae 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+@@ -348,7 +348,7 @@ static const struct irq_service_funcs irq_service_funcs_dcn21 = {
+ .to_dal_irq_source = to_dal_irq_source_dcn21
+ };
+
+-static void construct(
++static void dcn21_irq_construct(
+ struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+ {
+@@ -367,6 +367,6 @@ struct irq_service *dal_irq_service_dcn21_create(
+ if (!irq_service)
+ return NULL;
+
+- construct(irq_service, init_data);
++ dcn21_irq_construct(irq_service, init_data);
+ return irq_service;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4488-drm-amd-display-add-color-space-option-when-sending-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4488-drm-amd-display-add-color-space-option-when-sending-.patch
new file mode 100644
index 00000000..6e4654bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4488-drm-amd-display-add-color-space-option-when-sending-.patch
@@ -0,0 +1,396 @@
+From 4aa44071610a84e54543ed1afba70c295c7ab1fa Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Tue, 15 Oct 2019 15:12:57 -0400
+Subject: [PATCH 4488/4736] drm/amd/display: add color space option when
+ sending link test pattern
+
+[why]
+In the TEST_MSIC dpcd register field definition, the test equipment
+has the option to choose between YCbCr601 or YCbCr709.
+We will apply corresponding YCbCr coefficient based on this test
+request.
+
+[how]
+Add a new input parameter in dc_link_dp_set_test_pattern to allow the
+selection between different color space.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 +
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 39 +++++++++++++++++--
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 10 ++---
+ drivers/gpu/drm/amd/display/dc/dc_link.h | 2 +
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 ++++-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 16 +++++++-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h | 1 +
+ .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 7 ++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
+ .../amd/display/include/link_service_types.h | 7 ++++
+ 11 files changed, 85 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+index 2bb1fae452d9..ae5c898ade17 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+@@ -655,6 +655,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
+ dc_link_set_test_pattern(
+ link,
+ test_pattern,
++ DP_TEST_PATTERN_COLOR_SPACE_RGB,
+ &link_training_settings,
+ custom_pattern,
+ 10);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 014cb7cf9cba..ec010dc0de8b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -3333,6 +3333,7 @@ void dc_link_disable_hpd(const struct dc_link *link)
+
+ void dc_link_set_test_pattern(struct dc_link *link,
+ enum dp_test_pattern test_pattern,
++ enum dp_test_pattern_color_space test_pattern_color_space,
+ const struct link_training_settings *p_link_settings,
+ const unsigned char *p_custom_pattern,
+ unsigned int cust_pattern_size)
+@@ -3341,6 +3342,7 @@ void dc_link_set_test_pattern(struct dc_link *link,
+ dc_link_dp_set_test_pattern(
+ link,
+ test_pattern,
++ test_pattern_color_space,
+ p_link_settings,
+ p_custom_pattern,
+ cust_pattern_size);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 66f59058b56d..4e0ca8d1b484 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2507,6 +2507,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
+ dc_link_dp_set_test_pattern(
+ link,
+ test_pattern,
++ DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
+ &link_training_settings,
+ test_80_bit_pattern,
+ (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
+@@ -2518,6 +2519,8 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
+ union link_test_pattern dpcd_test_pattern;
+ union test_misc dpcd_test_params;
+ enum dp_test_pattern test_pattern;
++ enum dp_test_pattern_color_space test_pattern_color_space =
++ DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
+
+ memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
+ memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
+@@ -2552,9 +2555,14 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
+ break;
+ }
+
++ test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
++ DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
++ DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
++
+ dc_link_dp_set_test_pattern(
+ link,
+ test_pattern,
++ test_pattern_color_space,
+ NULL,
+ NULL,
+ 0);
+@@ -3350,7 +3358,8 @@ static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
+
+ static void set_crtc_test_pattern(struct dc_link *link,
+ struct pipe_ctx *pipe_ctx,
+- enum dp_test_pattern test_pattern)
++ enum dp_test_pattern test_pattern,
++ enum dp_test_pattern_color_space test_pattern_color_space)
+ {
+ enum controller_dp_test_pattern controller_test_pattern;
+ enum dc_color_depth color_depth = pipe_ctx->
+@@ -3411,8 +3420,27 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ else if (opp->funcs->opp_set_disp_pattern_generator) {
+ struct pipe_ctx *odm_pipe;
++ enum controller_dp_color_space controller_color_space;
+ int opp_cnt = 1;
+
++ switch (test_pattern_color_space) {
++ case DP_TEST_PATTERN_COLOR_SPACE_RGB:
++ controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
++ break;
++ case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
++ controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
++ break;
++ case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
++ controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
++ break;
++ case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
++ default:
++ controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
++ DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
++ ASSERT(0);
++ break;
++ }
++
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ opp_cnt++;
+
+@@ -3424,6 +3452,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
+ odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ controller_test_pattern,
++ controller_color_space,
+ color_depth,
+ NULL,
+ width,
+@@ -3431,6 +3460,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ }
+ opp->funcs->opp_set_disp_pattern_generator(opp,
+ controller_test_pattern,
++ controller_color_space,
+ color_depth,
+ NULL,
+ width,
+@@ -3464,6 +3494,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
+ odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
++ CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ color_depth,
+ NULL,
+ width,
+@@ -3471,6 +3502,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ }
+ opp->funcs->opp_set_disp_pattern_generator(opp,
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
++ CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ color_depth,
+ NULL,
+ width,
+@@ -3488,6 +3520,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ bool dc_link_dp_set_test_pattern(
+ struct dc_link *link,
+ enum dp_test_pattern test_pattern,
++ enum dp_test_pattern_color_space test_pattern_color_space,
+ const struct link_training_settings *p_link_settings,
+ const unsigned char *p_custom_pattern,
+ unsigned int cust_pattern_size)
+@@ -3516,7 +3549,7 @@ bool dc_link_dp_set_test_pattern(
+ if (link->test_pattern_enabled && test_pattern ==
+ DP_TEST_PATTERN_VIDEO_MODE) {
+ /* Set CRTC Test Pattern */
+- set_crtc_test_pattern(link, pipe_ctx, test_pattern);
++ set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
+ dp_set_hw_test_pattern(link, test_pattern,
+ (uint8_t *)p_custom_pattern,
+ (uint32_t)cust_pattern_size);
+@@ -3631,7 +3664,7 @@ bool dc_link_dp_set_test_pattern(
+ }
+ } else {
+ /* CRTC Patterns */
+- set_crtc_test_pattern(link, pipe_ctx, test_pattern);
++ set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
+ /* Set Test Pattern state */
+ link->test_pattern_enabled = true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index ef79a686e4c2..f0a6e25d2d4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -524,14 +524,14 @@ union link_test_pattern {
+
+ union test_misc {
+ struct dpcd_test_misc_bits {
+- unsigned char SYNC_CLOCK :1;
++ unsigned char SYNC_CLOCK :1;
+ /* dpcd_test_color_format */
+- unsigned char CLR_FORMAT :2;
++ unsigned char CLR_FORMAT :2;
+ /* dpcd_test_dyn_range */
+- unsigned char DYN_RANGE :1;
+- unsigned char YCBCR :1;
++ unsigned char DYN_RANGE :1;
++ unsigned char YCBCR_COEFS :1;
+ /* dpcd_test_bit_depth */
+- unsigned char BPC :3;
++ unsigned char BPC :3;
+ } bits;
+ unsigned char raw;
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 67ba6666a324..ccb68c14a806 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -260,6 +260,7 @@ void dc_link_dp_disable_hpd(const struct dc_link *link);
+ bool dc_link_dp_set_test_pattern(
+ struct dc_link *link,
+ enum dp_test_pattern test_pattern,
++ enum dp_test_pattern_color_space test_pattern_color_space,
+ const struct link_training_settings *p_link_settings,
+ const unsigned char *p_custom_pattern,
+ unsigned int cust_pattern_size);
+@@ -291,6 +292,7 @@ void dc_link_enable_hpd(const struct dc_link *link);
+ void dc_link_disable_hpd(const struct dc_link *link);
+ void dc_link_set_test_pattern(struct dc_link *link,
+ enum dp_test_pattern test_pattern,
++ enum dp_test_pattern_color_space test_pattern_color_space,
+ const struct link_training_settings *p_link_settings,
+ const unsigned char *p_custom_pattern,
+ unsigned int cust_pattern_size);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 921a36668ced..cb71b2787ddb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -225,6 +225,7 @@ void dcn20_init_blank(
+ opp->funcs->opp_set_disp_pattern_generator(
+ opp,
+ CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
++ CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ COLOR_DEPTH_UNDEFINED,
+ &black_color,
+ otg_active_width,
+@@ -234,6 +235,7 @@ void dcn20_init_blank(
+ bottom_opp->funcs->opp_set_disp_pattern_generator(
+ bottom_opp,
+ CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
++ CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ COLOR_DEPTH_UNDEFINED,
+ &black_color,
+ otg_active_width,
+@@ -855,6 +857,7 @@ void dcn20_blank_pixel_data(
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ enum dc_color_space color_space = stream->output_color_space;
+ enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
++ enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
+ struct pipe_ctx *odm_pipe;
+ int odm_cnt = 1;
+
+@@ -873,8 +876,10 @@ void dcn20_blank_pixel_data(
+ if (stream_res->abm)
+ stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
+
+- if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
++ if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
+ test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
++ test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
++ }
+ } else {
+ test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
+ }
+@@ -882,6 +887,7 @@ void dcn20_blank_pixel_data(
+ stream_res->opp->funcs->opp_set_disp_pattern_generator(
+ stream_res->opp,
+ test_pattern,
++ test_pattern_color_space,
+ stream->timing.display_color_depth,
+ &black_color,
+ width,
+@@ -892,6 +898,7 @@ void dcn20_blank_pixel_data(
+ odm_pipe->stream_res.opp,
+ dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
+ CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
++ test_pattern_color_space,
+ stream->timing.display_color_depth,
+ &black_color,
+ width,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+index 40164ed015ea..023cc71fad0f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+@@ -41,6 +41,7 @@
+ void opp2_set_disp_pattern_generator(
+ struct output_pixel_processor *opp,
+ enum controller_dp_test_pattern test_pattern,
++ enum controller_dp_color_space color_space,
+ enum dc_color_depth color_depth,
+ const struct tg_color *solid_color,
+ int width,
+@@ -100,9 +101,22 @@ void opp2_set_disp_pattern_generator(
+ TEST_PATTERN_DYN_RANGE_CEA :
+ TEST_PATTERN_DYN_RANGE_VESA);
+
++ switch (color_space) {
++ case CONTROLLER_DP_COLOR_SPACE_YCBCR601:
++ mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR601;
++ break;
++ case CONTROLLER_DP_COLOR_SPACE_YCBCR709:
++ mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR709;
++ break;
++ case CONTROLLER_DP_COLOR_SPACE_RGB:
++ default:
++ mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
++ break;
++ }
++
+ REG_UPDATE_6(DPG_CONTROL,
+ DPG_EN, 1,
+- DPG_MODE, TEST_PATTERN_MODE_COLORSQUARES_RGB,
++ DPG_MODE, mode,
+ DPG_DYNAMIC_RANGE, dyn_range,
+ DPG_BIT_DEPTH, bit_depth,
+ DPG_VRES, 6,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
+index abd8de9a78f8..4093bec172c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
+@@ -140,6 +140,7 @@ void dcn20_opp_construct(struct dcn20_opp *oppn20,
+ void opp2_set_disp_pattern_generator(
+ struct output_pixel_processor *opp,
+ enum controller_dp_test_pattern test_pattern,
++ enum controller_dp_color_space color_space,
+ enum dc_color_depth color_depth,
+ const struct tg_color *solid_color,
+ int width,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+index f82365e2d03c..91fda51e5370 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+@@ -255,6 +255,13 @@ enum controller_dp_test_pattern {
+ CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
+ };
+
++enum controller_dp_color_space {
++ CONTROLLER_DP_COLOR_SPACE_RGB,
++ CONTROLLER_DP_COLOR_SPACE_YCBCR601,
++ CONTROLLER_DP_COLOR_SPACE_YCBCR709,
++ CONTROLLER_DP_COLOR_SPACE_UDEFINED
++};
++
+ enum dc_lut_mode {
+ LUT_BYPASS,
+ LUT_RAM_A,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index 18def2b6fafe..b01ff30145fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -309,6 +309,7 @@ struct opp_funcs {
+ void (*opp_set_disp_pattern_generator)(
+ struct output_pixel_processor *opp,
+ enum controller_dp_test_pattern test_pattern,
++ enum controller_dp_color_space color_space,
+ enum dc_color_depth color_depth,
+ const struct tg_color *solid_color,
+ int width,
+diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
+index 876b0b3e1a9c..4869d4562e4d 100644
+--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
++++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
+@@ -123,6 +123,13 @@ enum dp_test_pattern {
+ DP_TEST_PATTERN_UNSUPPORTED
+ };
+
++enum dp_test_pattern_color_space {
++ DP_TEST_PATTERN_COLOR_SPACE_RGB,
++ DP_TEST_PATTERN_COLOR_SPACE_YCBCR601,
++ DP_TEST_PATTERN_COLOR_SPACE_YCBCR709,
++ DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
++};
++
+ enum dp_panel_mode {
+ /* not required */
+ DP_PANEL_MODE_DEFAULT,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch
new file mode 100644
index 00000000..d2853f2b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch
@@ -0,0 +1,51 @@
+From 5f7f2f8aea196df5274a3bf3a7ff96d119be54d7 Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Fri, 1 Nov 2019 17:29:20 -0400
+Subject: [PATCH 4489/4736] drm/amd/display: Adjust DML workaround threshold
+
+[Why]
+There is a case where the margin is between 50 and 60, but applying the
+workaround causes a hang. By increasing the threshold, we are blocking more
+cases from switching p-state during active, but those cases will fall back
+to switching during blank, which is fine.
+
+[How]
+ - increase required margin from 50 to 60
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 2 +-
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+index 77b7574c63cb..3b224b155e8c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+@@ -2578,7 +2578,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
+ + mode_lib->vba.DRAMClockChangeLatency;
+
+ if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
+- mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) {
+ mode_lib->vba.DRAMClockChangeWatermark += 25;
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 62dfd36d830a..6482d7b99bae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2612,7 +2612,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ + mode_lib->vba.DRAMClockChangeLatency;
+
+ if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
+- mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++ mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) {
+ mode_lib->vba.DRAMClockChangeWatermark += 25;
+ mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ } else if (mode_lib->vba.DummyPStateCheck &&
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4490-drm-amd-display-Add-debug-trace-for-dmcub-FW-autoloa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4490-drm-amd-display-Add-debug-trace-for-dmcub-FW-autoloa.patch
new file mode 100644
index 00000000..1dec9bea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4490-drm-amd-display-Add-debug-trace-for-dmcub-FW-autoloa.patch
@@ -0,0 +1,163 @@
+From f5b00cee7af647b42e233533666123bdc6024de3 Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Sat, 26 Oct 2019 10:19:40 -0400
+Subject: [PATCH 4490/4736] drm/amd/display: Add debug trace for dmcub FW
+ autoload.
+
+[Why & How]
+1. Add trace code enum for easy debugging.
+2. Add trace during uC boot up, including loading phy FW
+ and dmcu FW.
+3. Change cache memory type back to write back,
+ since write through has issue when resume from S0i3 100% hang after
+ 3.2ms.
+4. Change CW3 base address to hard code value to avoid memory overlap
+ with cw1.
+5. Change polling phy init done to infinite loop to avoid dcn hang when
+ dmcub uC stalled.
+6. Add dmcub FW dis-assembly file to repositatory for debug purpose.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../amd/display/dmub/inc/dmub_trace_buffer.h | 21 +++++++++++++++++--
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 2 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 20 +++++++++++-------
+ 3 files changed, 33 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+index 9707706ba8ce..b0ee099d8a6e 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+@@ -30,8 +30,25 @@
+ #define LOAD_DMCU_FW 1
+ #define LOAD_PHY_FW 2
+
++
++enum dmucb_trace_code {
++ DMCUB__UNKNOWN,
++ DMCUB__MAIN_BEGIN,
++ DMCUB__PHY_INIT_BEGIN,
++ DMCUB__PHY_FW_SRAM_LOAD_BEGIN,
++ DMCUB__PHY_FW_SRAM_LOAD_END,
++ DMCUB__PHY_INIT_POLL_DONE,
++ DMCUB__PHY_INIT_END,
++ DMCUB__DMCU_ERAM_LOAD_BEGIN,
++ DMCUB__DMCU_ERAM_LOAD_END,
++ DMCUB__DMCU_ISR_LOAD_BEGIN,
++ DMCUB__DMCU_ISR_LOAD_END,
++ DMCUB__MAIN_IDLE,
++ DMCUB__PERF_TRACE,
++};
++
+ struct dmcub_trace_buf_entry {
+- uint32_t trace_code;
++ enum dmucb_trace_code trace_code;
+ uint32_t tick_count;
+ uint32_t param0;
+ uint32_t param1;
+@@ -40,6 +57,7 @@ struct dmcub_trace_buf_entry {
+ #define TRACE_BUF_SIZE (1024) //1 kB
+ #define PERF_TRACE_MAX_ENTRY ((TRACE_BUF_SIZE - 8)/sizeof(struct dmcub_trace_buf_entry))
+
++
+ struct dmcub_trace_buf {
+ uint32_t entry_count;
+ uint32_t clk_freq;
+@@ -47,5 +65,4 @@ struct dmcub_trace_buf {
+ };
+
+
+-
+ #endif /* _DMUB_TRACE_BUFFER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 89fd27758dd5..e2b2cf2e01fd 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -138,5 +138,5 @@ bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
+
+ bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub)
+ {
+- return REG_READ(DMCUB_SCRATCH10) != 0;
++ return REG_READ(DMCUB_SCRATCH10) == 0;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 0dd32edbbcb3..5ae1906ff1b1 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -26,6 +26,8 @@
+ #include "../inc/dmub_srv.h"
+ #include "dmub_dcn20.h"
+ #include "dmub_dcn21.h"
++#include "dmub_trace_buffer.h"
++#include "os_types.h"
+ /*
+ * Note: the DMUB service is standalone. No additional headers should be
+ * added below or above this line unless they reside within the DMUB
+@@ -44,8 +46,6 @@
+ /* Mailbox size */
+ #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
+
+-/* Tracebuffer size */
+-#define DMUB_TRACEBUFF_SIZE (1024) //1kB buffer
+
+ /* Number of windows in use. */
+ #define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1)
+@@ -53,6 +53,7 @@
+
+ #define DMUB_CW0_BASE (0x60000000)
+ #define DMUB_CW1_BASE (0x61000000)
++#define DMUB_CW3_BASE (0x63000000)
+ #define DMUB_CW5_BASE (0x65000000)
+
+ static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
+@@ -181,7 +182,7 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
+ mail->top = mail->base + DMUB_MAILBOX_SIZE;
+
+ trace_buff->base = dmub_align(mail->top, 256);
+- trace_buff->top = trace_buff->base + DMUB_TRACEBUFF_SIZE;
++ trace_buff->top = trace_buff->base + TRACE_BUF_SIZE;
+
+ out->fb_size = dmub_align(trace_buff->top, 4096);
+
+@@ -291,7 +292,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ cw2.region.top = cw2.region.base + data_fb->size;
+
+ cw3.offset.quad_part = bios_fb->gpu_addr;
+- cw3.region.base = DMUB_CW1_BASE + stack_fb->size;
++ cw3.region.base = DMUB_CW3_BASE;
+ cw3.region.top = cw3.region.base + bios_fb->size;
+
+ cw4.offset.quad_part = mail_fb->gpu_addr;
+@@ -394,19 +395,24 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
+ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
+ uint32_t timeout_us)
+ {
+- uint32_t i;
++ uint32_t i = 0;
+
+ if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
+ return DMUB_STATUS_INVALID;
+
+- for (i = 0; i <= timeout_us; i += 10) {
++/* for (i = 0; i <= timeout_us; i += 10) {
+ if (dmub->hw_funcs.is_phy_init(dmub))
+ return DMUB_STATUS_OK;
+
+ udelay(10);
++ }*/
++ while (!dmub->hw_funcs.is_phy_init(dmub)) {
++ ASSERT(i <= timeout_us);
++ i += 10;
++ udelay(10);
+ }
+
+- return DMUB_STATUS_TIMEOUT;
++ return DMUB_STATUS_OK;
+ }
+
+ enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4491-drm-amd-display-3.2.60.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4491-drm-amd-display-3.2.60.patch
new file mode 100644
index 00000000..3ee4d1d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4491-drm-amd-display-3.2.60.patch
@@ -0,0 +1,28 @@
+From d93b4fe44ad3e710e20b0c58e9dd4c55dc9ebcc1 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 4 Nov 2019 08:31:14 -0500
+Subject: [PATCH 4491/4736] drm/amd/display: 3.2.60
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b107d6fab972..068c4437fdeb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.59"
++#define DC_VER "3.2.60"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4492-drm-amd-display-add-debugfs-sdp-hook-up-function-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4492-drm-amd-display-add-debugfs-sdp-hook-up-function-for.patch
new file mode 100644
index 00000000..c69a9dbf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4492-drm-amd-display-add-debugfs-sdp-hook-up-function-for.patch
@@ -0,0 +1,36 @@
+From 526eba4084b53b22121ec9f467a77410ad5dc176 Mon Sep 17 00:00:00 2001
+From: "David (Dingchen) Zhang" <dingchen.zhang@amd.com>
+Date: Thu, 31 Oct 2019 14:36:51 -0400
+Subject: [PATCH 4492/4736] drm/amd/display: add debugfs sdp hook up function
+ for Navi
+
+[why]
+need to send immediate SDP message via debugfs on Navi board.
+
+[how]
+hook up the DCN1x encoder function of sending immediate sdp
+message to DCN2.
+
+Signed-off-by: David (Dingchen) Zhang <dingchen.zhang@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index d60d072848ba..b909c526b7f9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -563,6 +563,8 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ enc2_stream_encoder_stop_hdmi_info_packets,
+ .update_dp_info_packets =
+ enc2_stream_encoder_update_dp_info_packets,
++ .send_immediate_sdp_message =
++ enc1_stream_encoder_send_immediate_sdp_message,
+ .stop_dp_info_packets =
+ enc1_stream_encoder_stop_dp_info_packets,
+ .dp_blank =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4493-drm-amd-display-Avoid-conflict-between-HDR-multiplie.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4493-drm-amd-display-Avoid-conflict-between-HDR-multiplie.patch
new file mode 100644
index 00000000..1f3478f5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4493-drm-amd-display-Avoid-conflict-between-HDR-multiplie.patch
@@ -0,0 +1,183 @@
+From 23b89fbecda472cfbce9af0e7393f9f55f0c80e8 Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Sun, 3 Nov 2019 09:35:03 -0500
+Subject: [PATCH 4493/4736] drm/amd/display: Avoid conflict between HDR
+ multiplier and 3dlut
+
+[WHY]
+There can be a conflict between OS HDR multiplier and 3dlut HDR
+multiplier, which are both sent to DC.
+
+[HOW]
+Instead of having dc determine which HDR multiplier to use, make the
+decision in dm and send only the intended value in a surface update.
+Store the current OS HDR multiplier and determine whether to use it or
+the 3dlut's multiplier before sending the surface update to dc. Send
+multiplier to dc in fixed31_32 format, dc then converts it to hw format.
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 17 ++++++++++-------
+ drivers/gpu/drm/amd/display/dc/dc.h | 9 ++++-----
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +++++++---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 10 +---------
+ 4 files changed, 22 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 7539c3accd59..66ddc2443e1e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1484,11 +1484,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
+ elevate_update_type(&update_type, UPDATE_TYPE_MED);
+ }
+
+- if (u->plane_info->sdr_white_level != u->surface->sdr_white_level) {
+- update_flags->bits.sdr_white_level = 1;
+- elevate_update_type(&update_type, UPDATE_TYPE_MED);
+- }
+-
+ if (u->plane_info->dcc.enable != u->surface->dcc.enable
+ || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
+ || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
+@@ -1635,6 +1630,12 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
+ update_flags->bits.gamma_change = 1;
+ }
+
++ if (u->hdr_mult.value)
++ if (u->hdr_mult.value != u->surface->hdr_mult.value) {
++ update_flags->bits.hdr_mult = 1;
++ elevate_update_type(&overall_type, UPDATE_TYPE_MED);
++ }
++
+ if (update_flags->bits.in_transfer_func_change) {
+ type = UPDATE_TYPE_MED;
+ elevate_update_type(&overall_type, type);
+@@ -1818,8 +1819,6 @@ static void copy_surface_update_to_plane(
+ srf_update->plane_info->global_alpha_value;
+ surface->dcc =
+ srf_update->plane_info->dcc;
+- surface->sdr_white_level =
+- srf_update->plane_info->sdr_white_level;
+ surface->layer_index =
+ srf_update->plane_info->layer_index;
+ }
+@@ -1865,6 +1864,10 @@ static void copy_surface_update_to_plane(
+ memcpy(surface->lut3d_func, srf_update->lut3d_func,
+ sizeof(*surface->lut3d_func));
+
++ if (srf_update->hdr_mult.value)
++ surface->hdr_mult =
++ srf_update->hdr_mult;
++
+ if (srf_update->blend_tf &&
+ (surface->blend_tf !=
+ srf_update->blend_tf))
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 068c4437fdeb..8af7014b1588 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -690,7 +690,7 @@ union dc_3dlut_state {
+ struct dc_3dlut {
+ struct kref refcount;
+ struct tetrahedral_params lut_3d;
+- uint32_t hdr_multiplier;
++ struct fixed31_32 hdr_multiplier;
+ bool initialized; /*remove after diag fix*/
+ union dc_3dlut_state state;
+ struct dc_context *ctx;
+@@ -718,7 +718,7 @@ union surface_update_flags {
+ uint32_t horizontal_mirror_change:1;
+ uint32_t per_pixel_alpha_change:1;
+ uint32_t global_alpha_change:1;
+- uint32_t sdr_white_level:1;
++ uint32_t hdr_mult:1;
+ uint32_t rotation_change:1;
+ uint32_t swizzle_change:1;
+ uint32_t scaling_change:1;
+@@ -764,7 +764,7 @@ struct dc_plane_state {
+ struct dc_bias_and_scale *bias_and_scale;
+ struct dc_csc_transform input_csc_color_matrix;
+ struct fixed31_32 coeff_reduction_factor;
+- uint32_t sdr_white_level;
++ struct fixed31_32 hdr_mult;
+
+ // TODO: No longer used, remove
+ struct dc_hdr_static_metadata hdr_static_ctx;
+@@ -811,7 +811,6 @@ struct dc_plane_info {
+ enum dc_rotation_angle rotation;
+ enum plane_stereo_format stereo_format;
+ enum dc_color_space color_space;
+- unsigned int sdr_white_level;
+ bool horizontal_mirror;
+ bool visible;
+ bool per_pixel_alpha;
+@@ -835,7 +834,7 @@ struct dc_surface_update {
+ const struct dc_flip_addrs *flip_addr;
+ const struct dc_plane_info *plane_info;
+ const struct dc_scaling_info *scaling_info;
+-
++ struct fixed31_32 hdr_mult;
+ /* following updates require alloc/sleep/spin that is not isr safe,
+ * null means no updates
+ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 4b6213d3ecbf..c8bd1c0cdb45 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2471,16 +2471,20 @@ static void dcn10_blank_pixel_data(
+
+ void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
+ {
+- struct fixed31_32 multiplier = dc_fixpt_from_fraction(
+- pipe_ctx->plane_state->sdr_white_level, 80);
++ struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
+ uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
+ struct custom_float_format fmt;
++ bool mult_negative; // True if fixed31_32 sign bit indicates negative value
++ uint32_t mult_int; // int component of fixed31_32
+
+ fmt.exponenta_bits = 6;
+ fmt.mantissa_bits = 12;
+ fmt.sign = true;
+
+- if (pipe_ctx->plane_state->sdr_white_level > 80)
++ mult_negative = multiplier.value >> 63 != 0;
++ mult_int = multiplier.value >> 32;
++
++ if (mult_int && !mult_negative) // Check if greater than 1
+ convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
+
+ pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index cb71b2787ddb..92117b6d0012 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -738,14 +738,6 @@ bool dcn20_set_shaper_3dlut(
+ else
+ result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
+
+- if (plane_state->lut3d_func &&
+- plane_state->lut3d_func->state.bits.initialized == 1 &&
+- plane_state->lut3d_func->hdr_multiplier != 0)
+- dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
+- plane_state->lut3d_func->hdr_multiplier);
+- else
+- dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000);
+-
+ return result;
+ }
+
+@@ -1386,7 +1378,7 @@ static void dcn20_program_pipe(
+ dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
+
+ if (pipe_ctx->update_flags.bits.enable
+- || pipe_ctx->plane_state->update_flags.bits.sdr_white_level)
++ || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
+ set_hdr_multiplier(pipe_ctx);
+
+ if (pipe_ctx->update_flags.bits.enable ||
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4494-drm-amd-display-Don-t-spin-forever-waiting-for-DMCUB.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4494-drm-amd-display-Don-t-spin-forever-waiting-for-DMCUB.patch
new file mode 100644
index 00000000..e7f45eed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4494-drm-amd-display-Don-t-spin-forever-waiting-for-DMCUB.patch
@@ -0,0 +1,68 @@
+From 19ec27063b8d4efbfcd0c9f2c0399ce53b87a2bb Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 4 Nov 2019 13:32:46 -0500
+Subject: [PATCH 4494/4736] drm/amd/display: Don't spin forever waiting for
+ DMCUB phy/auto init
+
+[Why]
+It's an interface violation to use infinite loops within DMUB
+service functions and we'll lock up the kernel by doing so.
+
+[How]
+Revert the function back to its intended functionality.
+Move the infinite loops into DC/DM as necessary.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 6 ++++--
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 9 ++-------
+ 2 files changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+index 61cefe0a3790..74ffe53eb49d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+@@ -112,8 +112,10 @@ void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
+ struct dc_context *dc_ctx = dc_dmub_srv->ctx;
+ enum dmub_status status;
+
+- status = dmub_srv_wait_for_phy_init(dmub, 1000000);
+- if (status != DMUB_STATUS_OK)
++ status = dmub_srv_wait_for_phy_init(dmub, 10000000);
++ if (status != DMUB_STATUS_OK) {
+ DC_ERROR("Error waiting for DMUB phy init: status=%d\n",
+ status);
++ ASSERT(0);
++ }
+ }
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 5ae1906ff1b1..60c574a39c6a 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -400,19 +400,14 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
+ if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
+ return DMUB_STATUS_INVALID;
+
+-/* for (i = 0; i <= timeout_us; i += 10) {
++ for (i = 0; i <= timeout_us; i += 10) {
+ if (dmub->hw_funcs.is_phy_init(dmub))
+ return DMUB_STATUS_OK;
+
+ udelay(10);
+- }*/
+- while (!dmub->hw_funcs.is_phy_init(dmub)) {
+- ASSERT(i <= timeout_us);
+- i += 10;
+- udelay(10);
+ }
+
+- return DMUB_STATUS_OK;
++ return DMUB_STATUS_TIMEOUT;
+ }
+
+ enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch
new file mode 100644
index 00000000..4903443e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch
@@ -0,0 +1,795 @@
+From 83f4f8104261c5f2877e3b21909ed8a9d49a59c3 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Thu, 31 Oct 2019 15:53:24 -0400
+Subject: [PATCH 4495/4736] drm/amd/display: DML Validation Dump/Check with
+ Logging
+
+[Why]
+Need validation that we are programming the expected values (rq, ttu, dlg)
+from DML. This debug feature will output logs if we are programming
+incorrect values and may help differentiate DAL issues from HW issues.
+
+[How]
+Dump relevant registers for each pipe with active stream. Compare current
+reg values with the converted DML output. Log mismatches when found.
+
+Change-Id: I42f3f19de1f0330ddb2c0c877aa32cd7798205b0
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 18 +-
+ drivers/gpu/drm/amd/display/dc/dc.h | 1 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 310 ++++++++++++++++
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 345 ++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 7 +
+ 5 files changed, 680 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 66ddc2443e1e..81f4499490b9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2198,8 +2198,24 @@ static void commit_planes_for_stream(struct dc *dc,
+ }
+ }
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+- if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST)
++ if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ dc->hwss.program_front_end_for_ctx(dc, context);
++#ifdef CONFIG_DRM_AMD_DC_DCN1_0
++ if (dc->debug.validate_dml_output) {
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
++ struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
++ if (cur_pipe.stream == NULL)
++ continue;
++
++ cur_pipe.plane_res.hubp->funcs->validate_dml_output(
++ cur_pipe.plane_res.hubp, dc->ctx,
++ &context->res_ctx.pipe_ctx[i].rq_regs,
++ &context->res_ctx.pipe_ctx[i].dlg_regs,
++ &context->res_ctx.pipe_ctx[i].ttu_regs);
++ }
++ }
++#endif
++ }
+ #endif
+
+ // Update Type FAST, Surface updates
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 8af7014b1588..bc422728dd54 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -424,6 +424,7 @@ struct dc_debug_options {
+
+ bool nv12_iflip_vm_wa;
+ bool disable_dram_clock_change_vactive_support;
++ bool validate_dml_output;
+ };
+
+ struct dc_debug_data {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 391f0629b955..4c60fa4b89e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -30,6 +30,8 @@
+ #include "reg_helper.h"
+ #include "basics/conversion.h"
+
++#define DC_LOGGER_INIT(logger)
++
+ #define REG(reg)\
+ hubp2->hubp_regs->reg
+
+@@ -1246,6 +1248,313 @@ void hubp2_read_state(struct hubp *hubp)
+
+ }
+
++void hubp2_validate_dml_output(struct hubp *hubp,
++ struct dc_context *ctx,
++ struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
++ struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
++ struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
++{
++ struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++ struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
++ struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
++ struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
++ DC_LOGGER_INIT(ctx->logger);
++
++ /* Requestor Regs */
++ REG_GET(HUBPRET_CONTROL,
++ DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
++ REG_GET_4(DCN_EXPANSION_MODE,
++ DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
++ PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
++ MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
++ CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
++ CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
++ MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
++ META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
++ MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
++ DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
++ MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
++ SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
++ PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
++ CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
++ MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
++ META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
++ MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
++ DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
++ MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
++ SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
++ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
++
++ if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
++ DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
++ dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
++ if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
++ dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
++ if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
++ dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
++ if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
++ dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
++ if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
++ dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
++
++ if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
++ if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
++ if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
++ if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
++ if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
++ if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
++ if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
++ if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
++
++ if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
++ if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
++ if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
++ if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
++ if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
++ if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
++ if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
++ if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
++
++ /* DLG - Per hubp */
++ REG_GET_2(BLANK_OFFSET_0,
++ REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
++ DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
++ REG_GET(BLANK_OFFSET_1,
++ MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
++ REG_GET(DST_DIMENSIONS,
++ REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
++ REG_GET_2(DST_AFTER_SCALER,
++ REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
++ DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
++ REG_GET(REF_FREQ_TO_PIX_FREQ,
++ REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
++
++ if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
++ if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
++ if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",
++ dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
++ if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
++ DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
++ if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
++ if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
++ if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
++ DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",
++ dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
++
++ /* DLG - Per luma/chroma */
++ REG_GET(VBLANK_PARAMETERS_1,
++ REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
++ if (REG(NOM_PARAMETERS_0))
++ REG_GET(NOM_PARAMETERS_0,
++ DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
++ if (REG(NOM_PARAMETERS_1))
++ REG_GET(NOM_PARAMETERS_1,
++ REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
++ REG_GET(NOM_PARAMETERS_4,
++ DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
++ REG_GET(NOM_PARAMETERS_5,
++ REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
++ REG_GET_2(PER_LINE_DELIVERY,
++ REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
++ REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
++ REG_GET_2(PER_LINE_DELIVERY_PRE,
++ REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
++ REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
++ REG_GET(VBLANK_PARAMETERS_2,
++ REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
++ if (REG(NOM_PARAMETERS_2))
++ REG_GET(NOM_PARAMETERS_2,
++ DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
++ if (REG(NOM_PARAMETERS_3))
++ REG_GET(NOM_PARAMETERS_3,
++ REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
++ REG_GET(NOM_PARAMETERS_6,
++ DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
++ REG_GET(NOM_PARAMETERS_7,
++ REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
++ REG_GET(VBLANK_PARAMETERS_3,
++ REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
++ REG_GET(VBLANK_PARAMETERS_4,
++ REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++ if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
++ if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
++ if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
++ if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
++ if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
++ if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
++ if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
++ if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
++ if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
++ if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
++ if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
++ if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
++ if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
++ if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
++ if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
++ if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++ /* TTU - per hubp */
++ REG_GET_2(DCN_TTU_QOS_WM,
++ QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
++ QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
++
++ if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
++ if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
++
++ /* TTU - per luma/chroma */
++ /* Assumed surf0 is luma and 1 is chroma */
++ REG_GET_3(DCN_SURF0_TTU_CNTL0,
++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
++ REG_GET_3(DCN_SURF1_TTU_CNTL0,
++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
++ REG_GET_3(DCN_CUR0_TTU_CNTL0,
++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
++ REG_GET(FLIP_PARAMETERS_1,
++ REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
++ REG_GET(DCN_CUR0_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
++ REG_GET(DCN_CUR1_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
++ REG_GET(DCN_SURF0_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
++ REG_GET(DCN_SURF1_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
++
++ if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
++ if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
++ if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
++ if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
++ if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
++ if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
++ if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
++ if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
++ if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
++ if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
++ if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
++ if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
++ if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
++ if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
++}
++
+ static struct hubp_funcs dcn20_hubp_funcs = {
+ .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+ .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+@@ -1269,6 +1578,7 @@ static struct hubp_funcs dcn20_hubp_funcs = {
+ .hubp_clear_underflow = hubp2_clear_underflow,
+ .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+ .hubp_init = hubp1_init,
++ .validate_dml_output = hubp2_validate_dml_output,
+ };
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 32e8b589aeb5..0be1c917b242 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -29,6 +29,8 @@
+ #include "dm_services.h"
+ #include "reg_helper.h"
+
++#define DC_LOGGER_INIT(logger)
++
+ #define REG(reg)\
+ hubp21->hubp_regs->reg
+
+@@ -254,6 +256,348 @@ void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
+ SYSTEM_ACCESS_MODE, 0x3);
+ }
+
++void hubp21_validate_dml_output(struct hubp *hubp,
++ struct dc_context *ctx,
++ struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
++ struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
++ struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
++{
++ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++ struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
++ struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
++ struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
++ DC_LOGGER_INIT(ctx->logger);
++
++ /* Requester - Per hubp */
++ REG_GET(HUBPRET_CONTROL,
++ DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
++ REG_GET_4(DCN_EXPANSION_MODE,
++ DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
++ PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
++ MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
++ CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
++ CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
++ MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
++ META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
++ MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
++ DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
++ VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
++ SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
++ PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
++ REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
++ CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
++ MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
++ META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
++ MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
++ DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
++ SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
++ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
++
++ if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
++ DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
++ dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
++ if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
++ dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
++ if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
++ dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
++ if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
++ dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
++ if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
++ DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
++ dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
++
++ if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
++ if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
++ if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
++ if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
++ if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
++ if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
++ if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
++ if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
++
++ if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
++ if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
++ if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
++ if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
++ if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
++ if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
++ if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
++ DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",
++ dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
++
++
++ /* DLG - Per hubp */
++ REG_GET_2(BLANK_OFFSET_0,
++ REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
++ DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
++ REG_GET(BLANK_OFFSET_1,
++ MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
++ REG_GET(DST_DIMENSIONS,
++ REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
++ REG_GET_2(DST_AFTER_SCALER,
++ REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
++ DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
++ REG_GET(REF_FREQ_TO_PIX_FREQ,
++ REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
++
++ if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
++ if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
++ if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
++ DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",
++ dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
++ if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
++ DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
++ if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
++ if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
++ DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
++ if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
++ DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",
++ dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
++
++ /* DLG - Per luma/chroma */
++ REG_GET(VBLANK_PARAMETERS_1,
++ REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
++ if (REG(NOM_PARAMETERS_0))
++ REG_GET(NOM_PARAMETERS_0,
++ DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
++ if (REG(NOM_PARAMETERS_1))
++ REG_GET(NOM_PARAMETERS_1,
++ REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
++ REG_GET(NOM_PARAMETERS_4,
++ DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
++ REG_GET(NOM_PARAMETERS_5,
++ REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
++ REG_GET_2(PER_LINE_DELIVERY,
++ REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
++ REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
++ REG_GET_2(PER_LINE_DELIVERY_PRE,
++ REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
++ REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
++ REG_GET(VBLANK_PARAMETERS_2,
++ REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
++ if (REG(NOM_PARAMETERS_2))
++ REG_GET(NOM_PARAMETERS_2,
++ DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
++ if (REG(NOM_PARAMETERS_3))
++ REG_GET(NOM_PARAMETERS_3,
++ REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
++ REG_GET(NOM_PARAMETERS_6,
++ DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
++ REG_GET(NOM_PARAMETERS_7,
++ REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
++ REG_GET(VBLANK_PARAMETERS_3,
++ REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
++ REG_GET(VBLANK_PARAMETERS_4,
++ REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++ if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
++ if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
++ if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
++ if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
++ if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
++ if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
++ if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
++ if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
++ if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
++ if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
++ if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
++ if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
++ DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
++ if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
++ if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
++ DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
++ if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
++ if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++ /* TTU - per hubp */
++ REG_GET_2(DCN_TTU_QOS_WM,
++ QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
++ QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
++
++ if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
++ if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
++ DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
++
++ /* TTU - per luma/chroma */
++ /* Assumed surf0 is luma and 1 is chroma */
++ REG_GET_3(DCN_SURF0_TTU_CNTL0,
++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
++ REG_GET_3(DCN_SURF1_TTU_CNTL0,
++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
++ REG_GET_3(DCN_CUR0_TTU_CNTL0,
++ REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
++ QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
++ QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
++ REG_GET(FLIP_PARAMETERS_1,
++ REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
++ REG_GET(DCN_CUR0_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
++ REG_GET(DCN_CUR1_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
++ REG_GET(DCN_SURF0_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
++ REG_GET(DCN_SURF1_TTU_CNTL1,
++ REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
++
++ if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
++ if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
++ if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
++ if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
++ if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
++ if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
++ if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
++ if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
++ if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
++ if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
++ if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
++ if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
++ DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
++ if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
++ if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
++ DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
++ dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
++
++ /* Host VM deadline regs */
++ REG_GET(VBLANK_PARAMETERS_5,
++ REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank);
++ REG_GET(VBLANK_PARAMETERS_6,
++ REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank);
++ REG_GET(FLIP_PARAMETERS_3,
++ REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip);
++ REG_GET(FLIP_PARAMETERS_4,
++ REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip);
++ REG_GET(FLIP_PARAMETERS_5,
++ REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c);
++ REG_GET(FLIP_PARAMETERS_6,
++ REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c);
++ REG_GET(FLIP_PARAMETERS_2,
++ REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l);
++
++ if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank);
++ if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank)
++ DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank);
++ if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip)
++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip);
++ if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip)
++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip);
++ if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c)
++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c);
++ if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c)
++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c);
++ if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l)
++ DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n",
++ dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l);
++}
++
+ void hubp21_init(struct hubp *hubp)
+ {
+ // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
+@@ -286,6 +630,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
+ .hubp_clear_underflow = hubp1_clear_underflow,
+ .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+ .hubp_init = hubp21_init,
++ .validate_dml_output = hubp21_validate_dml_output,
+ };
+
+ bool hubp21_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 809b62b51a43..9def990d40a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -161,6 +161,13 @@ struct hubp_funcs {
+ bool enable);
+ #endif
+
++ void (*validate_dml_output)(
++ struct hubp *hubp,
++ struct dc_context *ctx,
++ struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
++ struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
++ struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
++
+ };
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4496-drm-amd-display-Spin-for-DMCUB-PHY-init-in-DC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4496-drm-amd-display-Spin-for-DMCUB-PHY-init-in-DC.patch
new file mode 100644
index 00000000..c4ce7cb3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4496-drm-amd-display-Spin-for-DMCUB-PHY-init-in-DC.patch
@@ -0,0 +1,62 @@
+From c56c8bc443366b91351ad9f2f248b09fdc6da1da Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 5 Nov 2019 12:51:51 -0500
+Subject: [PATCH 4496/4736] drm/amd/display: Spin for DMCUB PHY init in DC
+
+[Why]
+DCN will hang if we access registers before PHY init is done.
+
+So we need to spin or abort.
+
+[How]
+On hardware with DMCUB running and working we shouldn't time out
+waiting for this to finish and we shouldn't hit the spin cycle.
+
+If there's no hardware support then we should exit out of the function
+early assuming that PHY init was already done elsewhere.
+
+If we hit the timeout then there's likely a bug in firmware or software
+and we need to debug - add errors and asserts as appropriate.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 21 ++++++++++++++++----
+ 1 file changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+index 74ffe53eb49d..03e2842cb573 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+@@ -112,10 +112,23 @@ void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
+ struct dc_context *dc_ctx = dc_dmub_srv->ctx;
+ enum dmub_status status;
+
+- status = dmub_srv_wait_for_phy_init(dmub, 10000000);
+- if (status != DMUB_STATUS_OK) {
+- DC_ERROR("Error waiting for DMUB phy init: status=%d\n",
+- status);
++ for (;;) {
++ /* Wait up to a second for PHY init. */
++ status = dmub_srv_wait_for_phy_init(dmub, 1000000);
++ if (status == DMUB_STATUS_OK)
++ /* Initialization OK */
++ break;
++
++ DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
+ ASSERT(0);
++
++ if (status != DMUB_STATUS_TIMEOUT)
++ /*
++ * Server likely initialized or we don't have
++ * DMCUB HW support - this won't end.
++ */
++ break;
++
++ /* Continue spinning so we don't hang the ASIC. */
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4497-drm-amd-display-Add-DSC-422Native-debug-option.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4497-drm-amd-display-Add-DSC-422Native-debug-option.patch
new file mode 100644
index 00000000..4ffe87de
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4497-drm-amd-display-Add-DSC-422Native-debug-option.patch
@@ -0,0 +1,61 @@
+From ac153fe111ca34f00f37d17b89a4c2c3a700650d Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Thu, 3 Oct 2019 17:35:32 -0400
+Subject: [PATCH 4497/4736] drm/amd/display: Add DSC 422Native debug option
+
+[Why]
+Need to be able to enable native 422 for debugging purposes.
+
+[How]
+Add new dc_debug_options bool and check it in the get_dsc_enc_caps
+function.
+
+Change-Id: I4acc72d0faf363ef1b278708db94f353471c5d01
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 1 +
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 6 +++++-
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index bc422728dd54..18fdd61a606b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -368,6 +368,7 @@ struct dc_debug_options {
+ bool disable_dsc_power_gate;
+ int dsc_min_slice_height_override;
+ #endif
++ bool native422_support;
+ bool disable_pplib_wm_range;
+ enum wm_report_mode pplib_wm_report_mode;
+ unsigned int min_disp_clk_khz;
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index e60f760585e4..f76a72a96631 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -26,6 +26,7 @@
+ #include "dc_hw_types.h"
+ #include "dsc.h"
+ #include <drm/drm_dp_helper.h>
++#include "dc.h"
+
+ struct dc_dsc_policy {
+ bool use_min_slices_h;
+@@ -237,8 +238,11 @@ static void get_dsc_enc_caps(
+ // This is a static HW query, so we can use any DSC
+
+ memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
+- if (dsc)
++ if (dsc) {
+ dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
++ if (dsc->ctx->dc->debug.native422_support)
++ dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
++ }
+ }
+
+ /* Returns 'false' if no intersection was found for at least one capablity.
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4498-drm-amd-display-Add-Navi10-DMUB-VBIOS-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4498-drm-amd-display-Add-Navi10-DMUB-VBIOS-code.patch
new file mode 100644
index 00000000..6ed8e5ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4498-drm-amd-display-Add-Navi10-DMUB-VBIOS-code.patch
@@ -0,0 +1,45 @@
+From 7557fd5567be9994f4235ca9a074145b8067ce77 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 4 Nov 2019 15:36:16 -0500
+Subject: [PATCH 4498/4736] drm/amd/display: Add Navi10 DMUB VBIOS code
+
+[Why]
+We need some extra dmub_cmd_type for NV10
+
+[How]
+Add command table functions in DMUB firmware.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Xiong Yan <Xiong.Yan@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+index b25f92e3280d..43f1cd647aab 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+@@ -45,6 +45,17 @@ enum dmub_cmd_type {
+ DMUB_CMD__ENABLE_DISP_POWER_GATING,
+ DMUB_CMD__DPPHY_INIT,
+ DMUB_CMD__DIG1_TRANSMITTER_CONTROL,
++ DMUB_CMD__SETUP_DISPLAY_MODE,
++ DMUB_CMD__BLANK_CRTC,
++ DMUB_CMD__ENABLE_DISPPATH,
++ DMUB_CMD__DISABLE_DISPPATH,
++ DMUB_CMD__DISABLE_DISPPATH_OUTPUT,
++ DMUB_CMD__READ_DISPPATH_EDID,
++ DMUB_CMD__DP_PRE_LINKTRAINING,
++ DMUB_CMD__INIT_CONTROLLER,
++ DMUB_CMD__RESET_CONTROLLER,
++ DMUB_CMD__SET_BRI_LEVEL,
++ DMUB_CMD__LVTMA_CONTROL,
+
+ // PSR
+ DMUB_CMD__PSR_ENABLE,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4499-drm-amd-display-add-automated-audio-test-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4499-drm-amd-display-add-automated-audio-test-support.patch
new file mode 100644
index 00000000..38ff0e30
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4499-drm-amd-display-add-automated-audio-test-support.patch
@@ -0,0 +1,234 @@
+From c8b372b25d04f3b1747ce7df0680b109740d9f0f Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Fri, 26 Jul 2019 11:25:43 -0400
+Subject: [PATCH 4499/4736] drm/amd/display: add automated audio test support
+
+Change-Id: I2b01c053888b2bb3e1f117af591c8dd3f3a36111
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 92 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 48 ++++++++--
+ drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
+ include/drm/drm_dp_helper.h | 15 +++
+ 4 files changed, 149 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 4e0ca8d1b484..a32626864154 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2568,6 +2568,92 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
+ 0);
+ }
+
++static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
++{
++ union audio_test_mode dpcd_test_mode = {0};
++ struct audio_test_pattern_type dpcd_pattern_type = {0};
++ union audio_test_pattern_period dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
++ enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
++
++ struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
++ struct pipe_ctx *pipe_ctx = &pipes[0];
++ unsigned int channel_count;
++ unsigned int channel = 0;
++ unsigned int modes = 0;
++ unsigned int sampling_rate_in_hz = 0;
++
++ // get audio test mode and test pattern parameters
++ core_link_read_dpcd(
++ link,
++ DP_TEST_AUDIO_MODE,
++ &dpcd_test_mode.raw,
++ sizeof(dpcd_test_mode));
++
++ core_link_read_dpcd(
++ link,
++ DP_TEST_AUDIO_PATTERN_TYPE,
++ &dpcd_pattern_type.value,
++ sizeof(dpcd_pattern_type));
++
++ channel_count = dpcd_test_mode.bits.channel_count + 1;
++
++ // read pattern periods for requested channels when sawTooth pattern is requested
++ if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
++ dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
++
++ test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
++ DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
++ // read period for each channel
++ for (channel = 0; channel < channel_count; channel++) {
++ core_link_read_dpcd(
++ link,
++ DP_TEST_AUDIO_PERIOD_CH1 + channel,
++ &dpcd_pattern_period[channel].raw,
++ sizeof(dpcd_pattern_period[channel]));
++ }
++ }
++
++ // translate sampling rate
++ switch (dpcd_test_mode.bits.sampling_rate) {
++ case AUDIO_SAMPLING_RATE_32KHZ:
++ sampling_rate_in_hz = 32000;
++ break;
++ case AUDIO_SAMPLING_RATE_44_1KHZ:
++ sampling_rate_in_hz = 44100;
++ break;
++ case AUDIO_SAMPLING_RATE_48KHZ:
++ sampling_rate_in_hz = 48000;
++ break;
++ case AUDIO_SAMPLING_RATE_88_2KHZ:
++ sampling_rate_in_hz = 88200;
++ break;
++ case AUDIO_SAMPLING_RATE_96KHZ:
++ sampling_rate_in_hz = 96000;
++ break;
++ case AUDIO_SAMPLING_RATE_176_4KHZ:
++ sampling_rate_in_hz = 176400;
++ break;
++ case AUDIO_SAMPLING_RATE_192KHZ:
++ sampling_rate_in_hz = 192000;
++ break;
++ default:
++ sampling_rate_in_hz = 0;
++ break;
++ }
++
++ link->audio_test_data.flags.test_requested = 1;
++ link->audio_test_data.flags.disable_video = disable_video;
++ link->audio_test_data.sampling_rate = sampling_rate_in_hz;
++ link->audio_test_data.channel_count = channel_count;
++ link->audio_test_data.pattern_type = test_pattern;
++
++ if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
++ for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
++ link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
++ }
++ }
++}
++
+ static void handle_automated_test(struct dc_link *link)
+ {
+ union test_request test_request;
+@@ -2597,6 +2683,12 @@ static void handle_automated_test(struct dc_link *link)
+ dp_test_send_link_test_pattern(link);
+ test_response.bits.ACK = 1;
+ }
++
++ if (test_request.bits.AUDIO_TEST_PATTERN) {
++ dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
++ test_response.bits.ACK = 1;
++ }
++
+ if (test_request.bits.PHY_TEST_PATTERN) {
+ dp_test_send_phy_test_pattern(link);
+ test_response.bits.ACK = 1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index f0a6e25d2d4a..28234d8fdb2c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -471,13 +471,13 @@ union training_aux_rd_interval {
+ /* Automated test structures */
+ union test_request {
+ struct {
+- uint8_t LINK_TRAINING :1;
+- uint8_t LINK_TEST_PATTRN :1;
+- uint8_t EDID_READ :1;
+- uint8_t PHY_TEST_PATTERN :1;
+- uint8_t AUDIO_TEST_PATTERN :1;
+- uint8_t RESERVED :1;
+- uint8_t TEST_STEREO_3D :1;
++ uint8_t LINK_TRAINING :1;
++ uint8_t LINK_TEST_PATTRN :1;
++ uint8_t EDID_READ :1;
++ uint8_t PHY_TEST_PATTERN :1;
++ uint8_t RESERVED :1;
++ uint8_t AUDIO_TEST_PATTERN :1;
++ uint8_t TEST_AUDIO_DISABLED_VIDEO :1;
+ } bits;
+ uint8_t raw;
+ };
+@@ -536,6 +536,40 @@ union test_misc {
+ unsigned char raw;
+ };
+
++union audio_test_mode {
++ struct {
++ unsigned char sampling_rate :4;
++ unsigned char channel_count :4;
++ } bits;
++ unsigned char raw;
++};
++
++union audio_test_pattern_period {
++ struct {
++ unsigned char pattern_period :4;
++ unsigned char reserved :4;
++ } bits;
++ unsigned char raw;
++};
++
++struct audio_test_pattern_type {
++ unsigned char value;
++};
++
++struct dp_audio_test_data_flags {
++ uint8_t test_requested :1;
++ uint8_t disable_video :1;
++};
++
++struct dp_audio_test_data {
++
++ struct dp_audio_test_data_flags flags;
++ uint8_t sampling_rate;
++ uint8_t channel_count;
++ uint8_t pattern_type;
++ uint8_t pattern_period[8];
++};
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* FEC capability DPCD register field bits-*/
+ union dpcd_fec_capability {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index ccb68c14a806..03efdc1a7b03 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -96,6 +96,7 @@ struct dc_link {
+ struct dc_lane_settings cur_lane_setting;
+ struct dc_link_settings preferred_link_setting;
+ struct dc_link_training_overrides preferred_training_settings;
++ struct dp_audio_test_data audio_test_data;
+
+ uint8_t ddc_hw_inst;
+
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index 4f9184a238dd..5de6fa29300e 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -61,6 +61,21 @@
+ #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
+ #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
+
++
++#if !defined(DP_TEST_AUDIO_MODE)
++#define DP_TEST_AUDIO_MODE 0x271
++#endif
++
++#if !defined(DP_TEST_AUDIO_PATTERN_TYPE)
++#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
++#endif
++
++#if !defined(DP_TEST_AUDIO_PERIOD_CH1)
++#define DP_TEST_AUDIO_PERIOD_CH1 0x273
++#endif
++
++
++
+ /* AUX CH addresses */
+ /* DPCD */
+ #define DP_DPCD_REV 0x000
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4500-drm-amd-display-Add-PSP-block-to-verify-HDCP2.2-step.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4500-drm-amd-display-Add-PSP-block-to-verify-HDCP2.2-step.patch
new file mode 100644
index 00000000..42e9d2af
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4500-drm-amd-display-Add-PSP-block-to-verify-HDCP2.2-step.patch
@@ -0,0 +1,863 @@
+From 960ca96c1baf29d4050e20323e0a8ac78b018125 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:19:51 -0400
+Subject: [PATCH 4500/4736] drm/amd/display: Add PSP block to verify HDCP2.2
+ steps
+
+[Why]
+All the HDCP transactions should be verified using PSP
+
+[How]
+This patch adds the psp calls we need to verify the steps
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 44 ++
+ .../drm/amd/display/modules/hdcp/hdcp_psp.c | 502 +++++++++++++++++-
+ .../drm/amd/display/modules/hdcp/hdcp_psp.h | 194 +++++++
+ 3 files changed, 739 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index 5664bc0b5bd0..d83f0ab1cadb 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -111,8 +111,33 @@ struct mod_hdcp_message_hdcp1 {
+ uint16_t binfo_dp;
+ };
+
++struct mod_hdcp_message_hdcp2 {
++ uint8_t hdcp2version_hdmi;
++ uint8_t rxcaps_dp[3];
++ uint16_t rxstatus;
++
++ uint8_t ake_init[12];
++ uint8_t ake_cert[534];
++ uint8_t ake_no_stored_km[129];
++ uint8_t ake_stored_km[33];
++ uint8_t ake_h_prime[33];
++ uint8_t ake_pairing_info[17];
++ uint8_t lc_init[9];
++ uint8_t lc_l_prime[33];
++ uint8_t ske_eks[25];
++ uint8_t rx_id_list[177]; // 22 + 5 * 31
++ uint16_t rx_id_list_size;
++ uint8_t repeater_auth_ack[17];
++ uint8_t repeater_auth_stream_manage[68]; // 6 + 2 * 31
++ uint16_t stream_manage_size;
++ uint8_t repeater_auth_stream_ready[33];
++
++ uint8_t content_stream_type_dp[2];
++};
++
+ union mod_hdcp_message {
+ struct mod_hdcp_message_hdcp1 hdcp1;
++ struct mod_hdcp_message_hdcp2 hdcp2;
+ };
+
+ struct mod_hdcp_auth_counters {
+@@ -234,6 +259,25 @@ enum mod_hdcp_status mod_hdcp_hdcp1_enable_dp_stream_encryption(
+ enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *hdcp,
+ enum mod_hdcp_encryption_status *encryption_status);
++enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_ake_init(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_ake_cert(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_h_prime(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_lc_init(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_l_prime(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_eks(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_rx_id_list(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(
++ struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_stream_management(
++ struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_stream_ready(
++ struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_get_link_encryption_status(struct mod_hdcp *hdcp,
++ enum mod_hdcp_encryption_status *encryption_status);
++
+ /* ddc functions */
+ enum mod_hdcp_status mod_hdcp_read_bksv(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_bcaps(struct mod_hdcp *hdcp);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index 646d909bbc37..ddba0cfa5722 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -31,6 +31,19 @@
+ #include "amdgpu.h"
+ #include "hdcp_psp.h"
+
++static void hdcp2_message_init(struct mod_hdcp *hdcp,
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *in)
++{
++ in->session_handle = hdcp->auth.id;
++ in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++ in->prepare.msg2_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++ in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++ in->process.msg1_desc.msg_size = 0;
++ in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++ in->process.msg2_desc.msg_size = 0;
++ in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++ in->process.msg3_desc.msg_id = 0;
++}
+ enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
+ {
+
+@@ -42,7 +55,7 @@ enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
+ dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
+
+ for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
+- if (hdcp->connection.displays[i].state == MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED) {
++ if (is_display_added(&(hdcp->connection.displays[i]))) {
+
+ memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
+
+@@ -326,3 +339,490 @@ enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *
+ return MOD_HDCP_STATUS_SUCCESS;
+ }
+
++enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct mod_hdcp_display *display = get_first_added_display(hdcp);
++
++ if (!psp->hdcp_context.hdcp_initialized) {
++ DRM_ERROR("Failed to create hdcp session, HDCP TA is not initialized");
++ return MOD_HDCP_STATUS_FAILURE;
++ }
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ if (!display)
++ return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
++
++ hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = display->index;
++
++ if (hdcp->connection.link.adjust.hdcp2.disable_type1)
++ hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
++ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE0;
++ else
++ hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
++ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__MAX_SUPPORTED;
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_CREATE_SESSION_V2;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE;
++
++ hdcp->auth.id = hdcp_cmd->out_msg.hdcp2_create_session_v2.session_handle;
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ hdcp_cmd->in_msg.hdcp2_destroy_session.session_handle = hdcp->auth.id;
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_DESTROY_SESSION;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE;
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_ake_init(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++ msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__AKE_INIT;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE;
++
++ memcpy(&hdcp->auth.msg.hdcp2.ake_init[0], &msg_out->prepare.transmitter_message[0],
++ sizeof(hdcp->auth.msg.hdcp2.ake_init));
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_ake_cert(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_CERT;
++ msg_in->process.msg1_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT;
++
++ memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.ake_cert,
++ sizeof(hdcp->auth.msg.hdcp2.ake_cert));
++
++ msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__AKE_NO_STORED_KM;
++ msg_in->prepare.msg2_id = TA_HDCP_HDCP2_MSG_ID__AKE_STORED_KM;
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE;
++
++ memcpy(hdcp->auth.msg.hdcp2.ake_no_stored_km, &msg_out->prepare.transmitter_message[0],
++ sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km));
++
++ memcpy(hdcp->auth.msg.hdcp2.ake_stored_km,
++ &msg_out->prepare.transmitter_message[sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km)],
++ sizeof(hdcp->auth.msg.hdcp2.ake_stored_km));
++
++ if (msg_out->process.msg1_status == TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS) {
++ hdcp->connection.is_km_stored = msg_out->process.is_km_stored ? 1 : 0;
++ hdcp->connection.is_repeater = msg_out->process.is_repeater ? 1 : 0;
++ return MOD_HDCP_STATUS_SUCCESS;
++ }
++
++ return MOD_HDCP_STATUS_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_h_prime(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_H_PRIME;
++ msg_in->process.msg1_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_H_PRIME;
++
++ memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.ake_h_prime,
++ sizeof(hdcp->auth.msg.hdcp2.ake_h_prime));
++
++ if (!hdcp->connection.is_km_stored) {
++ msg_in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_PAIRING_INFO;
++ msg_in->process.msg2_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_PAIRING_INFO;
++ memcpy(&msg_in->process.receiver_message[sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)],
++ hdcp->auth.msg.hdcp2.ake_pairing_info, sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info));
++ }
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE;
++
++ if (msg_out->process.msg1_status != TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE;
++ else if (!hdcp->connection.is_km_stored &&
++ msg_out->process.msg2_status != TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE;
++
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_lc_init(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__LC_INIT;
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE;
++
++ memcpy(hdcp->auth.msg.hdcp2.lc_init, &msg_out->prepare.transmitter_message[0],
++ sizeof(hdcp->auth.msg.hdcp2.lc_init));
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_l_prime(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__LC_SEND_L_PRIME;
++ msg_in->process.msg1_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_SEND_L_PRIME;
++
++ memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.lc_l_prime,
++ sizeof(hdcp->auth.msg.hdcp2.lc_l_prime));
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE;
++
++ if (msg_out->process.msg1_status != TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE;
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_eks(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__SKE_SEND_EKS;
++
++ if (is_dp_hdcp(hdcp))
++ msg_in->prepare.msg2_id = TA_HDCP_HDCP2_MSG_ID__SIGNAL_CONTENT_STREAM_TYPE_DP;
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE;
++
++ memcpy(hdcp->auth.msg.hdcp2.ske_eks, &msg_out->prepare.transmitter_message[0],
++ sizeof(hdcp->auth.msg.hdcp2.ske_eks));
++ msg_out->prepare.msg1_desc.msg_size = sizeof(hdcp->auth.msg.hdcp2.ske_eks);
++
++ if (is_dp_hdcp(hdcp)) {
++ memcpy(hdcp->auth.msg.hdcp2.content_stream_type_dp,
++ &msg_out->prepare.transmitter_message[sizeof(hdcp->auth.msg.hdcp2.ske_eks)],
++ sizeof(hdcp->auth.msg.hdcp2.content_stream_type_dp));
++ }
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++ struct mod_hdcp_display *display = get_first_added_display(hdcp);
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ if (!display)
++ return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
++
++ hdcp_cmd->in_msg.hdcp1_enable_encryption.session_handle = hdcp->auth.id;
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_SET_ENCRYPTION;
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE;
++
++ if (!is_dp_mst_hdcp(hdcp)) {
++ display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++ }
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_rx_id_list(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_RECEIVERID_LIST;
++ msg_in->process.msg1_desc.msg_size = sizeof(hdcp->auth.msg.hdcp2.rx_id_list);
++ memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.rx_id_list,
++ sizeof(hdcp->auth.msg.hdcp2.rx_id_list));
++
++ msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_ACK;
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE;
++
++ memcpy(hdcp->auth.msg.hdcp2.repeater_auth_ack, &msg_out->prepare.transmitter_message[0],
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack));
++
++ if (msg_out->process.msg1_status == TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS) {
++ hdcp->connection.is_km_stored = msg_out->process.is_km_stored ? 1 : 0;
++ hdcp->connection.is_repeater = msg_out->process.is_repeater ? 1 : 0;
++ return MOD_HDCP_STATUS_SUCCESS;
++ }
++
++
++ return MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++ uint8_t i;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++
++ for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++ if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED ||
++ hdcp->connection.displays[i].adjust.disable)
++ continue;
++ hdcp_cmd->in_msg.hdcp2_enable_dp_stream_encryption.display_handle = hdcp->connection.displays[i].index;
++ hdcp_cmd->in_msg.hdcp2_enable_dp_stream_encryption.session_handle = hdcp->auth.id;
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_ENABLE_DP_STREAM_ENCRYPTION;
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ break;
++
++ hdcp->connection.displays[i].state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++ }
++
++ return (hdcp_cmd->hdcp_status == TA_HDCP_STATUS__SUCCESS) ? MOD_HDCP_STATUS_SUCCESS
++ : MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_stream_management(struct mod_hdcp *hdcp)
++{
++
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_MANAGE;
++
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE;
++
++ hdcp->auth.msg.hdcp2.stream_manage_size = msg_out->prepare.msg1_desc.msg_size;
++
++ memcpy(hdcp->auth.msg.hdcp2.repeater_auth_stream_manage, &msg_out->prepare.transmitter_message[0],
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_manage));
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_stream_ready(struct mod_hdcp *hdcp)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++ msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++ hdcp2_message_init(hdcp, msg_in);
++
++ msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_READY;
++
++ msg_in->process.msg1_desc.msg_size = sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready);
++
++ memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.repeater_auth_stream_ready,
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready));
++
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ return (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS) &&
++ (msg_out->process.msg1_status == TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++ ? MOD_HDCP_STATUS_SUCCESS
++ : MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_get_link_encryption_status(struct mod_hdcp *hdcp,
++ enum mod_hdcp_encryption_status *encryption_status)
++{
++ struct psp_context *psp = hdcp->config.psp.handle;
++ struct ta_hdcp_shared_memory *hdcp_cmd;
++
++ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++
++ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++ hdcp_cmd->in_msg.hdcp2_get_encryption_status.session_handle = hdcp->auth.id;
++ hdcp_cmd->out_msg.hdcp2_get_encryption_status.protection_level = 0;
++ hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_GET_ENCRYPTION_STATUS;
++ *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++
++ psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++ return MOD_HDCP_STATUS_FAILURE;
++
++ if (hdcp_cmd->out_msg.hdcp2_get_encryption_status.protection_level == 1) {
++ if (hdcp_cmd->out_msg.hdcp2_get_encryption_status.hdcp2_type == TA_HDCP2_CONTENT_TYPE__TYPE1)
++ *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON;
++ else
++ *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON;
++ }
++
++ return MOD_HDCP_STATUS_SUCCESS;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+index 986fc07ea9ea..82a5e997d573 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+@@ -36,6 +36,11 @@ enum bgd_security_hdcp_encryption_level {
+ HDCP_ENCRYPTION_LEVEL__ON
+ };
+
++enum bgd_security_hdcp2_content_type {
++ HDCP2_CONTENT_TYPE__INVALID = 0,
++ HDCP2_CONTENT_TYPE__TYPE0,
++ HDCP2_CONTENT_TYPE__TYPE1
++};
+ enum ta_dtm_command {
+ TA_DTM_COMMAND__UNUSED_1 = 1,
+ TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2,
+@@ -121,8 +126,64 @@ enum ta_hdcp_command {
+ TA_HDCP_COMMAND__HDCP1_ENABLE_ENCRYPTION,
+ TA_HDCP_COMMAND__HDCP1_ENABLE_DP_STREAM_ENCRYPTION,
+ TA_HDCP_COMMAND__HDCP1_GET_ENCRYPTION_STATUS,
++ TA_HDCP_COMMAND__UNUSED_1,
++ TA_HDCP_COMMAND__HDCP2_DESTROY_SESSION,
++ TA_HDCP_COMMAND__UNUSED_2,
++ TA_HDCP_COMMAND__HDCP2_SET_ENCRYPTION,
++ TA_HDCP_COMMAND__HDCP2_GET_ENCRYPTION_STATUS,
++ TA_HDCP_COMMAND__UNUSED_3,
++ TA_HDCP_COMMAND__HDCP2_CREATE_SESSION_V2,
++ TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2,
++ TA_HDCP_COMMAND__HDCP2_ENABLE_DP_STREAM_ENCRYPTION
++};
++
++enum ta_hdcp2_msg_id {
++ TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE = 1,
++ TA_HDCP_HDCP2_MSG_ID__AKE_INIT = 2,
++ TA_HDCP_HDCP2_MSG_ID__AKE_SEND_CERT = 3,
++ TA_HDCP_HDCP2_MSG_ID__AKE_NO_STORED_KM = 4,
++ TA_HDCP_HDCP2_MSG_ID__AKE_STORED_KM = 5,
++ TA_HDCP_HDCP2_MSG_ID__AKE_SEND_RRX = 6,
++ TA_HDCP_HDCP2_MSG_ID__AKE_SEND_H_PRIME = 7,
++ TA_HDCP_HDCP2_MSG_ID__AKE_SEND_PAIRING_INFO = 8,
++ TA_HDCP_HDCP2_MSG_ID__LC_INIT = 9,
++ TA_HDCP_HDCP2_MSG_ID__LC_SEND_L_PRIME = 10,
++ TA_HDCP_HDCP2_MSG_ID__SKE_SEND_EKS = 11,
++ TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_RECEIVERID_LIST = 12,
++ TA_HDCP_HDCP2_MSG_ID__RTT_READY = 13,
++ TA_HDCP_HDCP2_MSG_ID__RTT_CHALLENGE = 14,
++ TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_ACK = 15,
++ TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_MANAGE = 16,
++ TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_READY = 17,
++ TA_HDCP_HDCP2_MSG_ID__RECEIVER_AUTH_STATUS = 18,
++ TA_HDCP_HDCP2_MSG_ID__AKE_TRANSMITTER_INFO = 19,
++ TA_HDCP_HDCP2_MSG_ID__AKE_RECEIVER_INFO = 20,
++ TA_HDCP_HDCP2_MSG_ID__SIGNAL_CONTENT_STREAM_TYPE_DP = 129
+ };
+
++enum ta_hdcp2_hdcp2_msg_id_max_size {
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__NULL_MESSAGE = 0,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_INIT = 12,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT = 534,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_NO_STORED_KM = 129,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_STORED_KM = 33,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_RRX = 9,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_H_PRIME = 33,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_PAIRING_INFO = 17,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_INIT = 9,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_SEND_L_PRIME = 33,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__SKE_SEND_EKS = 25,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_SEND_RECEIVERID_LIST = 181,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RTT_READY = 1,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RTT_CHALLENGE = 17,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_SEND_RACK = 17,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_STREAM_MANAGE = 13,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_STREAM_READY = 33,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RECEIVER_AUTH_STATUS = 4,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_TRANSMITTER_INFO = 6,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_RECEIVER_INFO = 6,
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__SIGNAL_CONTENT_STREAM_TYPE_DP = 1
++};
+
+ /* HDCP related enumerations */
+ /**********************************************************/
+@@ -131,6 +192,12 @@ enum ta_hdcp_command {
+ #define TA_HDCP__HDCP1_KSV_SIZE 5
+ #define TA_HDCP__HDCP1_KSV_LIST_MAX_ENTRIES 127
+ #define TA_HDCP__HDCP1_V_PRIME_SIZE 20
++#define TA_HDCP__HDCP2_TX_BUF_MAX_SIZE \
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_NO_STORED_KM + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_STORED_KM + 6
++
++// 64 bits boundaries
++#define TA_HDCP__HDCP2_RX_BUF_MAX_SIZE \
++ TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_RECEIVER_INFO + 4
+
+ enum ta_hdcp_status {
+ TA_HDCP_STATUS__SUCCESS = 0x00,
+@@ -165,9 +232,47 @@ enum ta_hdcp_authentication_status {
+ TA_HDCP_AUTHENTICATION_STATUS__HDCP1_FIRST_PART_COMPLETE = 0x02,
+ TA_HDCP_AUTHENTICATION_STATUS__HDCP1_SECOND_PART_FAILED = 0x03,
+ TA_HDCP_AUTHENTICATION_STATUS__HDCP1_AUTHENTICATED = 0x04,
++ TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATION_PENDING = 0x06,
++ TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATION_FAILED = 0x07,
++ TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATED = 0x08,
+ TA_HDCP_AUTHENTICATION_STATUS__HDCP1_KSV_VALIDATION_FAILED = 0x09
+ };
+
++enum ta_hdcp2_msg_authentication_status {
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS = 0,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__KM_NOT_AVAILABLE,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__UNUSED,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID = 100, // everything above does not fail the request
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__NOT_ENOUGH_MEMORY,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__NOT_EXPECTED_MSG,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__SIGNATURE_CERTIFICAT_ERROR,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__INCORRECT_HDCP_VERSION,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__UNKNOWN_MESSAGE,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_HMAC,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_TOPOLOGY,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_SEQ_NUM,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_SIZE,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_LENGTH,
++ TA_HDCP2_MSG_AUTHENTICATION_STATUS__REAUTH_REQUEST
++};
++
++enum ta_hdcp_content_type {
++ TA_HDCP2_CONTENT_TYPE__TYPE0 = 1,
++ TA_HDCP2_CONTENT_TYPE__TYPE1,
++};
++
++enum ta_hdcp_content_type_negotiation_type {
++ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE0 = 1,
++ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE1,
++ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__MAX_SUPPORTED
++};
++
++enum ta_hdcp2_version {
++ TA_HDCP2_VERSION_UNKNOWN = 0,
++ TA_HDCP2_VERSION_2_0 = 20,
++ TA_HDCP2_VERSION_2_1 = 21,
++ TA_HDCP2_VERSION_2_2 = 22
++};
+
+ /* input/output structures for HDCP commands */
+ /**********************************************************/
+@@ -232,6 +337,84 @@ struct ta_hdcp_cmd_hdcp1_get_encryption_status_output {
+ uint32_t protection_level;
+ };
+
++struct ta_hdcp_cmd_hdcp2_create_session_input_v2 {
++ uint32_t display_handle;
++ enum ta_hdcp_content_type_negotiation_type negotiate_content_type;
++};
++
++struct ta_hdcp_cmd_hdcp2_create_session_output_v2 {
++ uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_destroy_session_input {
++ uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_authentication_message_v2 {
++ enum ta_hdcp2_msg_id msg_id;
++ uint32_t msg_size;
++};
++
++struct ta_hdcp_cmd_hdcp2_process_authentication_message_input_v2 {
++ struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg1_desc;
++ struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg2_desc;
++ struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg3_desc;
++ uint8_t receiver_message[TA_HDCP__HDCP2_RX_BUF_MAX_SIZE];
++};
++
++struct ta_hdcp_cmd_hdcp2_process_authentication_message_output_v2 {
++ uint32_t hdcp_version;
++ uint32_t is_km_stored;
++ uint32_t is_locality_precompute_support;
++ uint32_t is_repeater;
++ enum ta_hdcp2_msg_authentication_status msg1_status;
++ enum ta_hdcp2_msg_authentication_status msg2_status;
++ enum ta_hdcp2_msg_authentication_status msg3_status;
++};
++
++struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_input_v2 {
++ enum ta_hdcp2_msg_id msg1_id;
++ enum ta_hdcp2_msg_id msg2_id;
++};
++
++struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_output_v2 {
++ enum ta_hdcp2_msg_authentication_status msg1_status;
++ enum ta_hdcp2_msg_authentication_status msg2_status;
++ struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg1_desc;
++ struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg2_desc;
++ uint8_t transmitter_message[TA_HDCP__HDCP2_TX_BUF_MAX_SIZE];
++};
++
++struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 {
++ uint32_t session_handle;
++ struct ta_hdcp_cmd_hdcp2_process_authentication_message_input_v2 process;
++ struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_input_v2 prepare;
++};
++
++struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 {
++ uint32_t authentication_status;
++ struct ta_hdcp_cmd_hdcp2_process_authentication_message_output_v2 process;
++ struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_output_v2 prepare;
++};
++
++struct ta_hdcp_cmd_hdcp2_set_encryption_input {
++ uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_get_encryption_status_input {
++ uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_get_encryption_status_output {
++ enum ta_hdcp_content_type hdcp2_type;
++ uint32_t protection_level;
++};
++
++struct ta_hdcp_cmd_hdcp2_enable_dp_stream_encryption_input {
++ uint32_t session_handle;
++ uint32_t display_handle;
++};
++
+ /**********************************************************/
+ /* Common input structure for HDCP callbacks */
+ union ta_hdcp_cmd_input {
+@@ -242,6 +425,13 @@ union ta_hdcp_cmd_input {
+ struct ta_hdcp_cmd_hdcp1_enable_encryption_input hdcp1_enable_encryption;
+ struct ta_hdcp_cmd_hdcp1_enable_dp_stream_encryption_input hdcp1_enable_dp_stream_encryption;
+ struct ta_hdcp_cmd_hdcp1_get_encryption_status_input hdcp1_get_encryption_status;
++ struct ta_hdcp_cmd_hdcp2_destroy_session_input hdcp2_destroy_session;
++ struct ta_hdcp_cmd_hdcp2_set_encryption_input hdcp2_set_encryption;
++ struct ta_hdcp_cmd_hdcp2_get_encryption_status_input hdcp2_get_encryption_status;
++ struct ta_hdcp_cmd_hdcp2_create_session_input_v2 hdcp2_create_session_v2;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2
++ hdcp2_prepare_process_authentication_message_v2;
++ struct ta_hdcp_cmd_hdcp2_enable_dp_stream_encryption_input hdcp2_enable_dp_stream_encryption;
+ };
+
+ /* Common output structure for HDCP callbacks */
+@@ -250,6 +440,10 @@ union ta_hdcp_cmd_output {
+ struct ta_hdcp_cmd_hdcp1_first_part_authentication_output hdcp1_first_part_authentication;
+ struct ta_hdcp_cmd_hdcp1_second_part_authentication_output hdcp1_second_part_authentication;
+ struct ta_hdcp_cmd_hdcp1_get_encryption_status_output hdcp1_get_encryption_status;
++ struct ta_hdcp_cmd_hdcp2_get_encryption_status_output hdcp2_get_encryption_status;
++ struct ta_hdcp_cmd_hdcp2_create_session_output_v2 hdcp2_create_session_v2;
++ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2
++ hdcp2_prepare_process_authentication_message_v2;
+ };
+ /**********************************************************/
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4501-drm-amd-display-Add-DDC-handles-for-HDCP2.2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4501-drm-amd-display-Add-DDC-handles-for-HDCP2.2.patch
new file mode 100644
index 00000000..2c223e04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4501-drm-amd-display-Add-DDC-handles-for-HDCP2.2.patch
@@ -0,0 +1,377 @@
+From 4ea723ead2666d8b4634197039488c9b5fcb4fa5 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:23:07 -0400
+Subject: [PATCH 4501/4736] drm/amd/display: Add DDC handles for HDCP2.2
+
+[Why]
+We need these to read and write to aux/i2c, during
+authentication
+
+[How]
+Create read/write functions for all the steps
+(Eg, h_prime, paring_info etc)
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/modules/hdcp/hdcp_ddc.c | 326 ++++++++++++++++++
+ 1 file changed, 326 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+index e7baae059b85..8059aff9911f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+@@ -51,6 +51,26 @@ enum mod_hdcp_ddc_message_id {
+ MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO,
+ MOD_HDCP_MESSAGE_ID_READ_BINFO,
+
++ /* HDCP 2.2 */
++
++ MOD_HDCP_MESSAGE_ID_HDCP2VERSION,
++ MOD_HDCP_MESSAGE_ID_RX_CAPS,
++ MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT,
++ MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
++ MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
++ MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
++ MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
++ MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
++ MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT,
++ MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
++ MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
++ MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
++ MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
++ MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
++ MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
++ MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
++ MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
++
+ MOD_HDCP_MESSAGE_ID_MAX
+ };
+
+@@ -70,6 +90,22 @@ static const uint8_t hdcp_i2c_offsets[] = {
+ [MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x41,
+ [MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x43,
+ [MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0xFF,
++ [MOD_HDCP_MESSAGE_ID_HDCP2VERSION] = 0x50,
++ [MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x60,
++ [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x80,
++ [MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x60,
++ [MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x60,
++ [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x80,
++ [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x80,
++ [MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x60,
++ [MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x80,
++ [MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x60,
++ [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x80,
++ [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60,
++ [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60,
++ [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80,
++ [MOD_HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70,
++ [MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x0
+ };
+
+ static const uint32_t hdcp_dpcd_addrs[] = {
+@@ -88,6 +124,22 @@ static const uint32_t hdcp_dpcd_addrs[] = {
+ [MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x68029,
+ [MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x6802c,
+ [MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0x6802a,
++ [MOD_HDCP_MESSAGE_ID_RX_CAPS] = 0x6921d,
++ [MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x69000,
++ [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x6900b,
++ [MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x69220,
++ [MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x692a0,
++ [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x692c0,
++ [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x692e0,
++ [MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x692f0,
++ [MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x692f8,
++ [MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x69318,
++ [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x69330,
++ [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x693e0,
++ [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x693f0,
++ [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x69473,
++ [MOD_HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x69493,
++ [MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x69494
+ };
+
+ static enum mod_hdcp_status read(struct mod_hdcp *hdcp,
+@@ -303,3 +355,277 @@ enum mod_hdcp_status mod_hdcp_write_an(struct mod_hdcp *hdcp)
+ hdcp->auth.msg.hdcp1.an,
+ sizeof(hdcp->auth.msg.hdcp1.an));
+ }
++
++enum mod_hdcp_status mod_hdcp_read_hdcp2version(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = MOD_HDCP_STATUS_INVALID_OPERATION;
++ else
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_HDCP2VERSION,
++ &hdcp->auth.msg.hdcp2.hdcp2version_hdmi,
++ sizeof(hdcp->auth.msg.hdcp2.hdcp2version_hdmi));
++
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_rxcaps(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (!is_dp_hdcp(hdcp))
++ status = MOD_HDCP_STATUS_INVALID_OPERATION;
++ else
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_RX_CAPS,
++ hdcp->auth.msg.hdcp2.rxcaps_dp,
++ sizeof(hdcp->auth.msg.hdcp2.rxcaps_dp));
++
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_rxstatus(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp)) {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
++ (uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,
++ 1);
++ } else {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
++ (uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,
++ sizeof(hdcp->auth.msg.hdcp2.rxstatus));
++ }
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_ake_cert(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp)) {
++ hdcp->auth.msg.hdcp2.ake_cert[0] = 3;
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
++ hdcp->auth.msg.hdcp2.ake_cert+1,
++ sizeof(hdcp->auth.msg.hdcp2.ake_cert)-1);
++
++ } else {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
++ hdcp->auth.msg.hdcp2.ake_cert,
++ sizeof(hdcp->auth.msg.hdcp2.ake_cert));
++ }
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_h_prime(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp)) {
++ hdcp->auth.msg.hdcp2.ake_h_prime[0] = 7;
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
++ hdcp->auth.msg.hdcp2.ake_h_prime+1,
++ sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)-1);
++
++ } else {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
++ hdcp->auth.msg.hdcp2.ake_h_prime,
++ sizeof(hdcp->auth.msg.hdcp2.ake_h_prime));
++ }
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_pairing_info(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp)) {
++ hdcp->auth.msg.hdcp2.ake_pairing_info[0] = 8;
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
++ hdcp->auth.msg.hdcp2.ake_pairing_info+1,
++ sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)-1);
++
++ } else {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
++ hdcp->auth.msg.hdcp2.ake_pairing_info,
++ sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info));
++ }
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_l_prime(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp)) {
++ hdcp->auth.msg.hdcp2.lc_l_prime[0] = 10;
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
++ hdcp->auth.msg.hdcp2.lc_l_prime+1,
++ sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)-1);
++
++ } else {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
++ hdcp->auth.msg.hdcp2.lc_l_prime,
++ sizeof(hdcp->auth.msg.hdcp2.lc_l_prime));
++ }
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_rx_id_list(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp)) {
++ hdcp->auth.msg.hdcp2.rx_id_list[0] = 12;
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
++ hdcp->auth.msg.hdcp2.rx_id_list+1,
++ sizeof(hdcp->auth.msg.hdcp2.rx_id_list)-1);
++
++ } else {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
++ hdcp->auth.msg.hdcp2.rx_id_list,
++ hdcp->auth.msg.hdcp2.rx_id_list_size);
++ }
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_stream_ready(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp)) {
++ hdcp->auth.msg.hdcp2.repeater_auth_stream_ready[0] = 17;
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
++ hdcp->auth.msg.hdcp2.repeater_auth_stream_ready+1,
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)-1);
++
++ } else {
++ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
++ hdcp->auth.msg.hdcp2.repeater_auth_stream_ready,
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready));
++ }
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_ake_init(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT,
++ hdcp->auth.msg.hdcp2.ake_init+1,
++ sizeof(hdcp->auth.msg.hdcp2.ake_init)-1);
++ else
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT,
++ hdcp->auth.msg.hdcp2.ake_init,
++ sizeof(hdcp->auth.msg.hdcp2.ake_init));
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_no_stored_km(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
++ hdcp->auth.msg.hdcp2.ake_no_stored_km+1,
++ sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km)-1);
++ else
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
++ hdcp->auth.msg.hdcp2.ake_no_stored_km,
++ sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km));
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_stored_km(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
++ hdcp->auth.msg.hdcp2.ake_stored_km+1,
++ sizeof(hdcp->auth.msg.hdcp2.ake_stored_km)-1);
++ else
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
++ hdcp->auth.msg.hdcp2.ake_stored_km,
++ sizeof(hdcp->auth.msg.hdcp2.ake_stored_km));
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_lc_init(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT,
++ hdcp->auth.msg.hdcp2.lc_init+1,
++ sizeof(hdcp->auth.msg.hdcp2.lc_init)-1);
++ else
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT,
++ hdcp->auth.msg.hdcp2.lc_init,
++ sizeof(hdcp->auth.msg.hdcp2.lc_init));
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_eks(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp,
++ MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
++ hdcp->auth.msg.hdcp2.ske_eks+1,
++ sizeof(hdcp->auth.msg.hdcp2.ske_eks)-1);
++ else
++ status = write(hdcp,
++ MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
++ hdcp->auth.msg.hdcp2.ske_eks,
++ sizeof(hdcp->auth.msg.hdcp2.ske_eks));
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_repeater_auth_ack(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
++ hdcp->auth.msg.hdcp2.repeater_auth_ack+1,
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack)-1);
++ else
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
++ hdcp->auth.msg.hdcp2.repeater_auth_ack,
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack));
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_stream_manage(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp,
++ MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
++ hdcp->auth.msg.hdcp2.repeater_auth_stream_manage+1,
++ hdcp->auth.msg.hdcp2.stream_manage_size-1);
++ else
++ status = write(hdcp,
++ MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
++ hdcp->auth.msg.hdcp2.repeater_auth_stream_manage,
++ hdcp->auth.msg.hdcp2.stream_manage_size);
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_content_type(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
++ hdcp->auth.msg.hdcp2.content_stream_type_dp+1,
++ sizeof(hdcp->auth.msg.hdcp2.content_stream_type_dp)-1);
++ else
++ status = MOD_HDCP_STATUS_INVALID_OPERATION;
++ return status;
++}
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4502-drm-amd-display-Add-execution-and-transition-states-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4502-drm-amd-display-Add-execution-and-transition-states-.patch
new file mode 100644
index 00000000..66d7df04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4502-drm-amd-display-Add-execution-and-transition-states-.patch
@@ -0,0 +1,1992 @@
+From d3cc90c80f602b70998a55f10658fc714d481f96 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:18:15 -0400
+Subject: [PATCH 4502/4736] drm/amd/display: Add execution and transition
+ states for HDCP2.2
+
+The module works like a state machine
+
+ +-------------+
+ ------> | Execution.c | ------
+ | +-------------+ |
+ | V
+ +----+ +--------+ +--------------+
+ | DM | -----> | Hdcp.c | <------------ | Transition.c |
+ +----+ <----- +--------+ +--------------+
+
+This patch adds the execution and transition files for 2.2
+
+Extension to "40a702d427 drm/amd/display: Add HDCP module" for 2.2
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/Makefile | 3 +-
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 86 +-
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 127 +++
+ .../display/modules/hdcp/hdcp2_execution.c | 881 ++++++++++++++++++
+ .../display/modules/hdcp/hdcp2_transition.c | 674 ++++++++++++++
+ .../drm/amd/display/modules/inc/mod_hdcp.h | 2 +
+ 6 files changed, 1764 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/Makefile b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+index 1c3c6d47973a..904424da01b5 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+@@ -24,7 +24,8 @@
+ #
+
+ HDCP = hdcp_ddc.o hdcp_log.o hdcp_psp.o hdcp.o \
+- hdcp1_execution.o hdcp1_transition.o
++ hdcp1_execution.o hdcp1_transition.o \
++ hdcp2_execution.o hdcp2_transition.o
+
+ AMD_DAL_HDCP = $(addprefix $(AMDDALPATH)/modules/hdcp/,$(HDCP))
+ #$(info ************ DAL-HDCP_MAKEFILE ************)
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index d7ac445dec6f..a74812977963 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -37,24 +37,52 @@ static void push_error_status(struct mod_hdcp *hdcp,
+ HDCP_ERROR_TRACE(hdcp, status);
+ }
+
+- hdcp->connection.hdcp1_retry_count++;
++ if (is_hdcp1(hdcp)) {
++ hdcp->connection.hdcp1_retry_count++;
++ } else if (is_hdcp2(hdcp)) {
++ hdcp->connection.hdcp2_retry_count++;
++ }
+ }
+
+ static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)
+ {
+- int i, display_enabled = 0;
++ int i, is_auth_needed = 0;
+
+- /* if all displays on the link are disabled, hdcp is not desired */
++ /* if all displays on the link don't need authentication,
++ * hdcp is not desired
++ */
+ for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
+ if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_INACTIVE &&
+ !hdcp->connection.displays[i].adjust.disable) {
+- display_enabled = 1;
++ is_auth_needed = 1;
+ break;
+ }
+ }
+
+ return (hdcp->connection.hdcp1_retry_count < MAX_NUM_OF_ATTEMPTS) &&
+- display_enabled && !hdcp->connection.link.adjust.hdcp1.disable;
++ is_auth_needed &&
++ !hdcp->connection.link.adjust.hdcp1.disable;
++}
++
++static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)
++{
++ int i, is_auth_needed = 0;
++
++ /* if all displays on the link don't need authentication,
++ * hdcp is not desired
++ */
++ for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++ if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_INACTIVE &&
++ !hdcp->connection.displays[i].adjust.disable) {
++ is_auth_needed = 1;
++ break;
++ }
++ }
++
++ return (hdcp->connection.hdcp2_retry_count < MAX_NUM_OF_ATTEMPTS) &&
++ is_auth_needed &&
++ !hdcp->connection.link.adjust.hdcp2.disable &&
++ !hdcp->connection.is_hdcp2_revoked;
+ }
+
+ static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
+@@ -82,6 +110,11 @@ static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
+ } else if (is_in_hdcp1_dp_states(hdcp)) {
+ status = mod_hdcp_hdcp1_dp_execution(hdcp,
+ event_ctx, &input->hdcp1);
++ } else if (is_in_hdcp2_states(hdcp)) {
++ status = mod_hdcp_hdcp2_execution(hdcp, event_ctx, &input->hdcp2);
++ } else if (is_in_hdcp2_dp_states(hdcp)) {
++ status = mod_hdcp_hdcp2_dp_execution(hdcp,
++ event_ctx, &input->hdcp2);
+ }
+ out:
+ return status;
+@@ -99,7 +132,10 @@ static enum mod_hdcp_status transition(struct mod_hdcp *hdcp,
+
+ if (is_in_initialized_state(hdcp)) {
+ if (is_dp_hdcp(hdcp))
+- if (is_cp_desired_hdcp1(hdcp)) {
++ if (is_cp_desired_hdcp2(hdcp)) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A0_DETERMINE_RX_HDCP_CAPABLE);
++ } else if (is_cp_desired_hdcp1(hdcp)) {
+ callback_in_ms(0, output);
+ set_state_id(hdcp, output, D1_A0_DETERMINE_RX_HDCP_CAPABLE);
+ } else {
+@@ -107,7 +143,10 @@ static enum mod_hdcp_status transition(struct mod_hdcp *hdcp,
+ set_state_id(hdcp, output, HDCP_CP_NOT_DESIRED);
+ }
+ else if (is_hdmi_dvi_sl_hdcp(hdcp))
+- if (is_cp_desired_hdcp1(hdcp)) {
++ if (is_cp_desired_hdcp2(hdcp)) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A0_KNOWN_HDCP2_CAPABLE_RX);
++ } else if (is_cp_desired_hdcp1(hdcp)) {
+ callback_in_ms(0, output);
+ set_state_id(hdcp, output, H1_A0_WAIT_FOR_ACTIVE_RX);
+ } else {
+@@ -126,6 +165,12 @@ static enum mod_hdcp_status transition(struct mod_hdcp *hdcp,
+ } else if (is_in_hdcp1_dp_states(hdcp)) {
+ status = mod_hdcp_hdcp1_dp_transition(hdcp,
+ event_ctx, &input->hdcp1, output);
++ } else if (is_in_hdcp2_states(hdcp)) {
++ status = mod_hdcp_hdcp2_transition(hdcp,
++ event_ctx, &input->hdcp2, output);
++ } else if (is_in_hdcp2_dp_states(hdcp)) {
++ status = mod_hdcp_hdcp2_dp_transition(hdcp,
++ event_ctx, &input->hdcp2, output);
+ } else {
+ status = MOD_HDCP_STATUS_INVALID_STATE;
+ }
+@@ -139,9 +184,13 @@ static enum mod_hdcp_status reset_authentication(struct mod_hdcp *hdcp,
+ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
+ if (is_hdcp1(hdcp)) {
+- if (hdcp->auth.trans_input.hdcp1.create_session != UNKNOWN)
++ if (hdcp->auth.trans_input.hdcp1.create_session != UNKNOWN) {
++ /* TODO - update psp to unify create session failure
++ * recovery between hdcp1 and 2.
++ */
+ mod_hdcp_hdcp1_destroy_session(hdcp);
+
++ }
+ if (hdcp->auth.trans_input.hdcp1.add_topology == PASS) {
+ status = mod_hdcp_remove_display_topology(hdcp);
+ if (status != MOD_HDCP_STATUS_SUCCESS) {
+@@ -154,6 +203,27 @@ static enum mod_hdcp_status reset_authentication(struct mod_hdcp *hdcp,
+ memset(&hdcp->auth, 0, sizeof(struct mod_hdcp_authentication));
+ memset(&hdcp->state, 0, sizeof(struct mod_hdcp_state));
+ set_state_id(hdcp, output, HDCP_INITIALIZED);
++ } else if (is_hdcp2(hdcp)) {
++ if (hdcp->auth.trans_input.hdcp2.create_session == PASS) {
++ status = mod_hdcp_hdcp2_destroy_session(hdcp);
++ if (status != MOD_HDCP_STATUS_SUCCESS) {
++ output->callback_needed = 0;
++ output->watchdog_timer_needed = 0;
++ goto out;
++ }
++ }
++ if (hdcp->auth.trans_input.hdcp2.add_topology == PASS) {
++ status = mod_hdcp_remove_display_topology(hdcp);
++ if (status != MOD_HDCP_STATUS_SUCCESS) {
++ output->callback_needed = 0;
++ output->watchdog_timer_needed = 0;
++ goto out;
++ }
++ }
++ HDCP_TOP_RESET_AUTH_TRACE(hdcp);
++ memset(&hdcp->auth, 0, sizeof(struct mod_hdcp_authentication));
++ memset(&hdcp->state, 0, sizeof(struct mod_hdcp_state));
++ set_state_id(hdcp, output, HDCP_INITIALIZED);
+ } else if (is_in_cp_not_desired_state(hdcp)) {
+ status = mod_hdcp_remove_display_topology(hdcp);
+ if (status != MOD_HDCP_STATUS_SUCCESS) {
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index d83f0ab1cadb..9887c5ea6d5f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -44,11 +44,13 @@
+ #define BINFO_MAX_DEVS_EXCEEDED_MASK_DP 0x0080
+ #define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP 0x0800
+
++#define VERSION_HDCP2_MASK 0x04
+ #define RXSTATUS_MSG_SIZE_MASK 0x03FF
+ #define RXSTATUS_READY_MASK 0x0400
+ #define RXSTATUS_REAUTH_REQUEST_MASK 0x0800
+ #define RXIDLIST_DEVICE_COUNT_LOWER_MASK 0xf0
+ #define RXIDLIST_DEVICE_COUNT_UPPER_MASK 0x01
++#define RXCAPS_BYTE2_HDCP2_VERSION_DP 0x02
+ #define RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP 0x02
+ #define RXSTATUS_READY_MASK_DP 0x0001
+ #define RXSTATUS_H_P_AVAILABLE_MASK_DP 0x0002
+@@ -92,8 +94,52 @@ struct mod_hdcp_transition_input_hdcp1 {
+ uint8_t stream_encryption_dp;
+ };
+
++struct mod_hdcp_transition_input_hdcp2 {
++ uint8_t hdcp2version_read;
++ uint8_t hdcp2_capable_check;
++ uint8_t add_topology;
++ uint8_t create_session;
++ uint8_t ake_init_prepare;
++ uint8_t ake_init_write;
++ uint8_t rxstatus_read;
++ uint8_t ake_cert_available;
++ uint8_t ake_cert_read;
++ uint8_t ake_cert_validation;
++ uint8_t stored_km_write;
++ uint8_t no_stored_km_write;
++ uint8_t h_prime_available;
++ uint8_t h_prime_read;
++ uint8_t pairing_available;
++ uint8_t pairing_info_read;
++ uint8_t h_prime_validation;
++ uint8_t lc_init_prepare;
++ uint8_t lc_init_write;
++ uint8_t l_prime_available_poll;
++ uint8_t l_prime_read;
++ uint8_t l_prime_validation;
++ uint8_t eks_prepare;
++ uint8_t eks_write;
++ uint8_t enable_encryption;
++ uint8_t reauth_request_check;
++ uint8_t rx_id_list_read;
++ uint8_t device_count_check;
++ uint8_t rx_id_list_validation;
++ uint8_t repeater_auth_ack_write;
++ uint8_t prepare_stream_manage;
++ uint8_t stream_manage_write;
++ uint8_t stream_ready_available;
++ uint8_t stream_ready_read;
++ uint8_t stream_ready_validation;
++
++ uint8_t rx_caps_read_dp;
++ uint8_t content_stream_type_write;
++ uint8_t link_integrity_check_dp;
++ uint8_t stream_encryption_dp;
++};
++
+ union mod_hdcp_transition_input {
+ struct mod_hdcp_transition_input_hdcp1 hdcp1;
++ struct mod_hdcp_transition_input_hdcp2 hdcp2;
+ };
+
+ struct mod_hdcp_message_hdcp1 {
+@@ -150,8 +196,10 @@ struct mod_hdcp_connection {
+ struct mod_hdcp_display displays[MAX_NUM_OF_DISPLAYS];
+ uint8_t is_repeater;
+ uint8_t is_km_stored;
++ uint8_t is_hdcp2_revoked;
+ struct mod_hdcp_trace trace;
+ uint8_t hdcp1_retry_count;
++ uint8_t hdcp2_retry_count;
+ };
+
+ /* contains values per authentication cycle */
+@@ -219,6 +267,50 @@ enum mod_hdcp_hdcp1_dp_state_id {
+ HDCP1_DP_STATE_END = D1_A7_READ_KSV_LIST,
+ };
+
++enum mod_hdcp_hdcp2_state_id {
++ HDCP2_STATE_START = HDCP1_DP_STATE_END,
++ H2_A0_KNOWN_HDCP2_CAPABLE_RX,
++ H2_A1_SEND_AKE_INIT,
++ H2_A1_VALIDATE_AKE_CERT,
++ H2_A1_SEND_NO_STORED_KM,
++ H2_A1_READ_H_PRIME,
++ H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME,
++ H2_A1_SEND_STORED_KM,
++ H2_A1_VALIDATE_H_PRIME,
++ H2_A2_LOCALITY_CHECK,
++ H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER,
++ H2_ENABLE_ENCRYPTION,
++ H2_A5_AUTHENTICATED,
++ H2_A6_WAIT_FOR_RX_ID_LIST,
++ H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK,
++ H2_A9_SEND_STREAM_MANAGEMENT,
++ H2_A9_VALIDATE_STREAM_READY,
++ HDCP2_STATE_END = H2_A9_VALIDATE_STREAM_READY,
++};
++
++enum mod_hdcp_hdcp2_dp_state_id {
++ HDCP2_DP_STATE_START = HDCP2_STATE_END,
++ D2_A0_DETERMINE_RX_HDCP_CAPABLE,
++ D2_A1_SEND_AKE_INIT,
++ D2_A1_VALIDATE_AKE_CERT,
++ D2_A1_SEND_NO_STORED_KM,
++ D2_A1_READ_H_PRIME,
++ D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME,
++ D2_A1_SEND_STORED_KM,
++ D2_A1_VALIDATE_H_PRIME,
++ D2_A2_LOCALITY_CHECK,
++ D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER,
++ D2_SEND_CONTENT_STREAM_TYPE,
++ D2_ENABLE_ENCRYPTION,
++ D2_A5_AUTHENTICATED,
++ D2_A6_WAIT_FOR_RX_ID_LIST,
++ D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK,
++ D2_A9_SEND_STREAM_MANAGEMENT,
++ D2_A9_VALIDATE_STREAM_READY,
++ HDCP2_DP_STATE_END = D2_A9_VALIDATE_STREAM_READY,
++ HDCP_STATE_END = HDCP2_DP_STATE_END,
++};
++
+ /* hdcp1 executions and transitions */
+ typedef enum mod_hdcp_status (*mod_hdcp_action)(struct mod_hdcp *hdcp);
+ uint8_t mod_hdcp_execute_and_set(
+@@ -239,6 +331,22 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
+ struct mod_hdcp_transition_input_hdcp1 *input,
+ struct mod_hdcp_output *output);
+
++/* hdcp2 executions and transitions */
++enum mod_hdcp_status mod_hdcp_hdcp2_execution(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input);
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_execution(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input);
++enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input,
++ struct mod_hdcp_output *output);
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input,
++ struct mod_hdcp_output *output);
++
+ /* log functions */
+ void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,
+ uint8_t *buf, uint32_t buf_size);
+@@ -289,6 +397,7 @@ enum mod_hdcp_status mod_hdcp_read_binfo(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_write_aksv(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_write_ainfo(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_write_an(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_hdcp2version(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_rxcaps(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_rxstatus(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_ake_cert(struct mod_hdcp *hdcp);
+@@ -352,11 +461,28 @@ static inline uint8_t is_in_hdcp1_dp_states(struct mod_hdcp *hdcp)
+ current_state(hdcp) <= HDCP1_DP_STATE_END);
+ }
+
++static inline uint8_t is_in_hdcp2_states(struct mod_hdcp *hdcp)
++{
++ return (current_state(hdcp) > HDCP2_STATE_START &&
++ current_state(hdcp) <= HDCP2_STATE_END);
++}
++
++static inline uint8_t is_in_hdcp2_dp_states(struct mod_hdcp *hdcp)
++{
++ return (current_state(hdcp) > HDCP2_DP_STATE_START &&
++ current_state(hdcp) <= HDCP2_DP_STATE_END);
++}
++
+ static inline uint8_t is_hdcp1(struct mod_hdcp *hdcp)
+ {
+ return (is_in_hdcp1_states(hdcp) || is_in_hdcp1_dp_states(hdcp));
+ }
+
++static inline uint8_t is_hdcp2(struct mod_hdcp *hdcp)
++{
++ return (is_in_hdcp2_states(hdcp) || is_in_hdcp2_dp_states(hdcp));
++}
++
+ static inline uint8_t is_in_cp_not_desired_state(struct mod_hdcp *hdcp)
+ {
+ return current_state(hdcp) == HDCP_CP_NOT_DESIRED;
+@@ -481,6 +607,7 @@ static inline struct mod_hdcp_display *get_empty_display_container(
+ static inline void reset_retry_counts(struct mod_hdcp *hdcp)
+ {
+ hdcp->connection.hdcp1_retry_count = 0;
++ hdcp->connection.hdcp2_retry_count = 0;
+ }
+
+ #endif /* HDCP_H_ */
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+new file mode 100644
+index 000000000000..c93c8098d972
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+@@ -0,0 +1,881 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp *hdcp)
++{
++ uint8_t is_ready = 0;
++
++ if (is_dp_hdcp(hdcp))
++ is_ready = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK_DP) ? 1 : 0;
++ else
++ is_ready = ((hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK) &&
++ (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK)) ? 1 : 0;
++ return is_ready ? MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY;
++}
++
++static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++
++ if (is_dp_hdcp(hdcp))
++ status = ((hdcp->auth.msg.hdcp2.rxcaps_dp[2] &
++ RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP) &&
++ (hdcp->auth.msg.hdcp2.rxcaps_dp[0] ==
++ RXCAPS_BYTE2_HDCP2_VERSION_DP)) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
++ else
++ status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi & VERSION_HDCP2_MASK) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
++ return status;
++}
++
++static inline enum mod_hdcp_status check_reauthentication_request(
++ struct mod_hdcp *hdcp)
++{
++ uint8_t ret = 0;
++
++ if (is_dp_hdcp(hdcp))
++ ret = (hdcp->auth.msg.hdcp2.rxstatus &
++ RXSTATUS_REAUTH_REQUEST_MASK_DP) ?
++ MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
++ MOD_HDCP_STATUS_SUCCESS;
++ else
++ ret = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_REAUTH_REQUEST_MASK) ?
++ MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
++ MOD_HDCP_STATUS_SUCCESS;
++ return ret;
++}
++
++static inline enum mod_hdcp_status check_link_integrity_failure_dp(
++ struct mod_hdcp *hdcp)
++{
++ return (hdcp->auth.msg.hdcp2.rxstatus &
++ RXSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP) ?
++ MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE :
++ MOD_HDCP_STATUS_SUCCESS;
++}
++
++static enum mod_hdcp_status check_ake_cert_available(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++ uint16_t size;
++
++ if (is_dp_hdcp(hdcp)) {
++ status = MOD_HDCP_STATUS_SUCCESS;
++ } else {
++ status = mod_hdcp_read_rxstatus(hdcp);
++ if (status == MOD_HDCP_STATUS_SUCCESS) {
++ size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_cert)) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING;
++ }
++ }
++ return status;
++}
++
++static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++ uint8_t size;
++
++ status = mod_hdcp_read_rxstatus(hdcp);
++ if (status != MOD_HDCP_STATUS_SUCCESS)
++ goto out;
++
++ if (is_dp_hdcp(hdcp)) {
++ status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_H_P_AVAILABLE_MASK_DP) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
++ } else {
++ size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
++ }
++out:
++ return status;
++}
++
++static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++ uint8_t size;
++
++ status = mod_hdcp_read_rxstatus(hdcp);
++ if (status != MOD_HDCP_STATUS_SUCCESS)
++ goto out;
++
++ if (is_dp_hdcp(hdcp)) {
++ status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_PAIRING_AVAILABLE_MASK_DP) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
++ } else {
++ size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
++ }
++out:
++ return status;
++}
++
++static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++ uint8_t size;
++ uint16_t max_wait = 20000; // units of us
++ uint16_t num_polls = 5;
++ uint16_t wait_time = max_wait / num_polls;
++
++ if (is_dp_hdcp(hdcp))
++ status = MOD_HDCP_STATUS_INVALID_OPERATION;
++ else
++ for (; num_polls; num_polls--) {
++ udelay(wait_time);
++
++ status = mod_hdcp_read_rxstatus(hdcp);
++ if (status != MOD_HDCP_STATUS_SUCCESS)
++ break;
++
++ size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ status = (size == sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING;
++ if (status == MOD_HDCP_STATUS_SUCCESS)
++ break;
++ }
++ return status;
++}
++
++static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)
++{
++ enum mod_hdcp_status status;
++ uint8_t size;
++
++ if (is_dp_hdcp(hdcp)) {
++ status = MOD_HDCP_STATUS_INVALID_OPERATION;
++ } else {
++ status = mod_hdcp_read_rxstatus(hdcp);
++ if (status != MOD_HDCP_STATUS_SUCCESS)
++ goto out;
++ size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ status = (size == sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)) ?
++ MOD_HDCP_STATUS_SUCCESS :
++ MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING;
++ }
++out:
++ return status;
++}
++
++static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
++{
++ return ((hdcp->auth.msg.hdcp2.rx_id_list[2] & RXIDLIST_DEVICE_COUNT_LOWER_MASK) >> 4) +
++ ((hdcp->auth.msg.hdcp2.rx_id_list[1] & RXIDLIST_DEVICE_COUNT_UPPER_MASK) << 4);
++}
++
++static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
++{
++ /* device count must be greater than or equal to tracked hdcp displays */
++ return (get_device_count(hdcp) < get_added_display_count(hdcp)) ?
++ MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE :
++ MOD_HDCP_STATUS_SUCCESS;
++}
++
++static uint8_t process_rxstatus(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input,
++ enum mod_hdcp_status *status)
++{
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_rxstatus,
++ &input->rxstatus_read, status,
++ hdcp, "rxstatus_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(check_reauthentication_request,
++ &input->reauth_request_check, status,
++ hdcp, "reauth_request_check"))
++ goto out;
++ if (is_dp_hdcp(hdcp)) {
++ if (!mod_hdcp_execute_and_set(check_link_integrity_failure_dp,
++ &input->link_integrity_check_dp, status,
++ hdcp, "link_integrity_check_dp"))
++ goto out;
++ }
++ if (hdcp->connection.is_repeater)
++ if (check_receiver_id_list_ready(hdcp) ==
++ MOD_HDCP_STATUS_SUCCESS) {
++ HDCP_INPUT_PASS_TRACE(hdcp, "rx_id_list_ready");
++ event_ctx->rx_id_list_ready = 1;
++ if (is_dp_hdcp(hdcp))
++ hdcp->auth.msg.hdcp2.rx_id_list_size =
++ sizeof(hdcp->auth.msg.hdcp2.rx_id_list);
++ else
++ hdcp->auth.msg.hdcp2.rx_id_list_size =
++ hdcp->auth.msg.hdcp2.rxstatus & 0x3FF;
++ }
++out:
++ return (*status == MOD_HDCP_STATUS_SUCCESS);
++}
++
++static enum mod_hdcp_status known_hdcp2_capable_rx(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_hdcp2version,
++ &input->hdcp2version_read, &status,
++ hdcp, "hdcp2version_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(check_hdcp2_capable,
++ &input->hdcp2_capable_check, &status,
++ hdcp, "hdcp2_capable"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status send_ake_init(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++ if (!mod_hdcp_execute_and_set(mod_hdcp_add_display_topology,
++ &input->add_topology, &status,
++ hdcp, "add_topology"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_create_session,
++ &input->create_session, &status,
++ hdcp, "create_session"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_ake_init,
++ &input->ake_init_prepare, &status,
++ hdcp, "ake_init_prepare"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_ake_init,
++ &input->ake_init_write, &status,
++ hdcp, "ake_init_write"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status validate_ake_cert(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (is_hdmi_dvi_sl_hdcp(hdcp))
++ if (!mod_hdcp_execute_and_set(check_ake_cert_available,
++ &input->ake_cert_available, &status,
++ hdcp, "ake_cert_available"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_ake_cert,
++ &input->ake_cert_read, &status,
++ hdcp, "ake_cert_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_ake_cert,
++ &input->ake_cert_validation, &status,
++ hdcp, "ake_cert_validation"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status send_no_stored_km(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_no_stored_km,
++ &input->no_stored_km_write, &status,
++ hdcp, "no_stored_km_write"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status read_h_prime(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++ event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(check_h_prime_available,
++ &input->h_prime_available, &status,
++ hdcp, "h_prime_available"))
++ goto out;
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_h_prime,
++ &input->h_prime_read, &status,
++ hdcp, "h_prime_read"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status read_pairing_info_and_validate_h_prime(
++ struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++ event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(check_pairing_info_available,
++ &input->pairing_available, &status,
++ hdcp, "pairing_available"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_pairing_info,
++ &input->pairing_info_read, &status,
++ hdcp, "pairing_info_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_h_prime,
++ &input->h_prime_validation, &status,
++ hdcp, "h_prime_validation"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status send_stored_km(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_stored_km,
++ &input->stored_km_write, &status,
++ hdcp, "stored_km_write"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status validate_h_prime(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++ event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(check_h_prime_available,
++ &input->h_prime_available, &status,
++ hdcp, "h_prime_available"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_h_prime,
++ &input->h_prime_read, &status,
++ hdcp, "h_prime_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_h_prime,
++ &input->h_prime_validation, &status,
++ hdcp, "h_prime_validation"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status locality_check(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_lc_init,
++ &input->lc_init_prepare, &status,
++ hdcp, "lc_init_prepare"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init,
++ &input->lc_init_write, &status,
++ hdcp, "lc_init_write"))
++ goto out;
++ if (is_dp_hdcp(hdcp))
++ udelay(16000);
++ else
++ if (!mod_hdcp_execute_and_set(poll_l_prime_available,
++ &input->l_prime_available_poll, &status,
++ hdcp, "l_prime_available_poll"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime,
++ &input->l_prime_read, &status,
++ hdcp, "l_prime_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_l_prime,
++ &input->l_prime_validation, &status,
++ hdcp, "l_prime_validation"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status exchange_ks_and_test_for_repeater(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_eks,
++ &input->eks_prepare, &status,
++ hdcp, "eks_prepare"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_eks,
++ &input->eks_write, &status,
++ hdcp, "eks_write"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status enable_encryption(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++ if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++ process_rxstatus(hdcp, event_ctx, input, &status);
++ goto out;
++ }
++
++ if (is_hdmi_dvi_sl_hdcp(hdcp)) {
++ if (!process_rxstatus(hdcp, event_ctx, input, &status))
++ goto out;
++ if (event_ctx->rx_id_list_ready)
++ goto out;
++ }
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_enable_encryption,
++ &input->enable_encryption, &status,
++ hdcp, "enable_encryption"))
++ goto out;
++ if (is_dp_mst_hdcp(hdcp)) {
++ if (!mod_hdcp_execute_and_set(
++ mod_hdcp_hdcp2_enable_dp_stream_encryption,
++ &input->stream_encryption_dp, &status,
++ hdcp, "stream_encryption_dp"))
++ goto out;
++ }
++out:
++ return status;
++}
++
++static enum mod_hdcp_status authenticated(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!process_rxstatus(hdcp, event_ctx, input, &status))
++ goto out;
++ if (event_ctx->rx_id_list_ready)
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status wait_for_rx_id_list(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++ event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!process_rxstatus(hdcp, event_ctx, input, &status))
++ goto out;
++ if (!event_ctx->rx_id_list_ready) {
++ status = MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY;
++ goto out;
++ }
++out:
++ return status;
++}
++
++static enum mod_hdcp_status verify_rx_id_list_and_send_ack(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++ if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++ process_rxstatus(hdcp, event_ctx, input, &status);
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_rx_id_list,
++ &input->rx_id_list_read,
++ &status, hdcp, "receiver_id_list_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(check_device_count,
++ &input->device_count_check,
++ &status, hdcp, "device_count_check"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_rx_id_list,
++ &input->rx_id_list_validation,
++ &status, hdcp, "rx_id_list_validation"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_repeater_auth_ack,
++ &input->repeater_auth_ack_write,
++ &status, hdcp, "repeater_auth_ack_write"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status send_stream_management(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++ if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++ process_rxstatus(hdcp, event_ctx, input, &status);
++ goto out;
++ }
++
++ if (is_hdmi_dvi_sl_hdcp(hdcp)) {
++ if (!process_rxstatus(hdcp, event_ctx, input, &status))
++ goto out;
++ if (event_ctx->rx_id_list_ready)
++ goto out;
++ }
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_stream_management,
++ &input->prepare_stream_manage,
++ &status, hdcp, "prepare_stream_manage"))
++ goto out;
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_stream_manage,
++ &input->stream_manage_write,
++ &status, hdcp, "stream_manage_write"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status validate_stream_ready(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++ event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++ if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++ process_rxstatus(hdcp, event_ctx, input, &status);
++ goto out;
++ }
++
++ if (is_hdmi_dvi_sl_hdcp(hdcp)) {
++ if (!process_rxstatus(hdcp, event_ctx, input, &status))
++ goto out;
++ if (event_ctx->rx_id_list_ready) {
++ goto out;
++ }
++ }
++ if (is_hdmi_dvi_sl_hdcp(hdcp))
++ if (!mod_hdcp_execute_and_set(check_stream_ready_available,
++ &input->stream_ready_available,
++ &status, hdcp, "stream_ready_available"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_stream_ready,
++ &input->stream_ready_read,
++ &status, hdcp, "stream_ready_read"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_stream_ready,
++ &input->stream_ready_validation,
++ &status, hdcp, "stream_ready_validation"))
++ goto out;
++
++out:
++ return status;
++}
++
++static enum mod_hdcp_status determine_rx_hdcp_capable_dp(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!mod_hdcp_execute_and_set(mod_hdcp_read_rxcaps,
++ &input->rx_caps_read_dp,
++ &status, hdcp, "rx_caps_read_dp"))
++ goto out;
++ if (!mod_hdcp_execute_and_set(check_hdcp2_capable,
++ &input->hdcp2_capable_check, &status,
++ hdcp, "hdcp2_capable_check"))
++ goto out;
++out:
++ return status;
++}
++
++static enum mod_hdcp_status send_content_stream_type_dp(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++ event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++ event_ctx->unexpected_event = 1;
++ goto out;
++ }
++
++ if (!process_rxstatus(hdcp, event_ctx, input, &status))
++ goto out;
++ if (!mod_hdcp_execute_and_set(mod_hdcp_write_content_type,
++ &input->content_stream_type_write, &status,
++ hdcp, "content_stream_type_write"))
++ goto out;
++out:
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_execution(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ switch (current_state(hdcp)) {
++ case H2_A0_KNOWN_HDCP2_CAPABLE_RX:
++ status = known_hdcp2_capable_rx(hdcp, event_ctx, input);
++ break;
++ case H2_A1_SEND_AKE_INIT:
++ status = send_ake_init(hdcp, event_ctx, input);
++ break;
++ case H2_A1_VALIDATE_AKE_CERT:
++ status = validate_ake_cert(hdcp, event_ctx, input);
++ break;
++ case H2_A1_SEND_NO_STORED_KM:
++ status = send_no_stored_km(hdcp, event_ctx, input);
++ break;
++ case H2_A1_READ_H_PRIME:
++ status = read_h_prime(hdcp, event_ctx, input);
++ break;
++ case H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++ status = read_pairing_info_and_validate_h_prime(hdcp,
++ event_ctx, input);
++ break;
++ case H2_A1_SEND_STORED_KM:
++ status = send_stored_km(hdcp, event_ctx, input);
++ break;
++ case H2_A1_VALIDATE_H_PRIME:
++ status = validate_h_prime(hdcp, event_ctx, input);
++ break;
++ case H2_A2_LOCALITY_CHECK:
++ status = locality_check(hdcp, event_ctx, input);
++ break;
++ case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++ status = exchange_ks_and_test_for_repeater(hdcp, event_ctx, input);
++ break;
++ case H2_ENABLE_ENCRYPTION:
++ status = enable_encryption(hdcp, event_ctx, input);
++ break;
++ case H2_A5_AUTHENTICATED:
++ status = authenticated(hdcp, event_ctx, input);
++ break;
++ case H2_A6_WAIT_FOR_RX_ID_LIST:
++ status = wait_for_rx_id_list(hdcp, event_ctx, input);
++ break;
++ case H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++ status = verify_rx_id_list_and_send_ack(hdcp, event_ctx, input);
++ break;
++ case H2_A9_SEND_STREAM_MANAGEMENT:
++ status = send_stream_management(hdcp, event_ctx, input);
++ break;
++ case H2_A9_VALIDATE_STREAM_READY:
++ status = validate_stream_ready(hdcp, event_ctx, input);
++ break;
++ default:
++ status = MOD_HDCP_STATUS_INVALID_STATE;
++ break;
++ }
++
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_execution(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++ switch (current_state(hdcp)) {
++ case D2_A0_DETERMINE_RX_HDCP_CAPABLE:
++ status = determine_rx_hdcp_capable_dp(hdcp, event_ctx, input);
++ break;
++ case D2_A1_SEND_AKE_INIT:
++ status = send_ake_init(hdcp, event_ctx, input);
++ break;
++ case D2_A1_VALIDATE_AKE_CERT:
++ status = validate_ake_cert(hdcp, event_ctx, input);
++ break;
++ case D2_A1_SEND_NO_STORED_KM:
++ status = send_no_stored_km(hdcp, event_ctx, input);
++ break;
++ case D2_A1_READ_H_PRIME:
++ status = read_h_prime(hdcp, event_ctx, input);
++ break;
++ case D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++ status = read_pairing_info_and_validate_h_prime(hdcp,
++ event_ctx, input);
++ break;
++ case D2_A1_SEND_STORED_KM:
++ status = send_stored_km(hdcp, event_ctx, input);
++ break;
++ case D2_A1_VALIDATE_H_PRIME:
++ status = validate_h_prime(hdcp, event_ctx, input);
++ break;
++ case D2_A2_LOCALITY_CHECK:
++ status = locality_check(hdcp, event_ctx, input);
++ break;
++ case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++ status = exchange_ks_and_test_for_repeater(hdcp,
++ event_ctx, input);
++ break;
++ case D2_SEND_CONTENT_STREAM_TYPE:
++ status = send_content_stream_type_dp(hdcp, event_ctx, input);
++ break;
++ case D2_ENABLE_ENCRYPTION:
++ status = enable_encryption(hdcp, event_ctx, input);
++ break;
++ case D2_A5_AUTHENTICATED:
++ status = authenticated(hdcp, event_ctx, input);
++ break;
++ case D2_A6_WAIT_FOR_RX_ID_LIST:
++ status = wait_for_rx_id_list(hdcp, event_ctx, input);
++ break;
++ case D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++ status = verify_rx_id_list_and_send_ack(hdcp, event_ctx, input);
++ break;
++ case D2_A9_SEND_STREAM_MANAGEMENT:
++ status = send_stream_management(hdcp, event_ctx, input);
++ break;
++ case D2_A9_VALIDATE_STREAM_READY:
++ status = validate_stream_ready(hdcp, event_ctx, input);
++ break;
++ default:
++ status = MOD_HDCP_STATUS_INVALID_STATE;
++ break;
++ }
++
++ return status;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+new file mode 100644
+index 000000000000..94a0e5fa931b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+@@ -0,0 +1,674 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input,
++ struct mod_hdcp_output *output)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++ struct mod_hdcp_connection *conn = &hdcp->connection;
++ struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust;
++
++ switch (current_state(hdcp)) {
++ case H2_A0_KNOWN_HDCP2_CAPABLE_RX:
++ if (input->hdcp2version_read != PASS ||
++ input->hdcp2_capable_check != PASS) {
++ adjust->hdcp2.disable = 1;
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, HDCP_INITIALIZED);
++ } else {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A1_SEND_AKE_INIT);
++ }
++ break;
++ case H2_A1_SEND_AKE_INIT:
++ if (input->add_topology != PASS ||
++ input->create_session != PASS ||
++ input->ake_init_prepare != PASS) {
++ /* out of sync with psp state */
++ adjust->hdcp2.disable = 1;
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (input->ake_init_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ set_watchdog_in_ms(hdcp, 100, output);
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A1_VALIDATE_AKE_CERT);
++ break;
++ case H2_A1_VALIDATE_AKE_CERT:
++ if (input->ake_cert_available != PASS) {
++ if (event_ctx->event ==
++ MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ /* 1A-08: consider ake timeout a failure */
++ /* some hdmi receivers are not ready for HDCP
++ * immediately after video becomes active,
++ * delay 1s before retry on first HDCP message
++ * timeout.
++ */
++ fail_and_restart_in_ms(1000, &status, output);
++ } else {
++ /* continue ake cert polling*/
++ callback_in_ms(10, output);
++ increment_stay_counter(hdcp);
++ }
++ break;
++ } else if (input->ake_cert_read != PASS ||
++ input->ake_cert_validation != PASS) {
++ /*
++ * 1A-09: consider invalid ake cert a failure
++ * 1A-10: consider receiver id listed in SRM a failure
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ if (conn->is_km_stored &&
++ !adjust->hdcp2.force_no_stored_km) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A1_SEND_STORED_KM);
++ } else {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A1_SEND_NO_STORED_KM);
++ }
++ break;
++ case H2_A1_SEND_NO_STORED_KM:
++ if (input->no_stored_km_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ if (adjust->hdcp2.increase_h_prime_timeout)
++ set_watchdog_in_ms(hdcp, 2000, output);
++ else
++ set_watchdog_in_ms(hdcp, 1000, output);
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A1_READ_H_PRIME);
++ break;
++ case H2_A1_READ_H_PRIME:
++ if (input->h_prime_available != PASS) {
++ if (event_ctx->event ==
++ MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ /* 1A-11-3: consider h' timeout a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ } else {
++ /* continue h' polling */
++ callback_in_ms(100, output);
++ increment_stay_counter(hdcp);
++ }
++ break;
++ } else if (input->h_prime_read != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ set_watchdog_in_ms(hdcp, 200, output);
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME);
++ break;
++ case H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++ if (input->pairing_available != PASS) {
++ if (event_ctx->event ==
++ MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ /* 1A-12: consider pairing info timeout
++ * a failure
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ } else {
++ /* continue pairing info polling */
++ callback_in_ms(20, output);
++ increment_stay_counter(hdcp);
++ }
++ break;
++ } else if (input->pairing_info_read != PASS ||
++ input->h_prime_validation != PASS) {
++ /* 1A-11-1: consider invalid h' a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A2_LOCALITY_CHECK);
++ break;
++ case H2_A1_SEND_STORED_KM:
++ if (input->stored_km_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ set_watchdog_in_ms(hdcp, 200, output);
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A1_VALIDATE_H_PRIME);
++ break;
++ case H2_A1_VALIDATE_H_PRIME:
++ if (input->h_prime_available != PASS) {
++ if (event_ctx->event ==
++ MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ /* 1A-11-2: consider h' timeout a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ } else {
++ /* continue h' polling */
++ callback_in_ms(20, output);
++ increment_stay_counter(hdcp);
++ }
++ break;
++ } else if (input->h_prime_read != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (input->h_prime_validation != PASS) {
++ /* 1A-11-1: consider invalid h' a failure */
++ adjust->hdcp2.force_no_stored_km = 1;
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A2_LOCALITY_CHECK);
++ break;
++ case H2_A2_LOCALITY_CHECK:
++ if (hdcp->state.stay_count > 10 ||
++ input->lc_init_prepare != PASS ||
++ input->lc_init_write != PASS ||
++ input->l_prime_available_poll != PASS ||
++ input->l_prime_read != PASS) {
++ /*
++ * 1A-05: consider disconnection after LC init a failure
++ * 1A-13-1: consider invalid l' a failure
++ * 1A-13-2: consider l' timeout a failure
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (input->l_prime_validation != PASS) {
++ callback_in_ms(0, output);
++ increment_stay_counter(hdcp);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER);
++ break;
++ case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++ if (input->eks_prepare != PASS ||
++ input->eks_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ if (conn->is_repeater) {
++ set_watchdog_in_ms(hdcp, 3000, output);
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A6_WAIT_FOR_RX_ID_LIST);
++ } else {
++ /* some CTS equipment requires a delay GREATER than
++ * 200 ms, so delay 210 ms instead of 200 ms
++ */
++ callback_in_ms(210, output);
++ set_state_id(hdcp, output, H2_ENABLE_ENCRYPTION);
++ }
++ break;
++ case H2_ENABLE_ENCRYPTION:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS) {
++ /*
++ * 1A-07: restart hdcp on REAUTH_REQ
++ * 1B-08: restart hdcp on REAUTH_REQ
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ } else if (input->enable_encryption != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A5_AUTHENTICATED);
++ HDCP_FULL_DDC_TRACE(hdcp);
++ break;
++ case H2_A5_AUTHENTICATED:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ }
++ callback_in_ms(500, output);
++ increment_stay_counter(hdcp);
++ break;
++ case H2_A6_WAIT_FOR_RX_ID_LIST:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (!event_ctx->rx_id_list_ready) {
++ if (event_ctx->event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ /* 1B-02: consider rx id list timeout a failure */
++ /* some CTS equipment's actual timeout
++ * measurement is slightly greater than 3000 ms.
++ * Delay 100 ms to ensure it is fully timeout
++ * before re-authentication.
++ */
++ fail_and_restart_in_ms(100, &status, output);
++ } else {
++ callback_in_ms(300, output);
++ increment_stay_counter(hdcp);
++ }
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ case H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS ||
++ input->rx_id_list_read != PASS ||
++ input->device_count_check != PASS ||
++ input->rx_id_list_validation != PASS ||
++ input->repeater_auth_ack_write != PASS) {
++ /* 1B-03: consider invalid v' a failure
++ * 1B-04: consider MAX_DEVS_EXCEEDED a failure
++ * 1B-05: consider MAX_CASCADE_EXCEEDED a failure
++ * 1B-06: consider invalid seq_num_V a failure
++ * 1B-09: consider seq_num_V rollover a failure
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A9_SEND_STREAM_MANAGEMENT);
++ break;
++ case H2_A9_SEND_STREAM_MANAGEMENT:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ } else if (input->prepare_stream_manage != PASS ||
++ input->stream_manage_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ set_watchdog_in_ms(hdcp, 100, output);
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A9_VALIDATE_STREAM_READY);
++ break;
++ case H2_A9_VALIDATE_STREAM_READY:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ } else if (input->stream_ready_available != PASS) {
++ if (event_ctx->event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++ /* 1B-10-2: restart content stream management on
++ * stream ready timeout
++ */
++ hdcp->auth.count.stream_management_retry_count++;
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A9_SEND_STREAM_MANAGEMENT);
++ } else {
++ callback_in_ms(10, output);
++ increment_stay_counter(hdcp);
++ }
++ break;
++ } else if (input->stream_ready_read != PASS ||
++ input->stream_ready_validation != PASS) {
++ /*
++ * 1B-10-1: restart content stream management
++ * on invalid M'
++ */
++ if (hdcp->auth.count.stream_management_retry_count > 10) {
++ fail_and_restart_in_ms(0, &status, output);
++ } else {
++ hdcp->auth.count.stream_management_retry_count++;
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, H2_A9_SEND_STREAM_MANAGEMENT);
++ }
++ break;
++ }
++ callback_in_ms(200, output);
++ set_state_id(hdcp, output, H2_ENABLE_ENCRYPTION);
++ break;
++ default:
++ status = MOD_HDCP_STATUS_INVALID_STATE;
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++
++ return status;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
++ struct mod_hdcp_event_context *event_ctx,
++ struct mod_hdcp_transition_input_hdcp2 *input,
++ struct mod_hdcp_output *output)
++{
++ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++ struct mod_hdcp_connection *conn = &hdcp->connection;
++ struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust;
++
++ switch (current_state(hdcp)) {
++ case D2_A0_DETERMINE_RX_HDCP_CAPABLE:
++ if (input->rx_caps_read_dp != PASS ||
++ input->hdcp2_capable_check != PASS) {
++ adjust->hdcp2.disable = 1;
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, HDCP_INITIALIZED);
++ } else {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A1_SEND_AKE_INIT);
++ }
++ break;
++ case D2_A1_SEND_AKE_INIT:
++ if (input->add_topology != PASS ||
++ input->create_session != PASS ||
++ input->ake_init_prepare != PASS) {
++ /* out of sync with psp state */
++ adjust->hdcp2.disable = 1;
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (input->ake_init_write != PASS) {
++ /* possibly display not ready */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(100, output);
++ set_state_id(hdcp, output, D2_A1_VALIDATE_AKE_CERT);
++ break;
++ case D2_A1_VALIDATE_AKE_CERT:
++ if (input->ake_cert_read != PASS ||
++ input->ake_cert_validation != PASS) {
++ /*
++ * 1A-08: consider invalid ake cert a failure
++ * 1A-09: consider receiver id listed in SRM a failure
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ if (conn->is_km_stored &&
++ !adjust->hdcp2.force_no_stored_km) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A1_SEND_STORED_KM);
++ } else {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A1_SEND_NO_STORED_KM);
++ }
++ break;
++ case D2_A1_SEND_NO_STORED_KM:
++ if (input->no_stored_km_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ if (adjust->hdcp2.increase_h_prime_timeout)
++ set_watchdog_in_ms(hdcp, 2000, output);
++ else
++ set_watchdog_in_ms(hdcp, 1000, output);
++ set_state_id(hdcp, output, D2_A1_READ_H_PRIME);
++ break;
++ case D2_A1_READ_H_PRIME:
++ if (input->h_prime_available != PASS) {
++ if (event_ctx->event ==
++ MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++ /* 1A-10-3: consider h' timeout a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ else
++ increment_stay_counter(hdcp);
++ break;
++ } else if (input->h_prime_read != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ set_watchdog_in_ms(hdcp, 200, output);
++ set_state_id(hdcp, output, D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME);
++ break;
++ case D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++ if (input->pairing_available != PASS) {
++ if (event_ctx->event ==
++ MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++ /*
++ * 1A-11: consider pairing info timeout
++ * a failure
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ else
++ increment_stay_counter(hdcp);
++ break;
++ } else if (input->pairing_info_read != PASS ||
++ input->h_prime_validation != PASS) {
++ /* 1A-10-1: consider invalid h' a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A2_LOCALITY_CHECK);
++ break;
++ case D2_A1_SEND_STORED_KM:
++ if (input->stored_km_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ set_watchdog_in_ms(hdcp, 200, output);
++ set_state_id(hdcp, output, D2_A1_VALIDATE_H_PRIME);
++ break;
++ case D2_A1_VALIDATE_H_PRIME:
++ if (input->h_prime_available != PASS) {
++ if (event_ctx->event ==
++ MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++ /* 1A-10-2: consider h' timeout a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ else
++ increment_stay_counter(hdcp);
++ break;
++ } else if (input->h_prime_read != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (input->h_prime_validation != PASS) {
++ /* 1A-10-1: consider invalid h' a failure */
++ adjust->hdcp2.force_no_stored_km = 1;
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A2_LOCALITY_CHECK);
++ break;
++ case D2_A2_LOCALITY_CHECK:
++ if (hdcp->state.stay_count > 10 ||
++ input->lc_init_prepare != PASS ||
++ input->lc_init_write != PASS ||
++ input->l_prime_read != PASS) {
++ /* 1A-12: consider invalid l' a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (input->l_prime_validation != PASS) {
++ callback_in_ms(0, output);
++ increment_stay_counter(hdcp);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER);
++ break;
++ case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++ if (input->eks_prepare != PASS ||
++ input->eks_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ if (conn->is_repeater) {
++ set_watchdog_in_ms(hdcp, 3000, output);
++ set_state_id(hdcp, output, D2_A6_WAIT_FOR_RX_ID_LIST);
++ } else {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_SEND_CONTENT_STREAM_TYPE);
++ }
++ break;
++ case D2_SEND_CONTENT_STREAM_TYPE:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS ||
++ input->link_integrity_check_dp != PASS ||
++ input->content_stream_type_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(210, output);
++ set_state_id(hdcp, output, D2_ENABLE_ENCRYPTION);
++ break;
++ case D2_ENABLE_ENCRYPTION:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS ||
++ input->link_integrity_check_dp != PASS) {
++ /*
++ * 1A-07: restart hdcp on REAUTH_REQ
++ * 1B-08: restart hdcp on REAUTH_REQ
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ } else if (input->enable_encryption != PASS ||
++ (is_dp_mst_hdcp(hdcp) && input->stream_encryption_dp != PASS)) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ set_state_id(hdcp, output, D2_A5_AUTHENTICATED);
++ HDCP_FULL_DDC_TRACE(hdcp);
++ break;
++ case D2_A5_AUTHENTICATED:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (input->link_integrity_check_dp != PASS) {
++ if (hdcp->connection.hdcp2_retry_count >= 1)
++ adjust->hdcp2.disable_type1 = 1;
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ }
++ increment_stay_counter(hdcp);
++ break;
++ case D2_A6_WAIT_FOR_RX_ID_LIST:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS ||
++ input->link_integrity_check_dp != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (!event_ctx->rx_id_list_ready) {
++ if (event_ctx->event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++ /* 1B-02: consider rx id list timeout a failure */
++ fail_and_restart_in_ms(0, &status, output);
++ else
++ increment_stay_counter(hdcp);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ case D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS ||
++ input->link_integrity_check_dp != PASS ||
++ input->rx_id_list_read != PASS ||
++ input->device_count_check != PASS ||
++ input->rx_id_list_validation != PASS ||
++ input->repeater_auth_ack_write != PASS) {
++ /*
++ * 1B-03: consider invalid v' a failure
++ * 1B-04: consider MAX_DEVS_EXCEEDED a failure
++ * 1B-05: consider MAX_CASCADE_EXCEEDED a failure
++ * 1B-06: consider invalid seq_num_V a failure
++ * 1B-09: consider seq_num_V rollover a failure
++ */
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A9_SEND_STREAM_MANAGEMENT);
++ break;
++ case D2_A9_SEND_STREAM_MANAGEMENT:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS ||
++ input->link_integrity_check_dp != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ } else if (input->prepare_stream_manage != PASS ||
++ input->stream_manage_write != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ callback_in_ms(100, output);
++ set_state_id(hdcp, output, D2_A9_VALIDATE_STREAM_READY);
++ break;
++ case D2_A9_VALIDATE_STREAM_READY:
++ if (input->rxstatus_read != PASS ||
++ input->reauth_request_check != PASS ||
++ input->link_integrity_check_dp != PASS) {
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ } else if (event_ctx->rx_id_list_ready) {
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++ break;
++ } else if (input->stream_ready_read != PASS ||
++ input->stream_ready_validation != PASS) {
++ /*
++ * 1B-10-1: restart content stream management
++ * on invalid M'
++ * 1B-10-2: consider stream ready timeout a failure
++ */
++ if (hdcp->auth.count.stream_management_retry_count > 10) {
++ fail_and_restart_in_ms(0, &status, output);
++ } else {
++ hdcp->auth.count.stream_management_retry_count++;
++ callback_in_ms(0, output);
++ set_state_id(hdcp, output, D2_A9_SEND_STREAM_MANAGEMENT);
++ }
++ break;
++ }
++ callback_in_ms(200, output);
++ set_state_id(hdcp, output, D2_ENABLE_ENCRYPTION);
++ break;
++ default:
++ status = MOD_HDCP_STATUS_INVALID_STATE;
++ fail_and_restart_in_ms(0, &status, output);
++ break;
++ }
++ return status;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+index dea21702edff..97ecbf5bfec1 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+@@ -77,6 +77,7 @@ enum mod_hdcp_status {
+ MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING,
+ MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING,
+ MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE,
++ MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED,
+ MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE,
+ MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE,
+ MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE,
+@@ -86,6 +87,7 @@ enum mod_hdcp_status {
+ MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE,
+ MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY,
+ MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE,
++ MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED,
+ MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION,
+ MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING,
+ MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4503-drm-amd-display-Add-logging-for-HDCP2.2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4503-drm-amd-display-Add-logging-for-HDCP2.2.patch
new file mode 100644
index 00000000..d35a3ef4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4503-drm-amd-display-Add-logging-for-HDCP2.2.patch
@@ -0,0 +1,309 @@
+From 4f15a05fdfe99ba65a5cb3574965f6acf4316bd0 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:24:09 -0400
+Subject: [PATCH 4503/4736] drm/amd/display: Add logging for HDCP2.2
+
+[Why]
+We need to log the state changes for 2.2
+This patch extends the existing logging functions to handle
+HDCP2.2.
+
+[How]
+We do this by adding if/else in the defines, and output the log
+ based on the hdcp version
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/modules/hdcp/hdcp_log.c | 118 ++++++++++++++++++
+ .../drm/amd/display/modules/hdcp/hdcp_log.h | 94 +++++++++++---
+ .../drm/amd/display/modules/hdcp/hdcp_psp.c | 4 +
+ 3 files changed, 196 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+index 3982ced5f969..724ebcee9a19 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+@@ -116,6 +116,58 @@ char *mod_hdcp_status_to_str(int32_t status)
+ return "MOD_HDCP_STATUS_DDC_FAILURE";
+ case MOD_HDCP_STATUS_INVALID_OPERATION:
+ return "MOD_HDCP_STATUS_INVALID_OPERATION";
++ case MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE:
++ return "MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE";
++ case MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING:
++ return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING";
++ case MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING:
++ return "MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING";
++ case MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING:
++ return "MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING";
++ case MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED:
++ return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED";
++ case MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING:
++ return "MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING";
++ case MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED:
++ return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED";
++ case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY:
++ return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY";
++ case MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION:
++ return "MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION";
++ case MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING:
++ return "MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING";
++ case MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST:
++ return "MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST";
++ case MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE";
++ case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE:
++ return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE";
+ default:
+ return "MOD_HDCP_STATUS_UNKNOWN";
+ }
+@@ -156,6 +208,72 @@ char *mod_hdcp_state_id_to_str(int32_t id)
+ return "D1_A6_WAIT_FOR_READY";
+ case D1_A7_READ_KSV_LIST:
+ return "D1_A7_READ_KSV_LIST";
++ case H2_A0_KNOWN_HDCP2_CAPABLE_RX:
++ return "H2_A0_KNOWN_HDCP2_CAPABLE_RX";
++ case H2_A1_SEND_AKE_INIT:
++ return "H2_A1_SEND_AKE_INIT";
++ case H2_A1_VALIDATE_AKE_CERT:
++ return "H2_A1_VALIDATE_AKE_CERT";
++ case H2_A1_SEND_NO_STORED_KM:
++ return "H2_A1_SEND_NO_STORED_KM";
++ case H2_A1_READ_H_PRIME:
++ return "H2_A1_READ_H_PRIME";
++ case H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++ return "H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME";
++ case H2_A1_SEND_STORED_KM:
++ return "H2_A1_SEND_STORED_KM";
++ case H2_A1_VALIDATE_H_PRIME:
++ return "H2_A1_VALIDATE_H_PRIME";
++ case H2_A2_LOCALITY_CHECK:
++ return "H2_A2_LOCALITY_CHECK";
++ case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++ return "H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER";
++ case H2_ENABLE_ENCRYPTION:
++ return "H2_ENABLE_ENCRYPTION";
++ case H2_A5_AUTHENTICATED:
++ return "H2_A5_AUTHENTICATED";
++ case H2_A6_WAIT_FOR_RX_ID_LIST:
++ return "H2_A6_WAIT_FOR_RX_ID_LIST";
++ case H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++ return "H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK";
++ case H2_A9_SEND_STREAM_MANAGEMENT:
++ return "H2_A9_SEND_STREAM_MANAGEMENT";
++ case H2_A9_VALIDATE_STREAM_READY:
++ return "H2_A9_VALIDATE_STREAM_READY";
++ case D2_A0_DETERMINE_RX_HDCP_CAPABLE:
++ return "D2_A0_DETERMINE_RX_HDCP_CAPABLE";
++ case D2_A1_SEND_AKE_INIT:
++ return "D2_A1_SEND_AKE_INIT";
++ case D2_A1_VALIDATE_AKE_CERT:
++ return "D2_A1_VALIDATE_AKE_CERT";
++ case D2_A1_SEND_NO_STORED_KM:
++ return "D2_A1_SEND_NO_STORED_KM";
++ case D2_A1_READ_H_PRIME:
++ return "D2_A1_READ_H_PRIME";
++ case D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++ return "D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME";
++ case D2_A1_SEND_STORED_KM:
++ return "D2_A1_SEND_STORED_KM";
++ case D2_A1_VALIDATE_H_PRIME:
++ return "D2_A1_VALIDATE_H_PRIME";
++ case D2_A2_LOCALITY_CHECK:
++ return "D2_A2_LOCALITY_CHECK";
++ case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++ return "D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER";
++ case D2_SEND_CONTENT_STREAM_TYPE:
++ return "D2_SEND_CONTENT_STREAM_TYPE";
++ case D2_ENABLE_ENCRYPTION:
++ return "D2_ENABLE_ENCRYPTION";
++ case D2_A5_AUTHENTICATED:
++ return "D2_A5_AUTHENTICATED";
++ case D2_A6_WAIT_FOR_RX_ID_LIST:
++ return "D2_A6_WAIT_FOR_RX_ID_LIST";
++ case D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++ return "D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK";
++ case D2_A9_SEND_STREAM_MANAGEMENT:
++ return "D2_A9_SEND_STREAM_MANAGEMENT";
++ case D2_A9_VALIDATE_STREAM_READY:
++ return "D2_A9_VALIDATE_STREAM_READY";
+ default:
+ return "UNKNOWN_STATE_ID";
+ };
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+index 2fd0e0a893ef..b29322e7d5fe 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+@@ -45,6 +45,10 @@
+ HDCP_LOG_VER(hdcp, \
+ "[Link %d] HDCP 1.4 enabled on display %d", \
+ hdcp->config.index, displayIndex)
++#define HDCP_HDCP2_ENABLED_TRACE(hdcp, displayIndex) \
++ HDCP_LOG_VER(hdcp, \
++ "[Link %d] HDCP 2.2 enabled on display %d", \
++ hdcp->config.index, displayIndex)
+ /* state machine logs */
+ #define HDCP_REMOVE_DISPLAY_TRACE(hdcp, displayIndex) \
+ HDCP_LOG_FSM(hdcp, \
+@@ -93,26 +97,73 @@
+ hdcp->buf); \
+ } while (0)
+ #define HDCP_FULL_DDC_TRACE(hdcp) do { \
+- HDCP_DDC_READ_TRACE(hdcp, "BKSV", hdcp->auth.msg.hdcp1.bksv, \
+- sizeof(hdcp->auth.msg.hdcp1.bksv)); \
+- HDCP_DDC_READ_TRACE(hdcp, "BCAPS", &hdcp->auth.msg.hdcp1.bcaps, \
+- sizeof(hdcp->auth.msg.hdcp1.bcaps)); \
+- HDCP_DDC_WRITE_TRACE(hdcp, "AN", hdcp->auth.msg.hdcp1.an, \
+- sizeof(hdcp->auth.msg.hdcp1.an)); \
+- HDCP_DDC_WRITE_TRACE(hdcp, "AKSV", hdcp->auth.msg.hdcp1.aksv, \
+- sizeof(hdcp->auth.msg.hdcp1.aksv)); \
+- HDCP_DDC_WRITE_TRACE(hdcp, "AINFO", &hdcp->auth.msg.hdcp1.ainfo, \
+- sizeof(hdcp->auth.msg.hdcp1.ainfo)); \
+- HDCP_DDC_READ_TRACE(hdcp, "RI' / R0'", \
+- (uint8_t *)&hdcp->auth.msg.hdcp1.r0p, \
+- sizeof(hdcp->auth.msg.hdcp1.r0p)); \
+- HDCP_DDC_READ_TRACE(hdcp, "BINFO", \
+- (uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp, \
+- sizeof(hdcp->auth.msg.hdcp1.binfo_dp)); \
+- HDCP_DDC_READ_TRACE(hdcp, "KSVLIST", hdcp->auth.msg.hdcp1.ksvlist, \
+- hdcp->auth.msg.hdcp1.ksvlist_size); \
+- HDCP_DDC_READ_TRACE(hdcp, "V'", hdcp->auth.msg.hdcp1.vp, \
+- sizeof(hdcp->auth.msg.hdcp1.vp)); \
++ if (is_hdcp1(hdcp)) { \
++ HDCP_DDC_READ_TRACE(hdcp, "BKSV", hdcp->auth.msg.hdcp1.bksv, \
++ sizeof(hdcp->auth.msg.hdcp1.bksv)); \
++ HDCP_DDC_READ_TRACE(hdcp, "BCAPS", &hdcp->auth.msg.hdcp1.bcaps, \
++ sizeof(hdcp->auth.msg.hdcp1.bcaps)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "AN", hdcp->auth.msg.hdcp1.an, \
++ sizeof(hdcp->auth.msg.hdcp1.an)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "AKSV", hdcp->auth.msg.hdcp1.aksv, \
++ sizeof(hdcp->auth.msg.hdcp1.aksv)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "AINFO", &hdcp->auth.msg.hdcp1.ainfo, \
++ sizeof(hdcp->auth.msg.hdcp1.ainfo)); \
++ HDCP_DDC_READ_TRACE(hdcp, "RI' / R0'", \
++ (uint8_t *)&hdcp->auth.msg.hdcp1.r0p, \
++ sizeof(hdcp->auth.msg.hdcp1.r0p)); \
++ HDCP_DDC_READ_TRACE(hdcp, "BINFO", \
++ (uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp, \
++ sizeof(hdcp->auth.msg.hdcp1.binfo_dp)); \
++ HDCP_DDC_READ_TRACE(hdcp, "KSVLIST", hdcp->auth.msg.hdcp1.ksvlist, \
++ hdcp->auth.msg.hdcp1.ksvlist_size); \
++ HDCP_DDC_READ_TRACE(hdcp, "V'", hdcp->auth.msg.hdcp1.vp, \
++ sizeof(hdcp->auth.msg.hdcp1.vp)); \
++ } else { \
++ HDCP_DDC_READ_TRACE(hdcp, "HDCP2Version", \
++ &hdcp->auth.msg.hdcp2.hdcp2version_hdmi, \
++ sizeof(hdcp->auth.msg.hdcp2.hdcp2version_hdmi)); \
++ HDCP_DDC_READ_TRACE(hdcp, "Rx Caps", hdcp->auth.msg.hdcp2.rxcaps_dp, \
++ sizeof(hdcp->auth.msg.hdcp2.rxcaps_dp)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "AKE Init", hdcp->auth.msg.hdcp2.ake_init, \
++ sizeof(hdcp->auth.msg.hdcp2.ake_init)); \
++ HDCP_DDC_READ_TRACE(hdcp, "AKE Cert", hdcp->auth.msg.hdcp2.ake_cert, \
++ sizeof(hdcp->auth.msg.hdcp2.ake_cert)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "Stored KM", \
++ hdcp->auth.msg.hdcp2.ake_stored_km, \
++ sizeof(hdcp->auth.msg.hdcp2.ake_stored_km)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "No Stored KM", \
++ hdcp->auth.msg.hdcp2.ake_no_stored_km, \
++ sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km)); \
++ HDCP_DDC_READ_TRACE(hdcp, "H'", hdcp->auth.msg.hdcp2.ake_h_prime, \
++ sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)); \
++ HDCP_DDC_READ_TRACE(hdcp, "Pairing Info", \
++ hdcp->auth.msg.hdcp2.ake_pairing_info, \
++ sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "LC Init", hdcp->auth.msg.hdcp2.lc_init, \
++ sizeof(hdcp->auth.msg.hdcp2.lc_init)); \
++ HDCP_DDC_READ_TRACE(hdcp, "L'", hdcp->auth.msg.hdcp2.lc_l_prime, \
++ sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "Exchange KS", hdcp->auth.msg.hdcp2.ske_eks, \
++ sizeof(hdcp->auth.msg.hdcp2.ske_eks)); \
++ HDCP_DDC_READ_TRACE(hdcp, "Rx Status", \
++ (uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus, \
++ sizeof(hdcp->auth.msg.hdcp2.rxstatus)); \
++ HDCP_DDC_READ_TRACE(hdcp, "Rx Id List", \
++ hdcp->auth.msg.hdcp2.rx_id_list, \
++ hdcp->auth.msg.hdcp2.rx_id_list_size); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "Rx Id List Ack", \
++ hdcp->auth.msg.hdcp2.repeater_auth_ack, \
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "Content Stream Management", \
++ hdcp->auth.msg.hdcp2.repeater_auth_stream_manage, \
++ hdcp->auth.msg.hdcp2.stream_manage_size); \
++ HDCP_DDC_READ_TRACE(hdcp, "Stream Ready", \
++ hdcp->auth.msg.hdcp2.repeater_auth_stream_ready, \
++ sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)); \
++ HDCP_DDC_WRITE_TRACE(hdcp, "Content Stream Type", \
++ hdcp->auth.msg.hdcp2.content_stream_type_dp, \
++ sizeof(hdcp->auth.msg.hdcp2.content_stream_type_dp)); \
++ } \
+ } while (0)
+ #define HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, i) \
+ HDCP_LOG_TOP(hdcp, "[Link %d]\tadd display %d", \
+@@ -123,6 +174,9 @@
+ #define HDCP_TOP_HDCP1_DESTROY_SESSION_TRACE(hdcp) \
+ HDCP_LOG_TOP(hdcp, "[Link %d]\tdestroy hdcp1 session", \
+ hdcp->config.index)
++#define HDCP_TOP_HDCP2_DESTROY_SESSION_TRACE(hdcp) \
++ HDCP_LOG_TOP(hdcp, "[Link %d]\tdestroy hdcp2 session", \
++ hdcp->config.index)
+ #define HDCP_TOP_RESET_AUTH_TRACE(hdcp) \
+ HDCP_LOG_TOP(hdcp, "[Link %d]\treset authentication", hdcp->config.index)
+ #define HDCP_TOP_RESET_CONN_TRACE(hdcp) \
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index ddba0cfa5722..a365cf00bc4c 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -393,6 +393,8 @@ enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp)
+ if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
+ return MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE;
+
++ HDCP_TOP_HDCP2_DESTROY_SESSION_TRACE(hdcp);
++
+ return MOD_HDCP_STATUS_SUCCESS;
+ }
+
+@@ -649,6 +651,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp)
+
+ if (!is_dp_mst_hdcp(hdcp)) {
+ display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++ HDCP_HDCP2_ENABLED_TRACE(hdcp, display->index);
+ }
+
+ return MOD_HDCP_STATUS_SUCCESS;
+@@ -727,6 +730,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(struct mod_hdcp
+ break;
+
+ hdcp->connection.displays[i].state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++ HDCP_HDCP2_ENABLED_TRACE(hdcp, hdcp->connection.displays[i].index);
+ }
+
+ return (hdcp_cmd->hdcp_status == TA_HDCP_STATUS__SUCCESS) ? MOD_HDCP_STATUS_SUCCESS
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4504-drm-amd-display-Change-ERROR-to-WARN-for-HDCP-module.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4504-drm-amd-display-Change-ERROR-to-WARN-for-HDCP-module.patch
new file mode 100644
index 00000000..eedcc6a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4504-drm-amd-display-Change-ERROR-to-WARN-for-HDCP-module.patch
@@ -0,0 +1,48 @@
+From 64c431ef83bb5b79760d2ccec2e87b8e2b03a1b8 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:24:39 -0400
+Subject: [PATCH 4504/4736] drm/amd/display: Change ERROR to WARN for HDCP
+ module
+
+[Why]
+HDCP is a bit finicky so we try it 3 times, this leads to a case where
+if we fail the first time and pass the second time the error is still
+shown in dmesg for the first failed attempt.
+
+This leads to false positive errors.
+
+[How]
+Change the logging from ERROR to WARNING. Warnings are still shown in dmesg
+to know what went wrong.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+index b29322e7d5fe..ff91373ebada 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+@@ -27,7 +27,7 @@
+ #define MOD_HDCP_LOG_H_
+
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+-#define HDCP_LOG_ERR(hdcp, ...) DRM_ERROR(__VA_ARGS__)
++#define HDCP_LOG_ERR(hdcp, ...) DRM_WARN(__VA_ARGS__)
+ #define HDCP_LOG_VER(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
+ #define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
+ #define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__)
+@@ -37,7 +37,7 @@
+ /* default logs */
+ #define HDCP_ERROR_TRACE(hdcp, status) \
+ HDCP_LOG_ERR(hdcp, \
+- "[Link %d] ERROR %s IN STATE %s", \
++ "[Link %d] WARNING %s IN STATE %s", \
+ hdcp->config.index, \
+ mod_hdcp_status_to_str(status), \
+ mod_hdcp_state_id_to_str(hdcp->state.id))
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4505-drm-amd-display-Enable-HDCP-2.2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4505-drm-amd-display-Enable-HDCP-2.2.patch
new file mode 100644
index 00000000..224e05ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4505-drm-amd-display-Enable-HDCP-2.2.patch
@@ -0,0 +1,58 @@
+From 07ec6fac9421d37e317e547585d4a37e925477c8 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 23 Jul 2019 11:25:10 -0400
+Subject: [PATCH 4505/4736] drm/amd/display: Enable HDCP 2.2
+
+[Why]
+HDCP 2.2 was disabled, we need to enable it
+
+[How]
+-Update display topology to support 2.2
+-Unset hdcp2.disable in update_config
+-Change logic of event_update_property, now we set the property to be
+ENABLED for any level of encryption (2.2 or 1.4).
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +--
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 2 +-
+ 2 files changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 77181ddf6c8e..970f2d58c6dc 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -190,7 +190,7 @@ static void event_property_update(struct work_struct *work)
+ }
+ }
+
+- if (hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON)
++ if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF)
+ drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
+ else
+ drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED);
+@@ -294,7 +294,6 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
+ link->dig_be = config->link_enc_inst;
+ link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
+ link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
+- link->adjust.hdcp2.disable = 1;
+
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index a365cf00bc4c..a9511612f426 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -109,7 +109,7 @@ enum mod_hdcp_status mod_hdcp_add_display_topology(struct mod_hdcp *hdcp)
+ dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = display->dig_fe;
+ dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid = display->vc_id;
+ dtm_cmd->dtm_in_message.topology_update_v2.max_hdcp_supported_version =
+- TA_DTM_HDCP_VERSION_MAX_SUPPORTED__1_x;
++ TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_2;
+ dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
+
+ psp_dtm_invoke(psp, dtm_cmd->cmd_id);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4506-drm-amd-display-Handle-hdcp2.2-type0-1-in-dm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4506-drm-amd-display-Handle-hdcp2.2-type0-1-in-dm.patch
new file mode 100644
index 00000000..490a1df7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4506-drm-amd-display-Handle-hdcp2.2-type0-1-in-dm.patch
@@ -0,0 +1,164 @@
+From 370e7141a7d4f568b25dec0fda37ceaeaa77ce5e Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 16 Aug 2019 14:49:05 -0400
+Subject: [PATCH 4506/4736] drm/amd/display: Handle hdcp2.2 type0/1 in dm
+
+[Why]
+HDCP 2.2 uses type0 and type1 content type. This is passed to the receiver
+to stream the proper content.
+
+For example, in a MST case if the main
+device is HDCP2.2 capable but the secondary device is only 1.4 capabale
+we can use Type0
+
+Type0 content: use HDCP 1.4 or HDCP2.2 type0
+Type1 content: Only use HDCP 2.2 type1
+
+[How]
+We use the "hdcp content type" property in drm. We use the
+disable_type1 flag in hdcp module to select the type based on the
+properties.
+
+For updating the property we use the same logic as 1.4, but now we
+consider content_type as well and update the property if the
+requirements are met
+
+Change-Id: I17bffd50b245e119adfba8ea0ad6a1402fcdd939
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ++++++++++++++----
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 17 +++++++++++++----
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 4 ++--
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 5 ++++-
+ 4 files changed, 33 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ec9fac7d4559..3828a19a87bb 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -43,6 +43,7 @@
+ #include "amdgpu_dm.h"
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ #include "amdgpu_dm_hdcp.h"
++#include <drm/drm_hdcp.h>
+ #endif
+ #include "amdgpu_pm.h"
+
+@@ -5477,7 +5478,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ adev->mode_info.freesync_capable_property, 0);
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ if (adev->asic_type >= CHIP_RAVEN)
+- drm_connector_attach_content_protection_property(&aconnector->base, false);
++ drm_connector_attach_content_protection_property(&aconnector->base, true);
+ #endif
+ }
+ }
+@@ -5728,6 +5729,12 @@ static bool is_content_protection_different(struct drm_connector_state *state,
+ {
+ struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+
++ if (old_state->hdcp_content_type != state->hdcp_content_type &&
++ state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
++ state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++ return true;
++ }
++
+ /* CP is being re enabled, ignore this */
+ if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+ state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+@@ -5760,11 +5767,14 @@ static void update_content_protection(struct drm_connector_state *state, const s
+ struct hdcp_workqueue *hdcp_w)
+ {
+ struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
++ bool disable_type1 = state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false;
+
+- if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
+- hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector);
+- else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
++ if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
++ hdcp_reset_display(hdcp_w, aconnector->dc_link->link_index);
++ hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector, disable_type1);
++ } else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+ hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
++ }
+
+ }
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 970f2d58c6dc..a2ad1390977d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -87,7 +87,8 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+
+ }
+
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector)
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
++ bool disable_type1)
+ {
+ struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+ struct mod_hdcp_display *display = &hdcp_work[link_index].display;
+@@ -96,6 +97,8 @@ void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,
+ mutex_lock(&hdcp_w->mutex);
+ hdcp_w->aconnector = aconnector;
+
++ hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
++
+ mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
+
+ schedule_delayed_work(&hdcp_w->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+@@ -190,10 +193,16 @@ static void event_property_update(struct work_struct *work)
+ }
+ }
+
+- if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF)
+- drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
+- else
++ if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
++ if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 &&
++ hdcp_work->encryption_status <= MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON)
++ drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
++ else if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE1 &&
++ hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
++ drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
++ } else {
+ drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED);
++ }
+
+
+ mutex_unlock(&hdcp_work->mutex);
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index d3ba505d0696..098f7218f83a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -54,8 +54,8 @@ struct hdcp_workqueue {
+ uint8_t max_link;
+ };
+
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,
+- struct amdgpu_dm_connector *aconnector);
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
++ bool disable_type1);
+ void hdcp_remove_display(struct hdcp_workqueue *work, unsigned int link_index, unsigned int display_index);
+ void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
+ void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index a74812977963..0f2f242710b3 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -417,7 +417,10 @@ enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
+ query->trace = &hdcp->connection.trace;
+ query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+
+- mod_hdcp_hdcp1_get_link_encryption_status(hdcp, &query->encryption_status);
++ if (is_hdcp1(hdcp))
++ mod_hdcp_hdcp1_get_link_encryption_status(hdcp, &query->encryption_status);
++ else if (is_hdcp2(hdcp))
++ mod_hdcp_hdcp2_get_link_encryption_status(hdcp, &query->encryption_status);
+
+ out:
+ return status;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4507-drm-amd-display-Refactor-HDCP-to-handle-multiple-dis.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4507-drm-amd-display-Refactor-HDCP-to-handle-multiple-dis.patch
new file mode 100644
index 00000000..d1b0bdbb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4507-drm-amd-display-Refactor-HDCP-to-handle-multiple-dis.patch
@@ -0,0 +1,178 @@
+From 99a2fd8154613cbb8cc2720f94d56d7c1a75059b Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 28 Aug 2019 15:10:03 -0400
+Subject: [PATCH 4507/4736] drm/amd/display: Refactor HDCP to handle multiple
+ displays per link
+
+[Why]
+We need to do this to support HDCP over MST
+
+Currently we save a display per link, in a MST case we need to save
+multiple displays per link.
+
+[How]
+We can create an array per link to cache the displays, but it
+complicates the design. Instead we can use the module to cache the
+displays.
+
+Now we will always add all the displays to the module, but we use the
+adjustment flag to disable hdcp on all of them before they are added.
+
+When we want to enable hdcp we just query the display(cache), remove
+it then add it back with different adjustments. Its the similar for
+disable.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ++-----
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 53 ++++++++++---------
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 9 ++--
+ 3 files changed, 40 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3828a19a87bb..9ca6806f7cef 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5763,20 +5763,6 @@ static bool is_content_protection_different(struct drm_connector_state *state,
+ return false;
+ }
+
+-static void update_content_protection(struct drm_connector_state *state, const struct drm_connector *connector,
+- struct hdcp_workqueue *hdcp_w)
+-{
+- struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+- bool disable_type1 = state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false;
+-
+- if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+- hdcp_reset_display(hdcp_w, aconnector->dc_link->link_index);
+- hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector, disable_type1);
+- } else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+- hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
+- }
+-
+-}
+ #endif
+ static void remove_stream(struct amdgpu_device *adev,
+ struct amdgpu_crtc *acrtc,
+@@ -6740,7 +6726,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ }
+
+ if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
+- update_content_protection(new_con_state, connector, adev->dm.hdcp_workqueue);
++ hdcp_update_display(
++ adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
++ new_con_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false,
++ new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
++ : false);
+ }
+ #endif
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index a2ad1390977d..53e382bff54d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -87,43 +87,45 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+
+ }
+
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
+- bool disable_type1)
++void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
++ unsigned int link_index,
++ struct amdgpu_dm_connector *aconnector,
++ bool disable_type1,
++ bool enable_encryption)
+ {
+ struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+ struct mod_hdcp_display *display = &hdcp_work[link_index].display;
+ struct mod_hdcp_link *link = &hdcp_work[link_index].link;
++ struct mod_hdcp_display_query query;
+
+ mutex_lock(&hdcp_w->mutex);
+ hdcp_w->aconnector = aconnector;
+
+- hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
+-
+- mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
+-
+- schedule_delayed_work(&hdcp_w->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+-
+- process_output(hdcp_w);
+-
+- mutex_unlock(&hdcp_w->mutex);
+-
+-}
+-
+-void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, unsigned int display_index)
+-{
+- struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+-
+- mutex_lock(&hdcp_w->mutex);
++ query.display = NULL;
++ mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &query);
++
++ if (query.display != NULL) {
++ memcpy(display, query.display, sizeof(struct mod_hdcp_display));
++ mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
++
++ if (enable_encryption) {
++ display->adjust.disable = 0;
++ hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
++ schedule_delayed_work(&hdcp_w->property_validate_dwork,
++ msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
++ } else {
++ display->adjust.disable = 1;
++ hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++ cancel_delayed_work(&hdcp_w->property_validate_dwork);
++ }
+
+- mod_hdcp_remove_display(&hdcp_w->hdcp, display_index, &hdcp_w->output);
++ display->state = MOD_HDCP_DISPLAY_ACTIVE;
++ }
+
+- cancel_delayed_work(&hdcp_w->property_validate_dwork);
+- hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++ mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
+
+ process_output(hdcp_w);
+-
+ mutex_unlock(&hdcp_w->mutex);
+-
+ }
+
+ void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
+@@ -303,7 +305,10 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
+ link->dig_be = config->link_enc_inst;
+ link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
+ link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
++ display->adjust.disable = 1;
++ link->adjust.auth_delay = 2;
+
++ hdcp_update_display(hdcp_work, link_index, aconnector, false, false);
+ }
+
+ struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index 098f7218f83a..71e121f037cb 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -54,9 +54,12 @@ struct hdcp_workqueue {
+ uint8_t max_link;
+ };
+
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
+- bool disable_type1);
+-void hdcp_remove_display(struct hdcp_workqueue *work, unsigned int link_index, unsigned int display_index);
++void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
++ unsigned int link_index,
++ struct amdgpu_dm_connector *aconnector,
++ bool disable_type1,
++ bool enable_encryption);
++
+ void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
+ void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
+ void hdcp_destroy(struct hdcp_workqueue *work);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4508-drm-amd-display-add-force-Type0-1-flag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4508-drm-amd-display-add-force-Type0-1-flag.patch
new file mode 100644
index 00000000..58278366
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4508-drm-amd-display-add-force-Type0-1-flag.patch
@@ -0,0 +1,157 @@
+From bc8f313777b528428a92ed7477258eb6c38dbbe0 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 29 Aug 2019 15:26:54 -0400
+Subject: [PATCH 4508/4736] drm/amd/display: add force Type0/1 flag
+
+[Why]
+Before we had a disable_type1 flag, this forced HDCP 2.2 to type0
+There was no way to force type1.
+
+[How]
+Remove disable_type1 flag and instead add a flag to force type0/1.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 12 +++++++++---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 2 +-
+ .../drm/amd/display/modules/hdcp/hdcp2_transition.c | 2 +-
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 7 +++++--
+ drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 11 +++++++++--
+ 6 files changed, 26 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 9ca6806f7cef..430008124373 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -6728,7 +6728,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
+ hdcp_update_display(
+ adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
+- new_con_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false,
++ new_con_state->hdcp_content_type,
+ new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
+ : false);
+ }
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 53e382bff54d..244a8e80334a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -90,7 +90,7 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+ unsigned int link_index,
+ struct amdgpu_dm_connector *aconnector,
+- bool disable_type1,
++ uint8_t content_type,
+ bool enable_encryption)
+ {
+ struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+@@ -108,9 +108,15 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+ memcpy(display, query.display, sizeof(struct mod_hdcp_display));
+ mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
+
++ hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
++
+ if (enable_encryption) {
+ display->adjust.disable = 0;
+- hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
++ if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0)
++ hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
++ else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1)
++ hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1;
++
+ schedule_delayed_work(&hdcp_w->property_validate_dwork,
+ msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+ } else {
+@@ -308,7 +314,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
+ display->adjust.disable = 1;
+ link->adjust.auth_delay = 2;
+
+- hdcp_update_display(hdcp_work, link_index, aconnector, false, false);
++ hdcp_update_display(hdcp_work, link_index, aconnector, DRM_MODE_HDCP_CONTENT_TYPE0, false);
+ }
+
+ struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index 71e121f037cb..6abde86bce4a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -57,7 +57,7 @@ struct hdcp_workqueue {
+ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+ unsigned int link_index,
+ struct amdgpu_dm_connector *aconnector,
+- bool disable_type1,
++ uint8_t content_type,
+ bool enable_encryption);
+
+ void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+index 94a0e5fa931b..e8043c903a84 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+@@ -570,7 +570,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
+ break;
+ } else if (input->link_integrity_check_dp != PASS) {
+ if (hdcp->connection.hdcp2_retry_count >= 1)
+- adjust->hdcp2.disable_type1 = 1;
++ adjust->hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
+ fail_and_restart_in_ms(0, &status, output);
+ break;
+ } else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index a9511612f426..2dd5feec8e6c 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -358,10 +358,13 @@ enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)
+
+ hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = display->index;
+
+- if (hdcp->connection.link.adjust.hdcp2.disable_type1)
++ if (hdcp->connection.link.adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_0)
+ hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
+ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE0;
+- else
++ else if (hdcp->connection.link.adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_1)
++ hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
++ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE1;
++ else if (hdcp->connection.link.adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_MAX)
+ hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
+ TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__MAX_SUPPORTED;
+
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+index 97ecbf5bfec1..ff2bb2bfbb53 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+@@ -158,12 +158,18 @@ struct mod_hdcp_link_adjustment_hdcp1 {
+ uint8_t reserved : 6;
+ };
+
++enum mod_hdcp_force_hdcp_type {
++ MOD_HDCP_FORCE_TYPE_MAX = 0,
++ MOD_HDCP_FORCE_TYPE_0,
++ MOD_HDCP_FORCE_TYPE_1
++};
++
+ struct mod_hdcp_link_adjustment_hdcp2 {
+ uint8_t disable : 1;
+- uint8_t disable_type1 : 1;
++ uint8_t force_type : 2;
+ uint8_t force_no_stored_km : 1;
+ uint8_t increase_h_prime_timeout: 1;
+- uint8_t reserved : 4;
++ uint8_t reserved : 3;
+ };
+
+ struct mod_hdcp_link_adjustment {
+@@ -185,6 +191,7 @@ struct mod_hdcp_trace {
+ enum mod_hdcp_encryption_status {
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
++ MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON,
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4509-drm-amd-display-Refactor-HDCP-encryption-status-upda.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4509-drm-amd-display-Refactor-HDCP-encryption-status-upda.patch
new file mode 100644
index 00000000..d7deda01
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4509-drm-amd-display-Refactor-HDCP-encryption-status-upda.patch
@@ -0,0 +1,94 @@
+From e3fa5bc34929d64e2706634adbd8a6c369a7bbbe Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 4 Sep 2019 16:52:20 -0400
+Subject: [PATCH 4509/4736] drm/amd/display: Refactor HDCP encryption status
+ update
+
+[Why]
+The old way was to poll PSP and update the properties. But due to a
+limitation in the PSP interface this doesn't work for MST.
+
+[How]
+According to PSP if set_encryption return success, the link is encrypted
+and the only way it will not be is if we get a link loss(which we handle
+already).
+
+So this method should be good enough to report HDCP status.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +--
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 18 ++++++++++++++----
+ .../gpu/drm/amd/display/modules/inc/mod_hdcp.h | 4 ++--
+ 3 files changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 244a8e80334a..f6864a51891a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -85,6 +85,7 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+ schedule_delayed_work(&hdcp_work->watchdog_timer_dwork,
+ msecs_to_jiffies(output.watchdog_timer_delay));
+
++ schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0));
+ }
+
+ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+@@ -234,8 +235,6 @@ static void event_property_validate(struct work_struct *work)
+ schedule_work(&hdcp_work->property_update_work);
+ }
+
+- schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+-
+ mutex_unlock(&hdcp_work->mutex);
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index 0f2f242710b3..cbb5e9c063ec 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -417,10 +417,20 @@ enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
+ query->trace = &hdcp->connection.trace;
+ query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+
+- if (is_hdcp1(hdcp))
+- mod_hdcp_hdcp1_get_link_encryption_status(hdcp, &query->encryption_status);
+- else if (is_hdcp2(hdcp))
+- mod_hdcp_hdcp2_get_link_encryption_status(hdcp, &query->encryption_status);
++ if (is_display_encryption_enabled(display)) {
++ if (is_hdcp1(hdcp)) {
++ query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON;
++ } else if (is_hdcp2(hdcp)) {
++ if (query->link->adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_0)
++ query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON;
++ else if (query->link->adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_1)
++ query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON;
++ else
++ query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON;
++ }
++ } else {
++ query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++ }
+
+ out:
+ return status;
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+index ff2bb2bfbb53..f2a0e1a064da 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+@@ -191,9 +191,9 @@ struct mod_hdcp_trace {
+ enum mod_hdcp_encryption_status {
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
+- MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON,
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
+- MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON
++ MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON,
++ MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON
+ };
+
+ /* per link events dm has to notify to hdcp module */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4510-drm-amd-display-add-and-use-defines-from-drm_hdcp.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4510-drm-amd-display-add-and-use-defines-from-drm_hdcp.h.patch
new file mode 100644
index 00000000..0c7d4f74
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4510-drm-amd-display-add-and-use-defines-from-drm_hdcp.h.patch
@@ -0,0 +1,242 @@
+From 33346f2afd0be41522106850c13d8c6d76721fc6 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 21 Oct 2019 14:40:55 -0400
+Subject: [PATCH 4510/4736] drm/amd/display: add and use defines from
+ drm_hdcp.h
+
+[Why]
+These defines/macros exist already no need to redefine them
+
+[How]
+Use the defines/macros from drm_hdcp.h
+
+-we share the rxstatus between HDMI and DP (2 bytes), But upstream
+defines/macros for HDMI are for 1 byte. So we need to create a separate
+rxstatus for HDMI
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 40 ++++++++-----------
+ .../display/modules/hdcp/hdcp1_execution.c | 22 +++++-----
+ .../display/modules/hdcp/hdcp2_execution.c | 24 +++++------
+ 3 files changed, 37 insertions(+), 49 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index 9887c5ea6d5f..bfb32afc1868 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -29,34 +29,28 @@
+ #include "mod_hdcp.h"
+ #include "hdcp_log.h"
+
+-#define BCAPS_READY_MASK 0x20
+-#define BCAPS_REPEATER_MASK 0x40
+-#define BSTATUS_DEVICE_COUNT_MASK 0X007F
+-#define BSTATUS_MAX_DEVS_EXCEEDED_MASK 0x0080
++#include <drm/drm_hdcp.h>
++#include <drm/drm_dp_helper.h>
++
++/* TODO:
++ * Replace below defines with these
++ *
++ * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
++ * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
++ * #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
++ * #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
++ * #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
++ *
++ * Currently we share rx_status between HDMI and DP, so we use 16bits
++ * The upstream defines work with 1bytes at a time. So we need to
++ * split the HDMI rxstatus into 2bytes before we can use usptream defs
++ */
++
+ #define BSTATUS_MAX_CASCADE_EXCEEDED_MASK 0x0800
+-#define BCAPS_HDCP_CAPABLE_MASK_DP 0x01
+-#define BCAPS_REPEATER_MASK_DP 0x02
+-#define BSTATUS_READY_MASK_DP 0x01
+-#define BSTATUS_R0_P_AVAILABLE_MASK_DP 0x02
+-#define BSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP 0x04
+-#define BSTATUS_REAUTH_REQUEST_MASK_DP 0x08
+-#define BINFO_DEVICE_COUNT_MASK_DP 0X007F
+-#define BINFO_MAX_DEVS_EXCEEDED_MASK_DP 0x0080
+ #define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP 0x0800
+-
+-#define VERSION_HDCP2_MASK 0x04
+ #define RXSTATUS_MSG_SIZE_MASK 0x03FF
+ #define RXSTATUS_READY_MASK 0x0400
+ #define RXSTATUS_REAUTH_REQUEST_MASK 0x0800
+-#define RXIDLIST_DEVICE_COUNT_LOWER_MASK 0xf0
+-#define RXIDLIST_DEVICE_COUNT_UPPER_MASK 0x01
+-#define RXCAPS_BYTE2_HDCP2_VERSION_DP 0x02
+-#define RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP 0x02
+-#define RXSTATUS_READY_MASK_DP 0x0001
+-#define RXSTATUS_H_P_AVAILABLE_MASK_DP 0x0002
+-#define RXSTATUS_PAIRING_AVAILABLE_MASK_DP 0x0004
+-#define RXSTATUS_REAUTH_REQUEST_MASK_DP 0x0008
+-#define RXSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP 0x0010
+
+ enum mod_hdcp_trans_input_result {
+ UNKNOWN = 0,
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+index 3db4a7da414f..4618abd6504f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -41,17 +41,17 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)
+ static inline enum mod_hdcp_status check_ksv_ready(struct mod_hdcp *hdcp)
+ {
+ if (is_dp_hdcp(hdcp))
+- return (hdcp->auth.msg.hdcp1.bstatus & BSTATUS_READY_MASK_DP) ?
++ return (hdcp->auth.msg.hdcp1.bstatus & DP_BSTATUS_READY) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY;
+- return (hdcp->auth.msg.hdcp1.bcaps & BCAPS_READY_MASK) ?
++ return (hdcp->auth.msg.hdcp1.bcaps & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY;
+ }
+
+ static inline enum mod_hdcp_status check_hdcp_capable_dp(struct mod_hdcp *hdcp)
+ {
+- return (hdcp->auth.msg.hdcp1.bcaps & BCAPS_HDCP_CAPABLE_MASK_DP) ?
++ return (hdcp->auth.msg.hdcp1.bcaps & DP_BCAPS_HDCP_CAPABLE) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE;
+ }
+@@ -61,7 +61,7 @@ static inline enum mod_hdcp_status check_r0p_available_dp(struct mod_hdcp *hdcp)
+ enum mod_hdcp_status status;
+ if (is_dp_hdcp(hdcp)) {
+ status = (hdcp->auth.msg.hdcp1.bstatus &
+- BSTATUS_R0_P_AVAILABLE_MASK_DP) ?
++ DP_BSTATUS_R0_PRIME_READY) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING;
+ } else {
+@@ -74,7 +74,7 @@ static inline enum mod_hdcp_status check_link_integrity_dp(
+ struct mod_hdcp *hdcp)
+ {
+ return (hdcp->auth.msg.hdcp1.bstatus &
+- BSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP) ?
++ DP_BSTATUS_LINK_FAILURE) ?
+ MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE :
+ MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -82,7 +82,7 @@ static inline enum mod_hdcp_status check_link_integrity_dp(
+ static inline enum mod_hdcp_status check_no_reauthentication_request_dp(
+ struct mod_hdcp *hdcp)
+ {
+- return (hdcp->auth.msg.hdcp1.bstatus & BSTATUS_REAUTH_REQUEST_MASK_DP) ?
++ return (hdcp->auth.msg.hdcp1.bstatus & DP_BSTATUS_REAUTH_REQ) ?
+ MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED :
+ MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -109,13 +109,11 @@ static inline enum mod_hdcp_status check_no_max_devs(struct mod_hdcp *hdcp)
+ enum mod_hdcp_status status;
+
+ if (is_dp_hdcp(hdcp))
+- status = (hdcp->auth.msg.hdcp1.binfo_dp &
+- BINFO_MAX_DEVS_EXCEEDED_MASK_DP) ?
++ status = DRM_HDCP_MAX_DEVICE_EXCEEDED(hdcp->auth.msg.hdcp1.binfo_dp) ?
+ MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE :
+ MOD_HDCP_STATUS_SUCCESS;
+ else
+- status = (hdcp->auth.msg.hdcp1.bstatus &
+- BSTATUS_MAX_DEVS_EXCEEDED_MASK) ?
++ status = DRM_HDCP_MAX_DEVICE_EXCEEDED(hdcp->auth.msg.hdcp1.bstatus) ?
+ MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE :
+ MOD_HDCP_STATUS_SUCCESS;
+ return status;
+@@ -124,8 +122,8 @@ static inline enum mod_hdcp_status check_no_max_devs(struct mod_hdcp *hdcp)
+ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
+ {
+ return is_dp_hdcp(hdcp) ?
+- (hdcp->auth.msg.hdcp1.binfo_dp & BINFO_DEVICE_COUNT_MASK_DP) :
+- (hdcp->auth.msg.hdcp1.bstatus & BSTATUS_DEVICE_COUNT_MASK);
++ DRM_HDCP_NUM_DOWNSTREAM(hdcp->auth.msg.hdcp1.binfo_dp) :
++ DRM_HDCP_NUM_DOWNSTREAM(hdcp->auth.msg.hdcp1.bstatus);
+ }
+
+ static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+index c93c8098d972..7513b3b3c353 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+@@ -30,7 +30,7 @@ static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp
+ uint8_t is_ready = 0;
+
+ if (is_dp_hdcp(hdcp))
+- is_ready = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK_DP) ? 1 : 0;
++ is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus) ? 1 : 0;
+ else
+ is_ready = ((hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK) &&
+ (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK)) ? 1 : 0;
+@@ -43,14 +43,12 @@ static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp)
+ enum mod_hdcp_status status;
+
+ if (is_dp_hdcp(hdcp))
+- status = ((hdcp->auth.msg.hdcp2.rxcaps_dp[2] &
+- RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP) &&
+- (hdcp->auth.msg.hdcp2.rxcaps_dp[0] ==
+- RXCAPS_BYTE2_HDCP2_VERSION_DP)) ?
++ status = (hdcp->auth.msg.hdcp2.rxcaps_dp[2] & HDCP_2_2_RX_CAPS_VERSION_VAL) &&
++ HDCP_2_2_DP_HDCP_CAPABLE(hdcp->auth.msg.hdcp2.rxcaps_dp[0]) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
+ else
+- status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi & VERSION_HDCP2_MASK) ?
++ status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi & HDCP_2_2_HDMI_SUPPORT_MASK) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
+ return status;
+@@ -62,8 +60,7 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ uint8_t ret = 0;
+
+ if (is_dp_hdcp(hdcp))
+- ret = (hdcp->auth.msg.hdcp2.rxstatus &
+- RXSTATUS_REAUTH_REQUEST_MASK_DP) ?
++ ret = HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus) ?
+ MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
+ MOD_HDCP_STATUS_SUCCESS;
+ else
+@@ -76,8 +73,7 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ static inline enum mod_hdcp_status check_link_integrity_failure_dp(
+ struct mod_hdcp *hdcp)
+ {
+- return (hdcp->auth.msg.hdcp2.rxstatus &
+- RXSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP) ?
++ return HDCP_2_2_DP_RXSTATUS_LINK_FAILED(hdcp->auth.msg.hdcp2.rxstatus) ?
+ MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE :
+ MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -111,7 +107,7 @@ static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)
+ goto out;
+
+ if (is_dp_hdcp(hdcp)) {
+- status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_H_P_AVAILABLE_MASK_DP) ?
++ status = HDCP_2_2_DP_RXSTATUS_H_PRIME(hdcp->auth.msg.hdcp2.rxstatus) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
+ } else {
+@@ -134,7 +130,7 @@ static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)
+ goto out;
+
+ if (is_dp_hdcp(hdcp)) {
+- status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_PAIRING_AVAILABLE_MASK_DP) ?
++ status = HDCP_2_2_DP_RXSTATUS_PAIRING(hdcp->auth.msg.hdcp2.rxstatus) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
+ } else {
+@@ -197,8 +193,8 @@ static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)
+
+ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
+ {
+- return ((hdcp->auth.msg.hdcp2.rx_id_list[2] & RXIDLIST_DEVICE_COUNT_LOWER_MASK) >> 4) +
+- ((hdcp->auth.msg.hdcp2.rx_id_list[1] & RXIDLIST_DEVICE_COUNT_UPPER_MASK) << 4);
++ return HDCP_2_2_DEV_COUNT_LO(hdcp->auth.msg.hdcp2.rx_id_list[2]) +
++ (HDCP_2_2_DEV_COUNT_HI(hdcp->auth.msg.hdcp2.rx_id_list[1]) << 4);
+ }
+
+ static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4511-drm-amd-display-use-drm-defines-for-MAX-CASCADE-MASK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4511-drm-amd-display-use-drm-defines-for-MAX-CASCADE-MASK.patch
new file mode 100644
index 00000000..20585ba3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4511-drm-amd-display-use-drm-defines-for-MAX-CASCADE-MASK.patch
@@ -0,0 +1,75 @@
+From 50a7be8911fff66f9b4a719d80aab7cf89967fc1 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 24 Oct 2019 16:07:43 -0400
+Subject: [PATCH 4511/4736] drm/amd/display: use drm defines for MAX CASCADE
+ MASK
+
+[Why]
+drm already has this define
+
+[How]
+drm Mask is 0x08 vs 0x0800. The reason is because drm mask
+works on a byte. ^^
+ =======||
+ ||
+Since the first byte is always zero we can ignore it and only check the
+second byte.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h | 4 ----
+ .../drm/amd/display/modules/hdcp/hdcp1_execution.c | 14 ++++++--------
+ 2 files changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index bfb32afc1868..f6bba487d1d4 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -35,8 +35,6 @@
+ /* TODO:
+ * Replace below defines with these
+ *
+- * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
+- * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
+ * #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
+ * #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
+ * #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
+@@ -46,8 +44,6 @@
+ * split the HDMI rxstatus into 2bytes before we can use usptream defs
+ */
+
+-#define BSTATUS_MAX_CASCADE_EXCEEDED_MASK 0x0800
+-#define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP 0x0800
+ #define RXSTATUS_MSG_SIZE_MASK 0x03FF
+ #define RXSTATUS_READY_MASK 0x0400
+ #define RXSTATUS_REAUTH_REQUEST_MASK 0x0800
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+index 4618abd6504f..4d11041a8c6f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -92,15 +92,13 @@ static inline enum mod_hdcp_status check_no_max_cascade(struct mod_hdcp *hdcp)
+ enum mod_hdcp_status status;
+
+ if (is_dp_hdcp(hdcp))
+- status = (hdcp->auth.msg.hdcp1.binfo_dp &
+- BINFO_MAX_CASCADE_EXCEEDED_MASK_DP) ?
+- MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE :
+- MOD_HDCP_STATUS_SUCCESS;
++ status = DRM_HDCP_MAX_CASCADE_EXCEEDED(hdcp->auth.msg.hdcp1.binfo_dp >> 8)
++ ? MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE
++ : MOD_HDCP_STATUS_SUCCESS;
+ else
+- status = (hdcp->auth.msg.hdcp1.bstatus &
+- BSTATUS_MAX_CASCADE_EXCEEDED_MASK) ?
+- MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE :
+- MOD_HDCP_STATUS_SUCCESS;
++ status = DRM_HDCP_MAX_CASCADE_EXCEEDED(hdcp->auth.msg.hdcp1.bstatus >> 8)
++ ? MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE
++ : MOD_HDCP_STATUS_SUCCESS;
+ return status;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4512-drm-amd-display-split-rxstatus-for-hdmi-and-dp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4512-drm-amd-display-split-rxstatus-for-hdmi-and-dp.patch
new file mode 100644
index 00000000..92731dd0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4512-drm-amd-display-split-rxstatus-for-hdmi-and-dp.patch
@@ -0,0 +1,196 @@
+From bb329a5c7eb0e2584576fe336b329f87d8066cec Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 24 Oct 2019 16:07:58 -0400
+Subject: [PATCH 4512/4736] drm/amd/display: split rxstatus for hdmi and dp
+
+[Why]
+Currently we share rxstatus between HDMI and DP, so we use 16bits
+The drm defines work with 1bytes at a time. So we need to
+split the HDMI rxstatus into 2bytes before we can use drm defines
+
+[How]
+-create rxstatus for dp and hdmi. rxstatus for hdmi is split into bytes
+using arrays.
+-use drm_hdcp defines for the remaining structs
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 20 ++---------
+ .../display/modules/hdcp/hdcp2_execution.c | 35 +++++++++++--------
+ .../drm/amd/display/modules/hdcp/hdcp_ddc.c | 2 +-
+ 3 files changed, 24 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index f6bba487d1d4..f98d3d9ecb6d 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -32,22 +32,6 @@
+ #include <drm/drm_hdcp.h>
+ #include <drm/drm_dp_helper.h>
+
+-/* TODO:
+- * Replace below defines with these
+- *
+- * #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
+- * #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
+- * #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
+- *
+- * Currently we share rx_status between HDMI and DP, so we use 16bits
+- * The upstream defines work with 1bytes at a time. So we need to
+- * split the HDMI rxstatus into 2bytes before we can use usptream defs
+- */
+-
+-#define RXSTATUS_MSG_SIZE_MASK 0x03FF
+-#define RXSTATUS_READY_MASK 0x0400
+-#define RXSTATUS_REAUTH_REQUEST_MASK 0x0800
+-
+ enum mod_hdcp_trans_input_result {
+ UNKNOWN = 0,
+ PASS,
+@@ -150,7 +134,7 @@ struct mod_hdcp_message_hdcp1 {
+ struct mod_hdcp_message_hdcp2 {
+ uint8_t hdcp2version_hdmi;
+ uint8_t rxcaps_dp[3];
+- uint16_t rxstatus;
++ uint8_t rxstatus[2];
+
+ uint8_t ake_init[12];
+ uint8_t ake_cert[534];
+@@ -167,7 +151,7 @@ struct mod_hdcp_message_hdcp2 {
+ uint8_t repeater_auth_stream_manage[68]; // 6 + 2 * 31
+ uint16_t stream_manage_size;
+ uint8_t repeater_auth_stream_ready[33];
+-
++ uint8_t rxstatus_dp;
+ uint8_t content_stream_type_dp[2];
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+index 7513b3b3c353..110c8620907b 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+@@ -30,10 +30,11 @@ static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp
+ uint8_t is_ready = 0;
+
+ if (is_dp_hdcp(hdcp))
+- is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus) ? 1 : 0;
++ is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus_dp) ? 1 : 0;
+ else
+- is_ready = ((hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK) &&
+- (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK)) ? 1 : 0;
++ is_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus[0]) &&
++ (HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++ hdcp->auth.msg.hdcp2.rxstatus[0])) ? 1 : 0;
+ return is_ready ? MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY;
+ }
+@@ -60,11 +61,11 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ uint8_t ret = 0;
+
+ if (is_dp_hdcp(hdcp))
+- ret = HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus) ?
++ ret = HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
+ MOD_HDCP_STATUS_SUCCESS;
+ else
+- ret = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_REAUTH_REQUEST_MASK) ?
++ ret = HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus[0]) ?
+ MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
+ MOD_HDCP_STATUS_SUCCESS;
+ return ret;
+@@ -73,7 +74,7 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ static inline enum mod_hdcp_status check_link_integrity_failure_dp(
+ struct mod_hdcp *hdcp)
+ {
+- return HDCP_2_2_DP_RXSTATUS_LINK_FAILED(hdcp->auth.msg.hdcp2.rxstatus) ?
++ return HDCP_2_2_DP_RXSTATUS_LINK_FAILED(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE :
+ MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -88,7 +89,8 @@ static enum mod_hdcp_status check_ake_cert_available(struct mod_hdcp *hdcp)
+ } else {
+ status = mod_hdcp_read_rxstatus(hdcp);
+ if (status == MOD_HDCP_STATUS_SUCCESS) {
+- size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++ hdcp->auth.msg.hdcp2.rxstatus[0];
+ status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_cert)) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING;
+@@ -107,11 +109,12 @@ static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)
+ goto out;
+
+ if (is_dp_hdcp(hdcp)) {
+- status = HDCP_2_2_DP_RXSTATUS_H_PRIME(hdcp->auth.msg.hdcp2.rxstatus) ?
++ status = HDCP_2_2_DP_RXSTATUS_H_PRIME(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
+ } else {
+- size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++ hdcp->auth.msg.hdcp2.rxstatus[0];
+ status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
+@@ -130,11 +133,12 @@ static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)
+ goto out;
+
+ if (is_dp_hdcp(hdcp)) {
+- status = HDCP_2_2_DP_RXSTATUS_PAIRING(hdcp->auth.msg.hdcp2.rxstatus) ?
++ status = HDCP_2_2_DP_RXSTATUS_PAIRING(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
+ } else {
+- size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++ hdcp->auth.msg.hdcp2.rxstatus[0];
+ status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
+@@ -161,7 +165,8 @@ static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp)
+ if (status != MOD_HDCP_STATUS_SUCCESS)
+ break;
+
+- size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++ hdcp->auth.msg.hdcp2.rxstatus[0];
+ status = (size == sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING;
+@@ -182,7 +187,8 @@ static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)
+ status = mod_hdcp_read_rxstatus(hdcp);
+ if (status != MOD_HDCP_STATUS_SUCCESS)
+ goto out;
+- size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++ size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++ hdcp->auth.msg.hdcp2.rxstatus[0];
+ status = (size == sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)) ?
+ MOD_HDCP_STATUS_SUCCESS :
+ MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING;
+@@ -234,7 +240,8 @@ static uint8_t process_rxstatus(struct mod_hdcp *hdcp,
+ sizeof(hdcp->auth.msg.hdcp2.rx_id_list);
+ else
+ hdcp->auth.msg.hdcp2.rx_id_list_size =
+- hdcp->auth.msg.hdcp2.rxstatus & 0x3FF;
++ HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++ hdcp->auth.msg.hdcp2.rxstatus[0];
+ }
+ out:
+ return (*status == MOD_HDCP_STATUS_SUCCESS);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+index 8059aff9911f..ff9d54812e62 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+@@ -390,7 +390,7 @@ enum mod_hdcp_status mod_hdcp_read_rxstatus(struct mod_hdcp *hdcp)
+
+ if (is_dp_hdcp(hdcp)) {
+ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
+- (uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,
++ &hdcp->auth.msg.hdcp2.rxstatus_dp,
+ 1);
+ } else {
+ status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4513-drm-amd-display-Fix-static-analysis-bug-in-validate_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4513-drm-amd-display-Fix-static-analysis-bug-in-validate_.patch
new file mode 100644
index 00000000..73c36f1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4513-drm-amd-display-Fix-static-analysis-bug-in-validate_.patch
@@ -0,0 +1,45 @@
+From e90602e57aacf7202229cb99d213ff0ce8954699 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 6 Nov 2019 14:58:45 -0500
+Subject: [PATCH 4513/4736] drm/amd/display: Fix static analysis bug in
+ validate_bksv
+
+[Why]
+static analysis throws the error below
+
+Out-of-bounds read (OVERRUN)
+Overrunning array of 5 bytes at byte offset 7 by dereferencing pointer
+(uint64_t *)hdcp->auth.msg.hdcp1.bksv.
+
+var n is going to contain r0p and bcaps. if they are non-zero the count
+will be wrong
+
+How]
+Use memcpy instead to avoid this.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+index 4d11041a8c6f..04845e43df15 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -27,9 +27,11 @@
+
+ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)
+ {
+- uint64_t n = *(uint64_t *)hdcp->auth.msg.hdcp1.bksv;
++ uint64_t n = 0;
+ uint8_t count = 0;
+
++ memcpy(&n, hdcp->auth.msg.hdcp1.bksv, sizeof(uint64_t));
++
+ while (n) {
+ count++;
+ n &= (n - 1);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4514-drm-amdkfd-remove-set-but-not-used-variable-top_dev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4514-drm-amdkfd-remove-set-but-not-used-variable-top_dev.patch
new file mode 100644
index 00000000..ad51cab5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4514-drm-amdkfd-remove-set-but-not-used-variable-top_dev.patch
@@ -0,0 +1,37 @@
+From d5fd1655587eb432b0d47243c678488f7253e6c4 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 11:20:25 +0800
+Subject: [PATCH 4514/4736] drm/amdkfd: remove set but not used variable
+ 'top_dev'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdkfd/kfd_iommu.c: In function kfd_iommu_device_init:
+drivers/gpu/drm/amd/amdkfd/kfd_iommu.c:65:30: warning: variable top_dev set but not used [-Wunused-but-set-variable]
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Fixes: 1ae99eab34f9 ("drm/amdkfd: Initialize HSA_CAP_ATS_PRESENT capability in topology codes")
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_iommu.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+index 193e2835bd4d..8d871514671e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+@@ -62,9 +62,6 @@ int kfd_iommu_device_init(struct kfd_dev *kfd)
+ struct amd_iommu_device_info iommu_info;
+ unsigned int pasid_limit;
+ int err;
+- struct kfd_topology_device *top_dev;
+-
+- top_dev = kfd_topology_device_by_id(kfd->id);
+
+ if (!kfd->device_info->needs_iommu_device)
+ return 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4515-drm-amdgpu-vcn2.5-fix-the-enc-loop-with-hw-fini.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4515-drm-amdgpu-vcn2.5-fix-the-enc-loop-with-hw-fini.patch
new file mode 100644
index 00000000..01d0f98c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4515-drm-amdgpu-vcn2.5-fix-the-enc-loop-with-hw-fini.patch
@@ -0,0 +1,38 @@
+From 58b0eb3e79e22759ddfb375c4e1247a2b371b631 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 15 Nov 2019 17:10:34 -0500
+Subject: [PATCH 4515/4736] drm/amdgpu/vcn2.5: fix the enc loop with hw fini
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 98f423f30d2f..11dd533fb1ab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -268,7 +268,7 @@ static int vcn_v2_5_hw_fini(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring;
+- int i;
++ int i, j;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.harvest_config & (1 << i))
+@@ -280,8 +280,8 @@ static int vcn_v2_5_hw_fini(void *handle)
+
+ ring->sched.ready = false;
+
+- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+- ring = &adev->vcn.inst[i].ring_enc[i];
++ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
++ ring = &adev->vcn.inst[i].ring_enc[j];
+ ring->sched.ready = false;
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4516-drm-amdgpu-put-flush_dealyed_work-at-first.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4516-drm-amdgpu-put-flush_dealyed_work-at-first.patch
new file mode 100644
index 00000000..4d603188
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4516-drm-amdgpu-put-flush_dealyed_work-at-first.patch
@@ -0,0 +1,63 @@
+From 9852e1ef2fd04bb8469914ea973a173584b84deb Mon Sep 17 00:00:00 2001
+From: Yintian Tao <yttao@amd.com>
+Date: Mon, 18 Nov 2019 16:06:00 +0800
+Subject: [PATCH 4516/4736] drm/amdgpu: put flush_dealyed_work at first
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is one regression from 042f3d7b745cd76aa
+To put flush_delayed_work after adev->shutdown = true
+which will make amdgpu_ih_process not response the irq
+At last, all ib ring tests will be failed just like below
+
+[drm] amdgpu: finishing device.
+[drm] Fence fallback timer expired on ring gfx
+[drm] Fence fallback timer expired on ring comp_1.0.0
+[drm] Fence fallback timer expired on ring comp_1.1.0
+[drm] Fence fallback timer expired on ring comp_1.2.0
+[drm] Fence fallback timer expired on ring comp_1.3.0
+[drm] Fence fallback timer expired on ring comp_1.0.1
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.1.1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.2.1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.3.1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma0 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd_enc_0.0 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vce0 (-110).
+[drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110).
+
+v2: replace cancel_delayed_work_sync() with flush_delayed_work()
+
+Signed-off-by: Yintian Tao <yttao@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 7ccc9518c173..61fb27b4e89c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3119,9 +3119,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ int r;
+
+ DRM_INFO("amdgpu: finishing device.\n");
+- adev->shutdown = true;
+-
+ flush_delayed_work(&adev->delayed_init_work);
++ adev->shutdown = true;
+
+ /* disable all interrupts */
+ amdgpu_irq_disable_all(adev);
+@@ -3141,7 +3140,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ adev->firmware.gpu_info_fw = NULL;
+ }
+ adev->accel_working = false;
+- cancel_delayed_work_sync(&adev->delayed_init_work);
+ /* free i2c buses */
+ if (!amdgpu_device_has_dc_support(adev))
+ amdgpu_i2c_fini(adev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4517-drm-amdgpu-soc15-move-struct-definition-around-to-al.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4517-drm-amdgpu-soc15-move-struct-definition-around-to-al.patch
new file mode 100644
index 00000000..8c679e32
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4517-drm-amdgpu-soc15-move-struct-definition-around-to-al.patch
@@ -0,0 +1,38 @@
+From e82498dd48da16c5608bc8e76752ec9809c3ccfb Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 16:21:27 -0400
+Subject: [PATCH 4517/4736] drm/amdgpu/soc15: move struct definition around to
+ align with other soc15 asics
+
+Move reset_method next to reset callback to match the struct layout and
+the other definition in this file.
+
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index fea3222c40bc..67e84e8493b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1017,6 +1017,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ .read_bios_from_rom = &soc15_read_bios_from_rom,
+ .read_register = &soc15_read_register,
+ .reset = &soc15_asic_reset,
++ .reset_method = &soc15_asic_reset_method,
+ .set_vga_state = &soc15_vga_set_state,
+ .get_xclk = &soc15_get_xclk,
+ .set_uvd_clocks = &soc15_set_uvd_clocks,
+@@ -1029,7 +1030,6 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ .get_pcie_usage = &vega20_get_pcie_usage,
+ .need_reset_on_init = &soc15_need_reset_on_init,
+ .get_pcie_replay_count = &soc15_get_pcie_replay_count,
+- .reset_method = &soc15_asic_reset_method
+ };
+
+ static int soc15_common_early_init(void *handle)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4518-drm-amdgpu-nv-add-asic-func-for-fetching-vbios-from-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4518-drm-amdgpu-nv-add-asic-func-for-fetching-vbios-from-.patch
new file mode 100644
index 00000000..aaa0508d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4518-drm-amdgpu-nv-add-asic-func-for-fetching-vbios-from-.patch
@@ -0,0 +1,59 @@
+From 4baaff63c41abaecb938ac4c3b72ce6e6ce41bd9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 13 Nov 2019 14:27:54 -0500
+Subject: [PATCH 4518/4736] drm/amdgpu/nv: add asic func for fetching vbios
+ from rom directly
+
+Needed as a fallback if the vbios can't be fetched by other means.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 24 ++++++++++++++++++++++--
+ 1 file changed, 22 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 9163f3507a84..91b0482278c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -39,6 +39,7 @@
+ #include "gc/gc_10_1_0_sh_mask.h"
+ #include "hdp/hdp_5_0_0_offset.h"
+ #include "hdp/hdp_5_0_0_sh_mask.h"
++#include "smuio/smuio_11_0_0_offset.h"
+
+ #include "soc15.h"
+ #include "soc15_common.h"
+@@ -156,8 +157,27 @@ static bool nv_read_disabled_bios(struct amdgpu_device *adev)
+ static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
+ u8 *bios, u32 length_bytes)
+ {
+- /* TODO: will implement it when SMU header is available */
+- return false;
++ u32 *dw_ptr;
++ u32 i, length_dw;
++
++ if (bios == NULL)
++ return false;
++ if (length_bytes == 0)
++ return false;
++ /* APU vbios image is part of sbios image */
++ if (adev->flags & AMD_IS_APU)
++ return false;
++
++ dw_ptr = (u32 *)bios;
++ length_dw = ALIGN(length_bytes, 4) / 4;
++
++ /* set rom index to 0 */
++ WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
++ /* read out the rom data */
++ for (i = 0; i < length_dw; i++)
++ dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
++
++ return true;
+ }
+
+ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4519-drm-amdgpu-fix-bad-DMA-from-INTERRUPT_CNTL2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4519-drm-amdgpu-fix-bad-DMA-from-INTERRUPT_CNTL2.patch
new file mode 100644
index 00000000..1dec60b5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4519-drm-amdgpu-fix-bad-DMA-from-INTERRUPT_CNTL2.patch
@@ -0,0 +1,37 @@
+From f7dfb5fae746cff572f21503242b9004792d9790 Mon Sep 17 00:00:00 2001
+From: Sam Bobroff <sbobroff@linux.ibm.com>
+Date: Mon, 18 Nov 2019 10:53:54 +1100
+Subject: [PATCH 4519/4736] drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2
+
+The INTERRUPT_CNTL2 register expects a valid DMA address, but is
+currently set with a GPU MC address. This can cause problems on
+systems that detect the resulting DMA read from an invalid address
+(found on a Power8 guest).
+
+Instead, use the DMA address of the dummy page because it will always
+be safe.
+
+Fixes: 27ae10641e9c ("drm/amdgpu: add interupt handler implementation for si v3")
+Signed-off-by: Sam Bobroff <sbobroff@linux.ibm.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
+index 8c50c9cab455..28e04fe0ed33 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
+@@ -62,7 +62,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
+ u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
+
+ si_ih_disable_interrupts(adev);
+- WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
++ /* set dummy read address to dummy page address */
++ WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ interrupt_cntl = RREG32(INTERRUPT_CNTL);
+ interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
+ interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch
new file mode 100644
index 00000000..5aac7746
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch
@@ -0,0 +1,124 @@
+From 9a383d04b57ff6e3339a1d679458a3dbc02e23a9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 18 Nov 2019 12:21:26 -0500
+Subject: [PATCH 4520/4736] Revert "drm/amdgpu: don't read registers if gfxoff
+ is enabled (v2)"
+
+This reverts commit 5e49d6f654c569c2de920babbaf5cf7c4c4a353f.
+
+Drop this workaround in favor of a better one.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 27 ++++++++++----------------
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++------------------
+ 2 files changed, 22 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 91b0482278c2..4a52e5d59807 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -221,25 +221,17 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
+ return val;
+ }
+
+-static int nv_get_register_value(struct amdgpu_device *adev,
++static uint32_t nv_get_register_value(struct amdgpu_device *adev,
+ bool indexed, u32 se_num,
+- u32 sh_num, u32 reg_offset,
+- u32 *value)
++ u32 sh_num, u32 reg_offset)
+ {
+ if (indexed) {
+- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+- return -EINVAL;
+- *value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
++ return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ } else {
+- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+- *value = adev->gfx.config.gb_addr_config;
+- } else {
+- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+- return -EINVAL;
+- *value = RREG32(reg_offset);
+- }
++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
++ return adev->gfx.config.gb_addr_config;
++ return RREG32(reg_offset);
+ }
+- return 0;
+ }
+
+ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -255,9 +247,10 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+ (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
+ continue;
+
+- return nv_get_register_value(adev,
+- nv_allowed_read_registers[i].grbm_indexed,
+- se_num, sh_num, reg_offset, value);
++ *value = nv_get_register_value(adev,
++ nv_allowed_read_registers[i].grbm_indexed,
++ se_num, sh_num, reg_offset);
++ return 0;
+ }
+ return -EINVAL;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 67e84e8493b8..a458dded99c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -364,27 +364,19 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
+ return val;
+ }
+
+-static int soc15_get_register_value(struct amdgpu_device *adev,
++static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
+ bool indexed, u32 se_num,
+- u32 sh_num, u32 reg_offset,
+- u32 *value)
++ u32 sh_num, u32 reg_offset)
+ {
+ if (indexed) {
+- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+- return -EINVAL;
+- *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
++ return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ } else {
+- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+- *value = adev->gfx.config.gb_addr_config;
+- } else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
+- *value = adev->gfx.config.db_debug2;
+- } else {
+- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+- return -EINVAL;
+- *value = RREG32(reg_offset);
+- }
++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
++ return adev->gfx.config.gb_addr_config;
++ else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
++ return adev->gfx.config.db_debug2;
++ return RREG32(reg_offset);
+ }
+- return 0;
+ }
+
+ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -400,9 +392,10 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+ + en->reg_offset))
+ continue;
+
+- return soc15_get_register_value(adev,
+- soc15_allowed_read_registers[i].grbm_indexed,
+- se_num, sh_num, reg_offset, value);
++ *value = soc15_get_register_value(adev,
++ soc15_allowed_read_registers[i].grbm_indexed,
++ se_num, sh_num, reg_offset);
++ return 0;
+ }
+ return -EINVAL;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4521-drm-amdgpu-remove-not-needed-memset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4521-drm-amdgpu-remove-not-needed-memset.patch
new file mode 100644
index 00000000..a445cbff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4521-drm-amdgpu-remove-not-needed-memset.patch
@@ -0,0 +1,31 @@
+From d4f6653700813610901bac4467378a33e43ef68f Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 18 Nov 2019 17:00:31 +0800
+Subject: [PATCH 4521/4736] drm/amdgpu: remove not needed memset
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c:64:13-31: WARNING: dma_alloc_coherent use in ih -> ring already zeroes out memory, so memset is not needed
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+index 934dfdcb4e73..d922187d91f5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+@@ -65,7 +65,6 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+ if (ih->ring == NULL)
+ return -ENOMEM;
+
+- memset((void *)ih->ring, 0, ih->ring_size + 8);
+ ih->gpu_addr = dma_addr;
+ ih->wptr_addr = dma_addr + ih->ring_size;
+ ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4522-drm-amdgpu-expand-sdma-copy_buffer-interface-with-tm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4522-drm-amdgpu-expand-sdma-copy_buffer-interface-with-tm.patch
new file mode 100644
index 00000000..6b7d0bef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4522-drm-amdgpu-expand-sdma-copy_buffer-interface-with-tm.patch
@@ -0,0 +1,157 @@
+From 142541f86444a33597f842aced7388bbd9698604 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 15 Oct 2019 15:37:48 +0800
+Subject: [PATCH 4522/4736] drm/amdgpu: expand sdma copy_buffer interface with
+ tmz parameter
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch expands sdma copy_buffer interface with tmz parameter.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 5 +++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++-
+ 8 files changed, 17 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+index 761ff8be6314..b3134655789f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+@@ -79,7 +79,8 @@ struct amdgpu_buffer_funcs {
+ /* dst addr in bytes */
+ uint64_t dst_offset,
+ /* number of byte to transfer */
+- uint32_t byte_count);
++ uint32_t byte_count,
++ bool tmz);
+
+ /* maximum bytes in a single operation */
+ uint32_t fill_max_bytes;
+@@ -97,7 +98,7 @@ struct amdgpu_buffer_funcs {
+ uint32_t byte_count);
+ };
+
+-#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
++#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
+ #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
+
+ struct amdgpu_sdma_instance *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index b5028af50cc2..ee5c8fec9375 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2343,7 +2343,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
+ dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
+ amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
+- dst_addr, num_bytes);
++ dst_addr, num_bytes, false);
+
+ amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+ WARN_ON(job->ibs[0].length_dw > num_dw);
+@@ -2414,7 +2414,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
+
+ amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
+- dst_offset, cur_size_in_bytes);
++ dst_offset, cur_size_in_bytes, false);
+
+ src_offset += cur_size_in_bytes;
+ dst_offset += cur_size_in_bytes;
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+index d42808b05971..6e52d6f86435 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+@@ -1311,7 +1311,8 @@ static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
+ static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+- uint32_t byte_count)
++ uint32_t byte_count,
++ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
+ ib->ptr[ib->length_dw++] = byte_count;
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+index 36196372e8db..c448e782fc4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+@@ -1197,7 +1197,8 @@ static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+- uint32_t byte_count)
++ uint32_t byte_count,
++ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+index 6d39544e7829..017ac444f8e7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -1635,7 +1635,8 @@ static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+- uint32_t byte_count)
++ uint32_t byte_count,
++ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 2653d3c6ddd3..fa9dd28ebd5a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2337,7 +2337,8 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+- uint32_t byte_count)
++ uint32_t byte_count,
++ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index ec47542e21b0..66e89bebe0ed 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1657,7 +1657,8 @@ static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+- uint32_t byte_count)
++ uint32_t byte_count,
++ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+index 3eeefd40dae0..2161769c6fec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+@@ -775,7 +775,8 @@ static void si_dma_set_irq_funcs(struct amdgpu_device *adev)
+ static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib,
+ uint64_t src_offset,
+ uint64_t dst_offset,
+- uint32_t byte_count)
++ uint32_t byte_count,
++ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
+ 1, 0, 0, byte_count);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4523-drm-amdgpu-expand-amdgpu_copy_buffer-interface-with-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4523-drm-amdgpu-expand-amdgpu_copy_buffer-interface-with-.patch
new file mode 100644
index 00000000..2a286a76
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4523-drm-amdgpu-expand-amdgpu_copy_buffer-interface-with-.patch
@@ -0,0 +1,117 @@
+From a9b88b455e2bcdfd22776bb1de9ed8345bc615d9 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 15 Oct 2019 15:45:23 +0800
+Subject: [PATCH 4523/4736] drm/amdgpu: expand amdgpu_copy_buffer interface
+ with tmz parameter
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch expands amdgpu_copy_buffer interface with tmz parameter.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +-
+ 5 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+index 0f2aeb41e5c8..3ac31e1febb7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+@@ -40,7 +40,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
+ for (i = 0; i < n; i++) {
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
+- false, false);
++ false, false, false);
+ if (r)
+ goto exit_do_move;
+ r = dma_fence_wait(fence, false);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index 1350666355e0..aaccf287141c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -785,7 +785,7 @@ int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
+
+ return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
+ amdgpu_bo_size(shadow), NULL, fence,
+- true, false);
++ true, false, false);
+ }
+
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+index 41d3142ef3cf..a8828570a526 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+@@ -124,7 +124,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ amdgpu_bo_kunmap(gtt_obj[i]);
+
+ r = amdgpu_copy_buffer(ring, gart_addr, vram_addr,
+- size, NULL, &fence, false, false);
++ size, NULL, &fence, false, false, false);
+
+ if (r) {
+ DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
+@@ -170,7 +170,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ amdgpu_bo_kunmap(vram_obj);
+
+ r = amdgpu_copy_buffer(ring, vram_addr, gart_addr,
+- size, NULL, &fence, false, false);
++ size, NULL, &fence, false, false, false);
+
+ if (r) {
+ DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index ee5c8fec9375..d93bfaca5daf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -487,7 +487,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+ }
+
+ r = amdgpu_copy_buffer(ring, from, to, cur_size,
+- resv, &next, false, true);
++ resv, &next, false, true, false);
+ if (r)
+ goto error;
+
+@@ -2373,7 +2373,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ uint64_t dst_offset, uint32_t byte_count,
+ struct reservation_object *resv,
+ struct dma_fence **fence, bool direct_submit,
+- bool vm_needs_flush)
++ bool vm_needs_flush, bool tmz)
+ {
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_job *job;
+@@ -2414,7 +2414,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
+
+ amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
+- dst_offset, cur_size_in_bytes, false);
++ dst_offset, cur_size_in_bytes, tmz);
+
+ src_offset += cur_size_in_bytes;
+ dst_offset += cur_size_in_bytes;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+index b92297987138..f8cd8adb3337 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+@@ -93,7 +93,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ uint64_t dst_offset, uint32_t byte_count,
+ struct reservation_object *resv,
+ struct dma_fence **fence, bool direct_submit,
+- bool vm_needs_flush);
++ bool vm_needs_flush, bool tmz);
+ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+ struct amdgpu_copy_mem *src,
+ struct amdgpu_copy_mem *dst,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4524-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4524-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
new file mode 100644
index 00000000..12c24dbf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4524-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
@@ -0,0 +1,36 @@
+From 35308892286076ad11b3c0297ae0178605f52005 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 15 Oct 2019 16:47:44 +0800
+Subject: [PATCH 4524/4736] drm/amdgpu: enable TMZ bit in sdma copy pkt for
+ sdma v4
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enable sdma TMZ mode via setting TMZ bit in sdma copy pkt
+for sdma v4
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index fa9dd28ebd5a..5a5d825f5cab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2341,7 +2341,8 @@ static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+- SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
++ SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
+ ib->ptr[ib->length_dw++] = byte_count - 1;
+ ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
+ ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4525-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4525-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
new file mode 100644
index 00000000..d3642b4d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4525-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
@@ -0,0 +1,32 @@
+From 5ab485e2af46cd114f85eaef65fd6190ef64cf9b Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 15 Nov 2019 16:18:03 +0800
+Subject: [PATCH 4525/4736] drm/amdgpu: enable TMZ bit in sdma copy pkt for
+ sdma v5
+
+Enable sdma TMZ mode via setting TMZ bit in sdma copy pkt
+for sdma v5.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 66e89bebe0ed..948e9a46da2d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1661,7 +1661,8 @@ static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ bool tmz)
+ {
+ ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+- SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++ SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
++ SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
+ ib->ptr[ib->length_dw++] = byte_count - 1;
+ ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
+ ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4526-drm-amdgpu-enable-TMZ-bit-in-FRAME_CONTROL-for-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4526-drm-amdgpu-enable-TMZ-bit-in-FRAME_CONTROL-for-gfx10.patch
new file mode 100644
index 00000000..6462a20c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4526-drm-amdgpu-enable-TMZ-bit-in-FRAME_CONTROL-for-gfx10.patch
@@ -0,0 +1,30 @@
+From 2c35b29c8a3d9ab6308d866262c5dc8c9fa5df04 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 15 Nov 2019 15:08:36 +0800
+Subject: [PATCH 4526/4736] drm/amdgpu: enable TMZ bit in FRAME_CONTROL for
+ gfx10
+
+This patch enables TMZ bit in FRAME_CONTROL for gfx10.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 9274bd4b6c68..678ad1b26535 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4596,7 +4596,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ gfx_v10_0_ring_emit_ce_meta(ring,
+ flags & AMDGPU_IB_PREEMPTED ? true : false);
+
+- gfx_v10_0_ring_emit_tmz(ring, true, false);
++ gfx_v10_0_ring_emit_tmz(ring, true, trusted);
+
+ dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
+ if (flags & AMDGPU_HAVE_CTX_SWITCH) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4527-drm-amdgpu-powerplay-fix-dereference-before-null-che.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4527-drm-amdgpu-powerplay-fix-dereference-before-null-che.patch
new file mode 100644
index 00000000..920f9549
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4527-drm-amdgpu-powerplay-fix-dereference-before-null-che.patch
@@ -0,0 +1,43 @@
+From f70d7dab0998e1e9af945550a69c3535835c82eb Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 15 Nov 2019 09:47:54 +0000
+Subject: [PATCH 4527/4736] drm/amdgpu/powerplay: fix dereference before null
+ check of pointer hwmgr
+
+The assignment of adev dereferences pointer hwmgr before hwmgr is null
+checked, hence there is a potential null pointer deference issue. Fix
+this by assigning adev after the null check.
+
+Addresses-Coverity: ("Dereference before null check")
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+index 72f2b09195dc..cf5043bbf748 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+@@ -81,7 +81,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
+
+ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ {
+- struct amdgpu_device *adev = hwmgr->adev;
++ struct amdgpu_device *adev;
+
+ if (!hwmgr)
+ return -EINVAL;
+@@ -96,6 +96,8 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ hwmgr_init_workload_prority(hwmgr);
+ hwmgr->gfxoff_state_changed_by_workload = false;
+
++ adev = hwmgr->adev;
++
+ switch (hwmgr->chip_family) {
+ case AMDGPU_FAMILY_CI:
+ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4528-drm-amd-powerplay-return-errno-code-to-caller-when-e.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4528-drm-amd-powerplay-return-errno-code-to-caller-when-e.patch
new file mode 100644
index 00000000..ce283ef4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4528-drm-amd-powerplay-return-errno-code-to-caller-when-e.patch
@@ -0,0 +1,43 @@
+From 3e7c55707c521fca516b611a8b862312e477cc69 Mon Sep 17 00:00:00 2001
+From: Chen Wandun <chenwandun@huawei.com>
+Date: Mon, 18 Nov 2019 16:03:34 +0800
+Subject: [PATCH 4528/4736] drm/amd/powerplay: return errno code to caller when
+ error occur
+
+return errno code to caller when error occur, and meanwhile
+remove gcc '-Wunused-but-set-variable' warning.
+
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c: In function vegam_populate_smc_boot_level:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:1364:6: warning: variable result set but not used [-Wunused-but-set-variable]
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Chen Wandun <chenwandun@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index 2068eb00d2f8..50896e9b2579 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -1371,11 +1371,16 @@ static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+ result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+ data->vbios_boot_state.sclk_bootup_value,
+ (uint32_t *)&(table->GraphicsBootLevel));
++ if (result)
++ return result;
+
+ result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+ data->vbios_boot_state.mclk_bootup_value,
+ (uint32_t *)&(table->MemoryBootLevel));
+
++ if (result)
++ return result;
++
+ table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
+ VOLTAGE_SCALE;
+ table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4529-drm-amd-powerplay-correct-swSMU-baco-reset-related-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4529-drm-amd-powerplay-correct-swSMU-baco-reset-related-s.patch
new file mode 100644
index 00000000..1b08056d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4529-drm-amd-powerplay-correct-swSMU-baco-reset-related-s.patch
@@ -0,0 +1,68 @@
+From 1e4f35f41e12e21e3787690d9ab6a52746c868f0 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 18 Nov 2019 17:04:24 +0800
+Subject: [PATCH 4529/4736] drm/amd/powerplay: correct swSMU baco reset related
+ settings
+
+Added bif doorbell interrupt setting and applied different
+settings for BACO reset for RAS recovery.
+
+Change-Id: I823b2d478699d469ecc7746e2a8fb1110a4a146f
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 30 ++++++++++++++++++++---
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 928877f73dfd..71e2bbe25cf6 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1667,6 +1667,10 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ {
+
+ struct smu_baco_context *smu_baco = &smu->smu_baco;
++ struct amdgpu_device *adev = smu->adev;
++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
++ uint32_t bif_doorbell_intr_cntl;
++ uint32_t data;
+ int ret = 0;
+
+ if (smu_v11_0_baco_get_state(smu) == state)
+@@ -1674,10 +1678,30 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+
+ mutex_lock(&smu_baco->mutex);
+
+- if (state == SMU_BACO_STATE_ENTER)
+- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
+- else
++ bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
++
++ if (state == SMU_BACO_STATE_ENTER) {
++ bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++ BIF_DOORBELL_INT_CNTL,
++ DOORBELL_INTERRUPT_DISABLE, 1);
++ WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++
++ if (!ras || !ras->supported) {
++ data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
++ data |= 0x80000000;
++ WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
++
++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0);
++ } else {
++ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1);
++ }
++ } else {
+ ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
++ bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++ BIF_DOORBELL_INT_CNTL,
++ DOORBELL_INTERRUPT_DISABLE, 0);
++ WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++ }
+ if (ret)
+ goto out;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4530-drm-amd-powerplay-add-Arcturus-baco-reset-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4530-drm-amd-powerplay-add-Arcturus-baco-reset-support.patch
new file mode 100644
index 00000000..3cc03ff1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4530-drm-amd-powerplay-add-Arcturus-baco-reset-support.patch
@@ -0,0 +1,90 @@
+From 3c0de548a406f11a7e39af0639c51771ee5cc29a Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 4 Nov 2019 17:31:29 +0800
+Subject: [PATCH 4530/4736] drm/amd/powerplay: add Arcturus baco reset support
+
+Enable baco reset support on Arcturus.
+
+Change-Id: I7b69016ee0d238e0fcb323aa10215e29924a6ca6
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 14 ++++++++++----
+ 3 files changed, 18 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index a458dded99c6..41724a368d76 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -558,6 +558,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
+ return AMD_RESET_METHOD_MODE2;
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
++ case CHIP_ARCTURUS:
+ soc15_asic_get_baco_capability(adev, &baco_reset);
+ break;
+ case CHIP_VEGA20:
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 6d1401b30aaf..06c331d1e3e7 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -495,6 +495,7 @@ static int arcturus_store_powerplay_table(struct smu_context *smu)
+ {
+ struct smu_11_0_powerplay_table *powerplay_table = NULL;
+ struct smu_table_context *table_context = &smu->smu_table;
++ struct smu_baco_context *smu_baco = &smu->smu_baco;
+ int ret = 0;
+
+ if (!table_context->power_play_table)
+@@ -507,6 +508,12 @@ static int arcturus_store_powerplay_table(struct smu_context *smu)
+
+ table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
+
++ mutex_lock(&smu_baco->mutex);
++ if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
++ powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
++ smu_baco->platform_support = true;
++ mutex_unlock(&smu_baco->mutex);
++
+ return ret;
+ }
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 71e2bbe25cf6..238d584805b3 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1641,7 +1641,9 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
+ if (!baco_support)
+ return false;
+
+- if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
++ /* Arcturus does not support this bit mask */
++ if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
++ !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
+ return false;
+
+ val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+@@ -1713,11 +1715,15 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+
+ int smu_v11_0_baco_reset(struct smu_context *smu)
+ {
++ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+
+- ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+- if (ret)
+- return ret;
++ /* Arcturus does not need this audio workaround */
++ if (adev->asic_type != CHIP_ARCTURUS) {
++ ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
++ if (ret)
++ return ret;
++ }
+
+ ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
+ if (ret)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4531-drm-amd-powerplay-add-missing-header-file-declaratio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4531-drm-amd-powerplay-add-missing-header-file-declaratio.patch
new file mode 100644
index 00000000..fa1970bc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4531-drm-amd-powerplay-add-missing-header-file-declaratio.patch
@@ -0,0 +1,40 @@
+From ca8db79cdb7fb6b91f9435e63b9fd1e064c845c6 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 19 Nov 2019 11:43:45 +0800
+Subject: [PATCH 4531/4736] drm/amd/powerplay: add missing header file
+ declaration
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This can fix the compile errors below:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function ‘smu_v11_0_baco_set_state’:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: error: implicit declaration of function ‘amdgpu_ras_get_context’ [-Werror=implicit-function-declaration]
+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ ^
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: warning: initialization makes pointer from integer without a cast [-Wint-conversion]
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1692:19: error: dereferencing pointer to incomplete type ‘struct amdgpu_ras’
+ if (!ras || !ras->supported) {
+
+Change-Id: I1242e64e82715774b8e2931530749782b9107e32
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 238d584805b3..52aadbaaabda 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -34,6 +34,7 @@
+ #include "soc15_common.h"
+ #include "atom.h"
+ #include "amd_pcie.h"
++#include "amdgpu_ras.h"
+
+ #include "asic_reg/thm/thm_11_0_2_offset.h"
+ #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4532-drm-amdgpu-add-psp-funcs-for-ring-write-pointer-read.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4532-drm-amdgpu-add-psp-funcs-for-ring-write-pointer-read.patch
new file mode 100644
index 00000000..597ca5c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4532-drm-amdgpu-add-psp-funcs-for-ring-write-pointer-read.patch
@@ -0,0 +1,217 @@
+From 5a274a9eba4f444bec6d0550400b726deb5ce4e4 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 17:13:56 +0800
+Subject: [PATCH 4532/4736] drm/amdgpu: add psp funcs for ring write pointer
+ read/write
+
+The ring write pointer regsiter update is the only part that
+is IP specific ones in psp_cmd_submit function.
+
+Add two callbacks for wptr read/write so that we unify the
+psp_cmd_submit function for all the ASICs.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 +++++
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 26 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 26 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 27 +++++++++++++++++++++++++
+ 5 files changed, 100 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 09c5474ebcc3..d5620c46f3fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -116,6 +116,8 @@ struct psp_funcs
+ int (*mem_training_init)(struct psp_context *psp);
+ void (*mem_training_fini)(struct psp_context *psp);
+ int (*mem_training)(struct psp_context *psp, uint32_t ops);
++ uint32_t (*ring_get_wptr)(struct psp_context *psp);
++ void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
+ };
+
+ #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
+@@ -346,6 +348,9 @@ struct amdgpu_psp_funcs {
+ ((psp)->funcs->ras_cure_posion ? \
+ (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
+
++#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
++#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
++
+ extern const struct amd_ip_funcs psp_ip_funcs;
+
+ extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index ed8beff02e62..b8a461d46cb5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -404,6 +404,20 @@ static int psp_v10_0_mode1_reset(struct psp_context *psp)
+ return -EINVAL;
+ }
+
++static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
++{
++ struct amdgpu_device *adev = psp->adev;
++
++ return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++}
++
++static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++ struct amdgpu_device *adev = psp->adev;
++
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v10_0_funcs = {
+ .init_microcode = psp_v10_0_init_microcode,
+ .ring_init = psp_v10_0_ring_init,
+@@ -413,6 +427,8 @@ static const struct psp_funcs psp_v10_0_funcs = {
+ .cmd_submit = psp_v10_0_cmd_submit,
+ .compare_sram_data = psp_v10_0_compare_sram_data,
+ .mode1_reset = psp_v10_0_mode1_reset,
++ .ring_get_wptr = psp_v10_0_ring_get_wptr,
++ .ring_set_wptr = psp_v10_0_ring_set_wptr,
+ };
+
+ void psp_v10_0_set_psp_funcs(struct psp_context *psp)
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 0875ece1bea2..68f4cd7311a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -1076,6 +1076,30 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
+ return 0;
+ }
+
++static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
++{
++ uint32_t data;
++ struct amdgpu_device *adev = psp->adev;
++
++ if (psp_v11_0_support_vmr_ring(psp))
++ data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
++ else
++ data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++
++ return data;
++}
++
++static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++ struct amdgpu_device *adev = psp->adev;
++
++ if (psp_v11_0_support_vmr_ring(psp)) {
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
++ } else
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v11_0_funcs = {
+ .init_microcode = psp_v11_0_init_microcode,
+ .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
+@@ -1099,6 +1123,8 @@ static const struct psp_funcs psp_v11_0_funcs = {
+ .mem_training_init = psp_v11_0_memory_training_init,
+ .mem_training_fini = psp_v11_0_memory_training_fini,
+ .mem_training = psp_v11_0_memory_training,
++ .ring_get_wptr = psp_v11_0_ring_get_wptr,
++ .ring_set_wptr = psp_v11_0_ring_set_wptr,
+ };
+
+ void psp_v11_0_set_psp_funcs(struct psp_context *psp)
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+index 8f553f6f92d6..75b3f9d15a18 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -547,6 +547,30 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
+ return 0;
+ }
+
++static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
++{
++ uint32_t data;
++ struct amdgpu_device *adev = psp->adev;
++
++ if (psp_v12_0_support_vmr_ring(psp))
++ data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
++ else
++ data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++
++ return data;
++}
++
++static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++ struct amdgpu_device *adev = psp->adev;
++
++ if (psp_v12_0_support_vmr_ring(psp)) {
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
++ } else
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v12_0_funcs = {
+ .init_microcode = psp_v12_0_init_microcode,
+ .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
+@@ -558,6 +582,8 @@ static const struct psp_funcs psp_v12_0_funcs = {
+ .cmd_submit = psp_v12_0_cmd_submit,
+ .compare_sram_data = psp_v12_0_compare_sram_data,
+ .mode1_reset = psp_v12_0_mode1_reset,
++ .ring_get_wptr = psp_v12_0_ring_get_wptr,
++ .ring_set_wptr = psp_v12_0_ring_set_wptr,
+ };
+
+ void psp_v12_0_set_psp_funcs(struct psp_context *psp)
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index f652241aa71a..1de86e550a90 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -640,6 +640,31 @@ static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)
+ return false;
+ }
+
++static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
++{
++ uint32_t data;
++ struct amdgpu_device *adev = psp->adev;
++
++ if (psp_v3_1_support_vmr_ring(psp))
++ data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
++ else
++ data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++ return data;
++}
++
++static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++ struct amdgpu_device *adev = psp->adev;
++
++ if (psp_v3_1_support_vmr_ring(psp)) {
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
++ /* send interrupt to PSP for SRIOV ring write pointer update */
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
++ GFX_CTRL_CMD_ID_CONSUME_CMD);
++ } else
++ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v3_1_funcs = {
+ .init_microcode = psp_v3_1_init_microcode,
+ .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
+@@ -653,6 +678,8 @@ static const struct psp_funcs psp_v3_1_funcs = {
+ .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
+ .mode1_reset = psp_v3_1_mode1_reset,
+ .support_vmr_ring = psp_v3_1_support_vmr_ring,
++ .ring_get_wptr = psp_v3_1_ring_get_wptr,
++ .ring_set_wptr = psp_v3_1_ring_set_wptr,
+ };
+
+ void psp_v3_1_set_psp_funcs(struct psp_context *psp)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4533-drm-amdgpu-add-helper-func-for-psp-ring-cmd-submissi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4533-drm-amdgpu-add-helper-func-for-psp-ring-cmd-submissi.patch
new file mode 100644
index 00000000..2fe6deb2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4533-drm-amdgpu-add-helper-func-for-psp-ring-cmd-submissi.patch
@@ -0,0 +1,96 @@
+From 2c729023ab5775f2963046218e056d49528474a5 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 17:03:12 +0800
+Subject: [PATCH 4533/4736] drm/amdgpu: add helper func for psp ring cmd
+ submission
+
+Except for ring wptr update, the psp ring cmd submission
+function shouldn't be IP specific one. Create a common
+helper function to be shared for all the ASICs.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 50 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 4 ++
+ 2 files changed, 54 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 2b513e41ed3c..648cf9a49203 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1724,6 +1724,56 @@ int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
+ return psp_execute_np_fw_load(&adev->psp, &ucode);
+ }
+
++int psp_ring_cmd_submit(struct psp_context *psp,
++ uint64_t cmd_buf_mc_addr,
++ uint64_t fence_mc_addr,
++ int index)
++{
++ unsigned int psp_write_ptr_reg = 0;
++ struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
++ struct psp_ring *ring = &psp->km_ring;
++ struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
++ struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
++ ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
++ struct amdgpu_device *adev = psp->adev;
++ uint32_t ring_size_dw = ring->ring_size / 4;
++ uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
++
++ /* KM (GPCOM) prepare write pointer */
++ psp_write_ptr_reg = psp_ring_get_wptr(psp);
++
++ /* Update KM RB frame pointer to new frame */
++ /* write_frame ptr increments by size of rb_frame in bytes */
++ /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
++ if ((psp_write_ptr_reg % ring_size_dw) == 0)
++ write_frame = ring_buffer_start;
++ else
++ write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
++ /* Check invalid write_frame ptr address */
++ if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
++ DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
++ ring_buffer_start, ring_buffer_end, write_frame);
++ DRM_ERROR("write_frame is pointing to address out of bounds\n");
++ return -EINVAL;
++ }
++
++ /* Initialize KM RB frame */
++ memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
++
++ /* Update KM RB frame */
++ write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
++ write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
++ write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
++ write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
++ write_frame->fence_value = index;
++ amdgpu_asic_flush_hdp(adev, NULL);
++
++ /* Update the write Pointer in DWORDs */
++ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
++ psp_ring_set_wptr(psp, psp_write_ptr_reg);
++ return 0;
++}
++
+ static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
+ enum AMDGPU_UCODE_ID ucode_type)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index d5620c46f3fc..482e7675b7da 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -377,4 +377,8 @@ int psp_rlc_autoload_start(struct psp_context *psp);
+ extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
+ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
+ uint32_t value);
++int psp_ring_cmd_submit(struct psp_context *psp,
++ uint64_t cmd_buf_mc_addr,
++ uint64_t fence_mc_addr,
++ int index);
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4534-drm-amdgpu-switch-to-common-helper-func-for-psp-cmd-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4534-drm-amdgpu-switch-to-common-helper-func-for-psp-cmd-.patch
new file mode 100644
index 00000000..0512e441
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4534-drm-amdgpu-switch-to-common-helper-func-for-psp-cmd-.patch
@@ -0,0 +1,359 @@
+From 194ee6fbff8c8a309fd7fd3be75bade3420ede60 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 17:39:55 +0800
+Subject: [PATCH 4534/4736] drm/amdgpu: switch to common helper func for psp
+ cmd submission
+
+Drop all the IP specific cmd_submit callback function
+and use the common helper instead
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 ---
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 49 --------------------
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 58 ------------------------
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 58 ------------------------
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 60 -------------------------
+ 6 files changed, 1 insertion(+), 231 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 648cf9a49203..4ba444baf6db 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -158,7 +158,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
+ memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
+
+ index = atomic_inc_return(&psp->fence_value);
+- ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
++ ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
+ if (ret) {
+ atomic_dec(&psp->fence_value);
+ mutex_unlock(&psp->mutex);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 482e7675b7da..40594f27dab1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -94,9 +94,6 @@ struct psp_funcs
+ enum psp_ring_type ring_type);
+ int (*ring_destroy)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+- int (*cmd_submit)(struct psp_context *psp,
+- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+- int index);
+ bool (*compare_sram_data)(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ enum AMDGPU_UCODE_ID ucode_type);
+@@ -302,8 +299,6 @@ struct amdgpu_psp_funcs {
+ #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
+ #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
+ #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
+-#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
+- (psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
+ #define psp_compare_sram_data(psp, ucode, type) \
+ (psp)->funcs->compare_sram_data((psp), (ucode), (type))
+ #define psp_init_microcode(psp) \
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index b8a461d46cb5..e7d56c25b0f8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -227,54 +227,6 @@ static int psp_v10_0_ring_destroy(struct psp_context *psp,
+ return ret;
+ }
+
+-static int psp_v10_0_cmd_submit(struct psp_context *psp,
+- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+- int index)
+-{
+- unsigned int psp_write_ptr_reg = 0;
+- struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
+- struct psp_ring *ring = &psp->km_ring;
+- struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+- struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+- ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+- struct amdgpu_device *adev = psp->adev;
+- uint32_t ring_size_dw = ring->ring_size / 4;
+- uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+- /* KM (GPCOM) prepare write pointer */
+- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+- /* Update KM RB frame pointer to new frame */
+- if ((psp_write_ptr_reg % ring_size_dw) == 0)
+- write_frame = ring_buffer_start;
+- else
+- write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+- /* Check invalid write_frame ptr address */
+- if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+- DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+- ring_buffer_start, ring_buffer_end, write_frame);
+- DRM_ERROR("write_frame is pointing to address out of bounds\n");
+- return -EINVAL;
+- }
+-
+- /* Initialize KM RB frame */
+- memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+- /* Update KM RB frame */
+- write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+- write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+- write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+- write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+- write_frame->fence_value = index;
+- amdgpu_asic_flush_hdp(adev, NULL);
+-
+- /* Update the write Pointer in DWORDs */
+- psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+- return 0;
+-}
+-
+ static int
+ psp_v10_0_sram_map(struct amdgpu_device *adev,
+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -424,7 +376,6 @@ static const struct psp_funcs psp_v10_0_funcs = {
+ .ring_create = psp_v10_0_ring_create,
+ .ring_stop = psp_v10_0_ring_stop,
+ .ring_destroy = psp_v10_0_ring_destroy,
+- .cmd_submit = psp_v10_0_cmd_submit,
+ .compare_sram_data = psp_v10_0_compare_sram_data,
+ .mode1_reset = psp_v10_0_mode1_reset,
+ .ring_get_wptr = psp_v10_0_ring_get_wptr,
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 68f4cd7311a8..a12804d6bdce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -527,63 +527,6 @@ static int psp_v11_0_ring_destroy(struct psp_context *psp,
+ return ret;
+ }
+
+-static int psp_v11_0_cmd_submit(struct psp_context *psp,
+- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+- int index)
+-{
+- unsigned int psp_write_ptr_reg = 0;
+- struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
+- struct psp_ring *ring = &psp->km_ring;
+- struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+- struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+- ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+- struct amdgpu_device *adev = psp->adev;
+- uint32_t ring_size_dw = ring->ring_size / 4;
+- uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+- /* KM (GPCOM) prepare write pointer */
+- if (psp_v11_0_support_vmr_ring(psp))
+- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+- else
+- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+- /* Update KM RB frame pointer to new frame */
+- /* write_frame ptr increments by size of rb_frame in bytes */
+- /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+- if ((psp_write_ptr_reg % ring_size_dw) == 0)
+- write_frame = ring_buffer_start;
+- else
+- write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+- /* Check invalid write_frame ptr address */
+- if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+- DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+- ring_buffer_start, ring_buffer_end, write_frame);
+- DRM_ERROR("write_frame is pointing to address out of bounds\n");
+- return -EINVAL;
+- }
+-
+- /* Initialize KM RB frame */
+- memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+- /* Update KM RB frame */
+- write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+- write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+- write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+- write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+- write_frame->fence_value = index;
+- amdgpu_asic_flush_hdp(adev, NULL);
+-
+- /* Update the write Pointer in DWORDs */
+- psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+- if (psp_v11_0_support_vmr_ring(psp)) {
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
+- } else
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+- return 0;
+-}
+-
+ static int
+ psp_v11_0_sram_map(struct amdgpu_device *adev,
+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -1109,7 +1052,6 @@ static const struct psp_funcs psp_v11_0_funcs = {
+ .ring_create = psp_v11_0_ring_create,
+ .ring_stop = psp_v11_0_ring_stop,
+ .ring_destroy = psp_v11_0_ring_destroy,
+- .cmd_submit = psp_v11_0_cmd_submit,
+ .compare_sram_data = psp_v11_0_compare_sram_data,
+ .mode1_reset = psp_v11_0_mode1_reset,
+ .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+index 75b3f9d15a18..58d8b6d732e8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -334,63 +334,6 @@ static int psp_v12_0_ring_destroy(struct psp_context *psp,
+ return ret;
+ }
+
+-static int psp_v12_0_cmd_submit(struct psp_context *psp,
+- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+- int index)
+-{
+- unsigned int psp_write_ptr_reg = 0;
+- struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
+- struct psp_ring *ring = &psp->km_ring;
+- struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+- struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+- ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+- struct amdgpu_device *adev = psp->adev;
+- uint32_t ring_size_dw = ring->ring_size / 4;
+- uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+- /* KM (GPCOM) prepare write pointer */
+- if (psp_v12_0_support_vmr_ring(psp))
+- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+- else
+- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+- /* Update KM RB frame pointer to new frame */
+- /* write_frame ptr increments by size of rb_frame in bytes */
+- /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+- if ((psp_write_ptr_reg % ring_size_dw) == 0)
+- write_frame = ring_buffer_start;
+- else
+- write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+- /* Check invalid write_frame ptr address */
+- if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+- DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+- ring_buffer_start, ring_buffer_end, write_frame);
+- DRM_ERROR("write_frame is pointing to address out of bounds\n");
+- return -EINVAL;
+- }
+-
+- /* Initialize KM RB frame */
+- memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+- /* Update KM RB frame */
+- write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+- write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+- write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+- write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+- write_frame->fence_value = index;
+- amdgpu_asic_flush_hdp(adev, NULL);
+-
+- /* Update the write Pointer in DWORDs */
+- psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+- if (psp_v12_0_support_vmr_ring(psp)) {
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
+- } else
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+- return 0;
+-}
+-
+ static int
+ psp_v12_0_sram_map(struct amdgpu_device *adev,
+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -579,7 +522,6 @@ static const struct psp_funcs psp_v12_0_funcs = {
+ .ring_create = psp_v12_0_ring_create,
+ .ring_stop = psp_v12_0_ring_stop,
+ .ring_destroy = psp_v12_0_ring_destroy,
+- .cmd_submit = psp_v12_0_cmd_submit,
+ .compare_sram_data = psp_v12_0_compare_sram_data,
+ .mode1_reset = psp_v12_0_mode1_reset,
+ .ring_get_wptr = psp_v12_0_ring_get_wptr,
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index 1de86e550a90..839806cf1c6a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -408,65 +408,6 @@ static int psp_v3_1_ring_destroy(struct psp_context *psp,
+ return ret;
+ }
+
+-static int psp_v3_1_cmd_submit(struct psp_context *psp,
+- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+- int index)
+-{
+- unsigned int psp_write_ptr_reg = 0;
+- struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
+- struct psp_ring *ring = &psp->km_ring;
+- struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+- struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+- ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+- struct amdgpu_device *adev = psp->adev;
+- uint32_t ring_size_dw = ring->ring_size / 4;
+- uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+- /* KM (GPCOM) prepare write pointer */
+- if (psp_v3_1_support_vmr_ring(psp))
+- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+- else
+- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+- /* Update KM RB frame pointer to new frame */
+- /* write_frame ptr increments by size of rb_frame in bytes */
+- /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+- if ((psp_write_ptr_reg % ring_size_dw) == 0)
+- write_frame = ring_buffer_start;
+- else
+- write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+- /* Check invalid write_frame ptr address */
+- if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+- DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+- ring_buffer_start, ring_buffer_end, write_frame);
+- DRM_ERROR("write_frame is pointing to address out of bounds\n");
+- return -EINVAL;
+- }
+-
+- /* Initialize KM RB frame */
+- memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+- /* Update KM RB frame */
+- write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+- write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+- write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+- write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+- write_frame->fence_value = index;
+- amdgpu_asic_flush_hdp(adev, NULL);
+-
+- /* Update the write Pointer in DWORDs */
+- psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+- if (psp_v3_1_support_vmr_ring(psp)) {
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
+- /* send interrupt to PSP for SRIOV ring write pointer update */
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
+- GFX_CTRL_CMD_ID_CONSUME_CMD);
+- } else
+- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+- return 0;
+-}
+-
+ static int
+ psp_v3_1_sram_map(struct amdgpu_device *adev,
+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -673,7 +614,6 @@ static const struct psp_funcs psp_v3_1_funcs = {
+ .ring_create = psp_v3_1_ring_create,
+ .ring_stop = psp_v3_1_ring_stop,
+ .ring_destroy = psp_v3_1_ring_destroy,
+- .cmd_submit = psp_v3_1_cmd_submit,
+ .compare_sram_data = psp_v3_1_compare_sram_data,
+ .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
+ .mode1_reset = psp_v3_1_mode1_reset,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4535-drm-amdgpu-pull-ras-controller-int-status-only-when-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4535-drm-amdgpu-pull-ras-controller-int-status-only-when-.patch
new file mode 100644
index 00000000..0c6df126
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4535-drm-amdgpu-pull-ras-controller-int-status-only-when-.patch
@@ -0,0 +1,55 @@
+From 34280098d831c417043d90306fc61b25a39e0587 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 18:17:12 +0800
+Subject: [PATCH 4535/4736] drm/amdgpu: pull ras controller int status only
+ when ras enabled
+
+ras_controller_irq and athub_err_event_irq are only registered
+when PCIE_BIF ras is marked as supported. as the result, the driver
+also just need pull the int status in such case.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 48af4830a74f..4f6f128d13ae 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -52,6 +52,7 @@
+ #include "amdgpu_connectors.h"
+ #include "amdgpu_trace.h"
+ #include "amdgpu_amdkfd.h"
++#include "amdgpu_ras.h"
+
+ #include <linux/pm_runtime.h>
+
+@@ -159,13 +160,15 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
+ * register to check whether the interrupt is triggered or not, and properly
+ * ack the interrupt if it is there
+ */
+- if (adev->nbio.funcs &&
+- adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
+- adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
+-
+- if (adev->nbio.funcs &&
+- adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
+- adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
++ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
++ if (adev->nbio.funcs &&
++ adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
++ adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
++
++ if (adev->nbio.funcs &&
++ adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
++ adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
++ }
+
+ return ret;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4536-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4536-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
new file mode 100644
index 00000000..d50c8652
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4536-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
@@ -0,0 +1,200 @@
+From 7a2e755d51f2676519900b8e877298bf012374a1 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Wed, 13 Nov 2019 17:17:09 +0800
+Subject: [PATCH 4536/4736] drm/amd/powerplay: enable gpu_busy_percent sys
+ interface for renoir (v2)
+
+To get the value of gpu_busy_percent, it needs to realize
+get_current_activity_percent and get_metrics_table.
+The framework of renoir smu is different from old ones like raven. It
+needs to realize get_current_activity_percent and get_metrics_table in
+renoir_ppt.c like navi10.
+
+v2: remove unused variable (Alex)
+
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 4 +
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 76 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 33 ++++++++
+ 3 files changed, 113 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 1745e0146fba..44c65dd8850d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -62,6 +62,10 @@ int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
+
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+
++int smu_v12_0_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size);
++
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+
+ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 784903a313b7..b44ce143e895 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -139,6 +139,27 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ return mapping.map_to;
+ }
+
++static int renoir_get_metrics_table(struct smu_context *smu,
++ SmuMetrics_t *metrics_table)
++{
++ struct smu_table_context *smu_table= &smu->smu_table;
++ int ret = 0;
++
++ if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
++ ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++ (void *)smu_table->metrics_table, false);
++ if (ret) {
++ pr_info("Failed to export SMU metrics table!\n");
++ return ret;
++ }
++ smu_table->metrics_time = jiffies;
++ }
++
++ memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
++
++ return ret;
++}
++
+ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+@@ -154,6 +175,11 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ if (!smu_table->clocks_table)
+ return -ENOMEM;
+
++ smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
++ if (!smu_table->metrics_table)
++ return -ENOMEM;
++ smu_table->metrics_time = 0;
++
+ return 0;
+ }
+
+@@ -386,6 +412,32 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ return ret;
+ }
+
++static int renoir_get_current_activity_percent(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ uint32_t *value)
++{
++ int ret = 0;
++ SmuMetrics_t metrics;
++
++ if (!value)
++ return -EINVAL;
++
++ ret = renoir_get_metrics_table(smu, &metrics);
++ if (ret)
++ return ret;
++
++ switch (sensor) {
++ case AMDGPU_PP_SENSOR_GPU_LOAD:
++ *value = metrics.AverageGfxActivity;
++ break;
++ default:
++ pr_err("Invalid sensor for retrieving clock activity\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
+ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
+ {
+
+@@ -699,6 +751,29 @@ static int renoir_get_power_profile_mode(struct smu_context *smu,
+ return size;
+ }
+
++static int renoir_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size)
++{
++ int ret = 0;
++
++ if (!data || !size)
++ return -EINVAL;
++
++ mutex_lock(&smu->sensor_lock);
++ switch (sensor) {
++ case AMDGPU_PP_SENSOR_GPU_LOAD:
++ ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
++ *size = 4;
++ break;
++ default:
++ ret = smu_v12_0_read_sensor(smu, sensor, data, size);
++ }
++ mutex_unlock(&smu->sensor_lock);
++
++ return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_smu_msg_index = renoir_get_smu_msg_index,
+ .get_smu_table_index = renoir_get_smu_table_index,
+@@ -719,6 +794,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_dpm_clock_table = renoir_get_dpm_clock_table,
+ .set_watermarks_table = renoir_set_watermarks_table,
+ .get_power_profile_mode = renoir_get_power_profile_mode,
++ .read_sensor = renoir_read_sensor,
+ .check_fw_status = smu_v12_0_check_fw_status,
+ .check_fw_version = smu_v12_0_check_fw_version,
+ .powergate_sdma = smu_v12_0_powergate_sdma,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 18b24f954380..045167311ae8 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -223,6 +223,39 @@ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+
++int smu_v12_0_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size)
++{
++ int ret = 0;
++
++ if(!data || !size)
++ return -EINVAL;
++
++ switch (sensor) {
++ case AMDGPU_PP_SENSOR_GFX_MCLK:
++ ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
++ *size = 4;
++ break;
++ case AMDGPU_PP_SENSOR_GFX_SCLK:
++ ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
++ *size = 4;
++ break;
++ case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
++ *(uint32_t *)data = 0;
++ *size = 4;
++ break;
++ default:
++ ret = smu_common_read_sensor(smu, sensor, data, size);
++ break;
++ }
++
++ if (ret)
++ *size = 0;
++
++ return ret;
++}
++
+ /**
+ * smu_v12_0_get_gfxoff_status - get gfxoff status
+ *
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4537-drm-amdgpu-disable-gfxoff-when-using-register-read-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4537-drm-amdgpu-disable-gfxoff-when-using-register-read-i.patch
new file mode 100644
index 00000000..cf032b70
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4537-drm-amdgpu-disable-gfxoff-when-using-register-read-i.patch
@@ -0,0 +1,45 @@
+From 1914c0f1e3c19c49877c37ac9bdae96b1691993c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 14 Nov 2019 11:39:05 -0500
+Subject: [PATCH 4537/4736] drm/amdgpu: disable gfxoff when using register read
+ interface
+
+When gfxoff is enabled, accessing gfx registers via MMIO
+can lead to a hang.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
+Acked-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 3a7ea8e953f8..74ff077e89d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -678,15 +678,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ return -ENOMEM;
+ alloc_size = info->read_mmr_reg.count * sizeof(*regs);
+
+- for (i = 0; i < info->read_mmr_reg.count; i++)
++ amdgpu_gfx_off_ctrl(adev, false);
++ for (i = 0; i < info->read_mmr_reg.count; i++) {
+ if (amdgpu_asic_read_register(adev, se_num, sh_num,
+ info->read_mmr_reg.dword_offset + i,
+ &regs[i])) {
+ DRM_DEBUG_KMS("unallowed offset %#x\n",
+ info->read_mmr_reg.dword_offset + i);
+ kfree(regs);
++ amdgpu_gfx_off_ctrl(adev, true);
+ return -EFAULT;
+ }
++ }
++ amdgpu_gfx_off_ctrl(adev, true);
+ n = copy_to_user(out, regs, min(size, alloc_size));
+ kfree(regs);
+ return n ? -EFAULT : 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4538-drm-amdgpu-add-asic-callback-for-BACO-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4538-drm-amdgpu-add-asic-callback-for-BACO-support.patch
new file mode 100644
index 00000000..701103e5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4538-drm-amdgpu-add-asic-callback-for-BACO-support.patch
@@ -0,0 +1,41 @@
+From ac82736a44cd284962cf06b49c16c3f27746f3fd Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:01:35 -0500
+Subject: [PATCH 4538/4736] drm/amdgpu: add asic callback for BACO support
+
+BACO - Bus Active, Chip Off
+
+Used to check whether the device supports BACO. This will
+be used to enable runtime pm on devices which support BACO.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 9915f0472611..0e736a65d5dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -599,6 +599,8 @@ struct amdgpu_asic_funcs {
+ bool (*need_reset_on_init)(struct amdgpu_device *adev);
+ /* PCIe replay counter */
+ uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
++ /* device supports BACO */
++ bool (*supports_baco)(struct amdgpu_device *adev);
+ };
+
+ /*
+@@ -1168,6 +1170,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
+ #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
+ #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
+ #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
++#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
++
+ #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
+
+ /* Common functions */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4539-drm-amdgpu-add-supports_baco-callback-for-soc15-asic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4539-drm-amdgpu-add-supports_baco-callback-for-soc15-asic.patch
new file mode 100644
index 00000000..aae0cba9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4539-drm-amdgpu-add-supports_baco-callback-for-soc15-asic.patch
@@ -0,0 +1,70 @@
+From 72042998f27c98580d9b30c17eab504fad1389dc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 16:23:31 -0400
+Subject: [PATCH 4539/4736] drm/amdgpu: add supports_baco callback for soc15
+ asics. (v2)
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+v2: drop unrelated struct cleanup
+
+Reviewed-by: Evan Quan <evan.quan@amd.com> (v1)
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 41724a368d76..92230f1af2dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -601,6 +601,28 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
+ }
+ }
+
++static bool soc15_supports_baco(struct amdgpu_device *adev)
++{
++ bool baco_support;
++
++ switch (adev->asic_type) {
++ case CHIP_VEGA10:
++ case CHIP_VEGA12:
++ soc15_asic_get_baco_capability(adev, &baco_support);
++ break;
++ case CHIP_VEGA20:
++ if (adev->psp.sos_fw_version >= 0x80067)
++ soc15_asic_get_baco_capability(adev, &baco_support);
++ else
++ baco_support = false;
++ break;
++ default:
++ return false;
++ }
++
++ return baco_support;
++}
++
+ /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
+ u32 cntl_reg, u32 status_reg)
+ {
+@@ -1003,6 +1025,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
+ .get_pcie_usage = &soc15_get_pcie_usage,
+ .need_reset_on_init = &soc15_need_reset_on_init,
+ .get_pcie_replay_count = &soc15_get_pcie_replay_count,
++ .supports_baco = &soc15_supports_baco,
+ };
+
+ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+@@ -1024,6 +1047,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ .get_pcie_usage = &vega20_get_pcie_usage,
+ .need_reset_on_init = &soc15_need_reset_on_init,
+ .get_pcie_replay_count = &soc15_get_pcie_replay_count,
++ .supports_baco = &soc15_supports_baco,
+ };
+
+ static int soc15_common_early_init(void *handle)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4540-drm-amdgpu-add-supports_baco-callback-for-SI-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4540-drm-amdgpu-add-supports_baco-callback-for-SI-asics.patch
new file mode 100644
index 00000000..f212c60e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4540-drm-amdgpu-add-supports_baco-callback-for-SI-asics.patch
@@ -0,0 +1,43 @@
+From d2bae632b5d40c329461b88a0acf17144db05024 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:15:36 -0500
+Subject: [PATCH 4540/4736] drm/amdgpu: add supports_baco callback for SI
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Not supported.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/si.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
+index c8d645e45821..214d6cf4d295 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si.c
++++ b/drivers/gpu/drm/amd/amdgpu/si.c
+@@ -1196,6 +1196,11 @@ static int si_asic_reset(struct amdgpu_device *adev)
+ return 0;
+ }
+
++static bool si_asic_supports_baco(struct amdgpu_device *adev)
++{
++ return false;
++}
++
+ static enum amd_reset_method
+ si_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -1424,6 +1429,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
+ .get_pcie_usage = &si_get_pcie_usage,
+ .need_reset_on_init = &si_need_reset_on_init,
+ .get_pcie_replay_count = &si_get_pcie_replay_count,
++ .supports_baco = &si_asic_supports_baco,
+ };
+
+ static uint32_t si_get_rev_id(struct amdgpu_device *adev)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4541-drm-amdgpu-add-supports_baco-callback-for-CIK-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4541-drm-amdgpu-add-supports_baco-callback-for-CIK-asics.patch
new file mode 100644
index 00000000..24d4bb20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4541-drm-amdgpu-add-supports_baco-callback-for-CIK-asics.patch
@@ -0,0 +1,55 @@
+From 3e71111c486161a14d4129ee2b98cb22d4f7e626 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:16:15 -0500
+Subject: [PATCH 4541/4736] drm/amdgpu: add supports_baco callback for CIK
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index cc3d9f91a769..a5162412989b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1309,6 +1309,23 @@ static int cik_asic_pci_config_reset(struct amdgpu_device *adev)
+ return r;
+ }
+
++static bool cik_asic_supports_baco(struct amdgpu_device *adev)
++{
++ bool baco_support;
++
++ switch (adev->asic_type) {
++ case CHIP_BONAIRE:
++ case CHIP_HAWAII:
++ smu7_asic_get_baco_capability(adev, &baco_support);
++ break;
++ default:
++ baco_support = false;
++ break;
++ }
++
++ return baco_support;
++}
++
+ static enum amd_reset_method
+ cik_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -1898,6 +1915,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
+ .get_pcie_usage = &cik_get_pcie_usage,
+ .need_reset_on_init = &cik_need_reset_on_init,
+ .get_pcie_replay_count = &cik_get_pcie_replay_count,
++ .supports_baco = &cik_asic_supports_baco,
+ };
+
+ static int cik_common_early_init(void *handle)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4542-drm-amdgpu-add-supports_baco-callback-for-VI-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4542-drm-amdgpu-add-supports_baco-callback-for-VI-asics.patch
new file mode 100644
index 00000000..55340936
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4542-drm-amdgpu-add-supports_baco-callback-for-VI-asics.patch
@@ -0,0 +1,59 @@
+From 3f3118cc21cbe34225274412892b9e191f073159 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:17:05 -0500
+Subject: [PATCH 4542/4736] drm/amdgpu: add supports_baco callback for VI
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vi.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 34a466e785cb..14228bca071b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -743,6 +743,27 @@ static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
+ return r;
+ }
+
++static bool vi_asic_supports_baco(struct amdgpu_device *adev)
++{
++ bool baco_support;
++
++ switch (adev->asic_type) {
++ case CHIP_FIJI:
++ case CHIP_TONGA:
++ case CHIP_POLARIS10:
++ case CHIP_POLARIS11:
++ case CHIP_POLARIS12:
++ case CHIP_TOPAZ:
++ smu7_asic_get_baco_capability(adev, &baco_support);
++ break;
++ default:
++ baco_support = false;
++ break;
++ }
++
++ return baco_support;
++}
++
+ static enum amd_reset_method
+ vi_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -1114,6 +1135,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
+ .get_pcie_usage = &vi_get_pcie_usage,
+ .need_reset_on_init = &vi_need_reset_on_init,
+ .get_pcie_replay_count = &vi_get_pcie_replay_count,
++ .supports_baco = &vi_asic_supports_baco,
+ };
+
+ #define CZ_REV_BRISTOL(rev) \
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4543-drm-amdgpu-add-supports_baco-callback-for-NV-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4543-drm-amdgpu-add-supports_baco-callback-for-NV-asics.patch
new file mode 100644
index 00000000..b101211d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4543-drm-amdgpu-add-supports_baco-callback-for-NV-asics.patch
@@ -0,0 +1,48 @@
+From 670826463241f5b9990f453e52dc9c321a228b4b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 7 Nov 2019 18:12:17 -0500
+Subject: [PATCH 4543/4736] drm/amdgpu: add supports_baco callback for NV
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 4a52e5d59807..5cdd6528f011 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -314,6 +314,16 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
+ return ret;
+ }
+
++static bool nv_asic_supports_baco(struct amdgpu_device *adev)
++{
++ struct smu_context *smu = &adev->smu;
++
++ if (smu_baco_is_support(smu))
++ return true;
++ else
++ return false;
++}
++
+ static enum amd_reset_method
+ nv_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -619,6 +629,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+ .get_pcie_usage = &nv_get_pcie_usage,
+ .need_reset_on_init = &nv_need_reset_on_init,
+ .get_pcie_replay_count = &nv_get_pcie_replay_count,
++ .supports_baco = &nv_asic_supports_baco,
+ };
+
+ static int nv_common_early_init(void *handle)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4544-drm-amdgpu-add-a-amdgpu_device_supports_baco-helper.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4544-drm-amdgpu-add-a-amdgpu_device_supports_baco-helper.patch
new file mode 100644
index 00000000..890ae322
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4544-drm-amdgpu-add-a-amdgpu_device_supports_baco-helper.patch
@@ -0,0 +1,60 @@
+From 5074a9aaadd952d79318a24bedb2e81e470089bf Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 28 Oct 2019 14:47:38 -0400
+Subject: [PATCH 4544/4736] drm/amdgpu: add a amdgpu_device_supports_baco
+ helper
+
+BACO - Bus Active, Chip Off
+
+To check if a device supports BACO or not. This will be
+used in determining when to enable runtime pm.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++++++++++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 0e736a65d5dc..c73ef0017ca5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1189,6 +1189,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
+ const u32 array_size);
+
+ bool amdgpu_device_is_px(struct drm_device *dev);
++bool amdgpu_device_supports_baco(struct drm_device *dev);
+ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+ struct amdgpu_device *peer_adev);
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 61fb27b4e89c..ee045f328bf2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -153,6 +153,21 @@ bool amdgpu_device_is_px(struct drm_device *dev)
+ return false;
+ }
+
++/**
++ * amdgpu_device_supports_baco - Does the device support BACO
++ *
++ * @dev: drm_device pointer
++ *
++ * Returns true if the device supporte BACO,
++ * otherwise return false.
++ */
++bool amdgpu_device_supports_baco(struct drm_device *dev)
++{
++ struct amdgpu_device *adev = dev->dev_private;
++
++ return amdgpu_asic_supports_baco(adev);
++}
++
+ /**
+ * VRAM access helper functions.
+ *
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4545-drm-amdgpu-rename-amdgpu_device_is_px-to-amdgpu_devi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4545-drm-amdgpu-rename-amdgpu_device_is_px-to-amdgpu_devi.patch
new file mode 100644
index 00000000..999a8d96
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4545-drm-amdgpu-rename-amdgpu_device_is_px-to-amdgpu_devi.patch
@@ -0,0 +1,154 @@
+From 217481e7563fcefd8e806cb0bd39710623d6739e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:42:22 -0500
+Subject: [PATCH 4545/4736] drm/amdgpu: rename amdgpu_device_is_px to
+ amdgpu_device_supports_boco (v2)
+
+BACO - Bus Active, Chip Off
+BOCO - Bus Off, Chip Off
+
+To better match what we are checking for and to align with
+amdgpu_device_supports_baco.
+
+BOCO is used on PowerXpress/Hybrid Graphics systems and BACO
+is used on desktop dGPU boards.
+
+v2: fix typo in documentation
+
+Change-Id: Iba62fb630a8a1600c72e0da59524a3d99efc052a
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
+ 4 files changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index c73ef0017ca5..e0423a9efe14 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1188,7 +1188,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
+ const u32 *registers,
+ const u32 array_size);
+
+-bool amdgpu_device_is_px(struct drm_device *dev);
++bool amdgpu_device_supports_boco(struct drm_device *dev);
+ bool amdgpu_device_supports_baco(struct drm_device *dev);
+ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+ struct amdgpu_device *peer_adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ee045f328bf2..ac0dd28ca0a1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -137,14 +137,14 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
+ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
+
+ /**
+- * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
++ * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control
+ *
+ * @dev: drm_device pointer
+ *
+ * Returns true if the device is a dGPU with HG/PX power control,
+ * otherwise return false.
+ */
+-bool amdgpu_device_is_px(struct drm_device *dev)
++bool amdgpu_device_supports_boco(struct drm_device *dev)
+ {
+ struct amdgpu_device *adev = dev->dev_private;
+
+@@ -1091,7 +1091,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
+ {
+ struct drm_device *dev = pci_get_drvdata(pdev);
+
+- if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
++ if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF)
+ return;
+
+ if (state == VGA_SWITCHEROO_ON) {
+@@ -2919,7 +2919,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ * ignore it */
+ vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
+
+- if (amdgpu_device_is_px(ddev))
++ if (amdgpu_device_supports_boco(ddev))
+ runtime = true;
+ if (!pci_is_thunderbolt_attached(adev->pdev))
+ vga_switcheroo_register_client(adev->pdev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 298f78947048..3acdad16f0c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1200,7 +1200,7 @@ static int amdgpu_pmops_resume(struct device *dev)
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+ /* GPU comes up enabled by the bios on resume */
+- if (amdgpu_device_is_px(drm_dev)) {
++ if (amdgpu_device_supports_boco(drm_dev)) {
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+@@ -1248,7 +1248,7 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ int ret;
+
+- if (!amdgpu_device_is_px(drm_dev)) {
++ if (!amdgpu_device_supports_boco(drm_dev)) {
+ pm_runtime_forbid(dev);
+ return -EBUSY;
+ }
+@@ -1275,7 +1275,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ int ret;
+
+- if (!amdgpu_device_is_px(drm_dev))
++ if (!amdgpu_device_supports_boco(drm_dev))
+ return -EINVAL;
+
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+@@ -1300,7 +1300,7 @@ static int amdgpu_pmops_runtime_idle(struct device *dev)
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+ struct drm_crtc *crtc;
+
+- if (!amdgpu_device_is_px(drm_dev)) {
++ if (!amdgpu_device_supports_boco(drm_dev)) {
+ pm_runtime_forbid(dev);
+ return -EBUSY;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 74ff077e89d0..591558fc6a9f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -88,7 +88,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_request_full_gpu(adev, false);
+
+- if (amdgpu_device_is_px(dev)) {
++ if (amdgpu_device_supports_boco(dev)) {
+ pm_runtime_get_sync(dev->dev);
+ pm_runtime_forbid(dev->dev);
+ }
+@@ -177,7 +177,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ "Error during ACPI methods call\n");
+ }
+
+- if (amdgpu_device_is_px(dev)) {
++ if (amdgpu_device_supports_boco(dev)) {
+ dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
+ pm_runtime_use_autosuspend(dev->dev);
+ pm_runtime_set_autosuspend_delay(dev->dev, 5000);
+@@ -190,7 +190,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ out:
+ if (r) {
+ /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
+- if (adev->rmmio && amdgpu_device_is_px(dev))
++ if (adev->rmmio && amdgpu_device_supports_boco(dev))
+ pm_runtime_put_noidle(dev->dev);
+ amdgpu_driver_unload_kms(dev);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4546-drm-amdgpu-add-additional-boco-checks-to-runtime-sus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4546-drm-amdgpu-add-additional-boco-checks-to-runtime-sus.patch
new file mode 100644
index 00000000..075294bc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4546-drm-amdgpu-add-additional-boco-checks-to-runtime-sus.patch
@@ -0,0 +1,94 @@
+From 1d318cb06e47cb7a5235ba28549c45ec9f6d0c2c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:50:24 -0500
+Subject: [PATCH 4546/4736] drm/amdgpu: add additional boco checks to runtime
+ suspend/resume (v2)
+
+BACO - Bus Active, Chip Off
+BOCO - Bus Off, Chip Off
+
+We will take slightly different paths for boco and baco.
+
+v2: fold together two consecutive if clauses
+
+Change-Id: I2467c2906f855140f909cff322be587850c16a25
+Reviewed-by: Evan Quan <evan.quan@amd.com> (v1)
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 47 ++++++++++++++-----------
+ 1 file changed, 26 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 3acdad16f0c2..db41bdba954e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1253,18 +1253,21 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ return -EBUSY;
+ }
+
+- drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++ if (amdgpu_device_supports_boco(drm_dev))
++ drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+ drm_kms_helper_poll_disable(drm_dev);
+
+ ret = amdgpu_device_suspend(drm_dev, false, false);
+- pci_save_state(pdev);
+- pci_disable_device(pdev);
+- pci_ignore_hotplug(pdev);
+- if (amdgpu_is_atpx_hybrid())
+- pci_set_power_state(pdev, PCI_D3cold);
+- else if (!amdgpu_has_atpx_dgpu_power_cntl())
+- pci_set_power_state(pdev, PCI_D3hot);
+- drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
++ if (amdgpu_device_supports_boco(drm_dev)) {
++ pci_save_state(pdev);
++ pci_disable_device(pdev);
++ pci_ignore_hotplug(pdev);
++ if (amdgpu_is_atpx_hybrid())
++ pci_set_power_state(pdev, PCI_D3cold);
++ else if (!amdgpu_has_atpx_dgpu_power_cntl())
++ pci_set_power_state(pdev, PCI_D3hot);
++ drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
++ }
+
+ return 0;
+ }
+@@ -1278,20 +1281,22 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ if (!amdgpu_device_supports_boco(drm_dev))
+ return -EINVAL;
+
+- drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+-
+- if (amdgpu_is_atpx_hybrid() ||
+- !amdgpu_has_atpx_dgpu_power_cntl())
+- pci_set_power_state(pdev, PCI_D0);
+- pci_restore_state(pdev);
+- ret = pci_enable_device(pdev);
+- if (ret)
+- return ret;
+- pci_set_master(pdev);
+-
++ if (amdgpu_device_supports_boco(drm_dev)) {
++ drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++
++ if (amdgpu_is_atpx_hybrid() ||
++ !amdgpu_has_atpx_dgpu_power_cntl())
++ pci_set_power_state(pdev, PCI_D0);
++ pci_restore_state(pdev);
++ ret = pci_enable_device(pdev);
++ if (ret)
++ return ret;
++ pci_set_master(pdev);
++ }
+ ret = amdgpu_device_resume(drm_dev, false, false);
+ drm_kms_helper_poll_enable(drm_dev);
+- drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
++ if (amdgpu_device_supports_boco(drm_dev))
++ drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4547-drm-amdgpu-split-swSMU-baco_reset-into-enter-and-exi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4547-drm-amdgpu-split-swSMU-baco_reset-into-enter-and-exi.patch
new file mode 100644
index 00000000..dc2324a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4547-drm-amdgpu-split-swSMU-baco_reset-into-enter-and-exi.patch
@@ -0,0 +1,210 @@
+From 35d91a87c879ace6c7a7936a0b11a9a319f0268e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 28 Oct 2019 15:20:03 -0400
+Subject: [PATCH 4547/4736] drm/amdgpu: split swSMU baco_reset into enter and
+ exit
+
+BACO - Bus Active, Chip Off
+
+So we can use it for power savings rather than just reset.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 7 ++++++-
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++++++++--
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 20 ++++++++++++++++---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 ++-
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 ++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ++-
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 9 ++++++++-
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 3 ++-
+ 9 files changed, 51 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 5cdd6528f011..66af92e7dcdf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -352,7 +352,12 @@ static int nv_asic_reset(struct amdgpu_device *adev)
+ if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+ if (!adev->in_suspend)
+ amdgpu_inc_vram_lost(adev);
+- ret = smu_baco_reset(smu);
++ ret = smu_baco_enter(smu);
++ if (ret)
++ return ret;
++ ret = smu_baco_exit(smu);
++ if (ret)
++ return ret;
+ } else {
+ if (!adev->in_suspend)
+ amdgpu_inc_vram_lost(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 92230f1af2dd..805a92f87bf3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -510,9 +510,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+
+ if (is_support_sw_smu(adev)) {
+ struct smu_context *smu = &adev->smu;
++ int ret;
+
+- if (smu_baco_reset(smu))
+- return -EIO;
++ ret = smu_baco_enter(smu);
++ if (ret)
++ return ret;
++
++ ret = smu_baco_exit(smu);
++ if (ret)
++ return ret;
+ } else {
+ void *pp_handle = adev->powerplay.pp_handle;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 9483f5ff64e7..acbbafeea01c 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -2456,14 +2456,28 @@ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
+ return 0;
+ }
+
+-int smu_baco_reset(struct smu_context *smu)
++int smu_baco_enter(struct smu_context *smu)
+ {
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+
+- if (smu->ppt_funcs->baco_reset)
+- ret = smu->ppt_funcs->baco_reset(smu);
++ if (smu->ppt_funcs->baco_enter)
++ ret = smu->ppt_funcs->baco_enter(smu);
++
++ mutex_unlock(&smu->mutex);
++
++ return ret;
++}
++
++int smu_baco_exit(struct smu_context *smu)
++{
++ int ret = 0;
++
++ mutex_lock(&smu->mutex);
++
++ if (smu->ppt_funcs->baco_exit)
++ ret = smu->ppt_funcs->baco_exit(smu);
+
+ mutex_unlock(&smu->mutex);
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 06c331d1e3e7..cf3c31b0524c 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -2163,7 +2163,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ .baco_is_support= smu_v11_0_baco_is_support,
+ .baco_get_state = smu_v11_0_baco_get_state,
+ .baco_set_state = smu_v11_0_baco_set_state,
+- .baco_reset = smu_v11_0_baco_reset,
++ .baco_enter = smu_v11_0_baco_enter,
++ .baco_exit = smu_v11_0_baco_exit,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 5bac7efcd6ee..ada4a8dc4112 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -546,7 +546,8 @@ struct pptable_funcs {
+ bool (*baco_is_support)(struct smu_context *smu);
+ enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
+ int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
+- int (*baco_reset)(struct smu_context *smu);
++ int (*baco_enter)(struct smu_context *smu);
++ int (*baco_exit)(struct smu_context *smu);
+ int (*mode2_reset)(struct smu_context *smu);
+ int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
+@@ -628,7 +629,8 @@ bool smu_baco_is_support(struct smu_context *smu);
+
+ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
+
+-int smu_baco_reset(struct smu_context *smu);
++int smu_baco_enter(struct smu_context *smu);
++int smu_baco_exit(struct smu_context *smu);
+
+ int smu_mode2_reset(struct smu_context *smu);
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index e71445548c6f..716fcb274191 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -249,7 +249,8 @@ enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
+
+ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
+
+-int smu_v11_0_baco_reset(struct smu_context *smu);
++int smu_v11_0_baco_enter(struct smu_context *smu);
++int smu_v11_0_baco_exit(struct smu_context *smu);
+
+ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *min, uint32_t *max);
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 8d5f33baaa77..24765e813cc2 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -2109,7 +2109,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .baco_is_support= smu_v11_0_baco_is_support,
+ .baco_get_state = smu_v11_0_baco_get_state,
+ .baco_set_state = smu_v11_0_baco_set_state,
+- .baco_reset = smu_v11_0_baco_reset,
++ .baco_enter = smu_v11_0_baco_enter,
++ .baco_exit = smu_v11_0_baco_exit,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 52aadbaaabda..dd4437a9b3d0 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1714,7 +1714,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ return ret;
+ }
+
+-int smu_v11_0_baco_reset(struct smu_context *smu)
++int smu_v11_0_baco_enter(struct smu_context *smu)
+ {
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+@@ -1732,6 +1732,13 @@ int smu_v11_0_baco_reset(struct smu_context *smu)
+
+ msleep(10);
+
++ return ret;
++}
++
++int smu_v11_0_baco_exit(struct smu_context *smu)
++{
++ int ret = 0;
++
+ ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
+ if (ret)
+ return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 399697a2ad7f..83862544a45c 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3257,7 +3257,8 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ .baco_is_support= smu_v11_0_baco_is_support,
+ .baco_get_state = smu_v11_0_baco_get_state,
+ .baco_set_state = smu_v11_0_baco_set_state,
+- .baco_reset = smu_v11_0_baco_reset,
++ .baco_enter = smu_v11_0_baco_enter,
++ .baco_exit = smu_v11_0_baco_exit,
+ .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4548-drm-amdgpu-add-helpers-for-baco-entry-and-exit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4548-drm-amdgpu-add-helpers-for-baco-entry-and-exit.patch
new file mode 100644
index 00000000..59ef9498
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4548-drm-amdgpu-add-helpers-for-baco-entry-and-exit.patch
@@ -0,0 +1,106 @@
+From f98544ea9af75cdf57211c6a55b63dcf1ffeb999 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 12:33:09 -0500
+Subject: [PATCH 4548/4736] drm/amdgpu: add helpers for baco entry and exit
+
+BACO - Bus Active, Chip Off
+
+Will be used for runtime pm. Entry will enter the BACO
+state (chip off). Exit will exit the BACO state (chip on).
+
+Change-Id: I051a4b9996af9ee7c7639be65fbd5009a4379ab3
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 62 ++++++++++++++++++++++
+ 2 files changed, 64 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index e0423a9efe14..9679649082cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1192,7 +1192,8 @@ bool amdgpu_device_supports_boco(struct drm_device *dev);
+ bool amdgpu_device_supports_baco(struct drm_device *dev);
+ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+ struct amdgpu_device *peer_adev);
+-
++int amdgpu_device_baco_enter(struct drm_device *dev);
++int amdgpu_device_baco_exit(struct drm_device *dev);
+ /* atpx handler */
+ #if defined(CONFIG_VGA_SWITCHEROO)
+ void amdgpu_register_atpx_handler(void);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ac0dd28ca0a1..ebdf775ab9b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4333,3 +4333,65 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+ !(adev->gmc.aper_base & address_mask ||
+ aper_limit & address_mask);
+ }
++
++int amdgpu_device_baco_enter(struct drm_device *dev)
++{
++ struct amdgpu_device *adev = dev->dev_private;
++
++ if (!amdgpu_device_supports_baco(adev->ddev))
++ return -ENOTSUPP;
++
++ if (is_support_sw_smu(adev)) {
++ struct smu_context *smu = &adev->smu;
++ int ret;
++
++ ret = smu_baco_enter(smu);
++ if (ret)
++ return ret;
++
++ return 0;
++ } else {
++ void *pp_handle = adev->powerplay.pp_handle;
++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++ if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++ return -ENOENT;
++
++ /* enter BACO state */
++ if (pp_funcs->set_asic_baco_state(pp_handle, 1))
++ return -EIO;
++
++ return 0;
++ }
++}
++
++int amdgpu_device_baco_exit(struct drm_device *dev)
++{
++ struct amdgpu_device *adev = dev->dev_private;
++
++ if (!amdgpu_device_supports_baco(adev->ddev))
++ return -ENOTSUPP;
++
++ if (is_support_sw_smu(adev)) {
++ struct smu_context *smu = &adev->smu;
++ int ret;
++
++ ret = smu_baco_exit(smu);
++ if (ret)
++ return ret;
++
++ return 0;
++ } else {
++ void *pp_handle = adev->powerplay.pp_handle;
++ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++ if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++ return -ENOENT;
++
++ /* exit BACO state */
++ if (pp_funcs->set_asic_baco_state(pp_handle, 0))
++ return -EIO;
++
++ return 0;
++ }
++}
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4549-drm-amdgpu-add-baco-support-to-runtime-suspend-resum.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4549-drm-amdgpu-add-baco-support-to-runtime-suspend-resum.patch
new file mode 100644
index 00000000..8c3a8edd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4549-drm-amdgpu-add-baco-support-to-runtime-suspend-resum.patch
@@ -0,0 +1,53 @@
+From 7c67e9f1b6ee307d0470a82e31b21936d3724e4f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 12:54:12 -0500
+Subject: [PATCH 4549/4736] drm/amdgpu: add baco support to runtime
+ suspend/resume
+
+BACO - Bus Active, Chip Off
+
+This adds the necessary support to the runtime suspend
+and resume functions to handle boards that support
+baco.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index db41bdba954e..036e253def85 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1200,7 +1200,8 @@ static int amdgpu_pmops_resume(struct device *dev)
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+ /* GPU comes up enabled by the bios on resume */
+- if (amdgpu_device_supports_boco(drm_dev)) {
++ if (amdgpu_device_supports_boco(drm_dev) ||
++ amdgpu_device_supports_baco(drm_dev)) {
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+@@ -1267,6 +1268,8 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ else if (!amdgpu_has_atpx_dgpu_power_cntl())
+ pci_set_power_state(pdev, PCI_D3hot);
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
++ } else if (amdgpu_device_supports_baco(drm_dev)) {
++ amdgpu_device_baco_enter(drm_dev);
+ }
+
+ return 0;
+@@ -1292,6 +1295,8 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ if (ret)
+ return ret;
+ pci_set_master(pdev);
++ } else if (amdgpu_device_supports_baco(drm_dev)) {
++ amdgpu_device_baco_exit(drm_dev);
+ }
+ ret = amdgpu_device_resume(drm_dev, false, false);
+ drm_kms_helper_poll_enable(drm_dev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4550-drm-amdgpu-start-to-disentangle-boco-from-runtime-pm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4550-drm-amdgpu-start-to-disentangle-boco-from-runtime-pm.patch
new file mode 100644
index 00000000..bdfaf13b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4550-drm-amdgpu-start-to-disentangle-boco-from-runtime-pm.patch
@@ -0,0 +1,131 @@
+From 3f6b71254c91d80d5a77a0124ecb6a5587ec4b10 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 7 Nov 2019 18:13:14 -0500
+Subject: [PATCH 4550/4736] drm/amdgpu: start to disentangle boco from runtime
+ pm
+
+BACO - Bus Active, Chip Off
+BOCO - Bus Off, Chip Off
+
+We originally only supported runtime pm on PX/HG
+laptops so most of the runtime pm code looks for this.
+Add a new flag to check for runtime pm enablement and
+use this rather than checking for PX/HG.
+
+Change-Id: I09683aeef460c4a64ce904d0b21f8d949617a97c
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 ++++++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 13 ++++++++-----
+ 3 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 9679649082cb..ccb1fd7cd2b6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1035,6 +1035,8 @@ struct amdgpu_device {
+
+ /* device pstate */
+ int pstate;
++ /* enable runtime pm on the device */
++ bool runpm;
+ };
+
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 036e253def85..6957ef4ef514 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1247,9 +1247,10 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ {
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct drm_device *drm_dev = pci_get_drvdata(pdev);
++ struct amdgpu_device *adev = drm_dev->dev_private;
+ int ret;
+
+- if (!amdgpu_device_supports_boco(drm_dev)) {
++ if (!adev->runpm) {
+ pm_runtime_forbid(dev);
+ return -EBUSY;
+ }
+@@ -1279,9 +1280,10 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ {
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct drm_device *drm_dev = pci_get_drvdata(pdev);
++ struct amdgpu_device *adev = drm_dev->dev_private;
+ int ret;
+
+- if (!amdgpu_device_supports_boco(drm_dev))
++ if (!adev->runpm)
+ return -EINVAL;
+
+ if (amdgpu_device_supports_boco(drm_dev)) {
+@@ -1308,9 +1310,10 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ static int amdgpu_pmops_runtime_idle(struct device *dev)
+ {
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
++ struct amdgpu_device *adev = drm_dev->dev_private;
+ struct drm_crtc *crtc;
+
+- if (!amdgpu_device_supports_boco(drm_dev)) {
++ if (!adev->runpm) {
+ pm_runtime_forbid(dev);
+ return -EBUSY;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 591558fc6a9f..ab7697d7b70a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -88,7 +88,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_request_full_gpu(adev, false);
+
+- if (amdgpu_device_supports_boco(dev)) {
++ if (adev->runpm) {
+ pm_runtime_get_sync(dev->dev);
+ pm_runtime_forbid(dev->dev);
+ }
+@@ -147,14 +147,17 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ }
+ dev->dev_private = (void *)adev;
+
+- if ((amdgpu_runtime_pm != 0) &&
+- amdgpu_has_atpx() &&
++ if (amdgpu_has_atpx() &&
+ (amdgpu_is_atpx_hybrid() ||
+ amdgpu_has_atpx_dgpu_power_cntl()) &&
+ ((flags & AMD_IS_APU) == 0) &&
+ !pci_is_thunderbolt_attached(dev->pdev))
+ flags |= AMD_IS_PX;
+
++ if ((amdgpu_runtime_pm != 0) &&
++ (flags & AMD_IS_PX))
++ adev->runpm = true;
++
+ /* amdgpu_device_init should report only fatal error
+ * like memory allocation failure or iomapping failure,
+ * or memory manager initialization failure, it must
+@@ -177,7 +180,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ "Error during ACPI methods call\n");
+ }
+
+- if (amdgpu_device_supports_boco(dev)) {
++ if (adev->runpm) {
+ dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
+ pm_runtime_use_autosuspend(dev->dev);
+ pm_runtime_set_autosuspend_delay(dev->dev, 5000);
+@@ -190,7 +193,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ out:
+ if (r) {
+ /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
+- if (adev->rmmio && amdgpu_device_supports_boco(dev))
++ if (adev->rmmio && adev->runpm)
+ pm_runtime_put_noidle(dev->dev);
+ amdgpu_driver_unload_kms(dev);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4551-drm-amdgpu-disentangle-runtime-pm-and-vga_switcheroo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4551-drm-amdgpu-disentangle-runtime-pm-and-vga_switcheroo.patch
new file mode 100644
index 00000000..c9248ca9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4551-drm-amdgpu-disentangle-runtime-pm-and-vga_switcheroo.patch
@@ -0,0 +1,76 @@
+From a249a5a0231132509a586738be1e179f53737913 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 13:25:37 -0500
+Subject: [PATCH 4551/4736] drm/amdgpu: disentangle runtime pm and
+ vga_switcheroo
+
+Originally we only supported runtime pm on PX/HG laptops
+so vga_switcheroo and runtime pm are sort of entangled.
+
+Attempt to logically separate them.
+
+Change-Id: Ie7cfe18f55e79557018f004ffbb5ce66822c3efe
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 ++++++++++++--------
+ 1 file changed, 12 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ebdf775ab9b0..62d088a4840b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2749,7 +2749,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ uint32_t flags)
+ {
+ int r, i;
+- bool runtime = false;
++ bool boco = false;
+ u32 max_MBps;
+
+ adev->shutdown = false;
+@@ -2920,11 +2920,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
+
+ if (amdgpu_device_supports_boco(ddev))
+- runtime = true;
+- if (!pci_is_thunderbolt_attached(adev->pdev))
++ boco = true;
++ if (amdgpu_has_atpx() &&
++ (amdgpu_is_atpx_hybrid() ||
++ amdgpu_has_atpx_dgpu_power_cntl()))
+ vga_switcheroo_register_client(adev->pdev,
+- &amdgpu_switcheroo_ops, runtime);
+- if (runtime)
++ &amdgpu_switcheroo_ops, boco);
++ if (boco)
+ vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
+
+ if (amdgpu_emu_mode == 1) {
+@@ -3115,7 +3117,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+
+ failed:
+ amdgpu_vf_error_trans_all(adev);
+- if (runtime)
++ if (boco)
+ vga_switcheroo_fini_domain_pm_ops(adev->dev);
+
+ return r;
+@@ -3164,9 +3166,11 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+
+ kfree(adev->bios);
+ adev->bios = NULL;
+- if (!pci_is_thunderbolt_attached(adev->pdev))
++ if (amdgpu_has_atpx() &&
++ (amdgpu_is_atpx_hybrid() ||
++ amdgpu_has_atpx_dgpu_power_cntl()))
+ vga_switcheroo_unregister_client(adev->pdev);
+- if (adev->flags & AMD_IS_PX)
++ if (amdgpu_device_supports_boco(adev->ddev))
+ vga_switcheroo_fini_domain_pm_ops(adev->dev);
+ vga_client_register(adev->pdev, NULL, NULL, NULL);
+ if (adev->rio_mem)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4552-drm-amdgpu-enable-runtime-pm-on-BACO-capable-boards-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4552-drm-amdgpu-enable-runtime-pm-on-BACO-capable-boards-.patch
new file mode 100644
index 00000000..4ba2b701
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4552-drm-amdgpu-enable-runtime-pm-on-BACO-capable-boards-.patch
@@ -0,0 +1,50 @@
+From 6732f803e38ae86d6c4ca361808f9e508c5fde11 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 13:47:39 -0500
+Subject: [PATCH 4552/4736] drm/amdgpu: enable runtime pm on BACO capable
+ boards if runpm=1
+
+BACO - Bus Active, Chip Off
+
+Everything is in place now. Not enabled by default yet. You
+still have to specify runpm=1.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index ab7697d7b70a..5fce120e2d86 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -154,10 +154,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ !pci_is_thunderbolt_attached(dev->pdev))
+ flags |= AMD_IS_PX;
+
+- if ((amdgpu_runtime_pm != 0) &&
+- (flags & AMD_IS_PX))
+- adev->runpm = true;
+-
+ /* amdgpu_device_init should report only fatal error
+ * like memory allocation failure or iomapping failure,
+ * or memory manager initialization failure, it must
+@@ -170,6 +166,13 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ goto out;
+ }
+
++ if (amdgpu_device_supports_boco(dev) &&
++ (amdgpu_runtime_pm != 0)) /* enable runpm by default */
++ adev->runpm = true;
++ else if (amdgpu_device_supports_baco(dev) &&
++ (amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 */
++ adev->runpm = true;
++
+ /* Call ACPI methods: require modeset init
+ * but failure is not fatal
+ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4553-drm-amdgpu-add-flag-to-indicate-amdgpu-vm-context.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4553-drm-amdgpu-add-flag-to-indicate-amdgpu-vm-context.patch
new file mode 100644
index 00000000..771f038e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4553-drm-amdgpu-add-flag-to-indicate-amdgpu-vm-context.patch
@@ -0,0 +1,64 @@
+From 9292503daaf0f632834e3336e37b000b229e0564 Mon Sep 17 00:00:00 2001
+From: Alex Sierra <alex.sierra@amd.com>
+Date: Mon, 18 Nov 2019 13:28:46 -0600
+Subject: [PATCH 4553/4736] drm/amdgpu: add flag to indicate amdgpu vm context
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Flag added to indicate if the amdgpu vm context is used for compute or
+graphics.
+
+Change-Id: Ia813037fda2ec2947d73f5c7328388078fbeebe5
+Signed-off-by: Alex Sierra <alex.sierra@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 7c5d9891d89a..c3e87ca13c53 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2713,6 +2713,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ goto error_free_direct;
+
+ vm->pte_support_ats = false;
++ vm->is_compute_context = false;
+
+ if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
+ vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
+@@ -2900,6 +2901,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ vm->update_funcs = &amdgpu_vm_sdma_funcs;
+ dma_fence_put(vm->last_update);
+ vm->last_update = NULL;
++ vm->is_compute_context = true;
+
+ if (vm->pasid) {
+ unsigned long flags;
+@@ -2954,6 +2956,7 @@ void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
+ }
+ vm->pasid = 0;
++ vm->is_compute_context = false;
+ }
+
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 5cb25c1c54e0..76fcf853035c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -301,6 +301,8 @@ struct amdgpu_vm {
+ struct ttm_lru_bulk_move lru_bulk_move;
+ /* mark whether can do the bulk move */
+ bool bulk_moveable;
++ /* Flag to indicate if VM is used for compute */
++ bool is_compute_context;
+ };
+
+ struct amdgpu_vm_manager {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4554-amd-amdgpu-force-to-trigger-a-no-retry-fault-after-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4554-amd-amdgpu-force-to-trigger-a-no-retry-fault-after-a.patch
new file mode 100644
index 00000000..9fce78ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4554-amd-amdgpu-force-to-trigger-a-no-retry-fault-after-a.patch
@@ -0,0 +1,60 @@
+From 871a45729603c20acb9a0927eb549b667c9b68ba Mon Sep 17 00:00:00 2001
+From: Alex Sierra <alex.sierra@amd.com>
+Date: Mon, 18 Nov 2019 15:33:07 -0600
+Subject: [PATCH 4554/4736] amd/amdgpu: force to trigger a no-retry-fault after
+ a retry-fault
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Only for the debugger use case.
+
+[why]
+Avoid endless translation retries, after an invalid address access has
+been issued to the GPU. Instead, the trap handler is forced to enter by
+generating a no-retry-fault.
+A s_trap instruction is inserted in the debugger case to let the wave to
+enter trap handler to save context.
+
+[how]
+Intentionally using an invalid flag combination (F and P set at the same
+time) to trigger a no-retry-fault, after a retry-fault happens. This is
+only valid under compute context.
+
+Change-Id: I4180c30e2631dc0401cbd6171f8a6776e4733c9a
+Signed-off-by: Alex Sierra <alex.sierra@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index c3e87ca13c53..90ac5390ecdf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -3204,11 +3204,20 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid,
+ flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
+ AMDGPU_PTE_SYSTEM;
+
+- if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
++ if (vm->is_compute_context) {
++ /* Intentionally setting invalid PTE flag
++ * combination to force a no-retry-fault
++ */
++ flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
++ AMDGPU_PTE_TF;
++ value = 0;
++
++ } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
+ /* Redirect the access to the dummy page */
+ value = adev->dummy_page_addr;
+ flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
+ AMDGPU_PTE_WRITEABLE;
++
+ } else {
+ /* Let the hw retry silently on the PTE */
+ value = 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch
new file mode 100644
index 00000000..1debddf9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch
@@ -0,0 +1,5022 @@
+From 3ffff051d14b90a48427a1a00b28557d625a6567 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 6 Nov 2019 14:38:55 -0500
+Subject: [PATCH 4555/4736] drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and
+ DSC_SUPPORTED
+
+[Why]
+
+DCN2 and DSC are stable enough to be build by default. So drop the flags.
+
+[How]
+
+Remove them using the unifdef tool. The following commands were executed
+in sequence:
+
+$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'
+$ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'
+
+In addition:
+
+* Remove from kconfig, and replace any dependencies with DCN1_0.
+* Remove from any makefiles.
+* Fix and cleanup NV defninitions in dal_asic_id.h
+* Expand DCN1 ifdef to include DCN2 code in the following files:
+ * clk_mgr/clk_mgr.c: dc_clk_mgr_create()
+ * core/dc_resources.c: dc_create_resource_pool()
+ * dce/dce_dmcu.c: dcn20_*lock_phy()
+ * dce/dce_dmcu.c: dcn20_funcs
+ * dce/dce_dmcu.c: dcn20_dmcu_create()
+ * gpio/hw_factory.c: dal_hw_factory_init()
+ * gpio/hw_translate.c: dal_hw_translate_init()
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 --
+ drivers/gpu/drm/amd/display/Kconfig | 13 +----
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 -----
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 -
+ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 -
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 2 -
+ drivers/gpu/drm/amd/display/dc/Makefile | 12 ++---
+ .../drm/amd/display/dc/bios/bios_parser2.c | 2 -
+ .../display/dc/bios/command_table_helper2.c | 2 -
+ .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 --
+ .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 2 -
+ .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 4 +-
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 48 -------------------
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 -------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 24 ----------
+ .../drm/amd/display/dc/core/dc_link_hwss.c | 6 ---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 8 +---
+ .../gpu/drm/amd/display/dc/core/dc_stream.c | 6 ---
+ .../gpu/drm/amd/display/dc/core/dc_surface.c | 6 ---
+ drivers/gpu/drm/amd/display/dc/dc.h | 38 ---------------
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 4 --
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2 -
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 20 --------
+ drivers/gpu/drm/amd/display/dc/dc_link.h | 4 --
+ drivers/gpu/drm/amd/display/dc/dc_stream.h | 16 -------
+ drivers/gpu/drm/amd/display/dc/dc_types.h | 6 ---
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 4 --
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 2 -
+ .../drm/amd/display/dc/dce/dce_clock_source.c | 4 --
+ .../drm/amd/display/dc/dce/dce_clock_source.h | 6 ---
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 14 ++----
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 2 -
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 4 --
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 6 ---
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 8 ----
+ .../display/dc/dce110/dce110_hw_sequencer.c | 4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 6 ---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 4 --
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 2 -
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 2 -
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 2 -
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 2 -
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 -------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 6 ---
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h | 10 ----
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 -
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 9 ----
+ .../display/dc/dcn10/dcn10_stream_encoder.h | 8 ----
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 -
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 14 ------
+ .../amd/display/dc/dcn20/dcn20_link_encoder.c | 6 ---
+ .../amd/display/dc/dcn20/dcn20_link_encoder.h | 2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 4 --
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 2 -
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 42 ----------------
+ .../drm/amd/display/dc/dcn20/dcn20_resource.h | 2 -
+ .../display/dc/dcn20/dcn20_stream_encoder.c | 6 ---
+ .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 -
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 16 -------
+ drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 -
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 ---
+ drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 +-
+ .../dc/dml/dcn21/display_mode_vba_21.c | 2 -
+ .../dc/dml/dcn21/display_rq_dlg_calc_21.c | 2 -
+ .../amd/display/dc/dml/display_mode_enums.h | 2 -
+ .../drm/amd/display/dc/dml/display_mode_lib.c | 6 ---
+ .../drm/amd/display/dc/dml/display_mode_lib.h | 6 ---
+ .../amd/display/dc/dml/display_mode_structs.h | 2 -
+ .../drm/amd/display/dc/dml/display_mode_vba.c | 2 -
+ .../drm/amd/display/dc/dml/display_mode_vba.h | 2 -
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 -
+ .../gpu/drm/amd/display/dc/dsc/dscc_types.h | 2 -
+ .../gpu/drm/amd/display/dc/dsc/qp_tables.h | 2 -
+ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 -
+ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 2 -
+ .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 -
+ drivers/gpu/drm/amd/display/dc/gpio/Makefile | 2 -
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.c | 2 -
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.h | 2 -
+ .../dc/gpio/dcn20/hw_translate_dcn20.c | 2 -
+ .../dc/gpio/dcn20/hw_translate_dcn20.h | 2 -
+ .../display/dc/gpio/dcn21/hw_factory_dcn21.c | 2 -
+ .../dc/gpio/dcn21/hw_translate_dcn21.c | 2 -
+ .../gpu/drm/amd/display/dc/gpio/ddc_regs.h | 12 -----
+ drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 4 --
+ .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 6 +--
+ .../drm/amd/display/dc/gpio/hw_translate.c | 6 +--
+ .../gpu/drm/amd/display/dc/inc/core_status.h | 2 -
+ .../gpu/drm/amd/display/dc/inc/core_types.h | 22 ---------
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 -
+ .../amd/display/dc/inc/hw/clk_mgr_internal.h | 12 -----
+ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 4 --
+ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 12 -----
+ drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h | 2 -
+ drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 10 ----
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 --
+ .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 10 ----
+ .../drm/amd/display/dc/inc/hw/link_encoder.h | 8 ----
+ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 10 ----
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4 --
+ .../amd/display/dc/inc/hw/stream_encoder.h | 10 ----
+ .../amd/display/dc/inc/hw/timing_generator.h | 8 ----
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 12 -----
+ drivers/gpu/drm/amd/display/dc/inc/resource.h | 4 --
+ drivers/gpu/drm/amd/display/dc/irq/Makefile | 2 -
+ .../dc/virtual/virtual_stream_encoder.c | 8 ----
+ .../gpu/drm/amd/display/include/dal_asic_id.h | 2 -
+ .../gpu/drm/amd/display/include/dal_types.h | 2 -
+ .../drm/amd/display/include/logger_types.h | 6 ---
+ .../drm/amd/display/modules/inc/mod_shared.h | 2 -
+ 117 files changed, 14 insertions(+), 744 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 62d088a4840b..3f587dce39e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1545,7 +1545,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ }
+
+ parse_soc_bounding_box:
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /*
+ * soc bounding box info is not integrated in disocovery table,
+ * we always need to parse it from gpu info firmware.
+@@ -1556,7 +1555,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
+ }
+-#endif
+ break;
+ }
+ default:
+@@ -2620,8 +2618,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
+ case CHIP_VEGA20:
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case CHIP_RAVEN:
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
+ case CHIP_NAVI12:
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index 9eae7c67ceb5..19250f316da3 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -14,21 +14,11 @@ config DRM_AMD_DC
+ config DRM_AMD_DC_DCN1_0
+ def_bool n
+ help
+- RV family support for display engine
+-
+-config DRM_AMD_DC_DCN2_0
+- bool "DCN 2.0 family"
+- default y
+- depends on DRM_AMD_DC && X86
+- depends on DRM_AMD_DC_DCN1_0
+- help
+- Choose this option if you want to have
+- Navi support for display engine
++ RV and NV family support for display engine
+
+ config DRM_AMD_DC_DCN2_1
+ bool "DCN 2.1 family"
+ depends on DRM_AMD_DC && X86
+- depends on DRM_AMD_DC_DCN2_0
+ help
+ Choose this option if you want to have
+ Renoir support for display engine
+@@ -38,7 +28,6 @@ config DRM_AMD_DC_DSC_SUPPORT
+ default y
+ depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC_DCN1_0
+- depends on DRM_AMD_DC_DCN2_0
+ help
+ Choose this option if you want to have
+ Dynamic Stream Compression support
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 430008124373..3ec482e79ecf 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -943,9 +943,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+
+ init_data.flags.power_down_display_on_boot = true;
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ init_data.soc_bounding_box = adev->dm.soc_bounding_box;
+-#endif
+
+ /* Display Core create. */
+ adev->dm.dc = dc_create(&init_data);
+@@ -2741,10 +2739,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ break;
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case CHIP_RAVEN:
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case CHIP_RENOIR:
+ #endif
+@@ -2985,7 +2981,6 @@ static int dm_early_init(void *handle)
+ adev->mode_info.num_dig = 4;
+ break;
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case CHIP_NAVI10:
+ case CHIP_NAVI12:
+ adev->mode_info.num_crtc = 6;
+@@ -2997,7 +2992,6 @@ static int dm_early_init(void *handle)
+ adev->mode_info.num_hpd = 5;
+ adev->mode_info.num_dig = 5;
+ break;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case CHIP_RENOIR:
+ adev->mode_info.num_crtc = 4;
+@@ -3297,11 +3291,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
+ if (adev->asic_type == CHIP_VEGA10 ||
+ adev->asic_type == CHIP_VEGA12 ||
+ adev->asic_type == CHIP_VEGA20 ||
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ adev->asic_type == CHIP_NAVI10 ||
+ adev->asic_type == CHIP_NAVI14 ||
+ adev->asic_type == CHIP_NAVI12 ||
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ adev->asic_type == CHIP_RENOIR ||
+ #endif
+@@ -4001,10 +3993,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+ int mode_refresh;
+ int preferred_refresh = 0;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dsc_dec_dpcd_caps dsc_caps;
+ uint32_t link_bandwidth_kbps;
+-#endif
+
+ struct dc_sink *sink = NULL;
+ if (aconnector == NULL) {
+@@ -4078,7 +4068,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ fill_stream_properties_from_drm_display_mode(stream,
+ &mode, &aconnector->base, con_state, old_stream);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ stream->timing.flags.DSC = 0;
+
+ if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
+@@ -4097,7 +4086,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ &stream->timing.dsc_cfg))
+ stream->timing.flags.DSC = 1;
+ }
+-#endif
+
+ update_stream_scaling_settings(&mode, dm_state, stream);
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 1fc810bf02af..e5ef8be7b813 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -281,7 +281,6 @@ struct amdgpu_display_manager {
+
+ const struct firmware *fw_dmcu;
+ uint32_t dmcu_fw_version;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /**
+ * @soc_bounding_box:
+ *
+@@ -289,7 +288,6 @@ struct amdgpu_display_manager {
+ * available in FW
+ */
+ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+-#endif
+ };
+
+ struct amdgpu_dm_connector {
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index 92ba7ca84d7c..8522e66db4ea 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -539,7 +539,6 @@ bool dm_helpers_submit_i2c(
+
+ return result;
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dm_helpers_dp_write_dsc_enable(
+ struct dc_context *ctx,
+ const struct dc_stream_state *stream,
+@@ -550,7 +549,6 @@ bool dm_helpers_dp_write_dsc_enable(
+
+ return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
+ }
+-#endif
+
+ bool dm_helpers_is_dp_sink_present(struct dc_link *link)
+ {
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index e42b162ee5d3..254123a02aa3 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -996,7 +996,6 @@ void dm_pp_get_funcs(
+ funcs->rv_funcs.set_hard_min_fclk_by_freq =
+ pp_rv_set_hard_min_fclk_by_freq;
+ break;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ case DCN_VERSION_2_0:
+ funcs->ctx.ver = PP_SMU_VER_NV;
+ funcs->nv_funcs.pp_smu.dm = ctx;
+@@ -1019,7 +1018,6 @@ void dm_pp_get_funcs(
+ funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
+ funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
+ break;
+-#endif
+
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ case DCN_VERSION_2_1:
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 90482b158283..38ef29719400 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -25,18 +25,12 @@
+
+ DC_LIBS = basics bios calcs clk_mgr dce gpio irq virtual
+
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DC_LIBS += dcn20
+-endif
+-
+-
+-ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DC_LIBS += dsc
+-endif
+-
+-ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DC_LIBS += dcn10 dml
+ endif
++
+ ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ DC_LIBS += dcn21
+ endif
+@@ -59,7 +53,7 @@ include $(AMD_DC)
+ DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
+ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DISPLAY_CORE += dc_vm_helper.o
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 03a5e82a7b2d..c70bfdca5d2f 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1415,10 +1415,8 @@ static enum bp_result get_integrated_info_v11(
+ info->ma_channel_number = info_v11->umachannelnumber;
+ info->lvds_ss_percentage =
+ le16_to_cpu(info_v11->lvds_ss_percentage);
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ info->dp_ss_control =
+ le16_to_cpu(info_v11->reserved1);
+-#endif
+ info->lvds_sspread_rate_in_10hz =
+ le16_to_cpu(info_v11->lvds_ss_rate_10hz);
+ info->hdmi_ss_percentage =
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+index db153ddf0fee..45bb2bd81ba1 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+@@ -62,11 +62,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
+ return true;
+ #endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case DCN_VERSION_2_0:
+ *h = dal_cmd_tbl_helper_dce112_get_table2();
+ return true;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case DCN_VERSION_2_1:
+ *h = dal_cmd_tbl_helper_dce112_get_table2();
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+index 9b2cb57bf2ba..a4ddd657598f 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+@@ -53,13 +53,9 @@
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /* Defaults from spreadsheet rev#247.
+ * RV2 delta: dram_clock_change_latency, max_num_dpp
+ */
+-#else
+-/* Defaults from spreadsheet rev#247 */
+-#endif
+ const struct dcn_soc_bounding_box dcn10_soc_defaults = {
+ /* latencies */
+ .sr_exit_time = 17, /*us*/
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+index b864869cc7e3..9f15817a3eed 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+@@ -72,9 +72,7 @@ CLK_MGR_DCN10 = rv1_clk_mgr.o rv1_clk_mgr_vbios_smu.o rv2_clk_mgr.o
+ AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10))
+
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10)
+-endif
+
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ ###############################################################################
+ # DCN20
+ ###############################################################################
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+index 8af8fab14bcb..3d42bb4355f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+@@ -150,13 +150,11 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+ break;
+ }
+ break;
+-#endif /* Family RV */
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case FAMILY_NV:
+ dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+ break;
+-#endif /* Family NV */
++#endif /* Family RV and NV*/
+
+ default:
+ ASSERT(0); /* Unknown Asic */
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 81f4499490b9..121465bf223f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -57,13 +57,9 @@
+ #include "dc_link_dp.h"
+ #include "dc_dmub_srv.h"
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #include "vm_helper.h"
+-#endif
+
+ #include "dce/dce_i2c.h"
+
+@@ -575,11 +571,9 @@ static void dc_destruct(struct dc *dc)
+ dc->dcn_ip = NULL;
+
+ #endif
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ kfree(dc->vm_helper);
+ dc->vm_helper = NULL;
+
+-#endif
+ }
+
+ static bool dc_construct(struct dc *dc,
+@@ -596,11 +590,9 @@ static bool dc_construct(struct dc *dc,
+ enum dce_version dc_version = DCE_VERSION_UNKNOWN;
+ dc->config = init_params->flags;
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ // Allocate memory for the vm_helper
+ dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
+
+-#endif
+ memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
+
+ dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
+@@ -634,9 +626,7 @@ static bool dc_construct(struct dc *dc,
+ }
+
+ dc->dcn_ip = dcn_ip;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ dc->soc_bounding_box = init_params->soc_bounding_box;
+-#endif
+ #endif
+
+ dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
+@@ -738,7 +728,6 @@ static bool dc_construct(struct dc *dc,
+ return false;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static bool disable_all_writeback_pipes_for_stream(
+ const struct dc *dc,
+ struct dc_stream_state *stream,
+@@ -751,7 +740,6 @@ static bool disable_all_writeback_pipes_for_stream(
+
+ return true;
+ }
+-#endif
+
+ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ {
+@@ -777,16 +765,12 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ }
+ if (should_disable && old_stream) {
+ dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
+-#endif
+ if (dc->hwss.apply_ctx_for_surface)
+ dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, dangling_context);
+-#endif
+ }
+
+ current_ctx = dc->current_state;
+@@ -1176,10 +1160,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ context->stream_status[i].plane_count,
+ context); /* use new pipe config in new context */
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+
+ /* Program hardware */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+@@ -1198,10 +1180,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ }
+
+ /* Program all planes within new context*/
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+ for (i = 0; i < context->stream_count; i++) {
+ const struct dc_link *link = context->streams[i]->link;
+
+@@ -1685,10 +1665,8 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ if (stream_update->gamut_remap)
+ su_flags->bits.gamut_remap = 1;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (stream_update->wb_update)
+ su_flags->bits.wb_update = 1;
+-#endif
+ if (su_flags->raw != 0)
+ overall_type = UPDATE_TYPE_FULL;
+
+@@ -1851,7 +1829,6 @@ static void copy_surface_update_to_plane(
+ sizeof(struct dc_transfer_func_distributed_points));
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (srf_update->func_shaper &&
+ (surface->in_shaper_func !=
+ srf_update->func_shaper))
+@@ -1874,7 +1851,6 @@ static void copy_surface_update_to_plane(
+ memcpy(surface->blend_tf, srf_update->blend_tf,
+ sizeof(*surface->blend_tf));
+
+-#endif
+ if (srf_update->input_csc_color_matrix)
+ surface->input_csc_color_matrix =
+ *srf_update->input_csc_color_matrix;
+@@ -1949,7 +1925,6 @@ static void copy_stream_update_to_stream(struct dc *dc,
+
+ if (update->dither_option)
+ stream->dither_option = *update->dither_option;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* update current stream with writeback info */
+ if (update->wb_update) {
+ int i;
+@@ -1960,8 +1935,6 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ stream->writeback_info[i] =
+ update->wb_update->writeback_info[i];
+ }
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ if (update->dsc_config) {
+ struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
+ uint32_t old_dsc_enabled = stream->timing.flags.DSC;
+@@ -1976,7 +1949,6 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ stream->timing.flags.DSC = old_dsc_enabled;
+ }
+ }
+-#endif
+ }
+
+ static void commit_planes_do_stream_update(struct dc *dc,
+@@ -2017,31 +1989,25 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ dc_stream_program_csc_matrix(dc, stream);
+
+ if (stream_update->dither_option) {
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+-#endif
+ resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+ &pipe_ctx->stream->bit_depth_params);
+ pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ while (odm_pipe) {
+ odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
+-#endif
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) {
+ dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true);
+ dp_update_dsc_config(pipe_ctx);
+ dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false);
+ }
+-#endif
+ /* Full fe update*/
+ if (update_type == UPDATE_TYPE_FAST)
+ continue;
+@@ -2128,15 +2094,12 @@ static void commit_planes_for_stream(struct dc *dc,
+ */
+ if (dc->hwss.apply_ctx_for_surface)
+ dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+
+ return;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+ for (i = 0; i < surface_count; i++) {
+ struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2158,7 +2121,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ }
+ }
+ }
+-#endif
+
+ // Update Type FULL, Surface updates
+ for (j = 0; j < dc->res_pool->pipe_count; j++) {
+@@ -2179,7 +2141,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ if (update_type == UPDATE_TYPE_FAST)
+ continue;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
+
+ if (dc->hwss.program_triplebuffer != NULL &&
+@@ -2188,7 +2149,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ dc->hwss.program_triplebuffer(
+ dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
+ }
+-#endif
+ stream_status =
+ stream_get_status(context, pipe_ctx->stream);
+
+@@ -2197,7 +2157,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ dc, pipe_ctx->stream, stream_status->plane_count, context);
+ }
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ dc->hwss.program_front_end_for_ctx(dc, context);
+ #ifdef CONFIG_DRM_AMD_DC_DCN1_0
+@@ -2216,7 +2175,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ }
+ #endif
+ }
+-#endif
+
+ // Update Type FAST, Surface updates
+ if (update_type == UPDATE_TYPE_FAST) {
+@@ -2226,7 +2184,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ */
+ dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.set_flip_control_gsl)
+ for (i = 0; i < surface_count; i++) {
+ struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2245,7 +2202,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ plane_state->flip_immediate);
+ }
+ }
+-#endif
+ /* Perform requested Updates */
+ for (i = 0; i < surface_count; i++) {
+ struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2258,7 +2214,6 @@ static void commit_planes_for_stream(struct dc *dc,
+
+ if (pipe_ctx->plane_state != plane_state)
+ continue;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /*program triple buffer after lock based on flip type*/
+ if (dc->hwss.program_triplebuffer != NULL &&
+ !dc->debug.disable_tri_buf) {
+@@ -2266,7 +2221,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ dc->hwss.program_triplebuffer(
+ dc, pipe_ctx, plane_state->triplebuffer_flips);
+ }
+-#endif
+ if (srf_updates[i].flip_addr)
+ dc->hwss.update_plane_addr(dc, pipe_ctx);
+ }
+@@ -2432,12 +2386,10 @@ void dc_set_power_state(
+
+ dc->hwss.init_hw(dc);
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ if (dc->hwss.init_sys_ctx != NULL &&
+ dc->vm_pa_config.valid) {
+ dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
+ }
+-#endif
+
+ break;
+ default:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ec010dc0de8b..f27921e46937 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1494,9 +1494,7 @@ static enum dc_status enable_link_dp(
+ struct dc_link *link = stream->link;
+ struct dc_link_settings link_settings = {0};
+ enum dp_panel_mode panel_mode;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool fec_enable;
+-#endif
+ int i;
+ bool apply_seamless_boot_optimization = false;
+
+@@ -1571,14 +1569,12 @@ static enum dc_status enable_link_dp(
+ else
+ status = DC_FAIL_DP_LINK_TRAINING;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (link->preferred_training_settings.fec_enable != NULL)
+ fec_enable = *link->preferred_training_settings.fec_enable;
+ else
+ fec_enable = true;
+
+ dp_set_fec_enable(link, fec_enable);
+-#endif
+ return status;
+ }
+
+@@ -2201,14 +2197,12 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
+ dp_disable_link_phy(link, signal);
+ else
+ dp_disable_link_phy_mst(link, signal);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+
+ if (dc_is_dp_sst_signal(signal) ||
+ link->mst_stream_alloc_table.stream_count == 0) {
+ dp_set_fec_enable(link, false);
+ dp_set_fec_ready(link, false);
+ }
+-#endif
+ } else {
+ if (signal != SIGNAL_TYPE_VIRTUAL)
+ link->link_enc->funcs->disable_output(link->link_enc, signal);
+@@ -3015,23 +3009,19 @@ void core_link_enable_stream(
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ COLOR_DEPTH_UNDEFINED);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (pipe_ctx->stream->timing.flags.DSC) {
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ dp_set_dsc_enable(pipe_ctx, true);
+ }
+-#endif
+ core_dc->hwss.enable_stream(pipe_ctx);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* Set DPS PPS SDP (AKA "info frames") */
+ if (pipe_ctx->stream->timing.flags.DSC) {
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ dp_set_dsc_pps_sdp(pipe_ctx, true);
+ }
+-#endif
+
+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ dc_link_allocate_mst_payload(pipe_ctx);
+@@ -3045,14 +3035,12 @@ void core_link_enable_stream(
+ update_psp_stream_config(pipe_ctx, false);
+ #endif
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ dp_set_dsc_enable(pipe_ctx, true);
+
+ }
+-#endif
+ }
+
+ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+@@ -3101,12 +3089,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ core_dc->hwss.disable_stream(pipe_ctx);
+
+ disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (pipe_ctx->stream->timing.flags.DSC) {
+ if (dc_is_dp_signal(pipe_ctx->stream->signal))
+ dp_set_dsc_enable(pipe_ctx, false);
+ }
+-#endif
+ }
+
+ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+@@ -3174,13 +3160,11 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
+ uint32_t bits_per_channel = 0;
+ uint32_t kbps;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (timing->flags.DSC) {
+ kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
+ kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
+ return kbps;
+ }
+-#endif
+
+ switch (timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+@@ -3358,7 +3342,6 @@ uint32_t dc_link_bandwidth_kbps(
+ link_bw_kbps *= 8; /* 8 bits per byte*/
+ link_bw_kbps *= link_setting->lane_count;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
+ /* Account for FEC overhead.
+ * We have to do it based on caps,
+@@ -3383,7 +3366,6 @@ uint32_t dc_link_bandwidth_kbps(
+ link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
+ link_bw_kbps, 32);
+ }
+-#endif
+
+ return link_bw_kbps;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index a32626864154..272261192e82 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -4,12 +4,8 @@
+ #include "dc_link_dp.h"
+ #include "dm_helpers.h"
+ #include "opp.h"
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "resource.h"
+-#endif
+
+ #include "inc/core_types.h"
+ #include "link_hwss.h"
+@@ -1365,9 +1361,7 @@ enum link_training_result dc_link_dp_perform_link_training(
+ enum link_training_result status = LINK_TRAINING_SUCCESS;
+ struct link_training_settings lt_settings;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool fec_enable;
+-#endif
+ uint8_t repeater_cnt;
+ uint8_t repeater_id;
+
+@@ -1380,14 +1374,12 @@ enum link_training_result dc_link_dp_perform_link_training(
+ /* 1. set link rate, lane count and spread. */
+ dpcd_set_link_settings(link, &lt_settings);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (link->preferred_training_settings.fec_enable != NULL)
+ fec_enable = *link->preferred_training_settings.fec_enable;
+ else
+ fec_enable = true;
+
+ dp_set_fec_ready(link, fec_enable);
+-#endif
+
+ if (!link->is_lttpr_mode_transparent) {
+ /* Configure lttpr mode */
+@@ -1529,9 +1521,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
+ enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
+ enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
+ enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool fec_enable = false;
+-#endif
+
+ initialize_training_settings(
+ link,
+@@ -1551,11 +1541,9 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
+ dp_enable_link_phy(link, link->connector_signal,
+ dp_cs_id, link_settings);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* Set FEC enable */
+ fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
+ dp_set_fec_ready(link, fec_enable);
+-#endif
+
+ if (lt_overrides->alternate_scrambler_reset) {
+ if (*lt_overrides->alternate_scrambler_reset)
+@@ -1596,9 +1584,7 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
+ */
+ if (link_down == true) {
+ dp_disable_link_phy(link, link->connector_signal);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ dp_set_fec_ready(link, false);
+-#endif
+ }
+
+ link->sync_lt_in_progress = false;
+@@ -3306,7 +3292,6 @@ static bool retrieve_link_cap(struct dc_link *link)
+ dp_hw_fw_revision.ieee_fw_rev,
+ sizeof(dp_hw_fw_revision.ieee_fw_rev));
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ memset(&link->dpcd_caps.dsc_caps, '\0',
+ sizeof(link->dpcd_caps.dsc_caps));
+ memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
+@@ -3328,7 +3313,6 @@ static bool retrieve_link_cap(struct dc_link *link)
+ link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
+ sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw));
+ }
+-#endif
+
+ /* Connectivity log: detection */
+ CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
+@@ -3458,14 +3442,12 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ stream->timing.display_color_depth;
+ struct bit_depth_reduction_params params;
+ struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ int width = pipe_ctx->stream->timing.h_addressable +
+ pipe_ctx->stream->timing.h_border_left +
+ pipe_ctx->stream->timing.h_border_right;
+ int height = pipe_ctx->stream->timing.v_addressable +
+ pipe_ctx->stream->timing.v_border_bottom +
+ pipe_ctx->stream->timing.v_border_top;
+-#endif
+
+ memset(&params, 0, sizeof(params));
+
+@@ -3509,7 +3491,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+ pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+ controller_test_pattern, color_depth);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ else if (opp->funcs->opp_set_disp_pattern_generator) {
+ struct pipe_ctx *odm_pipe;
+ enum controller_dp_color_space controller_color_space;
+@@ -3558,7 +3539,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ width,
+ height);
+ }
+-#endif
+ }
+ break;
+ case DP_TEST_PATTERN_VIDEO_MODE:
+@@ -3571,7 +3551,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ color_depth);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ else if (opp->funcs->opp_set_disp_pattern_generator) {
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+@@ -3600,7 +3579,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ width,
+ height);
+ }
+-#endif
+ }
+ break;
+
+@@ -3876,7 +3854,6 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
+ return DP_PANEL_MODE_DEFAULT;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void dp_set_fec_ready(struct dc_link *link, bool ready)
+ {
+ /* FEC has to be "set ready" before the link training.
+@@ -3939,5 +3916,4 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
+ }
+ }
+ }
+-#endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 5efbdc1eb173..bb1e8e5b5252 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -12,12 +12,8 @@
+ #include "dc_link_ddc.h"
+ #include "dm_helpers.h"
+ #include "dpcd_defs.h"
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "resource.h"
+-#endif
+
+ static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
+ {
+@@ -374,7 +370,6 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define DC_LOGGER \
+ dsc->ctx->logger
+ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
+@@ -572,5 +567,4 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
+ dp_set_dsc_pps_sdp(pipe_ctx, true);
+ return true;
+ }
+-#endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 2acfaa9a24cd..081275a430ad 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -46,9 +46,7 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "dcn10/dcn10_resource.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/dcn20_resource.h"
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #include "dcn21/dcn21_resource.h"
+ #endif
+@@ -108,11 +106,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
+ break;
+ #endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case FAMILY_NV:
+ dc_version = DCN_VERSION_2_0;
+ break;
+-#endif
+ default:
+ dc_version = DCE_VERSION_UNKNOWN;
+ break;
+@@ -164,18 +160,16 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
+ case DCN_VERSION_1_01:
+ res_pool = dcn10_create_resource_pool(init_data, dc);
+ break;
+-#endif
+
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case DCN_VERSION_2_0:
+ res_pool = dcn20_create_resource_pool(init_data, dc);
+ break;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case DCN_VERSION_2_1:
+ res_pool = dcn21_create_resource_pool(init_data, dc);
+ break;
++#endif
+ #endif
+
+ default:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index ae7cbb6d7847..59eaa5c172a9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -105,7 +105,6 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ /* EDID CAP translation for HDMI 2.0 */
+ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
+ stream->timing.dsc_cfg.num_slices_h = 0;
+ stream->timing.dsc_cfg.num_slices_v = 0;
+@@ -114,7 +113,6 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ stream->timing.dsc_cfg.linebuf_depth = 9;
+ stream->timing.dsc_cfg.version_minor = 2;
+ stream->timing.dsc_cfg.ycbcr422_simple = 0;
+-#endif
+
+ update_stream_signal(stream, dc_sink_data);
+
+@@ -364,7 +362,6 @@ bool dc_stream_set_cursor_position(
+ return true;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_add_writeback(struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_writeback_info *wb_info)
+@@ -477,7 +474,6 @@ bool dc_stream_remove_writeback(struct dc *dc,
+
+ return true;
+ }
+-#endif
+
+ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
+ {
+@@ -564,7 +560,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ return ret;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ {
+ struct pipe_ctx *pipe = NULL;
+@@ -625,7 +620,6 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+
+ return true;
+ }
+-#endif
+
+ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index d534ac166512..5904c459fe8f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -48,7 +48,6 @@ static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *pl
+ plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
+ plane_state->in_transfer_func->ctx = ctx;
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ plane_state->in_shaper_func = dc_create_transfer_func();
+ if (plane_state->in_shaper_func != NULL) {
+ plane_state->in_shaper_func->type = TF_TYPE_BYPASS;
+@@ -65,7 +64,6 @@ static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *pl
+ plane_state->blend_tf->ctx = ctx;
+ }
+
+-#endif
+ }
+
+ static void dc_plane_destruct(struct dc_plane_state *plane_state)
+@@ -78,7 +76,6 @@ static void dc_plane_destruct(struct dc_plane_state *plane_state)
+ plane_state->in_transfer_func);
+ plane_state->in_transfer_func = NULL;
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (plane_state->in_shaper_func != NULL) {
+ dc_transfer_func_release(
+ plane_state->in_shaper_func);
+@@ -95,7 +92,6 @@ static void dc_plane_destruct(struct dc_plane_state *plane_state)
+ plane_state->blend_tf = NULL;
+ }
+
+-#endif
+ }
+
+ /*******************************************************************************
+@@ -260,7 +256,6 @@ struct dc_transfer_func *dc_create_transfer_func(void)
+ return NULL;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static void dc_3dlut_func_free(struct kref *kref)
+ {
+ struct dc_3dlut *lut = container_of(kref, struct dc_3dlut, refcount);
+@@ -294,6 +289,5 @@ void dc_3dlut_func_retain(struct dc_3dlut *lut)
+ {
+ kref_get(&lut->refcount);
+ }
+-#endif
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 18fdd61a606b..d710e123b53a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -113,17 +113,13 @@ struct dc_caps {
+ bool psp_setup_panel_mode;
+ bool extended_aux_timeout_support;
+ bool dmcub_support;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hw_3d_lut;
+-#endif
+ struct dc_plane_cap planes[MAX_PLANES];
+ };
+
+ struct dc_bug_wa {
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool no_connect_phy_config;
+ bool dedcn20_305_wa;
+-#endif
+ bool skip_clock_update;
+ };
+
+@@ -364,10 +360,8 @@ struct dc_debug_options {
+ bool disable_dfs_bypass;
+ bool disable_dpp_power_gate;
+ bool disable_hubp_power_gate;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool disable_dsc_power_gate;
+ int dsc_min_slice_height_override;
+-#endif
+ bool native422_support;
+ bool disable_pplib_wm_range;
+ enum wm_report_mode pplib_wm_report_mode;
+@@ -407,9 +401,7 @@ struct dc_debug_options {
+ bool dmcub_emulation;
+ bool dmub_command_table; /* for testing only */
+ struct dc_bw_validation_profile bw_val_profile;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool disable_fec;
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ bool disable_48mhz_pwrdwn;
+ #endif
+@@ -418,9 +410,7 @@ struct dc_debug_options {
+ */
+ unsigned int force_min_dcfclk_mhz;
+ bool disable_timing_sync;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool cm_in_bypass;
+-#endif
+ int force_clock_mode;/*every mode change.*/
+
+ bool nv12_iflip_vm_wa;
+@@ -434,7 +424,6 @@ struct dc_debug_data {
+ uint32_t auxErrorCount;
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config {
+ struct {
+ uint64_t start_addr;
+@@ -464,7 +453,6 @@ struct dc_virtual_addr_space_config {
+ uint32_t page_table_block_size_in_bytes;
+ uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
+ };
+-#endif
+
+ struct dc_bounding_box_overrides {
+ int sr_exit_time_ns;
+@@ -492,9 +480,7 @@ struct dc {
+ struct dc_bounding_box_overrides bb_overrides;
+ struct dc_bug_wa work_arounds;
+ struct dc_context *ctx;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config vm_pa_config;
+-#endif
+
+ uint8_t link_count;
+ struct dc_link *links[MAX_PIPES * 2];
+@@ -532,10 +518,8 @@ struct dc {
+ struct dc_debug_data debug_data;
+
+ const char *build_id;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct vm_helper *vm_helper;
+ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+-#endif
+ };
+
+ enum frame_buffer_mode {
+@@ -572,13 +556,11 @@ struct dc_init_data {
+
+ struct dc_config flags;
+ uint32_t log_mask;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /**
+ * gpu_info FW provided soc bounding box struct or 0 if not
+ * available in FW
+ */
+ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+-#endif
+ };
+
+ struct dc_callback_init {
+@@ -593,11 +575,9 @@ struct dc *dc_create(const struct dc_init_data *init_params);
+ void dc_hardware_init(struct dc *dc);
+
+ int dc_get_vmid_use_vector(struct dc *dc);
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
+ /* Returns the number of vmids supported */
+ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+-#endif
+ void dc_init_callbacks(struct dc *dc,
+ const struct dc_callback_init *init_params);
+ void dc_deinit_callbacks(struct dc *dc);
+@@ -673,7 +653,6 @@ struct dc_transfer_func {
+ };
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ union dc_3dlut_state {
+ struct {
+@@ -697,7 +676,6 @@ struct dc_3dlut {
+ union dc_3dlut_state state;
+ struct dc_context *ctx;
+ };
+-#endif
+ /*
+ * This structure is filled in by dc_surface_get_status and contains
+ * the last requested address and the currently active address so the called
+@@ -748,9 +726,7 @@ union surface_update_flags {
+ struct dc_plane_state {
+ struct dc_plane_address address;
+ struct dc_plane_flip_time time;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool triplebuffer_flips;
+-#endif
+ struct scaling_taps scaling_quality;
+ struct rect src_rect;
+ struct rect dst_rect;
+@@ -773,11 +749,9 @@ struct dc_plane_state {
+
+ enum dc_color_space color_space;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_3dlut *lut3d_func;
+ struct dc_transfer_func *in_shaper_func;
+ struct dc_transfer_func *blend_tf;
+-#endif
+
+ enum surface_pixel_format format;
+ enum dc_rotation_angle rotation;
+@@ -845,11 +819,9 @@ struct dc_surface_update {
+
+ const struct dc_csc_transform *input_csc_color_matrix;
+ const struct fixed31_32 *coeff_reduction_factor;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ const struct dc_transfer_func *func_shaper;
+ const struct dc_3dlut *lut3d_func;
+ const struct dc_transfer_func *blend_tf;
+-#endif
+ };
+
+ /*
+@@ -870,11 +842,9 @@ void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
+ void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
+ struct dc_transfer_func *dc_create_transfer_func(void);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_3dlut *dc_create_3dlut_func(void);
+ void dc_3dlut_func_release(struct dc_3dlut *lut);
+ void dc_3dlut_func_retain(struct dc_3dlut *lut);
+-#endif
+ /*
+ * This structure holds a surface address. There could be multiple addresses
+ * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
+@@ -991,10 +961,8 @@ struct dpcd_caps {
+ bool panel_mode_edp;
+ bool dpcd_display_control_capable;
+ bool ext_receiver_cap_field_present;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ union dpcd_fec_capability fec_cap;
+ struct dpcd_dsc_capabilities dsc_caps;
+-#endif
+ struct dc_lttpr_caps lttpr_caps;
+
+ };
+@@ -1017,14 +985,12 @@ struct dc_container_id {
+ };
+
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_sink_dsc_caps {
+ // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
+ // 'false' if they are sink's DSC caps
+ bool is_virtual_dpcd_dsc;
+ struct dsc_dec_dpcd_caps dsc_dec_caps;
+ };
+-#endif
+
+ /*
+ * The sink structure contains EDID and other display device properties
+@@ -1039,9 +1005,7 @@ struct dc_sink {
+ struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
+ bool converter_disable_audio;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_sink_dsc_caps sink_dsc_caps;
+-#endif
+
+ /* private to DC core */
+ struct dc_link *link;
+@@ -1102,10 +1066,8 @@ bool dc_is_dmcu_initialized(struct dc *dc);
+
+ enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
+ void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ /*******************************************************************************
+ * DSC Interfaces
+ ******************************************************************************/
+ #include "dc_dsc.h"
+-#endif
+ #endif /* DC_INTERFACE_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index 28234d8fdb2c..dfe4472c9e40 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -129,9 +129,7 @@ struct dc_link_training_overrides {
+ bool *alternate_scrambler_reset;
+ bool *enhanced_framing;
+ bool *mst_enable;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool *fec_enable;
+-#endif
+ };
+
+ union dpcd_rev {
+@@ -570,7 +568,6 @@ struct dp_audio_test_data {
+ uint8_t pattern_period[8];
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* FEC capability DPCD register field bits-*/
+ union dpcd_fec_capability {
+ struct {
+@@ -695,6 +692,5 @@ struct dpcd_dsc_capabilities {
+ union dpcd_dsc_ext_capabilities dsc_ext_caps;
+ };
+
+-#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
+
+ #endif /* DC_DP_TYPES_H */
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index 0ed2962add5a..a782ae18a1c5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -1,4 +1,3 @@
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #ifndef DC_DSC_H_
+ #define DC_DSC_H_
+ /*
+@@ -69,4 +68,3 @@ bool dc_dsc_compute_config(
+ const struct dc_crtc_timing *timing,
+ struct dc_dsc_config *dsc_cfg);
+ #endif
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index e0856bb8511f..86043d431d40 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -167,12 +167,10 @@ enum surface_pixel_format {
+ /*swaped & float*/
+ SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
+ /*grow graphics here if necessary */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX,
+ SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
+ SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
+ SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
+-#endif
+ SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
+ SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
+ SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
+@@ -180,10 +178,8 @@ enum surface_pixel_format {
+ SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
+ SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
+ SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010,
+ SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
+-#endif
+ SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
+ SURFACE_PIXEL_FORMAT_INVALID
+
+@@ -222,12 +218,10 @@ enum tile_split_values {
+ DC_ROTATED_MICRO_TILING = 0x3,
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum tripleBuffer_enable {
+ DC_TRIPLEBUFFER_DISABLE = 0x0,
+ DC_TRIPLEBUFFER_ENABLE = 0x1,
+ };
+-#endif
+
+ /* TODO: These values come from hardware spec. We need to readdress this
+ * if they ever change.
+@@ -427,13 +421,11 @@ struct dc_csc_transform {
+ bool enable_adjustment;
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_rgb_fixed {
+ struct fixed31_32 red;
+ struct fixed31_32 green;
+ struct fixed31_32 blue;
+ };
+-#endif
+
+ struct dc_gamma {
+ struct kref refcount;
+@@ -468,10 +460,8 @@ enum dc_cursor_color_format {
+ CURSOR_MODE_COLOR_1BIT_AND,
+ CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
+ CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
+ CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
+-#endif
+ };
+
+ /*
+@@ -626,10 +616,8 @@ enum dc_color_depth {
+ COLOR_DEPTH_121212,
+ COLOR_DEPTH_141414,
+ COLOR_DEPTH_161616,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ COLOR_DEPTH_999,
+ COLOR_DEPTH_111111,
+-#endif
+ COLOR_DEPTH_COUNT
+ };
+
+@@ -690,9 +678,7 @@ struct dc_crtc_timing_flags {
+ * rates less than or equal to 340Mcsc */
+ uint32_t LTE_340MCSC_SCRAMBLE:1;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ uint32_t DSC : 1; /* Use DSC with this timing */
+-#endif
+ };
+
+ enum dc_timing_3d_format {
+@@ -717,7 +703,6 @@ enum dc_timing_3d_format {
+ TIMING_3D_FORMAT_MAX,
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_dsc_config {
+ uint32_t num_slices_h; /* Number of DSC slices - horizontal */
+ uint32_t num_slices_v; /* Number of DSC slices - vertical */
+@@ -728,7 +713,6 @@ struct dc_dsc_config {
+ bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
+ int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
+ };
+-#endif
+ struct dc_crtc_timing {
+ uint32_t h_total;
+ uint32_t h_border_left;
+@@ -755,9 +739,7 @@ struct dc_crtc_timing {
+ enum scanning_type scan_type;
+
+ struct dc_crtc_timing_flags flags;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_dsc_config dsc_cfg;
+-#endif
+ };
+
+ #ifndef AMD_EDID_UTILITY
+@@ -796,7 +778,6 @@ enum vram_type {
+ VIDEO_MEMORY_TYPE_GDDR6 = 6,
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dwb_cnv_out_bpc {
+ DWB_CNV_OUT_BPC_8BPC = 0,
+ DWB_CNV_OUT_BPC_10BPC = 1,
+@@ -847,7 +828,6 @@ struct mcif_buf_params {
+ unsigned int swlock;
+ };
+
+-#endif
+
+ #define MAX_TG_COLOR_VALUE 0x3FF
+ struct tg_color {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 03efdc1a7b03..1ff79f703734 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -29,13 +29,11 @@
+ #include "dc_types.h"
+ #include "grph_object_defs.h"
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ enum dc_link_fec_state {
+ dc_link_fec_not_ready,
+ dc_link_fec_ready,
+ dc_link_fec_enabled
+ };
+-#endif
+ struct dc_link_status {
+ bool link_active;
+ struct dpcd_caps *dpcd_caps;
+@@ -142,9 +140,7 @@ struct dc_link {
+
+ struct link_trace link_trace;
+ struct gpio *hpd_gpio;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ enum dc_link_fec_state fec_state;
+-#endif
+ };
+
+ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index 70274fc43a72..3ea54321b045 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -52,7 +52,6 @@ struct freesync_context {
+ bool dummy;
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ enum hubp_dmdata_mode {
+ DMDATA_SW_MODE,
+ DMDATA_HW_MODE
+@@ -82,9 +81,7 @@ struct dc_dmdata_attributes {
+ /* An unbounded array of uint32s, represents software dmdata to be loaded */
+ uint32_t *dmdata_sw_data;
+ };
+-#endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_writeback_info {
+ bool wb_enabled;
+ int dwb_pipe_inst;
+@@ -96,7 +93,6 @@ struct dc_writeback_update {
+ unsigned int num_wb_info;
+ struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
+ };
+-#endif
+
+ enum vertical_interrupt_ref_point {
+ START_V_UPDATE = 0,
+@@ -121,9 +117,7 @@ union stream_update_flags {
+ uint32_t abm_level:1;
+ uint32_t dpms_off:1;
+ uint32_t gamut_remap:1;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t wb_update:1;
+-#endif
+ } bits;
+
+ uint32_t raw;
+@@ -204,11 +198,9 @@ struct dc_stream_state {
+
+ struct crtc_trigger_info triggered_crtc_reset;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* writeback */
+ unsigned int num_wb_info;
+ struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
+-#endif
+ /* Computed state bits */
+ bool mode_changed : 1;
+
+@@ -227,9 +219,7 @@ struct dc_stream_state {
+ bool apply_seamless_boot_optimization;
+
+ uint32_t stream_id;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool is_dsc_enabled;
+-#endif
+ union stream_update_flags update_flags;
+ };
+
+@@ -260,12 +250,8 @@ struct dc_stream_update {
+
+ struct dc_csc_transform *output_csc_transform;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_writeback_update *wb_update;
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ struct dc_dsc_config *dsc_config;
+-#endif
+ };
+
+ bool dc_is_stream_unchanged(
+@@ -355,7 +341,6 @@ bool dc_add_all_planes_for_stream(
+ int plane_count,
+ struct dc_state *context);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_add_writeback(struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_writeback_info *wb_info);
+@@ -366,7 +351,6 @@ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_dmdata_attributes *dmdata_attr);
+-#endif
+
+ enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 45dfed8bcaf7..1363e8907fbf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -468,7 +468,6 @@ enum display_content_type {
+ DISPLAY_CONTENT_TYPE_GAME = 8
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* writeback */
+ struct dwb_stereo_params {
+ bool stereo_enabled; /* false: normal mode, true: 3D stereo */
+@@ -499,7 +498,6 @@ struct dc_dwb_params {
+ enum dwb_subsample_position subsample_position;
+ struct dc_transfer_func *out_transfer_func;
+ };
+-#endif
+
+ /* audio*/
+
+@@ -607,9 +605,7 @@ enum dc_infoframe_type {
+ DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
+ DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
+ DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DC_DP_INFOFRAME_TYPE_PPS = 0x10,
+-#endif
+ };
+
+ struct dc_info_packet {
+@@ -788,7 +784,6 @@ struct dc_clock_config {
+ #endif /*AMD_EDID_UTILITY*/
+ //AMD EDID UTILITY does not need any of the above structures
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* DSC DPCD capabilities */
+ union dsc_slice_caps1 {
+ struct {
+@@ -858,6 +853,5 @@ struct dsc_dec_dpcd_caps {
+ uint32_t branch_overall_throughput_1_mps; /* In MPs */
+ uint32_t branch_max_line_width;
+ };
+-#endif
+
+ #endif /* DC_TYPES_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+index 7ba7e6f722f6..ba0caaffa24b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+@@ -67,7 +67,6 @@
+ SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+ NBIO_SR(BIOS_SCRATCH_2)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define ABM_DCN20_REG_LIST() \
+ ABM_COMMON_REG_LIST_DCE_BASE(), \
+ SR(DC_ABM1_HG_SAMPLE_RATE), \
+@@ -81,7 +80,6 @@
+ SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
+ SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
+ NBIO_SR(BIOS_SCRATCH_2)
+-#endif
+
+ #define ABM_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+@@ -163,9 +161,7 @@
+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+-#endif
+
+ #define ABM_REG_FIELD_LIST(type) \
+ type ABM1_HG_NUM_OF_BINS_SEL; \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index 2e2e925a506b..382465862f29 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -30,7 +30,6 @@
+ #include "inc/hw/aux_engine.h"
+
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define AUX_COMMON_REG_LIST0(id)\
+ SRI(AUX_CONTROL, DP_AUX, id), \
+ SRI(AUX_ARB_CONTROL, DP_AUX, id), \
+@@ -39,7 +38,6 @@
+ SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
+ SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
+ SRI(AUX_SW_STATUS, DP_AUX, id)
+-#endif
+
+ #define AUX_COMMON_REG_LIST(id)\
+ SRI(AUX_CONTROL, DP_AUX, id), \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index accae1089b83..24ad0b4dddb6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1002,7 +1002,6 @@ static bool get_pixel_clk_frequency_100hz(
+ return false;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
+ struct pixel_rate_range_table_entry {
+@@ -1062,7 +1061,6 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = {
+ .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
+ .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
+ };
+-#endif
+
+ /*****************************************/
+ /* Constructor */
+@@ -1433,7 +1431,6 @@ bool dce112_clk_src_construct(
+ return true;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dcn20_clk_src_construct(
+ struct dce110_clk_src *clk_src,
+ struct dc_context *ctx,
+@@ -1449,4 +1446,3 @@ bool dcn20_clk_src_construct(
+
+ return ret;
+ }
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+index 43c1bf60b83c..5b4a29ee1696 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+@@ -55,7 +55,6 @@
+ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
+ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
+ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+ SRII(PHASE, DP_DTO, 0),\
+@@ -76,7 +75,6 @@
+ SRII(PIXEL_RATE_CNTL, OTG, 3),\
+ SRII(PIXEL_RATE_CNTL, OTG, 4),\
+ SRII(PIXEL_RATE_CNTL, OTG, 5)
+-#endif
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
+@@ -95,13 +93,11 @@
+ SRII(PIXEL_RATE_CNTL, OTG, 3)
+ #endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
+ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
+ CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
+ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
+ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
+-#endif
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+
+@@ -201,7 +197,6 @@ bool dce112_clk_src_construct(
+ const struct dce110_clk_src_shift *cs_shift,
+ const struct dce110_clk_src_mask *cs_mask);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dcn20_clk_src_construct(
+ struct dce110_clk_src *clk_src,
+ struct dc_context *ctx,
+@@ -210,6 +205,5 @@ bool dcn20_clk_src_construct(
+ const struct dce110_clk_src_regs *regs,
+ const struct dce110_clk_src_shift *cs_shift,
+ const struct dce110_clk_src_mask *cs_mask);
+-#endif
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+index da9a07edcb06..6e23a82afe8b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+@@ -745,9 +745,7 @@ static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
+ return true;
+ }
+
+-#endif //(CONFIG_DRM_AMD_DC_DCN1_0)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ static bool dcn20_lock_phy(struct dmcu *dmcu)
+ {
+@@ -795,7 +793,7 @@ static bool dcn20_unlock_phy(struct dmcu *dmcu)
+ return true;
+ }
+
+-#endif //(CONFIG_DRM_AMD_DC_DCN2_0)
++#endif //(CONFIG_DRM_AMD_DC_DCN1_0)
+
+ static const struct dmcu_funcs dce_funcs = {
+ .dmcu_init = dce_dmcu_init,
+@@ -819,9 +817,7 @@ static const struct dmcu_funcs dcn10_funcs = {
+ .get_psr_wait_loop = dcn10_get_psr_wait_loop,
+ .is_dmcu_initialized = dcn10_is_dmcu_initialized
+ };
+-#endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static const struct dmcu_funcs dcn20_funcs = {
+ .dmcu_init = dcn10_dmcu_init,
+ .load_iram = dcn10_dmcu_load_iram,
+@@ -834,7 +830,6 @@ static const struct dmcu_funcs dcn20_funcs = {
+ .lock_phy = dcn20_lock_phy,
+ .unlock_phy = dcn20_unlock_phy
+ };
+-#endif
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ static const struct dmcu_funcs dcn21_funcs = {
+@@ -850,6 +845,7 @@ static const struct dmcu_funcs dcn21_funcs = {
+ .unlock_phy = dcn20_unlock_phy
+ };
+ #endif
++#endif
+
+ static void dce_dmcu_construct(
+ struct dce_dmcu *dmcu_dce,
+@@ -869,7 +865,7 @@ static void dce_dmcu_construct(
+ dmcu_dce->dmcu_mask = dmcu_mask;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ static void dcn21_dmcu_construct(
+ struct dce_dmcu *dmcu_dce,
+ struct dc_context *ctx,
+@@ -931,9 +927,7 @@ struct dmcu *dcn10_dmcu_create(
+
+ return &dmcu_dce->base;
+ }
+-#endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dmcu *dcn20_dmcu_create(
+ struct dc_context *ctx,
+ const struct dce_dmcu_registers *regs,
+@@ -954,7 +948,6 @@ struct dmcu *dcn20_dmcu_create(
+
+ return &dmcu_dce->base;
+ }
+-#endif
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ struct dmcu *dcn21_dmcu_create(
+@@ -978,6 +971,7 @@ struct dmcu *dcn21_dmcu_create(
+ return &dmcu_dce->base;
+ }
+ #endif
++#endif
+
+ void dce_dmcu_destroy(struct dmcu **dmcu)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+index 1a42b2cbb21b..89277899b507 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+@@ -266,13 +266,11 @@ struct dmcu *dcn10_dmcu_create(
+ const struct dce_dmcu_shift *dmcu_shift,
+ const struct dce_dmcu_mask *dmcu_mask);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dmcu *dcn20_dmcu_create(
+ struct dc_context *ctx,
+ const struct dce_dmcu_registers *regs,
+ const struct dce_dmcu_shift *dmcu_shift,
+ const struct dce_dmcu_mask *dmcu_mask);
+-#endif
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ struct dmcu *dcn21_dmcu_create(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index a0d1c3b811a9..7e3dde764111 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -210,7 +210,6 @@
+ SR(DC_IP_REQUEST_CNTL), \
+ BL_REG_LIST()
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define HWSEQ_DCN2_REG_LIST()\
+ HWSEQ_DCN_REG_LIST(), \
+ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
+@@ -276,7 +275,6 @@
+ SR(D6VGA_CONTROL), \
+ SR(DC_IP_REQUEST_CNTL), \
+ BL_REG_LIST()
+-#endif
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define HWSEQ_DCN21_REG_LIST()\
+@@ -577,7 +575,6 @@ struct dce_hwseq_registers {
+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+ HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+@@ -637,7 +634,6 @@ struct dce_hwseq_registers {
+ HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+-#endif
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+index 0495a1b5dd74..f4c1ce4f4e6a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+@@ -293,9 +293,7 @@ static bool setup_engine(
+ struct dce_i2c_hw *dce_i2c_hw)
+ {
+ uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t reset_length = 0;
+-#endif
+ /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
+ REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
+
+@@ -319,14 +317,12 @@ static bool setup_engine(
+ REG_UPDATE_N(SETUP, 2,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ } else {
+ reset_length = dce_i2c_hw->send_reset_length;
+ REG_UPDATE_N(SETUP, 3,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
+-#endif
+ }
+ /* Program HW priority
+ * set to High - interrupt software I2C at any time
+@@ -702,7 +698,6 @@ void dcn1_i2c_hw_construct(
+ dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn2_i2c_hw_construct(
+ struct dce_i2c_hw *dce_i2c_hw,
+ struct dc_context *ctx,
+@@ -721,4 +716,3 @@ void dcn2_i2c_hw_construct(
+ if (ctx->dc->debug.scl_reset_length10)
+ dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10;
+ }
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+index cb0234e5d597..d4b2037f7d74 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+@@ -177,9 +177,7 @@ struct dce_i2c_shift {
+ uint8_t DC_I2C_INDEX;
+ uint8_t DC_I2C_INDEX_WRITE;
+ uint8_t XTAL_REF_DIV;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
+-#endif
+ uint8_t DC_I2C_REG_RW_CNTL_STATUS;
+ };
+
+@@ -220,17 +218,13 @@ struct dce_i2c_mask {
+ uint32_t DC_I2C_INDEX;
+ uint32_t DC_I2C_INDEX_WRITE;
+ uint32_t XTAL_REF_DIV;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
+-#endif
+ uint32_t DC_I2C_REG_RW_CNTL_STATUS;
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
+ I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
+ I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
+-#endif
+
+ struct dce_i2c_registers {
+ uint32_t SETUP;
+@@ -312,7 +306,6 @@ void dcn1_i2c_hw_construct(
+ const struct dce_i2c_shift *shifts,
+ const struct dce_i2c_mask *masks);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn2_i2c_hw_construct(
+ struct dce_i2c_hw *dce_i2c_hw,
+ struct dc_context *ctx,
+@@ -320,7 +313,6 @@ void dcn2_i2c_hw_construct(
+ const struct dce_i2c_registers *regs,
+ const struct dce_i2c_shift *shifts,
+ const struct dce_i2c_mask *masks);
+-#endif
+
+ bool dce_i2c_submit_command_hw(
+ struct resource_pool *pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 050634926263..01fefe19ee92 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1319,9 +1319,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct drr_params params = {0};
+ unsigned int event_triggers = 0;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+-#endif
+
+ if (dc->hwss.disable_stream_gating) {
+ dc->hwss.disable_stream_gating(dc, pipe_ctx);
+@@ -1387,7 +1385,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ pipe_ctx->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ while (odm_pipe) {
+ odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
+ odm_pipe->stream_res.opp,
+@@ -1401,7 +1398,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ &stream->clamping);
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
+-#endif
+
+ if (!stream->dpms_off)
+ core_link_enable_stream(context, pipe_ctx);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+index 997e9582edc7..0e682b5aa3eb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+@@ -290,12 +290,8 @@ void dpp1_cnv_setup (
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct dc_csc_transform input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dc_color_space input_color_space,
+ struct cnv_alpha_2bit_lut *alpha_2bit_lut)
+-#else
+- enum dc_color_space input_color_space)
+-#endif
+ {
+ uint32_t pixel_format;
+ uint32_t alpha_en;
+@@ -542,11 +538,9 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
+ .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
+ .dpp_dppclk_control = dpp1_dppclk_control,
+ .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .dpp_program_blnd_lut = NULL,
+ .dpp_program_shaper_lut = NULL,
+ .dpp_program_3dlut = NULL
+-#endif
+ };
+
+ static struct dpp_caps dcn10_dpp_cap = {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+index 1d4a7d640334..2edf566b3a72 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+@@ -1486,12 +1486,8 @@ void dpp1_cnv_setup (
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct dc_csc_transform input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dc_color_space input_color_space,
+ struct cnv_alpha_2bit_lut *alpha_2bit_lut);
+-#else
+- enum dc_color_space input_color_space);
+-#endif
+
+ void dpp1_full_bypass(struct dpp *dpp_base);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index 6f1a312c6a5a..6b7593dd0c77 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -736,10 +736,8 @@ void dpp1_full_bypass(struct dpp *dpp_base)
+ /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
+ if (dpp->tf_mask->CM_BYPASS_EN)
+ REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ else
+ REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
+-#endif
+
+ /* Setting degamma bypass for now */
+ REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+index d67e0abeee93..fce37c527a0b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+@@ -218,14 +218,12 @@ static void dpp1_dscl_set_lb(
+ INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
+ LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ else {
+ /* DSCL caps: pixel data processed in float format */
+ REG_SET_2(LB_DATA_FORMAT, 0,
+ INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
+ LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
+ }
+-#endif
+
+ REG_SET_2(LB_MEMORY_CTRL, 0,
+ MEMORY_CONFIG, mem_size_config,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+index 374cc9acda3b..64b31edc8cf6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+@@ -109,9 +109,7 @@ const struct dwbc_funcs dcn10_dwbc_funcs = {
+ .update = NULL,
+ .set_stereo = NULL,
+ .set_new_content = NULL,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .set_warmup = NULL,
+-#endif
+ .dwb_set_scaler = NULL,
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 5aeee938605a..31b64733d693 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -306,7 +306,6 @@ void hubp1_program_pixel_format(
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 12);
+ break;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 112);
+@@ -327,7 +326,6 @@ void hubp1_program_pixel_format(
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 119);
+ break;
+-#endif
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+@@ -1251,10 +1249,8 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
+ .hubp_get_underflow_status = hubp1_get_underflow_status,
+ .hubp_init = hubp1_init,
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .dmdata_set_attributes = NULL,
+ .dmdata_load = NULL,
+-#endif
+ };
+
+ /*****************************************/
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index e65e76f018e4..780af5b3c16f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -729,13 +729,11 @@ void hubp1_dcc_control(struct hubp *hubp,
+ bool enable,
+ enum hubp_ind_block_size independent_64b_blks);
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hubp1_program_surface_flip_and_addr(
+ struct hubp *hubp,
+ const struct dc_plane_address *address,
+ bool flip_immediate);
+
+-#endif
+ bool hubp1_is_flip_pending(struct hubp *hubp);
+
+ void hubp1_cursor_set_attributes(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index c8bd1c0cdb45..df59bd9185b5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -48,9 +48,7 @@
+ #include "clk_mgr.h"
+
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+
+ #define DC_LOGGER_INIT(logger)
+
+@@ -314,7 +312,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ /* Read shared OTG state registers for all DCNx */
+ optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /*
+ * For DCN2 and greater, a register on the OPP is used to
+ * determine if the CRTC is blanked instead of the OTG. So use
+@@ -326,9 +323,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);
+ else
+ s.blank_enabled = tg->funcs->is_blanked(tg);
+-#else
+- s.blank_enabled = tg->funcs->is_blanked(tg);
+-#endif
+
+ //only print if OTG master is enabled
+ if ((s.otg_enabled & 1) == 0)
+@@ -363,7 +357,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ }
+ DTN_INFO("\n");
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n");
+ for (i = 0; i < pool->res_cap->num_dsc; i++) {
+ struct display_stream_compressor *dsc = pool->dscs[i];
+@@ -418,7 +411,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ }
+ }
+ DTN_INFO("\n");
+-#endif
+
+ DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
+ "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
+@@ -1272,11 +1264,9 @@ static void dcn10_init_hw(struct dc *dc)
+ }
+
+ /* Power gate DSCs */
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+ if (dc->hwss.dsc_pg_control != NULL)
+ dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+-#endif
+
+ /* If taking control over from VBIOS, we may want to optimize our first
+ * mode set, so we need to skip powering down pipes until we know which
+@@ -2188,12 +2178,8 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
+ plane_state->format,
+ EXPANSION_MODE_ZERO,
+ plane_state->input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ plane_state->color_space,
+ NULL);
+-#else
+- plane_state->color_space);
+-#endif
+
+ //set scale and bias registers
+ dcn10_build_prescale_params(&bns_params, plane_state);
+@@ -2651,11 +2637,9 @@ static void dcn10_apply_ctx_for_surface(
+ if (num_planes > 0)
+ program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* Program secondary blending tree and writeback pipes */
+ if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
+ dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
+-#endif
+ if (interdependent_update)
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+index 1580f9c6d27d..24b68337d76e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+@@ -51,11 +51,9 @@ static const struct ipp_funcs dcn10_ipp_funcs = {
+ .ipp_destroy = dcn10_ipp_destroy
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static const struct ipp_funcs dcn20_ipp_funcs = {
+ .ipp_destroy = dcn10_ipp_destroy
+ };
+-#endif
+
+ void dcn10_ipp_construct(
+ struct dcn10_ipp *ippn10,
+@@ -74,7 +72,6 @@ void dcn10_ipp_construct(
+ ippn10->ipp_mask = ipp_mask;
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn20_ipp_construct(
+ struct dcn10_ipp *ippn10,
+ struct dc_context *ctx,
+@@ -91,4 +88,3 @@ void dcn20_ipp_construct(
+ ippn10->ipp_shift = ipp_shift;
+ ippn10->ipp_mask = ipp_mask;
+ }
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+index cfa24459242b..f0e0d07b0311 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+@@ -49,7 +49,6 @@
+ SRI(CURSOR_HOT_SPOT, CURSOR, id), \
+ SRI(CURSOR_DST_OFFSET, CURSOR, id)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define IPP_REG_LIST_DCN20(id) \
+ IPP_REG_LIST_DCN(id), \
+ SRI(CURSOR_SETTINGS, HUBPREQ, id), \
+@@ -60,7 +59,6 @@
+ SRI(CURSOR_POSITION, CURSOR0_, id), \
+ SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
+ SRI(CURSOR_DST_OFFSET, CURSOR0_, id)
+-#endif
+
+ #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
+ #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L
+@@ -105,7 +103,6 @@
+ IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
+ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define IPP_MASK_SH_LIST_DCN20(mask_sh) \
+ IPP_MASK_SH_LIST_DCN(mask_sh), \
+ IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+@@ -124,7 +121,6 @@
+ IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
+-#endif
+
+ #define IPP_DCN10_REG_FIELD_LIST(type) \
+ type CNVC_SURFACE_PIXEL_FORMAT; \
+@@ -196,13 +192,11 @@ void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
+ const struct dcn10_ipp_shift *ipp_shift,
+ const struct dcn10_ipp_mask *ipp_mask);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn20_ipp_construct(struct dcn10_ipp *ippn10,
+ struct dc_context *ctx,
+ int inst,
+ const struct dcn10_ipp_registers *regs,
+ const struct dcn10_ipp_shift *ipp_shift,
+ const struct dcn10_ipp_mask *ipp_mask);
+-#endif
+
+ #endif /* _DCN10_IPP_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 88fcc395adf5..7493a630f4dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -72,9 +72,7 @@
+ struct dcn10_link_enc_aux_registers {
+ uint32_t AUX_CONTROL;
+ uint32_t AUX_DPHY_RX_CONTROL0;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ uint32_t AUX_DPHY_TX_CONTROL;
+-#endif
+ };
+
+ struct dcn10_link_enc_hpd_registers {
+@@ -106,7 +104,6 @@ struct dcn10_link_enc_registers {
+ uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
+ uint32_t DP_SEC_CNTL1;
+ uint32_t TMDS_CTL_BITS;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* DCCG */
+ uint32_t CLOCK_ENABLE;
+ /* DIG */
+@@ -136,7 +133,6 @@ struct dcn10_link_enc_registers {
+ uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
+ uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
+-#endif
+ };
+
+ #define LE_SF(reg_name, field_name, post_fix)\
+@@ -242,7 +238,6 @@ struct dcn10_link_enc_registers {
+ type AUX_LS_READ_EN;\
+ type AUX_RX_RECEIVE_WINDOW
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
+ type RDPCS_PHY_DP_TX0_DATA_EN;\
+@@ -423,20 +418,15 @@ struct dcn10_link_enc_registers {
+ type AUX_TX_PRECHARGE_SYMBOLS; \
+ type AUX_MODE_DET_CHECK_DELAY;\
+ type DPCS_DBG_CBUS_DIS
+-#endif
+
+ struct dcn10_link_enc_shift {
+ DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+-#endif
+ };
+
+ struct dcn10_link_enc_mask {
+ DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+-#endif
+ };
+
+ struct dcn10_link_encoder {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+index b3f66e1de15d..04f863499cfb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+@@ -464,12 +464,10 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
+ .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
+ .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
+ .update_blending = mpc1_update_blending,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .set_denorm = NULL,
+ .set_denorm_clamp = NULL,
+ .set_output_csc = NULL,
+ .set_output_gamma = NULL,
+-#endif
+ };
+
+ void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index 8249b4429186..f2368be8e06d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -371,11 +371,9 @@ void opp1_program_oppbuf(
+ */
+ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* Controls the number of padded pixels at the end of a segment */
+ if (REG(OPPBUF_CONTROL1))
+ REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS, oppbuf->num_segment_padded_pixels);
+-#endif
+ }
+
+ void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
+@@ -402,10 +400,8 @@ static const struct opp_funcs dcn10_opp_funcs = {
+ .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
+ .opp_program_stereo = opp1_program_stereo,
+ .opp_pipe_clock_control = opp1_pipe_clock_control,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .opp_set_disp_pattern_generator = NULL,
+ .dpg_is_blanked = NULL,
+-#endif
+ .opp_destroy = opp1_destroy
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index 30c025918568..cd7412dc42d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -1502,7 +1502,6 @@ void dcn10_timing_generator_init(struct optc *optc1)
+ optc1->min_v_sync_width = 1;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
+ *
+ * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
+@@ -1515,15 +1514,12 @@ void dcn10_timing_generator_init(struct optc *optc1)
+ * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
+ *
+ */
+-#endif
+ bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+ {
+ bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+ && !timing->dsc_cfg.ycbcr422_simple);
+-#endif
+ return two_pix;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 4476bc8cdb4d..3afeb1a30f21 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -165,13 +165,11 @@ struct dcn_optc_registers {
+ uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
+ uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
+ uint32_t GSL_SOURCE_SELECT;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ uint32_t DWB_SOURCE_SELECT;
+ uint32_t OTG_DSC_START_POSITION;
+ uint32_t OPTC_DATA_FORMAT_CONTROL;
+ uint32_t OPTC_BYTES_PER_PIXEL;
+ uint32_t OPTC_WIDTH_CONTROL;
+-#endif
+ };
+
+ #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
+@@ -456,7 +454,6 @@ struct dcn_optc_registers {
+ type MANUAL_FLOW_CONTROL;\
+ type MANUAL_FLOW_CONTROL_SEL;
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+
+ #define TG_REG_FIELD_LIST(type) \
+ TG_REG_FIELD_LIST_DCN1_0(type)\
+@@ -479,12 +476,6 @@ struct dcn_optc_registers {
+ type OPTC_DWB0_SOURCE_SELECT;\
+ type OPTC_DWB1_SOURCE_SELECT;
+
+-#else
+-
+-#define TG_REG_FIELD_LIST(type) \
+- TG_REG_FIELD_LIST_DCN1_0(type)
+-
+-#endif
+
+
+ struct dcn_optc_shift {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index 2f00f2389e40..f9b9e221c698 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -163,14 +163,12 @@ struct dcn10_stream_enc_registers {
+ uint32_t DP_MSA_TIMING_PARAM3;
+ uint32_t DP_MSA_TIMING_PARAM4;
+ uint32_t HDMI_DB_CONTROL;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t DP_DSC_CNTL;
+ uint32_t DP_DSC_BYTES_PER_PIXEL;
+ uint32_t DME_CONTROL;
+ uint32_t DP_SEC_METADATA_TRANSMISSION;
+ uint32_t HDMI_METADATA_PACKET_CONTROL;
+ uint32_t DP_SEC_FRAMING4;
+-#endif
+ uint32_t DIG_CLOCK_PATTERN;
+ };
+
+@@ -466,7 +464,6 @@ struct dcn10_stream_enc_registers {
+ type DIG_SOURCE_SELECT;\
+ type DIG_CLOCK_PATTERN
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define SE_REG_FIELD_LIST_DCN2_0(type) \
+ type DP_DSC_MODE;\
+ type DP_DSC_SLICE_WIDTH;\
+@@ -485,20 +482,15 @@ struct dcn10_stream_enc_registers {
+ type DOLBY_VISION_EN;\
+ type DP_PIXEL_COMBINE;\
+ type DP_SST_SDP_SPLITTING
+-#endif
+
+ struct dcn10_stream_encoder_shift {
+ SE_REG_FIELD_LIST_DCN1_0(uint8_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ SE_REG_FIELD_LIST_DCN2_0(uint8_t);
+-#endif
+ };
+
+ struct dcn10_stream_encoder_mask {
+ SE_REG_FIELD_LIST_DCN1_0(uint32_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ SE_REG_FIELD_LIST_DCN2_0(uint32_t);
+-#endif
+ };
+
+ struct dcn10_stream_encoder {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index be3a614963c6..89c581196c4c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -6,9 +6,7 @@ DCN20 = dcn20_resource.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
+ dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \
+ dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o
+
+-ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DCN20 += dcn20_dsc.o
+-endif
+
+ CFLAGS_dcn20_resource.o := -mhard-float -msse
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index dc9944427d2f..0111545dac75 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -23,7 +23,6 @@
+ *
+ */
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "reg_helper.h"
+ #include "dcn20_dsc.h"
+ #include "dsc/dscc_types.h"
+@@ -734,4 +733,3 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const
+ }
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+index 4e2fb38390a4..9855a7ed0387 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+@@ -21,7 +21,6 @@
+ * Authors: AMD
+ *
+ */
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #ifndef __DCN20_DSC_H__
+ #define __DCN20_DSC_H__
+
+@@ -572,4 +571,3 @@ void dsc2_construct(struct dcn20_dsc *dsc,
+
+ #endif
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 4c60fa4b89e7..2823be75b071 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -485,7 +485,6 @@ void hubp2_program_pixel_format(
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 12);
+ break;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 112);
+@@ -506,7 +505,6 @@ void hubp2_program_pixel_format(
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 119);
+ break;
+-#endif
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 92117b6d0012..868099fbe8ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -33,9 +33,7 @@
+ #include "dcn10/dcn10_hw_sequencer.h"
+ #include "dcn20_hwseq.h"
+ #include "dce/dce_hwseq.h"
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dcn20/dcn20_dsc.h"
+-#endif
+ #include "abm.h"
+ #include "clk_mgr.h"
+ #include "dmcu.h"
+@@ -245,7 +243,6 @@ void dcn20_init_blank(
+ dcn20_hwss_wait_for_blank_complete(opp);
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ static void dcn20_dsc_pg_control(
+ struct dce_hwseq *hws,
+ unsigned int dsc_inst,
+@@ -322,7 +319,6 @@ static void dcn20_dsc_pg_control(
+ if (org_ip_request_cntl == 0)
+ REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+ }
+-#endif
+
+ static void dcn20_dpp_pg_control(
+ struct dce_hwseq *hws,
+@@ -1695,7 +1691,6 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
+
+ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dce_hwseq *hws = dc->hwseq;
+
+ if (pipe_ctx->stream_res.dsc) {
+@@ -1707,12 +1702,10 @@ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
+ }
+-#endif
+ }
+
+ static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dce_hwseq *hws = dc->hwseq;
+
+ if (pipe_ctx->stream_res.dsc) {
+@@ -1724,7 +1717,6 @@ static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
+ }
+-#endif
+ }
+
+ void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
+@@ -1923,11 +1915,9 @@ static void dcn20_reset_back_end_for_pipe(
+ }
+ }
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ else if (pipe_ctx->stream_res.dsc) {
+ dp_set_dsc_enable(pipe_ctx, false);
+ }
+-#endif
+
+ /* by upper caller loop, parent pipe: pipe0, will be reset last.
+ * back end share by all pipes and will be disable only when disable
+@@ -2439,11 +2429,7 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
+ dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
+ dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+-#else
+- dc->hwss.dsc_pg_control = NULL;
+-#endif
+ dc->hwss.disable_vga = dcn20_disable_vga;
+
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+index 0e0306d84cd8..e4ac73035c84 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+@@ -168,10 +168,8 @@ static struct mpll_cfg dcn2_mpll_cfg[] = {
+ void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
+ {
+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DC_LOG_DSC("%s FEC at link encoder inst %d",
+ enable ? "Enabling" : "Disabling", enc->id.enum_id);
+-#endif
+ REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
+ }
+
+@@ -192,7 +190,6 @@ bool enc2_fec_is_active(struct link_encoder *enc)
+ return (active != 0);
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
+ * into a dcn_dsc_state struct.
+ */
+@@ -205,7 +202,6 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
+ REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
+ REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
+ }
+-#endif
+
+ static bool update_cfg_data(
+ struct dcn10_link_encoder *enc10,
+@@ -316,9 +312,7 @@ void enc2_hw_init(struct link_encoder *enc)
+ }
+
+ static const struct link_encoder_funcs dcn20_link_enc_funcs = {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .read_state = link_enc2_read_state,
+-#endif
+ .validate_output_with_stream =
+ dcn10_link_encoder_validate_output_with_stream,
+ .hw_init = enc2_hw_init,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+index 0c98a0bbbd14..62dfd34c69f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+@@ -158,9 +158,7 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready);
+ bool enc2_fec_is_active(struct link_encoder *enc);
+ void enc2_hw_init(struct link_encoder *enc);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s);
+-#endif
+
+ void dcn20_link_encoder_enable_dp_output(
+ struct link_encoder *enc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 3b613fb93ef8..0e50dc9b611a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -167,7 +167,6 @@ void optc2_set_gsl_source_select(
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
+ void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
+ int x_position,
+@@ -201,7 +200,6 @@ void optc2_set_dsc_config(struct timing_generator *optc,
+ REG_UPDATE(OPTC_WIDTH_CONTROL,
+ OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
+ }
+-#endif
+
+ /**
+ * PTI i think is already done somewhere else for 2ka
+@@ -448,9 +446,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
+ .setup_global_swap_lock = NULL,
+ .get_crc = optc1_get_crc,
+ .configure_crc = optc1_configure_crc,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .set_dsc_config = optc2_set_dsc_config,
+-#endif
+ .set_dwb_source = optc2_set_dwb_source,
+ .set_odm_bypass = optc2_set_odm_bypass,
+ .set_odm_combine = optc2_set_odm_combine,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+index 32a58431fd09..9ae22146d2d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+@@ -86,12 +86,10 @@ void optc2_set_gsl_source_select(struct timing_generator *optc,
+ int group_idx,
+ uint32_t gsl_ready_signal);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void optc2_set_dsc_config(struct timing_generator *optc,
+ enum optc_dsc_mode dsc_mode,
+ uint32_t dsc_bytes_per_pixel,
+ uint32_t dsc_slice_width);
+-#endif
+
+ void optc2_set_odm_bypass(struct timing_generator *optc,
+ const struct dc_crtc_timing *dc_crtc_timing);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 3119714586dd..9f721d5bea3b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -43,9 +43,7 @@
+ #include "dcn10/dcn10_resource.h"
+ #include "dcn20_opp.h"
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dcn20_dsc.h"
+-#endif
+
+ #include "dcn20_link_encoder.h"
+ #include "dcn20_stream_encoder.h"
+@@ -93,11 +91,7 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+ .hostvm_max_page_table_levels = 4,
+ .hostvm_cached_page_table_levels = 0,
+ .pte_group_size_bytes = 2048,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .num_dsc = 6,
+-#else
+- .num_dsc = 0,
+-#endif
+ .rob_buffer_size_kbytes = 168,
+ .det_buffer_size_kbytes = 164,
+ .dpte_buffer_size_in_pte_reqs_luma = 84,
+@@ -742,7 +736,6 @@ static const struct dce110_aux_registers_mask aux_mask = {
+ };
+
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define dsc_regsDCN20(id)\
+ [id] = {\
+ DSC_REG_LIST_DCN20(id)\
+@@ -764,7 +757,6 @@ static const struct dcn20_dsc_shift dsc_shift = {
+ static const struct dcn20_dsc_mask dsc_mask = {
+ DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+ };
+-#endif
+
+ static const struct dccg_registers dccg_regs = {
+ DCCG_REG_LIST_DCN2()
+@@ -788,9 +780,7 @@ static const struct resource_caps res_cap_nv10 = {
+ .num_dwb = 1,
+ .num_ddc = 6,
+ .num_vmid = 16,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .num_dsc = 6,
+-#endif
+ };
+
+ static const struct dc_plane_cap plane_cap = {
+@@ -1211,7 +1201,6 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src)
+ *clk_src = NULL;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+
+ struct display_stream_compressor *dcn20_dsc_create(
+ struct dc_context *ctx, uint32_t inst)
+@@ -1234,7 +1223,6 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
+ *dsc = NULL;
+ }
+
+-#endif
+
+ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
+ {
+@@ -1247,12 +1235,10 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ if (pool->base.dscs[i] != NULL)
+ dcn20_dsc_destroy(&pool->base.dscs[i]);
+ }
+-#endif
+
+ if (pool->base.mpc != NULL) {
+ kfree(TO_DCN20_MPC(pool->base.mpc));
+@@ -1463,7 +1449,6 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state
+ return status;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+
+ static void acquire_dsc(struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+@@ -1497,10 +1482,8 @@ static void release_dsc(struct resource_context *res_ctx,
+ }
+ }
+
+-#endif
+
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+ struct dc_state *dc_ctx,
+ struct dc_stream_state *dc_stream)
+@@ -1552,7 +1535,6 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
+ else
+ return DC_OK;
+ }
+-#endif
+
+
+ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
+@@ -1564,11 +1546,9 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx,
+ if (result == DC_OK)
+ result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* Get a DSC if required and available */
+ if (result == DC_OK && dc_stream->timing.flags.DSC)
+ result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
+-#endif
+
+ if (result == DC_OK)
+ result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
+@@ -1581,9 +1561,7 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_
+ {
+ enum dc_status result = DC_OK;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
+-#endif
+
+ return result;
+ }
+@@ -1666,9 +1644,7 @@ bool dcn20_split_stream_for_odm(
+ next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
+ next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
+ next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ next_odm_pipe->stream_res.dsc = NULL;
+-#endif
+ if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
+ next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
+ next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
+@@ -1714,14 +1690,12 @@ bool dcn20_split_stream_for_odm(
+ sd->recout.x = 0;
+ }
+ next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (next_odm_pipe->stream->timing.flags.DSC == 1) {
+ acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
+ ASSERT(next_odm_pipe->stream_res.dsc);
+ if (next_odm_pipe->stream_res.dsc == NULL)
+ return false;
+ }
+-#endif
+
+ return true;
+ }
+@@ -1745,9 +1719,7 @@ void dcn20_split_stream_for_mpc(
+ secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
+ secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
+ secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ secondary_pipe->stream_res.dsc = NULL;
+-#endif
+ if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
+ ASSERT(!secondary_pipe->bottom_pipe);
+ secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
+@@ -1835,11 +1807,9 @@ int dcn20_populate_dml_pipes_from_context(
+ pipes[pipe_cnt].pipe.src.dcc = 0;
+ pipes[pipe_cnt].pipe.src.vm = 0;*/
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
+ /* todo: rotation?*/
+ pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
+-#endif
+ if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
+ pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
+ /* 1/2 vblank */
+@@ -1927,14 +1897,12 @@ int dcn20_populate_dml_pipes_from_context(
+ case COLOR_DEPTH_161616:
+ output_bpc = 16;
+ break;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ case COLOR_DEPTH_999:
+ output_bpc = 9;
+ break;
+ case COLOR_DEPTH_111111:
+ output_bpc = 11;
+ break;
+-#endif
+ default:
+ output_bpc = 8;
+ break;
+@@ -1962,10 +1930,8 @@ int dcn20_populate_dml_pipes_from_context(
+ pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
+ pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
+-#endif
+
+ /* todo: default max for now, until there is logic reflecting this in dc*/
+ pipes[pipe_cnt].dout.output_bpc = 12;
+@@ -2187,7 +2153,6 @@ void dcn20_set_mcif_arb_params(
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ {
+ int i;
+@@ -2221,7 +2186,6 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ }
+ return true;
+ }
+-#endif
+
+ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ struct resource_context *res_ctx,
+@@ -2324,10 +2288,8 @@ void dcn20_merge_pipes_for_validate(
+ odm_pipe->bottom_pipe = NULL;
+ odm_pipe->prev_odm_pipe = NULL;
+ odm_pipe->next_odm_pipe = NULL;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (odm_pipe->stream_res.dsc)
+ release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
+-#endif
+ /* Clear plane_res and stream_res */
+ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
+ memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
+@@ -2547,14 +2509,12 @@ bool dcn20_fast_validate_bw(
+ ASSERT(0);
+ }
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* Actual dsc count per stream dsc validation*/
+ if (!dcn20_validate_dsc(dc, context)) {
+ context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
+ DML_FAIL_DSC_VALIDATION_FAILURE;
+ goto validate_fail;
+ }
+-#endif
+
+ *vlevel_out = vlevel;
+
+@@ -3656,7 +3616,6 @@ static bool dcn20_resource_construct(
+ goto create_fail;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
+ if (pool->base.dscs[i] == NULL) {
+@@ -3665,7 +3624,6 @@ static bool dcn20_resource_construct(
+ goto create_fail;
+ }
+ }
+-#endif
+
+ if (!dcn20_dwbc_create(ctx, &pool->base)) {
+ BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index 7187e0f8eb28..840ca66c34e1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -127,9 +127,7 @@ int dcn20_validate_apply_pipe_split_flags(
+ struct dc_state *context,
+ int vlevel,
+ bool *split);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
+-#endif
+ void dcn20_split_stream_for_mpc(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index b909c526b7f9..3549c81b20b7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -203,7 +203,6 @@ static void enc2_stream_encoder_stop_hdmi_info_packets(
+ HDMI_GENERIC7_LINE, 0);
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+
+ /* Update GSP7 SDP 128 byte long */
+ static void enc2_update_gsp7_128_info_packet(
+@@ -358,7 +357,6 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s)
+ REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
+ }
+ }
+-#endif
+
+ /* Set Dynamic Metadata-configuration.
+ * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME
+@@ -438,10 +436,8 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+ {
+ bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+ && !timing->dsc_cfg.ycbcr422_simple);
+-#endif
+ return two_pix;
+ }
+
+@@ -587,11 +583,9 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ .dp_get_pixel_format =
+ enc1_stream_encoder_dp_get_pixel_format,
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .enc_read_state = enc2_read_state,
+ .dp_set_dsc_config = enc2_dp_set_dsc_config,
+ .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
+-#endif
+ .set_dynamic_metadata = enc2_set_dynamic_metadata,
+ .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+index e8a504ca5890..e45683ac871a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+@@ -323,9 +323,7 @@ void dcn21_link_encoder_disable_output(
+
+
+ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .read_state = link_enc2_read_state,
+-#endif
+ .validate_output_with_stream =
+ dcn10_link_encoder_validate_output_with_stream,
+ .hw_init = enc2_hw_init,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 9ec73b513488..f68f643a82af 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -88,11 +88,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
+ .gpuvm_max_page_table_levels = 1,
+ .hostvm_max_page_table_levels = 4,
+ .hostvm_cached_page_table_levels = 2,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .num_dsc = 3,
+-#else
+- .num_dsc = 0,
+-#endif
+ .rob_buffer_size_kbytes = 168,
+ .det_buffer_size_kbytes = 164,
+ .dpte_buffer_size_in_pte_reqs_luma = 44,
+@@ -538,7 +534,6 @@ static const struct dcn20_vmid_mask vmid_masks = {
+ DCN20_VMID_MASK_SH_LIST(_MASK)
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define dsc_regsDCN20(id)\
+ [id] = {\
+ DSC_REG_LIST_DCN20(id)\
+@@ -560,7 +555,6 @@ static const struct dcn20_dsc_shift dsc_shift = {
+ static const struct dcn20_dsc_mask dsc_mask = {
+ DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+ };
+-#endif
+
+ #define ipp_regs(id)\
+ [id] = {\
+@@ -757,9 +751,7 @@ static const struct resource_caps res_cap_rn = {
+ .num_dwb = 1,
+ .num_ddc = 5,
+ .num_vmid = 1,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .num_dsc = 3,
+-#endif
+ };
+
+ #ifdef DIAGS_BUILD
+@@ -784,9 +776,7 @@ static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
+ .num_pll = 4,
+ .num_dwb = 1,
+ .num_ddc = 4,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .num_dsc = 2,
+-#endif
+ };
+ #endif
+
+@@ -865,12 +855,10 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
+ }
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ if (pool->base.dscs[i] != NULL)
+ dcn20_dsc_destroy(&pool->base.dscs[i]);
+ }
+-#endif
+
+ if (pool->base.mpc != NULL) {
+ kfree(TO_DCN20_MPC(pool->base.mpc));
+@@ -1299,7 +1287,6 @@ static void read_dce_straps(
+
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+
+ struct display_stream_compressor *dcn21_dsc_create(
+ struct dc_context *ctx, uint32_t inst)
+@@ -1315,7 +1302,6 @@ struct display_stream_compressor *dcn21_dsc_create(
+ dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+ return &dsc->base;
+ }
+-#endif
+
+ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+ {
+@@ -1875,7 +1861,6 @@ static bool dcn21_resource_construct(
+ goto create_fail;
+ }
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
+ if (pool->base.dscs[i] == NULL) {
+@@ -1884,7 +1869,6 @@ static bool dcn21_resource_construct(
+ goto create_fail;
+ }
+ }
+-#endif
+
+ if (!dcn20_dwbc_create(ctx, &pool->base)) {
+ BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+index 94b75e942607..8bde1d688f2e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+@@ -118,13 +118,11 @@ bool dm_helpers_submit_i2c(
+ const struct dc_link *link,
+ struct i2c_command *cmd);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dm_helpers_dp_write_dsc_enable(
+ struct dc_context *ctx,
+ const struct dc_stream_state *stream,
+ bool enable
+ );
+-#endif
+ bool dm_helpers_is_dp_sink_present(
+ struct dc_link *link);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 95f3193da951..04d54283c94f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -41,9 +41,7 @@ enum pp_smu_ver {
+ */
+ PP_SMU_UNSUPPORTED,
+ PP_SMU_VER_RV,
+-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ PP_SMU_VER_NV,
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ PP_SMU_VER_RN,
+ #endif
+@@ -137,7 +135,6 @@ struct pp_smu_funcs_rv {
+ void (*set_pme_wa_enable)(struct pp_smu *pp);
+ };
+
+-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ /* Used by pp_smu_funcs_nv.set_voltage_by_freq
+ *
+ */
+@@ -241,7 +238,6 @@ struct pp_smu_funcs_nv {
+ enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,
+ BOOLEAN pstate_handshake_supported);
+ };
+-#endif
+
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
+@@ -285,9 +281,7 @@ struct pp_smu_funcs {
+ struct pp_smu ctx;
+ union {
+ struct pp_smu_funcs_rv rv_funcs;
+-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ struct pp_smu_funcs_nv nv_funcs;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ struct pp_smu_funcs_rn rn_funcs;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index 9cc2fe56ed64..e3d6546a08c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -43,7 +43,7 @@ endif
+
+ CFLAGS_display_mode_lib.o := $(dml_ccflags)
+
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ CFLAGS_display_mode_vba.o := $(dml_ccflags)
+ CFLAGS_display_mode_vba_20.o := $(dml_ccflags)
+ CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
+@@ -64,7 +64,7 @@ CFLAGS_dml_common_defs.o := $(dml_ccflags)
+ DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
+ dml_common_defs.o
+
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
+ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
+ endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index ba77957aefe3..945291d5ad98 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -23,7 +23,6 @@
+ *
+ */
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+
+ #include "../display_mode_lib.h"
+ #include "../dml_inline_defs.h"
+@@ -6126,4 +6125,3 @@ static double CalculateExtraLatency(
+ return CalculateExtraLatency;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+index a1f207cbb966..a4b103eb4b02 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+@@ -23,7 +23,6 @@
+ *
+ */
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+
+ #include "../display_mode_lib.h"
+ #include "../display_mode_vba.h"
+@@ -1820,4 +1819,3 @@ static void calculate_ttu_cursor(
+ }
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+index 1c97083b8d0b..55d4cb23a073 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+@@ -135,9 +135,7 @@ enum dm_validation_status {
+ DML_FAIL_DIO_SUPPORT,
+ DML_FAIL_NOT_ENOUGH_DSC,
+ DML_FAIL_DSC_CLK_REQUIRED,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DML_FAIL_DSC_VALIDATION_FAILURE,
+-#endif
+ DML_FAIL_URGENT_LATENCY,
+ DML_FAIL_REORDERING_BUFFER,
+ DML_FAIL_DISPCLK_DPPCLK,
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+index 704efefdcba8..9c6016e57d2b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+@@ -25,18 +25,15 @@
+
+ #include "display_mode_lib.h"
+ #include "dc_features.h"
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/display_mode_vba_20.h"
+ #include "dcn20/display_rq_dlg_calc_20.h"
+ #include "dcn20/display_mode_vba_20v2.h"
+ #include "dcn20/display_rq_dlg_calc_20v2.h"
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ #include "dcn21/display_mode_vba_21.h"
+ #include "dcn21/display_rq_dlg_calc_21.h"
+ #endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ const struct dml_funcs dml20_funcs = {
+ .validate = dml20_ModeSupportAndSystemConfigurationFull,
+ .recalculate = dml20_recalculate,
+@@ -50,7 +47,6 @@ const struct dml_funcs dml20v2_funcs = {
+ .rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg,
+ .rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg
+ };
+-#endif
+
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ const struct dml_funcs dml21_funcs = {
+@@ -70,14 +66,12 @@ void dml_init_instance(struct display_mode_lib *lib,
+ lib->ip = *ip_params;
+ lib->project = project;
+ switch (project) {
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ case DML_PROJECT_NAVI10:
+ lib->funcs = dml20_funcs;
+ break;
+ case DML_PROJECT_NAVI10v2:
+ lib->funcs = dml20v2_funcs;
+ break;
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ case DML_PROJECT_DCN21:
+ lib->funcs = dml21_funcs;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+index d8c59aa356b6..212188be1ec1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+@@ -27,17 +27,13 @@
+
+
+ #include "dml_common_defs.h"
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #include "display_mode_vba.h"
+-#endif
+
+ enum dml_project {
+ DML_PROJECT_UNDEFINED,
+ DML_PROJECT_RAVEN1,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DML_PROJECT_NAVI10,
+ DML_PROJECT_NAVI10v2,
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ DML_PROJECT_DCN21,
+ #endif
+@@ -70,9 +66,7 @@ struct display_mode_lib {
+ struct _vcs_dpi_ip_params_st ip;
+ struct _vcs_dpi_soc_bounding_box_st soc;
+ enum dml_project project;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct vba_vars_st vba;
+-#endif
+ struct dal_logger *logger;
+ struct dml_funcs funcs;
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index 19356180cbb6..516396d53d01 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -146,7 +146,6 @@ struct _vcs_dpi_ip_params_st {
+ unsigned int writeback_interface_buffer_size_kbytes;
+ unsigned int writeback_line_buffer_buffer_size;
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ unsigned int writeback_10bpc420_supported;
+ double writeback_max_hscl_ratio;
+ double writeback_max_vscl_ratio;
+@@ -156,7 +155,6 @@ struct _vcs_dpi_ip_params_st {
+ unsigned int writeback_max_vscl_taps;
+ unsigned int writeback_line_buffer_luma_buffer_size;
+ unsigned int writeback_line_buffer_chroma_buffer_size;
+-#endif
+
+ unsigned int max_page_table_levels;
+ unsigned int max_num_dpp;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index da5e9d2fd6b6..b1c2b79e42b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -23,7 +23,6 @@
+ *
+ */
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+
+ #include "display_mode_lib.h"
+ #include "display_mode_vba.h"
+@@ -862,4 +861,3 @@ double CalculateWriteBackDISPCLK(
+ return CalculateWriteBackDISPCLK;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 6d8b5c61de68..3eb657ed5714 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -23,7 +23,6 @@
+ *
+ */
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+
+ #ifndef __DML2_DISPLAY_MODE_VBA_H__
+ #define __DML2_DISPLAY_MODE_VBA_H__
+@@ -872,4 +871,3 @@ double CalculateWriteBackDISPCLK(
+ unsigned int WritebackChromaLineBufferWidth);
+
+ #endif /* _DML2_DISPLAY_MODE_VBA_H_ */
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index f76a72a96631..ec86ba73a039 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -22,7 +22,6 @@
+ * Author: AMD
+ */
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dc_hw_types.h"
+ #include "dsc.h"
+ #include <drm/drm_dp_helper.h>
+@@ -907,4 +906,3 @@ bool dc_dsc_compute_config(
+ timing, dsc_min_slice_height_override, dsc_cfg);
+ return is_dsc_possible;
+ }
+-#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h b/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
+index 020ad8f685ea..9f70e87b3ecb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ /*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -51,4 +50,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par
+
+ #endif
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h b/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
+index f66d006eac5d..e5fac9f4181d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
++++ b/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ /*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -703,4 +702,3 @@ const qp_table qp_table_422_8bpc_max = {
+ { 16, { 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 4} }
+ };
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+index 76c4b12d6824..03ae15946c6d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+
+ /*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -252,4 +251,3 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com
+ rc->rc_buf_thresh[13] = 8064;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+index f1d6e793bc61..b6b1f09c2009 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ /*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -82,4 +81,3 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com
+
+ #endif
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+index 73172fd0b529..1f6e63b71456 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ /*
+ * Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+@@ -144,4 +143,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par
+ return ret;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+index b3062275711e..7791cd29fc18 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+@@ -67,12 +67,10 @@ GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
+ AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
+
+ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10)
+-endif
+
+ ###############################################################################
+ # DCN 2
+ ###############################################################################
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ GPIO_DCN20 = hw_translate_dcn20.o hw_factory_dcn20.o
+
+ AMD_DAL_GPIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn20/,$(GPIO_DCN20))
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+index 2664cb22dfe7..83f798cb8b21 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+@@ -22,7 +22,6 @@
+ * Authors: AMD
+ *
+ */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dm_services.h"
+ #include "include/gpio_types.h"
+ #include "../hw_factory.h"
+@@ -258,4 +257,3 @@ void dal_hw_factory_dcn20_init(struct hw_factory *factory)
+ factory->funcs = &funcs;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
+index 43a4ce7aa3bf..0fd9b315bd7a 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
+@@ -22,7 +22,6 @@
+ * Authors: AMD
+ *
+ */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifndef __DAL_HW_FACTORY_DCN20_H__
+ #define __DAL_HW_FACTORY_DCN20_H__
+
+@@ -30,4 +29,3 @@
+ void dal_hw_factory_dcn20_init(struct hw_factory *factory);
+
+ #endif /* __DAL_HW_FACTORY_DCN20_H__ */
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+index 915e896e0e91..52ba62b3b5e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+@@ -26,7 +26,6 @@
+ /*
+ * Pre-requisites: headers required by header of this unit
+ */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "hw_translate_dcn20.h"
+
+ #include "dm_services.h"
+@@ -379,4 +378,3 @@ void dal_hw_translate_dcn20_init(struct hw_translate *tr)
+ tr->funcs = &funcs;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
+index 01f52c7bed86..5f7a35530e26 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
+@@ -22,7 +22,6 @@
+ * Authors: AMD
+ *
+ */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifndef __DAL_HW_TRANSLATE_DCN20_H__
+ #define __DAL_HW_TRANSLATE_DCN20_H__
+
+@@ -32,4 +31,3 @@ struct hw_translate;
+ void dal_hw_translate_dcn20_init(struct hw_translate *tr);
+
+ #endif /* __DAL_HW_TRANSLATE_DCN20_H__ */
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+index 8572678f8d4f..907c5911eb9e 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+@@ -22,7 +22,6 @@
+ * Authors: AMD
+ *
+ */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dm_services.h"
+ #include "include/gpio_types.h"
+ #include "../hw_factory.h"
+@@ -239,4 +238,3 @@ void dal_hw_factory_dcn21_init(struct hw_factory *factory)
+ factory->funcs = &funcs;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+index fbb58fb8c318..291966efe63d 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+@@ -26,7 +26,6 @@
+ /*
+ * Pre-requisites: headers required by header of this unit
+ */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "hw_translate_dcn21.h"
+
+ #include "dm_services.h"
+@@ -382,4 +381,3 @@ void dal_hw_translate_dcn21_init(struct hw_translate *tr)
+ tr->funcs = &funcs;
+ }
+
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
+index f91e85b04956..308a543178a5 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
+@@ -48,13 +48,11 @@
+ DDC_GPIO_REG_LIST(cd,id),\
+ .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define DDC_REG_LIST_DCN2(cd, id) \
+ DDC_GPIO_REG_LIST(cd, id),\
+ .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
+ .phy_aux_cntl = REG(PHY_AUX_CNTL), \
+ .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
+-#endif
+
+ #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
+ .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
+@@ -90,13 +88,11 @@
+ DDC_GPIO_I2C_REG_LIST(cd),\
+ .ddc_setup = 0
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define DDC_I2C_REG_LIST_DCN2(cd) \
+ DDC_GPIO_I2C_REG_LIST(cd),\
+ .ddc_setup = 0,\
+ .phy_aux_cntl = REG(PHY_AUX_CNTL), \
+ .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
+-#endif
+ #define DDC_MASK_SH_LIST_COMMON(mask_sh) \
+ SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
+ SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
+@@ -110,22 +106,18 @@
+ SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
+ SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \
+ {DDC_MASK_SH_LIST_COMMON(mask_sh),\
+ 0,\
+ 0,\
+ (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
+ (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
+-#endif
+
+ struct ddc_registers {
+ struct gpio_registers gpio;
+ uint32_t ddc_setup;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t phy_aux_cntl;
+ uint32_t dc_gpio_aux_ctrl_5;
+-#endif
+ };
+
+ struct ddc_sh_mask {
+@@ -140,11 +132,9 @@ struct ddc_sh_mask {
+ /* i2cpad_mask */
+ uint32_t DC_GPIO_SDA_PD_DIS;
+ uint32_t DC_GPIO_SCL_PD_DIS;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ //phy_aux_cntl
+ uint32_t AUX_PAD_RXSEL;
+ uint32_t DDC_PAD_I2CMODE;
+-#endif
+ };
+
+
+@@ -180,7 +170,6 @@ struct ddc_sh_mask {
+ {\
+ DDC_I2C_REG_LIST(SCL)\
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define ddc_data_regs_dcn2(id) \
+ {\
+ DDC_REG_LIST_DCN2(DATA, id)\
+@@ -200,7 +189,6 @@ struct ddc_sh_mask {
+ {\
+ DDC_REG_LIST_DCN2(SCL)\
+ }
+-#endif
+
+
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+index 95d1c44a1d47..847da5a76b70 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+@@ -147,7 +147,6 @@ static enum gpio_result set_config(
+ AUX_PAD1_MODE, 0);
+ }
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
+ REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1);
+ }
+@@ -155,7 +154,6 @@ static enum gpio_result set_config(
+ if (ddc->regs->phy_aux_cntl != 0) {
+ REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1);
+ }
+-#endif
+ return GPIO_RESULT_OK;
+ case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
+ /* set the AUX pad mode */
+@@ -163,12 +161,10 @@ static enum gpio_result set_config(
+ REG_SET(gpio.MASK_reg, regval,
+ AUX_PAD1_MODE, 1);
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
+ REG_UPDATE(dc_gpio_aux_ctrl_5,
+ DDC_PAD_I2CMODE, 0);
+ }
+-#endif
+
+ return GPIO_RESULT_OK;
+ case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+index cb5857c8c7e9..18b9fab15676 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+@@ -46,9 +46,7 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "dcn10/hw_factory_dcn10.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/hw_factory_dcn20.h"
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #include "dcn21/hw_factory_dcn21.h"
+ #endif
+@@ -93,17 +91,15 @@ bool dal_hw_factory_init(
+ case DCN_VERSION_1_01:
+ dal_hw_factory_dcn10_init(factory);
+ return true;
+-#endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case DCN_VERSION_2_0:
+ dal_hw_factory_dcn20_init(factory);
+ return true;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case DCN_VERSION_2_1:
+ dal_hw_factory_dcn21_init(factory);
+ return true;
++#endif
+ #endif
+
+ default:
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+index f2046f55d6a8..8e10bff4c074 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+@@ -46,9 +46,7 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "dcn10/hw_translate_dcn10.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/hw_translate_dcn20.h"
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #include "dcn21/hw_translate_dcn21.h"
+ #endif
+@@ -90,17 +88,15 @@ bool dal_hw_translate_init(
+ case DCN_VERSION_1_01:
+ dal_hw_translate_dcn10_init(translate);
+ return true;
+-#endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case DCN_VERSION_2_0:
+ dal_hw_translate_dcn20_init(translate);
+ return true;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case DCN_VERSION_2_1:
+ dal_hw_translate_dcn21_init(translate);
+ return true;
++#endif
+ #endif
+
+ default:
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+index fd39e2abe2ed..4ead89dd7c41 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+@@ -43,10 +43,8 @@ enum dc_status {
+ DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */
+ DC_FAIL_SCALING = 14,
+ DC_FAIL_DP_LINK_TRAINING = 15,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DC_FAIL_DSC_VALIDATE = 16,
+ DC_NO_DSC_RESOURCE = 17,
+-#endif
+ DC_FAIL_UNSUPPORTED_1 = 18,
+ DC_FAIL_CLK_EXCEED_MAX = 21,
+ DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index 67efc8094ae7..d7018e894bc2 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -36,10 +36,8 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "mpc.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dwb.h"
+ #include "mcif_wb.h"
+-#endif
+
+ #define MAX_CLOCK_SOURCES 7
+
+@@ -135,7 +133,6 @@ struct resource_funcs {
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*populate_dml_writeback_from_context)(
+ struct dc *dc,
+ struct resource_context *res_ctx,
+@@ -146,7 +143,6 @@ struct resource_funcs {
+ struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt);
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ void (*update_bw_bounding_box)(
+ struct dc *dc,
+@@ -180,7 +176,6 @@ struct resource_pool {
+ struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
+ bool i2c_hw_buffer_in_use;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dwbc *dwbc[MAX_DWB_PIPES];
+ struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
+ struct {
+@@ -188,11 +183,8 @@ struct resource_pool {
+ unsigned int gsl_1:1;
+ unsigned int gsl_2:1;
+ } gsl_groups;
+-#endif
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct display_stream_compressor *dscs[MAX_PIPES];
+-#endif
+
+ unsigned int pipe_count;
+ unsigned int underlay_pipe_index;
+@@ -206,9 +198,7 @@ struct resource_pool {
+ unsigned int timing_generator_count;
+ unsigned int mpcc_count;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ unsigned int writeback_pipe_count;
+-#endif
+ /*
+ * reserved clock source for DP
+ */
+@@ -240,9 +230,7 @@ struct dcn_fe_bandwidth {
+
+ struct stream_resource {
+ struct output_pixel_processor *opp;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct display_stream_compressor *dsc;
+-#endif
+ struct timing_generator *tg;
+ struct stream_encoder *stream_enc;
+ struct audio *audio;
+@@ -251,12 +239,10 @@ struct stream_resource {
+ struct encoder_info_frame encoder_info_frame;
+
+ struct abm *abm;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* There are only (num_pipes+1)/2 groups. 0 means unassigned,
+ * otherwise it's using group number 'gsl_group-1'
+ */
+ uint8_t gsl_group;
+-#endif
+ };
+
+ struct plane_resource {
+@@ -315,10 +301,8 @@ struct pipe_ctx {
+ struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
+ #endif
+ union pipe_update_flags update_flags;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dwbc *dwbc;
+ struct mcif_wb *mcif_wb;
+-#endif
+ };
+
+ struct resource_context {
+@@ -327,9 +311,7 @@ struct resource_context {
+ bool is_audio_acquired[MAX_PIPES];
+ uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
+ uint8_t dp_clock_source_ref_count;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool is_dsc_acquired[MAX_PIPES];
+-#endif
+ };
+
+ struct dce_bw_output {
+@@ -349,18 +331,14 @@ struct dce_bw_output {
+ int blackout_recovery_time_us;
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dcn_bw_writeback {
+ struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
+ };
+-#endif
+
+ struct dcn_bw_output {
+ struct dc_clocks clk;
+ struct dcn_watermark_set watermarks;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dcn_bw_writeback bw_writeback;
+-#endif
+ };
+
+ union bw_output {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 1e6ff6eb5bfc..4879cf54d8f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -75,13 +75,11 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
+ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
+ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void dp_set_fec_ready(struct dc_link *link, bool ready);
+ void dp_set_fec_enable(struct dc_link *link, bool enable);
+ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
+ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
+ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
+ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
+-#endif
+
+ #endif /* __DC_LINK_DP_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index a17a77192690..862952c0286a 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -96,12 +96,10 @@ enum dentist_divider_range {
+ .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
+ .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define CLK_REG_LIST_NV10() \
+ SR(DENTIST_DISPCLK_CNTL), \
+ CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
+ CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
+-#endif
+
+ #define CLK_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+@@ -120,7 +118,6 @@ enum dentist_divider_range {
+ CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
+ CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
+ CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
+ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
+@@ -130,7 +127,6 @@ enum dentist_divider_range {
+ CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+ CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
+ CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
+-#endif
+
+ #define CLK_REG_FIELD_LIST(type) \
+ type DPREFCLK_SRC_SEL; \
+@@ -143,30 +139,24 @@ enum dentist_divider_range {
+ ****************** Clock Manager Private Structures ***********************************
+ ***************************************************************************************
+ */
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define CLK20_REG_FIELD_LIST(type) \
+ type DENTIST_DPPCLK_WDIVIDER; \
+ type DENTIST_DPPCLK_CHG_DONE; \
+ type FbMult_int; \
+ type FbMult_frac;
+-#endif
+
+ #define VBIOS_SMU_REG_FIELD_LIST(type) \
+ type CONTENT;
+
+ struct clk_mgr_shift {
+ CLK_REG_FIELD_LIST(uint8_t)
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ CLK20_REG_FIELD_LIST(uint8_t)
+-#endif
+ VBIOS_SMU_REG_FIELD_LIST(uint32_t)
+ };
+
+ struct clk_mgr_mask {
+ CLK_REG_FIELD_LIST(uint32_t)
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ CLK20_REG_FIELD_LIST(uint32_t)
+-#endif
+ VBIOS_SMU_REG_FIELD_LIST(uint32_t)
+ };
+
+@@ -174,10 +164,8 @@ struct clk_mgr_registers {
+ uint32_t DPREFCLK_CNTL;
+ uint32_t DENTIST_DISPCLK_CNTL;
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ uint32_t CLK3_CLK2_DFS_CNTL;
+ uint32_t CLK3_CLK_PLL_REQ;
+-#endif
+
+ uint32_t MP1_SMN_C2PMSG_67;
+ uint32_t MP1_SMN_C2PMSG_83;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index c81a17aeaa25..c0dc1d0f5cae 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -52,7 +52,6 @@ struct dcn_hubbub_wm {
+ struct dcn_hubbub_wm_set sets[4];
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dcn_hubbub_page_table_depth {
+ DCN_PAGE_TABLE_DEPTH_1_LEVEL,
+ DCN_PAGE_TABLE_DEPTH_2_LEVEL,
+@@ -101,13 +100,11 @@ struct hubbub_addr_config {
+ } default_addrs;
+ };
+
+-#endif
+ struct hubbub_funcs {
+ void (*update_dchub)(
+ struct hubbub *hubbub,
+ struct dchub_init_data *dh_data);
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ int (*init_dchub_sys_ctx)(
+ struct hubbub *hubbub,
+ struct dcn_hubbub_phys_addr_config *pa_config);
+@@ -116,7 +113,6 @@ struct hubbub_funcs {
+ struct dcn_hubbub_virt_addr_config *va_config,
+ int vmid);
+
+-#endif
+ bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
+ const struct dc_dcc_surface_param *input,
+ struct dc_surface_dcc_cap *output);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+index 474c7194a9f8..125e42dbd3c5 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+@@ -36,14 +36,10 @@ struct dpp {
+ struct dpp_caps *caps;
+ struct pwl_params regamma_params;
+ struct pwl_params degamma_params;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dpp_cursor_attributes cur_attr;
+-#endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct pwl_params shaper_params;
+ bool cm_bypass_mode;
+-#endif
+ };
+
+ struct dpp_input_csc_matrix {
+@@ -56,7 +52,6 @@ struct dpp_grph_csc_adjustment {
+ enum graphics_gamut_adjust_type gamut_adjust_type;
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct cnv_color_keyer_params {
+ int color_keyer_en;
+ int color_keyer_mode;
+@@ -82,7 +77,6 @@ struct cnv_alpha_2bit_lut {
+ int lut2;
+ int lut3;
+ };
+-#endif
+
+ struct dcn_dpp_state {
+ uint32_t is_enabled;
+@@ -190,12 +184,8 @@ struct dpp_funcs {
+ enum surface_pixel_format format,
+ enum expansion_mode mode,
+ struct dc_csc_transform input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dc_color_space input_color_space,
+ struct cnv_alpha_2bit_lut *alpha_2bit_lut);
+-#else
+- enum dc_color_space input_color_space);
+-#endif
+
+ void (*dpp_full_bypass)(struct dpp *dpp_base);
+
+@@ -224,7 +214,6 @@ struct dpp_funcs {
+ bool dppclk_div,
+ bool enable);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool (*dpp_program_blnd_lut)(
+ struct dpp *dpp,
+ const struct pwl_params *params);
+@@ -237,7 +226,6 @@ struct dpp_funcs {
+ void (*dpp_cnv_set_alpha_keyer)(
+ struct dpp *dpp_base,
+ struct cnv_color_keyer_params *color_keyer);
+-#endif
+ };
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+index c6ff3d78b435..c59740084ebc 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+@@ -22,7 +22,6 @@
+ * Authors: AMD
+ *
+ */
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #ifndef __DAL_DSC_H__
+ #define __DAL_DSC_H__
+
+@@ -98,4 +97,3 @@ struct dsc_funcs {
+ };
+
+ #endif
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+index ff1a07b35c85..aed67754e81b 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+@@ -51,11 +51,7 @@ enum dwb_source {
+ dwb_src_otg3, /* for DCN1.x/DCN2.x */
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* DCN1.x, DCN2.x support 2 pipes */
+-#else
+-/* DCN1.x supports 2 pipes */
+-#endif
+ enum dwb_pipe {
+ dwb_pipe0 = 0,
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+@@ -64,7 +60,6 @@ enum dwb_pipe {
+ dwb_pipe_max_num,
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ enum dwb_frame_capture_enable {
+ DWB_FRAME_CAPTURE_DISABLE = 0,
+ DWB_FRAME_CAPTURE_ENABLE = 1,
+@@ -77,9 +72,7 @@ enum wbscl_coef_filter_type_sel {
+ WBSCL_COEF_CHROMA_HORZ_FILTER = 3
+ };
+
+-#endif
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dwb_warmup_params {
+ bool warmup_en; /* false: normal mode, true: enable pattern generator */
+ bool warmup_mode; /* false: 420, true: 444 */
+@@ -88,7 +81,6 @@ struct dwb_warmup_params {
+ int warmup_width; /* Pattern width (pixels) */
+ int warmup_height; /* Pattern height (lines) */
+ };
+-#endif
+
+ struct dwb_caps {
+ enum dce_version hw_version; /* DCN engine version. */
+@@ -150,13 +142,11 @@ struct dwbc_funcs {
+ struct dwbc *dwbc,
+ bool is_new_content);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ void (*set_warmup)(
+ struct dwbc *dwbc,
+ struct dwb_warmup_params *warmup_params);
+
+-#endif
+
+ bool (*get_dwb_status)(
+ struct dwbc *dwbc);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 9def990d40a6..9793da0f3c7e 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -38,9 +38,7 @@ enum cursor_pitch {
+ };
+
+ enum cursor_lines_per_chunk {
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */
+-#endif
+ CURSOR_LINE_PER_CHUNK_2 = 1,
+ CURSOR_LINE_PER_CHUNK_4,
+ CURSOR_LINE_PER_CHUNK_8,
+@@ -139,7 +137,6 @@ struct hubp_funcs {
+ unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
+ void (*hubp_init)(struct hubp *hubp);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*dmdata_set_attributes)(
+ struct hubp *hubp,
+ const struct dc_dmdata_attributes *attr);
+@@ -159,7 +156,6 @@ struct hubp_funcs {
+ void (*hubp_set_flip_control_surface_gsl)(
+ struct hubp *hubp,
+ bool enable);
+-#endif
+
+ void (*validate_dml_output)(
+ struct hubp *hubp,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+index 91fda51e5370..75d419081e76 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+@@ -36,9 +36,7 @@
+
+ #define MAX_AUDIOS 7
+ #define MAX_PIPES 6
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define MAX_DWB_PIPES 1
+-#endif
+
+ struct gamma_curve {
+ uint32_t offset;
+@@ -81,7 +79,6 @@ struct pwl_result_data {
+ uint32_t delta_blue_reg;
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_rgb {
+ uint32_t red;
+ uint32_t green;
+@@ -110,7 +107,6 @@ struct tetrahedral_params {
+ bool use_12bits;
+
+ };
+-#endif
+
+ /* arr_curve_points - regamma regions/segments specification
+ * arr_points - beginning and end point specified separately (only one on DCE)
+@@ -195,13 +191,11 @@ enum opp_regamma {
+ OPP_REGAMMA_USER
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ enum optc_dsc_mode {
+ OPTC_DSC_DISABLED = 0,
+ OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
+ OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
+ };
+-#endif
+
+ struct dc_bias_and_scale {
+ uint16_t scale_red;
+@@ -224,12 +218,8 @@ enum test_pattern_mode {
+ TEST_PATTERN_MODE_VERTICALBARS,
+ TEST_PATTERN_MODE_HORIZONTALBARS,
+ TEST_PATTERN_MODE_SINGLERAMP_RGB,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ TEST_PATTERN_MODE_DUALRAMP_RGB,
+ TEST_PATTERN_MODE_XR_BIAS_RGB
+-#else
+- TEST_PATTERN_MODE_DUALRAMP_RGB
+-#endif
+ };
+
+ enum test_pattern_color_format {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+index af57751ed8a1..fb748f082c56 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+@@ -113,12 +113,9 @@ struct link_encoder {
+ struct encoder_feature_support features;
+ enum transmitter transmitter;
+ enum hpd_source_id hpd_source;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool usbc_combo_phy;
+-#endif
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct link_enc_state {
+
+ uint32_t dphy_fec_en;
+@@ -127,13 +124,10 @@ struct link_enc_state {
+ uint32_t dp_link_training_complete;
+
+ };
+-#endif
+
+ struct link_encoder_funcs {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void (*read_state)(
+ struct link_encoder *enc, struct link_enc_state *s);
+-#endif
+ bool (*validate_output_with_stream)(
+ struct link_encoder *enc, const struct dc_stream_state *stream);
+ void (*hw_init)(struct link_encoder *enc);
+@@ -175,7 +169,6 @@ struct link_encoder_funcs {
+ unsigned int (*get_dig_frontend)(struct link_encoder *enc);
+ void (*destroy)(struct link_encoder **enc);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*fec_set_enable)(struct link_encoder *enc,
+ bool enable);
+
+@@ -183,7 +176,6 @@ struct link_encoder_funcs {
+ bool ready);
+
+ bool (*fec_is_active)(struct link_encoder *enc);
+-#endif
+ bool (*is_in_alt_mode) (struct link_encoder *enc);
+
+ void (*get_max_link_cap)(struct link_encoder *enc,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+index 58826be81395..094afc4c8173 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+@@ -31,9 +31,7 @@
+ #define MAX_MPCC 6
+ #define MAX_OPP 6
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define MAX_DWB 1
+-#endif
+
+ enum mpc_output_csc_mode {
+ MPC_OUTPUT_CSC_DISABLE = 0,
+@@ -66,14 +64,12 @@ struct mpcc_blnd_cfg {
+ int global_alpha;
+ bool overlap_only;
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* MPCC top/bottom gain settings */
+ int bottom_gain_mode;
+ int background_color_bpc;
+ int top_gain;
+ int bottom_inside_gain;
+ int bottom_outside_gain;
+-#endif
+ };
+
+ struct mpcc_sm_cfg {
+@@ -90,7 +86,6 @@ struct mpcc_sm_cfg {
+ int force_next_field_polarity;
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct mpc_denorm_clamp {
+ int clamp_max_r_cr;
+ int clamp_min_r_cr;
+@@ -99,7 +94,6 @@ struct mpc_denorm_clamp {
+ int clamp_max_b_cb;
+ int clamp_min_b_cb;
+ };
+-#endif
+
+ /*
+ * MPCC connection and blending configuration for a single MPCC instance.
+@@ -126,10 +120,8 @@ struct mpc {
+ struct dc_context *ctx;
+
+ struct mpcc mpcc_array[MAX_MPCC];
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct pwl_params blender_params;
+ bool cm_bypass_mode;
+-#endif
+ };
+
+ struct mpcc_state {
+@@ -230,7 +222,6 @@ struct mpc_funcs {
+ struct mpc *mpc,
+ struct mpc_tree *tree);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*set_denorm)(struct mpc *mpc,
+ int opp_id,
+ enum dc_color_depth output_depth);
+@@ -258,7 +249,6 @@ struct mpc_funcs {
+ struct mpc *mpc,
+ int mpcc_id,
+ bool power_on);
+-#endif
+
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index b01ff30145fd..7575564b2265 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -263,9 +263,7 @@ struct oppbuf_params {
+ enum oppbuf_display_segmentation mso_segmentation;
+ uint32_t mso_overlap_pixel_num;
+ uint32_t pixel_repetition;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t num_segment_padded_pixels;
+-#endif
+ };
+
+ struct opp_funcs {
+@@ -305,7 +303,6 @@ struct opp_funcs {
+ struct output_pixel_processor *opp,
+ bool enable);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*opp_set_disp_pattern_generator)(
+ struct output_pixel_processor *opp,
+ enum controller_dp_test_pattern test_pattern,
+@@ -325,7 +322,6 @@ struct opp_funcs {
+ void (*opp_program_left_edge_extra_pixel)(
+ struct output_pixel_processor *opp,
+ bool count);
+-#endif
+
+ };
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index c0b93d51ca8d..351b387ad606 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -65,13 +65,11 @@ struct audio_clock_info {
+ uint32_t cts_48khz;
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ enum dynamic_metadata_mode {
+ dmdata_dp,
+ dmdata_hdmi,
+ dmdata_dolby_vision
+ };
+-#endif
+
+ struct encoder_info_frame {
+ /* auxiliary video information */
+@@ -90,9 +88,7 @@ struct encoder_info_frame {
+ struct encoder_unblank_param {
+ struct dc_link_settings link_settings;
+ struct dc_crtc_timing timing;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ int opp_cnt;
+-#endif
+ };
+
+ struct encoder_set_dp_phy_pattern_param {
+@@ -109,7 +105,6 @@ struct stream_encoder {
+ enum engine_id id;
+ };
+
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct enc_state {
+ uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state.
+ uint32_t dsc_slice_width;
+@@ -119,7 +114,6 @@ struct enc_state {
+ uint32_t sec_gsp_pps_enable;
+ uint32_t sec_stream_enable;
+ };
+-#endif
+
+ struct stream_encoder_funcs {
+ void (*dp_set_stream_attribute)(
+@@ -220,8 +214,6 @@ struct stream_encoder_funcs {
+ enum dc_pixel_encoding *encoding,
+ enum dc_color_depth *depth);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
+
+ void (*dp_set_dsc_config)(
+@@ -233,7 +225,6 @@ struct stream_encoder_funcs {
+ void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc,
+ bool enable,
+ uint8_t *dsc_packed_pps);
+-#endif
+
+ void (*set_dynamic_metadata)(struct stream_encoder *enc,
+ bool enable,
+@@ -243,7 +234,6 @@ struct stream_encoder_funcs {
+ void (*dp_set_odm_combine)(
+ struct stream_encoder *enc,
+ bool odm_combine);
+-#endif
+ };
+
+ #endif /* STREAM_ENCODER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index 27c73caf74ee..2d3efd71fa51 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -195,10 +195,8 @@ struct timing_generator_funcs {
+ void (*lock)(struct timing_generator *tg);
+ void (*lock_doublebuffer_disable)(struct timing_generator *tg);
+ void (*lock_doublebuffer_enable)(struct timing_generator *tg);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void(*triplebuffer_unlock)(struct timing_generator *tg);
+ void(*triplebuffer_lock)(struct timing_generator *tg);
+-#endif
+ void (*enable_reset_trigger)(struct timing_generator *tg,
+ int source_tg_inst);
+ void (*enable_crtc_reset)(struct timing_generator *tg,
+@@ -235,7 +233,6 @@ struct timing_generator_funcs {
+ bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
+ void (*clear_optc_underflow)(struct timing_generator *tg);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*set_dwb_source)(struct timing_generator *optc,
+ uint32_t dwb_pipe_inst);
+
+@@ -243,7 +240,6 @@ struct timing_generator_funcs {
+ uint32_t *num_of_input_segments,
+ uint32_t *seg0_src_sel,
+ uint32_t *seg1_src_sel);
+-#endif
+
+ /**
+ * Configure CRCs for the given timing generator. Return false if TG is
+@@ -267,13 +263,10 @@ struct timing_generator_funcs {
+ void (*set_vtg_params)(struct timing_generator *optc,
+ const struct dc_crtc_timing *dc_crtc_timing);
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void (*set_dsc_config)(struct timing_generator *optc,
+ enum optc_dsc_mode dsc_mode,
+ uint32_t dsc_bytes_per_pixel,
+ uint32_t dsc_slice_width);
+-#endif
+ void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
+ void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
+ struct dc_crtc_timing *timing);
+@@ -281,7 +274,6 @@ struct timing_generator_funcs {
+ void (*set_gsl_source_select)(struct timing_generator *optc,
+ int group_idx,
+ uint32_t gsl_ready_signal);
+-#endif
+ };
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index d39c1e11def5..23e3a541b7c9 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -66,19 +66,15 @@ struct dce_hwseq {
+
+ struct pipe_ctx;
+ struct dc_state;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_stream_status;
+ struct dc_writeback_info;
+-#endif
+ struct dchub_init_data;
+ struct dc_static_screen_events;
+ struct resource_pool;
+ struct resource_context;
+ struct stream_resource;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config;
+ struct dc_virtual_addr_space_config;
+-#endif
+ struct hubp;
+ struct dpp;
+
+@@ -113,7 +109,6 @@ struct hw_sequencer_funcs {
+ uint16_t *matrix,
+ int opp_id);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*program_front_end_for_ctx)(
+ struct dc *dc,
+ struct dc_state *context);
+@@ -124,7 +119,6 @@ struct hw_sequencer_funcs {
+ void (*set_flip_control_gsl)(
+ struct pipe_ctx *pipe_ctx,
+ bool flip_immediate);
+-#endif
+
+ void (*update_plane_addr)(
+ const struct dc *dc,
+@@ -138,7 +132,6 @@ struct hw_sequencer_funcs {
+ struct dce_hwseq *hws,
+ struct dchub_init_data *dh_data);
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ int (*init_sys_ctx)(
+ struct dce_hwseq *hws,
+ struct dc *dc,
+@@ -148,7 +141,6 @@ struct hw_sequencer_funcs {
+ struct dc *dc,
+ struct dc_virtual_addr_space_config *va_config,
+ int vmid);
+-#endif
+ void (*update_mpcc)(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx);
+@@ -239,13 +231,11 @@ struct hw_sequencer_funcs {
+ const struct dc *dc,
+ struct dc_state *context);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool (*update_bandwidth)(
+ struct dc *dc,
+ struct dc_state *context);
+ void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
+ bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
+-#endif
+
+ void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
+ unsigned int vmin, unsigned int vmax,
+@@ -323,7 +313,6 @@ struct hw_sequencer_funcs {
+ bool power_on);
+
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ void (*program_all_writeback_pipes_in_tree)(
+ struct dc *dc,
+@@ -339,7 +328,6 @@ struct hw_sequencer_funcs {
+ struct dc_state *context);
+ void (*disable_writeback)(struct dc *dc,
+ unsigned int dwb_pipe_inst);
+-#endif
+ enum dc_status (*set_clock)(struct dc *dc,
+ enum dc_clock_type clock_type,
+ uint32_t clk_khz,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+index bef224bf803e..7a85abc53d05 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+@@ -46,12 +46,8 @@ struct resource_caps {
+ int num_pll;
+ int num_dwb;
+ int num_ddc;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ int num_vmid;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ int num_dsc;
+-#endif
+-#endif
+ };
+
+ struct resource_straps {
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
+index ea75420fc876..75db39691616 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
+@@ -66,11 +66,9 @@ IRQ_DCN1 = irq_service_dcn10.o
+ AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
+
+ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1)
+-endif
+ ###############################################################################
+ # DCN 20
+ ###############################################################################
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ IRQ_DCN2 = irq_service_dcn20.o
+
+ AMD_DAL_IRQ_DCN2 = $(addprefix $(AMDDALPATH)/dc/irq/dcn20/,$(IRQ_DCN2))
+diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+index b37db73478eb..2d7c298cf5d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+@@ -80,22 +80,14 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute(
+ struct stream_encoder *enc)
+ {}
+
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ static void virtual_enc_dp_set_odm_combine(
+ struct stream_encoder *enc,
+ bool odm_combine)
+ {}
+-#endif
+-#endif
+
+ static const struct stream_encoder_funcs virtual_str_enc_funcs = {
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .dp_set_odm_combine =
+ virtual_enc_dp_set_odm_combine,
+-#endif
+-#endif
+ .dp_set_stream_attribute =
+ virtual_stream_encoder_dp_set_stream_attribute,
+ .hdmi_set_stream_attribute =
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index 68e8f6378d40..d51fe99349ed 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -149,7 +149,6 @@
+
+ #define FAMILY_RV 142 /* DCN 1*/
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+ #define FAMILY_NV 143 /* DCN 2*/
+
+@@ -163,7 +162,6 @@ enum {
+ #define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0)
+ #define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
+ #define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define RENOIR_A0 0x91
+ #define DEVICE_ID_RENOIR_1636 0x1636 // Renoir
+diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
+index fcc42372b6cf..2db5d4f60ac3 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_types.h
++++ b/drivers/gpu/drm/amd/display/include/dal_types.h
+@@ -46,9 +46,7 @@ enum dce_version {
+ DCE_VERSION_MAX,
+ DCN_VERSION_1_0,
+ DCN_VERSION_1_01,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ DCN_VERSION_2_0,
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ DCN_VERSION_2_1,
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
+index 2b219cdb13ad..89a709267019 100644
+--- a/drivers/gpu/drm/amd/display/include/logger_types.h
++++ b/drivers/gpu/drm/amd/display/include/logger_types.h
+@@ -66,12 +66,8 @@
+ #define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
+ #define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
+ #define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__)
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN3_0) || defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define DC_LOG_DWB(...) DRM_DEBUG_KMS(__VA_ARGS__)
+-#endif
+
+ struct dal_logger;
+
+@@ -116,9 +112,7 @@ enum dc_log_type {
+ LOG_PERF_TRACE,
+ LOG_DISPLAYSTATS,
+ LOG_HDMI_RETIMER_REDRIVER,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ LOG_DSC,
+-#endif
+ LOG_DWB,
+ LOG_GAMMA_DEBUG,
+ LOG_MAX_HW_POINTS,
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+index b45f7d65e76a..fe2117904329 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+@@ -45,7 +45,6 @@ enum vrr_packet_type {
+ PACKET_TYPE_VTEM
+ };
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ union lut3d_control_flags {
+ unsigned int raw;
+ struct {
+@@ -104,6 +103,5 @@ struct lut3d_settings {
+ enum lut3d_control_gamut_map map2;
+ enum lut3d_control_rotation_mode rotation2;
+ };
+-#endif
+
+ #endif /* MOD_SHARED_H_ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch
new file mode 100644
index 00000000..55f28921
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch
@@ -0,0 +1,50 @@
+From 38eb1b45802cde565f6d4b708cb5e00bb7529119 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 14 Nov 2019 16:56:08 +0800
+Subject: [PATCH 4556/4736] drm/amdgpu/gfx10: explicitly wait for cp idle after
+ halt/unhalt
+
+50us is not enough to wait for cp ready after gpu reset on some navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Suggested-by: Jack Xiao <Jack.Xiao@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 678ad1b26535..5403567683b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -2404,7 +2404,7 @@ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
++static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
+ {
+ int i;
+ u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
+@@ -2417,7 +2417,17 @@ static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
+ adev->gfx.gfx_ring[i].sched.ready = false;
+ }
+ WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
+- udelay(50);
++
++ for (i = 0; i < adev->usec_timeout; i++) {
++ if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
++ break;
++ udelay(1);
++ }
++
++ if (i >= adev->usec_timeout)
++ DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
++
++ return 0;
+ }
+
+ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4557-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4557-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
new file mode 100644
index 00000000..b5e3bfe3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4557-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
@@ -0,0 +1,105 @@
+From 309d7e98b251cde7df611946887daa4b1ccc0ae2 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 20 Nov 2019 14:02:22 +0800
+Subject: [PATCH 4557/4736] drm/amdgpu/gfx10: re-init clear state buffer after
+ gpu reset
+
+This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
+
+clear state buffer (resides in vram) is corrupted after 1st baco reset,
+upon gfxoff exit, CPF gets garbage header in CSIB and hangs.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++----
+ 1 file changed, 37 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 5403567683b7..a364f2f645c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
+ }
+
+-static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
++static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
++ int r;
++
++ if (!adev->in_gpu_reset) {
++ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
++ if (r)
++ return r;
++
++ r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
++ (void **)&adev->gfx.rlc.cs_ptr);
++ if (!r) {
++ adev->gfx.rlc.funcs->get_csb_buffer(adev,
++ adev->gfx.rlc.cs_ptr);
++ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
++ }
++
++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++ if (r)
++ return r;
++ }
++
+ /* csib */
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+ adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
+ adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
++
++ return 0;
+ }
+
+-static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
++static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
+ {
+ int i;
++ int r;
+
+- gfx_v10_0_init_csb(adev);
++ r = gfx_v10_0_init_csb(adev);
++ if (r)
++ return r;
+
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+
+ /* TODO: init power gating */
+- return;
++ return 0;
+ }
+
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+@@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ if (r)
+ return r;
+- gfx_v10_0_init_pg(adev);
++
++ r = gfx_v10_0_init_pg(adev);
++ if (r)
++ return r;
+
+ /* enable RLC SRM */
+ gfx_v10_0_rlc_enable_srm(adev);
+@@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ return r;
+ }
+
+- gfx_v10_0_init_pg(adev);
++ r = gfx_v10_0_init_pg(adev);
++ if (r)
++ return r;
++
+ adev->gfx.rlc.funcs->start(adev);
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4558-drm-amdgpu-gfx10-fix-out-of-bound-mqd_backup-array-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4558-drm-amdgpu-gfx10-fix-out-of-bound-mqd_backup-array-a.patch
new file mode 100644
index 00000000..aee0d5c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4558-drm-amdgpu-gfx10-fix-out-of-bound-mqd_backup-array-a.patch
@@ -0,0 +1,29 @@
+From 1a16172d56c6074979ca02624d4be10bf2089202 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 20 Nov 2019 14:38:00 +0800
+Subject: [PATCH 4558/4736] drm/amdgpu/gfx10: fix out-of-bound mqd_backup array
+ access
+
+Fixes: 4990f957c845 ("drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings")
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index a492174ef29b..52c27e49bc7b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -454,8 +454,6 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
+ }
+
+ ring = &adev->gfx.kiq.ring;
+- if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring)
+- kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
+ kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
+ amdgpu_bo_free_kernel(&ring->mqd_obj,
+ &ring->mqd_gpu_addr,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4559-drm-amdgpu-define-soc15_ras_field_entry-for-reuse.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4559-drm-amdgpu-define-soc15_ras_field_entry-for-reuse.patch
new file mode 100644
index 00000000..54b3d285
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4559-drm-amdgpu-define-soc15_ras_field_entry-for-reuse.patch
@@ -0,0 +1,118 @@
+From f126c8ac8a2ce8b49ac547adfc68deab63ec7a01 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Tue, 19 Nov 2019 16:25:25 +0800
+Subject: [PATCH 4559/4736] drm/amdgpu: define soc15_ras_field_entry for reuse
+
+The struct soc15_ras_field_entry will be reused by
+other IPs, such as mmhub and gc
+
+v2: rename ras_subblock_regs to gc_ras_fields_vg20,
+because the future asic maybe have a different table.
+
+Change-Id: I6c3388a09b5fbf927ad90fcd626baa448d1681a6
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 34 +++++++++------------------
+ drivers/gpu/drm/amd/amdgpu/soc15.h | 12 ++++++++++
+ 2 files changed, 23 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 79cc4b95423b..2526159c467d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -127,18 +127,6 @@ MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
+ #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c
+ #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0
+
+-struct ras_gfx_subblock_reg {
+- const char *name;
+- uint32_t hwip;
+- uint32_t inst;
+- uint32_t seg;
+- uint32_t reg_offset;
+- uint32_t sec_count_mask;
+- uint32_t sec_count_shift;
+- uint32_t ded_count_mask;
+- uint32_t ded_count_shift;
+-};
+-
+ enum ta_ras_gfx_subblock {
+ /*CPC*/
+ TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+@@ -5490,7 +5478,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
+ }
+
+
+-static const struct ras_gfx_subblock_reg ras_subblock_regs[] = {
++static const struct soc15_ras_field_entry gc_ras_fields_vg20[] = {
+ { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
+ SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
+ SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
+@@ -6149,29 +6137,29 @@ static int __get_ras_error_count(const struct soc15_reg_entry *reg,
+ uint32_t i;
+ uint32_t sec_cnt, ded_cnt;
+
+- for (i = 0; i < ARRAY_SIZE(ras_subblock_regs); i++) {
+- if(ras_subblock_regs[i].reg_offset != reg->reg_offset ||
+- ras_subblock_regs[i].seg != reg->seg ||
+- ras_subblock_regs[i].inst != reg->inst)
++ for (i = 0; i < ARRAY_SIZE(gc_ras_fields_vg20); i++) {
++ if(gc_ras_fields_vg20[i].reg_offset != reg->reg_offset ||
++ gc_ras_fields_vg20[i].seg != reg->seg ||
++ gc_ras_fields_vg20[i].inst != reg->inst)
+ continue;
+
+ sec_cnt = (value &
+- ras_subblock_regs[i].sec_count_mask) >>
+- ras_subblock_regs[i].sec_count_shift;
++ gc_ras_fields_vg20[i].sec_count_mask) >>
++ gc_ras_fields_vg20[i].sec_count_shift;
+ if (sec_cnt) {
+ DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
+- ras_subblock_regs[i].name,
++ gc_ras_fields_vg20[i].name,
+ se_id, inst_id,
+ sec_cnt);
+ *sec_count += sec_cnt;
+ }
+
+ ded_cnt = (value &
+- ras_subblock_regs[i].ded_count_mask) >>
+- ras_subblock_regs[i].ded_count_shift;
++ gc_ras_fields_vg20[i].ded_count_mask) >>
++ gc_ras_fields_vg20[i].ded_count_shift;
+ if (ded_cnt) {
+ DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
+- ras_subblock_regs[i].name,
++ gc_ras_fields_vg20[i].name,
+ se_id, inst_id,
+ ded_cnt);
+ *ded_count += ded_cnt;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
+index 9af6c6ffbfa2..344280b869c4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
+@@ -60,6 +60,18 @@ struct soc15_allowed_register_entry {
+ bool grbm_indexed;
+ };
+
++struct soc15_ras_field_entry {
++ const char *name;
++ uint32_t hwip;
++ uint32_t inst;
++ uint32_t seg;
++ uint32_t reg_offset;
++ uint32_t sec_count_mask;
++ uint32_t sec_count_shift;
++ uint32_t ded_count_mask;
++ uint32_t ded_count_shift;
++};
++
+ #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
+
+ #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch
new file mode 100644
index 00000000..6fec2621
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch
@@ -0,0 +1,769 @@
+From 2a45b43ad84392eafa5b6b974534ad0358e6ca88 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Tue, 19 Nov 2019 16:02:28 +0800
+Subject: [PATCH 4560/4736] drm/amdgpu: refine query function of mmhub EDC
+ counter in vg20
+
+Add codes to print the detail EDC info for the subblock of mmhub
+
+v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header
+files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local
+static variable and function.
+
+Change-Id: I1d5b3df38caa8f0b437c96b78091662aaeaf264b
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 232 ++++++++++++----
+ .../include/asic_reg/mmhub/mmhub_1_0_offset.h | 16 ++
+ .../asic_reg/mmhub/mmhub_1_0_sh_mask.h | 122 +++++++++
+ .../asic_reg/mmhub/mmhub_9_4_0_offset.h | 53 ----
+ .../asic_reg/mmhub/mmhub_9_4_0_sh_mask.h | 257 ------------------
+ 5 files changed, 318 insertions(+), 362 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 41c340bfc953..c0041d74df09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -27,17 +27,13 @@
+ #include "mmhub/mmhub_1_0_offset.h"
+ #include "mmhub/mmhub_1_0_sh_mask.h"
+ #include "mmhub/mmhub_1_0_default.h"
+-#include "mmhub/mmhub_9_4_0_offset.h"
+ #include "vega10_enum.h"
+-
++#include "soc15.h"
+ #include "soc15_common.h"
+
+ #define mmDAGB0_CNTL_MISC2_RV 0x008f
+ #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
+
+-#define EA_EDC_CNT_MASK 0x3
+-#define EA_EDC_CNT_SHIFT 0x2
+-
+ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
+ {
+ u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
+@@ -562,59 +558,191 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ *flags |= AMD_CG_SUPPORT_MC_LS;
+ }
+
++static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = {
++ { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ }
++};
++
++static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = {
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0},
++};
++
++static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg,
++ uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
++{
++ uint32_t i;
++ uint32_t sec_cnt, ded_cnt;
++
++ for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) {
++ if(mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
++ continue;
++
++ sec_cnt = (value &
++ mmhub_v1_0_ras_fields[i].sec_count_mask) >>
++ mmhub_v1_0_ras_fields[i].sec_count_shift;
++ if (sec_cnt) {
++ DRM_INFO("MMHUB SubBlock %s, SEC %d\n",
++ mmhub_v1_0_ras_fields[i].name,
++ sec_cnt);
++ *sec_count += sec_cnt;
++ }
++
++ ded_cnt = (value &
++ mmhub_v1_0_ras_fields[i].ded_count_mask) >>
++ mmhub_v1_0_ras_fields[i].ded_count_shift;
++ if (ded_cnt) {
++ DRM_INFO("MMHUB SubBlock %s, DED %d\n",
++ mmhub_v1_0_ras_fields[i].name,
++ ded_cnt);
++ *ded_count += ded_cnt;
++ }
++ }
++
++ return 0;
++}
++
+ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
+ void *ras_error_status)
+ {
+- int i;
+- uint32_t ea0_edc_cnt, ea0_edc_cnt2;
+- uint32_t ea1_edc_cnt, ea1_edc_cnt2;
+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+-
+- /* EDC CNT will be cleared automatically after read */
+- ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);
+- ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);
+- ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);
+- ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);
+-
+- /* error count of each error type is recorded by 2 bits,
+- * ce and ue count in EDC_CNT
+- */
+- for (i = 0; i < 5; i++) {
+- err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
+- err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
+- ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
+- ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
+- err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
+- err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
+- ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
+- ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
+- }
+- /* successive ue count in EDC_CNT */
+- for (i = 0; i < 5; i++) {
+- err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
+- err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
+- ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
+- ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
++ uint32_t sec_count = 0, ded_count = 0;
++ uint32_t i;
++ uint32_t reg_value;
++
++ err_data->ue_count = 0;
++ err_data->ce_count = 0;
++
++ for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) {
++ reg_value =
++ RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
++ if (reg_value)
++ mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i],
++ reg_value, &sec_count, &ded_count);
+ }
+
+- /* ce and ue count in EDC_CNT2 */
+- for (i = 0; i < 3; i++) {
+- err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
+- err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
+- ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+- ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+- err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
+- err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
+- ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+- ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+- }
+- /* successive ue count in EDC_CNT2 */
+- for (i = 0; i < 6; i++) {
+- err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
+- err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
+- ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+- ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+- }
++ err_data->ce_count += sec_count;
++ err_data->ue_count += ded_count;
+ }
+
+ const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
+index 352ffae7a7ca..2c3ce243861a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
+@@ -1964,4 +1964,20 @@
+ #define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a
+ #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+
++/* MMEA */
++#define mmMMEA0_EDC_CNT_VG20 0x0206
++#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0
++#define mmMMEA0_EDC_CNT2_VG20 0x0207
++#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0
++#define mmMMEA1_EDC_CNT_VG20 0x0346
++#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0
++#define mmMMEA1_EDC_CNT2_VG20 0x0347
++#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0
++
++// addressBlock: mmhub_utcl2_vmsharedpfdec
++// base address: 0x6a040
++#define mmMC_VM_XGMI_LFB_CNTL 0x0823
++#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0
++#define mmMC_VM_XGMI_LFB_SIZE 0x0824
++#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0
+ #endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
+index 34278ef2aa1b..198f5f93ed1a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
+@@ -10124,4 +10124,126 @@
+ #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
+ #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
+
++//MMEA0_EDC_CNT
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
++#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
++#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
++#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
++#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
++#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
++#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
++#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
++#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
++#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
++//MMEA0_EDC_CNT2
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
++#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
++#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
++#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10
++#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12
++#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14
++#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
++#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
++//MMEA1_EDC_CNT
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
++#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
++#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
++#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
++#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
++#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
++#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
++#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
++#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
++#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
++//MMEA1_EDC_CNT2
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
++#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
++#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
++#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10
++#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12
++#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14
++#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
++#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
++
++// addressBlock: mmhub_utcl2_vmsharedpfdec
++//MC_VM_XGMI_LFB_CNTL
++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0
++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4
++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L
++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L
++//MC_VM_XGMI_LFB_SIZE
++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0
++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL
+ #endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
+deleted file mode 100644
+index f2ae3a58949e..000000000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
++++ /dev/null
+@@ -1,53 +0,0 @@
+-/*
+- * Copyright (C) 2018 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _mmhub_9_4_0_OFFSET_HEADER
+-#define _mmhub_9_4_0_OFFSET_HEADER
+-
+-/* MMEA */
+-#define mmMMEA0_SDP_ARB_FINAL_VG20 0x01ee
+-#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX 0
+-#define mmMMEA0_EDC_CNT_VG20 0x0206
+-#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0
+-#define mmMMEA0_EDC_CNT2_VG20 0x0207
+-#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0
+-#define mmMMEA0_EDC_MODE_VG20 0x0210
+-#define mmMMEA0_EDC_MODE_VG20_BASE_IDX 0
+-#define mmMMEA0_ERR_STATUS_VG20 0x0211
+-#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX 0
+-#define mmMMEA1_SDP_ARB_FINAL_VG20 0x032e
+-#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX 0
+-#define mmMMEA1_EDC_CNT_VG20 0x0346
+-#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0
+-#define mmMMEA1_EDC_CNT2_VG20 0x0347
+-#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0
+-#define mmMMEA1_EDC_MODE_VG20 0x0350
+-#define mmMMEA1_EDC_MODE_VG20_BASE_IDX 0
+-#define mmMMEA1_ERR_STATUS_VG20 0x0351
+-#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX 0
+-
+-// addressBlock: mmhub_utcl2_vmsharedpfdec
+-// base address: 0x6a040
+-#define mmMC_VM_XGMI_LFB_CNTL 0x0823
+-#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0
+-#define mmMC_VM_XGMI_LFB_SIZE 0x0824
+-#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
+deleted file mode 100644
+index c24259ed12a1..000000000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
++++ /dev/null
+@@ -1,257 +0,0 @@
+-/*
+- * Copyright (C) 2018 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _mmhub_9_4_0_SH_MASK_HEADER
+-#define _mmhub_9_4_0_SH_MASK_HEADER
+-
+-//MMEA0_SDP_ARB_FINAL
+-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+-//MMEA0_EDC_CNT
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
+-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
+-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
+-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
+-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
+-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
+-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
+-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
+-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
+-//MMEA0_EDC_CNT2
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+-#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+-#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+-#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+-#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+-#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+-#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+-#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+-#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+-//MMEA0_EDC_MODE
+-#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+-#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11
+-#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14
+-#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d
+-#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f
+-#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+-#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L
+-#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L
+-#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L
+-#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L
+-//MMEA0_ERR_STATUS
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+-#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+-#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+-//MMEA1_SDP_ARB_FINAL
+-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
+-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
+-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
+-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
+-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
+-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
+-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
+-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
+-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
+-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
+-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
+-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
+-//MMEA1_EDC_CNT
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
+-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
+-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
+-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
+-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
+-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
+-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
+-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
+-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
+-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
+-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
+-//MMEA1_EDC_CNT2
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
+-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
+-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
+-#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
+-#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
+-#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
+-#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
+-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
+-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
+-#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
+-#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
+-#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
+-#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
+-//MMEA1_EDC_MODE
+-#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
+-#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11
+-#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14
+-#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d
+-#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f
+-#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
+-#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L
+-#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L
+-#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L
+-#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L
+-//MMEA1_ERR_STATUS
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
+-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
+-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
+-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
+-#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
+-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
+-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
+-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
+-#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
+-
+-// addressBlock: mmhub_utcl2_vmsharedpfdec
+-//MC_VM_XGMI_LFB_CNTL
+-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0
+-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4
+-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L
+-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L
+-//MC_VM_XGMI_LFB_SIZE
+-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0
+-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL
+-
+-#endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4561-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4561-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
new file mode 100644
index 00000000..e5869717
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4561-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
@@ -0,0 +1,326 @@
+From 073f2de5b3fb3e5cd72a778097df09ad875f769f Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Tue, 19 Nov 2019 14:02:57 +0800
+Subject: [PATCH 4561/4736] drm/amdgpu: implement querying ras error count for
+ mmhub9.4
+
+Get mmhub error counter by accessing EDC_CNT registers.
+
+v2: Add mmhub_v9_4_ prefix for local static variable and function
+
+Change-Id: I728d4183a08707aaf0fc71d184e86322a681e725
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 253 +++++++++++++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h | 2 +
+ 3 files changed, 257 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index db4582925b8d..992ecc74ea38 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -654,6 +654,9 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
+ case CHIP_VEGA20:
+ adev->mmhub.funcs = &mmhub_v1_0_funcs;
+ break;
++ case CHIP_ARCTURUS:
++ adev->mmhub.funcs = &mmhub_v9_4_funcs;
++ break;
+ default:
+ break;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 2c5adfe803a2..6fe5c39e5581 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -21,6 +21,7 @@
+ *
+ */
+ #include "amdgpu.h"
++#include "amdgpu_ras.h"
+ #include "mmhub_v9_4.h"
+
+ #include "mmhub/mmhub_9_4_1_offset.h"
+@@ -29,7 +30,7 @@
+ #include "athub/athub_1_0_offset.h"
+ #include "athub/athub_1_0_sh_mask.h"
+ #include "vega10_enum.h"
+-
++#include "soc15.h"
+ #include "soc15_common.h"
+
+ #define MMHUB_NUM_INSTANCES 2
+@@ -651,3 +652,253 @@ void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_MC_LS;
+ }
++
++static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
++ { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
++ },
++ { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
++ },
++ { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
++ },
++ { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++ SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
++ 0, 0,
++ },
++ { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
++ },
++ { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
++ },
++ { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
++ },
++ { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
++ },
++ { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++ 0, 0,
++ SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
++ }
++};
++
++static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0},
++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0},
++};
++
++static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
++ uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
++{
++ uint32_t i;
++ uint32_t sec_cnt, ded_cnt;
++
++ for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
++ if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
++ continue;
++
++ sec_cnt = (value &
++ mmhub_v9_4_ras_fields[i].sec_count_mask) >>
++ mmhub_v9_4_ras_fields[i].sec_count_shift;
++ if (sec_cnt) {
++ DRM_INFO("MMHUB SubBlock %s, SEC %d\n",
++ mmhub_v9_4_ras_fields[i].name,
++ sec_cnt);
++ *sec_count += sec_cnt;
++ }
++
++ ded_cnt = (value &
++ mmhub_v9_4_ras_fields[i].ded_count_mask) >>
++ mmhub_v9_4_ras_fields[i].ded_count_shift;
++ if (ded_cnt) {
++ DRM_INFO("MMHUB SubBlock %s, DED %d\n",
++ mmhub_v9_4_ras_fields[i].name,
++ ded_cnt);
++ *ded_count += ded_cnt;
++ }
++ }
++
++ return 0;
++}
++
++static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
++ void *ras_error_status)
++{
++ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++ uint32_t sec_count = 0, ded_count = 0;
++ uint32_t i;
++ uint32_t reg_value;
++
++ err_data->ue_count = 0;
++ err_data->ce_count = 0;
++
++ for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
++ reg_value =
++ RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
++ if (reg_value)
++ mmhub_v9_4_get_ras_error_count(&mmhub_v9_4_edc_cnt_regs[i],
++ reg_value, &sec_count, &ded_count);
++ }
++
++ err_data->ce_count += sec_count;
++ err_data->ue_count += ded_count;
++}
++
++const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
++ .ras_late_init = amdgpu_mmhub_ras_late_init,
++ .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
++};
+\ No newline at end of file
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+index d435cfcec1a8..354a4b7e875b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+@@ -23,6 +23,8 @@
+ #ifndef __MMHUB_V9_4_H__
+ #define __MMHUB_V9_4_H__
+
++extern const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs;
++
+ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev);
+ int mmhub_v9_4_gart_enable(struct amdgpu_device *adev);
+ void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4562-drm-amdgpu-Update-Arcturus-golden-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4562-drm-amdgpu-Update-Arcturus-golden-registers.patch
new file mode 100644
index 00000000..59f0b789
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4562-drm-amdgpu-Update-Arcturus-golden-registers.patch
@@ -0,0 +1,26 @@
+From 1d650ef1104521cb6f855f77a98488714d04086d Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Wed, 20 Nov 2019 16:32:46 +0000
+Subject: [PATCH 4562/4736] drm/amdgpu: Update Arcturus golden registers
+
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2526159c467d..0932e4a7c63c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -688,6 +688,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
+ };
+
+ static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4563-drm-amd-display-Change-mmhub_9_4_0_-headers-to-mmhub.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4563-drm-amd-display-Change-mmhub_9_4_0_-headers-to-mmhub.patch
new file mode 100644
index 00000000..1c0b8204
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4563-drm-amd-display-Change-mmhub_9_4_0_-headers-to-mmhub.patch
@@ -0,0 +1,39 @@
+From 8b92f281daaefb0e0c265784505e38a6afa8bac3 Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Wed, 20 Nov 2019 14:35:37 -0500
+Subject: [PATCH 4563/4736] drm/amd/display: Change mmhub_9_4_0_ headers to
+ mmhub_1_0_ ones.
+
+[Why]
+Kernal won't compile without this patch. That is because
+mmhub_9_4_0_ headers are obsolete. All contents within
+mmhub_9_4_0_ headers are inherited by their corresponding
+mmhub_1_0_ ones.
+
+[How]
+Change mmhub_9_4_0_ headers to their corresponding mmhub_1_0_ ones.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index e9157583817f..b00d17cade1a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -61,8 +61,8 @@
+ #include "soc15_hw_ip.h"
+ #include "vega10_ip_offset.h"
+ #include "nbio/nbio_6_1_offset.h"
+-#include "mmhub/mmhub_9_4_0_offset.h"
+-#include "mmhub/mmhub_9_4_0_sh_mask.h"
++#include "mmhub/mmhub_1_0_offset.h"
++#include "mmhub/mmhub_1_0_sh_mask.h"
+ #include "reg_helper.h"
+
+ #include "dce100/dce100_resource.h"
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4564-drm-amdkfd-Delete-KFD_MQD_TYPE_COMPUTE.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4564-drm-amdkfd-Delete-KFD_MQD_TYPE_COMPUTE.patch
new file mode 100644
index 00000000..9645f0b2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4564-drm-amdkfd-Delete-KFD_MQD_TYPE_COMPUTE.patch
@@ -0,0 +1,125 @@
+From 6a0c2a06d1a5df450573d6f35c258770b01480d3 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 23:57:37 -0500
+Subject: [PATCH 4564/4736] drm/amdkfd: Delete KFD_MQD_TYPE_COMPUTE
+
+It is the same as KFD_MQD_TYPE_CP, so delete it. As a result, we will
+have one less mqd mananger per device.
+
+Change-Id: Iaa98fc17be06b216de7a826c3577f44bc0536b4c
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +--
+ 6 files changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 0ec9370976d9..67a364ecf8c8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1744,7 +1744,7 @@ static int get_wave_state(struct device_queue_manager *dqm,
+ goto dqm_unlock;
+ }
+
+- mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++ mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+
+ if (!mqd_mgr->get_wave_state) {
+ r = -EINVAL;
+@@ -2187,7 +2187,7 @@ void copy_context_work_handler (struct work_struct *work)
+
+
+ list_for_each_entry(q, &qpd->queues_list, list) {
+- mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++ mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+
+ /* We ignore the return value from get_wave_state
+ * because
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 9431dc2ca54b..3f2220442bd9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -403,7 +403,6 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+@@ -475,7 +474,7 @@ struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
+ mqd = mqd_manager_init_cik(type, dev);
+ if (!mqd)
+ return NULL;
+- if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++ if (type == KFD_MQD_TYPE_CP)
+ mqd->update_mqd = update_mqd_hawaii;
+ return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 65a03d1d79db..b132bf301c63 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -401,7 +401,6 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ pr_debug("%s@%i\n", __func__, __LINE__);
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 822747377c28..76ad9a0891e6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -528,7 +528,6 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 39c9b470e227..c93835fb6414 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -466,7 +466,6 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+@@ -539,7 +538,7 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
+ mqd = mqd_manager_init_vi(type, dev);
+ if (!mqd)
+ return NULL;
+- if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++ if (type == KFD_MQD_TYPE_CP)
+ mqd->update_mqd = update_mqd_tonga;
+ return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index e937679f8ca1..b91029047953 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -576,8 +576,7 @@ struct queue {
+ * Please read the kfd_mqd_manager.h description.
+ */
+ enum KFD_MQD_TYPE {
+- KFD_MQD_TYPE_COMPUTE = 0, /* for no cp scheduling */
+- KFD_MQD_TYPE_HIQ, /* for hiq */
++ KFD_MQD_TYPE_HIQ = 0, /* for hiq */
+ KFD_MQD_TYPE_CP, /* for cp queues and diq */
+ KFD_MQD_TYPE_SDMA, /* for sdma queues */
+ KFD_MQD_TYPE_DIQ, /* for diq */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4565-drm-amdkfd-DIQ-should-not-use-HIQ-way-to-allocate-me.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4565-drm-amdkfd-DIQ-should-not-use-HIQ-way-to-allocate-me.patch
new file mode 100644
index 00000000..b2fe1e67
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4565-drm-amdkfd-DIQ-should-not-use-HIQ-way-to-allocate-me.patch
@@ -0,0 +1,74 @@
+From 033aff03c39979d2f714a32967091297854d34ea Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 9 Nov 2019 00:47:31 -0500
+Subject: [PATCH 4565/4736] drm/amdkfd: DIQ should not use HIQ way to allocate
+ memory
+
+In the mqd_diq_sdma buffer, there should be only one HIQ mqd. All DIQs
+should be allocated somewhere else using the regular way.
+
+Change-Id: Ibf3eb33604d0ec30501c244228cdb3b24615b699
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 3f2220442bd9..37ce9571a175 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -431,7 +431,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index b132bf301c63..1e83abacf248 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -432,7 +432,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ pr_debug("%s@%i\n", __func__, __LINE__);
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 76ad9a0891e6..59f75b169459 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -557,7 +557,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index c93835fb6414..f71679443300 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -495,7 +495,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4566-drm-amdgpu-initialize-vm_inv_eng0_sem-for-gfxhub-and.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4566-drm-amdgpu-initialize-vm_inv_eng0_sem-for-gfxhub-and.patch
new file mode 100644
index 00000000..96ada6d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4566-drm-amdgpu-initialize-vm_inv_eng0_sem-for-gfxhub-and.patch
@@ -0,0 +1,109 @@
+From 36664bd1742e7a463222014761d07eea7e19261b Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Tue, 19 Nov 2019 10:18:39 +0800
+Subject: [PATCH 4566/4736] drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub
+ and mmhub
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+SW must acquire/release one of the vm_invalidate_eng*_sem around the
+invalidation req/ack. Through this way,it can avoid losing invalidate
+acknowledge state across power-gating off cycle.
+To use vm_invalidate_eng*_sem, it needs to initialize
+vm_invalidate_eng*_sem firstly.
+
+Change-Id: I9f73b18c5c1f75d3195a6f5c448f71060ce0ab25
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 4 ++++
+ 6 files changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 02bbb571756a..cee7e8ae214f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -77,6 +77,7 @@ struct amdgpu_gmc_fault {
+ struct amdgpu_vmhub {
+ uint32_t ctx0_ptb_addr_lo32;
+ uint32_t ctx0_ptb_addr_hi32;
++ uint32_t vm_inv_eng0_sem;
+ uint32_t vm_inv_eng0_req;
+ uint32_t vm_inv_eng0_ack;
+ uint32_t vm_context0_cntl;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+index db8baf733508..2c8a542cbd94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+@@ -367,6 +367,8 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)
+ hub->ctx0_ptb_addr_hi32 =
+ SOC15_REG_OFFSET(GC, 0,
+ mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++ hub->vm_inv_eng0_sem =
++ SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
+ hub->vm_inv_eng0_req =
+ SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
+ hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index b4f32d853ca1..b70c7b483c24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -356,6 +356,8 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
+ hub->ctx0_ptb_addr_hi32 =
+ SOC15_REG_OFFSET(GC, 0,
+ mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++ hub->vm_inv_eng0_sem =
++ SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
+ hub->vm_inv_eng0_req =
+ SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
+ hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index c0041d74df09..cc4947afa34d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -416,6 +416,8 @@ void mmhub_v1_0_init(struct amdgpu_device *adev)
+ hub->ctx0_ptb_addr_hi32 =
+ SOC15_REG_OFFSET(MMHUB, 0,
+ mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++ hub->vm_inv_eng0_sem =
++ SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
+ hub->vm_inv_eng0_req =
+ SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
+ hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 945533634711..a7cb185d639a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -348,6 +348,8 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
+ hub->ctx0_ptb_addr_hi32 =
+ SOC15_REG_OFFSET(MMHUB, 0,
+ mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++ hub->vm_inv_eng0_sem =
++ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
+ hub->vm_inv_eng0_req =
+ SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
+ hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 6fe5c39e5581..753eea25b569 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -505,6 +505,10 @@ void mmhub_v9_4_init(struct amdgpu_device *adev)
+ SOC15_REG_OFFSET(MMHUB, 0,
+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
+ i * MMHUB_INSTANCE_REGISTER_OFFSET;
++ hub[i]->vm_inv_eng0_sem =
++ SOC15_REG_OFFSET(MMHUB, 0,
++ mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
++ i * MMHUB_INSTANCE_REGISTER_OFFSET;
+ hub[i]->vm_inv_eng0_req =
+ SOC15_REG_OFFSET(MMHUB, 0,
+ mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4567-drm-amdgpu-simplify-runtime-suspend.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4567-drm-amdgpu-simplify-runtime-suspend.patch
new file mode 100644
index 00000000..ba5d8b73
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4567-drm-amdgpu-simplify-runtime-suspend.patch
@@ -0,0 +1,77 @@
+From d01273461600fcd798305122d28fec38aa5e2773 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 20 Nov 2019 14:20:32 -0500
+Subject: [PATCH 4567/4736] drm/amdgpu: simplify runtime suspend
+
+In the standard _PR3 case, the pci core handles the pci state.
+The driver only needs to handle it in the legacy ATPX case.
+
+This may fix issues with runtime suspend/resume on certain
+hybrid graphics laptops.
+
+Change-Id: Ifa10d4905a885132c9f8d1168eac5bbd550d1ceb
+Acked-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 ++++++++++++++++---------
+ 1 file changed, 22 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 6957ef4ef514..4ca9b9bde917 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1261,13 +1261,17 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+
+ ret = amdgpu_device_suspend(drm_dev, false, false);
+ if (amdgpu_device_supports_boco(drm_dev)) {
+- pci_save_state(pdev);
+- pci_disable_device(pdev);
+- pci_ignore_hotplug(pdev);
+- if (amdgpu_is_atpx_hybrid())
++ /* Only need to handle PCI state in the driver for ATPX
++ * PCI core handles it for _PR3.
++ */
++ if (amdgpu_is_atpx_hybrid()) {
++ pci_ignore_hotplug(pdev);
++ } else {
++ pci_save_state(pdev);
++ pci_disable_device(pdev);
++ pci_ignore_hotplug(pdev);
+ pci_set_power_state(pdev, PCI_D3cold);
+- else if (!amdgpu_has_atpx_dgpu_power_cntl())
+- pci_set_power_state(pdev, PCI_D3hot);
++ }
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
+ } else if (amdgpu_device_supports_baco(drm_dev)) {
+ amdgpu_device_baco_enter(drm_dev);
+@@ -1289,14 +1293,19 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ if (amdgpu_device_supports_boco(drm_dev)) {
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+
+- if (amdgpu_is_atpx_hybrid() ||
+- !amdgpu_has_atpx_dgpu_power_cntl())
++ /* Only need to handle PCI state in the driver for ATPX
++ * PCI core handles it for _PR3.
++ */
++ if (amdgpu_is_atpx_hybrid()) {
++ pci_set_master(pdev);
++ } else {
+ pci_set_power_state(pdev, PCI_D0);
+- pci_restore_state(pdev);
+- ret = pci_enable_device(pdev);
+- if (ret)
+- return ret;
+- pci_set_master(pdev);
++ pci_restore_state(pdev);
++ ret = pci_enable_device(pdev);
++ if (ret)
++ return ret;
++ pci_set_master(pdev);
++ }
+ } else if (amdgpu_device_supports_baco(drm_dev)) {
+ amdgpu_device_baco_exit(drm_dev);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4568-drm-amdgpu-remove-redundant-assignment-to-pointer-wr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4568-drm-amdgpu-remove-redundant-assignment-to-pointer-wr.patch
new file mode 100644
index 00000000..f3c29ec3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4568-drm-amdgpu-remove-redundant-assignment-to-pointer-wr.patch
@@ -0,0 +1,34 @@
+From 4af3b4fd4a39d70100720cd8fb796728e592044f Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 21 Nov 2019 16:54:01 +0000
+Subject: [PATCH 4568/4736] drm/amdgpu: remove redundant assignment to pointer
+ write_frame
+
+The pointer write_frame is being initialized with a value that is
+never read and it is being updated later with a new value. The
+initialization is redundant and can be removed.
+
+Change-Id: Iaa3ee0742a108d292b38ac4727bf7434c8103668
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 4ba444baf6db..b9922a5f6890 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1730,7 +1730,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
+ int index)
+ {
+ unsigned int psp_write_ptr_reg = 0;
+- struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
++ struct psp_gfx_rb_frame *write_frame;
+ struct psp_ring *ring = &psp->km_ring;
+ struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+ struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4569-Revert-drm-amdgpu-gfx10-re-init-clear-state-buffer-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4569-Revert-drm-amdgpu-gfx10-re-init-clear-state-buffer-a.patch
new file mode 100644
index 00000000..ae81cd1e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4569-Revert-drm-amdgpu-gfx10-re-init-clear-state-buffer-a.patch
@@ -0,0 +1,104 @@
+From 485b768977869e07005145ec36e59c97ea358090 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 22 Nov 2019 11:37:39 +0800
+Subject: [PATCH 4569/4736] Revert "drm/amdgpu/gfx10: re-init clear state
+ buffer after gpu reset"
+
+there's a copy-paste error (!adev->in_gpu_reset), re-submit the patch
+
+This reverts commit 61d914ea3925eb70960210d7e8df15b349942ddb.
+
+Change-Id: Ib49e4a6e4016154a91b422fc6855517c7ad83b07
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++----------------------
+ 1 file changed, 6 insertions(+), 37 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index a364f2f645c2..5403567683b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1789,52 +1789,27 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
+ }
+
+-static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
++static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
+- int r;
+-
+- if (!adev->in_gpu_reset) {
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+- if (r)
+- return r;
+-
+- r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
+- (void **)&adev->gfx.rlc.cs_ptr);
+- if (!r) {
+- adev->gfx.rlc.funcs->get_csb_buffer(adev,
+- adev->gfx.rlc.cs_ptr);
+- amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+- }
+-
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+- if (r)
+- return r;
+- }
+-
+ /* csib */
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+ adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
+ adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
+-
+- return 0;
+ }
+
+-static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
++static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
+ {
+ int i;
+- int r;
+
+- r = gfx_v10_0_init_csb(adev);
+- if (r)
+- return r;
++ gfx_v10_0_init_csb(adev);
+
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+
+ /* TODO: init power gating */
+- return 0;
++ return;
+ }
+
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+@@ -1936,10 +1911,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ if (r)
+ return r;
+-
+- r = gfx_v10_0_init_pg(adev);
+- if (r)
+- return r;
++ gfx_v10_0_init_pg(adev);
+
+ /* enable RLC SRM */
+ gfx_v10_0_rlc_enable_srm(adev);
+@@ -1965,10 +1937,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ return r;
+ }
+
+- r = gfx_v10_0_init_pg(adev);
+- if (r)
+- return r;
+-
++ gfx_v10_0_init_pg(adev);
+ adev->gfx.rlc.funcs->start(adev);
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4570-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4570-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
new file mode 100644
index 00000000..a67165cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4570-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
@@ -0,0 +1,106 @@
+From e109af54893aafc8255e7a71b48f6c2ec8b01f8b Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 20 Nov 2019 14:02:22 +0800
+Subject: [PATCH 4570/4736] drm/amdgpu/gfx10: re-init clear state buffer after
+ gpu reset
+
+This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
+
+clear state buffer (resides in vram) is corrupted after 1st baco reset,
+upon gfxoff exit, CPF gets garbage header in CSIB and hangs.
+
+Change-Id: Ifaf95d0aab103f87b9f7970f395e95f8c4c5cc3e
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++----
+ 1 file changed, 37 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 5403567683b7..bfc2b8f8c1d4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
+ }
+
+-static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
++static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
++ int r;
++
++ if (adev->in_gpu_reset) {
++ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
++ if (r)
++ return r;
++
++ r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
++ (void **)&adev->gfx.rlc.cs_ptr);
++ if (!r) {
++ adev->gfx.rlc.funcs->get_csb_buffer(adev,
++ adev->gfx.rlc.cs_ptr);
++ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
++ }
++
++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++ if (r)
++ return r;
++ }
++
+ /* csib */
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+ adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
+ adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
++
++ return 0;
+ }
+
+-static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
++static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
+ {
+ int i;
++ int r;
+
+- gfx_v10_0_init_csb(adev);
++ r = gfx_v10_0_init_csb(adev);
++ if (r)
++ return r;
+
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+
+ /* TODO: init power gating */
+- return;
++ return 0;
+ }
+
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+@@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ if (r)
+ return r;
+- gfx_v10_0_init_pg(adev);
++
++ r = gfx_v10_0_init_pg(adev);
++ if (r)
++ return r;
+
+ /* enable RLC SRM */
+ gfx_v10_0_rlc_enable_srm(adev);
+@@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ return r;
+ }
+
+- gfx_v10_0_init_pg(adev);
++ r = gfx_v10_0_init_pg(adev);
++ if (r)
++ return r;
++
+ adev->gfx.rlc.funcs->start(adev);
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4571-drm-amdkfd-add-kfd-missing-patch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4571-drm-amdkfd-add-kfd-missing-patch.patch
new file mode 100644
index 00000000..bb909a3b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4571-drm-amdkfd-add-kfd-missing-patch.patch
@@ -0,0 +1,65 @@
+From 2f88fdb683379b0f32e6e44aa034147cfb99046f Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Mon, 25 Nov 2019 13:41:00 +0800
+Subject: [PATCH 4571/4736] drm/amdkfd: add kfd missing patch
+
+from commit 99ac52a3dd189 - Merge amd-staging-drm-next into
+amd-kfd-staging
+
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 67a364ecf8c8..f2325e5f15ce 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -736,6 +736,10 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ q->properties.type)];
+ q->properties.is_active = false;
+ dqm->queue_count--;
++ if (q->properties.is_gws) {
++ dqm->gws_queue_count--;
++ qpd->mapped_gws_queue = false;
++ }
+
+ if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
+ continue;
+@@ -748,10 +752,6 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ * maintain a consistent eviction state
+ */
+ ret = retval;
+- if (q->properties.is_gws) {
+- dqm->gws_queue_count--;
+- qpd->mapped_gws_queue = false;
+- }
+ }
+
+ out:
+@@ -858,6 +858,10 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ q->properties.type)];
+ q->properties.is_active = true;
+ dqm->queue_count++;
++ if (q->properties.is_gws) {
++ dqm->gws_queue_count++;
++ qpd->mapped_gws_queue = true;
++ }
+
+ if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
+ continue;
+@@ -869,10 +873,6 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ * maintain a consistent eviction state
+ */
+ ret = retval;
+- if (q->properties.is_gws) {
+- dqm->gws_queue_count++;
+- qpd->mapped_gws_queue = true;
+- }
+ }
+ qpd->evicted = 0;
+ out:
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4572-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4572-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
new file mode 100644
index 00000000..b28ee4cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4572-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
@@ -0,0 +1,123 @@
+From 0a3db18ee805bf4e05b380d052863fb3647caf7c Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Mon, 25 Nov 2019 14:17:44 +0800
+Subject: [PATCH 4572/4736] drm/amdkfd: add missing KFD_MQD_TYPE_COMPUTE
+
+from amd-kfd-staging branch
+
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 ++-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 ++-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++-
+ 6 files changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index f2325e5f15ce..76c7f0ec3de3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1744,7 +1744,7 @@ static int get_wave_state(struct device_queue_manager *dqm,
+ goto dqm_unlock;
+ }
+
+- mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
++ mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
+
+ if (!mqd_mgr->get_wave_state) {
+ r = -EINVAL;
+@@ -2187,7 +2187,7 @@ void copy_context_work_handler (struct work_struct *work)
+
+
+ list_for_each_entry(q, &qpd->queues_list, list) {
+- mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
++ mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
+
+ /* We ignore the return value from get_wave_state
+ * because
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 37ce9571a175..c8561c3283b2 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -403,6 +403,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
++ case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+@@ -474,7 +475,7 @@ struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
+ mqd = mqd_manager_init_cik(type, dev);
+ if (!mqd)
+ return NULL;
+- if (type == KFD_MQD_TYPE_CP)
++ if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
+ mqd->update_mqd = update_mqd_hawaii;
+ return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 1e83abacf248..df383c8ff5f9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -401,6 +401,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
++ case KFD_MQD_TYPE_COMPUTE:
+ pr_debug("%s@%i\n", __func__, __LINE__);
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 59f75b169459..6dec54bf49c6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -528,6 +528,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
++ case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index f71679443300..5454ee562a00 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -466,6 +466,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
++ case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+@@ -538,7 +539,7 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
+ mqd = mqd_manager_init_vi(type, dev);
+ if (!mqd)
+ return NULL;
+- if (type == KFD_MQD_TYPE_CP)
++ if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
+ mqd->update_mqd = update_mqd_tonga;
+ return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index b91029047953..e937679f8ca1 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -576,7 +576,8 @@ struct queue {
+ * Please read the kfd_mqd_manager.h description.
+ */
+ enum KFD_MQD_TYPE {
+- KFD_MQD_TYPE_HIQ = 0, /* for hiq */
++ KFD_MQD_TYPE_COMPUTE = 0, /* for no cp scheduling */
++ KFD_MQD_TYPE_HIQ, /* for hiq */
+ KFD_MQD_TYPE_CP, /* for cp queues and diq */
+ KFD_MQD_TYPE_SDMA, /* for sdma queues */
+ KFD_MQD_TYPE_DIQ, /* for diq */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4573-drm-amdkfd-add-missing-mqd-init-from-kfd-staging.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4573-drm-amdkfd-add-missing-mqd-init-from-kfd-staging.patch
new file mode 100644
index 00000000..6b2dcf6b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4573-drm-amdkfd-add-missing-mqd-init-from-kfd-staging.patch
@@ -0,0 +1,72 @@
+From ac4523f48b820462921d04ad5124da91e5b57b06 Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Mon, 25 Nov 2019 14:18:09 +0800
+Subject: [PATCH 4573/4736] drm/amdkfd: add missing mqd init from kfd-staging
+
+partially missing from commit 8636e53c4715d - drm/amdkfd: Separate mqd
+allocation and initialization
+
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index c8561c3283b2..9431dc2ca54b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -432,7 +432,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_mqd;
++ mqd->allocate_mqd = allocate_hiq_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index df383c8ff5f9..65a03d1d79db 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -433,7 +433,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ pr_debug("%s@%i\n", __func__, __LINE__);
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_mqd;
++ mqd->allocate_mqd = allocate_hiq_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 6dec54bf49c6..822747377c28 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -558,7 +558,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_mqd;
++ mqd->allocate_mqd = allocate_hiq_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 5454ee562a00..39c9b470e227 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -496,7 +496,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_mqd;
++ mqd->allocate_mqd = allocate_hiq_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4574-drm-amdgpu-disable-gfxoff-on-original-raven.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4574-drm-amdgpu-disable-gfxoff-on-original-raven.patch
new file mode 100644
index 00000000..bbf105c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4574-drm-amdgpu-disable-gfxoff-on-original-raven.patch
@@ -0,0 +1,41 @@
+From 86c604910dc6eb1b09587b3442a8a168caef04b1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Nov 2019 10:21:23 -0500
+Subject: [PATCH 4574/4736] drm/amdgpu: disable gfxoff on original raven
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are still combinations of sbios and firmware that
+are not stable.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204689
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 0932e4a7c63c..18490f23e0d9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1036,8 +1036,13 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+ case CHIP_VEGA20:
+ break;
+ case CHIP_RAVEN:
+- if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+- &&((adev->gfx.rlc_fw_version != 106 &&
++ /* Disable GFXOFF on original raven. There are combinations
++ * of sbios and platforms that are not stable.
++ */
++ if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
++ else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
++ &&((adev->gfx.rlc_fw_version != 106 &&
+ adev->gfx.rlc_fw_version < 531) ||
+ (adev->gfx.rlc_fw_version == 53815) ||
+ (adev->gfx.rlc_feature_version < 1) ||
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4575-Revert-drm-amd-display-enable-S-G-for-RAVEN-chip.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4575-Revert-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
new file mode 100644
index 00000000..8165f97c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4575-Revert-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
@@ -0,0 +1,50 @@
+From 491a758e006216162226c162a2c1c540b8338870 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Nov 2019 10:26:52 -0500
+Subject: [PATCH 4575/4736] Revert "drm/amd/display: enable S/G for RAVEN chip"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit 1c4259159132ae4ceaf7c6db37a6cf76417f73d9.
+
+S/G display is not stable with the IOMMU enabled on some
+platforms.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205523
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +-
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index dcabe24e4dc3..cf589c055305 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -512,7 +512,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
+ * Also, don't allow GTT domain if the BO doens't have USWC falg set.
+ */
+ if (adev->asic_type >= CHIP_CARRIZO &&
+- adev->asic_type <= CHIP_RAVEN &&
++ adev->asic_type < CHIP_RAVEN &&
+ (adev->flags & AMD_IS_APU) &&
+ (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
+ amdgpu_bo_support_uswc(bo_flags) &&
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3ec482e79ecf..841f0bfd1e4f 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -929,7 +929,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ */
+ if (adev->flags & AMD_IS_APU &&
+ adev->asic_type >= CHIP_CARRIZO &&
+- adev->asic_type <= CHIP_RAVEN)
++ adev->asic_type < CHIP_RAVEN)
+ init_data.flags.gpu_vm_support = true;
+
+ if (amdgpu_dc_feature_mask & DC_FBC_MASK)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4576-drm-amd-amdgpu-sriov-temporarily-skip-ras-dtm-hdcp-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4576-drm-amd-amdgpu-sriov-temporarily-skip-ras-dtm-hdcp-f.patch
new file mode 100644
index 00000000..e243c09e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4576-drm-amd-amdgpu-sriov-temporarily-skip-ras-dtm-hdcp-f.patch
@@ -0,0 +1,103 @@
+From 1880194a969a309d0591171b910a4cbfaaf035bf Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Thu, 21 Nov 2019 13:59:28 +0800
+Subject: [PATCH 4576/4736] drm/amd/amdgpu/sriov temporarily skip ras,dtm,hdcp
+ for arcturus VF
+
+Temporarily skip ras,dtm,hdcp initialize and terminate for arcturus VF
+Currently the three features haven't been enabled at SRIOV, it would
+trigger guest driver load fail with the bare-metal path of the three
+features.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index b9922a5f6890..0f903c4bab2e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -760,6 +760,12 @@ static int psp_ras_terminate(struct psp_context *psp)
+ {
+ int ret;
+
++ /*
++ * TODO: bypass the terminate in sriov for now
++ */
++ if (amdgpu_sriov_vf(psp->adev))
++ return 0;
++
+ if (!psp->ras.ras_initialized)
+ return 0;
+
+@@ -781,6 +787,12 @@ static int psp_ras_initialize(struct psp_context *psp)
+ {
+ int ret;
+
++ /*
++ * TODO: bypass the initialize in sriov for now
++ */
++ if (amdgpu_sriov_vf(psp->adev))
++ return 0;
++
+ if (!psp->adev->psp.ta_ras_ucode_size ||
+ !psp->adev->psp.ta_ras_start_addr) {
+ dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
+@@ -876,6 +888,12 @@ static int psp_hdcp_initialize(struct psp_context *psp)
+ {
+ int ret;
+
++ /*
++ * TODO: bypass the initialize in sriov for now
++ */
++ if (amdgpu_sriov_vf(psp->adev))
++ return 0;
++
+ if (!psp->adev->psp.ta_hdcp_ucode_size ||
+ !psp->adev->psp.ta_hdcp_start_addr) {
+ dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
+@@ -964,6 +982,12 @@ static int psp_hdcp_terminate(struct psp_context *psp)
+ {
+ int ret;
+
++ /*
++ * TODO: bypass the terminate in sriov for now
++ */
++ if (amdgpu_sriov_vf(psp->adev))
++ return 0;
++
+ if (!psp->hdcp_context.hdcp_initialized)
+ return 0;
+
+@@ -1055,6 +1079,12 @@ static int psp_dtm_initialize(struct psp_context *psp)
+ {
+ int ret;
+
++ /*
++ * TODO: bypass the initialize in sriov for now
++ */
++ if (amdgpu_sriov_vf(psp->adev))
++ return 0;
++
+ if (!psp->adev->psp.ta_dtm_ucode_size ||
+ !psp->adev->psp.ta_dtm_start_addr) {
+ dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
+@@ -1113,6 +1143,12 @@ static int psp_dtm_terminate(struct psp_context *psp)
+ {
+ int ret;
+
++ /*
++ * TODO: bypass the terminate in sriov for now
++ */
++ if (amdgpu_sriov_vf(psp->adev))
++ return 0;
++
+ if (!psp->dtm_context.dtm_initialized)
+ return 0;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4577-drm-amd-amdgpu-sriov-skip-RLCG-s-r-list-for-arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4577-drm-amd-amdgpu-sriov-skip-RLCG-s-r-list-for-arcturus.patch
new file mode 100644
index 00000000..85c999d7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4577-drm-amd-amdgpu-sriov-skip-RLCG-s-r-list-for-arcturus.patch
@@ -0,0 +1,37 @@
+From 23e70ae93d3599bd6c79232bbf67ae5929bcbdd5 Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Thu, 21 Nov 2019 14:09:08 +0800
+Subject: [PATCH 4577/4736] drm/amd/amdgpu/sriov skip RLCG s/r list for
+ arcturus VF.
+
+After rlcg fw 2.1, kmd driver starts to load extra fw for
+LIST_CNTL,GPM_MEM,SRM_MEM. We needs to skip the three fw
+because all rlcg related fw have been loaded by host driver.
+Guest driver would load the three fw fail without this change.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 0f903c4bab2e..c74c5f183a10 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1472,7 +1472,10 @@ static int psp_np_fw_load(struct psp_context *psp)
+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
+ || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
+- || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
++ || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
++ || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
++ || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
++ || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM))
+ /*skip ucode loading in SRIOV VF */
+ continue;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4578-drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4578-drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-.patch
new file mode 100644
index 00000000..eb84ba85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4578-drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-.patch
@@ -0,0 +1,223 @@
+From 7d29c52c9ae3611a23c78e779ccf81ca0e7a9f8c Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Tue, 19 Nov 2019 11:13:29 +0800
+Subject: [PATCH 4578/4736] drm/amdgpu: invalidate mmhub semaphore workaround
+ in gmc9/gmc10
+
+It may lose gpuvm invalidate acknowldege state across power-gating off
+cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire
+before invalidation and semaphore release after invalidation.
+
+After adding semaphore acquire before invalidation, the semaphore
+register become read-only if another process try to acquire semaphore.
+Then it will not be able to release this semaphore. Then it may cause
+deadlock problem. If this deadlock problem happens, it needs a semaphore
+firmware fix.
+
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 57 ++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 57 ++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.h | 4 +-
+ 3 files changed, 116 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index af2615ba52aa..9effec6a7a67 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -234,6 +234,29 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
+ const unsigned eng = 17;
+ unsigned int i;
+
++ spin_lock(&adev->gmc.invalidate_lock);
++ /*
++ * It may lose gpuvm invalidate acknowldege state across power-gating
++ * off cycle, add semaphore acquire before invalidation and semaphore
++ * release after invalidation to avoid entering power gated state
++ * to WA the Issue
++ */
++
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (vmhub == AMDGPU_MMHUB_0 ||
++ vmhub == AMDGPU_MMHUB_1) {
++ for (i = 0; i < adev->usec_timeout; i++) {
++ /* a read return value of 1 means semaphore acuqire */
++ tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
++ if (tmp & 0x1)
++ break;
++ udelay(1);
++ }
++
++ if (i >= adev->usec_timeout)
++ DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
++ }
++
+ WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+
+ /*
+@@ -253,6 +276,17 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
+ udelay(1);
+ }
+
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (vmhub == AMDGPU_MMHUB_0 ||
++ vmhub == AMDGPU_MMHUB_1)
++ /*
++ * add semaphore release after invalidation,
++ * write with 0 means semaphore release
++ */
++ WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
++
++ spin_unlock(&adev->gmc.invalidate_lock);
++
+ if (i < adev->usec_timeout)
+ return;
+
+@@ -338,6 +372,20 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
+ unsigned eng = ring->vm_inv_eng;
+
++ /*
++ * It may lose gpuvm invalidate acknowldege state across power-gating
++ * off cycle, add semaphore acquire before invalidation and semaphore
++ * release after invalidation to avoid entering power gated state
++ * to WA the Issue
++ */
++
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++ ring->funcs->vmhub == AMDGPU_MMHUB_1)
++ /* a read return value of 1 means semaphore acuqire */
++ amdgpu_ring_emit_reg_wait(ring,
++ hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
++
+ amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
+ lower_32_bits(pd_addr));
+
+@@ -348,6 +396,15 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++ ring->funcs->vmhub == AMDGPU_MMHUB_1)
++ /*
++ * add semaphore release after invalidation,
++ * write with 0 means semaphore release
++ */
++ amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
++
+ return pd_addr;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 992ecc74ea38..b051ede2fb83 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -455,6 +455,29 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+ }
+
+ spin_lock(&adev->gmc.invalidate_lock);
++
++ /*
++ * It may lose gpuvm invalidate acknowldege state across power-gating
++ * off cycle, add semaphore acquire before invalidation and semaphore
++ * release after invalidation to avoid entering power gated state
++ * to WA the Issue
++ */
++
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (vmhub == AMDGPU_MMHUB_0 ||
++ vmhub == AMDGPU_MMHUB_1) {
++ for (j = 0; j < adev->usec_timeout; j++) {
++ /* a read return value of 1 means semaphore acuqire */
++ tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
++ if (tmp & 0x1)
++ break;
++ udelay(1);
++ }
++
++ if (j >= adev->usec_timeout)
++ DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
++ }
++
+ WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+
+ /*
+@@ -470,7 +493,18 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+ break;
+ udelay(1);
+ }
++
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (vmhub == AMDGPU_MMHUB_0 ||
++ vmhub == AMDGPU_MMHUB_1)
++ /*
++ * add semaphore release after invalidation,
++ * write with 0 means semaphore release
++ */
++ WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
++
+ spin_unlock(&adev->gmc.invalidate_lock);
++
+ if (j < adev->usec_timeout)
+ return;
+
+@@ -485,6 +519,20 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
+ unsigned eng = ring->vm_inv_eng;
+
++ /*
++ * It may lose gpuvm invalidate acknowldege state across power-gating
++ * off cycle, add semaphore acquire before invalidation and semaphore
++ * release after invalidation to avoid entering power gated state
++ * to WA the Issue
++ */
++
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++ ring->funcs->vmhub == AMDGPU_MMHUB_1)
++ /* a read return value of 1 means semaphore acuqire */
++ amdgpu_ring_emit_reg_wait(ring,
++ hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
++
+ amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
+ lower_32_bits(pd_addr));
+
+@@ -495,6 +543,15 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ hub->vm_inv_eng0_ack + eng,
+ req, 1 << vmid);
+
++ /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++ if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++ ring->funcs->vmhub == AMDGPU_MMHUB_1)
++ /*
++ * add semaphore release after invalidation,
++ * write with 0 means semaphore release
++ */
++ amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
++
+ return pd_addr;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
+index 344280b869c4..d0fb7a67c1a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
+@@ -28,8 +28,8 @@
+ #include "nbio_v7_0.h"
+ #include "nbio_v7_4.h"
+
+-#define SOC15_FLUSH_GPU_TLB_NUM_WREG 4
+-#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 1
++#define SOC15_FLUSH_GPU_TLB_NUM_WREG 6
++#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3
+
+ extern const struct amd_ip_funcs soc15_common_ip_funcs;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4579-drm-amdkfd-Remove-duplicate-functions-update_mqd_hiq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4579-drm-amdkfd-Remove-duplicate-functions-update_mqd_hiq.patch
new file mode 100644
index 00000000..d1ee0e0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4579-drm-amdkfd-Remove-duplicate-functions-update_mqd_hiq.patch
@@ -0,0 +1,118 @@
+From a54a55ca5ec95676e24f1dd63c048760e4f1174e Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 9 Nov 2019 01:16:05 -0500
+Subject: [PATCH 4579/4736] drm/amdkfd: Remove duplicate functions
+ update_mqd_hiq()
+
+The functions are the same as update_mqd().
+
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 ++--------------
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 16 ++--------------
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 4 ----
+ 3 files changed, 4 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 65a03d1d79db..0487ddcbfa00 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -282,18 +282,6 @@ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
+ 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
+ }
+
+-static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
+- struct queue_properties *q)
+-{
+- struct v10_compute_mqd *m;
+-
+- update_mqd(mm, mqd, q);
+-
+- /* TODO: what's the point? update_mqd already does this. */
+- m = get_mqd(mqd);
+- m->cp_hqd_vmid = q->vmid;
+-}
+-
+ static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+ struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
+ struct queue_properties *q)
+@@ -423,7 +411,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd_hiq_sdma;
+ mqd->load_mqd = load_mqd;
+- mqd->update_mqd = update_mqd_hiq;
++ mqd->update_mqd = update_mqd;
+ mqd->destroy_mqd = destroy_mqd;
+ mqd->is_occupied = is_occupied;
+ mqd->mqd_size = sizeof(struct v10_compute_mqd);
+@@ -437,7 +425,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+- mqd->update_mqd = update_mqd_hiq;
++ mqd->update_mqd = update_mqd;
+ mqd->destroy_mqd = destroy_mqd;
+ mqd->is_occupied = is_occupied;
+ mqd->mqd_size = sizeof(struct v10_compute_mqd);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 822747377c28..d8fd332c7b14 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -409,18 +409,6 @@ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
+ 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
+ }
+
+-static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
+- struct queue_properties *q)
+-{
+- struct v9_mqd *m;
+-
+- update_mqd(mm, mqd, q);
+-
+- /* TODO: what's the point? update_mqd already does this. */
+- m = get_mqd(mqd);
+- m->cp_hqd_vmid = q->vmid;
+-}
+-
+ static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+ struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
+ struct queue_properties *q)
+@@ -548,7 +536,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd_hiq_sdma;
+ mqd->load_mqd = load_mqd;
+- mqd->update_mqd = update_mqd_hiq;
++ mqd->update_mqd = update_mqd;
+ mqd->destroy_mqd = destroy_mqd;
+ mqd->is_occupied = is_occupied;
+ mqd->check_queue_active = check_queue_active;
+@@ -562,7 +550,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+- mqd->update_mqd = update_mqd_hiq;
++ mqd->update_mqd = update_mqd;
+ mqd->destroy_mqd = destroy_mqd;
+ mqd->is_occupied = is_occupied;
+ mqd->check_queue_active = check_queue_active;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 39c9b470e227..6909b79361a7 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -353,11 +353,7 @@ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
+ static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
+ struct queue_properties *q)
+ {
+- struct vi_mqd *m;
+ __update_mqd(mm, mqd, q, MTYPE_UC, 0);
+-
+- m = get_mqd(mqd);
+- m->cp_hqd_vmid = q->vmid;
+ }
+
+ static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4580-drm-amd-powerplay-Use-ARRAY_SIZE-for-smu7_profiling.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4580-drm-amd-powerplay-Use-ARRAY_SIZE-for-smu7_profiling.patch
new file mode 100644
index 00000000..fac17dec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4580-drm-amd-powerplay-Use-ARRAY_SIZE-for-smu7_profiling.patch
@@ -0,0 +1,33 @@
+From d890a769542d98fa2e26548543322354fe1dfffe Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Fri, 22 Nov 2019 11:42:51 +0800
+Subject: [PATCH 4580/4736] drm/amd/powerplay: Use ARRAY_SIZE for
+ smu7_profiling
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:4946:28-29: WARNING: Use ARRAY_SIZE
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 5c6b71b356e7..901b5c263744 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -4942,7 +4942,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+ title[0], title[1], title[2], title[3],
+ title[4], title[5], title[6], title[7]);
+
+- len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
++ len = ARRAY_SIZE(smu7_profiling);
+
+ for (i = 0; i < len; i++) {
+ if (i == hwmgr->power_profile_mode) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4581-drm-amdgpu-Use-ARRAY_SIZE-for-sos_old_versions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4581-drm-amdgpu-Use-ARRAY_SIZE-for-sos_old_versions.patch
new file mode 100644
index 00000000..e818f35b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4581-drm-amdgpu-Use-ARRAY_SIZE-for-sos_old_versions.patch
@@ -0,0 +1,32 @@
+From fc4ba60efac03b9af545aee58cd5918ce5e601c2 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Fri, 22 Nov 2019 11:42:52 +0800
+Subject: [PATCH 4581/4736] drm/amdgpu: Use ARRAY_SIZE for sos_old_versions
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/amdgpu/psp_v3_1.c:182:40-41: WARNING: Use ARRAY_SIZE
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index 839806cf1c6a..773e272efc93 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -177,7 +177,7 @@ static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver)
+ * Double check if the latest four legacy versions.
+ * If yes, it is still the right version.
+ */
+- for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) {
++ for (i = 0; i < ARRAY_SIZE(sos_old_versions); i++) {
+ if (sos_old_versions[i] == adev->psp.sos_fw_version)
+ return true;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4582-drm-amd-display-add-default-clocks-if-not-able-to-fe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4582-drm-amd-display-add-default-clocks-if-not-able-to-fe.patch
new file mode 100644
index 00000000..bf21a228
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4582-drm-amd-display-add-default-clocks-if-not-able-to-fe.patch
@@ -0,0 +1,34 @@
+From 332156cfc87987494734f42a22cfb63359313d2f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 19 Nov 2019 15:54:17 -0500
+Subject: [PATCH 4582/4736] drm/amd/display: add default clocks if not able to
+ fetch them
+
+dm_pp_get_clock_levels_by_type needs to add the default clocks
+to the powerplay case as well. This was accidently dropped.
+
+Fixes: b3ea88fef321de ("drm/amd/powerplay: add get_clock_by_type interface for display")
+Bug: https://gitlab.freedesktop.org/drm/amd/issues/906
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 254123a02aa3..800cdfb5b566 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -343,7 +343,8 @@ bool dm_pp_get_clock_levels_by_type(
+ if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) {
+ if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
+ dc_to_pp_clock_type(clk_type), &pp_clks)) {
+- /* Error in pplib. Provide default values. */
++ /* Error in pplib. Provide default values. */
++ get_default_clock_levels(clk_type, dc_clks);
+ return true;
+ }
+ } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4583-drm-amdgpu-Apply-noretry-setting-for-mmhub9.4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4583-drm-amdgpu-Apply-noretry-setting-for-mmhub9.4.patch
new file mode 100644
index 00000000..9fb5677a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4583-drm-amdgpu-Apply-noretry-setting-for-mmhub9.4.patch
@@ -0,0 +1,40 @@
+From 806e277434cc6343e91dea823ed66099c6d1683b Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 22 Nov 2019 14:15:43 -0600
+Subject: [PATCH 4583/4736] drm/amdgpu: Apply noretry setting for mmhub9.4
+
+Config the translation retry behavior according to noretry
+kernel parameter
+
+Change-Id: I5b91ea77715137cf8cb84e258ccdfbb19c7a4ed1
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Suggested-by: Jay Cornwall <Jay.Cornwall@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 753eea25b569..8599bfdb9a9e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -314,7 +314,8 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
+ adev->vm_manager.block_size - 9);
+ /* Send no-retry XNACK on fault to suppress VM fault storm. */
+ tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
+- RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
++ RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
++ !amdgpu_noretry);
+ WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
+ hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i,
+ tmp);
+@@ -905,4 +906,4 @@ static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
+ const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
+ .ras_late_init = amdgpu_mmhub_ras_late_init,
+ .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
+-};
+\ No newline at end of file
++};
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4584-Revert-drm-amd-powerplay-read-pcie-speed-width-info.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4584-Revert-drm-amd-powerplay-read-pcie-speed-width-info.patch
new file mode 100644
index 00000000..d07ad400
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4584-Revert-drm-amd-powerplay-read-pcie-speed-width-info.patch
@@ -0,0 +1,198 @@
+From 80378c10988a4817bfffaeb7063e3dc1259f532e Mon Sep 17 00:00:00 2001
+From: "Stanley.Yang" <Stanley.Yang@amd.com>
+Date: Mon, 25 Nov 2019 15:50:45 +0800
+Subject: [PATCH 4584/4736] Revert "drm/amd/powerplay: read pcie speed/width
+ info"
+
+This reverts commit 3666556f6d713db86b4d593d5cc691cdba86fa85.
+
+Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 ---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 50 +------------------
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 3 --
+ 4 files changed, 5 insertions(+), 66 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index acbbafeea01c..d5335bdc709b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1081,6 +1081,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ return ret;
+
+ if (adev->asic_type != CHIP_ARCTURUS) {
++ ret = smu_override_pcie_parameters(smu);
++ if (ret)
++ return ret;
++
+ ret = smu_notify_display_change(smu);
+ if (ret)
+ return ret;
+@@ -1109,12 +1113,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ return ret;
+ }
+
+- if (adev->asic_type != CHIP_ARCTURUS) {
+- ret = smu_override_pcie_parameters(smu);
+- if (ret)
+- return ret;
+- }
+-
+ ret = smu_set_default_od_settings(smu, initialize);
+ if (ret)
+ return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 716fcb274191..ebdf7bd79a67 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -49,8 +49,6 @@
+
+ #define SMU11_TOOL_SIZE 0x19000
+
+-#define MAX_PCIE_CONF 2
+-
+ #define CLK_MAP(clk, index) \
+ [SMU_##clk] = {1, (index)}
+
+@@ -91,11 +89,6 @@ struct smu_11_0_dpm_table {
+ uint32_t max; /* MHz */
+ };
+
+-struct smu_11_0_pcie_table {
+- uint8_t pcie_gen[MAX_PCIE_CONF];
+- uint8_t pcie_lane[MAX_PCIE_CONF];
+-};
+-
+ struct smu_11_0_dpm_tables {
+ struct smu_11_0_dpm_table soc_table;
+ struct smu_11_0_dpm_table gfx_table;
+@@ -108,7 +101,6 @@ struct smu_11_0_dpm_tables {
+ struct smu_11_0_dpm_table display_table;
+ struct smu_11_0_dpm_table phy_table;
+ struct smu_11_0_dpm_table fclk_table;
+- struct smu_11_0_pcie_table pcie_table;
+ };
+
+ struct smu_11_0_dpm_context {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 24765e813cc2..aca913289e3c 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -35,7 +35,6 @@
+ #include "navi10_ppt.h"
+ #include "smu_v11_0_pptable.h"
+ #include "smu_v11_0_ppsmc.h"
+-#include "nbio/nbio_7_4_sh_mask.h"
+
+ #include "asic_reg/mp/mp_11_0_sh_mask.h"
+
+@@ -601,7 +600,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ PPTable_t *driver_ppt = NULL;
+- int i;
+
+ driver_ppt = table_context->driver_pptable;
+
+@@ -632,11 +630,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+ dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+
+- for (i = 0; i < MAX_PCIE_CONF; i++) {
+- dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
+- dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
+- }
+-
+ return 0;
+ }
+
+@@ -743,11 +736,6 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ struct smu_table_context *table_context = &smu->smu_table;
+ od_table = (OverDriveTable_t *)table_context->overdrive_table;
+ od_settings = smu->od_settings;
+- uint32_t gen_speed, lane_width;
+- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+- struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+- struct amdgpu_device *adev = smu->adev;
+- PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+@@ -798,30 +786,6 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+
+ }
+ break;
+- case SMU_PCIE:
+- gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+- >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+- lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+- PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+- >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+- for (i = 0; i < NUM_LINK_LEVELS; i++)
+- size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
+- (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
+- (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
+- (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
+- (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
+- (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
+- (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
+- (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
+- (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
+- (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
+- (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
+- pptable->LclkFreq[i],
+- (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
+- (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
+- "*" : "");
+- break;
+ case SMU_OD_SCLK:
+ if (!smu->od_enabled || !od_table || !od_settings)
+ break;
+@@ -1758,9 +1722,6 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ int ret, i;
+ uint32_t smu_pcie_arg;
+
+- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+- struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+-
+ for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ smu_pcie_arg = (i << 16) |
+ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
+@@ -1769,17 +1730,8 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_OverridePcieParameters,
+ smu_pcie_arg);
+-
+- if (ret)
+- return ret;
+-
+- if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
+- dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
+- if (pptable->PcieLaneCount[i] > pcie_width_cap)
+- dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
+ }
+-
+- return 0;
++ return ret;
+ }
+
+ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index ec03c7992f6d..fd6dda1a67a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -35,9 +35,6 @@
+
+ #define NAVI10_VOLTAGE_SCALE (4)
+
+-#define smnPCIE_LC_SPEED_CNTL 0x11140290
+-#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
+-
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch
new file mode 100644
index 00000000..72664fbb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch
@@ -0,0 +1,214 @@
+From 1eb88c64a5d5fa596fc96e37b5f72e79a7da6064 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Tue, 12 Nov 2019 16:27:11 +0800
+Subject: [PATCH 4585/4736] drm/amd/powerplay: read pcie speed/width info (v2)
+
+sysfs interface to read pcie speed&width info on navi1x.
+
+v2: fix warning (trivial)
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 57 +++++++++++++++++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 3 +
+ 4 files changed, 69 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d5335bdc709b..acbbafeea01c 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1081,10 +1081,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ return ret;
+
+ if (adev->asic_type != CHIP_ARCTURUS) {
+- ret = smu_override_pcie_parameters(smu);
+- if (ret)
+- return ret;
+-
+ ret = smu_notify_display_change(smu);
+ if (ret)
+ return ret;
+@@ -1113,6 +1109,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ return ret;
+ }
+
++ if (adev->asic_type != CHIP_ARCTURUS) {
++ ret = smu_override_pcie_parameters(smu);
++ if (ret)
++ return ret;
++ }
++
+ ret = smu_set_default_od_settings(smu, initialize);
+ if (ret)
+ return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index ebdf7bd79a67..716fcb274191 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -49,6 +49,8 @@
+
+ #define SMU11_TOOL_SIZE 0x19000
+
++#define MAX_PCIE_CONF 2
++
+ #define CLK_MAP(clk, index) \
+ [SMU_##clk] = {1, (index)}
+
+@@ -89,6 +91,11 @@ struct smu_11_0_dpm_table {
+ uint32_t max; /* MHz */
+ };
+
++struct smu_11_0_pcie_table {
++ uint8_t pcie_gen[MAX_PCIE_CONF];
++ uint8_t pcie_lane[MAX_PCIE_CONF];
++};
++
+ struct smu_11_0_dpm_tables {
+ struct smu_11_0_dpm_table soc_table;
+ struct smu_11_0_dpm_table gfx_table;
+@@ -101,6 +108,7 @@ struct smu_11_0_dpm_tables {
+ struct smu_11_0_dpm_table display_table;
+ struct smu_11_0_dpm_table phy_table;
+ struct smu_11_0_dpm_table fclk_table;
++ struct smu_11_0_pcie_table pcie_table;
+ };
+
+ struct smu_11_0_dpm_context {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index aca913289e3c..c94c2b67c309 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -35,6 +35,7 @@
+ #include "navi10_ppt.h"
+ #include "smu_v11_0_pptable.h"
+ #include "smu_v11_0_ppsmc.h"
++#include "nbio/nbio_7_4_sh_mask.h"
+
+ #include "asic_reg/mp/mp_11_0_sh_mask.h"
+
+@@ -600,6 +601,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ PPTable_t *driver_ppt = NULL;
++ int i;
+
+ driver_ppt = table_context->driver_pptable;
+
+@@ -630,6 +632,11 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+ dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+
++ for (i = 0; i < MAX_PCIE_CONF; i++) {
++ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
++ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
++ }
++
+ return 0;
+ }
+
+@@ -726,16 +733,20 @@ static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_tabl
+ static int navi10_print_clk_levels(struct smu_context *smu,
+ enum smu_clk_type clk_type, char *buf)
+ {
+- OverDriveTable_t *od_table;
+- struct smu_11_0_overdrive_table *od_settings;
+ uint16_t *curve_settings;
+ int i, size = 0, ret = 0;
+ uint32_t cur_value = 0, value = 0, count = 0;
+ uint32_t freq_values[3] = {0};
+ uint32_t mark_index = 0;
+ struct smu_table_context *table_context = &smu->smu_table;
+- od_table = (OverDriveTable_t *)table_context->overdrive_table;
+- od_settings = smu->od_settings;
++ uint32_t gen_speed, lane_width;
++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++ struct amdgpu_device *adev = smu->adev;
++ PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
++ OverDriveTable_t *od_table =
++ (OverDriveTable_t *)table_context->overdrive_table;
++ struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+@@ -786,6 +797,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+
+ }
+ break;
++ case SMU_PCIE:
++ gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
++ PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
++ >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
++ lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
++ PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
++ >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
++ for (i = 0; i < NUM_LINK_LEVELS; i++)
++ size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
++ (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
++ (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
++ pptable->LclkFreq[i],
++ (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
++ (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
++ "*" : "");
++ break;
+ case SMU_OD_SCLK:
+ if (!smu->od_enabled || !od_table || !od_settings)
+ break;
+@@ -1722,6 +1757,9 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ int ret, i;
+ uint32_t smu_pcie_arg;
+
++ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++
+ for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ smu_pcie_arg = (i << 16) |
+ ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
+@@ -1730,8 +1768,17 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_OverridePcieParameters,
+ smu_pcie_arg);
++
++ if (ret)
++ return ret;
++
++ if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
++ dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
++ if (pptable->PcieLaneCount[i] > pcie_width_cap)
++ dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
+ }
+- return ret;
++
++ return 0;
+ }
+
+ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index fd6dda1a67a1..ec03c7992f6d 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -35,6 +35,9 @@
+
+ #define NAVI10_VOLTAGE_SCALE (4)
+
++#define smnPCIE_LC_SPEED_CNTL 0x11140290
++#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4586-Revert-drm-amd-powerplay-enable-gpu_busy_percent-sys.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4586-Revert-drm-amd-powerplay-enable-gpu_busy_percent-sys.patch
new file mode 100644
index 00000000..1e103903
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4586-Revert-drm-amd-powerplay-enable-gpu_busy_percent-sys.patch
@@ -0,0 +1,192 @@
+From d3356fee47c1ba461195da707e7b0c0e9868fd80 Mon Sep 17 00:00:00 2001
+From: "Stanley.Yang" <Stanley.Yang@amd.com>
+Date: Mon, 25 Nov 2019 16:51:51 +0800
+Subject: [PATCH 4586/4736] Revert "drm/amd/powerplay: enable gpu_busy_percent
+ sys interface for renoir"
+
+This reverts commit 06a4360eecaf6c178518c3b531a583f2fe4c6ae6.
+
+Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 4 -
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 75 -------------------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 33 --------
+ 3 files changed, 112 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 44c65dd8850d..1745e0146fba 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -62,10 +62,6 @@ int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
+
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+
+-int smu_v12_0_read_sensor(struct smu_context *smu,
+- enum amd_pp_sensors sensor,
+- void *data, uint32_t *size);
+-
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+
+ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index b44ce143e895..2c624cdf1d81 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -139,27 +139,6 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ return mapping.map_to;
+ }
+
+-static int renoir_get_metrics_table(struct smu_context *smu,
+- SmuMetrics_t *metrics_table)
+-{
+- struct smu_table_context *smu_table= &smu->smu_table;
+- int ret = 0;
+-
+- if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
+- ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+- (void *)smu_table->metrics_table, false);
+- if (ret) {
+- pr_info("Failed to export SMU metrics table!\n");
+- return ret;
+- }
+- smu_table->metrics_time = jiffies;
+- }
+-
+- memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+-
+- return ret;
+-}
+-
+ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+@@ -175,11 +154,6 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ if (!smu_table->clocks_table)
+ return -ENOMEM;
+
+- smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+- if (!smu_table->metrics_table)
+- return -ENOMEM;
+- smu_table->metrics_time = 0;
+-
+ return 0;
+ }
+
+@@ -412,32 +386,6 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ return ret;
+ }
+
+-static int renoir_get_current_activity_percent(struct smu_context *smu,
+- enum amd_pp_sensors sensor,
+- uint32_t *value)
+-{
+- int ret = 0;
+- SmuMetrics_t metrics;
+-
+- if (!value)
+- return -EINVAL;
+-
+- ret = renoir_get_metrics_table(smu, &metrics);
+- if (ret)
+- return ret;
+-
+- switch (sensor) {
+- case AMDGPU_PP_SENSOR_GPU_LOAD:
+- *value = metrics.AverageGfxActivity;
+- break;
+- default:
+- pr_err("Invalid sensor for retrieving clock activity\n");
+- return -EINVAL;
+- }
+-
+- return 0;
+-}
+-
+ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
+ {
+
+@@ -751,28 +699,6 @@ static int renoir_get_power_profile_mode(struct smu_context *smu,
+ return size;
+ }
+
+-static int renoir_read_sensor(struct smu_context *smu,
+- enum amd_pp_sensors sensor,
+- void *data, uint32_t *size)
+-{
+- int ret = 0;
+-
+- if (!data || !size)
+- return -EINVAL;
+-
+- mutex_lock(&smu->sensor_lock);
+- switch (sensor) {
+- case AMDGPU_PP_SENSOR_GPU_LOAD:
+- ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
+- *size = 4;
+- break;
+- default:
+- ret = smu_v12_0_read_sensor(smu, sensor, data, size);
+- }
+- mutex_unlock(&smu->sensor_lock);
+-
+- return ret;
+-}
+
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_smu_msg_index = renoir_get_smu_msg_index,
+@@ -794,7 +720,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_dpm_clock_table = renoir_get_dpm_clock_table,
+ .set_watermarks_table = renoir_set_watermarks_table,
+ .get_power_profile_mode = renoir_get_power_profile_mode,
+- .read_sensor = renoir_read_sensor,
+ .check_fw_status = smu_v12_0_check_fw_status,
+ .check_fw_version = smu_v12_0_check_fw_version,
+ .powergate_sdma = smu_v12_0_powergate_sdma,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 045167311ae8..18b24f954380 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -223,39 +223,6 @@ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+
+-int smu_v12_0_read_sensor(struct smu_context *smu,
+- enum amd_pp_sensors sensor,
+- void *data, uint32_t *size)
+-{
+- int ret = 0;
+-
+- if(!data || !size)
+- return -EINVAL;
+-
+- switch (sensor) {
+- case AMDGPU_PP_SENSOR_GFX_MCLK:
+- ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
+- *size = 4;
+- break;
+- case AMDGPU_PP_SENSOR_GFX_SCLK:
+- ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
+- *size = 4;
+- break;
+- case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
+- *(uint32_t *)data = 0;
+- *size = 4;
+- break;
+- default:
+- ret = smu_common_read_sensor(smu, sensor, data, size);
+- break;
+- }
+-
+- if (ret)
+- *size = 0;
+-
+- return ret;
+-}
+-
+ /**
+ * smu_v12_0_get_gfxoff_status - get gfxoff status
+ *
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4587-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4587-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
new file mode 100644
index 00000000..9301c8cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4587-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
@@ -0,0 +1,201 @@
+From 648728cff5215646111ed6176035e676253a8c60 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Wed, 13 Nov 2019 17:17:09 +0800
+Subject: [PATCH 4587/4736] drm/amd/powerplay: enable gpu_busy_percent sys
+ interface for renoir (v2)
+
+To get the value of gpu_busy_percent, it needs to realize
+get_current_activity_percent and get_metrics_table.
+The framework of renoir smu is different from old ones like raven. It
+needs to realize get_current_activity_percent and get_metrics_table in
+renoir_ppt.c like navi10.
+
+v2: remove unused variable (Alex)
+
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 4 +
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 76 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 33 ++++++++
+ 3 files changed, 113 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 1745e0146fba..44c65dd8850d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -62,6 +62,10 @@ int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
+
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+
++int smu_v12_0_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size);
++
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+
+ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 2c624cdf1d81..e5ff08820658 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -139,6 +139,27 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ return mapping.map_to;
+ }
+
++static int renoir_get_metrics_table(struct smu_context *smu,
++ SmuMetrics_t *metrics_table)
++{
++ struct smu_table_context *smu_table= &smu->smu_table;
++ int ret = 0;
++
++ if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
++ ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++ (void *)smu_table->metrics_table, false);
++ if (ret) {
++ pr_info("Failed to export SMU metrics table!\n");
++ return ret;
++ }
++ smu_table->metrics_time = jiffies;
++ }
++
++ memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
++
++ return ret;
++}
++
+ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+@@ -154,6 +175,11 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ if (!smu_table->clocks_table)
+ return -ENOMEM;
+
++ smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
++ if (!smu_table->metrics_table)
++ return -ENOMEM;
++ smu_table->metrics_time = 0;
++
+ return 0;
+ }
+
+@@ -386,6 +412,32 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ return ret;
+ }
+
++static int renoir_get_current_activity_percent(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ uint32_t *value)
++{
++ int ret = 0;
++ SmuMetrics_t metrics;
++
++ if (!value)
++ return -EINVAL;
++
++ ret = renoir_get_metrics_table(smu, &metrics);
++ if (ret)
++ return ret;
++
++ switch (sensor) {
++ case AMDGPU_PP_SENSOR_GPU_LOAD:
++ *value = metrics.AverageGfxActivity;
++ break;
++ default:
++ pr_err("Invalid sensor for retrieving clock activity\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
+ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
+ {
+
+@@ -700,6 +752,29 @@ static int renoir_get_power_profile_mode(struct smu_context *smu,
+ }
+
+
++static int renoir_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size)
++{
++ int ret = 0;
++
++ if (!data || !size)
++ return -EINVAL;
++
++ mutex_lock(&smu->sensor_lock);
++ switch (sensor) {
++ case AMDGPU_PP_SENSOR_GPU_LOAD:
++ ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
++ *size = 4;
++ break;
++ default:
++ ret = smu_v12_0_read_sensor(smu, sensor, data, size);
++ }
++ mutex_unlock(&smu->sensor_lock);
++
++ return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_smu_msg_index = renoir_get_smu_msg_index,
+ .get_smu_table_index = renoir_get_smu_table_index,
+@@ -720,6 +795,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_dpm_clock_table = renoir_get_dpm_clock_table,
+ .set_watermarks_table = renoir_set_watermarks_table,
+ .get_power_profile_mode = renoir_get_power_profile_mode,
++ .read_sensor = renoir_read_sensor,
+ .check_fw_status = smu_v12_0_check_fw_status,
+ .check_fw_version = smu_v12_0_check_fw_version,
+ .powergate_sdma = smu_v12_0_powergate_sdma,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 18b24f954380..045167311ae8 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -223,6 +223,39 @@ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+
++int smu_v12_0_read_sensor(struct smu_context *smu,
++ enum amd_pp_sensors sensor,
++ void *data, uint32_t *size)
++{
++ int ret = 0;
++
++ if(!data || !size)
++ return -EINVAL;
++
++ switch (sensor) {
++ case AMDGPU_PP_SENSOR_GFX_MCLK:
++ ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
++ *size = 4;
++ break;
++ case AMDGPU_PP_SENSOR_GFX_SCLK:
++ ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
++ *size = 4;
++ break;
++ case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
++ *(uint32_t *)data = 0;
++ *size = 4;
++ break;
++ default:
++ ret = smu_common_read_sensor(smu, sensor, data, size);
++ break;
++ }
++
++ if (ret)
++ *size = 0;
++
++ return ret;
++}
++
+ /**
+ * smu_v12_0_get_gfxoff_status - get gfxoff status
+ *
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4588-Revert-drm-amdkfd-add-missing-mqd-init-from-kfd-stag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4588-Revert-drm-amdkfd-add-missing-mqd-init-from-kfd-stag.patch
new file mode 100644
index 00000000..3bfc13c0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4588-Revert-drm-amdkfd-add-missing-mqd-init-from-kfd-stag.patch
@@ -0,0 +1,70 @@
+From 61a5456532d8e58d3d5ec61c43998179d05495be Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Tue, 26 Nov 2019 13:09:09 +0800
+Subject: [PATCH 4588/4736] Revert "drm/amdkfd: add missing mqd init from
+ kfd-staging"
+
+This reverts commit 898a4edbdfcd6361324cebd82ebf2eac30566f5b.
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 9431dc2ca54b..c8561c3283b2 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -432,7 +432,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 0487ddcbfa00..afe2d3bb5c24 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -421,7 +421,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ pr_debug("%s@%i\n", __func__, __LINE__);
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index d8fd332c7b14..5d691d36599f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -546,7 +546,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 6909b79361a7..7c56b850b00f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -492,7 +492,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ #endif
+ break;
+ case KFD_MQD_TYPE_DIQ:
+- mqd->allocate_mqd = allocate_hiq_mqd;
++ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd_hiq;
+ mqd->free_mqd = free_mqd;
+ mqd->load_mqd = load_mqd;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4589-Revert-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4589-Revert-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
new file mode 100644
index 00000000..ad79aeac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4589-Revert-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
@@ -0,0 +1,122 @@
+From 56423d2187b56d80fc34b4186b5a8ef8941eea4f Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Tue, 26 Nov 2019 13:10:51 +0800
+Subject: [PATCH 4589/4736] Revert "drm/amdkfd: add missing
+ KFD_MQD_TYPE_COMPUTE"
+
+This reverts commit ab30ae4ff91d3fbaffdee54985ce1b0624222bff.
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +--
+ 6 files changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 76c7f0ec3de3..f2325e5f15ce 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1744,7 +1744,7 @@ static int get_wave_state(struct device_queue_manager *dqm,
+ goto dqm_unlock;
+ }
+
+- mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++ mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+
+ if (!mqd_mgr->get_wave_state) {
+ r = -EINVAL;
+@@ -2187,7 +2187,7 @@ void copy_context_work_handler (struct work_struct *work)
+
+
+ list_for_each_entry(q, &qpd->queues_list, list) {
+- mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++ mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+
+ /* We ignore the return value from get_wave_state
+ * because
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index c8561c3283b2..37ce9571a175 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -403,7 +403,6 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+@@ -475,7 +474,7 @@ struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
+ mqd = mqd_manager_init_cik(type, dev);
+ if (!mqd)
+ return NULL;
+- if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++ if (type == KFD_MQD_TYPE_CP)
+ mqd->update_mqd = update_mqd_hawaii;
+ return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index afe2d3bb5c24..4677ed90d16c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -389,7 +389,6 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ pr_debug("%s@%i\n", __func__, __LINE__);
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 5d691d36599f..f9ee530774bf 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -516,7 +516,6 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 7c56b850b00f..2aeba387d7d6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -462,7 +462,6 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+
+ switch (type) {
+ case KFD_MQD_TYPE_CP:
+- case KFD_MQD_TYPE_COMPUTE:
+ mqd->allocate_mqd = allocate_mqd;
+ mqd->init_mqd = init_mqd;
+ mqd->free_mqd = free_mqd;
+@@ -535,7 +534,7 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
+ mqd = mqd_manager_init_vi(type, dev);
+ if (!mqd)
+ return NULL;
+- if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++ if (type == KFD_MQD_TYPE_CP)
+ mqd->update_mqd = update_mqd_tonga;
+ return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index e937679f8ca1..b91029047953 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -576,8 +576,7 @@ struct queue {
+ * Please read the kfd_mqd_manager.h description.
+ */
+ enum KFD_MQD_TYPE {
+- KFD_MQD_TYPE_COMPUTE = 0, /* for no cp scheduling */
+- KFD_MQD_TYPE_HIQ, /* for hiq */
++ KFD_MQD_TYPE_HIQ = 0, /* for hiq */
+ KFD_MQD_TYPE_CP, /* for cp queues and diq */
+ KFD_MQD_TYPE_SDMA, /* for sdma queues */
+ KFD_MQD_TYPE_DIQ, /* for diq */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4590-drm-amd-amdgpu-sriov-skip-jpeg-ip-block-for-ARCTURUS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4590-drm-amd-amdgpu-sriov-skip-jpeg-ip-block-for-ARCTURUS.patch
new file mode 100644
index 00000000..f0e03550
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4590-drm-amd-amdgpu-sriov-skip-jpeg-ip-block-for-ARCTURUS.patch
@@ -0,0 +1,32 @@
+From 677928bc86ece7e295bac905e8c9017e41bf9e42 Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Tue, 26 Nov 2019 14:47:29 +0800
+Subject: [PATCH 4590/4736] drm/amd/amdgpu/sriov skip jpeg ip block for
+ ARCTURUS VF
+
+Currently ARCTURUS VF doesn't support jpeg ip block.
+Skip jpeg ip block in case guest driver load fail.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Zhexi Zhang <zhexi.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 805a92f87bf3..3a2ec932c0bb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -833,7 +833,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+
+ if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
+ amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+- amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
++ if (!amdgpu_sriov_vf(adev))
++ amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
+ break;
+ case CHIP_RENOIR:
+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4591-drm-amdgpu-Resolved-offchip-EEPROM-I-O-issue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4591-drm-amdgpu-Resolved-offchip-EEPROM-I-O-issue.patch
new file mode 100644
index 00000000..34ad9b8b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4591-drm-amdgpu-Resolved-offchip-EEPROM-I-O-issue.patch
@@ -0,0 +1,104 @@
+From 323de75bf9aaa107e8d18e3b9596a3ac2d30d578 Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Mon, 25 Nov 2019 18:24:17 +0800
+Subject: [PATCH 4591/4736] drm/amdgpu: Resolved offchip EEPROM I/O issue
+
+Updated target I2C address
+
+Change-Id: Ie86f7f3214177e3902b02a6b8201421375a89ae4
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 17 ++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 1 +
+ 2 files changed, 13 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 7de16c0c2f20..2a8e04895595 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -27,7 +27,8 @@
+ #include <linux/bits.h>
+ #include "smu_v11_0_i2c.h"
+
+-#define EEPROM_I2C_TARGET_ADDR 0xA0
++#define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8
++#define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0
+
+ /*
+ * The 2 macros bellow represent the actual size in bytes that
+@@ -83,7 +84,7 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
+ {
+ int ret = 0;
+ struct i2c_msg msg = {
+- .addr = EEPROM_I2C_TARGET_ADDR,
++ .addr = 0,
+ .flags = 0,
+ .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
+ .buf = buff,
+@@ -93,6 +94,8 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
+ *(uint16_t *)buff = EEPROM_HDR_START;
+ __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
+
++ msg.addr = control->i2c_address;
++
+ ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
+ if (ret < 1)
+ DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
+@@ -203,7 +206,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
+ struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
+ struct i2c_msg msg = {
+- .addr = EEPROM_I2C_TARGET_ADDR,
++ .addr = 0,
+ .flags = I2C_M_RD,
+ .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
+ .buf = buff,
+@@ -213,10 +216,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
++ control->i2c_address = EEPROM_I2C_TARGET_ADDR_VEGA20;
+ ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
+ break;
+
+ case CHIP_ARCTURUS:
++ control->i2c_address = EEPROM_I2C_TARGET_ADDR_ARCTURUS;
+ ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
+ break;
+
+@@ -229,6 +234,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ return ret;
+ }
+
++ msg.addr = control->i2c_address;
++
+ /* Read/Create table header from EEPROM address 0 */
+ ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
+ if (ret < 1) {
+@@ -408,8 +415,8 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ * Update bits 16,17 of EEPROM address in I2C address by setting them
+ * to bits 1,2 of Device address byte
+ */
+- msg->addr = EEPROM_I2C_TARGET_ADDR |
+- ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
++ msg->addr = control->i2c_address |
++ ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
+ msg->flags = write ? 0 : I2C_M_RD;
+ msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
+ msg->buf = buff;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+index 622269957c1b..ca78f812d436 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+@@ -50,6 +50,7 @@ struct amdgpu_ras_eeprom_control {
+ struct mutex tbl_mutex;
+ bool bus_locked;
+ uint32_t tbl_byte_sum;
++ uint16_t i2c_address; // 8-bit represented address
+ };
+
+ /*
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4592-drm-amd-Fix-Kconfig-indentation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4592-drm-amd-Fix-Kconfig-indentation.patch
new file mode 100644
index 00000000..fd49f296
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4592-drm-amd-Fix-Kconfig-indentation.patch
@@ -0,0 +1,40 @@
+From 61f5f09dcccbda3755e7989735e4e053161a288a Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzk@kernel.org>
+Date: Thu, 21 Nov 2019 21:29:30 +0800
+Subject: [PATCH 4592/4736] drm/amd: Fix Kconfig indentation
+
+Adjust indentation from spaces to tab (+optional two spaces) as in
+coding style with command like:
+ $ sed -e 's/^ /\t/' -i */Kconfig
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/acp/Kconfig | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
+index e503e3d6d920..fc1f9194781e 100644
+--- a/drivers/gpu/drm/amd/acp/Kconfig
++++ b/drivers/gpu/drm/amd/acp/Kconfig
+@@ -1,11 +1,11 @@
+ menu "ACP (Audio CoProcessor) Configuration"
+
+ config DRM_AMD_ACP
+- bool "Enable AMD Audio CoProcessor IP support"
+- depends on DRM_AMDGPU
+- select MFD_CORE
+- select PM_GENERIC_DOMAINS if PM
+- help
++ bool "Enable AMD Audio CoProcessor IP support"
++ depends on DRM_AMDGPU
++ select MFD_CORE
++ select PM_GENERIC_DOMAINS if PM
++ help
+ Choose this option to enable ACP IP support for AMD SOCs.
+ This adds the ACP (Audio CoProcessor) IP driver and wires
+ it up into the amdgpu driver. The ACP block provides the DMA
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4593-MAINTAINERS-Drop-Rex-Zhu-for-amdgpu-powerplay.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4593-MAINTAINERS-Drop-Rex-Zhu-for-amdgpu-powerplay.patch
new file mode 100644
index 00000000..ba63b9af
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4593-MAINTAINERS-Drop-Rex-Zhu-for-amdgpu-powerplay.patch
@@ -0,0 +1,29 @@
+From 3268488a9583dccd84309eac3af94a5910042a2a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 22 Nov 2019 14:16:55 -0500
+Subject: [PATCH 4593/4736] MAINTAINERS: Drop Rex Zhu for amdgpu powerplay
+
+No longer works on the driver.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ MAINTAINERS | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 38f553e09240..3a4c825b520b 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -786,7 +786,6 @@ F: drivers/gpu/drm/amd/include/v9_structs.h
+ F: include/uapi/linux/kfd_ioctl.h
+
+ AMD POWERPLAY
+-M: Rex Zhu <rex.zhu@amd.com>
+ M: Evan Quan <evan.quan@amd.com>
+ L: amd-gfx@lists.freedesktop.org
+ S: Supported
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4594-drm-amd-powerplay-remove-redundant-assignment-to-var.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4594-drm-amd-powerplay-remove-redundant-assignment-to-var.patch
new file mode 100644
index 00000000..67733212
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4594-drm-amd-powerplay-remove-redundant-assignment-to-var.patch
@@ -0,0 +1,35 @@
+From bf8c2ee372d7c70161ef6f75da978bdaa925d9c0 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 22 Nov 2019 23:04:07 +0000
+Subject: [PATCH 4594/4736] drm/amd/powerplay: remove redundant assignment to
+ variables HiSidd and LoSidd
+
+The variables HiSidd and LoSidd are being initialized with values that
+are never read and are being updated a little later with a new value.
+The initialization is redundant and can be removed.
+
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+index edc5fba0f3e1..405bae2872b3 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+@@ -652,8 +652,8 @@ static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
+ static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+ {
+ struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+- uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
+- uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
++ uint16_t HiSidd;
++ uint16_t LoSidd;
+ struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
+
+ HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4595-drm-amdgpu-Ensure-ret-is-always-initialized-when-usi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4595-drm-amdgpu-Ensure-ret-is-always-initialized-when-usi.patch
new file mode 100644
index 00000000..3a317415
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4595-drm-amdgpu-Ensure-ret-is-always-initialized-when-usi.patch
@@ -0,0 +1,64 @@
+From 6c13d7d3ba65090b6817972126a06f380f8e20b8 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Sat, 23 Nov 2019 12:23:36 -0700
+Subject: [PATCH 4595/4736] drm/amdgpu: Ensure ret is always initialized when
+ using SOC15_WAIT_ON_RREG
+
+Commit b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from
+VCN2.0") introduced a new clang warning in the vcn_v2_0_stop function:
+
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: warning: variable 'r'
+is used uninitialized whenever 'while' loop exits because its condition
+is false [-Wsometimes-uninitialized]
+ SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
+expanded from macro 'SOC15_WAIT_ON_RREG'
+ while ((tmp_ & (mask)) != (expected_value)) { \
+ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1083:6: note: uninitialized use
+occurs here
+ if (r)
+ ^
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: note: remove the
+condition if it is always true
+ SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+ ^
+../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
+expanded from macro 'SOC15_WAIT_ON_RREG'
+ while ((tmp_ & (mask)) != (expected_value)) { \
+ ^
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1072:7: note: initialize the
+variable 'r' to silence this warning
+ int r;
+ ^
+ = 0
+1 warning generated.
+
+To prevent warnings like this from happening in the future, make the
+SOC15_WAIT_ON_RREG macro initialize its ret variable before the while
+loop that can time out. This macro's return value is always checked so
+it should set ret in both the success and fail path.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/776
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+index 839f186e1182..19e870c79896 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+@@ -52,6 +52,7 @@
+ uint32_t old_ = 0; \
+ uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+ uint32_t loop = adev->usec_timeout; \
++ ret = 0; \
+ while ((tmp_ & (mask)) != (expected_value)) { \
+ if (old_ != tmp_) { \
+ loop = adev->usec_timeout; \
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4596-drm-amd-display-remove-set-but-not-used-variable-msg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4596-drm-amd-display-remove-set-but-not-used-variable-msg.patch
new file mode 100644
index 00000000..c6bf1407
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4596-drm-amd-display-remove-set-but-not-used-variable-msg.patch
@@ -0,0 +1,57 @@
+From 2444f631c300021dccd5fe68688bd78bf1da8da3 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 25 Nov 2019 22:54:45 +0800
+Subject: [PATCH 4596/4736] drm/amd/display: remove set but not used variable
+ 'msg_out'
+
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c: In function mod_hdcp_hdcp2_enable_encryption:
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:633:77: warning: variable msg_out set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c: In function mod_hdcp_hdcp2_enable_dp_stream_encryption:
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:710:77: warning: variable msg_out set but not used [-Wunused-but-set-variable]
+
+It is never used, so remove it.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index 2dd5feec8e6c..468f5e6c3487 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -630,14 +630,12 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp)
+ struct psp_context *psp = hdcp->config.psp.handle;
+ struct ta_hdcp_shared_memory *hdcp_cmd;
+ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
+- struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
+ struct mod_hdcp_display *display = get_first_added_display(hdcp);
+
+ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
+ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
+
+ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
+- msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
+
+ hdcp2_message_init(hdcp, msg_in);
+
+@@ -707,14 +705,12 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(struct mod_hdcp
+ struct psp_context *psp = hdcp->config.psp.handle;
+ struct ta_hdcp_shared_memory *hdcp_cmd;
+ struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
+- struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
+ uint8_t i;
+
+ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
+ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
+
+ msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
+- msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
+
+ hdcp2_message_init(hdcp, msg_in);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4597-drm-amd-powerplay-remove-set-but-not-used-variable-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4597-drm-amd-powerplay-remove-set-but-not-used-variable-s.patch
new file mode 100644
index 00000000..e28b485d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4597-drm-amd-powerplay-remove-set-but-not-used-variable-s.patch
@@ -0,0 +1,50 @@
+From 73bbe069ff269e69ba108a150cd3139433d09930 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 25 Nov 2019 22:58:43 +0800
+Subject: [PATCH 4597/4736] drm/amd/powerplay: remove set but not used variable
+ 'stretch_amount2'
+
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:
+ In function vegam_populate_clock_stretcher_data_table:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:1489:29:
+ warning: variable stretch_amount2 set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index 50896e9b2579..b0e0d67cd54b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -1486,7 +1486,7 @@ static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+ struct vegam_smumgr *smu_data =
+ (struct vegam_smumgr *)(hwmgr->smu_backend);
+
+- uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
++ uint8_t i, stretch_amount, volt_offset = 0;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+@@ -1525,11 +1525,9 @@ static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+ (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
+ table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
+ /* Populate CKS Lookup Table */
+- if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
+- stretch_amount2 = 0;
+- else if (stretch_amount == 3 || stretch_amount == 4)
+- stretch_amount2 = 1;
+- else {
++ if (!(stretch_amount == 1 || stretch_amount == 2 ||
++ stretch_amount == 5 || stretch_amount == 3 ||
++ stretch_amount == 4)) {
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ClockStretcher);
+ PP_ASSERT_WITH_CODE(false,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4598-drm-amd-display-Null-check-aconnector-in-event_prope.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4598-drm-amd-display-Null-check-aconnector-in-event_prope.patch
new file mode 100644
index 00000000..280900f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4598-drm-amd-display-Null-check-aconnector-in-event_prope.patch
@@ -0,0 +1,42 @@
+From a274fbfefeca017c09c8536ac85dce2fcf9866c7 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 25 Nov 2019 10:34:13 -0500
+Subject: [PATCH 4598/4736] drm/amd/display: Null check aconnector in
+ event_property_validate
+
+[Why]
+previously event_property_validate was only called after we enabled the display.
+But after "Refactor HDCP to handle multiple displays per link" this function
+can be called at any time. In certain cases we don't have a aconnector
+
+[How]
+Null check aconnector and exit early. This is ok because we only need to check the
+ENABLED->DESIRED transition if a connector exists.
+
+Fixes: cc5dae9f6286 ("drm/amd/display: Refactor HDCP to handle multiple
+displays per link")
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index f6864a51891a..ae329335dfcc 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -225,6 +225,9 @@ static void event_property_validate(struct work_struct *work)
+ struct mod_hdcp_display_query query;
+ struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
+
++ if (!aconnector)
++ return;
++
+ mutex_lock(&hdcp_work->mutex);
+
+ query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4599-drm-amdgpu-Raise-KFD-unpinned-system-memory-limit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4599-drm-amdgpu-Raise-KFD-unpinned-system-memory-limit.patch
new file mode 100644
index 00000000..f46adc4b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4599-drm-amdgpu-Raise-KFD-unpinned-system-memory-limit.patch
@@ -0,0 +1,39 @@
+From eeef2304ec82d7aa4a53e26d1500cd431baeb7d0 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 25 Nov 2019 16:25:35 -0500
+Subject: [PATCH 4599/4736] drm/amdgpu: Raise KFD unpinned system memory limit
+
+Allow KFD applications to use more unpinned system memory through
+HMM.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 083bd8fe8057..a0d138849b61 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -85,7 +85,7 @@ static bool check_if_add_bo_to_vm(struct amdgpu_vm *avm,
+ }
+
+ /* Set memory usage limits. Current, limits are
+- * System (TTM + userptr) memory - 3/4th System RAM
++ * System (TTM + userptr) memory - 15/16th System RAM
+ * TTM memory - 3/8th System RAM
+ */
+ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
+@@ -98,7 +98,7 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
+ mem *= si.mem_unit;
+
+ spin_lock_init(&kfd_mem_limit.mem_limit_lock);
+- kfd_mem_limit.max_system_mem_limit = (mem >> 1) + (mem >> 2);
++ kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
+ kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
+ pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
+ (kfd_mem_limit.max_system_mem_limit >> 20),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4600-drm-amdgpu-Optimize-KFD-page-table-reservation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4600-drm-amdgpu-Optimize-KFD-page-table-reservation.patch
new file mode 100644
index 00000000..5f502cc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4600-drm-amdgpu-Optimize-KFD-page-table-reservation.patch
@@ -0,0 +1,53 @@
+From 2bd2c52721418a622b717d892211569b53db0120 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 15 Jul 2019 16:18:03 -0400
+Subject: [PATCH 4600/4736] drm/amdgpu: Optimize KFD page table reservation
+
+Be less pessimistic about estimated page table use for KFD. Most
+allocations use 2MB pages and therefore need less VRAM for page
+tables. This allows more VRAM to be used for applications especially
+on large systems with many GPUs and hundreds of GB of system memory.
+
+Example: 8 GPUs with 32GB VRAM each + 256GB system memory = 512GB
+Old page table reservation per GPU: 1GB
+New page table reservation per GPU: 32MB
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: xinhui pan <xinhui.pan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index a0d138849b61..3d7d6b5f423e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -105,11 +105,24 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
+ (kfd_mem_limit.max_ttm_mem_limit >> 20));
+ }
+
++/* Estimate page table size needed to represent a given memory size
++ *
++ * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
++ * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
++ * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
++ * for 2MB pages for TLB efficiency. However, small allocations and
++ * fragmented system memory still need some 4KB pages. We choose a
++ * compromise that should work in most cases without reserving too
++ * much memory for page tables unnecessarily (factor 16K, >> 14).
++ */
++#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
++
+ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
+ uint64_t size, u32 domain, bool sg)
+ {
++ uint64_t reserved_for_pt =
++ ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
+ size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
+- uint64_t reserved_for_pt = amdgpu_amdkfd_total_mem_size >> 9;
+ int ret = 0;
+
+ acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4601-drm-amdgpu-apply-gpr-gds-workaround-before-enabling-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4601-drm-amdgpu-apply-gpr-gds-workaround-before-enabling-.patch
new file mode 100644
index 00000000..bb6a097d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4601-drm-amdgpu-apply-gpr-gds-workaround-before-enabling-.patch
@@ -0,0 +1,45 @@
+From 4dfd7149c57f60d4a25d860971f03613a5c15f77 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 20 Nov 2019 19:21:35 +0800
+Subject: [PATCH 4601/4736] drm/amdgpu: apply gpr/gds workaround before
+ enabling GFX EDC mode
+
+gfx memory should be initialized before enabling
+DED and FUE field in mmGB_EDC_MODE
+
+Change-Id: I248a087364cbd9858cba32a70be456af3f07c90d
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 18490f23e0d9..1aff77c89e7a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4238,10 +4238,6 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int r;
+
+- r = amdgpu_gfx_ras_late_init(adev);
+- if (r)
+- return r;
+-
+ r = gfx_v9_0_do_edc_gds_workarounds(adev);
+ if (r)
+ return r;
+@@ -4251,6 +4247,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ if (r)
+ return r;
+
++ r = amdgpu_gfx_ras_late_init(adev);
++ if (r)
++ return r;
++
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4602-drm-amdgpu-move-pci-handling-out-of-pm-ops.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4602-drm-amdgpu-move-pci-handling-out-of-pm-ops.patch
new file mode 100644
index 00000000..1784d283
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4602-drm-amdgpu-move-pci-handling-out-of-pm-ops.patch
@@ -0,0 +1,196 @@
+From baf01d88b72d9251f4ea6c51dc64dce686617e87 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 20 Nov 2019 17:31:11 -0500
+Subject: [PATCH 4602/4736] drm/amdgpu: move pci handling out of pm ops
+
+The documentation says the that PCI core handles this
+for you unless you choose to implement it. Just rely
+on the PCI core to handle the pci specific bits.
+
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +++++++++-------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 16 +++++------
+ 3 files changed, 24 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index ccb1fd7cd2b6..553d93a45e64 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1232,8 +1232,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
+ void amdgpu_driver_postclose_kms(struct drm_device *dev,
+ struct drm_file *file_priv);
+ int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
+-int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
+-int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
++int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
++int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
+ u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
+ int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+ void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 3f587dce39e2..bb04f9bb038c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1090,6 +1090,7 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
+ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
+ {
+ struct drm_device *dev = pci_get_drvdata(pdev);
++ int r;
+
+ if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF)
+ return;
+@@ -1099,7 +1100,12 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
+ /* don't suspend or resume card normally */
+ dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+
+- amdgpu_device_resume(dev, true, true);
++ pci_set_power_state(dev->pdev, PCI_D0);
++ pci_restore_state(dev->pdev);
++ r = pci_enable_device(dev->pdev);
++ if (r)
++ DRM_WARN("pci_enable_device failed (%d)\n", r);
++ amdgpu_device_resume(dev, true);
+
+ dev->switch_power_state = DRM_SWITCH_POWER_ON;
+ drm_kms_helper_poll_enable(dev);
+@@ -1107,7 +1113,11 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
+ pr_info("amdgpu: switched off\n");
+ drm_kms_helper_poll_disable(dev);
+ dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+- amdgpu_device_suspend(dev, true, true);
++ amdgpu_device_suspend(dev, true);
++ pci_save_state(dev->pdev);
++ /* Shut down the device */
++ pci_disable_device(dev->pdev);
++ pci_set_power_state(dev->pdev, PCI_D3cold);
+ dev->switch_power_state = DRM_SWITCH_POWER_OFF;
+ }
+ }
+@@ -3203,7 +3213,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ * Returns 0 for success or an error on failure.
+ * Called at driver suspend.
+ */
+-int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
++int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
+ {
+ struct amdgpu_device *adev;
+ struct drm_crtc *crtc;
+@@ -3286,13 +3296,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ */
+ amdgpu_bo_evict_vram(adev);
+
+- if (suspend) {
+- pci_save_state(dev->pdev);
+- /* Shut down the device */
+- pci_disable_device(dev->pdev);
+- pci_set_power_state(dev->pdev, PCI_D3hot);
+- }
+-
+ return 0;
+ }
+
+@@ -3307,7 +3310,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ * Returns 0 for success or an error on failure.
+ * Called at driver resume.
+ */
+-int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
++int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
+ {
+ struct drm_connector *connector;
+ struct drm_connector_list_iter iter;
+@@ -3318,14 +3321,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
+ if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+ return 0;
+
+- if (resume) {
+- pci_set_power_state(dev->pdev, PCI_D0);
+- pci_restore_state(dev->pdev);
+- r = pci_enable_device(dev->pdev);
+- if (r)
+- return r;
+- }
+-
+ /* post card */
+ if (amdgpu_device_need_post(adev)) {
+ r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 4ca9b9bde917..25c206d0fdfd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1192,7 +1192,7 @@ static int amdgpu_pmops_suspend(struct device *dev)
+ {
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+- return amdgpu_device_suspend(drm_dev, true, true);
++ return amdgpu_device_suspend(drm_dev, true);
+ }
+
+ static int amdgpu_pmops_resume(struct device *dev)
+@@ -1207,7 +1207,7 @@ static int amdgpu_pmops_resume(struct device *dev)
+ pm_runtime_enable(dev);
+ }
+
+- return amdgpu_device_resume(drm_dev, true, true);
++ return amdgpu_device_resume(drm_dev, true);
+ }
+
+ static int amdgpu_pmops_freeze(struct device *dev)
+@@ -1216,7 +1216,7 @@ static int amdgpu_pmops_freeze(struct device *dev)
+ struct amdgpu_device *adev = drm_dev->dev_private;
+ int r;
+
+- r = amdgpu_device_suspend(drm_dev, false, true);
++ r = amdgpu_device_suspend(drm_dev, true);
+ if (r)
+ return r;
+ return amdgpu_asic_reset(adev);
+@@ -1226,21 +1226,21 @@ static int amdgpu_pmops_thaw(struct device *dev)
+ {
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+- return amdgpu_device_resume(drm_dev, false, true);
++ return amdgpu_device_resume(drm_dev, true);
+ }
+
+ static int amdgpu_pmops_poweroff(struct device *dev)
+ {
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+- return amdgpu_device_suspend(drm_dev, true, true);
++ return amdgpu_device_suspend(drm_dev, true);
+ }
+
+ static int amdgpu_pmops_restore(struct device *dev)
+ {
+ struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+- return amdgpu_device_resume(drm_dev, false, true);
++ return amdgpu_device_resume(drm_dev, true);
+ }
+
+ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+@@ -1259,7 +1259,7 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+ drm_kms_helper_poll_disable(drm_dev);
+
+- ret = amdgpu_device_suspend(drm_dev, false, false);
++ ret = amdgpu_device_suspend(drm_dev, false);
+ if (amdgpu_device_supports_boco(drm_dev)) {
+ /* Only need to handle PCI state in the driver for ATPX
+ * PCI core handles it for _PR3.
+@@ -1309,7 +1309,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ } else if (amdgpu_device_supports_baco(drm_dev)) {
+ amdgpu_device_baco_exit(drm_dev);
+ }
+- ret = amdgpu_device_resume(drm_dev, false, false);
++ ret = amdgpu_device_resume(drm_dev, false);
+ drm_kms_helper_poll_enable(drm_dev);
+ if (amdgpu_device_supports_boco(drm_dev))
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4603-drm-amdgpu-flag-vram-lost-on-baco-reset-for-VI-CIK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4603-drm-amdgpu-flag-vram-lost-on-baco-reset-for-VI-CIK.patch
new file mode 100644
index 00000000..253523f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4603-drm-amdgpu-flag-vram-lost-on-baco-reset-for-VI-CIK.patch
@@ -0,0 +1,62 @@
+From 8743a9f301867b65a7a690d147237052a6e5d999 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 25 Nov 2019 11:11:18 -0500
+Subject: [PATCH 4603/4736] drm/amdgpu: flag vram lost on baco reset for VI/CIK
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+VI/CIK BACO was inflight when this fix landed for SOC15/NV.
+Add the fix to VI/CIK as well.
+
+Acked-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++++--
+ drivers/gpu/drm/amd/amdgpu/vi.c | 7 +++++--
+ 2 files changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index a5162412989b..51cbcd36f3d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1362,10 +1362,13 @@ static int cik_asic_reset(struct amdgpu_device *adev)
+ {
+ int r;
+
+- if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++ if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
++ if (!adev->in_suspend)
++ amdgpu_inc_vram_lost(adev);
+ r = smu7_asic_baco_reset(adev);
+- else
++ } else {
+ r = cik_asic_pci_config_reset(adev);
++ }
+
+ return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 14228bca071b..461f13d7366a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -802,10 +802,13 @@ static int vi_asic_reset(struct amdgpu_device *adev)
+ {
+ int r;
+
+- if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++ if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
++ if (!adev->in_suspend)
++ amdgpu_inc_vram_lost(adev);
+ r = smu7_asic_baco_reset(adev);
+- else
++ } else {
+ r = vi_asic_pci_config_reset(adev);
++ }
+
+ return r;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4604-drm-amdgpu-Fix-a-bug-in-jpeg_v1_0_start.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4604-drm-amdgpu-Fix-a-bug-in-jpeg_v1_0_start.patch
new file mode 100644
index 00000000..4629cf2c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4604-drm-amdgpu-Fix-a-bug-in-jpeg_v1_0_start.patch
@@ -0,0 +1,32 @@
+From ae732308d0383f698a48078008fd6e79089e46cc Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Tue, 26 Nov 2019 15:10:29 +0300
+Subject: [PATCH 4604/4736] drm/amdgpu: Fix a bug in jpeg_v1_0_start()
+
+Originally the last WREG32_SOC15() was a part of the if statement block
+but the curly braces are on the wrong line.
+
+Fixes: bb0db70f3f75 ("drm/amdgpu: separate JPEG1.0 code out from VCN1.0")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+index 553506df077d..a141408dfb23 100644
+--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+@@ -522,7 +522,8 @@ void jpeg_v1_0_start(struct amdgpu_device *adev, int mode)
+ WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
+ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
+- } WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++ WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++ }
+
+ /* initialize wptr */
+ ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4605-drm-amd-display-Modify-comments-to-match-the-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4605-drm-amd-display-Modify-comments-to-match-the-code.patch
new file mode 100644
index 00000000..b4ff537e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4605-drm-amd-display-Modify-comments-to-match-the-code.patch
@@ -0,0 +1,42 @@
+From 8b35343eac17af3e2aabd323fbf6d3dba5d8fe6b Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Mon, 25 Nov 2019 17:25:18 -0500
+Subject: [PATCH 4605/4736] drm/amd/display: Modify comments to match the code
+
+[Why]
+This line of code was modified. However, comments
+remained unchanged. As a result, comments and code are
+mismatching.
+
+[How]
+Modifying comments to reflect code. At the same time,
+explaining why the value was changed from 200ms to
+3000ms.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index 24e4684034f5..acdedd889716 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -482,7 +482,12 @@ void generic_reg_wait(const struct dc_context *ctx,
+ return;
+ }
+
+- /* something is terribly wrong if time out is > 200ms. (5Hz) */
++ /*
++ * Something is terribly wrong if time out is > 3000ms.
++ * 3000ms is the maximum time needed for SMU to pass values back.
++ * This value comes from experiments.
++ *
++ */
+ ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
+
+ for (i = 0; i <= time_out_num_tries; i++) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4606-drm-amdkfd-Eliminate-unnecessary-kernel-queue-functi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4606-drm-amdkfd-Eliminate-unnecessary-kernel-queue-functi.patch
new file mode 100644
index 00000000..721de83b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4606-drm-amdkfd-Eliminate-unnecessary-kernel-queue-functi.patch
@@ -0,0 +1,417 @@
+From 858f55ddeac45eaca40516c74fd835777960e429 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 00:30:49 -0500
+Subject: [PATCH 4606/4736] drm/amdkfd: Eliminate unnecessary kernel queue
+ function pointers v2
+
+Up to this point, those functions are all the same for all ASICs, so
+no need to call them by functions pointers. Removing the function
+pointers will greatly increase the code readablity. If there is ever
+need for those function pointers, we can add it back then.
+
+v2: Adapt for amd-kfd-staging branch, which has acquire_inline_ib()
+exclusively.
+
+Change-Id: I9515fdece70110067cda66e2d24d6768b4846c2f
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 14 +++---
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 35 +++++++--------
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 44 ++++++-------------
+ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 34 +++++++-------
+ 4 files changed, 54 insertions(+), 73 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+index 142ac7954032..3e5904f8876a 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+@@ -74,11 +74,11 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+ * The receive packet buff will be sitting on the Indirect Buffer
+ * and in the PQ we put the IB packet + sync packet(s).
+ */
+- status = kq->ops.acquire_packet_buffer(kq,
++ status = kq_acquire_packet_buffer(kq,
+ pq_packets_size_in_bytes / sizeof(uint32_t),
+ &ib_packet_buff);
+ if (status) {
+- pr_err("acquire_packet_buffer failed\n");
++ pr_err("kq_acquire_packet_buffer failed\n");
+ return status;
+ }
+
+@@ -101,7 +101,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+ ib_packet->bitfields5.pasid = pasid;
+
+ if (!sync) {
+- kq->ops.submit_packet(kq);
++ kq_submit_packet(kq);
+ return status;
+ }
+
+@@ -122,7 +122,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+
+ if (status) {
+ pr_err("Failed to allocate GART memory\n");
+- kq->ops.rollback_packet(kq);
++ kq_rollback_packet(kq);
+ return status;
+ }
+
+@@ -158,7 +158,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+
+ rm_packet->data_lo = QUEUESTATE__ACTIVE;
+
+- kq->ops.submit_packet(kq);
++ kq_submit_packet(kq);
+
+ /* Wait till CP writes sync code: */
+ status = amdkfd_fence_wait_timeout(
+@@ -372,7 +372,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
+ return -EINVAL;
+ }
+
+- status = dbgdev->kq->ops.acquire_inline_ib(dbgdev->kq,
++ status = kq_acquire_inline_ib(dbgdev->kq,
+ ib_size/sizeof(uint32_t),
+ &packet_buff_uint, &packet_buff_gpu_addr);
+ if (status) {
+@@ -652,7 +652,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
+
+ pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
+
+- status = dbgdev->kq->ops.acquire_inline_ib(dbgdev->kq,
++ status = kq_acquire_inline_ib(dbgdev->kq,
+ ib_size / sizeof(uint32_t),
+ &packet_buff_uint, &packet_buff_gpu_addr);
+ if (status) {
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index ca7e8d299c8b..236023ce1125 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -34,7 +34,10 @@
+
+ #define PM4_COUNT_ZERO (((1 << 15) - 1) << 16)
+
+-static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
++/* Initialize a kernel queue, including allocations of GART memory
++ * needed for the queue.
++ */
++static bool kq_initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ enum kfd_queue_type type, unsigned int queue_size)
+ {
+ struct queue_properties prop;
+@@ -88,7 +91,7 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ kq->pq_gpu_addr = kq->pq->gpu_addr;
+
+ /* For CIK family asics, kq->eop_mem is not needed */
+- if (dev->device_info->asic_family > CHIP_HAWAII) {
++ if (dev->device_info->asic_family > CHIP_MULLINS) {
+ retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+ if (retval != 0)
+ goto err_eop_allocate_vidmem;
+@@ -192,7 +195,8 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+
+ }
+
+-static void uninitialize(struct kernel_queue *kq)
++/* Uninitialize a kernel queue and free all its memory usages. */
++static void kq_uninitialize(struct kernel_queue *kq)
+ {
+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
+@@ -221,7 +225,7 @@ static void uninitialize(struct kernel_queue *kq)
+ uninit_queue(kq->queue);
+ }
+
+-static int acquire_packet_buffer(struct kernel_queue *kq,
++int kq_acquire_packet_buffer(struct kernel_queue *kq,
+ size_t packet_size_in_dwords, unsigned int **buffer_ptr)
+ {
+ size_t available_size;
+@@ -282,7 +286,7 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
+ return -ENOMEM;
+ }
+
+-static int acquire_inline_ib(struct kernel_queue *kq,
++int kq_acquire_inline_ib(struct kernel_queue *kq,
+ size_t size_in_dwords,
+ unsigned int **buffer_ptr,
+ uint64_t *gpu_addr)
+@@ -297,7 +301,7 @@ static int acquire_inline_ib(struct kernel_queue *kq,
+ /* Allocate size_in_dwords on the ring, plus an extra dword
+ * for a NOP packet header
+ */
+- ret = acquire_packet_buffer(kq, size_in_dwords + 1, &buf);
++ ret = kq_acquire_packet_buffer(kq, size_in_dwords + 1, &buf);
+ if (ret)
+ return ret;
+
+@@ -315,7 +319,7 @@ static int acquire_inline_ib(struct kernel_queue *kq,
+ return 0;
+ }
+
+-static void submit_packet(struct kernel_queue *kq)
++void kq_submit_packet(struct kernel_queue *kq)
+ {
+ #ifdef DEBUG
+ int i;
+@@ -338,7 +342,7 @@ static void submit_packet(struct kernel_queue *kq)
+ }
+ }
+
+-static void rollback_packet(struct kernel_queue *kq)
++void kq_rollback_packet(struct kernel_queue *kq)
+ {
+ if (kq->dev->device_info->doorbell_size == 8) {
+ kq->pending_wptr64 = *kq->wptr64_kernel;
+@@ -358,14 +362,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ if (!kq)
+ return NULL;
+
+- kq->ops.initialize = initialize;
+- kq->ops.uninitialize = uninitialize;
+- kq->ops.acquire_packet_buffer = acquire_packet_buffer;
+- kq->ops.acquire_inline_ib = acquire_inline_ib;
+- kq->ops.submit_packet = submit_packet;
+- kq->ops.rollback_packet = rollback_packet;
+-
+- if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
++ if (kq_initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
+ return kq;
+
+ pr_err("Failed to init kernel queue\n");
+@@ -376,7 +373,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+
+ void kernel_queue_uninit(struct kernel_queue *kq)
+ {
+- kq->ops.uninitialize(kq);
++ kq_uninitialize(kq);
+ kfree(kq);
+ }
+
+@@ -396,7 +393,7 @@ static __attribute__((unused)) void test_kq(struct kfd_dev *dev)
+ return;
+ }
+
+- retval = kq->ops.acquire_packet_buffer(kq, 5, &buffer);
++ retval = kq_acquire_packet_buffer(kq, 5, &buffer);
+ if (unlikely(retval != 0)) {
+ pr_err(" Failed to acquire packet buffer\n");
+ pr_err("Kernel queue test failed\n");
+@@ -404,7 +401,7 @@ static __attribute__((unused)) void test_kq(struct kfd_dev *dev)
+ }
+ for (i = 0; i < 5; i++)
+ buffer[i] = kq->nop_packet;
+- kq->ops.submit_packet(kq);
++ kq_submit_packet(kq);
+
+ pr_err("Ending kernel queue test\n");
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index 852de7466cc4..3e39dcb542df 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -29,54 +29,38 @@
+ #include "kfd_priv.h"
+
+ /**
+- * struct kernel_queue_ops
+- *
+- * @initialize: Initialize a kernel queue, including allocations of GART memory
+- * needed for the queue.
+- *
+- * @uninitialize: Uninitialize a kernel queue and free all its memory usages.
+- *
+- * @acquire_packet_buffer: Returns a pointer to the location in the kernel
++ * kq_acquire_packet_buffer: Returns a pointer to the location in the kernel
+ * queue ring buffer where the calling function can write its packet. It is
+ * Guaranteed that there is enough space for that packet. It also updates the
+ * pending write pointer to that location so subsequent calls to
+ * acquire_packet_buffer will get a correct write pointer
+ *
+- * @acquire_inline_ib: Returns a pointer to the location in the kernel
++ * kq_acquire_inline_ib: Returns a pointer to the location in the kernel
+ * queue ring buffer where the calling function can write an inline IB. It is
+ * Guaranteed that there is enough space for that IB. It also updates the
+ * pending write pointer to that location so subsequent calls to
+ * acquire_packet_buffer will get a correct write pointer
+ *
+- * @submit_packet: Update the write pointer and doorbell of a kernel queue.
+- *
+- * @sync_with_hw: Wait until the write pointer and the read pointer of a kernel
+- * queue are equal, which means the CP has read all the submitted packets.
++ * kq_submit_packet: Update the write pointer and doorbell of a kernel queue.
+ *
+- * @rollback_packet: This routine is called if we failed to build an acquired
++ * kq_rollback_packet: This routine is called if we failed to build an acquired
+ * packet for some reason. It just overwrites the pending wptr with the current
+ * one
+ *
+ */
+-struct kernel_queue_ops {
+- bool (*initialize)(struct kernel_queue *kq, struct kfd_dev *dev,
+- enum kfd_queue_type type, unsigned int queue_size);
+- void (*uninitialize)(struct kernel_queue *kq);
+- int (*acquire_packet_buffer)(struct kernel_queue *kq,
+- size_t packet_size_in_dwords,
+- unsigned int **buffer_ptr);
+- int (*acquire_inline_ib)(struct kernel_queue *kq,
+- size_t packet_size_in_dwords,
+- unsigned int **buffer_ptr,
+- uint64_t *gpu_addr);
+
+- void (*submit_packet)(struct kernel_queue *kq);
+- void (*rollback_packet)(struct kernel_queue *kq);
+-};
++int kq_acquire_packet_buffer(struct kernel_queue *kq,
++ size_t packet_size_in_dwords,
++ unsigned int **buffer_ptr);
++int kq_acquire_inline_ib(struct kernel_queue *kq,
++ size_t size_in_dwords,
++ unsigned int **buffer_ptr,
++ uint64_t *gpu_addr);
++void kq_submit_packet(struct kernel_queue *kq);
++void kq_rollback_packet(struct kernel_queue *kq);
+
+-struct kernel_queue {
+- struct kernel_queue_ops ops;
+
++struct kernel_queue {
+ /* data */
+ struct kfd_dev *dev;
+ struct mqd_manager *mqd_mgr;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index cbf83ed96dad..6ef4dc60852d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -280,7 +280,7 @@ int pm_send_set_resources(struct packet_manager *pm,
+
+ size = pm->pmf->set_resources_size;
+ mutex_lock(&pm->lock);
+- pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++ kq_acquire_packet_buffer(pm->priv_queue,
+ size / sizeof(uint32_t),
+ (unsigned int **)&buffer);
+ if (!buffer) {
+@@ -291,9 +291,9 @@ int pm_send_set_resources(struct packet_manager *pm,
+
+ retval = pm->pmf->set_resources(pm, buffer, res);
+ if (!retval)
+- pm->priv_queue->ops.submit_packet(pm->priv_queue);
++ kq_submit_packet(pm->priv_queue);
+ else
+- pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++ kq_rollback_packet(pm->priv_queue);
+
+ out:
+ mutex_unlock(&pm->lock);
+@@ -318,7 +318,7 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues)
+ packet_size_dwords = pm->pmf->runlist_size / sizeof(uint32_t);
+ mutex_lock(&pm->lock);
+
+- retval = pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++ retval = kq_acquire_packet_buffer(pm->priv_queue,
+ packet_size_dwords, &rl_buffer);
+ if (retval)
+ goto fail_acquire_packet_buffer;
+@@ -328,14 +328,14 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues)
+ if (retval)
+ goto fail_create_runlist;
+
+- pm->priv_queue->ops.submit_packet(pm->priv_queue);
++ kq_submit_packet(pm->priv_queue);
+
+ mutex_unlock(&pm->lock);
+
+ return retval;
+
+ fail_create_runlist:
+- pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++ kq_rollback_packet(pm->priv_queue);
+ fail_acquire_packet_buffer:
+ mutex_unlock(&pm->lock);
+ fail_create_runlist_ib:
+@@ -354,7 +354,7 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
+
+ size = pm->pmf->query_status_size;
+ mutex_lock(&pm->lock);
+- pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++ kq_acquire_packet_buffer(pm->priv_queue,
+ size / sizeof(uint32_t), (unsigned int **)&buffer);
+ if (!buffer) {
+ pr_err("Failed to allocate buffer on kernel queue\n");
+@@ -364,9 +364,9 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
+
+ retval = pm->pmf->query_status(pm, buffer, fence_address, fence_value);
+ if (!retval)
+- pm->priv_queue->ops.submit_packet(pm->priv_queue);
++ kq_submit_packet(pm->priv_queue);
+ else
+- pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++ kq_rollback_packet(pm->priv_queue);
+
+ out:
+ mutex_unlock(&pm->lock);
+@@ -383,7 +383,7 @@ int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period)
+ mutex_lock(&pm->lock);
+
+ if (size) {
+- pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++ kq_acquire_packet_buffer(pm->priv_queue,
+ size / sizeof(uint32_t),
+ (unsigned int **)&buffer);
+
+@@ -395,9 +395,9 @@ int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period)
+
+ retval = pm->pmf->set_grace_period(pm, buffer, grace_period);
+ if (!retval)
+- pm->priv_queue->ops.submit_packet(pm->priv_queue);
++ kq_submit_packet(pm->priv_queue);
+ else
+- pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++ kq_rollback_packet(pm->priv_queue);
+ }
+
+ out:
+@@ -415,7 +415,7 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
+
+ size = pm->pmf->unmap_queues_size;
+ mutex_lock(&pm->lock);
+- pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++ kq_acquire_packet_buffer(pm->priv_queue,
+ size / sizeof(uint32_t), (unsigned int **)&buffer);
+ if (!buffer) {
+ pr_err("Failed to allocate buffer on kernel queue\n");
+@@ -426,9 +426,9 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
+ retval = pm->pmf->unmap_queues(pm, buffer, type, filter, filter_param,
+ reset, sdma_engine);
+ if (!retval)
+- pm->priv_queue->ops.submit_packet(pm->priv_queue);
++ kq_submit_packet(pm->priv_queue);
+ else
+- pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++ kq_rollback_packet(pm->priv_queue);
+
+ out:
+ mutex_unlock(&pm->lock);
+@@ -473,7 +473,7 @@ int pm_debugfs_hang_hws(struct packet_manager *pm)
+
+ size = pm->pmf->query_status_size;
+ mutex_lock(&pm->lock);
+- pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++ kq_acquire_packet_buffer(pm->priv_queue,
+ size / sizeof(uint32_t), (unsigned int **)&buffer);
+ if (!buffer) {
+ pr_err("Failed to allocate buffer on kernel queue\n");
+@@ -481,7 +481,7 @@ int pm_debugfs_hang_hws(struct packet_manager *pm)
+ goto out;
+ }
+ memset(buffer, 0x55, size);
+- pm->priv_queue->ops.submit_packet(pm->priv_queue);
++ kq_submit_packet(pm->priv_queue);
+
+ pr_info("Submitting %x %x %x %x %x %x %x to HIQ to hang the HWS.",
+ buffer[0], buffer[1], buffer[2], buffer[3],
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4607-drm-amdgpu-gfx10-unlock-srbm_mutex-after-queue-progr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4607-drm-amdgpu-gfx10-unlock-srbm_mutex-after-queue-progr.patch
new file mode 100644
index 00000000..2c2b7f33
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4607-drm-amdgpu-gfx10-unlock-srbm_mutex-after-queue-progr.patch
@@ -0,0 +1,51 @@
+From 8ba808c2f1cf3757741eec7d2288d15ae6f2e431 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 6 Nov 2019 21:10:20 +0800
+Subject: [PATCH 4607/4736] drm/amdgpu/gfx10: unlock srbm_mutex after queue
+ programming finish
+
+srbm_mutex is to guarantee atomicity for r/w of gfx indexed registers
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index bfc2b8f8c1d4..96a9acb0dd6a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -2829,7 +2829,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
+ /* Init gfx ring 0 for pipe 0 */
+ mutex_lock(&adev->srbm_mutex);
+ gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
+- mutex_unlock(&adev->srbm_mutex);
++
+ /* Set ring buffer size */
+ ring = &adev->gfx.gfx_ring[0];
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+@@ -2867,11 +2867,11 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
+ WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
+
+ gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
++ mutex_unlock(&adev->srbm_mutex);
+
+ /* Init gfx ring 1 for pipe 1 */
+ mutex_lock(&adev->srbm_mutex);
+ gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
+- mutex_unlock(&adev->srbm_mutex);
+ ring = &adev->gfx.gfx_ring[1];
+ rb_bufsz = order_base_2(ring->ring_size / 8);
+ tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
+@@ -2901,6 +2901,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
+ WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
+
+ gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
++ mutex_unlock(&adev->srbm_mutex);
+
+ /* Switch to pipe 0 */
+ mutex_lock(&adev->srbm_mutex);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4608-drm-amdgpu-gfx10-remove-outdated-comments.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4608-drm-amdgpu-gfx10-remove-outdated-comments.patch
new file mode 100644
index 00000000..b88a4a17
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4608-drm-amdgpu-gfx10-remove-outdated-comments.patch
@@ -0,0 +1,28 @@
+From 086b1d934b2a7b24b118bcfe63a2d35ae00daa04 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 6 Nov 2019 21:08:06 +0800
+Subject: [PATCH 4608/4736] drm/amdgpu/gfx10: remove outdated comments
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 96a9acb0dd6a..cd4982d70889 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -46,9 +46,6 @@
+ * Navi10 has two graphic rings to share each graphic pipe.
+ * 1. Primary ring
+ * 2. Async ring
+- *
+- * In bring-up phase, it just used primary ring so set gfx ring number as 1 at
+- * first.
+ */
+ #define GFX10_NUM_GFX_RINGS 2
+ #define GFX10_MEC_HPD_SIZE 2048
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4609-drm-amdgpu-gfx-Clear-more-EDC-cnt.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4609-drm-amdgpu-gfx-Clear-more-EDC-cnt.patch
new file mode 100644
index 00000000..d2b627bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4609-drm-amdgpu-gfx-Clear-more-EDC-cnt.patch
@@ -0,0 +1,39 @@
+From 7662a48fa43894acc6dd80ede850985de652d213 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 26 Nov 2019 14:23:10 -0500
+Subject: [PATCH 4609/4736] drm/amdgpu/gfx: Clear more EDC cnt
+
+Clear SDMA and HDP EDC counter in GPR workarounds.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1aff77c89e7a..d008105a5757 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -44,6 +44,8 @@
+
+ #include "amdgpu_ras.h"
+
++#include "sdma0/sdma0_4_0_offset.h"
++#include "sdma1/sdma1_4_0_offset.h"
+ #define GFX9_NUM_GFX_RINGS 1
+ #define GFX9_MEC_HPD_SIZE 4096
+ #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
+@@ -4032,6 +4034,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
+ { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
+ { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
+ { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
++ { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
++ { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
++ { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
+ };
+
+ static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4610-drm-amdgpu-gfx-Increase-dispatch-packet-number.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4610-drm-amdgpu-gfx-Increase-dispatch-packet-number.patch
new file mode 100644
index 00000000..66b1f54b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4610-drm-amdgpu-gfx-Increase-dispatch-packet-number.patch
@@ -0,0 +1,38 @@
+From be1ff76f766e0a5362640cd62e5012def7a8d031 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 26 Nov 2019 14:27:46 -0500
+Subject: [PATCH 4610/4736] drm/amdgpu/gfx: Increase dispatch packet number
+
+For Arcturus, increase dispatch packet number to stress scheduler.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index d008105a5757..8f9861361a9d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4149,7 +4149,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+
+ /* write dispatch packet */
+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+- ib.ptr[ib.length_dw++] = 128; /* x */
++ ib.ptr[ib.length_dw++] = 256; /* x */
+ ib.ptr[ib.length_dw++] = 1; /* y */
+ ib.ptr[ib.length_dw++] = 1; /* z */
+ ib.ptr[ib.length_dw++] =
+@@ -4177,7 +4177,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+
+ /* write dispatch packet */
+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+- ib.ptr[ib.length_dw++] = 128; /* x */
++ ib.ptr[ib.length_dw++] = 256; /* x */
+ ib.ptr[ib.length_dw++] = 1; /* y */
+ ib.ptr[ib.length_dw++] = 1; /* z */
+ ib.ptr[ib.length_dw++] =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4611-drm-amd-display-Include-num_vmid-and-num_dsc-within-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4611-drm-amd-display-Include-num_vmid-and-num_dsc-within-.patch
new file mode 100644
index 00000000..5cceb87b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4611-drm-amd-display-Include-num_vmid-and-num_dsc-within-.patch
@@ -0,0 +1,36 @@
+From fdf561f7ee9326da840da019007eec6f281b280a Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Thu, 28 Nov 2019 14:12:11 -0500
+Subject: [PATCH 4611/4736] drm/amd/display: Include num_vmid and num_dsc
+ within NV14's resource caps
+
+[Why]
+"num_vmid" and "num_dsc" are missing within NV14's resource caps structure.
+
+[How]
+Add the missing parts.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 9f721d5bea3b..f30e9aef53ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -816,6 +816,10 @@ static const struct resource_caps res_cap_nv14 = {
+ .num_pll = 5,
+ .num_dwb = 1,
+ .num_ddc = 5,
++ .num_vmid = 16,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++ .num_dsc = 5,
++#endif
+ };
+
+ static const struct dc_debug_options debug_defaults_drv = {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4612-drm-amd-display-Drop-AMD_EDID_UTILITY-defines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4612-drm-amd-display-Drop-AMD_EDID_UTILITY-defines.patch
new file mode 100644
index 00000000..fb4dfd71
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4612-drm-amd-display-Drop-AMD_EDID_UTILITY-defines.patch
@@ -0,0 +1,96 @@
+From 12d45f8bdc7c9d1d078f104da0a20788a8e3bdfc Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Thu, 28 Nov 2019 11:30:10 -0500
+Subject: [PATCH 4612/4736] drm/amd/display: Drop AMD_EDID_UTILITY defines
+
+We don't use this upstream in the Linux kernel.
+
+Change-Id: I3dd29b4bd46b3493e6a0c218df048712ea665c9a
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2 --
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 8 --------
+ drivers/gpu/drm/amd/display/dc/dc_types.h | 4 ----
+ 3 files changed, 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index a782ae18a1c5..cc9915e545cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -41,10 +41,8 @@ struct dc_dsc_bw_range {
+
+ struct display_stream_compressor {
+ const struct dsc_funcs *funcs;
+-#ifndef AMD_EDID_UTILITY
+ struct dc_context *ctx;
+ int inst;
+-#endif
+ };
+
+ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index 86043d431d40..25c50bcab9e9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -26,8 +26,6 @@
+ #ifndef DC_HW_TYPES_H
+ #define DC_HW_TYPES_H
+
+-#ifndef AMD_EDID_UTILITY
+-
+ #include "os_types.h"
+ #include "fixed31_32.h"
+ #include "signal_types.h"
+@@ -584,8 +582,6 @@ struct scaling_taps {
+ bool integer_scaling;
+ };
+
+-#endif /* AMD_EDID_UTILITY */
+-
+ enum dc_timing_standard {
+ DC_TIMING_STANDARD_UNDEFINED,
+ DC_TIMING_STANDARD_DMT,
+@@ -742,8 +738,6 @@ struct dc_crtc_timing {
+ struct dc_dsc_config dsc_cfg;
+ };
+
+-#ifndef AMD_EDID_UTILITY
+-
+ enum trigger_delay {
+ TRIGGER_DELAY_NEXT_PIXEL = 0,
+ TRIGGER_DELAY_NEXT_LINE,
+@@ -837,7 +831,5 @@ struct tg_color {
+ uint16_t color_b_cb;
+ };
+
+-#endif /* AMD_EDID_UTILITY */
+-
+ #endif /* DC_HW_TYPES_H */
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 1363e8907fbf..2b92bfa28bde 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -25,7 +25,6 @@
+ #ifndef DC_TYPES_H_
+ #define DC_TYPES_H_
+
+-#ifndef AMD_EDID_UTILITY
+ /* AND EdidUtility only needs a portion
+ * of this file, including the rest only
+ * causes additional issues.
+@@ -781,9 +780,6 @@ struct dc_clock_config {
+ uint32_t current_clock_khz;/*current clock in use*/
+ };
+
+-#endif /*AMD_EDID_UTILITY*/
+-//AMD EDID UTILITY does not need any of the above structures
+-
+ /* DSC DPCD capabilities */
+ union dsc_slice_caps1 {
+ struct {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4613-drm-amdgpu-fix-calltrace-during-kmd-unload-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4613-drm-amdgpu-fix-calltrace-during-kmd-unload-v3.patch
new file mode 100644
index 00000000..b47602b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4613-drm-amdgpu-fix-calltrace-during-kmd-unload-v3.patch
@@ -0,0 +1,324 @@
+From 52f19708950e75cdb45af6c578c2b811eeb4084b Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:42:25 +0800
+Subject: [PATCH 4613/4736] drm/amdgpu: fix calltrace during kmd unload(v3)
+
+issue:
+kernel would report a warning from a double unpin
+during the driver unloading on the CSB bo
+
+why:
+we unpin it during hw_fini, and there will be another
+unpin in sw_fini on CSB bo.
+
+fix:
+actually we don't need to pin/unpin it during
+hw_init/fini since it is created with kernel pinned,
+we only need to fullfill the CSB again during hw_init
+to prevent CSB/VRAM lost after S3
+
+v2:
+get_csb in init_rlc so hw_init() will make CSIB content
+back even after reset or s3
+
+v3:
+use bo_create_kernel instead of bo_create_reserved for CSB
+otherwise the bo_free_kernel() on CSB is not aligned and
+would lead to its internal reserve pending there forever
+
+take care of gfx7/8 as well
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 10 +----
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 58 +------------------------
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +----------------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +----------------
+ 5 files changed, 6 insertions(+), 144 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+index c8793e6cc3c5..6373bfb47d55 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+@@ -124,13 +124,12 @@ int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws)
+ */
+ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
+ {
+- volatile u32 *dst_ptr;
+ u32 dws;
+ int r;
+
+ /* allocate clear state block */
+ adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
+- r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
++ r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &adev->gfx.rlc.clear_state_obj,
+ &adev->gfx.rlc.clear_state_gpu_addr,
+@@ -141,13 +140,6 @@ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
+ return r;
+ }
+
+- /* set up the cs buffer */
+- dst_ptr = adev->gfx.rlc.cs_ptr;
+- adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
+- amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+- amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+ return 0;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index cd4982d70889..914d4b2f8401 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -987,39 +987,6 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
+-{
+- int r;
+-
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+- if (unlikely(r != 0))
+- return r;
+-
+- r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+- AMDGPU_GEM_DOMAIN_VRAM);
+- if (!r)
+- adev->gfx.rlc.clear_state_gpu_addr =
+- amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+-
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+- return r;
+-}
+-
+-static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
+-{
+- int r;
+-
+- if (!adev->gfx.rlc.clear_state_obj)
+- return;
+-
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+- if (likely(r == 0)) {
+- amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+- }
+-}
+-
+ static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
+ {
+ amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
+@@ -1788,25 +1755,7 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+
+ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
+- int r;
+-
+- if (adev->in_gpu_reset) {
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+- if (r)
+- return r;
+-
+- r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
+- (void **)&adev->gfx.rlc.cs_ptr);
+- if (!r) {
+- adev->gfx.rlc.funcs->get_csb_buffer(adev,
+- adev->gfx.rlc.cs_ptr);
+- amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+- }
+-
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+- if (r)
+- return r;
+- }
++ adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+
+ /* csib */
+ WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+@@ -3777,10 +3726,6 @@ static int gfx_v10_0_hw_init(void *handle)
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+- r = gfx_v10_0_csb_vram_pin(adev);
+- if (r)
+- return r;
+-
+ if (!amdgpu_emu_mode)
+ gfx_v10_0_init_golden_registers(adev);
+
+@@ -3868,7 +3813,6 @@ static int gfx_v10_0_hw_fini(void *handle)
+ }
+ gfx_v10_0_cp_enable(adev, false);
+ gfx_v10_0_enable_gui_idle_interrupt(adev, false);
+- gfx_v10_0_csb_vram_unpin(adev);
+
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index b8c2e9d9c711..0dabd0d0889c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -4543,6 +4543,8 @@ static int gfx_v7_0_hw_init(void *handle)
+
+ gfx_v7_0_constants_init(adev);
+
++ /* init CSB */
++ adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+ /* init rlc */
+ r = adev->gfx.rlc.funcs->resume(adev);
+ if (r)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 1f4f7c05e269..387e95319594 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -1317,39 +1317,6 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
+-{
+- int r;
+-
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+- if (unlikely(r != 0))
+- return r;
+-
+- r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+- AMDGPU_GEM_DOMAIN_VRAM);
+- if (!r)
+- adev->gfx.rlc.clear_state_gpu_addr =
+- amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+-
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+- return r;
+-}
+-
+-static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
+-{
+- int r;
+-
+- if (!adev->gfx.rlc.clear_state_obj)
+- return;
+-
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+- if (likely(r == 0)) {
+- amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+- }
+-}
+-
+ static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
+ {
+ amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
+@@ -3903,6 +3870,7 @@ static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+
+ static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
+ {
++ adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+ /* csib */
+ WREG32(mmRLC_CSIB_ADDR_HI,
+ adev->gfx.rlc.clear_state_gpu_addr >> 32);
+@@ -4822,10 +4790,6 @@ static int gfx_v8_0_hw_init(void *handle)
+ gfx_v8_0_init_golden_registers(adev);
+ gfx_v8_0_constants_init(adev);
+
+- r = gfx_v8_0_csb_vram_pin(adev);
+- if (r)
+- return r;
+-
+ r = adev->gfx.rlc.funcs->resume(adev);
+ if (r)
+ return r;
+@@ -4943,8 +4907,6 @@ static int gfx_v8_0_hw_fini(void *handle)
+ pr_err("rlc is busy, skip halt rlc\n");
+ amdgpu_gfx_rlc_exit_safe_mode(adev);
+
+- gfx_v8_0_csb_vram_unpin(adev);
+-
+ return 0;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 8f9861361a9d..e644d5ea56b9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1681,39 +1681,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
+-{
+- int r;
+-
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+- if (unlikely(r != 0))
+- return r;
+-
+- r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+- AMDGPU_GEM_DOMAIN_VRAM);
+- if (!r)
+- adev->gfx.rlc.clear_state_gpu_addr =
+- amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+-
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+- return r;
+-}
+-
+-static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
+-{
+- int r;
+-
+- if (!adev->gfx.rlc.clear_state_obj)
+- return;
+-
+- r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+- if (likely(r == 0)) {
+- amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+- }
+-}
+-
+ static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
+ {
+ amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
+@@ -2408,6 +2375,7 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+
+ static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
+ {
++ adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+ /* csib */
+ WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
+ adev->gfx.rlc.clear_state_gpu_addr >> 32);
+@@ -3699,10 +3667,6 @@ static int gfx_v9_0_hw_init(void *handle)
+
+ gfx_v9_0_constants_init(adev);
+
+- r = gfx_v9_0_csb_vram_pin(adev);
+- if (r)
+- return r;
+-
+ r = adev->gfx.rlc.funcs->resume(adev);
+ if (r)
+ return r;
+@@ -3784,8 +3748,6 @@ static int gfx_v9_0_hw_fini(void *handle)
+ gfx_v9_0_cp_enable(adev, false);
+ adev->gfx.rlc.funcs->stop(adev);
+
+- gfx_v9_0_csb_vram_unpin(adev);
+-
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4614-drm-amdgpu-skip-rlc-ucode-loading-for-SRIOV-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4614-drm-amdgpu-skip-rlc-ucode-loading-for-SRIOV-gfx10.patch
new file mode 100644
index 00000000..10a5a6dc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4614-drm-amdgpu-skip-rlc-ucode-loading-for-SRIOV-gfx10.patch
@@ -0,0 +1,119 @@
+From bc96184e89b8dc328d8c0e1c533d2315f6bb48bc Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:36:29 +0800
+Subject: [PATCH 4614/4736] drm/amdgpu: skip rlc ucode loading for SRIOV gfx10
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 80 +++++++++++++-------------
+ 1 file changed, 41 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 914d4b2f8401..5bd31e49601c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -684,59 +684,61 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+ adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+
+- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
+- err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
+- if (err)
+- goto out;
+- err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+- rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
+- version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
+- version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
+- if (version_major == 2 && version_minor == 1)
+- adev->gfx.rlc.is_rlc_v2_1 = true;
+-
+- adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+- adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
+- adev->gfx.rlc.save_and_restore_offset =
++ if (!amdgpu_sriov_vf(adev)) {
++ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
++ err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
++ if (err)
++ goto out;
++ err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
++ rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
++ version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
++ version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
++ if (version_major == 2 && version_minor == 1)
++ adev->gfx.rlc.is_rlc_v2_1 = true;
++
++ adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
++ adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
++ adev->gfx.rlc.save_and_restore_offset =
+ le32_to_cpu(rlc_hdr->save_and_restore_offset);
+- adev->gfx.rlc.clear_state_descriptor_offset =
++ adev->gfx.rlc.clear_state_descriptor_offset =
+ le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
+- adev->gfx.rlc.avail_scratch_ram_locations =
++ adev->gfx.rlc.avail_scratch_ram_locations =
+ le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
+- adev->gfx.rlc.reg_restore_list_size =
++ adev->gfx.rlc.reg_restore_list_size =
+ le32_to_cpu(rlc_hdr->reg_restore_list_size);
+- adev->gfx.rlc.reg_list_format_start =
++ adev->gfx.rlc.reg_list_format_start =
+ le32_to_cpu(rlc_hdr->reg_list_format_start);
+- adev->gfx.rlc.reg_list_format_separate_start =
++ adev->gfx.rlc.reg_list_format_separate_start =
+ le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
+- adev->gfx.rlc.starting_offsets_start =
++ adev->gfx.rlc.starting_offsets_start =
+ le32_to_cpu(rlc_hdr->starting_offsets_start);
+- adev->gfx.rlc.reg_list_format_size_bytes =
++ adev->gfx.rlc.reg_list_format_size_bytes =
+ le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
+- adev->gfx.rlc.reg_list_size_bytes =
++ adev->gfx.rlc.reg_list_size_bytes =
+ le32_to_cpu(rlc_hdr->reg_list_size_bytes);
+- adev->gfx.rlc.register_list_format =
++ adev->gfx.rlc.register_list_format =
+ kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
+- adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
+- if (!adev->gfx.rlc.register_list_format) {
+- err = -ENOMEM;
+- goto out;
+- }
++ adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
++ if (!adev->gfx.rlc.register_list_format) {
++ err = -ENOMEM;
++ goto out;
++ }
+
+- tmp = (unsigned int *)((uintptr_t)rlc_hdr +
+- le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
+- for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
+- adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
++ tmp = (unsigned int *)((uintptr_t)rlc_hdr +
++ le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
++ for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
++ adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
+
+- adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
++ adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
+
+- tmp = (unsigned int *)((uintptr_t)rlc_hdr +
+- le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
+- for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
+- adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
++ tmp = (unsigned int *)((uintptr_t)rlc_hdr +
++ le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
++ for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
++ adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
+
+- if (adev->gfx.rlc.is_rlc_v2_1)
+- gfx_v10_0_init_rlc_ext_microcode(adev);
++ if (adev->gfx.rlc.is_rlc_v2_1)
++ gfx_v10_0_init_rlc_ext_microcode(adev);
++ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
+ err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4615-drm-amdgpu-do-autoload-right-after-MEC-loaded-for-SR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4615-drm-amdgpu-do-autoload-right-after-MEC-loaded-for-SR.patch
new file mode 100644
index 00000000..eb2e31a3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4615-drm-amdgpu-do-autoload-right-after-MEC-loaded-for-SR.patch
@@ -0,0 +1,32 @@
+From b9099db37615143bba76082cb00bf2d3c43d80a7 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:38:22 +0800
+Subject: [PATCH 4615/4736] drm/amdgpu: do autoload right after MEC loaded for
+ SRIOV VF
+
+since we don't have RLCG ucode loading and no SRlist as well
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index c74c5f183a10..f219e2f77b4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1492,8 +1492,8 @@ static int psp_np_fw_load(struct psp_context *psp)
+ return ret;
+
+ /* Start rlc autoload after psp recieved all the gfx firmware */
+- if (psp->autoload_supported && ucode->ucode_id ==
+- AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
++ if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
++ AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
+ ret = psp_rlc_autoload(psp);
+ if (ret) {
+ DRM_ERROR("Failed to start rlc autoload\n");
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4616-drm-amdgpu-should-stop-GFX-ring-in-hw_fini.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4616-drm-amdgpu-should-stop-GFX-ring-in-hw_fini.patch
new file mode 100644
index 00000000..eb7ba795
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4616-drm-amdgpu-should-stop-GFX-ring-in-hw_fini.patch
@@ -0,0 +1,33 @@
+From cf9b2a4cf8e35ce24f5d1d6f7e98579cda2ec175 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Fri, 29 Nov 2019 16:20:51 +0800
+Subject: [PATCH 4616/4736] drm/amdgpu: should stop GFX ring in hw_fini
+
+To align with the scheme from gfx9
+
+disabling GFX ring after VM shutdown could avoid
+garbage data be fetched to GFX RB which may lead
+to unnecessary screw up on GFX
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 5bd31e49601c..fd7ae21eb540 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3810,7 +3810,7 @@ static int gfx_v10_0_hw_fini(void *handle)
+ if (amdgpu_gfx_disable_kcq(adev))
+ DRM_ERROR("KCQ disable failed\n");
+ if (amdgpu_sriov_vf(adev)) {
+- pr_debug("For SRIOV client, shouldn't do anything.\n");
++ gfx_v10_0_cp_gfx_enable(adev, false);
+ return 0;
+ }
+ gfx_v10_0_cp_enable(adev, false);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch
new file mode 100644
index 00000000..785a0841
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch
@@ -0,0 +1,89 @@
+From 34d7f239a288a1195c3b802a5851f493c6dce4e4 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:33:38 +0800
+Subject: [PATCH 4617/4736] drm/amdgpu: fix GFX10 missing CSIB set(v3)
+
+still need to init csb even for SRIOV
+
+v2:
+drop init_pg() for gfx10 at all since
+PG and GFX off feature will be fully controled
+by RLC and SMU fw for gfx10
+
+v3:
+drop the flush_gpu_tlb lines since we consider
+it is only usefull in emulation
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 33 ++++----------------------
+ 1 file changed, 5 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index fd7ae21eb540..ed630d37c32c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1769,22 +1769,6 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
+-{
+- int i;
+- int r;
+-
+- r = gfx_v10_0_init_csb(adev);
+- if (r)
+- return r;
+-
+- for (i = 0; i < adev->num_vmhubs; i++)
+- amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+-
+- /* TODO: init power gating */
+- return 0;
+-}
+-
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+ {
+ u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+@@ -1877,21 +1861,16 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ {
+ int r;
+
+- if (amdgpu_sriov_vf(adev))
+- return 0;
+-
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+- r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+- if (r)
+- return r;
+
+- r = gfx_v10_0_init_pg(adev);
++ r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ if (r)
+ return r;
+
+- /* enable RLC SRM */
+- gfx_v10_0_rlc_enable_srm(adev);
++ gfx_v10_0_init_csb(adev);
+
++ if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
++ gfx_v10_0_rlc_enable_srm(adev);
+ } else {
+ adev->gfx.rlc.funcs->stop(adev);
+
+@@ -1913,9 +1892,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ return r;
+ }
+
+- r = gfx_v10_0_init_pg(adev);
+- if (r)
+- return r;
++ gfx_v10_0_init_csb(adev);
+
+ adev->gfx.rlc.funcs->start(adev);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4618-drm-amdgpu-not-remove-sysfs-if-not-create-sysfs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4618-drm-amdgpu-not-remove-sysfs-if-not-create-sysfs.patch
new file mode 100644
index 00000000..a08e6164
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4618-drm-amdgpu-not-remove-sysfs-if-not-create-sysfs.patch
@@ -0,0 +1,126 @@
+From e619c353cc3f794e94a75070c06586c6b80d19d6 Mon Sep 17 00:00:00 2001
+From: Yintian Tao <yttao@amd.com>
+Date: Fri, 29 Nov 2019 16:05:55 +0800
+Subject: [PATCH 4618/4736] drm/amdgpu: not remove sysfs if not create sysfs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When load amdgpu failed before create pm_sysfs and ucode_sysfs,
+the pm_sysfs and ucode_sysfs should not be removed.
+Otherwise, there will be warning call trace just like below.
+[ 24.836386] [drm] VCE initialized successfully.
+[ 24.841352] amdgpu 0000:00:07.0: amdgpu_device_ip_init failed
+[ 25.370383] amdgpu 0000:00:07.0: Fatal error during GPU init
+[ 25.889575] [drm] amdgpu: finishing device.
+[ 26.069128] amdgpu 0000:00:07.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110)
+[ 26.070110] [drm:gfx_v9_0_hw_fini [amdgpu]] *ERROR* KCQ disable failed
+[ 26.200309] [TTM] Finalizing pool allocator
+[ 26.200314] [TTM] Finalizing DMA pool allocator
+[ 26.200349] [TTM] Zone kernel: Used memory at exit: 0 KiB
+[ 26.200351] [TTM] Zone dma32: Used memory at exit: 0 KiB
+[ 26.200353] [drm] amdgpu: ttm finalized
+[ 26.205329] ------------[ cut here ]------------
+[ 26.205330] sysfs group 'fw_version' not found for kobject '0000:00:07.0'
+[ 26.205347] WARNING: CPU: 0 PID: 1228 at fs/sysfs/group.c:256 sysfs_remove_group+0x80/0x90
+[ 26.205348] Modules linked in: amdgpu(OE+) gpu_sched(OE) ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache binfmt_misc snd_hda_codec_generic ledtrig_audio crct10dif_pclmul snd_hda_intel crc32_pclmul snd_hda_codec ghash_clmulni_intel snd_hda_core snd_hwdep snd_pcm snd_timer input_leds snd joydev soundcore serio_raw pcspkr evbug aesni_intel aes_x86_64 crypto_simd cryptd mac_hid glue_helper sunrpc ip_tables x_tables autofs4 8139too psmouse 8139cp mii i2c_piix4 pata_acpi floppy
+[ 26.205369] CPU: 0 PID: 1228 Comm: modprobe Tainted: G OE 5.2.0-rc1 #1
+[ 26.205370] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014
+[ 26.205372] RIP: 0010:sysfs_remove_group+0x80/0x90
+[ 26.205374] Code: e8 35 b9 ff ff 5b 41 5c 41 5d 5d c3 48 89 df e8 f6 b5 ff ff eb c6 49 8b 55 00 49 8b 34 24 48 c7 c7 48 7a 70 98 e8 60 63 d3 ff <0f> 0b eb d7 66 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55
+[ 26.205375] RSP: 0018:ffffbee242b0b908 EFLAGS: 00010282
+[ 26.205376] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000006
+[ 26.205377] RDX: 0000000000000007 RSI: 0000000000000092 RDI: ffff97ad6f817380
+[ 26.205377] RBP: ffffbee242b0b920 R08: ffffffff98f520c4 R09: 00000000000002b3
+[ 26.205378] R10: ffffbee242b0b8f8 R11: 00000000000002b3 R12: ffffffffc0e58240
+[ 26.205379] R13: ffff97ad6d1fe0b0 R14: ffff97ad4db954c8 R15: ffff97ad4db7fff0
+[ 26.205380] FS: 00007ff3d8a1c4c0(0000) GS:ffff97ad6f800000(0000) knlGS:0000000000000000
+[ 26.205381] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[ 26.205381] CR2: 00007f9b2ef1df04 CR3: 000000042aab8001 CR4: 00000000003606f0
+[ 26.205384] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+[ 26.205385] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+[ 26.205385] Call Trace:
+[ 26.205461] amdgpu_ucode_sysfs_fini+0x18/0x20 [amdgpu]
+[ 26.205518] amdgpu_device_fini+0x3b4/0x560 [amdgpu]
+[ 26.205573] amdgpu_driver_unload_kms+0x4f/0xa0 [amdgpu]
+[ 26.205623] amdgpu_driver_load_kms+0xcd/0x250 [amdgpu]
+[ 26.205637] drm_dev_register+0x12b/0x1c0 [drm]
+[ 26.205695] amdgpu_pci_probe+0x12a/0x1e0 [amdgpu]
+[ 26.205699] local_pci_probe+0x47/0xa0
+[ 26.205701] pci_device_probe+0x106/0x1b0
+[ 26.205704] really_probe+0x21a/0x3f0
+[ 26.205706] driver_probe_device+0x11c/0x140
+[ 26.205707] device_driver_attach+0x58/0x60
+[ 26.205709] __driver_attach+0xc3/0x140
+
+Signed-off-by: Yintian Tao <yttao@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Nirmoy Das <nirmoy.das@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 ++++++++++++----
+ 2 files changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 553d93a45e64..4eddee90553b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1037,6 +1037,9 @@ struct amdgpu_device {
+ int pstate;
+ /* enable runtime pm on the device */
+ bool runpm;
++
++ bool pm_sysfs_en;
++ bool ucode_sysfs_en;
+ };
+
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index bb04f9bb038c..0cef0443340d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3049,12 +3049,18 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ amdgpu_pm_virt_sysfs_init(adev);
+
+ r = amdgpu_pm_sysfs_init(adev);
+- if (r)
++ if (r) {
++ adev->pm_sysfs_en = false;
+ DRM_ERROR("registering pm debugfs failed (%d).\n", r);
++ } else
++ adev->pm_sysfs_en = true;
+
+ r = amdgpu_ucode_sysfs_init(adev);
+- if (r)
++ if (r) {
++ adev->ucode_sysfs_en = false;
+ DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
++ } else
++ adev->ucode_sysfs_en = true;
+
+ r = amdgpu_debugfs_gem_init(adev);
+ if (r)
+@@ -3155,7 +3161,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ }
+ amdgpu_ib_pool_fini(adev);
+ amdgpu_fence_driver_fini(adev);
+- amdgpu_pm_sysfs_fini(adev);
++ if (adev->pm_sysfs_en)
++ amdgpu_pm_sysfs_fini(adev);
+ amdgpu_fbdev_fini(adev);
+ r = amdgpu_device_ip_fini(adev);
+ if (adev->firmware.gpu_info_fw) {
+@@ -3190,7 +3197,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+
+ amdgpu_debugfs_regs_cleanup(adev);
+ device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
+- amdgpu_ucode_sysfs_fini(adev);
++ if (adev->ucode_sysfs_en)
++ amdgpu_ucode_sysfs_fini(adev);
+ if (IS_ENABLED(CONFIG_PERF_EVENTS))
+ amdgpu_pmu_fini(adev);
+ amdgpu_debugfs_preempt_cleanup(adev);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4619-drm-amd-display-Load-TA-firmware-for-navi10-12-14.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4619-drm-amd-display-Load-TA-firmware-for-navi10-12-14.patch
new file mode 100644
index 00000000..8be98eca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4619-drm-amd-display-Load-TA-firmware-for-navi10-12-14.patch
@@ -0,0 +1,55 @@
+From dc314ed13f38600a0dc22f8163aef634ffea8b80 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 8 Nov 2019 16:57:21 -0500
+Subject: [PATCH 4619/4736] drm/amd/display: Load TA firmware for navi10/12/14
+
+load the ta firmware for navi10/12/14.
+This is already being done for raven/picasso and
+is needed for supporting hdcp on navi
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index a12804d6bdce..2e936fc8b1dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -194,6 +194,31 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
+ case CHIP_NAVI12:
++ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
++ err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
++ if (err) {
++ release_firmware(adev->psp.ta_fw);
++ adev->psp.ta_fw = NULL;
++ dev_info(adev->dev,
++ "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
++ } else {
++ err = amdgpu_ucode_validate(adev->psp.ta_fw);
++ if (err)
++ goto out2;
++
++ ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
++ adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
++ adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
++ adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
++ le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
++
++ adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
++
++ adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
++ adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
++ adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
++ le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
++ }
+ break;
+ default:
+ BUG();
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4620-drm-amdgpu-Added-ASIC-specific-checks-in-gfxhub-V1.1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4620-drm-amdgpu-Added-ASIC-specific-checks-in-gfxhub-V1.1.patch
new file mode 100644
index 00000000..7c1e2ab3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4620-drm-amdgpu-Added-ASIC-specific-checks-in-gfxhub-V1.1.patch
@@ -0,0 +1,56 @@
+From 65fbe53b9185dbdfd217fc78f88629535635b260 Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Mon, 2 Dec 2019 17:57:25 +0800
+Subject: [PATCH 4620/4736] drm/amdgpu: Added ASIC specific checks in gfxhub
+ V1.1 get XGMI info
+
+Added max hive/node info checks per supported ASIC
+
+Change-Id: I1713285d7f650a1137b15d89fa000ea824421b6b
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+index 5e9ab8eb214a..c0ab71df0d90 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+@@ -33,16 +33,31 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
+ u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
+ u32 max_region =
+ REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
++ u32 max_num_physical_nodes = 0;
++ u32 max_physical_node_id = 0;
++
++ switch (adev->asic_type) {
++ case CHIP_VEGA20:
++ max_num_physical_nodes = 4;
++ max_physical_node_id = 3;
++ break;
++ case CHIP_ARCTURUS:
++ max_num_physical_nodes = 8;
++ max_physical_node_id = 7;
++ break;
++ default:
++ return -EINVAL;
++ }
+
+ /* PF_MAX_REGION=0 means xgmi is disabled */
+ if (max_region) {
+ adev->gmc.xgmi.num_physical_nodes = max_region + 1;
+- if (adev->gmc.xgmi.num_physical_nodes > 4)
++ if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
+ return -EINVAL;
+
+ adev->gmc.xgmi.physical_node_id =
+ REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
+- if (adev->gmc.xgmi.physical_node_id > 3)
++ if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
+ return -EINVAL;
+ adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
+ RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4621-drm-amdgpu-sriov-No-need-the-event-3-and-4-now.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4621-drm-amdgpu-sriov-No-need-the-event-3-and-4-now.patch
new file mode 100644
index 00000000..800bdce2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4621-drm-amdgpu-sriov-No-need-the-event-3-and-4-now.patch
@@ -0,0 +1,30 @@
+From ad26699d7664f99259113ec33051ae9d3aafbdb8 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Tue, 3 Dec 2019 01:53:10 +0800
+Subject: [PATCH 4621/4736] drm/amdgpu/sriov: No need the event 3 and 4 now
+
+As will call unload kms when initialize fail, and the unload kms will
+send event 3 and 4, so don't need event 3 and 4 in device init.
+
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 0cef0443340d..db80dd97f0ef 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3019,8 +3019,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ }
+ dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
+ amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
+- if (amdgpu_virt_request_full_gpu(adev, false))
+- amdgpu_virt_release_full_gpu(adev, false);
+ goto failed;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4622-drm-amdgpu-move-CS-secure-flag-next-the-structs-wher.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4622-drm-amdgpu-move-CS-secure-flag-next-the-structs-wher.patch
new file mode 100644
index 00000000..3988e602
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4622-drm-amdgpu-move-CS-secure-flag-next-the-structs-wher.patch
@@ -0,0 +1,45 @@
+From bfdfc240899956bb60f4c096e24245cb6f065974 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 27 Nov 2019 15:55:35 -0500
+Subject: [PATCH 4622/4736] drm/amdgpu: move CS secure flag next the structs
+ where it's used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+So it's not mixed up with the CTX stuff.
+
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ include/uapi/drm/amdgpu_drm.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 989afacefb92..78f155da2105 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -224,9 +224,6 @@ union drm_amdgpu_bo_list {
+ #define AMDGPU_CTX_OP_QUERY_STATE 3
+ #define AMDGPU_CTX_OP_QUERY_STATE2 4
+
+-/* Flag the command submission as secure */
+-#define AMDGPU_CS_FLAGS_SECURE (1 << 0)
+-
+ /* GPU reset status */
+ #define AMDGPU_CTX_NO_RESET 0
+ /* this the context caused it */
+@@ -615,6 +612,9 @@ struct drm_amdgpu_cs_chunk {
+ __u64 chunk_data;
+ };
+
++/* Flag the command submission as secure */
++#define AMDGPU_CS_FLAGS_SECURE (1 << 0)
++
+ struct drm_amdgpu_cs_in {
+ /** Rendering context id */
+ __u32 ctx_id;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4623-amd-amdgpu-sriov-swSMU-disable-for-sriov.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4623-amd-amdgpu-sriov-swSMU-disable-for-sriov.patch
new file mode 100644
index 00000000..c8cda30d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4623-amd-amdgpu-sriov-swSMU-disable-for-sriov.patch
@@ -0,0 +1,47 @@
+From daae5be7cdfd04391cb447f0ec09f4ddc9feb1f9 Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Mon, 2 Dec 2019 18:41:36 +0800
+Subject: [PATCH 4623/4736] amd/amdgpu/sriov swSMU disable for sriov
+
+For boards greater than ARCTURUS, and under sriov platform,
+swSMU is not supported because smu ip block is commented at
+guest driver.
+
+Generally for sriov, initialization of smu is moved to host driver.
+Thus, smu sw_init and hw_init will not be executed at guest driver.
+
+Without sw structure being initialized in guest driver, swSMU cannot
+declare to be supported.
+
+Change-Id: Idb1c577d0dc2fc67cb6e83352aba83c9a987875f
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index acbbafeea01c..b57239d2228b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -529,10 +529,13 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
+ bool is_support_sw_smu(struct amdgpu_device *adev)
+ {
+ if (adev->asic_type == CHIP_VEGA20)
+- return (amdgpu_dpm == 2) ? true: false;
+- else if (adev->asic_type >= CHIP_ARCTURUS)
+- return true;
+- else
++ return (amdgpu_dpm == 2) ? true : false;
++ else if (adev->asic_type >= CHIP_ARCTURUS) {
++ if (amdgpu_sriov_vf(adev))
++ return false;
++ else
++ return true;
++ } else
+ return false;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4624-drm-amd-display-Adding-NV14-IP-Parameters.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4624-drm-amd-display-Adding-NV14-IP-Parameters.patch
new file mode 100644
index 00000000..91901528
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4624-drm-amd-display-Adding-NV14-IP-Parameters.patch
@@ -0,0 +1,99 @@
+From cd1426784740abc2f9d7d71886ff87be1a28a58c Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Mon, 2 Dec 2019 14:54:16 -0500
+Subject: [PATCH 4624/4736] drm/amd/display: Adding NV14 IP Parameters
+
+[Why]
+NV14 IP Parameters are missing.
+
+[How]
+Add IP Parameters in.
+
+Signed-off-by: Zhan liu <zhan.liu@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 68 +++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f30e9aef53ba..6e6e4bb2d5ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -150,6 +150,74 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+ .xfc_fill_constant_bytes = 0,
+ };
+
++struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
++ .odm_capable = 1,
++ .gpuvm_enable = 0,
++ .hostvm_enable = 0,
++ .gpuvm_max_page_table_levels = 4,
++ .hostvm_max_page_table_levels = 4,
++ .hostvm_cached_page_table_levels = 0,
++ .num_dsc = 5,
++ .rob_buffer_size_kbytes = 168,
++ .det_buffer_size_kbytes = 164,
++ .dpte_buffer_size_in_pte_reqs_luma = 84,
++ .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
++ .dpp_output_buffer_pixels = 2560,
++ .opp_output_buffer_lines = 1,
++ .pixel_chunk_size_kbytes = 8,
++ .pte_enable = 1,
++ .max_page_table_levels = 4,
++ .pte_chunk_size_kbytes = 2,
++ .meta_chunk_size_kbytes = 2,
++ .writeback_chunk_size_kbytes = 2,
++ .line_buffer_size_bits = 789504,
++ .is_line_buffer_bpp_fixed = 0,
++ .line_buffer_fixed_bpp = 0,
++ .dcc_supported = true,
++ .max_line_buffer_lines = 12,
++ .writeback_luma_buffer_size_kbytes = 12,
++ .writeback_chroma_buffer_size_kbytes = 8,
++ .writeback_chroma_line_buffer_width_pixels = 4,
++ .writeback_max_hscl_ratio = 1,
++ .writeback_max_vscl_ratio = 1,
++ .writeback_min_hscl_ratio = 1,
++ .writeback_min_vscl_ratio = 1,
++ .writeback_max_hscl_taps = 12,
++ .writeback_max_vscl_taps = 12,
++ .writeback_line_buffer_luma_buffer_size = 0,
++ .writeback_line_buffer_chroma_buffer_size = 14643,
++ .cursor_buffer_size = 8,
++ .cursor_chunk_size = 2,
++ .max_num_otg = 5,
++ .max_num_dpp = 5,
++ .max_num_wb = 1,
++ .max_dchub_pscl_bw_pix_per_clk = 4,
++ .max_pscl_lb_bw_pix_per_clk = 2,
++ .max_lb_vscl_bw_pix_per_clk = 4,
++ .max_vscl_hscl_bw_pix_per_clk = 4,
++ .max_hscl_ratio = 8,
++ .max_vscl_ratio = 8,
++ .hscl_mults = 4,
++ .vscl_mults = 4,
++ .max_hscl_taps = 8,
++ .max_vscl_taps = 8,
++ .dispclk_ramp_margin_percent = 1,
++ .underscan_factor = 1.10,
++ .min_vblank_lines = 32, //
++ .dppclk_delay_subtotal = 77, //
++ .dppclk_delay_scl_lb_only = 16,
++ .dppclk_delay_scl = 50,
++ .dppclk_delay_cnvc_formatter = 8,
++ .dppclk_delay_cnvc_cursor = 6,
++ .dispclk_delay_subtotal = 87, //
++ .dcfclk_cstate_latency = 10, // SRExitTime
++ .max_inter_dcn_tile_repeaters = 8,
++ .xfc_supported = true,
++ .xfc_fill_bw_overhead_percent = 10.0,
++ .xfc_fill_constant_bytes = 0,
++ .ptoi_supported = 0
++};
++
+ struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
+ /* Defaults that get patched on driver load from firmware. */
+ .clock_limits = {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4625-drm-amd-display-Get-NV14-specific-ip-params-as-neede.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4625-drm-amd-display-Get-NV14-specific-ip-params-as-neede.patch
new file mode 100644
index 00000000..64897879
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4625-drm-amd-display-Get-NV14-specific-ip-params-as-neede.patch
@@ -0,0 +1,38 @@
+From ab2c209b31ddbf37089a6093112c51231d80fd2d Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Mon, 2 Dec 2019 15:12:27 -0500
+Subject: [PATCH 4625/4736] drm/amd/display: Get NV14 specific ip params as
+ needed
+
+[Why]
+NV14 is using its own ip params that's different from other
+DCN2.0 ASICs.
+
+[How]
+Add ASIC revision check to make sure NV14 gets correct
+ip params.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 6e6e4bb2d5ac..f26f79134000 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -3250,6 +3250,10 @@ static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
+ static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
+ uint32_t hw_internal_rev)
+ {
++ /* NV14 */
++ if (ASICREV_IS_NAVI14_M(hw_internal_rev))
++ return &dcn2_0_nv14_ip;
++
+ /* NV12 and NV10 */
+ return &dcn2_0_ip;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4626-drm-amd-display-re-enable-wait-in-pipelock-but-add-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4626-drm-amd-display-re-enable-wait-in-pipelock-but-add-t.patch
new file mode 100644
index 00000000..04814a9e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4626-drm-amd-display-re-enable-wait-in-pipelock-but-add-t.patch
@@ -0,0 +1,50 @@
+From d3dfff4a56eab00907d27cec27f84ce2a472ee07 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Nov 2019 10:02:44 -0500
+Subject: [PATCH 4626/4736] drm/amd/display: re-enable wait in pipelock, but
+ add timeout
+
+Removing this causes hangs in some games, so re-add it, but add
+a timeout so we don't hang while switching flip types.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205169
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=112266
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 868099fbe8ba..fa1ecff747a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1032,6 +1032,25 @@ void dcn20_pipe_control_lock(
+ if (pipe->plane_state != NULL)
+ flip_immediate = pipe->plane_state->flip_immediate;
+
++ if (flip_immediate && lock) {
++ const int TIMEOUT_FOR_FLIP_PENDING = 100000;
++ int i;
++
++ for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
++ if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
++ break;
++ udelay(1);
++ }
++
++ if (pipe->bottom_pipe != NULL) {
++ for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
++ if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
++ break;
++ udelay(1);
++ }
++ }
++ }
++
+ /* In flip immediate and pipe splitting case, we need to use GSL
+ * for synchronization. Only do setup on locking and on flip type change.
+ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4627-drm-amd-display-fix-double-assignment-to-msg_id-fiel.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4627-drm-amd-display-fix-double-assignment-to-msg_id-fiel.patch
new file mode 100644
index 00000000..ed6e2dfb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4627-drm-amd-display-fix-double-assignment-to-msg_id-fiel.patch
@@ -0,0 +1,34 @@
+From 906a1abc5579e083db64a97aa813727025f5e5b9 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Wed, 20 Nov 2019 17:22:42 +0000
+Subject: [PATCH 4627/4736] drm/amd/display: fix double assignment to msg_id
+ field
+
+The msg_id field is being assigned twice. Fix this by replacing the second
+assignment with an assignment to msg_size.
+
+Addresses-Coverity: ("Unused value")
+Fixes: 11a00965d261 ("drm/amd/display: Add PSP block to verify HDCP2.2 steps")
+Reviewed-by: Harry Wentland <harry.wentland>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index 468f5e6c3487..ef4eb55f4474 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -42,7 +42,7 @@ static void hdcp2_message_init(struct mod_hdcp *hdcp,
+ in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+ in->process.msg2_desc.msg_size = 0;
+ in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+- in->process.msg3_desc.msg_id = 0;
++ in->process.msg3_desc.msg_size = 0;
+ }
+ enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4628-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4628-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
new file mode 100644
index 00000000..48b8e862
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4628-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
@@ -0,0 +1,34 @@
+From 1d8164492291c41bf6fa12192c135b230c5b9478 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:37 +0800
+Subject: [PATCH 4628/4736] drm/amd/display: Remove unneeded semicolon in
+ bios_parser.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2192:2-3: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 714a862e7321..ca6a6a707619 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2187,7 +2187,7 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
+ break;
+ default:
+ break;
+- };
++ }
+
+ /* Unidentified device ID, return empty support mask. */
+ return 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4629-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4629-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
new file mode 100644
index 00000000..c4ae0f0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4629-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
@@ -0,0 +1,34 @@
+From 3a2f32f2c447c8973de693aeaef4136558c2fe66 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:38 +0800
+Subject: [PATCH 4629/4736] drm/amd/display: Remove unneeded semicolon in
+ bios_parser2.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c:995:2-3: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index c70bfdca5d2f..453ac65c7ee3 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -990,7 +990,7 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
+ break;
+ default:
+ break;
+- };
++ }
+
+ /* Unidentified device ID, return empty support mask. */
+ return 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4630-drm-amd-display-Remove-unneeded-semicolon-in-hdcp.c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4630-drm-amd-display-Remove-unneeded-semicolon-in-hdcp.c.patch
new file mode 100644
index 00000000..041f3700
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4630-drm-amd-display-Remove-unneeded-semicolon-in-hdcp.c.patch
@@ -0,0 +1,34 @@
+From f48b5b7ba85e258dfdc3eb0fb081cdebe54e8292 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:39 +0800
+Subject: [PATCH 4630/4736] drm/amd/display: Remove unneeded semicolon in
+ hdcp.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c:506:2-3: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index cbb5e9c063ec..8aa528e874c4 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -503,7 +503,7 @@ enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode(
+ break;
+ default:
+ break;
+- };
++ }
+
+ return mode;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4631-drm-amd-display-Remove-unneeded-semicolon-in-display.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4631-drm-amd-display-Remove-unneeded-semicolon-in-display.patch
new file mode 100644
index 00000000..765d2b04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4631-drm-amd-display-Remove-unneeded-semicolon-in-display.patch
@@ -0,0 +1,37 @@
+From 6bd201a6362cba670547da90bce90900e82e5d54 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:40 +0800
+Subject: [PATCH 4631/4736] drm/amd/display: Remove unneeded semicolon in
+ display_rq_dlg_calc_21.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:1525:144-145: Unneeded semicolon
+drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:1526:142-143: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+index a4b103eb4b02..e60af383b4db 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+@@ -1522,8 +1522,8 @@ static void dml_rq_dlg_get_dlg_params(
+
+ disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
+ disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
+- disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
+- disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
++ disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
++ disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
+
+ // Clamp to max for now
+ if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4632-drm-amd-display-remove-redundant-assignment-to-varia.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4632-drm-amd-display-remove-redundant-assignment-to-varia.patch
new file mode 100644
index 00000000..d736a34d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4632-drm-amd-display-remove-redundant-assignment-to-varia.patch
@@ -0,0 +1,33 @@
+From 517a2607999a6e4cdb4c8cdf8e21d3c7409a0466 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Mon, 2 Dec 2019 15:47:38 +0000
+Subject: [PATCH 4632/4736] drm/amd/display: remove redundant assignment to
+ variable v_total
+
+The variable v_total is being initialized with a value that is never
+read and it is being updated later with a new value. The initialization
+is redundant and can be removed.
+
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 9d68cfecd472..52c8edbde2c4 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -120,7 +120,7 @@ static unsigned int calc_v_total_from_refresh(
+ const struct dc_stream_state *stream,
+ unsigned int refresh_in_uhz)
+ {
+- unsigned int v_total = stream->timing.v_total;
++ unsigned int v_total;
+ unsigned int frame_duration_in_ns;
+
+ frame_duration_in_ns =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4633-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4633-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
new file mode 100644
index 00000000..6e78bf97
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4633-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
@@ -0,0 +1,38 @@
+From 1464891b5a6c0e9ea6ff2320a78285b2220b35f9 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:38 +0800
+Subject: [PATCH 4633/4736] drm/amd/powerplay: Remove unneeded variable
+ 'result' in smu10_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c:1154:5-11: Unneeded variable: "result". Return "0" on line 1159
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+index 1115761982a7..4e8ab139bb3b 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+@@ -1151,12 +1151,11 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+ struct smu10_hwmgr *data = hwmgr->backend;
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
+ Watermarks_t *table = &(data->water_marks_table);
+- int result = 0;
+
+ smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
+ smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
+ data->water_marks_exist = true;
+- return result;
++ return 0;
+ }
+
+ static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4634-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4634-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
new file mode 100644
index 00000000..8c3a4f7f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4634-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
@@ -0,0 +1,40 @@
+From c1b1e01ed7586270e02cd5b9218524bcb028798d Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:39 +0800
+Subject: [PATCH 4634/4736] drm/amd/powerplay: Remove unneeded variable
+ 'result' in vega10_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c:4363:5-11: Unneeded variable: "result". Return "0" on line 4370
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index b8cb492102ff..56feae198cae 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -4359,14 +4359,13 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+ struct vega10_hwmgr *data = hwmgr->backend;
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
+ Watermarks_t *table = &(data->smc_state_table.water_marks_table);
+- int result = 0;
+
+ if (!data->registry_data.disable_water_mark) {
+ smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
+ data->water_marks_bitmap = WaterMarksExist;
+ }
+
+- return result;
++ return 0;
+ }
+
+ static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4635-drm-amd-powerplay-Remove-unneeded-variable-ret-in-sm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4635-drm-amd-powerplay-Remove-unneeded-variable-ret-in-sm.patch
new file mode 100644
index 00000000..c8ef1dc9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4635-drm-amd-powerplay-Remove-unneeded-variable-ret-in-sm.patch
@@ -0,0 +1,39 @@
+From e706756e7a90fd3577282f32683b43a141834f40 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:40 +0800
+Subject: [PATCH 4635/4736] drm/amd/powerplay: Remove unneeded variable 'ret'
+ in smu7_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:5188:5-8: Unneeded variable: "ret". Return "0" on line 5196
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 901b5c263744..9e915f680c01 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -5184,13 +5184,11 @@ uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
+
+ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
+ {
+- int ret = 0;
+-
+ hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
+ if (hwmgr->pp_table_version == PP_TABLE_V0)
+ hwmgr->pptable_func = &pptable_funcs;
+ else if (hwmgr->pp_table_version == PP_TABLE_V1)
+ hwmgr->pptable_func = &pptable_v1_0_funcs;
+
+- return ret;
++ return 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4636-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4636-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
new file mode 100644
index 00000000..a01c0ef4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4636-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
@@ -0,0 +1,42 @@
+From be1308d03d686e74251b9ea6290c03710ec9f2c0 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:41 +0800
+Subject: [PATCH 4636/4736] drm/amd/powerplay: Remove unneeded variable
+ 'result' in vega12_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c:502:5-11: Unneeded variable: "result". Return "0" on line 515
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+index 7af9ad450ac4..aca61d1ff3c2 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+@@ -499,8 +499,6 @@ static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
+ static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
+ PPCLK_e clkID, uint32_t index, uint32_t *clock)
+ {
+- int result = 0;
+-
+ /*
+ *SMU expects the Clock ID to be in the top 16 bits.
+ *Lower 16 bits specify the level
+@@ -512,7 +510,7 @@ static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
+
+ *clock = smum_get_argument(hwmgr);
+
+- return result;
++ return 0;
+ }
+
+ static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4637-drm-amd-powerplay-Remove-unneeded-variable-ret-in-am.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4637-drm-amd-powerplay-Remove-unneeded-variable-ret-in-am.patch
new file mode 100644
index 00000000..9185f4ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4637-drm-amd-powerplay-Remove-unneeded-variable-ret-in-am.patch
@@ -0,0 +1,63 @@
+From 53207ce79068fdbac329a781fbe2a7a8802036d1 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:42 +0800
+Subject: [PATCH 4637/4736] drm/amd/powerplay: Remove unneeded variable 'ret'
+ in amdgpu_smu.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/amdgpu_smu.c:1192:5-8: Unneeded variable: "ret". Return "0" on line 1195
+drivers/gpu/drm/amd/powerplay/amdgpu_smu.c:1945:5-8: Unneeded variable: "ret". Return "0" on line 1961
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index b57239d2228b..42656628de90 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1192,10 +1192,9 @@ static int smu_free_memory_pool(struct smu_context *smu)
+ {
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *memory_pool = &smu_table->memory_pool;
+- int ret = 0;
+
+ if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
+- return ret;
++ return 0;
+
+ amdgpu_bo_free_kernel(&memory_pool->bo,
+ &memory_pool->mc_address,
+@@ -1203,7 +1202,7 @@ static int smu_free_memory_pool(struct smu_context *smu)
+
+ memset(memory_pool, 0, sizeof(struct smu_table));
+
+- return ret;
++ return 0;
+ }
+
+ static int smu_start_smc_engine(struct smu_context *smu)
+@@ -1945,7 +1944,6 @@ int smu_write_watermarks_table(struct smu_context *smu)
+ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+ {
+- int ret = 0;
+ struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+ void *table = watermarks->cpu_addr;
+
+@@ -1961,7 +1959,7 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+
+ mutex_unlock(&smu->mutex);
+
+- return ret;
++ return 0;
+ }
+
+ const struct amd_ip_funcs smu_ip_funcs = {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4638-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-than-3-4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4638-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-than-3-4.patch
new file mode 100644
index 00000000..2c806064
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4638-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-than-3-4.patch
@@ -0,0 +1,39 @@
+From 7d92d9d1d3705c164cbbb83b26c0b404efcafdce Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 3 Dec 2019 19:59:55 +0800
+Subject: [PATCH 4638/4736] Revert "drm/amdgpu: Set GTT size to be bigger than
+ 3/4 of RAM"
+
+This reverts commit 55dc9b6a685260f4545a0f16c16bec9756b71a86.
+
+This commit will cause oom issue when do vulcan CTS Test.
+
+Signed-off-by:Kevin Wang <kevin1.wang@amd.com>
+Acked-by: Feifei Xu <feifei.xue@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index d93bfaca5daf..6d295e7ee444 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2156,10 +2156,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ struct sysinfo si;
+
+ si_meminfo(&si);
+- gtt_size = max3((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+- adev->gmc.mc_vram_size,
+- ((uint64_t)si.totalram * si.mem_unit));
+- } else
++ gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
++ adev->gmc.mc_vram_size),
++ ((uint64_t)si.totalram * si.mem_unit * 3/4));
++ }
++ else
+ gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+
+ /* reserve for DGMA import domain */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4639-drm-amdgpu-drop-asd-shared-memory.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4639-drm-amdgpu-drop-asd-shared-memory.patch
new file mode 100644
index 00000000..90e27fd3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4639-drm-amdgpu-drop-asd-shared-memory.patch
@@ -0,0 +1,156 @@
+From d28621c36f48e8359a71a37f1f4f2e524e1cd9f8 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 2 Dec 2019 13:16:09 +0800
+Subject: [PATCH 4639/4736] drm/amdgpu: drop asd shared memory
+
+asd shared memory is not needed since drivers doesn't
+invoke any further cmd to asd directly after the asd
+loading. trust application is the one who needs
+to talk to asd after the initialization
+
+Change-Id: I4d3422cb8a2c27ece99a7373069dfc27898c5ecc
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 44 +++++++------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 12 ++++---
+ 2 files changed, 18 insertions(+), 38 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index f219e2f77b4c..ccd0c8d7c224 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -320,35 +320,17 @@ static int psp_tmr_load(struct psp_context *psp)
+ return ret;
+ }
+
+-static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+- uint64_t asd_mc, uint64_t asd_mc_shared,
+- uint32_t size, uint32_t shared_size)
++static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++ uint64_t asd_mc, uint32_t size)
+ {
+ cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
+ cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
+ cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
+ cmd->cmd.cmd_load_ta.app_len = size;
+
+- cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
+- cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
+- cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
+-}
+-
+-static int psp_asd_init(struct psp_context *psp)
+-{
+- int ret;
+-
+- /*
+- * Allocate 16k memory aligned to 4k from Frame Buffer (local
+- * physical) for shared ASD <-> Driver
+- */
+- ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
+- PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+- &psp->asd_shared_bo,
+- &psp->asd_shared_mc_addr,
+- &psp->asd_shared_buf);
+-
+- return ret;
++ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
++ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
++ cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
+ }
+
+ static int psp_asd_load(struct psp_context *psp)
+@@ -370,11 +352,15 @@ static int psp_asd_load(struct psp_context *psp)
+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+ memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
+
+- psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
+- psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
++ psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
++ psp->asd_ucode_size);
+
+ ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ psp->fence_buf_mc_addr);
++ if (!ret) {
++ psp->asd_context.asd_initialized = true;
++ psp->asd_context.session_id = cmd->resp.session_id;
++ }
+
+ kfree(cmd);
+
+@@ -1213,12 +1199,6 @@ static int psp_hw_start(struct psp_context *psp)
+ return ret;
+ }
+
+- ret = psp_asd_init(psp);
+- if (ret) {
+- DRM_ERROR("PSP asd init failed!\n");
+- return ret;
+- }
+-
+ ret = psp_asd_load(psp);
+ if (ret) {
+ DRM_ERROR("PSP load asd failed!\n");
+@@ -1632,8 +1612,6 @@ static int psp_hw_fini(void *handle)
+ &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
+ amdgpu_bo_free_kernel(&psp->fence_buf_bo,
+ &psp->fence_buf_mc_addr, &psp->fence_buf);
+- amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
+- &psp->asd_shared_buf);
+ amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
+ (void **)&psp->cmd_buf_mem);
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 40594f27dab1..5f8fd3e3535b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -32,7 +32,6 @@
+
+ #define PSP_FENCE_BUFFER_SIZE 0x1000
+ #define PSP_CMD_BUFFER_SIZE 0x1000
+-#define PSP_ASD_SHARED_MEM_SIZE 0x4000
+ #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
+ #define PSP_RAS_SHARED_MEM_SIZE 0x4000
+ #define PSP_1_MEG 0x100000
+@@ -130,6 +129,11 @@ struct psp_xgmi_topology_info {
+ struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
+ };
+
++struct psp_asd_context {
++ bool asd_initialized;
++ uint32_t session_id;
++};
++
+ struct psp_xgmi_context {
+ uint8_t initialized;
+ uint32_t session_id;
+@@ -238,15 +242,12 @@ struct psp_context
+ struct amdgpu_bo *tmr_bo;
+ uint64_t tmr_mc_addr;
+
+- /* asd firmware and buffer */
++ /* asd firmware */
+ const struct firmware *asd_fw;
+ uint32_t asd_fw_version;
+ uint32_t asd_feature_version;
+ uint32_t asd_ucode_size;
+ uint8_t *asd_start_addr;
+- struct amdgpu_bo *asd_shared_bo;
+- uint64_t asd_shared_mc_addr;
+- void *asd_shared_buf;
+
+ /* fence buffer */
+ struct amdgpu_bo *fence_buf_bo;
+@@ -281,6 +282,7 @@ struct psp_context
+ uint32_t ta_dtm_ucode_size;
+ uint8_t *ta_dtm_start_addr;
+
++ struct psp_asd_context asd_context;
+ struct psp_xgmi_context xgmi_context;
+ struct psp_ras_context ras;
+ struct psp_hdcp_context hdcp_context;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4640-drm-amdgpu-unload-asd-in-psp-hw-de-init-phase.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4640-drm-amdgpu-unload-asd-in-psp-hw-de-init-phase.patch
new file mode 100644
index 00000000..540b2d02
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4640-drm-amdgpu-unload-asd-in-psp-hw-de-init-phase.patch
@@ -0,0 +1,72 @@
+From ae5de338aad5f6a846bf2398df484b4b62bf56e2 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 2 Dec 2019 13:37:42 +0800
+Subject: [PATCH 4640/4736] drm/amdgpu: unload asd in psp hw de-init phase
+
+issue unload_ta_cmd to tOS to unload asd driver
+
+Change-Id: I8edde7e57bb1920f897e16354f2fb4103a51f656
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index ccd0c8d7c224..fe2b24e98268 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -367,6 +367,40 @@ static int psp_asd_load(struct psp_context *psp)
+ return ret;
+ }
+
++static void psp_prep_asd_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++ uint32_t asd_session_id)
++{
++ cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
++ cmd->cmd.cmd_unload_ta.session_id = asd_session_id;
++}
++
++static int psp_asd_unload(struct psp_context *psp)
++{
++ int ret;
++ struct psp_gfx_cmd_resp *cmd;
++
++ if (amdgpu_sriov_vf(psp->adev))
++ return 0;
++
++ if (!psp->asd_context.asd_initialized)
++ return 0;
++
++ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
++ if (!cmd)
++ return -ENOMEM;
++
++ psp_prep_asd_unload_cmd_buf(cmd, psp->asd_context.session_id);
++
++ ret = psp_cmd_submit_buf(psp, NULL, cmd,
++ psp->fence_buf_mc_addr);
++ if (!ret)
++ psp->asd_context.asd_initialized = false;
++
++ kfree(cmd);
++
++ return ret;
++}
++
+ static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ uint32_t id, uint32_t value)
+ {
+@@ -1604,6 +1638,8 @@ static int psp_hw_fini(void *handle)
+ psp_hdcp_terminate(psp);
+ }
+
++ psp_asd_unload(psp);
++
+ psp_ring_destroy(psp, PSP_RING_TYPE__KM);
+
+ pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4641-drm-amdgpu-load-np-fw-prior-before-loading-the-TAs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4641-drm-amdgpu-load-np-fw-prior-before-loading-the-TAs.patch
new file mode 100644
index 00000000..cb2e1dd4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4641-drm-amdgpu-load-np-fw-prior-before-loading-the-TAs.patch
@@ -0,0 +1,106 @@
+From 3e741d06ad7e1011e809c9427f2be3b830167730 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 2 Dec 2019 13:44:38 +0800
+Subject: [PATCH 4641/4736] drm/amdgpu: load np fw prior before loading the TAs
+
+Platform TAs will independently toggle DF Cstate.
+for instance, get/set topology from xgmi ta. do error
+injection from ras ta. In such case, PMFW needs to be
+loaded before TAs so that all the subsequent Cstate
+calls recieved by PSP FW can be routed to PMFW.
+
+Change-Id: I2e24b05d083349963b48674581a265bbceea1ecd
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 66 ++++++++++++-------------
+ 1 file changed, 33 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index fe2b24e98268..728f53ea2ad6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1233,39 +1233,6 @@ static int psp_hw_start(struct psp_context *psp)
+ return ret;
+ }
+
+- ret = psp_asd_load(psp);
+- if (ret) {
+- DRM_ERROR("PSP load asd failed!\n");
+- return ret;
+- }
+-
+- if (adev->gmc.xgmi.num_physical_nodes > 1) {
+- ret = psp_xgmi_initialize(psp);
+- /* Warning the XGMI seesion initialize failure
+- * Instead of stop driver initialization
+- */
+- if (ret)
+- dev_err(psp->adev->dev,
+- "XGMI: Failed to initialize XGMI session\n");
+- }
+-
+- if (psp->adev->psp.ta_fw) {
+- ret = psp_ras_initialize(psp);
+- if (ret)
+- dev_err(psp->adev->dev,
+- "RAS: Failed to initialize RAS\n");
+-
+- ret = psp_hdcp_initialize(psp);
+- if (ret)
+- dev_err(psp->adev->dev,
+- "HDCP: Failed to initialize HDCP\n");
+-
+- ret = psp_dtm_initialize(psp);
+- if (ret)
+- dev_err(psp->adev->dev,
+- "DTM: Failed to initialize DTM\n");
+- }
+-
+ return 0;
+ }
+
+@@ -1581,6 +1548,39 @@ static int psp_load_fw(struct amdgpu_device *adev)
+ if (ret)
+ goto failed;
+
++ ret = psp_asd_load(psp);
++ if (ret) {
++ DRM_ERROR("PSP load asd failed!\n");
++ return ret;
++ }
++
++ if (adev->gmc.xgmi.num_physical_nodes > 1) {
++ ret = psp_xgmi_initialize(psp);
++ /* Warning the XGMI seesion initialize failure
++ * Instead of stop driver initialization
++ */
++ if (ret)
++ dev_err(psp->adev->dev,
++ "XGMI: Failed to initialize XGMI session\n");
++ }
++
++ if (psp->adev->psp.ta_fw) {
++ ret = psp_ras_initialize(psp);
++ if (ret)
++ dev_err(psp->adev->dev,
++ "RAS: Failed to initialize RAS\n");
++
++ ret = psp_hdcp_initialize(psp);
++ if (ret)
++ dev_err(psp->adev->dev,
++ "HDCP: Failed to initialize HDCP\n");
++
++ ret = psp_dtm_initialize(psp);
++ if (ret)
++ dev_err(psp->adev->dev,
++ "DTM: Failed to initialize DTM\n");
++ }
++
+ return 0;
+
+ failed:
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4642-drm-amdkfd-Contain-MMHUB-number-in-mmhub_v9_4_setup_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4642-drm-amdkfd-Contain-MMHUB-number-in-mmhub_v9_4_setup_.patch
new file mode 100644
index 00000000..f46109c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4642-drm-amdkfd-Contain-MMHUB-number-in-mmhub_v9_4_setup_.patch
@@ -0,0 +1,114 @@
+From 1bfa29f65120b85cf1a90140f62cc8f0cdd150d1 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Mon, 2 Dec 2019 23:12:10 -0500
+Subject: [PATCH 4642/4736] drm/amdkfd: Contain MMHUB number in
+ mmhub_v9_4_setup_vm_pt_regs()
+
+Adjust the exposed function prototype so that the caller does not need
+to know the MMHUB number.
+
+Change-Id: I4420d1715984f703954f074682b075fc59e2a330
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 6 ++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 8 --------
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 14 ++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h | 2 ++
+ 4 files changed, 16 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index f1884b3941e2..4e3570e0e394 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -41,7 +41,7 @@
+ #include "soc15d.h"
+ #include "mmhub_v1_0.h"
+ #include "gfxhub_v1_0.h"
+-#include "gmc_v9_0.h"
++#include "mmhub_v9_4.h"
+
+
+ enum hqd_dequeue_request_type {
+@@ -962,9 +962,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmi
+ * on GFX8 and older.
+ */
+ if (adev->asic_type == CHIP_ARCTURUS) {
+- /* Two MMHUBs */
+- mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base);
+- mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base);
++ mmhub_v9_4_setup_vm_pt_regs(adev, vmid, page_table_base);
+ } else
+ mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+index 971c0840358f..49e8be761214 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+@@ -36,12 +36,4 @@
+
+ extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
+ extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
+-
+-/* amdgpu_amdkfd*.c */
+-void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+- uint64_t value);
+-void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+- uint64_t value);
+-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
+- uint32_t vmid, uint64_t value);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 8599bfdb9a9e..d9301e80522a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -54,7 +54,7 @@ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
+ return base;
+ }
+
+-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
++static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
+ uint32_t vmid, uint64_t value)
+ {
+ /* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
+@@ -80,7 +80,7 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
+ {
+ uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+- mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base);
++ mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
+
+ WREG32_SOC15_OFFSET(MMHUB, 0,
+ mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+@@ -101,6 +101,16 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
+ (u32)(adev->gmc.gart_end >> 44));
+ }
+
++void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++ uint64_t page_table_base)
++{
++ int i;
++
++ for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
++ mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
++ page_table_base);
++}
++
+ static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
+ int hubid)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+index 354a4b7e875b..1b979773776c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+@@ -34,5 +34,7 @@ void mmhub_v9_4_init(struct amdgpu_device *adev);
+ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+ enum amd_clockgating_state state);
+ void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
++void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++ uint64_t page_table_base);
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4643-drm-scheduler-Avoid-accessing-freed-bad-job.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4643-drm-scheduler-Avoid-accessing-freed-bad-job.patch
new file mode 100644
index 00000000..a2a0a85d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4643-drm-scheduler-Avoid-accessing-freed-bad-job.patch
@@ -0,0 +1,97 @@
+From de6e01403013d5d7ec970b8b4eb4ca07cc736d19 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 25 Nov 2019 15:51:29 -0500
+Subject: [PATCH 4643/4736] drm/scheduler: Avoid accessing freed bad job.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Problem:
+Due to a race between drm_sched_cleanup_jobs in sched thread and
+drm_sched_job_timedout in timeout work there is a possiblity that
+bad job was already freed while still being accessed from the
+timeout thread.
+
+Fix:
+Instead of just peeking at the bad job in the mirror list
+remove it from the list under lock and then put it back later when
+we are garanteed no race with main sched thread is possible which
+is after the thread is parked.
+
+v2: Lock around processing ring_mirror_list in drm_sched_cleanup_jobs.
+
+v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
+drm_sched_get_cleanup_job already has a lock there.
+
+v4: Fix comments to relfect latest code in drm-misc.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Tested-by: Emily Deng <Emily.Deng@amd.com>
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Link: https://patchwork.freedesktop.org/patch/342356
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_main.c | 27 ++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index 108bac88dedb..0ccce80513e5 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -288,10 +288,21 @@ static void drm_sched_job_timedout(struct work_struct *work)
+ unsigned long flags;
+
+ sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work);
++
++ /* Protects against concurrent deletion in drm_sched_get_cleanup_job */
++ spin_lock_irqsave(&sched->job_list_lock, flags);
+ job = list_first_entry_or_null(&sched->ring_mirror_list,
+ struct drm_sched_job, node);
+
+ if (job) {
++ /*
++ * Remove the bad job so it cannot be freed by concurrent
++ * drm_sched_cleanup_jobs. It will be reinserted back after sched->thread
++ * is parked at which point it's safe.
++ */
++ list_del_init(&job->node);
++ spin_unlock_irqrestore(&sched->job_list_lock, flags);
++
+ job->sched->ops->timedout_job(job);
+
+ /*
+@@ -302,6 +313,8 @@ static void drm_sched_job_timedout(struct work_struct *work)
+ job->sched->ops->free_job(job);
+ sched->free_guilty = false;
+ }
++ } else {
++ spin_unlock_irqrestore(&sched->job_list_lock, flags);
+ }
+
+ spin_lock_irqsave(&sched->job_list_lock, flags);
+@@ -413,6 +426,20 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad)
+ }
+ }
+
++ /*
++ * Reinsert back the bad job here - now it's safe as
++ * drm_sched_get_cleanup_job cannot race against us and release the
++ * bad job at this point - we parked (waited for) any in progress
++ * (earlier) cleanups and drm_sched_get_cleanup_job will not be called
++ * now until the scheduler thread is unparked.
++ */
++ if (bad && bad->sched == sched)
++ /*
++ * Add at the head of the queue to reflect it was the earliest
++ * job extracted.
++ */
++ list_add(&bad->node, &sched->ring_mirror_list);
++
+ /*
+ * Stop pending timer in flight as we rearm it in drm_sched_start. This
+ * avoids the pending timeout work in progress to fire right away after
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4644-drm-amdkfd-kfd-debugger-set-DISPATCH_PTR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4644-drm-amdkfd-kfd-debugger-set-DISPATCH_PTR.patch
new file mode 100644
index 00000000..5b24b5c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4644-drm-amdkfd-kfd-debugger-set-DISPATCH_PTR.patch
@@ -0,0 +1,35 @@
+From 148030d491eb0bc69792e800291ee61722ad1a51 Mon Sep 17 00:00:00 2001
+From: "Philip.Cox@amd.com" <Philip.Cox@amd.com>
+Date: Tue, 26 Nov 2019 14:28:24 -0500
+Subject: [PATCH 4644/4736] drm/amdkfd: kfd debugger -- set DISPATCH_PTR
+
+We need to set bit 14 in mqd var CP_HQD_HQ_STATUS0 to have the CP set
+the DISPATCH_PTR which is needed for the debugger.
+
+Bug: SWDEV-208421
+
+Change-Id: I2b98afc392a9299210aa2b6faa00fc83b27e51eb
+Signed-off-by: Philip.Cox@amd.com <Philip.Cox@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index f9ee530774bf..1b35cad950b4 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -193,6 +193,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
+ 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
+ 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
+
++ /* Set cp_hqd_hq_status0 bit 14 to 1 to have the CP set up the
++ * DISPATCH_PTR. This is required for the kfd debugger
++ */
++ m->cp_hqd_hq_status0 = 1 << 14;
++
+ if (q->format == KFD_QUEUE_FORMAT_AQL) {
+ m->cp_hqd_aql_control =
+ 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4645-drm-amd-display-Loading-NV10-14-Bounding-Box-Data-Di.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4645-drm-amd-display-Loading-NV10-14-Bounding-Box-Data-Di.patch
new file mode 100644
index 00000000..f1a1436b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4645-drm-amd-display-Loading-NV10-14-Bounding-Box-Data-Di.patch
@@ -0,0 +1,51 @@
+From fb7b766d7643ee5bc519bc1dcc98ac0c788306df Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Tue, 3 Dec 2019 12:46:01 -0500
+Subject: [PATCH 4645/4736] drm/amd/display: Loading NV10/14 Bounding Box Data
+ Directly From Code
+
+[Why]
+NV10/14 has released. Its time to get NV10/14 bounding box
+directly from code.
+
+[How]
+Retrieve NV10/14 bounding box data directly from code.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f26f79134000..2315da20fd41 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -79,8 +79,6 @@
+
+ #include "amdgpu_socbb.h"
+
+-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
+-#define SOC_BOUNDING_BOX_VALID false
+ #define DC_LOGGER_INIT(logger)
+
+ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+@@ -3277,12 +3275,13 @@ static bool init_soc_bounding_box(struct dc *dc,
+
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+- if (!bb && !SOC_BOUNDING_BOX_VALID) {
++ /* TODO: upstream NV12 bounding box when its launched */
++ if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
+ DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+ return false;
+ }
+
+- if (bb && !SOC_BOUNDING_BOX_VALID) {
++ if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
+ int i;
+
+ dcn2_0_nv12_soc.sr_exit_time_us =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4646-drm-amdgpu-powerplay-unify-smu-send-message-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4646-drm-amdgpu-powerplay-unify-smu-send-message-function.patch
new file mode 100644
index 00000000..4d6d51f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4646-drm-amdgpu-powerplay-unify-smu-send-message-function.patch
@@ -0,0 +1,244 @@
+From a7f8bf4e09c82148aa690d2dc58212dd7af468a9 Mon Sep 17 00:00:00 2001
+From: Likun Gao <Likun.Gao@amd.com>
+Date: Mon, 2 Dec 2019 15:04:35 +0800
+Subject: [PATCH 4646/4736] drm/amdgpu/powerplay: unify smu send message
+ function
+
+Drop smu_send_smc_msg function from ASIC specify structure.
+Reuse smu_send_smc_msg_with_param function for smu_send_smc_msg.
+Set paramer to 0 for smu_send_msg function, otherwise it will send
+with previous paramer value (Not a certain value).
+Materialize msg type for smu send message function definition.
+
+Signed-off-by: Likun Gao <Likun.Gao@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 ++++++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 -
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 5 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 5 ++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 -
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 1 -
+ drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 +--
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 29 ++-----------------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 28 ++----------------
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 -
+ 11 files changed, 21 insertions(+), 67 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 42656628de90..2dd960e85a24 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -2568,3 +2568,12 @@ uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
+
+ return ret;
+ }
++
++int smu_send_smc_msg(struct smu_context *smu,
++ enum smu_message_type msg)
++{
++ int ret;
++
++ ret = smu_send_smc_msg_with_param(smu, msg, 0);
++ return ret;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index cf3c31b0524c..b87be39c9a3b 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -2137,7 +2137,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .system_features_control = smu_v11_0_system_features_control,
+- .send_smc_msg = smu_v11_0_send_msg,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_smc_arg = smu_v11_0_read_arg,
+ .init_display_count = smu_v11_0_init_display_count,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index ada4a8dc4112..ca3fdc6777cf 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -500,8 +500,8 @@ struct pptable_funcs {
+ int (*notify_memory_pool_location)(struct smu_context *smu);
+ int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
+ int (*system_features_control)(struct smu_context *smu, bool en);
+- int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
+- int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
++ int (*send_smc_msg_with_param)(struct smu_context *smu,
++ enum smu_message_type msg, uint32_t param);
+ int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
+ int (*init_display_count)(struct smu_context *smu, uint32_t count);
+ int (*set_allowed_mask)(struct smu_context *smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 716fcb274191..610e301a5fce 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -178,10 +178,9 @@ int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
+ int smu_v11_0_system_features_control(struct smu_context *smu,
+ bool en);
+
+-int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
+-
+ int
+-smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v11_0_send_msg_with_param(struct smu_context *smu,
++ enum smu_message_type msg,
+ uint32_t param);
+
+ int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 44c65dd8850d..922973b7e29f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -44,10 +44,9 @@ int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
+
+ int smu_v12_0_wait_for_response(struct smu_context *smu);
+
+-int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg);
+-
+ int
+-smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v12_0_send_msg_with_param(struct smu_context *smu,
++ enum smu_message_type msg,
+ uint32_t param);
+
+ int smu_v12_0_check_fw_status(struct smu_context *smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index c94c2b67c309..cd8798610ed3 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -2082,7 +2082,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .system_features_control = smu_v11_0_system_features_control,
+- .send_smc_msg = smu_v11_0_send_msg,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_smc_arg = smu_v11_0_read_arg,
+ .init_display_count = smu_v11_0_init_display_count,
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index e5ff08820658..c982f69065ae 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -801,7 +801,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .powergate_sdma = smu_v12_0_powergate_sdma,
+ .powergate_vcn = smu_v12_0_powergate_vcn,
+ .powergate_jpeg = smu_v12_0_powergate_jpeg,
+- .send_smc_msg = smu_v12_0_send_msg,
+ .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ .read_smc_arg = smu_v12_0_read_arg,
+ .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index b2d81d3490cd..60ce1fccaeb5 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -77,8 +77,8 @@
+ #define smu_set_default_od_settings(smu, initialize) \
+ ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+
+-#define smu_send_smc_msg(smu, msg) \
+- ((smu)->ppt_funcs->send_smc_msg? (smu)->ppt_funcs->send_smc_msg((smu), (msg)) : 0)
++int smu_send_smc_msg(struct smu_context *smu, enum smu_message_type msg);
++
+ #define smu_send_smc_msg_with_param(smu, msg, param) \
+ ((smu)->ppt_funcs->send_smc_msg_with_param? (smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+ #define smu_read_smc_arg(smu, arg) \
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index dd4437a9b3d0..9e405a60ee6e 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -88,36 +88,11 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+
+-int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+-{
+- struct amdgpu_device *adev = smu->adev;
+- int ret = 0, index = 0;
+-
+- index = smu_msg_get_index(smu, msg);
+- if (index < 0)
+- return index;
+-
+- smu_v11_0_wait_for_response(smu);
+-
+- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+-
+- smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
+-
+- ret = smu_v11_0_wait_for_response(smu);
+-
+- if (ret)
+- pr_err("failed send message: %10s (%d) response %#x\n",
+- smu_get_message_name(smu, msg), index, ret);
+-
+- return ret;
+-
+-}
+-
+ int
+-smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v11_0_send_msg_with_param(struct smu_context *smu,
++ enum smu_message_type msg,
+ uint32_t param)
+ {
+-
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0, index = 0;
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 045167311ae8..269a7d73b58d 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -77,33 +77,9 @@ int smu_v12_0_wait_for_response(struct smu_context *smu)
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+
+-int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+-{
+- struct amdgpu_device *adev = smu->adev;
+- int ret = 0, index = 0;
+-
+- index = smu_msg_get_index(smu, msg);
+- if (index < 0)
+- return index;
+-
+- smu_v12_0_wait_for_response(smu);
+-
+- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+-
+- smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
+-
+- ret = smu_v12_0_wait_for_response(smu);
+-
+- if (ret)
+- pr_err("Failed to send message 0x%x, response 0x%x\n", index,
+- ret);
+-
+- return ret;
+-
+-}
+-
+ int
+-smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v12_0_send_msg_with_param(struct smu_context *smu,
++ enum smu_message_type msg,
+ uint32_t param)
+ {
+ struct amdgpu_device *adev = smu->adev;
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 83862544a45c..a371a0da427e 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3231,7 +3231,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .system_features_control = smu_v11_0_system_features_control,
+- .send_smc_msg = smu_v11_0_send_msg,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_smc_arg = smu_v11_0_read_arg,
+ .init_display_count = smu_v11_0_init_display_count,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4647-Revert-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4647-Revert-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-t.patch
new file mode 100644
index 00000000..0a9aa27d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4647-Revert-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-t.patch
@@ -0,0 +1,39 @@
+From 148f3d0786d30aa36adf097fe450b79446946400 Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Thu, 5 Dec 2019 11:25:42 +0800
+Subject: [PATCH 4647/4736] Revert "Revert "drm/amdgpu: Set GTT size to be
+ bigger than 3/4 of RAM""
+
+This reverts commit 50fab61ae24facd04e5460b1b92745c893a847b5.
+
+This patch should not be cherry-picked to release branch.
+This is for kfd/rocm performance improvement.
+
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 6d295e7ee444..d93bfaca5daf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2156,11 +2156,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ struct sysinfo si;
+
+ si_meminfo(&si);
+- gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+- adev->gmc.mc_vram_size),
+- ((uint64_t)si.totalram * si.mem_unit * 3/4));
+- }
+- else
++ gtt_size = max3((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
++ adev->gmc.mc_vram_size,
++ ((uint64_t)si.totalram * si.mem_unit));
++ } else
+ gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+
+ /* reserve for DGMA import domain */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4648-drm-amdgpu-add-check-before-enabling-disabling-broad.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4648-drm-amdgpu-add-check-before-enabling-disabling-broad.patch
new file mode 100644
index 00000000..b319af72
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4648-drm-amdgpu-add-check-before-enabling-disabling-broad.patch
@@ -0,0 +1,69 @@
+From a5f7a1f05cf52af7e351d3abd10747a1d6f67f53 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Wed, 4 Dec 2019 15:51:16 +0800
+Subject: [PATCH 4648/4736] drm/amdgpu: add check before enabling/disabling
+ broadcast mode
+
+When security violation from new vbios happens, data fabric is
+risky to stop working. So prevent the direct access to DF
+mmFabricConfigAccessControl from the new vbios and onwards.
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 38 ++++++++++++++++------------
+ 1 file changed, 22 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 72bfefdbfa65..9395aa8b8fd0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -268,23 +268,29 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ {
+ u32 tmp;
+
+- /* Put DF on broadcast mode */
+- adev->df_funcs->enable_broadcast_mode(adev, true);
+-
+- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
+- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+- tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
+- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+- } else {
+- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+- tmp |= DF_V3_6_MGCG_DISABLE;
+- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+- }
++ if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
++ /* Put DF on broadcast mode */
++ adev->df_funcs->enable_broadcast_mode(adev, true);
++
++ if (enable) {
++ tmp = RREG32_SOC15(DF, 0,
++ mmDF_PIE_AON0_DfGlobalClkGater);
++ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
++ tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
++ WREG32_SOC15(DF, 0,
++ mmDF_PIE_AON0_DfGlobalClkGater, tmp);
++ } else {
++ tmp = RREG32_SOC15(DF, 0,
++ mmDF_PIE_AON0_DfGlobalClkGater);
++ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
++ tmp |= DF_V3_6_MGCG_DISABLE;
++ WREG32_SOC15(DF, 0,
++ mmDF_PIE_AON0_DfGlobalClkGater, tmp);
++ }
+
+- /* Exit broadcast mode */
+- adev->df_funcs->enable_broadcast_mode(adev, false);
++ /* Exit broadcast mode */
++ adev->df_funcs->enable_broadcast_mode(adev, false);
++ }
+ }
+
+ static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4649-drm-amdgpu-gfx-Improvement-on-EDC-GPR-workarounds.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4649-drm-amdgpu-gfx-Improvement-on-EDC-GPR-workarounds.patch
new file mode 100644
index 00000000..d4ffdffe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4649-drm-amdgpu-gfx-Improvement-on-EDC-GPR-workarounds.patch
@@ -0,0 +1,150 @@
+From 245b79e8a454c5cead7d7624b3824fbb6eb00b0f Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 3 Dec 2019 15:40:10 -0500
+Subject: [PATCH 4649/4736] drm/amdgpu/gfx: Improvement on EDC GPR workarounds
+
+SPI limits total CS waves in flight per SE to no more than 32 * num_cu and
+we need to stuff 40 waves on a CU to completely clean the SGPR. This is
+accomplished in the WR by cleaning the SE in two steps, half of the CU per
+step.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 83 ++++++++++++++++++++-------
+ 1 file changed, 63 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index e644d5ea56b9..994b634c6355 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3941,24 +3941,37 @@ static const struct soc15_reg_entry vgpr_init_regs[] = {
+ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
+ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x100007f }, /* VGPRS=15 (256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
+ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */
+ };
+
+-static const struct soc15_reg_entry sgpr_init_regs[] = {
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
++static const struct soc15_reg_entry sgpr1_init_regs[] = {
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
++};
++
++static const struct soc15_reg_entry sgpr2_init_regs[] = {
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
+ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
+- { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 GPRS) */
++ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
+ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
+ };
+
+@@ -4068,7 +4081,9 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ total_size =
+ ((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
+ total_size +=
+- ((ARRAY_SIZE(sgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
++ ((ARRAY_SIZE(sgpr1_init_regs) * 3) + 4 + 5 + 2) * 4;
++ total_size +=
++ ((ARRAY_SIZE(sgpr2_init_regs) * 3) + 4 + 5 + 2) * 4;
+ total_size = ALIGN(total_size, 256);
+ vgpr_offset = total_size;
+ total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
+@@ -4111,7 +4126,35 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+
+ /* write dispatch packet */
+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+- ib.ptr[ib.length_dw++] = 256; /* x */
++ ib.ptr[ib.length_dw++] = 0x40*2; /* x */
++ ib.ptr[ib.length_dw++] = 1; /* y */
++ ib.ptr[ib.length_dw++] = 1; /* z */
++ ib.ptr[ib.length_dw++] =
++ REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
++
++ /* write CS partial flush packet */
++ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
++ ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
++
++ /* SGPR1 */
++ /* write the register state for the compute dispatch */
++ for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i++) {
++ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
++ ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
++ - PACKET3_SET_SH_REG_START;
++ ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
++ }
++ /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
++ gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
++ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
++ ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
++ - PACKET3_SET_SH_REG_START;
++ ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
++ ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
++
++ /* write dispatch packet */
++ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
++ ib.ptr[ib.length_dw++] = 0xA0*2; /* x */
+ ib.ptr[ib.length_dw++] = 1; /* y */
+ ib.ptr[ib.length_dw++] = 1; /* z */
+ ib.ptr[ib.length_dw++] =
+@@ -4121,13 +4164,13 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+
+- /* SGPR */
++ /* SGPR2 */
+ /* write the register state for the compute dispatch */
+- for (i = 0; i < ARRAY_SIZE(sgpr_init_regs); i++) {
++ for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i++) {
+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+- ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr_init_regs[i])
++ ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
+ - PACKET3_SET_SH_REG_START;
+- ib.ptr[ib.length_dw++] = sgpr_init_regs[i].reg_value;
++ ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
+ }
+ /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
+ gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
+@@ -4139,7 +4182,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+
+ /* write dispatch packet */
+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+- ib.ptr[ib.length_dw++] = 256; /* x */
++ ib.ptr[ib.length_dw++] = 0xA0*2; /* x */
+ ib.ptr[ib.length_dw++] = 1; /* y */
+ ib.ptr[ib.length_dw++] = 1; /* z */
+ ib.ptr[ib.length_dw++] =
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4650-drm-amdgpu-add-header-line-for-power-profile-on-Arct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4650-drm-amdgpu-add-header-line-for-power-profile-on-Arct.patch
new file mode 100644
index 00000000..e40cd8a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4650-drm-amdgpu-add-header-line-for-power-profile-on-Arct.patch
@@ -0,0 +1,39 @@
+From fb3ec24db056b9f2e4e37fea32d86351cb58f38f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 4 Dec 2019 22:07:49 -0500
+Subject: [PATCH 4650/4736] drm/amdgpu: add header line for power profile on
+ Arcturus
+
+So the output is consistent with other asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index b87be39c9a3b..3a793c6ccbf0 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1320,12 +1320,17 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
+ "VR",
+ "COMPUTE",
+ "CUSTOM"};
++ static const char *title[] = {
++ "PROFILE_INDEX(NAME)"};
+ uint32_t i, size = 0;
+ int16_t workload_type = 0;
+
+ if (!smu->pm_enabled || !buf)
+ return -EINVAL;
+
++ size += sprintf(buf + size, "%16s\n",
++ title[0]);
++
+ for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+ /*
+ * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4651-drm-amdgpu-display-fix-the-build-when-CONFIG_DRM_AMD.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4651-drm-amdgpu-display-fix-the-build-when-CONFIG_DRM_AMD.patch
new file mode 100644
index 00000000..9351479b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4651-drm-amdgpu-display-fix-the-build-when-CONFIG_DRM_AMD.patch
@@ -0,0 +1,57 @@
+From 26f647b03728c7a2593dad12b4767439c2b37bee Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 6 Nov 2019 20:51:14 -0500
+Subject: [PATCH 4651/4736] drm/amdgpu/display: fix the build when
+ CONFIG_DRM_AMD_DC_DCN is not set
+
+Need to protect some DSC functions.
+
+Change-Id: Ic67640caab59ec8252837f7b7fceb2a06262d728
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 841f0bfd1e4f..f98ff5f012d2 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3993,7 +3993,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+ int mode_refresh;
+ int preferred_refresh = 0;
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ struct dsc_dec_dpcd_caps dsc_caps;
++#endif
+ uint32_t link_bandwidth_kbps;
+
+ struct dc_sink *sink = NULL;
+@@ -4071,12 +4073,15 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ stream->timing.flags.DSC = 0;
+
+ if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+ aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
+ &dsc_caps);
++#endif
+ link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+ dc_link_get_link_cap(aconnector->dc_link));
+
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (dsc_caps.is_dsc_supported)
+ if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ &dsc_caps,
+@@ -4085,6 +4090,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ &stream->timing,
+ &stream->timing.dsc_cfg))
+ stream->timing.flags.DSC = 1;
++#endif
+ }
+
+ update_stream_scaling_settings(&mode, dm_state, stream);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4652-drm-amdgpu-display-fix-warning-when-CONFIG_DRM_AMD_D.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4652-drm-amdgpu-display-fix-warning-when-CONFIG_DRM_AMD_D.patch
new file mode 100644
index 00000000..ba93b635
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4652-drm-amdgpu-display-fix-warning-when-CONFIG_DRM_AMD_D.patch
@@ -0,0 +1,39 @@
+From f061100ad969742aef328f4d1bbcac87d664ba06 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 8 Nov 2019 11:22:57 -0500
+Subject: [PATCH 4652/4736] drm/amdgpu/display: fix warning when
+ CONFIG_DRM_AMD_DC_DCN is not set
+
+dm_dcn_crtc_high_irq() is only used when CONFIG_DRM_AMD_DC_DCN is set.
+
+Change-Id: I0a986136adc5fde5e6636de458580fc6080a1b9d
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index f98ff5f012d2..bc76d49187fd 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -484,7 +484,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
+ }
+ }
+
+-
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ /**
+ * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
+ * @interrupt params - interrupt parameters
+@@ -546,6 +546,7 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params)
+
+ spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
+ }
++#endif
+
+ static int dm_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4653-drm-amd-display-cleanup-of-function-pointer-tables.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4653-drm-amd-display-cleanup-of-function-pointer-tables.patch
new file mode 100644
index 00000000..a45f630b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4653-drm-amd-display-cleanup-of-function-pointer-tables.patch
@@ -0,0 +1,3251 @@
+From 30f07444549b52d8d00c4b540cfce280e0943d26 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 29 Oct 2019 15:05:56 -0400
+Subject: [PATCH 4653/4736] drm/amd/display: cleanup of function pointer tables
+
+[Why]
+It is becoming increasingly hard to figure out which
+function is called on the different DCN versions
+
+[How]
+1. Make function pointer table init in its own init.c file
+2. Remove other scenarios in hwseq.c file that need to
+include headers of other DCN versions. (If needed,
+it should have been done via the function pointers)
+
+Change-Id: I09ca21dfd5848cc7e678dbefef8df201947df7d3
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/basics/Makefile | 2 +-
+ .../gpu/drm/amd/display/dc/basics/dc_common.c | 101 ++++
+ .../gpu/drm/amd/display/dc/basics/dc_common.h | 42 ++
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-
+ .../gpu/drm/amd/display/dc/core/dc_stream.c | 3 +-
+ .../display/dc/dce110/dce110_hw_sequencer.c | 12 +-
+ .../display/dc/dce110/dce110_hw_sequencer.h | 1 -
+ drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 3 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 436 +++++-------------
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 181 ++++++--
+ .../dc/dcn10/dcn10_hw_sequencer_debug.h | 43 ++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 105 +++++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_init.h | 33 ++
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 428 +++++++----------
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 152 +++---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 131 ++++++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.h | 33 ++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 12 +-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +-
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 3 +-
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 13 +-
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.h | 14 +-
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 135 ++++++
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_init.h | 33 ++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 40 +-
+ 29 files changed, 1256 insertions(+), 716 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile
+index a50a76471107..7ad0cad0f4ef 100644
+--- a/drivers/gpu/drm/amd/display/dc/basics/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile
+@@ -25,7 +25,7 @@
+ # subcomponents.
+
+ BASICS = conversion.o fixpt31_32.o \
+- log_helpers.o vector.o
++ log_helpers.o vector.o dc_common.o
+
+ AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
+
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+new file mode 100644
+index 000000000000..b2fc4f8e6482
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+@@ -0,0 +1,101 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "core_types.h"
++#include "dc_common.h"
++#include "basics/conversion.h"
++
++bool is_rgb_cspace(enum dc_color_space output_color_space)
++{
++ switch (output_color_space) {
++ case COLOR_SPACE_SRGB:
++ case COLOR_SPACE_SRGB_LIMITED:
++ case COLOR_SPACE_2020_RGB_FULLRANGE:
++ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
++ case COLOR_SPACE_ADOBERGB:
++ return true;
++ case COLOR_SPACE_YCBCR601:
++ case COLOR_SPACE_YCBCR709:
++ case COLOR_SPACE_YCBCR601_LIMITED:
++ case COLOR_SPACE_YCBCR709_LIMITED:
++ case COLOR_SPACE_2020_YCBCR:
++ return false;
++ default:
++ /* Add a case to switch */
++ BREAK_TO_DEBUGGER();
++ return false;
++ }
++}
++
++bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
++{
++ if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
++ return true;
++ if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
++ return true;
++ return false;
++}
++
++bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
++{
++ if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
++ return true;
++ if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
++ return true;
++ return false;
++}
++
++bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
++{
++ if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
++ return true;
++ if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
++ return true;
++ if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
++ return true;
++ return false;
++}
++
++void build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
++ const struct dc_plane_state *plane_state)
++{
++ if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
++ && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
++ && plane_state->input_csc_color_matrix.enable_adjustment
++ && plane_state->coeff_reduction_factor.value != 0) {
++ bias_and_scale->scale_blue = fixed_point_to_int_frac(
++ dc_fixpt_mul(plane_state->coeff_reduction_factor,
++ dc_fixpt_from_fraction(256, 255)),
++ 2,
++ 13);
++ bias_and_scale->scale_red = bias_and_scale->scale_blue;
++ bias_and_scale->scale_green = bias_and_scale->scale_blue;
++ } else {
++ bias_and_scale->scale_blue = 0x2000;
++ bias_and_scale->scale_red = 0x2000;
++ bias_and_scale->scale_green = 0x2000;
++ }
++}
++
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+new file mode 100644
+index 000000000000..7c0cbf47e8ce
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DAL_DC_COMMON_H__
++#define __DAL_DC_COMMON_H__
++
++#include "core_types.h"
++
++bool is_rgb_cspace(enum dc_color_space output_color_space);
++
++bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
++
++bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
++
++bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
++
++void build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
++ const struct dc_plane_state *plane_state);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 121465bf223f..562a24f4553f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1968,11 +1968,11 @@ static void commit_planes_do_stream_update(struct dc *dc,
+
+ if (stream_update->periodic_interrupt0 &&
+ dc->hwss.setup_periodic_interrupt)
+- dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
++ dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
+
+ if (stream_update->periodic_interrupt1 &&
+ dc->hwss.setup_periodic_interrupt)
+- dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
++ dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
+
+ if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
+ stream_update->vrr_infopacket ||
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 59eaa5c172a9..9029786c7b08 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -24,6 +24,7 @@
+ */
+
+ #include "dm_services.h"
++#include "basics/dc_common.h"
+ #include "dc.h"
+ #include "core_types.h"
+ #include "resource.h"
+@@ -241,7 +242,7 @@ static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
+ if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
+ ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
+
+- vupdate_line = get_vupdate_offset_from_vsync(pipe_ctx);
++ vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+ if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
+ return;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 01fefe19ee92..6291f803cd16 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -58,6 +58,8 @@
+
+ #include "atomfirmware.h"
+
++#define GAMMA_HW_POINTS_NUM 256
++
+ /*
+ * All values are in milliseconds;
+ * For eDP, after power-up/power/down,
+@@ -265,7 +267,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
+ }
+
+ static bool
+-dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
++dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ const struct dc_plane_state *plane_state)
+ {
+ struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
+@@ -593,7 +595,7 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
+ }
+
+ static bool
+-dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
++dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ const struct dc_stream_state *stream)
+ {
+ struct transform *xfm = pipe_ctx->plane_res.xfm;
+@@ -1355,7 +1357,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
+
+ if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++ dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
+@@ -2498,10 +2500,10 @@ static void dce110_program_front_end_for_pipe(
+ if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+- dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
++ dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+- dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++ dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+
+ DC_LOG_SURFACE(
+ "Pipe:%d %p: addr hi:0x%x, "
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index 2f9b7dbdf415..c639e1680b7b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -28,7 +28,6 @@
+
+ #include "core_types.h"
+
+-#define GAMMA_HW_POINTS_NUM 256
+ struct dc;
+ struct dc_state;
+ struct dm_pp_display_configuration;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+index 032f872be89c..62ad1a11bff9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+@@ -22,7 +22,8 @@
+ #
+ # Makefile for DCN.
+
+-DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o dcn10_hw_sequencer_debug.o \
++DCN10 = dcn10_init.o dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
++ dcn10_hw_sequencer_debug.o \
+ dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
+ dcn10_hubp.o dcn10_mpc.o \
+ dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index df59bd9185b5..08d15982f526 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -24,17 +24,18 @@
+ */
+
+ #include "dm_services.h"
++#include "basics/dc_common.h"
+ #include "core_types.h"
+ #include "resource.h"
+ #include "custom_float.h"
+ #include "dcn10_hw_sequencer.h"
+-#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10_hw_sequencer_debug.h"
+ #include "dce/dce_hwseq.h"
+ #include "abm.h"
+ #include "dmcu.h"
+ #include "dcn10_optc.h"
+-#include "dcn10/dcn10_dpp.h"
+-#include "dcn10/dcn10_mpc.h"
++#include "dcn10_dpp.h"
++#include "dcn10_mpc.h"
+ #include "timing_generator.h"
+ #include "opp.h"
+ #include "ipp.h"
+@@ -65,6 +66,8 @@
+ #define DTN_INFO_MICRO_SEC(ref_cycle) \
+ print_microsec(dc_ctx, log_ctx, ref_cycle)
+
++#define GAMMA_HW_POINTS_NUM 256
++
+ void print_microsec(struct dc_context *dc_ctx,
+ struct dc_log_buffer_ctx *log_ctx,
+ uint32_t ref_cycle)
+@@ -78,6 +81,33 @@ void print_microsec(struct dc_context *dc_ctx,
+ us_x10 % frac);
+ }
+
++static void dcn10_lock_all_pipes(struct dc *dc,
++ struct dc_state *context,
++ bool lock)
++{
++ struct pipe_ctx *pipe_ctx;
++ struct timing_generator *tg;
++ int i;
++
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
++ pipe_ctx = &context->res_ctx.pipe_ctx[i];
++ tg = pipe_ctx->stream_res.tg;
++ /*
++ * Only lock the top pipe's tg to prevent redundant
++ * (un)locking. Also skip if pipe is disabled.
++ */
++ if (pipe_ctx->top_pipe ||
++ !pipe_ctx->stream || !pipe_ctx->plane_state ||
++ !tg->funcs->is_tg_enabled(tg))
++ continue;
++
++ if (lock)
++ tg->funcs->lock(tg);
++ else
++ tg->funcs->unlock(tg);
++ }
++}
++
+ static void log_mpc_crc(struct dc *dc,
+ struct dc_log_buffer_ctx *log_ctx)
+ {
+@@ -444,7 +474,7 @@ bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ return false;
+ }
+
+-static void dcn10_enable_power_gating_plane(
++void dcn10_enable_power_gating_plane(
+ struct dce_hwseq *hws,
+ bool enable)
+ {
+@@ -466,7 +496,7 @@ static void dcn10_enable_power_gating_plane(
+ REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
+ }
+
+-static void dcn10_disable_vga(
++void dcn10_disable_vga(
+ struct dce_hwseq *hws)
+ {
+ unsigned int in_vga1_mode = 0;
+@@ -499,7 +529,7 @@ static void dcn10_disable_vga(
+ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
+ }
+
+-static void dcn10_dpp_pg_control(
++void dcn10_dpp_pg_control(
+ struct dce_hwseq *hws,
+ unsigned int dpp_inst,
+ bool power_on)
+@@ -551,7 +581,7 @@ static void dcn10_dpp_pg_control(
+ }
+ }
+
+-static void dcn10_hubp_pg_control(
++void dcn10_hubp_pg_control(
+ struct dce_hwseq *hws,
+ unsigned int hubp_inst,
+ bool power_on)
+@@ -670,7 +700,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ hws->wa_state.DEGVIDCN10_253_applied = true;
+ }
+
+-static void dcn10_bios_golden_init(struct dc *dc)
++void dcn10_bios_golden_init(struct dc *dc)
+ {
+ struct dc_bios *bp = dc->ctx->dc_bios;
+ int i;
+@@ -738,7 +768,7 @@ static void false_optc_underflow_wa(
+ tg->funcs->clear_optc_underflow(tg);
+ }
+
+-static enum dc_status dcn10_enable_stream_timing(
++enum dc_status dcn10_enable_stream_timing(
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context,
+ struct dc *dc)
+@@ -984,7 +1014,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)
+ }
+
+ /* trigger HW to start disconnect plane from stream on the next vsync */
+-void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ int dpp_id = pipe_ctx->plane_res.dpp->inst;
+@@ -1010,10 +1040,10 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ hubp->funcs->hubp_disconnect(hubp);
+
+ if (dc->debug.sanity_checks)
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+
+-static void dcn10_plane_atomic_power_down(struct dc *dc,
++void dcn10_plane_atomic_power_down(struct dc *dc,
+ struct dpp *dpp,
+ struct hubp *hubp)
+ {
+@@ -1036,7 +1066,7 @@ static void dcn10_plane_atomic_power_down(struct dc *dc,
+ /* disable HW used by plane.
+ * note: cannot disable until disconnect is complete
+ */
+-static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+@@ -1068,7 +1098,7 @@ static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ pipe_ctx->plane_state = NULL;
+ }
+
+-static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+@@ -1083,7 +1113,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ pipe_ctx->pipe_idx);
+ }
+
+-static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
++void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ {
+ int i;
+ bool can_apply_seamless_boot = false;
+@@ -1182,7 +1212,7 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ }
+ }
+
+-static void dcn10_init_hw(struct dc *dc)
++void dcn10_init_hw(struct dc *dc)
+ {
+ int i;
+ struct abm *abm = dc->res_pool->abm;
+@@ -1314,7 +1344,7 @@ static void dcn10_init_hw(struct dc *dc)
+
+ }
+
+-static void dcn10_reset_hw_ctx_wrap(
++void dcn10_reset_hw_ctx_wrap(
+ struct dc *dc,
+ struct dc_state *context)
+ {
+@@ -1371,9 +1401,7 @@ static bool patch_address_for_sbs_tb_stereo(
+ return false;
+ }
+
+-
+-
+-static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ bool addr_patched = false;
+ PHYSICAL_ADDRESS_LOC addr;
+@@ -1398,8 +1426,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c
+ pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
+ }
+
+-static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+- const struct dc_plane_state *plane_state)
++bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++ const struct dc_plane_state *plane_state)
+ {
+ struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+ const struct dc_transfer_func *tf = NULL;
+@@ -1475,9 +1503,8 @@ static void log_tf(struct dc_context *ctx,
+ }
+ }
+
+-static bool
+-dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+- const struct dc_stream_state *stream)
++bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++ const struct dc_stream_state *stream)
+ {
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+
+@@ -1513,7 +1540,7 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ return true;
+ }
+
+-static void dcn10_pipe_control_lock(
++void dcn10_pipe_control_lock(
+ struct dc *dc,
+ struct pipe_ctx *pipe,
+ bool lock)
+@@ -1525,7 +1552,7 @@ static void dcn10_pipe_control_lock(
+ return;
+
+ if (dc->debug.sanity_checks)
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+
+ if (lock)
+ pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
+@@ -1533,7 +1560,7 @@ static void dcn10_pipe_control_lock(
+ pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
+
+ if (dc->debug.sanity_checks)
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+
+ static bool wait_for_reset_trigger_to_occur(
+@@ -1573,7 +1600,7 @@ static bool wait_for_reset_trigger_to_occur(
+ return rc;
+ }
+
+-static void dcn10_enable_timing_synchronization(
++void dcn10_enable_timing_synchronization(
+ struct dc *dc,
+ int group_index,
+ int group_size,
+@@ -1603,7 +1630,7 @@ static void dcn10_enable_timing_synchronization(
+ DC_SYNC_INFO("Sync complete\n");
+ }
+
+-static void dcn10_enable_per_frame_crtc_position_reset(
++void dcn10_enable_per_frame_crtc_position_reset(
+ struct dc *dc,
+ int group_size,
+ struct pipe_ctx *grouped_pipes[])
+@@ -1841,7 +1868,7 @@ static void dcn10_enable_plane(
+ struct dce_hwseq *hws = dc->hwseq;
+
+ if (dc->debug.sanity_checks) {
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+
+ undo_DEGVIDCN10_253_wa(dc);
+@@ -1898,11 +1925,11 @@ static void dcn10_enable_plane(
+ dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
+
+ if (dc->debug.sanity_checks) {
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+ }
+
+-static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
++void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
+ {
+ int i = 0;
+ struct dpp_grph_csc_adjustment adjust;
+@@ -1950,7 +1977,7 @@ static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint
+ matrix[11] = rgb_bias;
+ }
+
+-static void dcn10_program_output_csc(struct dc *dc,
++void dcn10_program_output_csc(struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ enum dc_color_space colorspace,
+ uint16_t *matrix,
+@@ -1982,57 +2009,6 @@ static void dcn10_program_output_csc(struct dc *dc,
+ }
+ }
+
+-bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+-{
+- if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
+- return true;
+- if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+- return true;
+- return false;
+-}
+-
+-bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+-{
+- if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
+- return true;
+- if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+- return true;
+- return false;
+-}
+-
+-bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+-{
+- if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
+- return true;
+- if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+- return true;
+- if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+- return true;
+- return false;
+-}
+-
+-bool is_rgb_cspace(enum dc_color_space output_color_space)
+-{
+- switch (output_color_space) {
+- case COLOR_SPACE_SRGB:
+- case COLOR_SPACE_SRGB_LIMITED:
+- case COLOR_SPACE_2020_RGB_FULLRANGE:
+- case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+- case COLOR_SPACE_ADOBERGB:
+- return true;
+- case COLOR_SPACE_YCBCR601:
+- case COLOR_SPACE_YCBCR709:
+- case COLOR_SPACE_YCBCR601_LIMITED:
+- case COLOR_SPACE_YCBCR709_LIMITED:
+- case COLOR_SPACE_2020_YCBCR:
+- return false;
+- default:
+- /* Add a case to switch */
+- BREAK_TO_DEBUGGER();
+- return false;
+- }
+-}
+-
+ void dcn10_get_surface_visual_confirm_color(
+ const struct pipe_ctx *pipe_ctx,
+ struct tg_color *color)
+@@ -2106,70 +2082,7 @@ void dcn10_get_hdr_visual_confirm_color(
+ }
+ }
+
+-static uint16_t fixed_point_to_int_frac(
+- struct fixed31_32 arg,
+- uint8_t integer_bits,
+- uint8_t fractional_bits)
+-{
+- int32_t numerator;
+- int32_t divisor = 1 << fractional_bits;
+-
+- uint16_t result;
+-
+- uint16_t d = (uint16_t)dc_fixpt_floor(
+- dc_fixpt_abs(
+- arg));
+-
+- if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
+- numerator = (uint16_t)dc_fixpt_floor(
+- dc_fixpt_mul_int(
+- arg,
+- divisor));
+- else {
+- numerator = dc_fixpt_floor(
+- dc_fixpt_sub(
+- dc_fixpt_from_int(
+- 1LL << integer_bits),
+- dc_fixpt_recip(
+- dc_fixpt_from_int(
+- divisor))));
+- }
+-
+- if (numerator >= 0)
+- result = (uint16_t)numerator;
+- else
+- result = (uint16_t)(
+- (1 << (integer_bits + fractional_bits + 1)) + numerator);
+-
+- if ((result != 0) && dc_fixpt_lt(
+- arg, dc_fixpt_zero))
+- result |= 1 << (integer_bits + fractional_bits);
+-
+- return result;
+-}
+-
+-void dcn10_build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
+- const struct dc_plane_state *plane_state)
+-{
+- if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
+- && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
+- && plane_state->input_csc_color_matrix.enable_adjustment
+- && plane_state->coeff_reduction_factor.value != 0) {
+- bias_and_scale->scale_blue = fixed_point_to_int_frac(
+- dc_fixpt_mul(plane_state->coeff_reduction_factor,
+- dc_fixpt_from_fraction(256, 255)),
+- 2,
+- 13);
+- bias_and_scale->scale_red = bias_and_scale->scale_blue;
+- bias_and_scale->scale_green = bias_and_scale->scale_blue;
+- } else {
+- bias_and_scale->scale_blue = 0x2000;
+- bias_and_scale->scale_red = 0x2000;
+- bias_and_scale->scale_green = 0x2000;
+- }
+-}
+-
+-static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
++static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
+ {
+ struct dc_bias_and_scale bns_params = {0};
+
+@@ -2182,12 +2095,12 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
+ NULL);
+
+ //set scale and bias registers
+- dcn10_build_prescale_params(&bns_params, plane_state);
++ build_prescale_params(&bns_params, plane_state);
+ if (dpp->funcs->dpp_program_bias_and_scale)
+ dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
+ }
+
+-static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct mpcc_blnd_cfg blnd_cfg = {{0}};
+@@ -2198,10 +2111,10 @@ static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
+
+ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+- dcn10_get_hdr_visual_confirm_color(
++ dc->hwss.get_hdr_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+- dcn10_get_surface_visual_confirm_color(
++ dc->hwss.get_surface_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else {
+ color_space_to_black_color(
+@@ -2283,7 +2196,7 @@ static void update_scaler(struct pipe_ctx *pipe_ctx)
+ pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
+ }
+
+-void update_dchubp_dpp(
++static void dcn10_update_dchubp_dpp(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context)
+@@ -2341,7 +2254,7 @@ void update_dchubp_dpp(
+
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.bpp_change)
+- update_dpp(dpp, plane_state);
++ dcn10_update_dpp(dpp, plane_state);
+
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.per_pixel_alpha_change ||
+@@ -2412,7 +2325,7 @@ void update_dchubp_dpp(
+ hubp->funcs->set_blank(hubp, false);
+ }
+
+-static void dcn10_blank_pixel_data(
++void dcn10_blank_pixel_data(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ bool blank)
+@@ -2455,7 +2368,7 @@ static void dcn10_blank_pixel_data(
+ }
+ }
+
+-void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
++void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
+ {
+ struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
+ uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
+@@ -2485,14 +2398,14 @@ void dcn10_program_pipe(
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ dcn10_enable_plane(dc, pipe_ctx, context);
+
+- update_dchubp_dpp(dc, pipe_ctx, context);
++ dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
+
+- set_hdr_multiplier(pipe_ctx);
++ dc->hwss.set_hdr_multiplier(pipe_ctx);
+
+ if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+- dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
++ dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+
+ /* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ * only do gamma programming for full update.
+@@ -2501,10 +2414,10 @@ void dcn10_program_pipe(
+ * doing heavy calculation and programming
+ */
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+- dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++ dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ }
+
+-static void program_all_pipe_in_tree(
++static void dcn10_program_all_pipe_in_tree(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context)
+@@ -2523,19 +2436,19 @@ static void program_all_pipe_in_tree(
+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+ if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++ dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+
+ dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+ }
+
+ if (pipe_ctx->plane_state != NULL)
+- dcn10_program_pipe(dc, pipe_ctx, context);
++ dc->hwss.program_pipe(dc, pipe_ctx, context);
+
+ if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
+- program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
++ dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+ }
+
+-struct pipe_ctx *find_top_pipe_for_stream(
++static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
+ struct dc *dc,
+ struct dc_state *context,
+ const struct dc_stream_state *stream)
+@@ -2559,7 +2472,7 @@ struct pipe_ctx *find_top_pipe_for_stream(
+ return NULL;
+ }
+
+-static void dcn10_apply_ctx_for_surface(
++void dcn10_apply_ctx_for_surface(
+ struct dc *dc,
+ const struct dc_stream_state *stream,
+ int num_planes,
+@@ -2571,7 +2484,7 @@ static void dcn10_apply_ctx_for_surface(
+ bool removed_pipe[4] = { false };
+ bool interdependent_update = false;
+ struct pipe_ctx *top_pipe_to_program =
+- find_top_pipe_for_stream(dc, context, stream);
++ dcn10_find_top_pipe_for_stream(dc, context, stream);
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ if (!top_pipe_to_program)
+@@ -2588,7 +2501,7 @@ static void dcn10_apply_ctx_for_surface(
+ ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
+
+ if (interdependent_update)
+- lock_all_pipes(dc, context, true);
++ dcn10_lock_all_pipes(dc, context, true);
+ else
+ dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
+
+@@ -2635,7 +2548,7 @@ static void dcn10_apply_ctx_for_surface(
+ }
+
+ if (num_planes > 0)
+- program_all_pipe_in_tree(dc, top_pipe_to_program, context);
++ dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+
+ /* Program secondary blending tree and writeback pipes */
+ if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
+@@ -2655,7 +2568,7 @@ static void dcn10_apply_ctx_for_surface(
+ }
+
+ if (interdependent_update)
+- lock_all_pipes(dc, context, false);
++ dcn10_lock_all_pipes(dc, context, false);
+ else
+ dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
+
+@@ -2692,14 +2605,14 @@ static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *contex
+ }
+ }
+
+-static void dcn10_prepare_bandwidth(
++void dcn10_prepare_bandwidth(
+ struct dc *dc,
+ struct dc_state *context)
+ {
+ struct hubbub *hubbub = dc->res_pool->hubbub;
+
+ if (dc->debug.sanity_checks)
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (context->stream_count == 0)
+@@ -2721,17 +2634,17 @@ static void dcn10_prepare_bandwidth(
+ dcn_bw_notify_pplib_of_wm_ranges(dc);
+
+ if (dc->debug.sanity_checks)
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+
+-static void dcn10_optimize_bandwidth(
++void dcn10_optimize_bandwidth(
+ struct dc *dc,
+ struct dc_state *context)
+ {
+ struct hubbub *hubbub = dc->res_pool->hubbub;
+
+ if (dc->debug.sanity_checks)
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (context->stream_count == 0)
+@@ -2753,10 +2666,10 @@ static void dcn10_optimize_bandwidth(
+ dcn_bw_notify_pplib_of_wm_ranges(dc);
+
+ if (dc->debug.sanity_checks)
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+
+-static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
++void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ int num_pipes, unsigned int vmin, unsigned int vmax,
+ unsigned int vmid, unsigned int vmid_frame_number)
+ {
+@@ -2784,7 +2697,7 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ }
+ }
+
+-static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
++void dcn10_get_position(struct pipe_ctx **pipe_ctx,
+ int num_pipes,
+ struct crtc_position *position)
+ {
+@@ -2796,7 +2709,7 @@ static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
+ pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
+ }
+
+-static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
++void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ int num_pipes, const struct dc_static_screen_events *events)
+ {
+ unsigned int i;
+@@ -2851,7 +2764,7 @@ static void dcn10_config_stereo_parameters(
+ return;
+ }
+
+-static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
++void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
+ {
+ struct crtc_stereo_flags flags = { 0 };
+ struct dc_stream_state *stream = pipe_ctx->stream;
+@@ -2890,7 +2803,7 @@ static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_in
+ return NULL;
+ }
+
+-static void dcn10_wait_for_mpcc_disconnect(
++void dcn10_wait_for_mpcc_disconnect(
+ struct dc *dc,
+ struct resource_pool *res_pool,
+ struct pipe_ctx *pipe_ctx)
+@@ -2898,7 +2811,7 @@ static void dcn10_wait_for_mpcc_disconnect(
+ int mpcc_inst;
+
+ if (dc->debug.sanity_checks) {
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+
+ if (!pipe_ctx->stream_res.opp)
+@@ -2915,12 +2828,12 @@ static void dcn10_wait_for_mpcc_disconnect(
+ }
+
+ if (dc->debug.sanity_checks) {
+- dcn10_verify_allow_pstate_change_high(dc);
++ dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+
+ }
+
+-static bool dcn10_dummy_display_power_gating(
++bool dcn10_dummy_display_power_gating(
+ struct dc *dc,
+ uint8_t controller_id,
+ struct dc_bios *dcb,
+@@ -2929,7 +2842,7 @@ static bool dcn10_dummy_display_power_gating(
+ return true;
+ }
+
+-static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
++void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
+ {
+ struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
+@@ -2953,7 +2866,7 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
+ }
+ }
+
+-static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
++void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
+ {
+ struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
+
+@@ -2961,7 +2874,7 @@ static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh
+ hubbub->funcs->update_dchub(hubbub, dh_data);
+ }
+
+-static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
++void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+ {
+ struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+@@ -3027,7 +2940,7 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+ dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
+ }
+
+-static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
++void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+ {
+ struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+
+@@ -3037,7 +2950,7 @@ static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+ pipe_ctx->plane_res.dpp, attributes);
+ }
+
+-static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
++void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
+ {
+ uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
+ struct fixed31_32 multiplier;
+@@ -3064,12 +2977,12 @@ static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
+ pipe_ctx->plane_res.dpp, &opt_attr);
+ }
+
+-/**
+-* apply_front_porch_workaround TODO FPGA still need?
+-*
+-* This is a workaround for a bug that has existed since R5xx and has not been
+-* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
+-*/
++/*
++ * apply_front_porch_workaround TODO FPGA still need?
++ *
++ * This is a workaround for a bug that has existed since R5xx and has not been
++ * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
++ */
+ static void apply_front_porch_workaround(
+ struct dc_crtc_timing *timing)
+ {
+@@ -3082,7 +2995,7 @@ static void apply_front_porch_workaround(
+ }
+ }
+
+-int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
++int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
+ {
+ const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
+ struct dc_crtc_timing patched_crtc_timing;
+@@ -3111,34 +3024,8 @@ int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
+ return vertical_line_start;
+ }
+
+-void lock_all_pipes(struct dc *dc,
+- struct dc_state *context,
+- bool lock)
+-{
+- struct pipe_ctx *pipe_ctx;
+- struct timing_generator *tg;
+- int i;
+-
+- for (i = 0; i < dc->res_pool->pipe_count; i++) {
+- pipe_ctx = &context->res_ctx.pipe_ctx[i];
+- tg = pipe_ctx->stream_res.tg;
+- /*
+- * Only lock the top pipe's tg to prevent redundant
+- * (un)locking. Also skip if pipe is disabled.
+- */
+- if (pipe_ctx->top_pipe ||
+- !pipe_ctx->stream || !pipe_ctx->plane_state ||
+- !tg->funcs->is_tg_enabled(tg))
+- continue;
+-
+- if (lock)
+- tg->funcs->lock(tg);
+- else
+- tg->funcs->unlock(tg);
+- }
+-}
+-
+-static void calc_vupdate_position(
++static void dcn10_calc_vupdate_position(
++ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ uint32_t *start_line,
+ uint32_t *end_line)
+@@ -3146,7 +3033,7 @@ static void calc_vupdate_position(
+ const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
+ int vline_int_offset_from_vupdate =
+ pipe_ctx->stream->periodic_interrupt0.lines_offset;
+- int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
++ int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+ int start_position;
+
+ if (vline_int_offset_from_vupdate > 0)
+@@ -3167,7 +3054,8 @@ static void calc_vupdate_position(
+ *end_line = 2;
+ }
+
+-static void cal_vline_position(
++static void dcn10_cal_vline_position(
++ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ enum vline_select vline,
+ uint32_t *start_line,
+@@ -3182,7 +3070,8 @@ static void cal_vline_position(
+
+ switch (ref_point) {
+ case START_V_UPDATE:
+- calc_vupdate_position(
++ dcn10_calc_vupdate_position(
++ dc,
+ pipe_ctx,
+ start_line,
+ end_line);
+@@ -3196,7 +3085,8 @@ static void cal_vline_position(
+ }
+ }
+
+-static void dcn10_setup_periodic_interrupt(
++void dcn10_setup_periodic_interrupt(
++ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ enum vline_select vline)
+ {
+@@ -3206,7 +3096,7 @@ static void dcn10_setup_periodic_interrupt(
+ uint32_t start_line = 0;
+ uint32_t end_line = 0;
+
+- cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
++ dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line);
+
+ tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
+
+@@ -3217,10 +3107,10 @@ static void dcn10_setup_periodic_interrupt(
+ }
+ }
+
+-static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
++void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
+- int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
++ int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+
+ if (start_line < 0) {
+ ASSERT(0);
+@@ -3231,7 +3121,7 @@ static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
+ tg->funcs->setup_vertical_interrupt2(tg, start_line);
+ }
+
+-static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
++void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ struct dc_link_settings *link_settings)
+ {
+ struct encoder_unblank_param params = { { 0 } };
+@@ -3254,7 +3144,7 @@ static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ }
+ }
+
+-static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
++void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
+ const uint8_t *custom_sdp_message,
+ unsigned int sdp_message_size)
+ {
+@@ -3265,7 +3155,7 @@ static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
+ sdp_message_size);
+ }
+ }
+-static enum dc_status dcn10_set_clock(struct dc *dc,
++enum dc_status dcn10_set_clock(struct dc *dc,
+ enum dc_clock_type clock_type,
+ uint32_t clk_khz,
+ uint32_t stepping)
+@@ -3305,7 +3195,7 @@ static enum dc_status dcn10_set_clock(struct dc *dc,
+
+ }
+
+-static void dcn10_get_clock(struct dc *dc,
++void dcn10_get_clock(struct dc *dc,
+ enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg)
+ {
+@@ -3315,77 +3205,3 @@ static void dcn10_get_clock(struct dc *dc,
+ dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
+
+ }
+-
+-static const struct hw_sequencer_funcs dcn10_funcs = {
+- .program_gamut_remap = dcn10_program_gamut_remap,
+- .init_hw = dcn10_init_hw,
+- .init_pipes = dcn10_init_pipes,
+- .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+- .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+- .update_plane_addr = dcn10_update_plane_addr,
+- .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
+- .update_dchub = dcn10_update_dchub,
+- .update_mpcc = dcn10_update_mpcc,
+- .update_pending_status = dcn10_update_pending_status,
+- .set_input_transfer_func = dcn10_set_input_transfer_func,
+- .set_output_transfer_func = dcn10_set_output_transfer_func,
+- .program_output_csc = dcn10_program_output_csc,
+- .power_down = dce110_power_down,
+- .enable_accelerated_mode = dce110_enable_accelerated_mode,
+- .enable_timing_synchronization = dcn10_enable_timing_synchronization,
+- .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+- .update_info_frame = dce110_update_info_frame,
+- .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+- .enable_stream = dce110_enable_stream,
+- .disable_stream = dce110_disable_stream,
+- .unblank_stream = dcn10_unblank_stream,
+- .blank_stream = dce110_blank_stream,
+- .enable_audio_stream = dce110_enable_audio_stream,
+- .disable_audio_stream = dce110_disable_audio_stream,
+- .enable_display_power_gating = dcn10_dummy_display_power_gating,
+- .disable_plane = dcn10_disable_plane,
+- .blank_pixel_data = dcn10_blank_pixel_data,
+- .pipe_control_lock = dcn10_pipe_control_lock,
+- .prepare_bandwidth = dcn10_prepare_bandwidth,
+- .optimize_bandwidth = dcn10_optimize_bandwidth,
+- .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
+- .enable_stream_timing = dcn10_enable_stream_timing,
+- .set_drr = dcn10_set_drr,
+- .get_position = dcn10_get_position,
+- .set_static_screen_control = dcn10_set_static_screen_control,
+- .setup_stereo = dcn10_setup_stereo,
+- .set_avmute = dce110_set_avmute,
+- .log_hw_state = dcn10_log_hw_state,
+- .get_hw_state = dcn10_get_hw_state,
+- .clear_status_bits = dcn10_clear_status_bits,
+- .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+- .edp_backlight_control = dce110_edp_backlight_control,
+- .edp_power_control = dce110_edp_power_control,
+- .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+- .set_cursor_position = dcn10_set_cursor_position,
+- .set_cursor_attribute = dcn10_set_cursor_attribute,
+- .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+- .disable_stream_gating = NULL,
+- .enable_stream_gating = NULL,
+- .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+- .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+- .set_clock = dcn10_set_clock,
+- .get_clock = dcn10_get_clock,
+- .did_underflow_occur = dcn10_did_underflow_occur,
+- .init_blank = NULL,
+- .disable_vga = dcn10_disable_vga,
+- .bios_golden_init = dcn10_bios_golden_init,
+- .plane_atomic_disable = dcn10_plane_atomic_disable,
+- .plane_atomic_power_down = dcn10_plane_atomic_power_down,
+- .enable_power_gating_plane = dcn10_enable_power_gating_plane,
+- .dpp_pg_control = dcn10_dpp_pg_control,
+- .hubp_pg_control = dcn10_hubp_pg_control,
+- .dsc_pg_control = NULL,
+-};
+-
+-
+-void dcn10_hw_sequencer_construct(struct dc *dc)
+-{
+- dc->hwss = dcn10_funcs;
+-}
+-
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+index d3616b1948cc..5aad3922be6c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+@@ -31,64 +31,155 @@
+ struct dc;
+
+ void dcn10_hw_sequencer_construct(struct dc *dc);
+-extern void fill_display_configs(
+- const struct dc_state *context,
+- struct dm_pp_display_configuration *pp_display_cfg);
+-
+-bool is_rgb_cspace(enum dc_color_space output_color_space);
+-
+-void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-void dcn10_verify_allow_pstate_change_high(struct dc *dc);
+
++int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
++void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
++enum dc_status dcn10_enable_stream_timing(
++ struct pipe_ctx *pipe_ctx,
++ struct dc_state *context,
++ struct dc *dc);
++void dcn10_optimize_bandwidth(
++ struct dc *dc,
++ struct dc_state *context);
++void dcn10_prepare_bandwidth(
++ struct dc *dc,
++ struct dc_state *context);
++void dcn10_pipe_control_lock(
++ struct dc *dc,
++ struct pipe_ctx *pipe,
++ bool lock);
++void dcn10_blank_pixel_data(
++ struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ bool blank);
++void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
++ struct dc_link_settings *link_settings);
++void dcn10_program_output_csc(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ enum dc_color_space colorspace,
++ uint16_t *matrix,
++ int opp_id);
++bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++ const struct dc_stream_state *stream);
++bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++ const struct dc_plane_state *plane_state);
++void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_reset_hw_ctx_wrap(
++ struct dc *dc,
++ struct dc_state *context);
++void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_apply_ctx_for_surface(
++ struct dc *dc,
++ const struct dc_stream_state *stream,
++ int num_planes,
++ struct dc_state *context);
++void dcn10_hubp_pg_control(
++ struct dce_hwseq *hws,
++ unsigned int hubp_inst,
++ bool power_on);
++void dcn10_dpp_pg_control(
++ struct dce_hwseq *hws,
++ unsigned int dpp_inst,
++ bool power_on);
++void dcn10_enable_power_gating_plane(
++ struct dce_hwseq *hws,
++ bool enable);
++void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_disable_vga(
++ struct dce_hwseq *hws);
+ void dcn10_program_pipe(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context);
+-
+-void dcn10_get_hw_state(
++void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
++void dcn10_init_hw(struct dc *dc);
++void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
++enum dc_status dce110_apply_ctx_to_hw(
++ struct dc *dc,
++ struct dc_state *context);
++void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
++void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);
++void dce110_power_down(struct dc *dc);
++void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
++void dcn10_enable_timing_synchronization(
++ struct dc *dc,
++ int group_index,
++ int group_size,
++ struct pipe_ctx *grouped_pipes[]);
++void dcn10_enable_per_frame_crtc_position_reset(
++ struct dc *dc,
++ int group_size,
++ struct pipe_ctx *grouped_pipes[]);
++void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
++void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
++ const uint8_t *custom_sdp_message,
++ unsigned int sdp_message_size);
++void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
++void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
++void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
++bool dcn10_dummy_display_power_gating(
+ struct dc *dc,
+- char *pBuf, unsigned int bufSize,
++ uint8_t controller_id,
++ struct dc_bios *dcb,
++ enum pipe_gating_control power_gating);
++void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
++ int num_pipes, unsigned int vmin, unsigned int vmax,
++ unsigned int vmid, unsigned int vmid_frame_number);
++void dcn10_get_position(struct pipe_ctx **pipe_ctx,
++ int num_pipes,
++ struct crtc_position *position);
++void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
++ int num_pipes, const struct dc_static_screen_events *events);
++void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
++void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
++void dcn10_log_hw_state(struct dc *dc,
++ struct dc_log_buffer_ctx *log_ctx);
++void dcn10_get_hw_state(struct dc *dc,
++ char *pBuf,
++ unsigned int bufSize,
+ unsigned int mask);
+-
+ void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
+-
+-bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+-
+-bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+-
+-bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+-
+-void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp);
+-
+-void set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
+-
++void dcn10_wait_for_mpcc_disconnect(
++ struct dc *dc,
++ struct resource_pool *res_pool,
++ struct pipe_ctx *pipe_ctx);
++void dce110_edp_backlight_control(
++ struct dc_link *link,
++ bool enable);
++void dce110_edp_power_control(
++ struct dc_link *link,
++ bool power_up);
++void dce110_edp_wait_for_hpd_ready(
++ struct dc_link *link,
++ bool power_up);
++void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);
++void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
++void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
++void dcn10_setup_periodic_interrupt(
++ struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ enum vline_select vline);
++enum dc_status dcn10_set_clock(struct dc *dc,
++ enum dc_clock_type clock_type,
++ uint32_t clk_khz,
++ uint32_t stepping);
++void dcn10_get_clock(struct dc *dc,
++ enum dc_clock_type clock_type,
++ struct dc_clock_config *clock_cfg);
++bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_bios_golden_init(struct dc *dc);
++void dcn10_plane_atomic_power_down(struct dc *dc,
++ struct dpp *dpp,
++ struct hubp *hubp);
+ void dcn10_get_surface_visual_confirm_color(
+ const struct pipe_ctx *pipe_ctx,
+ struct tg_color *color);
+-
+ void dcn10_get_hdr_visual_confirm_color(
+ struct pipe_ctx *pipe_ctx,
+ struct tg_color *color);
+-
+-bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-void update_dchubp_dpp(
+- struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- struct dc_state *context);
+-
+-struct pipe_ctx *find_top_pipe_for_stream(
+- struct dc *dc,
+- struct dc_state *context,
+- const struct dc_stream_state *stream);
+-
+-int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
+-
+-void dcn10_build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
+- const struct dc_plane_state *plane_state);
+-void lock_all_pipes(struct dc *dc,
+- struct dc_state *context,
+- bool lock);
++void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
++void dcn10_verify_allow_pstate_change_high(struct dc *dc);
+
+ #endif /* __DC_HWSS_DCN10_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h
+new file mode 100644
+index 000000000000..596f95c22e85
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h
+@@ -0,0 +1,43 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_HWSS_DCN10_DEBUG_H__
++#define __DC_HWSS_DCN10_DEBUG_H__
++
++#include "core_types.h"
++
++struct dc;
++
++void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
++
++void dcn10_log_hw_state(struct dc *dc,
++ struct dc_log_buffer_ctx *log_ctx);
++
++void dcn10_get_hw_state(struct dc *dc,
++ char *pBuf,
++ unsigned int bufSize,
++ unsigned int mask);
++
++#endif /* __DC_HWSS_DCN10_DEBUG_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+new file mode 100644
+index 000000000000..38923f3120ee
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+@@ -0,0 +1,105 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10_hw_sequencer.h"
++
++static const struct hw_sequencer_funcs dcn10_funcs = {
++ .program_gamut_remap = dcn10_program_gamut_remap,
++ .init_hw = dcn10_init_hw,
++ .init_pipes = dcn10_init_pipes,
++ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
++ .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
++ .update_plane_addr = dcn10_update_plane_addr,
++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++ .program_pipe = dcn10_program_pipe,
++ .update_dchub = dcn10_update_dchub,
++ .update_mpcc = dcn10_update_mpcc,
++ .update_pending_status = dcn10_update_pending_status,
++ .set_input_transfer_func = dcn10_set_input_transfer_func,
++ .set_output_transfer_func = dcn10_set_output_transfer_func,
++ .program_output_csc = dcn10_program_output_csc,
++ .power_down = dce110_power_down,
++ .enable_accelerated_mode = dce110_enable_accelerated_mode,
++ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
++ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
++ .update_info_frame = dce110_update_info_frame,
++ .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
++ .enable_stream = dce110_enable_stream,
++ .disable_stream = dce110_disable_stream,
++ .unblank_stream = dcn10_unblank_stream,
++ .blank_stream = dce110_blank_stream,
++ .enable_audio_stream = dce110_enable_audio_stream,
++ .disable_audio_stream = dce110_disable_audio_stream,
++ .enable_display_power_gating = dcn10_dummy_display_power_gating,
++ .disable_plane = dcn10_disable_plane,
++ .blank_pixel_data = dcn10_blank_pixel_data,
++ .pipe_control_lock = dcn10_pipe_control_lock,
++ .prepare_bandwidth = dcn10_prepare_bandwidth,
++ .optimize_bandwidth = dcn10_optimize_bandwidth,
++ .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
++ .enable_stream_timing = dcn10_enable_stream_timing,
++ .set_drr = dcn10_set_drr,
++ .get_position = dcn10_get_position,
++ .set_static_screen_control = dcn10_set_static_screen_control,
++ .setup_stereo = dcn10_setup_stereo,
++ .set_avmute = dce110_set_avmute,
++ .log_hw_state = dcn10_log_hw_state,
++ .get_hw_state = dcn10_get_hw_state,
++ .clear_status_bits = dcn10_clear_status_bits,
++ .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
++ .edp_backlight_control = dce110_edp_backlight_control,
++ .edp_power_control = dce110_edp_power_control,
++ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++ .set_cursor_position = dcn10_set_cursor_position,
++ .set_cursor_attribute = dcn10_set_cursor_attribute,
++ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++ .disable_stream_gating = NULL,
++ .enable_stream_gating = NULL,
++ .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
++ .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
++ .set_clock = dcn10_set_clock,
++ .get_clock = dcn10_get_clock,
++ .did_underflow_occur = dcn10_did_underflow_occur,
++ .init_blank = NULL,
++ .disable_vga = dcn10_disable_vga,
++ .bios_golden_init = dcn10_bios_golden_init,
++ .plane_atomic_disable = dcn10_plane_atomic_disable,
++ .plane_atomic_power_down = dcn10_plane_atomic_power_down,
++ .enable_power_gating_plane = dcn10_enable_power_gating_plane,
++ .dpp_pg_control = dcn10_dpp_pg_control,
++ .hubp_pg_control = dcn10_hubp_pg_control,
++ .dsc_pg_control = NULL,
++ .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
++ .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
++ .set_hdr_multiplier = dcn10_set_hdr_multiplier,
++ .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++void dcn10_hw_sequencer_construct(struct dc *dc)
++{
++ dc->hwss = dcn10_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h
+new file mode 100644
+index 000000000000..8c6fd7b844a4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_DCN10_INIT_H__
++#define __DC_DCN10_INIT_H__
++
++struct dc;
++
++void dcn10_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_DCN10_INIT_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index c4129e21e643..db820a0c79d6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -26,6 +26,8 @@
+ #include "dm_services.h"
+ #include "dc.h"
+
++#include "dcn10_init.h"
++
+ #include "resource.h"
+ #include "include/irq_service_interface.h"
+ #include "dcn10_resource.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index 89c581196c4c..c49ebe7a6fd9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN.
+
+-DCN20 = dcn20_resource.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
++DCN20 = dcn20_resource.o dcn20_init.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
+ dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_optc.o dcn20_mmhubbub.o \
+ dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \
+ dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index fa1ecff747a1..937ecb28948d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -25,15 +25,19 @@
+ #include <linux/delay.h>
+
+ #include "dm_services.h"
++#include "basics/dc_common.h"
+ #include "dm_helpers.h"
+ #include "core_types.h"
+ #include "resource.h"
+-#include "dcn20/dcn20_resource.h"
+-#include "dce110/dce110_hw_sequencer.h"
+-#include "dcn10/dcn10_hw_sequencer.h"
++#include "dcn20_resource.h"
+ #include "dcn20_hwseq.h"
+ #include "dce/dce_hwseq.h"
++// TODO: This may be cause problem
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dcn20/dcn20_dsc.h"
++#endif
++#include "dcn20_dsc.h"
++#include "dcn20_optc.h"
+ #include "abm.h"
+ #include "clk_mgr.h"
+ #include "dmcu.h"
+@@ -43,10 +47,9 @@
+ #include "ipp.h"
+ #include "mpc.h"
+ #include "mcif_wb.h"
++#include "dchubbub.h"
+ #include "reg_helper.h"
+ #include "dcn10/dcn10_cm_common.h"
+-#include "dcn10/dcn10_hubbub.h"
+-#include "dcn10/dcn10_optc.h"
+ #include "dc_link_dp.h"
+ #include "vm_helper.h"
+ #include "dccg.h"
+@@ -62,7 +65,125 @@
+ #define FN(reg_name, field_name) \
+ hws->shifts->field_name, hws->masks->field_name
+
+-static void dcn20_enable_power_gating_plane(
++static int find_free_gsl_group(const struct dc *dc)
++{
++ if (dc->res_pool->gsl_groups.gsl_0 == 0)
++ return 1;
++ if (dc->res_pool->gsl_groups.gsl_1 == 0)
++ return 2;
++ if (dc->res_pool->gsl_groups.gsl_2 == 0)
++ return 3;
++
++ return 0;
++}
++
++/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
++ * This is only used to lock pipes in pipe splitting case with immediate flip
++ * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
++ * so we get tearing with freesync since we cannot flip multiple pipes
++ * atomically.
++ * We use GSL for this:
++ * - immediate flip: find first available GSL group if not already assigned
++ * program gsl with that group, set current OTG as master
++ * and always us 0x4 = AND of flip_ready from all pipes
++ * - vsync flip: disable GSL if used
++ *
++ * Groups in stream_res are stored as +1 from HW registers, i.e.
++ * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
++ * Using a magic value like -1 would require tracking all inits/resets
++ */
++static void dcn20_setup_gsl_group_as_lock(
++ const struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ bool enable)
++{
++ struct gsl_params gsl;
++ int group_idx;
++
++ memset(&gsl, 0, sizeof(struct gsl_params));
++
++ if (enable) {
++ /* return if group already assigned since GSL was set up
++ * for vsync flip, we would unassign so it can't be "left over"
++ */
++ if (pipe_ctx->stream_res.gsl_group > 0)
++ return;
++
++ group_idx = find_free_gsl_group(dc);
++ ASSERT(group_idx != 0);
++ pipe_ctx->stream_res.gsl_group = group_idx;
++
++ /* set gsl group reg field and mark resource used */
++ switch (group_idx) {
++ case 1:
++ gsl.gsl0_en = 1;
++ dc->res_pool->gsl_groups.gsl_0 = 1;
++ break;
++ case 2:
++ gsl.gsl1_en = 1;
++ dc->res_pool->gsl_groups.gsl_1 = 1;
++ break;
++ case 3:
++ gsl.gsl2_en = 1;
++ dc->res_pool->gsl_groups.gsl_2 = 1;
++ break;
++ default:
++ BREAK_TO_DEBUGGER();
++ return; // invalid case
++ }
++ gsl.gsl_master_en = 1;
++ } else {
++ group_idx = pipe_ctx->stream_res.gsl_group;
++ if (group_idx == 0)
++ return; // if not in use, just return
++
++ pipe_ctx->stream_res.gsl_group = 0;
++
++ /* unset gsl group reg field and mark resource free */
++ switch (group_idx) {
++ case 1:
++ gsl.gsl0_en = 0;
++ dc->res_pool->gsl_groups.gsl_0 = 0;
++ break;
++ case 2:
++ gsl.gsl1_en = 0;
++ dc->res_pool->gsl_groups.gsl_1 = 0;
++ break;
++ case 3:
++ gsl.gsl2_en = 0;
++ dc->res_pool->gsl_groups.gsl_2 = 0;
++ break;
++ default:
++ BREAK_TO_DEBUGGER();
++ return;
++ }
++ gsl.gsl_master_en = 0;
++ }
++
++ /* at this point we want to program whether it's to enable or disable */
++ if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
++ pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
++ pipe_ctx->stream_res.tg->funcs->set_gsl(
++ pipe_ctx->stream_res.tg,
++ &gsl);
++
++ pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
++ pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
++ } else
++ BREAK_TO_DEBUGGER();
++}
++
++void dcn20_set_flip_control_gsl(
++ struct pipe_ctx *pipe_ctx,
++ bool flip_immediate)
++{
++ if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
++ pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
++ pipe_ctx->plane_res.hubp, flip_immediate);
++
++}
++
++void dcn20_enable_power_gating_plane(
+ struct dce_hwseq *hws,
+ bool enable)
+ {
+@@ -126,44 +247,6 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
+ /* This value is dependent on the hardware pipeline delay so set once per SOC */
+ REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+ }
+-void dcn20_display_init(struct dc *dc)
+-{
+- struct dce_hwseq *hws = dc->hwseq;
+-
+- /* RBBMIF
+- * disable RBBMIF timeout detection for all clients
+- * Ensure RBBMIF does not drop register accesses due to the per-client timeout
+- */
+- REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+- REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+-
+- /* DCCG */
+- dcn20_dccg_init(hws);
+-
+- REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);
+-
+- /* DCHUB/MMHUBBUB
+- * set global timer refclk divider
+- * 100Mhz refclk -> 2
+- * 27Mhz refclk -> 1
+- * 48Mhz refclk -> 1
+- */
+- REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+- REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+- REG_WRITE(REFCLK_CNTL, 0);
+-
+- /* OPTC
+- * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc
+- */
+-
+- /* AZ
+- * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser,
+- * if not, it should be programmed according to the ref clock
+- */
+- REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64);
+- /* Enable controller clock gating */
+- REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
+-}
+
+ void dcn20_disable_vga(
+ struct dce_hwseq *hws)
+@@ -176,15 +259,15 @@ void dcn20_disable_vga(
+ REG_WRITE(D6VGA_CONTROL, 0);
+ }
+
+-void dcn20_program_tripleBuffer(
++void dcn20_program_triple_buffer(
+ const struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+- bool enableTripleBuffer)
++ bool enable_triple_buffer)
+ {
+ if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
+ pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
+ pipe_ctx->plane_res.hubp,
+- enableTripleBuffer);
++ enable_triple_buffer);
+ }
+ }
+
+@@ -240,10 +323,10 @@ void dcn20_init_blank(
+ otg_active_height);
+ }
+
+- dcn20_hwss_wait_for_blank_complete(opp);
++ dc->hwss.wait_for_blank_complete(opp);
+ }
+
+-static void dcn20_dsc_pg_control(
++void dcn20_dsc_pg_control(
+ struct dce_hwseq *hws,
+ unsigned int dsc_inst,
+ bool power_on)
+@@ -320,7 +403,7 @@ static void dcn20_dsc_pg_control(
+ REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+ }
+
+-static void dcn20_dpp_pg_control(
++void dcn20_dpp_pg_control(
+ struct dce_hwseq *hws,
+ unsigned int dpp_inst,
+ bool power_on)
+@@ -394,7 +477,7 @@ static void dcn20_dpp_pg_control(
+ }
+
+
+-static void dcn20_hubp_pg_control(
++void dcn20_hubp_pg_control(
+ struct dce_hwseq *hws,
+ unsigned int hubp_inst,
+ bool power_on)
+@@ -471,7 +554,7 @@ static void dcn20_hubp_pg_control(
+ /* disable HW used by plane.
+ * note: cannot disable until disconnect is complete
+ */
+-static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+@@ -591,7 +674,7 @@ enum dc_status dcn20_enable_stream_timing(
+ return DC_ERROR_UNEXPECTED;
+ }
+
+- dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp);
++ dc->hwss.wait_for_blank_complete(pipe_ctx->stream_res.opp);
+
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
+@@ -647,7 +730,7 @@ void dcn20_program_output_csc(struct dc *dc,
+ }
+ }
+
+-bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
++bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ const struct dc_stream_state *stream)
+ {
+ int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+@@ -737,8 +820,9 @@ bool dcn20_set_shaper_3dlut(
+ return result;
+ }
+
+-bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+- const struct dc_plane_state *plane_state)
++bool dcn20_set_input_transfer_func(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ const struct dc_plane_state *plane_state)
+ {
+ struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+ const struct dc_transfer_func *tf = NULL;
+@@ -748,8 +832,8 @@ bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ if (dpp_base == NULL || plane_state == NULL)
+ return false;
+
+- dcn20_set_shaper_3dlut(pipe_ctx, plane_state);
+- dcn20_set_blend_lut(pipe_ctx, plane_state);
++ dc->hwss.set_shaper_3dlut(pipe_ctx, plane_state);
++ dc->hwss.set_blend_lut(pipe_ctx, plane_state);
+
+ if (plane_state->in_transfer_func)
+ tf = plane_state->in_transfer_func;
+@@ -814,7 +898,7 @@ bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ return result;
+ }
+
+-static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
++void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
+ {
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+@@ -1256,7 +1340,7 @@ static void dcn20_update_dchubp_dpp(
+
+ if (dpp->funcs->dpp_program_bias_and_scale) {
+ //TODO :for CNVC set scale and bias registers if necessary
+- dcn10_build_prescale_params(&bns_params, plane_state);
++ build_prescale_params(&bns_params, plane_state);
+ dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
+ }
+ }
+@@ -1380,7 +1464,7 @@ static void dcn20_program_pipe(
+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+ if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++ dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+ }
+
+ if (pipe_ctx->update_flags.bits.odm)
+@@ -1394,19 +1478,19 @@ static void dcn20_program_pipe(
+
+ if (pipe_ctx->update_flags.bits.enable
+ || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
+- set_hdr_multiplier(pipe_ctx);
++ dc->hwss.set_hdr_multiplier(pipe_ctx);
+
+ if (pipe_ctx->update_flags.bits.enable ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+- dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
++ dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+
+ /* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ * only do gamma programming for powering on, internal memcmp to avoid
+ * updating on slave planes
+ */
+ if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
+- dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++ dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+
+ /* If the pipe has been enabled or has a different opp, we
+ * should reprogram the fmt. This deals with cases where
+@@ -1440,7 +1524,7 @@ static bool does_pipe_need_lock(struct pipe_ctx *pipe)
+ return false;
+ }
+
+-static void dcn20_program_front_end_for_ctx(
++void dcn20_program_front_end_for_ctx(
+ struct dc *dc,
+ struct dc_state *context)
+ {
+@@ -1621,7 +1705,7 @@ bool dcn20_update_bandwidth(
+ dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+
+ if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++ dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+ }
+
+ pipe_ctx->plane_res.hubp->funcs->hubp_setup(
+@@ -1635,7 +1719,7 @@ bool dcn20_update_bandwidth(
+ return true;
+ }
+
+-static void dcn20_enable_writeback(
++void dcn20_enable_writeback(
+ struct dc *dc,
+ const struct dc_stream_status *stream_status,
+ struct dc_writeback_info *wb_info,
+@@ -1679,7 +1763,7 @@ void dcn20_disable_writeback(
+ mcif_wb->funcs->disable_mcif(mcif_wb);
+ }
+
+-bool dcn20_hwss_wait_for_blank_complete(
++bool dcn20_wait_for_blank_complete(
+ struct output_pixel_processor *opp)
+ {
+ int counter;
+@@ -1708,7 +1792,7 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
+ return hubp->funcs->dmdata_status_done(hubp);
+ }
+
+-static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct dce_hwseq *hws = dc->hwseq;
+
+@@ -1723,7 +1807,7 @@ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx
+ }
+ }
+
+-static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct dce_hwseq *hws = dc->hwseq;
+
+@@ -1758,12 +1842,7 @@ void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
+ hubp->funcs->dmdata_set_attributes(hubp, &attr);
+ }
+
+-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx)
+-{
+- dce110_disable_stream(pipe_ctx);
+-}
+-
+-static void dcn20_init_vm_ctx(
++void dcn20_init_vm_ctx(
+ struct dce_hwseq *hws,
+ struct dc *dc,
+ struct dc_virtual_addr_space_config *va_config,
+@@ -1785,7 +1864,7 @@ static void dcn20_init_vm_ctx(
+ dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
+ }
+
+-static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
++int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+ {
+ struct dcn_hubbub_phys_addr_config config;
+
+@@ -1829,8 +1908,7 @@ static bool patch_address_for_sbs_tb_stereo(
+ return false;
+ }
+
+-
+-static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ bool addr_patched = false;
+ PHYSICAL_ADDRESS_LOC addr;
+@@ -1876,7 +1954,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ params.link_settings.link_rate = link_settings->link_rate;
+
+ if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+- if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
++ if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
+ params.timing.pix_clk_100hz /= 2;
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
+ pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
+@@ -1888,10 +1966,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ }
+ }
+
+-void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
++void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
+- int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
++ int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+
+ if (start_line < 0)
+ start_line = 0;
+@@ -1967,7 +2045,7 @@ static void dcn20_reset_back_end_for_pipe(
+ pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
+ }
+
+-static void dcn20_reset_hw_ctx_wrap(
++void dcn20_reset_hw_ctx_wrap(
+ struct dc *dc,
+ struct dc_state *context)
+ {
+@@ -2020,7 +2098,7 @@ void dcn20_get_mpctree_visual_confirm_color(
+ *color = pipe_colors[top_pipe->pipe_idx];
+ }
+
+-static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct mpcc_blnd_cfg blnd_cfg = { {0} };
+@@ -2032,10 +2110,10 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+
+ // input to MPCC is always RGB, by default leave black_color at 0
+ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+- dcn10_get_hdr_visual_confirm_color(
++ dc->hwss.get_hdr_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+- dcn10_get_surface_visual_confirm_color(
++ dc->hwss.get_surface_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
+ dcn20_get_mpctree_visual_confirm_color(
+@@ -2102,125 +2180,7 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ hubp->mpcc_id = mpcc_id;
+ }
+
+-static int find_free_gsl_group(const struct dc *dc)
+-{
+- if (dc->res_pool->gsl_groups.gsl_0 == 0)
+- return 1;
+- if (dc->res_pool->gsl_groups.gsl_1 == 0)
+- return 2;
+- if (dc->res_pool->gsl_groups.gsl_2 == 0)
+- return 3;
+-
+- return 0;
+-}
+-
+-/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
+- * This is only used to lock pipes in pipe splitting case with immediate flip
+- * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
+- * so we get tearing with freesync since we cannot flip multiple pipes
+- * atomically.
+- * We use GSL for this:
+- * - immediate flip: find first available GSL group if not already assigned
+- * program gsl with that group, set current OTG as master
+- * and always us 0x4 = AND of flip_ready from all pipes
+- * - vsync flip: disable GSL if used
+- *
+- * Groups in stream_res are stored as +1 from HW registers, i.e.
+- * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
+- * Using a magic value like -1 would require tracking all inits/resets
+- */
+-void dcn20_setup_gsl_group_as_lock(
+- const struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- bool enable)
+-{
+- struct gsl_params gsl;
+- int group_idx;
+-
+- memset(&gsl, 0, sizeof(struct gsl_params));
+-
+- if (enable) {
+- /* return if group already assigned since GSL was set up
+- * for vsync flip, we would unassign so it can't be "left over"
+- */
+- if (pipe_ctx->stream_res.gsl_group > 0)
+- return;
+-
+- group_idx = find_free_gsl_group(dc);
+- ASSERT(group_idx != 0);
+- pipe_ctx->stream_res.gsl_group = group_idx;
+-
+- /* set gsl group reg field and mark resource used */
+- switch (group_idx) {
+- case 1:
+- gsl.gsl0_en = 1;
+- dc->res_pool->gsl_groups.gsl_0 = 1;
+- break;
+- case 2:
+- gsl.gsl1_en = 1;
+- dc->res_pool->gsl_groups.gsl_1 = 1;
+- break;
+- case 3:
+- gsl.gsl2_en = 1;
+- dc->res_pool->gsl_groups.gsl_2 = 1;
+- break;
+- default:
+- BREAK_TO_DEBUGGER();
+- return; // invalid case
+- }
+- gsl.gsl_master_en = 1;
+- } else {
+- group_idx = pipe_ctx->stream_res.gsl_group;
+- if (group_idx == 0)
+- return; // if not in use, just return
+-
+- pipe_ctx->stream_res.gsl_group = 0;
+-
+- /* unset gsl group reg field and mark resource free */
+- switch (group_idx) {
+- case 1:
+- gsl.gsl0_en = 0;
+- dc->res_pool->gsl_groups.gsl_0 = 0;
+- break;
+- case 2:
+- gsl.gsl1_en = 0;
+- dc->res_pool->gsl_groups.gsl_1 = 0;
+- break;
+- case 3:
+- gsl.gsl2_en = 0;
+- dc->res_pool->gsl_groups.gsl_2 = 0;
+- break;
+- default:
+- BREAK_TO_DEBUGGER();
+- return;
+- }
+- gsl.gsl_master_en = 0;
+- }
+-
+- /* at this point we want to program whether it's to enable or disable */
+- if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
+- pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
+- pipe_ctx->stream_res.tg->funcs->set_gsl(
+- pipe_ctx->stream_res.tg,
+- &gsl);
+-
+- pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
+- pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0);
+- } else
+- BREAK_TO_DEBUGGER();
+-}
+-
+-static void dcn20_set_flip_control_gsl(
+- struct pipe_ctx *pipe_ctx,
+- bool flip_immediate)
+-{
+- if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
+- pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
+- pipe_ctx->plane_res.hubp, flip_immediate);
+-
+-}
+-
+-static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
++void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
+ {
+ enum dc_lane_count lane_count =
+ pipe_ctx->stream->link->cur_link_settings.lane_count;
+@@ -2268,7 +2228,7 @@ static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
+ }
+ }
+
+-static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
++void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
+ {
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+@@ -2294,7 +2254,7 @@ static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
+ hubp->inst, mode);
+ }
+
+-static void dcn20_fpga_init_hw(struct dc *dc)
++void dcn20_fpga_init_hw(struct dc *dc)
+ {
+ int i, j;
+ struct dce_hwseq *hws = dc->hwseq;
+@@ -2315,7 +2275,7 @@ static void dcn20_fpga_init_hw(struct dc *dc)
+ REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+ REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+
+- dcn20_dccg_init(hws);
++ dc->hwss.dccg_init(hws);
+
+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+@@ -2379,7 +2339,7 @@ static void dcn20_fpga_init_hw(struct dc *dc)
+ dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ /*to do*/
+- hwss1_plane_atomic_disconnect(dc, pipe_ctx);
++ dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
+ }
+
+ /* initialize DWB pointer to MCIF_WB */
+@@ -2408,53 +2368,3 @@ static void dcn20_fpga_init_hw(struct dc *dc)
+ tg->funcs->tg_init(tg);
+ }
+ }
+-
+-void dcn20_hw_sequencer_construct(struct dc *dc)
+-{
+- dcn10_hw_sequencer_construct(dc);
+- dc->hwss.unblank_stream = dcn20_unblank_stream;
+- dc->hwss.update_plane_addr = dcn20_update_plane_addr;
+- dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
+- dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
+- dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
+- dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func;
+- dc->hwss.apply_ctx_for_surface = NULL;
+- dc->hwss.program_front_end_for_ctx = dcn20_program_front_end_for_ctx;
+- dc->hwss.pipe_control_lock = dcn20_pipe_control_lock;
+- dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global;
+- dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth;
+- dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth;
+- dc->hwss.update_bandwidth = dcn20_update_bandwidth;
+- dc->hwss.enable_writeback = dcn20_enable_writeback;
+- dc->hwss.disable_writeback = dcn20_disable_writeback;
+- dc->hwss.program_output_csc = dcn20_program_output_csc;
+- dc->hwss.update_odm = dcn20_update_odm;
+- dc->hwss.blank_pixel_data = dcn20_blank_pixel_data;
+- dc->hwss.dmdata_status_done = dcn20_dmdata_status_done;
+- dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine;
+- dc->hwss.enable_stream = dcn20_enable_stream;
+- dc->hwss.disable_stream = dcn20_disable_stream;
+- dc->hwss.init_sys_ctx = dcn20_init_sys_ctx;
+- dc->hwss.init_vm_ctx = dcn20_init_vm_ctx;
+- dc->hwss.disable_stream_gating = dcn20_disable_stream_gating;
+- dc->hwss.enable_stream_gating = dcn20_enable_stream_gating;
+- dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt;
+- dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
+- dc->hwss.update_mpcc = dcn20_update_mpcc;
+- dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
+- dc->hwss.init_blank = dcn20_init_blank;
+- dc->hwss.disable_plane = dcn20_disable_plane;
+- dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
+- dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
+- dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
+- dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+- dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+- dc->hwss.disable_vga = dcn20_disable_vga;
+-
+- if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+- dc->hwss.init_hw = dcn20_fpga_init_hw;
+- dc->hwss.init_pipes = NULL;
+- }
+-
+-
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 3098f1049ed7..f58b69c1b321 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -26,90 +26,112 @@
+ #ifndef __DC_HWSS_DCN20_H__
+ #define __DC_HWSS_DCN20_H__
+
+-struct dc;
+-
+-void dcn20_hw_sequencer_construct(struct dc *dc);
+-
+-enum dc_status dcn20_enable_stream_timing(
+- struct pipe_ctx *pipe_ctx,
+- struct dc_state *context,
+- struct dc *dc);
+-
+-void dcn20_blank_pixel_data(
++bool dcn20_set_blend_lut(
++ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++bool dcn20_set_shaper_3dlut(
++ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++void dcn20_program_front_end_for_ctx(
+ struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- bool blank);
+-
++ struct dc_state *context);
++void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
++bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++ const struct dc_plane_state *plane_state);
++bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++ const struct dc_stream_state *stream);
+ void dcn20_program_output_csc(struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ enum dc_color_space colorspace,
+ uint16_t *matrix,
+ int opp_id);
+-
++void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
++void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
++ struct dc_link_settings *link_settings);
++void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_blank_pixel_data(
++ struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ bool blank);
++void dcn20_pipe_control_lock(
++ struct dc *dc,
++ struct pipe_ctx *pipe,
++ bool lock);
++void dcn20_pipe_control_lock_global(
++ struct dc *dc,
++ struct pipe_ctx *pipe,
++ bool lock);
+ void dcn20_prepare_bandwidth(
+ struct dc *dc,
+ struct dc_state *context);
+-
+ void dcn20_optimize_bandwidth(
+ struct dc *dc,
+ struct dc_state *context);
+-
+ bool dcn20_update_bandwidth(
+ struct dc *dc,
+ struct dc_state *context);
+-
++void dcn20_reset_hw_ctx_wrap(
++ struct dc *dc,
++ struct dc_state *context);
++enum dc_status dcn20_enable_stream_timing(
++ struct pipe_ctx *pipe_ctx,
++ struct dc_state *context,
++ struct dc *dc);
++void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_init_blank(
++ struct dc *dc,
++ struct timing_generator *tg);
++void dcn20_disable_vga(
++ struct dce_hwseq *hws);
++void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_enable_power_gating_plane(
++ struct dce_hwseq *hws,
++ bool enable);
++void dcn20_dpp_pg_control(
++ struct dce_hwseq *hws,
++ unsigned int dpp_inst,
++ bool power_on);
++void dcn20_hubp_pg_control(
++ struct dce_hwseq *hws,
++ unsigned int hubp_inst,
++ bool power_on);
++void dcn20_program_triple_buffer(
++ const struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ bool enable_triple_buffer);
++void dcn20_enable_writeback(
++ struct dc *dc,
++ const struct dc_stream_status *stream_status,
++ struct dc_writeback_info *wb_info,
++ struct dc_state *context);
+ void dcn20_disable_writeback(
+ struct dc *dc,
+ unsigned int dwb_pipe_inst);
+-
+-bool dcn20_hwss_wait_for_blank_complete(
+- struct output_pixel_processor *opp);
+-
+-bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+- const struct dc_stream_state *stream);
+-
+-bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+- const struct dc_plane_state *plane_state);
+-
++void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_program_tripleBuffer(
+- const struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- bool enableTripleBuffer);
+-
+-void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_pipe_control_lock_global(
++void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
++void dcn20_init_vm_ctx(
++ struct dce_hwseq *hws,
+ struct dc *dc,
+- struct pipe_ctx *pipe,
+- bool lock);
+-void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- bool enable);
+-void dcn20_dccg_init(struct dce_hwseq *hws);
+-void dcn20_init_blank(
+- struct dc *dc,
+- struct timing_generator *tg);
+-void dcn20_display_init(struct dc *dc);
+-void dcn20_pipe_control_lock(
+- struct dc *dc,
+- struct pipe_ctx *pipe,
+- bool lock);
+-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-void dcn20_enable_plane(
+- struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- struct dc_state *context);
+-bool dcn20_set_blend_lut(
+- struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+-bool dcn20_set_shaper_3dlut(
+- struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+-void dcn20_get_mpctree_visual_confirm_color(
++ struct dc_virtual_addr_space_config *va_config,
++ int vmid);
++void dcn20_set_flip_control_gsl(
+ struct pipe_ctx *pipe_ctx,
+- struct tg_color *color);
++ bool flip_immediate);
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++void dcn20_dsc_pg_control(
++ struct dce_hwseq *hws,
++ unsigned int dsc_inst,
++ bool power_on);
++#endif
++void dcn20_fpga_init_hw(struct dc *dc);
++bool dcn20_wait_for_blank_complete(
++ struct output_pixel_processor *opp);
++void dcn20_dccg_init(struct dce_hwseq *hws);
++int dcn20_init_sys_ctx(struct dce_hwseq *hws,
++ struct dc *dc,
++ struct dc_phy_addr_space_config *pa_config);
++
+ #endif /* __DC_HWSS_DCN20_H__ */
++
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+new file mode 100644
+index 000000000000..10493777d192
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+@@ -0,0 +1,131 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10/dcn10_hw_sequencer.h"
++#include "dcn20_hwseq.h"
++
++static const struct hw_sequencer_funcs dcn20_funcs = {
++ .program_gamut_remap = dcn10_program_gamut_remap,
++ .init_hw = dcn10_init_hw,
++ .init_pipes = dcn10_init_pipes,
++ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
++ .apply_ctx_for_surface = NULL,
++ .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
++ .update_plane_addr = dcn20_update_plane_addr,
++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++ .update_dchub = dcn10_update_dchub,
++ .update_mpcc = dcn20_update_mpcc,
++ .update_pending_status = dcn10_update_pending_status,
++ .set_input_transfer_func = dcn20_set_input_transfer_func,
++ .set_output_transfer_func = dcn20_set_output_transfer_func,
++ .program_output_csc = dcn20_program_output_csc,
++ .power_down = dce110_power_down,
++ .enable_accelerated_mode = dce110_enable_accelerated_mode,
++ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
++ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
++ .update_info_frame = dce110_update_info_frame,
++ .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
++ .enable_stream = dcn20_enable_stream,
++ .disable_stream = dce110_disable_stream,
++ .unblank_stream = dcn20_unblank_stream,
++ .blank_stream = dce110_blank_stream,
++ .enable_audio_stream = dce110_enable_audio_stream,
++ .disable_audio_stream = dce110_disable_audio_stream,
++ .enable_display_power_gating = dcn10_dummy_display_power_gating,
++ .disable_plane = dcn20_disable_plane,
++ .blank_pixel_data = dcn20_blank_pixel_data,
++ .pipe_control_lock = dcn20_pipe_control_lock,
++ .pipe_control_lock_global = dcn20_pipe_control_lock_global,
++ .prepare_bandwidth = dcn20_prepare_bandwidth,
++ .optimize_bandwidth = dcn20_optimize_bandwidth,
++ .update_bandwidth = dcn20_update_bandwidth,
++ .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++ .enable_stream_timing = dcn20_enable_stream_timing,
++ .set_drr = dcn10_set_drr,
++ .get_position = dcn10_get_position,
++ .set_static_screen_control = dcn10_set_static_screen_control,
++ .setup_stereo = dcn10_setup_stereo,
++ .set_avmute = dce110_set_avmute,
++ .log_hw_state = dcn10_log_hw_state,
++ .get_hw_state = dcn10_get_hw_state,
++ .clear_status_bits = dcn10_clear_status_bits,
++ .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
++ .edp_backlight_control = dce110_edp_backlight_control,
++ .edp_power_control = dce110_edp_power_control,
++ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++ .set_cursor_position = dcn10_set_cursor_position,
++ .set_cursor_attribute = dcn10_set_cursor_attribute,
++ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++ .disable_stream_gating = dcn20_disable_stream_gating,
++ .enable_stream_gating = dcn20_enable_stream_gating,
++ .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
++ .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
++ .set_clock = dcn10_set_clock,
++ .get_clock = dcn10_get_clock,
++ .did_underflow_occur = dcn10_did_underflow_occur,
++ .init_blank = dcn20_init_blank,
++ .disable_vga = dcn20_disable_vga,
++ .bios_golden_init = dcn10_bios_golden_init,
++ .plane_atomic_disable = dcn20_plane_atomic_disable,
++ .plane_atomic_power_down = dcn10_plane_atomic_power_down,
++ .enable_power_gating_plane = dcn20_enable_power_gating_plane,
++ .dpp_pg_control = dcn20_dpp_pg_control,
++ .hubp_pg_control = dcn20_hubp_pg_control,
++ .dsc_pg_control = NULL,
++ .program_triplebuffer = dcn20_program_triple_buffer,
++ .enable_writeback = dcn20_enable_writeback,
++ .disable_writeback = dcn20_disable_writeback,
++ .update_odm = dcn20_update_odm,
++ .dmdata_status_done = dcn20_dmdata_status_done,
++ .program_dmdata_engine = dcn20_program_dmdata_engine,
++ .init_sys_ctx = dcn20_init_sys_ctx,
++ .init_vm_ctx = dcn20_init_vm_ctx,
++ .set_flip_control_gsl = dcn20_set_flip_control_gsl,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++ .dsc_pg_control = dcn20_dsc_pg_control,
++#else
++ .dsc_pg_control = NULL,
++#endif
++ .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
++ .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
++ .set_hdr_multiplier = dcn10_set_hdr_multiplier,
++ .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
++ .wait_for_blank_complete = dcn20_wait_for_blank_complete,
++ .dccg_init = dcn20_dccg_init,
++ .set_blend_lut = dcn20_set_blend_lut,
++ .set_shaper_3dlut = dcn20_set_shaper_3dlut,
++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++void dcn20_hw_sequencer_construct(struct dc *dc)
++{
++ dc->hwss = dcn20_funcs;
++
++ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++ dc->hwss.init_hw = dcn20_fpga_init_hw;
++ dc->hwss.init_pipes = NULL;
++ }
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h
+new file mode 100644
+index 000000000000..12277797cd71
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_DCN20_INIT_H__
++#define __DC_DCN20_INIT_H__
++
++struct dc;
++
++void dcn20_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_DCN20_INIT_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 0e50dc9b611a..f5854a5d2b76 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -201,11 +201,11 @@ void optc2_set_dsc_config(struct timing_generator *optc,
+ OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
+ }
+
+-/**
+- * PTI i think is already done somewhere else for 2ka
+- * (opp?, please double check.
+- * OPTC side only has 1 register to set for PTI_ENABLE)
+- */
++/*TEMP: Need to figure out inheritance model here.*/
++bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
++{
++ return optc1_is_two_pixels_per_containter(timing);
++}
+
+ void optc2_set_odm_bypass(struct timing_generator *optc,
+ const struct dc_crtc_timing *dc_crtc_timing)
+@@ -219,7 +219,7 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
+ OPTC_SEG1_SRC_SEL, 0xf);
+ REG_WRITE(OTG_H_TIMING_CNTL, 0);
+
+- h_div_2 = optc1_is_two_pixels_per_containter(dc_crtc_timing);
++ h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
+ REG_UPDATE(OTG_H_TIMING_CNTL,
+ OTG_H_TIMING_DIV_BY2, h_div_2);
+ REG_SET(OPTC_MEMORY_CONFIG, 0,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+index 9ae22146d2d8..ac93fbfaee03 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+@@ -107,5 +107,5 @@ void optc2_triplebuffer_unlock(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
+ void optc2_program_manual_trigger(struct timing_generator *optc);
+-
++bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
+ #endif /* __DC_OPTC_DCN20_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2315da20fd41..b000d5289684 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -26,6 +26,8 @@
+ #include "dm_services.h"
+ #include "dc.h"
+
++#include "dcn20_init.h"
++
+ #include "resource.h"
+ #include "include/irq_service_interface.h"
+ #include "dcn20/dcn20_resource.h"
+@@ -1453,7 +1455,7 @@ static void get_pixel_clock_parameters(
+
+ if (opp_cnt == 4)
+ pixel_clk_params->requested_pix_clk_100hz /= 4;
+- else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
++ else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
+ pixel_clk_params->requested_pix_clk_100hz /= 2;
+
+ if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index feb7e705e792..5a061e10ef4d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,8 @@
+ #
+ # Makefile for DCN21.
+
+-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
++DCN21 = dcn21_init.o dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o \
++ dcn21_hwseq.o dcn21_link_encoder.o
+
+ CFLAGS_dcn21_resource.o := -mhard-float -msse
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+index b25215cadf85..005894dcabc9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+@@ -28,7 +28,6 @@
+ #include "core_types.h"
+ #include "resource.h"
+ #include "dce/dce_hwseq.h"
+-#include "dcn20/dcn20_hwseq.h"
+ #include "vmid.h"
+ #include "reg_helper.h"
+ #include "hw/clk_mgr.h"
+@@ -61,7 +60,7 @@ static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *c
+
+ }
+
+-static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
++int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+ {
+ struct dcn_hubbub_phys_addr_config config;
+
+@@ -82,7 +81,7 @@ static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_ph
+
+ // work around for Renoir s0i3, if register is programmed, bypass golden init.
+
+-static bool dcn21_s0i3_golden_init_wa(struct dc *dc)
++bool dcn21_s0i3_golden_init_wa(struct dc *dc)
+ {
+ struct dce_hwseq *hws = dc->hwseq;
+ uint32_t value = 0;
+@@ -112,11 +111,3 @@ void dcn21_optimize_pwr_state(
+ true);
+ }
+
+-void dcn21_hw_sequencer_construct(struct dc *dc)
+-{
+- dcn20_hw_sequencer_construct(dc);
+- dc->hwss.init_sys_ctx = dcn21_init_sys_ctx;
+- dc->hwss.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa;
+- dc->hwss.optimize_pwr_state = dcn21_optimize_pwr_state;
+- dc->hwss.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state;
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+index be67b62e6fb1..2f7b8a220eb9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+@@ -28,6 +28,18 @@
+
+ struct dc;
+
+-void dcn21_hw_sequencer_construct(struct dc *dc);
++int dcn21_init_sys_ctx(struct dce_hwseq *hws,
++ struct dc *dc,
++ struct dc_phy_addr_space_config *pa_config);
++
++bool dcn21_s0i3_golden_init_wa(struct dc *dc);
++
++void dcn21_exit_optimized_pwr_state(
++ const struct dc *dc,
++ struct dc_state *context);
++
++void dcn21_optimize_pwr_state(
++ const struct dc *dc,
++ struct dc_state *context);
+
+ #endif /* __DC_HWSS_DCN21_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+new file mode 100644
+index 000000000000..cbd55037a04a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+@@ -0,0 +1,135 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10/dcn10_hw_sequencer.h"
++#include "dcn20/dcn20_hwseq.h"
++#include "dcn21_hwseq.h"
++
++static const struct hw_sequencer_funcs dcn21_funcs = {
++ .program_gamut_remap = dcn10_program_gamut_remap,
++ .init_hw = dcn10_init_hw,
++ .init_pipes = dcn10_init_pipes,
++ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
++ .apply_ctx_for_surface = NULL,
++ .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
++ .update_plane_addr = dcn20_update_plane_addr,
++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++ .update_dchub = dcn10_update_dchub,
++ .update_mpcc = dcn20_update_mpcc,
++ .update_pending_status = dcn10_update_pending_status,
++ .set_input_transfer_func = dcn20_set_input_transfer_func,
++ .set_output_transfer_func = dcn20_set_output_transfer_func,
++ .program_output_csc = dcn20_program_output_csc,
++ .power_down = dce110_power_down,
++ .enable_accelerated_mode = dce110_enable_accelerated_mode,
++ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
++ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
++ .update_info_frame = dce110_update_info_frame,
++ .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
++ .enable_stream = dcn20_enable_stream,
++ .disable_stream = dce110_disable_stream,
++ .unblank_stream = dcn20_unblank_stream,
++ .blank_stream = dce110_blank_stream,
++ .enable_audio_stream = dce110_enable_audio_stream,
++ .disable_audio_stream = dce110_disable_audio_stream,
++ .enable_display_power_gating = dcn10_dummy_display_power_gating,
++ .disable_plane = dcn20_disable_plane,
++ .blank_pixel_data = dcn20_blank_pixel_data,
++ .pipe_control_lock = dcn20_pipe_control_lock,
++ .pipe_control_lock_global = dcn20_pipe_control_lock_global,
++ .prepare_bandwidth = dcn20_prepare_bandwidth,
++ .optimize_bandwidth = dcn20_optimize_bandwidth,
++ .update_bandwidth = dcn20_update_bandwidth,
++ .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++ .enable_stream_timing = dcn20_enable_stream_timing,
++ .set_drr = dcn10_set_drr,
++ .get_position = dcn10_get_position,
++ .set_static_screen_control = dcn10_set_static_screen_control,
++ .setup_stereo = dcn10_setup_stereo,
++ .set_avmute = dce110_set_avmute,
++ .log_hw_state = dcn10_log_hw_state,
++ .get_hw_state = dcn10_get_hw_state,
++ .clear_status_bits = dcn10_clear_status_bits,
++ .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
++ .edp_backlight_control = dce110_edp_backlight_control,
++ .edp_power_control = dce110_edp_power_control,
++ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++ .set_cursor_position = dcn10_set_cursor_position,
++ .set_cursor_attribute = dcn10_set_cursor_attribute,
++ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++ .disable_stream_gating = dcn20_disable_stream_gating,
++ .enable_stream_gating = dcn20_enable_stream_gating,
++ .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
++ .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
++ .set_clock = dcn10_set_clock,
++ .get_clock = dcn10_get_clock,
++ .did_underflow_occur = dcn10_did_underflow_occur,
++ .init_blank = dcn20_init_blank,
++ .disable_vga = dcn20_disable_vga,
++ .bios_golden_init = dcn10_bios_golden_init,
++ .plane_atomic_disable = dcn20_plane_atomic_disable,
++ .plane_atomic_power_down = dcn10_plane_atomic_power_down,
++ .enable_power_gating_plane = dcn20_enable_power_gating_plane,
++ .dpp_pg_control = dcn20_dpp_pg_control,
++ .hubp_pg_control = dcn20_hubp_pg_control,
++ .dsc_pg_control = NULL,
++ .program_triplebuffer = dcn20_program_triple_buffer,
++ .enable_writeback = dcn20_enable_writeback,
++ .disable_writeback = dcn20_disable_writeback,
++ .update_odm = dcn20_update_odm,
++ .dmdata_status_done = dcn20_dmdata_status_done,
++ .program_dmdata_engine = dcn20_program_dmdata_engine,
++ .init_sys_ctx = dcn21_init_sys_ctx,
++ .init_vm_ctx = dcn20_init_vm_ctx,
++ .set_flip_control_gsl = dcn20_set_flip_control_gsl,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++ .dsc_pg_control = dcn20_dsc_pg_control,
++#else
++ .dsc_pg_control = NULL,
++#endif
++ .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
++ .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
++ .set_hdr_multiplier = dcn10_set_hdr_multiplier,
++ .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
++ .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
++ .optimize_pwr_state = dcn21_optimize_pwr_state,
++ .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
++ .wait_for_blank_complete = dcn20_wait_for_blank_complete,
++ .dccg_init = dcn20_dccg_init,
++ .set_blend_lut = dcn20_set_blend_lut,
++ .set_shaper_3dlut = dcn20_set_shaper_3dlut,
++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++void dcn21_hw_sequencer_construct(struct dc *dc)
++{
++ dc->hwss = dcn21_funcs;
++
++ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++ dc->hwss.init_hw = dcn20_fpga_init_hw;
++ dc->hwss.init_pipes = NULL;
++ }
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h
+new file mode 100644
+index 000000000000..3ed24292648a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_DCN21_INIT_H__
++#define __DC_DCN21_INIT_H__
++
++struct dc;
++
++void dcn21_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_DCN20_INIT_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index f68f643a82af..260471ac20c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -26,6 +26,8 @@
+ #include "dm_services.h"
+ #include "dc.h"
+
++#include "dcn21_init.h"
++
+ #include "resource.h"
+ #include "include/irq_service_interface.h"
+ #include "dcn20/dcn20_resource.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 23e3a541b7c9..937a02d02f18 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -148,11 +148,11 @@ struct hw_sequencer_funcs {
+ void (*update_pending_status)(
+ struct pipe_ctx *pipe_ctx);
+
+- bool (*set_input_transfer_func)(
++ bool (*set_input_transfer_func)(struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ const struct dc_plane_state *plane_state);
+
+- bool (*set_output_transfer_func)(
++ bool (*set_output_transfer_func)(struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ const struct dc_stream_state *stream);
+
+@@ -279,8 +279,10 @@ struct hw_sequencer_funcs {
+ void (*set_cursor_attribute)(struct pipe_ctx *pipe);
+ void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
+
+- void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
+- void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
++ void (*setup_periodic_interrupt)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ enum vline_select vline);
++ void (*setup_vupdate_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+ bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+
+ void (*init_blank)(struct dc *dc, struct timing_generator *tg);
+@@ -340,6 +342,36 @@ struct hw_sequencer_funcs {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ bool (*s0i3_golden_init_wa)(struct dc *dc);
+ #endif
++
++ void (*get_surface_visual_confirm_color)(
++ const struct pipe_ctx *pipe_ctx,
++ struct tg_color *color);
++
++ void (*get_hdr_visual_confirm_color)(
++ struct pipe_ctx *pipe_ctx,
++ struct tg_color *color);
++
++ void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
++
++ void (*verify_allow_pstate_change_high)(struct dc *dc);
++
++ void (*program_pipe)(
++ struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ struct dc_state *context);
++
++ bool (*wait_for_blank_complete)(
++ struct output_pixel_processor *opp);
++
++ void (*dccg_init)(struct dce_hwseq *hws);
++
++ bool (*set_blend_lut)(
++ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++
++ bool (*set_shaper_3dlut)(
++ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++
++ int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
+ };
+
+ void color_space_to_black_color(
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4654-drm-amd-display-Use-a-temporary-copy-of-the-current-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4654-drm-amd-display-Use-a-temporary-copy-of-the-current-.patch
new file mode 100644
index 00000000..1a756d53
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4654-drm-amd-display-Use-a-temporary-copy-of-the-current-.patch
@@ -0,0 +1,87 @@
+From 0021da190e287eb7c2b8dd43b32f8404f7dd75bb Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Mon, 4 Nov 2019 17:44:23 -0500
+Subject: [PATCH 4654/4736] drm/amd/display: Use a temporary copy of the
+ current state when updating DSC config
+
+[why]
+When updating DSC config, a new config has to be validated before proceeding
+with applying the update. Validation, however, modifies the current state.
+This means DSC config validation would affect pipe re-assignment, causing
+intermittent screen corruption issues when ODM is required for DSC.
+
+[how]
+- Use a copy of the current state for modified DSC config validation
+- Set the update type to FULL_UPDATE to correctly validate and set the
+ actual state used for committing the streams
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 33 +++++++++++++++++++-----
+ 1 file changed, 26 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 562a24f4553f..584127a5ec18 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1672,6 +1672,11 @@ static enum surface_update_type check_update_surfaces_for_stream(
+
+ if (stream_update->output_csc_transform || stream_update->output_color_space)
+ su_flags->bits.out_csc = 1;
++
++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
++ if (stream_update->dsc_config)
++ overall_type = UPDATE_TYPE_FULL;
++#endif
+ }
+
+ for (i = 0 ; i < surface_count; i++) {
+@@ -1863,8 +1868,10 @@ static void copy_surface_update_to_plane(
+ static void copy_stream_update_to_stream(struct dc *dc,
+ struct dc_state *context,
+ struct dc_stream_state *stream,
+- const struct dc_stream_update *update)
++ struct dc_stream_update *update)
+ {
++ struct dc_context *dc_ctx = dc->ctx;
++
+ if (update == NULL || stream == NULL)
+ return;
+
+@@ -1941,12 +1948,24 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
+ update->dsc_config->num_slices_v != 0);
+
+- stream->timing.dsc_cfg = *update->dsc_config;
+- stream->timing.flags.DSC = enable_dsc;
+- if (!dc->res_pool->funcs->validate_bandwidth(dc, context,
+- true)) {
+- stream->timing.dsc_cfg = old_dsc_cfg;
+- stream->timing.flags.DSC = old_dsc_enabled;
++ /* Use temporarry context for validating new DSC config */
++ struct dc_state *dsc_validate_context = dc_create_state(dc);
++
++ if (dsc_validate_context) {
++ dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
++
++ stream->timing.dsc_cfg = *update->dsc_config;
++ stream->timing.flags.DSC = enable_dsc;
++ if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
++ stream->timing.dsc_cfg = old_dsc_cfg;
++ stream->timing.flags.DSC = old_dsc_enabled;
++ update->dsc_config = false;
++ }
++
++ dc_release_state(dsc_validate_context);
++ } else {
++ DC_ERROR("Failed to allocate new validate context for DSC change\n");
++ update->dsc_config = false;
+ }
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4655-drm-amd-display-Use-NULL-for-pointer-assignment-in-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4655-drm-amd-display-Use-NULL-for-pointer-assignment-in-c.patch
new file mode 100644
index 00000000..fa09c7df
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4655-drm-amd-display-Use-NULL-for-pointer-assignment-in-c.patch
@@ -0,0 +1,53 @@
+From 525c62d8f942505378461536185b29d6e35c682d Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Sat, 23 Nov 2019 12:36:39 -0700
+Subject: [PATCH 4655/4736] drm/amd/display: Use NULL for pointer assignment in
+ copy_stream_update_to_stream
+
+Clang warns:
+
+../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1965:26: warning:
+expression which evaluates to zero treated as a null pointer constant of
+type 'struct dc_dsc_config *' [-Wnon-literal-null-conversion]
+ update->dsc_config = false;
+ ^~~~~
+../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1971:25: warning:
+expression which evaluates to zero treated as a null pointer constant of
+type 'struct dc_dsc_config *' [-Wnon-literal-null-conversion]
+ update->dsc_config = false;
+ ^~~~~
+2 warnings generated.
+
+Fixes: f6fe4053b91f ("drm/amd/display: Use a temporary copy of the current state when updating DSC config")
+Link: https://github.com/ClangBuiltLinux/linux/issues/777
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 584127a5ec18..09184adfccc8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1959,13 +1959,13 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
+ stream->timing.dsc_cfg = old_dsc_cfg;
+ stream->timing.flags.DSC = old_dsc_enabled;
+- update->dsc_config = false;
++ update->dsc_config = NULL;
+ }
+
+ dc_release_state(dsc_validate_context);
+ } else {
+ DC_ERROR("Failed to allocate new validate context for DSC change\n");
+- update->dsc_config = false;
++ update->dsc_config = NULL;
+ }
+ }
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4656-drm-amdgpu-add-cache-flush-workaround-to-gfx8-emit_f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4656-drm-amdgpu-add-cache-flush-workaround-to-gfx8-emit_f.patch
new file mode 100644
index 00000000..e6f0a58d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4656-drm-amdgpu-add-cache-flush-workaround-to-gfx8-emit_f.patch
@@ -0,0 +1,66 @@
+From eea79ae0d4fbca5c98b76b1d4e904de0e47ce24a Mon Sep 17 00:00:00 2001
+From: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
+Date: Thu, 28 Nov 2019 12:08:58 +0100
+Subject: [PATCH 4656/4736] drm/amdgpu: add cache flush workaround to gfx8
+ emit_fence
+
+The same workaround is used for gfx7.
+Both PAL and Mesa use it for gfx8 too, so port this commit to
+gfx_v8_0_ring_emit_fence_gfx.
+
+Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 387e95319594..e379b1de50ba 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -6131,7 +6131,23 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
+ bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
+ bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
+
+- /* EVENT_WRITE_EOP - flush caches, send int */
++ /* Workaround for cache flush problems. First send a dummy EOP
++ * event down the pipe with seq one below.
++ */
++ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
++ amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
++ EOP_TC_ACTION_EN |
++ EOP_TC_WB_ACTION_EN |
++ EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
++ EVENT_INDEX(5)));
++ amdgpu_ring_write(ring, addr & 0xfffffffc);
++ amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
++ DATA_SEL(1) | INT_SEL(0));
++ amdgpu_ring_write(ring, lower_32_bits(seq - 1));
++ amdgpu_ring_write(ring, upper_32_bits(seq - 1));
++
++ /* Then send the real EOP event down the pipe:
++ * EVENT_WRITE_EOP - flush caches, send int */
+ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+ amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
+ EOP_TC_ACTION_EN |
+@@ -6874,7 +6890,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
+ 5 + /* COND_EXEC */
+ 7 + /* PIPELINE_SYNC */
+ VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
+- 8 + /* FENCE for VM_FLUSH */
++ 12 + /* FENCE for VM_FLUSH */
+ 20 + /* GDS switch */
+ 4 + /* double SWITCH_BUFFER,
+ the first COND_EXEC jump to the place just
+@@ -6886,7 +6902,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
+ 31 + /* DE_META */
+ 3 + /* CNTX_CTRL */
+ 5 + /* HDP_INVL */
+- 8 + 8 + /* FENCE x2 */
++ 12 + 12 + /* FENCE x2 */
+ 2, /* SWITCH_BUFFER */
+ .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
+ .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4657-drm-amdgpu-remove-ras-global-recovery-handling-from-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4657-drm-amdgpu-remove-ras-global-recovery-handling-from-.patch
new file mode 100644
index 00000000..8677b689
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4657-drm-amdgpu-remove-ras-global-recovery-handling-from-.patch
@@ -0,0 +1,36 @@
+From 2a6a1ea67ecc93bb2e61b755093707cd1bbce018 Mon Sep 17 00:00:00 2001
+From: Le Ma <Le.Ma@amd.com>
+Date: Tue, 22 Oct 2019 02:41:26 +0800
+Subject: [PATCH 4657/4736] drm/amdgpu: remove ras global recovery handling
+ from ras_controller_int handler
+
+v2: add notification when ras controller interrupt generates
+
+Change-Id: Ic03e42e9d1c4dab1fa7f4817c191a16e485b48a9
+Signed-off-by: Le Ma <Le.Ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 0db458f9fafc..25231d699341 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -324,7 +324,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
+ RAS_CNTLR_INTERRUPT_CLEAR, 1);
+ WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
+
+- amdgpu_ras_global_ras_isr(adev);
++ DRM_WARN("RAS controller interrupt triggered by NBIF error\n");
++
++ /* ras_controller_int is dedicated for nbif ras error,
++ * not the global interrupt for sync flood
++ */
++ amdgpu_ras_reset_gpu(adev, true);
+ }
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4658-drm-amdgpu-export-amdgpu_ras_find_obj-to-use-externa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4658-drm-amdgpu-export-amdgpu_ras_find_obj-to-use-externa.patch
new file mode 100644
index 00000000..a5a5447c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4658-drm-amdgpu-export-amdgpu_ras_find_obj-to-use-externa.patch
@@ -0,0 +1,56 @@
+From c02c16055c57c778464896d81d3d17932c3c4b77 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 25 Nov 2019 12:26:09 +0800
+Subject: [PATCH 4658/4736] drm/amdgpu: export amdgpu_ras_find_obj to use
+ externally
+
+Change it to external interface.
+
+Change-Id: I2ab61f149c84a05a6f883a4c7415ea8012ec03a6
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 +++
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index bbd4fd5d7850..93294782e8c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -196,9 +196,6 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ return 0;
+ }
+
+-static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+- struct ras_common_if *head);
+-
+ /**
+ * DOC: AMDGPU RAS debugfs control interface
+ *
+@@ -443,7 +440,7 @@ static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
+ }
+
+ /* return an obj equal to head, or the first when head is NULL */
+-static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
++struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+ struct ras_common_if *head)
+ {
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index f80fd3428c98..a2c1ac1b9572 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -611,6 +611,9 @@ int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
+ int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
+ struct ras_dispatch_if *info);
+
++struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
++ struct ras_common_if *head);
++
+ extern atomic_t amdgpu_ras_in_intr;
+
+ static inline bool amdgpu_ras_intr_triggered(void)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch
new file mode 100644
index 00000000..55c78e06
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch
@@ -0,0 +1,55 @@
+From 995d14032141d5875eb3578387bce42f2deabcfc Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 22 Nov 2019 17:56:47 +0800
+Subject: [PATCH 4659/4736] drm/amdgpu: clear ras controller status registers
+ when interrupt occurs
+
+To fix issue that ras controller interrupt cannot be triggered anymore after
+one time nbif uncorrectable error. And error count is stored in nbif ras object
+for query.
+
+Change-Id: Iba482c169fdff3e9c390072c0289a622a522133c
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 25231d699341..9a3a65a0691c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -52,6 +52,9 @@
+ #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+ #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+
++static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
++ void *ras_error_status);
++
+ static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
+ {
+ WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+@@ -314,6 +317,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
+ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
+ {
+ uint32_t bif_doorbell_intr_cntl;
++ struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
+
+ bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
+ if (REG_GET_FIELD(bif_doorbell_intr_cntl,
+@@ -324,6 +328,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
+ RAS_CNTLR_INTERRUPT_CLEAR, 1);
+ WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
+
++ /*
++ * clear error status after ras_controller_intr according to
++ * hw team and count ue number for query
++ */
++ nbio_v7_4_query_ras_error_count(adev, &obj->err_data);
++
+ DRM_WARN("RAS controller interrupt triggered by NBIF error\n");
+
+ /* ras_controller_int is dedicated for nbif ras error,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4660-drm-amdgpu-clear-uncorrectable-parity-error-status-b.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4660-drm-amdgpu-clear-uncorrectable-parity-error-status-b.patch
new file mode 100644
index 00000000..c4c18944
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4660-drm-amdgpu-clear-uncorrectable-parity-error-status-b.patch
@@ -0,0 +1,56 @@
+From f7af664bf62fc3f66ac1435165116700552b4c60 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 22 Nov 2019 18:39:11 +0800
+Subject: [PATCH 4660/4736] drm/amdgpu: clear uncorrectable parity error status
+ bit
+
+This should be cleared during every nbif uncorrectable error cleanup work.
+
+Change-Id: If5de1fa2779d012ad8b20de03e19251d0d590fa2
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 9a3a65a0691c..bb701dbfd472 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -482,10 +482,12 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
+ return 0;
+ }
+
++#define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030
++
+ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ void *ras_error_status)
+ {
+- uint32_t global_sts, central_sts, int_eoi;
++ uint32_t global_sts, central_sts, int_eoi, parity_sts;
+ uint32_t corr, fatal, non_fatal;
+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+
+@@ -494,6 +496,7 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
+ non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
+ ParityErrNonFatal);
++ parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
+
+ if (corr)
+ err_data->ce_count++;
+@@ -505,6 +508,11 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ /* clear error status register */
+ WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
+
++ if (fatal)
++ /* clear parity fatal error indication field */
++ WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2,
++ parity_sts);
++
+ if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
+ BIFL_RasContller_Intr_Recv)) {
+ /* clear interrupt status register */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4661-drm-amdgpu-enable-disable-doorbell-interrupt-in-baco.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4661-drm-amdgpu-enable-disable-doorbell-interrupt-in-baco.patch
new file mode 100644
index 00000000..a71c7c69
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4661-drm-amdgpu-enable-disable-doorbell-interrupt-in-baco.patch
@@ -0,0 +1,85 @@
+From 2813c4e0bbdd1666e3d0f13248861d08d61c548f Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 26 Nov 2019 17:24:56 +0800
+Subject: [PATCH 4661/4736] drm/amdgpu: enable/disable doorbell interrupt in
+ baco entry/exit helper
+
+This operation is needed when baco entry/exit for ras recovery
+
+Change-Id: I535c7231693f3138a8e3d5acd55672e2ac68232f
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index db80dd97f0ef..863590e169ac 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4338,10 +4338,14 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+ int amdgpu_device_baco_enter(struct drm_device *dev)
+ {
+ struct amdgpu_device *adev = dev->dev_private;
++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+ if (!amdgpu_device_supports_baco(adev->ddev))
+ return -ENOTSUPP;
+
++ if (ras && ras->supported)
++ adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
++
+ if (is_support_sw_smu(adev)) {
+ struct smu_context *smu = &adev->smu;
+ int ret;
+@@ -4349,8 +4353,6 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
+ ret = smu_baco_enter(smu);
+ if (ret)
+ return ret;
+-
+- return 0;
+ } else {
+ void *pp_handle = adev->powerplay.pp_handle;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+@@ -4361,14 +4363,15 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
+ /* enter BACO state */
+ if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+ return -EIO;
+-
+- return 0;
+ }
++
++ return 0;
+ }
+
+ int amdgpu_device_baco_exit(struct drm_device *dev)
+ {
+ struct amdgpu_device *adev = dev->dev_private;
++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+ if (!amdgpu_device_supports_baco(adev->ddev))
+ return -ENOTSUPP;
+@@ -4381,7 +4384,6 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
+ if (ret)
+ return ret;
+
+- return 0;
+ } else {
+ void *pp_handle = adev->powerplay.pp_handle;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+@@ -4392,7 +4394,10 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
+ /* exit BACO state */
+ if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+ return -EIO;
+-
+- return 0;
+ }
++
++ if (ras && ras->supported)
++ adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
++
++ return 0;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4662-drm-amdgpu-add-concurrent-baco-reset-support-for-XGM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4662-drm-amdgpu-add-concurrent-baco-reset-support-for-XGM.patch
new file mode 100644
index 00000000..b549c229
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4662-drm-amdgpu-add-concurrent-baco-reset-support-for-XGM.patch
@@ -0,0 +1,182 @@
+From 2d2a5a052ea8e4ada3cfabafd23a9e1b896a23ee Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 26 Nov 2019 22:12:31 +0800
+Subject: [PATCH 4662/4736] drm/amdgpu: add concurrent baco reset support for
+ XGMI
+
+Currently each XGMI node reset wq does not run in parrallel if bound to same
+cpu. Make change to bound the xgmi_reset_work item to different cpus.
+
+XGMI requires all nodes enter into baco within very close proximity before
+any node exit baco. So schedule the xgmi_reset_work wq twice for enter/exit
+baco respectively.
+
+To use baco for XGMI, PMFW supported for baco on XGMI needs to be involved.
+
+The case that PSP reset and baco reset coexist within an XGMI hive never exist
+and is not in the consideration.
+
+v2: define use_baco flag to simplify the code for xgmi baco sequence
+
+Change-Id: I9c08cf90134f940b42e20d2129ff87fba761c532
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 82 ++++++++++++++++++----
+ 2 files changed, 72 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 4eddee90553b..566ae8bf2ba7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1040,6 +1040,8 @@ struct amdgpu_device {
+
+ bool pm_sysfs_en;
+ bool ucode_sysfs_en;
++
++ bool in_baco;
+ };
+
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 863590e169ac..2ca9d556c084 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2663,7 +2663,13 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
+ struct amdgpu_device *adev =
+ container_of(__work, struct amdgpu_device, xgmi_reset_work);
+
+- adev->asic_reset_res = amdgpu_asic_reset(adev);
++ if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++ adev->asic_reset_res = (adev->in_baco == false) ?
++ amdgpu_device_baco_enter(adev->ddev) :
++ amdgpu_device_baco_exit(adev->ddev);
++ else
++ adev->asic_reset_res = amdgpu_asic_reset(adev);
++
+ if (adev->asic_reset_res)
+ DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
+ adev->asic_reset_res, adev->ddev->unique);
+@@ -3795,13 +3801,18 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
+ return r;
+ }
+
+-static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
++static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
++ struct amdgpu_hive_info *hive,
+ struct list_head *device_list_handle,
+ bool *need_full_reset_arg)
+ {
+ struct amdgpu_device *tmp_adev = NULL;
+ bool need_full_reset = *need_full_reset_arg, vram_lost = false;
+ int r = 0;
++ int cpu = smp_processor_id();
++ bool use_baco =
++ (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
++ true : false;
+
+ /*
+ * ASIC reset has to be done on all HGMI hive nodes ASAP
+@@ -3809,21 +3820,24 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
+ */
+ if (need_full_reset) {
+ list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+- /* For XGMI run all resets in parallel to speed up the process */
++ /*
++ * For XGMI run all resets in parallel to speed up the
++ * process by scheduling the highpri wq on different
++ * cpus. For XGMI with baco reset, all nodes must enter
++ * baco within close proximity before anyone exit.
++ */
+ if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
+- if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
++ if (!queue_work_on(cpu, system_highpri_wq,
++ &tmp_adev->xgmi_reset_work))
+ r = -EALREADY;
++ cpu = cpumask_next(cpu, cpu_online_mask);
+ } else
+ r = amdgpu_asic_reset(tmp_adev);
+-
+- if (r) {
+- DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
+- r, tmp_adev->ddev->unique);
++ if (r)
+ break;
+- }
+ }
+
+- /* For XGMI wait for all PSP resets to complete before proceed */
++ /* For XGMI wait for all work to complete before proceed */
+ if (!r) {
+ list_for_each_entry(tmp_adev, device_list_handle,
+ gmc.xgmi.head) {
+@@ -3832,11 +3846,54 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
+ r = tmp_adev->asic_reset_res;
+ if (r)
+ break;
++ if (use_baco)
++ tmp_adev->in_baco = true;
+ }
+ }
+ }
+- }
+
++ /*
++ * For XGMI with baco reset, need exit baco phase by scheduling
++ * xgmi_reset_work one more time. PSP reset and sGPU skips this
++ * phase. Not assume the situation that PSP reset and baco reset
++ * coexist within an XGMI hive.
++ */
++
++ if (!r && use_baco) {
++ cpu = smp_processor_id();
++ list_for_each_entry(tmp_adev, device_list_handle,
++ gmc.xgmi.head) {
++ if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
++ if (!queue_work_on(cpu,
++ system_highpri_wq,
++ &tmp_adev->xgmi_reset_work))
++ r = -EALREADY;
++ if (r)
++ break;
++ cpu = cpumask_next(cpu, cpu_online_mask);
++ }
++ }
++ }
++
++ if (!r && use_baco) {
++ list_for_each_entry(tmp_adev, device_list_handle,
++ gmc.xgmi.head) {
++ if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
++ flush_work(&tmp_adev->xgmi_reset_work);
++ r = tmp_adev->asic_reset_res;
++ if (r)
++ break;
++ tmp_adev->in_baco = false;
++ }
++ }
++ }
++
++ if (r) {
++ DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
++ r, tmp_adev->ddev->unique);
++ goto end;
++ }
++ }
+
+ list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+ if (need_full_reset) {
+@@ -4121,7 +4178,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ if (r)
+ adev->asic_reset_res = r;
+ } else {
+- r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
++ r = amdgpu_do_asic_reset(adev, hive, device_list_handle,
++ &need_full_reset);
+ if (r && r == -EAGAIN)
+ goto retry;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4663-drm-amdgpu-support-full-gpu-reset-workflow-when-ras-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4663-drm-amdgpu-support-full-gpu-reset-workflow-when-ras-.patch
new file mode 100644
index 00000000..512f648a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4663-drm-amdgpu-support-full-gpu-reset-workflow-when-ras-.patch
@@ -0,0 +1,86 @@
+From f8258870fb3346e5920c15901858da7e88a7d29c Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 27 Nov 2019 13:17:17 +0800
+Subject: [PATCH 4663/4736] drm/amdgpu: support full gpu reset workflow when
+ ras err_event_athub occurs
+
+This athub fatal error can be recovered by baco without system-level reboot,
+so add a mode to use baco for the recovery. Not affect the default psp reset
+situations for now.
+
+Change-Id: Ib17f2a39254ff6b0473a785752adfdfea79d0e0d
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +++++++++++------
+ 1 file changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 2ca9d556c084..e20d324a6d90 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4026,12 +4026,15 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ struct amdgpu_device *tmp_adev = NULL;
+ int i, r = 0;
+ bool in_ras_intr = amdgpu_ras_intr_triggered();
++ bool use_baco =
++ (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
++ true : false;
+
+ /*
+ * Flush RAM to disk so that after reboot
+ * the user can read log and see why the system rebooted.
+ */
+- if (in_ras_intr && amdgpu_ras_get_context(adev)->reboot) {
++ if (in_ras_intr && !use_baco && amdgpu_ras_get_context(adev)->reboot) {
+
+ DRM_WARN("Emergency reboot.");
+
+@@ -4042,7 +4045,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ need_full_reset = job_signaled = false;
+ INIT_LIST_HEAD(&device_list);
+
+- dev_info(adev->dev, "GPU %s begin!\n", in_ras_intr ? "jobs stop":"reset");
++ dev_info(adev->dev, "GPU %s begin!\n",
++ (in_ras_intr && !use_baco) ? "jobs stop":"reset");
+
+ cancel_delayed_work_sync(&adev->delayed_init_work);
+
+@@ -4109,7 +4113,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ amdgpu_unregister_gpu_instance(tmp_adev);
+
+ /* disable ras on ALL IPs */
+- if (!in_ras_intr && amdgpu_device_ip_need_full_reset(tmp_adev))
++ if (!(in_ras_intr && !use_baco) &&
++ amdgpu_device_ip_need_full_reset(tmp_adev))
+ amdgpu_ras_suspend(tmp_adev);
+
+ for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+@@ -4120,13 +4125,13 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+
+ drm_sched_stop(&ring->sched, job ? &job->base : NULL);
+
+- if (in_ras_intr)
++ if (in_ras_intr && !use_baco)
+ amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
+ }
+ }
+
+
+- if (in_ras_intr)
++ if (in_ras_intr && !use_baco)
+ goto skip_sched_resume;
+
+ /*
+@@ -4220,7 +4225,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ skip_sched_resume:
+ list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+ /*unlock kfd: SRIOV would do it separately */
+- if (!in_ras_intr && !amdgpu_sriov_vf(tmp_adev))
++ if (!(in_ras_intr && !use_baco) && !amdgpu_sriov_vf(tmp_adev))
+ amdgpu_amdkfd_post_reset(tmp_adev);
+ amdgpu_device_unlock_adev(tmp_adev);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4664-drm-amdgpu-clear-err_event_athub-flag-after-reset-ex.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4664-drm-amdgpu-clear-err_event_athub-flag-after-reset-ex.patch
new file mode 100644
index 00000000..faeca608
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4664-drm-amdgpu-clear-err_event_athub-flag-after-reset-ex.patch
@@ -0,0 +1,52 @@
+From 5b46dfbb56ac49aece9d1a2f6175e7b9ef75e083 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 25 Oct 2019 17:19:38 +0800
+Subject: [PATCH 4664/4736] drm/amdgpu: clear err_event_athub flag after reset
+ exit
+
+Otherwise next err_event_athub error cannot call gpu reset. And following
+resume sequence will not be affected by this flag.
+
+v2: create function to clear amdgpu_ras_in_intr for modularity of ras driver
+
+Change-Id: I5cd293f30f23876bf2a1860681bcb50f47713ecd
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 +++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index e20d324a6d90..7bedbeb12627 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3895,6 +3895,9 @@ static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
+ }
+ }
+
++ if (!r && amdgpu_ras_intr_triggered())
++ amdgpu_ras_intr_cleared();
++
+ list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+ if (need_full_reset) {
+ /* post card */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index a2c1ac1b9572..d4ade4739245 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -621,6 +621,11 @@ static inline bool amdgpu_ras_intr_triggered(void)
+ return !!atomic_read(&amdgpu_ras_in_intr);
+ }
+
++static inline void amdgpu_ras_intr_cleared(void)
++{
++ atomic_set(&amdgpu_ras_in_intr, 0);
++}
++
+ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
+
+ #endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4665-drm-amdgpu-reduce-redundant-uvd-context-lost-warning.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4665-drm-amdgpu-reduce-redundant-uvd-context-lost-warning.patch
new file mode 100644
index 00000000..1041a49e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4665-drm-amdgpu-reduce-redundant-uvd-context-lost-warning.patch
@@ -0,0 +1,53 @@
+From 6a190b81b435736dbf4d2b6f12452132c624717a Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 27 Nov 2019 16:51:22 +0800
+Subject: [PATCH 4665/4736] drm/amdgpu: reduce redundant uvd context lost
+ warning message
+
+Move the print out of uvd instance loop in amdgpu_uvd_suspend
+
+v2: drop unnecessary brackets
+v3: grab ras_intr state once for multiple times use
+
+Change-Id: Ifad997debd84763e1b55d668e144b729598f115e
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index 32128e982e4c..04bc063ba1c7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -349,6 +349,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
+ unsigned size;
+ void *ptr;
+ int i, j;
++ bool in_ras_intr = amdgpu_ras_intr_triggered();
+
+ cancel_delayed_work_sync(&adev->uvd.idle_work);
+
+@@ -376,13 +377,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
+ return -ENOMEM;
+
+ /* re-write 0 since err_event_athub will corrupt VCPU buffer */
+- if (amdgpu_ras_intr_triggered()) {
+- DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
++ if (in_ras_intr)
+ memset(adev->uvd.inst[j].saved_bo, 0, size);
+- } else {
++ else
+ memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
+- }
+ }
++
++ if (in_ras_intr)
++ DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
++
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch
new file mode 100644
index 00000000..8517952d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch
@@ -0,0 +1,119 @@
+From d8de6521c6f1863d6c364855496b14593e66cda4 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Tue, 5 Nov 2019 11:59:38 -0500
+Subject: [PATCH 4666/4736] drm/amd/display: update sr and pstate latencies for
+ Renoir
+
+[Why]
+DF team has produced more optimized latency numbers.
+
+[How]
+Add sr latencies to the wm table, use different latencies
+for different wm sets.
+Also fix bb override from registery key for these latencies.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 ++++++++++++----
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 15 ++++++++++++---
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 ++
+ 3 files changed, 26 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 790a2d211bd6..841095d09d3c 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -523,25 +523,33 @@ struct clk_bw_params rn_bw_params = {
+ {
+ .wm_inst = WM_A,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 6.09,
++ .sr_enter_plus_exit_time_us = 7.14,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_B,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 10.12,
++ .sr_enter_plus_exit_time_us = 11.48,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_C,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 10.12,
++ .sr_enter_plus_exit_time_us = 11.48,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_D,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 10.12,
++ .sr_enter_plus_exit_time_us = 11.48,
+ .valid = true,
+ },
+ },
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 260471ac20c2..94a5611972cc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -972,6 +972,8 @@ static void calculate_wm_set_for_vlevel(
+ pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
+
+ dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
++ dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
++ dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
+
+ wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
+ wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
+@@ -989,14 +991,21 @@ static void calculate_wm_set_for_vlevel(
+
+ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
+ {
++ int i;
++
+ kernel_fpu_begin();
+ if (dc->bb_overrides.sr_exit_time_ns) {
+- bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
++ for (i = 0; i < WM_SET_COUNT; i++) {
++ dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
++ dc->bb_overrides.sr_exit_time_ns / 1000.0;
++ }
+ }
+
+ if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
+- bb->sr_enter_plus_exit_time_us =
+- dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
++ for (i = 0; i < WM_SET_COUNT; i++) {
++ dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
++ dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
++ }
+ }
+
+ if (dc->bb_overrides.urgent_latency_ns) {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 4e18e77dcf42..026e6a2a2c44 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -69,6 +69,8 @@ struct wm_range_table_entry {
+ unsigned int wm_inst;
+ unsigned int wm_type;
+ double pstate_latency_us;
++ double sr_exit_time_us;
++ double sr_enter_plus_exit_time_us;
+ bool valid;
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch
new file mode 100644
index 00000000..8a62c75b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch
@@ -0,0 +1,780 @@
+From 34231c7e48957fe66cb6f6469c55a2f267fda105 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 5 Nov 2019 13:04:34 -0500
+Subject: [PATCH 4667/4736] drm/amd/display: rename core_dc to dc
+
+[Why]
+First, to make code more consistent
+Second, to get rid of those scenario where we create a second
+local pointer to dc when it's already passed in.
+
+[How]
+Rename core_dc to dc
+Remove duplicate local pointers to dc
+
+Change-Id: Ibace3c21e3722d874f36567a2e240e2112ba2b17
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../dc/clk_mgr/dce112/dce112_clk_mgr.c | 12 ++--
+ .../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 6 +-
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 6 +-
+ .../gpu/drm/amd/display/dc/core/dc_debug.c | 7 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 64 +++++++++----------
+ .../drm/amd/display/dc/core/dc_link_hwss.c | 26 ++++----
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +-
+ .../gpu/drm/amd/display/dc/core/dc_stream.c | 40 ++++++------
+ .../gpu/drm/amd/display/dc/core/dc_surface.c | 22 +++----
+ .../display/dc/dce110/dce110_hw_sequencer.c | 8 +--
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +--
+ .../dc/irq/dce110/irq_service_dce110.c | 4 +-
+ 12 files changed, 102 insertions(+), 106 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+index a6c46e903ff9..d031bd3d3072 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+@@ -72,8 +72,8 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+ struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ struct bp_set_dce_clock_parameters dce_clk_params;
+ struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
+- struct dc *core_dc = clk_mgr_base->ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = clk_mgr_base->ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+ int actual_clock = requested_clk_khz;
+ /* Prepare to program display clock*/
+ memset(&dce_clk_params, 0, sizeof(dce_clk_params));
+@@ -110,7 +110,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+
+ bp->funcs->set_dce_clock(bp, &dce_clk_params);
+
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
+ dmcu->funcs->set_psr_wait_loop(dmcu,
+@@ -126,8 +126,8 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ {
+ struct bp_set_dce_clock_parameters dce_clk_params;
+ struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
+- struct dc *core_dc = clk_mgr->base.ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = clk_mgr->base.ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+ int actual_clock = requested_clk_khz;
+ /* Prepare to program display clock*/
+ memset(&dce_clk_params, 0, sizeof(dce_clk_params));
+@@ -152,7 +152,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+
+
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
+ dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+index 1897e91c8ccb..97b7f32294fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+@@ -88,8 +88,8 @@ int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned
+ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+ {
+ int actual_dispclk_set_mhz = -1;
+- struct dc *core_dc = clk_mgr->base.ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = clk_mgr->base.ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+
+ /* Unit of SMU msg parameter is Mhz */
+ actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
+@@ -100,7 +100,7 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di
+ /* Actual dispclk set is returned in the parameter register */
+ actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
+
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
+ dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index cb7c0e8b7e1b..6878aedf1d3e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -82,8 +82,8 @@ int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
+ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+ {
+ int actual_dispclk_set_mhz = -1;
+- struct dc *core_dc = clk_mgr->base.ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = clk_mgr->base.ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+
+ /* Unit of SMU msg parameter is Mhz */
+ actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+@@ -91,7 +91,7 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
+ VBIOSSMC_MSG_SetDispclkFreq,
+ requested_dispclk_khz / 1000);
+
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
+ dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+index b9227d5de3a3..5203159ad519 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+@@ -310,14 +310,13 @@ void context_timing_trace(
+ struct resource_context *res_ctx)
+ {
+ int i;
+- struct dc *core_dc = dc;
+ int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
+ struct crtc_position position;
+- unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
++ unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+
+- for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+ /* get_position() returns CRTC vertical/horizontal counter
+ * hence not applicable for underlay pipe
+@@ -329,7 +328,7 @@ void context_timing_trace(
+ h_pos[i] = position.horizontal_count;
+ v_pos[i] = position.vertical_count;
+ }
+- for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+
+ if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index f27921e46937..9f53cbcc7152 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2353,9 +2353,9 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ uint32_t backlight_pwm_u16_16,
+ uint32_t frame_ramp)
+ {
+- struct dc *core_dc = link->ctx->dc;
+- struct abm *abm = core_dc->res_pool->abm;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = link->ctx->dc;
++ struct abm *abm = dc->res_pool->abm;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+ unsigned int controller_id = 0;
+ bool use_smooth_brightness = true;
+ int i;
+@@ -2373,22 +2373,22 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+
+ if (dc_is_embedded_signal(link->connector_signal)) {
+ for (i = 0; i < MAX_PIPES; i++) {
+- if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
+- if (core_dc->current_state->res_ctx.
++ if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
++ if (dc->current_state->res_ctx.
+ pipe_ctx[i].stream->link
+ == link) {
+ /* DMCU -1 for all controller id values,
+ * therefore +1 here
+ */
+ controller_id =
+- core_dc->current_state->
++ dc->current_state->
+ res_ctx.pipe_ctx[i].stream_res.tg->inst +
+ 1;
+
+ /* Disable brightness ramping when the display is blanked
+ * as it can hang the DMCU
+ */
+- if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
++ if (dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
+ frame_ramp = 0;
+ }
+ }
+@@ -2406,8 +2406,8 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+
+ bool dc_link_set_abm_disable(const struct dc_link *link)
+ {
+- struct dc *core_dc = link->ctx->dc;
+- struct abm *abm = core_dc->res_pool->abm;
++ struct dc *dc = link->ctx->dc;
++ struct abm *abm = dc->res_pool->abm;
+
+ if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
+ return false;
+@@ -2419,8 +2419,8 @@ bool dc_link_set_abm_disable(const struct dc_link *link)
+
+ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
+ {
+- struct dc *core_dc = link->ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = link->ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+
+
+
+@@ -2434,8 +2434,8 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool
+
+ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
+ {
+- struct dc *core_dc = link->ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = link->ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+
+ if (dmcu != NULL && link->psr_feature_enabled)
+ dmcu->funcs->get_psr_state(dmcu, psr_state);
+@@ -2482,7 +2482,7 @@ bool dc_link_setup_psr(struct dc_link *link,
+ const struct dc_stream_state *stream, struct psr_config *psr_config,
+ struct psr_context *psr_context)
+ {
+- struct dc *core_dc;
++ struct dc *dc;
+ struct dmcu *dmcu;
+ int i;
+ /* updateSinkPsrDpcdConfig*/
+@@ -2493,8 +2493,8 @@ bool dc_link_setup_psr(struct dc_link *link,
+ if (!link)
+ return false;
+
+- core_dc = link->ctx->dc;
+- dmcu = core_dc->res_pool->dmcu;
++ dc = link->ctx->dc;
++ dmcu = dc->res_pool->dmcu;
+
+ if (!dmcu)
+ return false;
+@@ -2533,13 +2533,13 @@ bool dc_link_setup_psr(struct dc_link *link,
+ psr_context->engineId = link->link_enc->preferred_engine;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+- if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
++ if (dc->current_state->res_ctx.pipe_ctx[i].stream
+ == stream) {
+ /* dmcu -1 for all controller id values,
+ * therefore +1 here
+ */
+ psr_context->controllerId =
+- core_dc->current_state->res_ctx.
++ dc->current_state->res_ctx.
+ pipe_ctx[i].stream_res.tg->inst + 1;
+ break;
+ }
+@@ -2903,12 +2903,12 @@ void core_link_enable_stream(
+ struct dc_state *state,
+ struct pipe_ctx *pipe_ctx)
+ {
+- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++ struct dc *dc = pipe_ctx->stream->ctx->dc;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ enum dc_status status;
+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
+
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ return;
+
+@@ -2951,14 +2951,14 @@ void core_link_enable_stream(
+ pipe_ctx->stream_res.stream_enc,
+ &stream->timing);
+
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ bool apply_edp_fast_boot_optimization =
+ pipe_ctx->stream->apply_edp_fast_boot_optimization;
+
+ pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
+
+ resource_build_info_frame(pipe_ctx);
+- core_dc->hwss.update_info_frame(pipe_ctx);
++ dc->hwss.update_info_frame(pipe_ctx);
+
+ /* Do not touch link on seamless boot optimization. */
+ if (pipe_ctx->stream->apply_seamless_boot_optimization) {
+@@ -3001,7 +3001,7 @@ void core_link_enable_stream(
+ }
+ }
+
+- core_dc->hwss.enable_audio_stream(pipe_ctx);
++ dc->hwss.enable_audio_stream(pipe_ctx);
+
+ /* turn off otg test pattern if enable */
+ if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+@@ -3014,7 +3014,7 @@ void core_link_enable_stream(
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ dp_set_dsc_enable(pipe_ctx, true);
+ }
+- core_dc->hwss.enable_stream(pipe_ctx);
++ dc->hwss.enable_stream(pipe_ctx);
+
+ /* Set DPS PPS SDP (AKA "info frames") */
+ if (pipe_ctx->stream->timing.flags.DSC) {
+@@ -3026,7 +3026,7 @@ void core_link_enable_stream(
+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ dc_link_allocate_mst_payload(pipe_ctx);
+
+- core_dc->hwss.unblank_stream(pipe_ctx,
++ dc->hwss.unblank_stream(pipe_ctx,
+ &pipe_ctx->stream->link->cur_link_settings);
+
+ if (dc_is_dp_signal(pipe_ctx->stream->signal))
+@@ -3035,7 +3035,7 @@ void core_link_enable_stream(
+ update_psp_stream_config(pipe_ctx, false);
+ #endif
+ }
+- else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++ else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ dp_set_dsc_enable(pipe_ctx, true);
+@@ -3045,11 +3045,11 @@ void core_link_enable_stream(
+
+ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ {
+- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++ struct dc *dc = pipe_ctx->stream->ctx->dc;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct dc_link *link = stream->sink->link;
+
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ return;
+
+@@ -3057,7 +3057,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ update_psp_stream_config(pipe_ctx, true);
+ #endif
+
+- core_dc->hwss.blank_stream(pipe_ctx);
++ dc->hwss.blank_stream(pipe_ctx);
+
+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ deallocate_mst_payload(pipe_ctx);
+@@ -3086,7 +3086,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ write_i2c_redriver_setting(pipe_ctx, false);
+ }
+ }
+- core_dc->hwss.disable_stream(pipe_ctx);
++ dc->hwss.disable_stream(pipe_ctx);
+
+ disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+ if (pipe_ctx->stream->timing.flags.DSC) {
+@@ -3097,12 +3097,12 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+
+ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++ struct dc *dc = pipe_ctx->stream->ctx->dc;
+
+ if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
+ return;
+
+- core_dc->hwss.set_avmute(pipe_ctx, enable);
++ dc->hwss.set_avmute(pipe_ctx, enable);
+ }
+
+ /**
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index bb1e8e5b5252..67ce12df23f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -95,8 +95,8 @@ void dp_enable_link_phy(
+ const struct dc_link_settings *link_settings)
+ {
+ struct link_encoder *link_enc = link->link_enc;
+- struct dc *core_dc = link->ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = link->ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+
+ struct pipe_ctx *pipes =
+ link->dc->current_state->res_ctx.pipe_ctx;
+@@ -200,8 +200,8 @@ bool edp_receiver_ready_T7(struct dc_link *link)
+
+ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
+ {
+- struct dc *core_dc = link->ctx->dc;
+- struct dmcu *dmcu = core_dc->res_pool->dmcu;
++ struct dc *dc = link->ctx->dc;
++ struct dmcu *dmcu = dc->res_pool->dmcu;
+
+ if (!link->wa_flags.dp_keep_receiver_powered)
+ dp_receiver_power_ctrl(link, false);
+@@ -395,14 +395,14 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
+
+ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++ struct dc *dc = pipe_ctx->stream->ctx->dc;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ bool result = false;
+
+- if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ result = true;
+ else
+- result = dm_helpers_dp_write_dsc_enable(core_dc->ctx, stream, enable);
++ result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);
+ return result;
+ }
+
+@@ -412,7 +412,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++ struct dc *dc = pipe_ctx->stream->ctx->dc;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+@@ -448,7 +448,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+
+ /* Enable DSC in encoder */
+- if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
+ dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+@@ -473,7 +473,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ OPTC_DSC_DISABLED, 0, 0);
+
+ /* disable DSC in stream encoder */
+- if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
+ pipe_ctx->stream_res.stream_enc,
+ OPTC_DSC_DISABLED, 0, 0);
+@@ -516,7 +516,7 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
+ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+- struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++ struct dc *dc = pipe_ctx->stream->ctx->dc;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+
+ if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
+@@ -535,7 +535,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+
+ DC_LOG_DSC(" ");
+ dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
+- if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ pipe_ctx->stream_res.stream_enc,
+@@ -544,7 +544,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ }
+ } else {
+ /* disable DSC PPS in stream encoder */
+- if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ pipe_ctx->stream_res.stream_enc, false, NULL);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 081275a430ad..67d1c8cc583b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -2750,9 +2750,8 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
+
+ enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
+ {
+- struct dc *core_dc = dc;
+ struct dc_link *link = stream->link;
+- struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
++ struct timing_generator *tg = dc->res_pool->timing_generators[0];
+ enum dc_status res = DC_OK;
+
+ calculate_phy_pix_clks(stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 9029786c7b08..a43b4d7d5a50 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -268,7 +268,7 @@ bool dc_stream_set_cursor_attributes(
+ const struct dc_cursor_attributes *attributes)
+ {
+ int i;
+- struct dc *core_dc;
++ struct dc *dc;
+ struct resource_context *res_ctx;
+ struct pipe_ctx *pipe_to_program = NULL;
+
+@@ -286,8 +286,8 @@ bool dc_stream_set_cursor_attributes(
+ return false;
+ }
+
+- core_dc = stream->ctx->dc;
+- res_ctx = &core_dc->current_state->res_ctx;
++ dc = stream->ctx->dc;
++ res_ctx = &dc->current_state->res_ctx;
+ stream->cursor_attributes = *attributes;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+@@ -299,17 +299,17 @@ bool dc_stream_set_cursor_attributes(
+ if (!pipe_to_program) {
+ pipe_to_program = pipe_ctx;
+
+- delay_cursor_until_vupdate(pipe_ctx, core_dc);
+- core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
++ delay_cursor_until_vupdate(pipe_ctx, dc);
++ dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+ }
+
+- core_dc->hwss.set_cursor_attribute(pipe_ctx);
+- if (core_dc->hwss.set_cursor_sdr_white_level)
+- core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
++ dc->hwss.set_cursor_attribute(pipe_ctx);
++ if (dc->hwss.set_cursor_sdr_white_level)
++ dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
+ }
+
+ if (pipe_to_program)
+- core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
++ dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+
+ return true;
+ }
+@@ -319,7 +319,7 @@ bool dc_stream_set_cursor_position(
+ const struct dc_cursor_position *position)
+ {
+ int i;
+- struct dc *core_dc;
++ struct dc *dc;
+ struct resource_context *res_ctx;
+ struct pipe_ctx *pipe_to_program = NULL;
+
+@@ -333,8 +333,8 @@ bool dc_stream_set_cursor_position(
+ return false;
+ }
+
+- core_dc = stream->ctx->dc;
+- res_ctx = &core_dc->current_state->res_ctx;
++ dc = stream->ctx->dc;
++ res_ctx = &dc->current_state->res_ctx;
+ stream->cursor_position = *position;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+@@ -350,15 +350,15 @@ bool dc_stream_set_cursor_position(
+ if (!pipe_to_program) {
+ pipe_to_program = pipe_ctx;
+
+- delay_cursor_until_vupdate(pipe_ctx, core_dc);
+- core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
++ delay_cursor_until_vupdate(pipe_ctx, dc);
++ dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+ }
+
+- core_dc->hwss.set_cursor_position(pipe_ctx);
++ dc->hwss.set_cursor_position(pipe_ctx);
+ }
+
+ if (pipe_to_program)
+- core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
++ dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+
+ return true;
+ }
+@@ -479,9 +479,9 @@ bool dc_stream_remove_writeback(struct dc *dc,
+ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
+ {
+ uint8_t i;
+- struct dc *core_dc = stream->ctx->dc;
++ struct dc *dc = stream->ctx->dc;
+ struct resource_context *res_ctx =
+- &core_dc->current_state->res_ctx;
++ &dc->current_state->res_ctx;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
+@@ -538,9 +538,9 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ {
+ uint8_t i;
+ bool ret = false;
+- struct dc *core_dc = stream->ctx->dc;
++ struct dc *dc = stream->ctx->dc;
+ struct resource_context *res_ctx =
+- &core_dc->current_state->res_ctx;
++ &dc->current_state->res_ctx;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index 5904c459fe8f..834d6145aab4 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -106,16 +106,14 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
+
+ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
+ {
+- struct dc *core_dc = dc;
+-
+ struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
+- GFP_KERNEL);
++ GFP_KERNEL);
+
+ if (NULL == plane_state)
+ return NULL;
+
+ kref_init(&plane_state->refcount);
+- dc_plane_construct(core_dc->ctx, plane_state);
++ dc_plane_construct(dc->ctx, plane_state);
+
+ return plane_state;
+ }
+@@ -135,7 +133,7 @@ const struct dc_plane_status *dc_plane_get_status(
+ const struct dc_plane_state *plane_state)
+ {
+ const struct dc_plane_status *plane_status;
+- struct dc *core_dc;
++ struct dc *dc;
+ int i;
+
+ if (!plane_state ||
+@@ -146,15 +144,15 @@ const struct dc_plane_status *dc_plane_get_status(
+ }
+
+ plane_status = &plane_state->status;
+- core_dc = plane_state->ctx->dc;
++ dc = plane_state->ctx->dc;
+
+- if (core_dc->current_state == NULL)
++ if (dc->current_state == NULL)
+ return NULL;
+
+ /* Find the current plane state and set its pending bit to false */
+- for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx =
+- &core_dc->current_state->res_ctx.pipe_ctx[i];
++ &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->plane_state != plane_state)
+ continue;
+@@ -164,14 +162,14 @@ const struct dc_plane_status *dc_plane_get_status(
+ break;
+ }
+
+- for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx =
+- &core_dc->current_state->res_ctx.pipe_ctx[i];
++ &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->plane_state != plane_state)
+ continue;
+
+- core_dc->hwss.update_pending_status(pipe_ctx);
++ dc->hwss.update_pending_status(pipe_ctx);
+ }
+
+ return plane_status;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 6291f803cd16..ad53e6727df2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -942,15 +942,15 @@ void dce110_edp_backlight_control(
+ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ {
+ /* notify audio driver for audio modes of monitor */
+- struct dc *core_dc;
++ struct dc *dc;
+ struct clk_mgr *clk_mgr;
+ unsigned int i, num_audio = 1;
+
+ if (!pipe_ctx->stream)
+ return;
+
+- core_dc = pipe_ctx->stream->ctx->dc;
+- clk_mgr = core_dc->clk_mgr;
++ dc = pipe_ctx->stream->ctx->dc;
++ clk_mgr = dc->clk_mgr;
+
+ if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
+ return;
+@@ -958,7 +958,7 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ if (pipe_ctx->stream_res.audio) {
+ for (i = 0; i < MAX_PIPES; i++) {
+ /*current_state not updated yet*/
+- if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
++ if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
+ num_audio++;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 08d15982f526..1ed26ac33551 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1655,10 +1655,10 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ }
+
+ /*static void print_rq_dlg_ttu(
+- struct dc *core_dc,
++ struct dc *dc,
+ struct pipe_ctx *pipe_ctx)
+ {
+- DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ "\n============== DML TTU Output parameters [%d] ==============\n"
+ "qos_level_low_wm: %d, \n"
+ "qos_level_high_wm: %d, \n"
+@@ -1688,7 +1688,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
+ );
+
+- DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ "\n============== DML DLG Output parameters [%d] ==============\n"
+ "refcyc_h_blank_end: %d, \n"
+ "dlg_vblank_end: %d, \n"
+@@ -1723,7 +1723,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
+ );
+
+- DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ "\ndst_y_per_meta_row_nom_l: %d, \n"
+ "refcyc_per_meta_chunk_nom_l: %d, \n"
+ "refcyc_per_line_delivery_pre_l: %d, \n"
+@@ -1753,7 +1753,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
+ );
+
+- DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++ DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ "\n============== DML RQ Output parameters [%d] ==============\n"
+ "chunk_size: %d \n"
+ "min_chunk_size: %d \n"
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+index 80603e18ecd6..662266fc3edf 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+@@ -202,7 +202,7 @@ bool dce110_vblank_set(struct irq_service *irq_service,
+ bool enable)
+ {
+ struct dc_context *dc_ctx = irq_service->ctx;
+- struct dc *core_dc = irq_service->ctx->dc;
++ struct dc *dc = irq_service->ctx->dc;
+ enum dc_irq_source dal_irq_src =
+ dc_interrupt_to_irq_source(irq_service->ctx->dc,
+ info->src_id,
+@@ -210,7 +210,7 @@ bool dce110_vblank_set(struct irq_service *irq_service,
+ uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
+
+ struct timing_generator *tg =
+- core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
++ dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
+
+ if (enable) {
+ if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch
new file mode 100644
index 00000000..9fc92880
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch
@@ -0,0 +1,2772 @@
+From ff94007b6f9295e74823b8083017abfe9c10e5a5 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 5 Nov 2019 13:17:30 -0500
+Subject: [PATCH 4668/4736] drm/amd/display: add separate of private hwss
+ functions
+
+[Why]
+Some function pointers in the hwss function pointer table are
+meant to be hw sequencer entry points to be called from dc.
+
+However some of those function pointers are not meant to
+be entry points, but instead used as a code reuse/inheritance
+tool called directly by other hwss functions, not by dc.
+
+Therefore, we want a more clear separation of which functions
+we determine to be interface functions vs the functions we
+use within hwss.
+
+[How]
+DC interface functions will be stored in:
+ struct hw_sequencer_funcs
+Functions used within HWSS will be stored in:
+ struct hwseq_private_funcs
+
+Also compilation fix for CONFIG_DRM_AMD_DC_DCN2_0 and CONFIG_DRM_AMD_DC_DCN2_0
+are done
+Change-Id: Ia8d8be52879c996de697011d0d57feee11267a19
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/Makefile | 11 +-
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 56 ++-
+ .../gpu/drm/amd/display/dc/core/dc_debug.c | 1 -
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +-
+ .../gpu/drm/amd/display/dc/core/dc_stream.c | 9 +-
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +-
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 6 +-
+ .../display/dc/dce100/dce100_hw_sequencer.c | 3 +-
+ .../display/dc/dce100/dce100_hw_sequencer.h | 1 +
+ .../display/dc/dce110/dce110_hw_sequencer.c | 81 ++--
+ .../display/dc/dce110/dce110_hw_sequencer.h | 1 +
+ .../amd/display/dc/dce110/dce110_resource.c | 3 +-
+ .../display/dc/dce112/dce112_hw_sequencer.c | 2 +-
+ .../display/dc/dce112/dce112_hw_sequencer.h | 1 +
+ .../display/dc/dce120/dce120_hw_sequencer.c | 2 +-
+ .../display/dc/dce120/dce120_hw_sequencer.h | 1 +
+ .../amd/display/dc/dce80/dce80_hw_sequencer.c | 2 +-
+ .../amd/display/dc/dce80/dce80_hw_sequencer.h | 1 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 128 +++---
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 1 +
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 38 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 71 ++--
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 3 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 54 +--
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 1 +
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.h | 2 +
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 63 +--
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 385 +++++-------------
+ .../amd/display/dc/inc/hw_sequencer_private.h | 156 +++++++
+ 29 files changed, 613 insertions(+), 475 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 38ef29719400..57e12b6c48fa 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -25,9 +25,16 @@
+
+ DC_LIBS = basics bios calcs clk_mgr dce gpio irq virtual
+
+-ifdef CONFIG_DRM_AMD_DC_DCN1_0
++ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DC_LIBS += dcn20
++endif
++
++
++ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DC_LIBS += dsc
++endif
++
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DC_LIBS += dcn10 dml
+ endif
+
+@@ -53,7 +60,7 @@ include $(AMD_DC)
+ DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
+ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+
+-ifdef CONFIG_DRM_AMD_DC_DCN1_0
++ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DISPLAY_CORE += dc_vm_helper.o
+ endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 09184adfccc8..e5cbc5bf3290 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -57,9 +57,13 @@
+ #include "dc_link_dp.h"
+ #include "dc_dmub_srv.h"
+
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
++#endif
+
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #include "vm_helper.h"
++#endif
+
+ #include "dce/dce_i2c.h"
+
+@@ -571,8 +575,10 @@ static void dc_destruct(struct dc *dc)
+ dc->dcn_ip = NULL;
+
+ #endif
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ kfree(dc->vm_helper);
+ dc->vm_helper = NULL;
++#endif
+
+ }
+
+@@ -590,8 +596,10 @@ static bool dc_construct(struct dc *dc,
+ enum dce_version dc_version = DCE_VERSION_UNKNOWN;
+ dc->config = init_params->flags;
+
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ // Allocate memory for the vm_helper
+ dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
++#endif
+
+ memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
+
+@@ -626,7 +634,9 @@ static bool dc_construct(struct dc *dc,
+ }
+
+ dc->dcn_ip = dcn_ip;
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ dc->soc_bounding_box = init_params->soc_bounding_box;
++#endif
+ #endif
+
+ dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
+@@ -728,6 +738,7 @@ static bool dc_construct(struct dc *dc,
+ return false;
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static bool disable_all_writeback_pipes_for_stream(
+ const struct dc *dc,
+ struct dc_stream_state *stream,
+@@ -740,6 +751,7 @@ static bool disable_all_writeback_pipes_for_stream(
+
+ return true;
+ }
++#endif
+
+ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ {
+@@ -765,12 +777,16 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ }
+ if (should_disable && old_stream) {
+ dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
++#endif
+ if (dc->hwss.apply_ctx_for_surface)
+ dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
+ }
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, dangling_context);
++#endif
+ }
+
+ current_ctx = dc->current_state;
+@@ -1160,8 +1176,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ context->stream_status[i].plane_count,
+ context); /* use new pipe config in new context */
+ }
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
+
+ /* Program hardware */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+@@ -1180,8 +1198,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ }
+
+ /* Program all planes within new context*/
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
+ for (i = 0; i < context->stream_count; i++) {
+ const struct dc_link *link = context->streams[i]->link;
+
+@@ -1665,8 +1685,10 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ if (stream_update->gamut_remap)
+ su_flags->bits.gamut_remap = 1;
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (stream_update->wb_update)
+ su_flags->bits.wb_update = 1;
++#endif
+ if (su_flags->raw != 0)
+ overall_type = UPDATE_TYPE_FULL;
+
+@@ -1834,6 +1856,7 @@ static void copy_surface_update_to_plane(
+ sizeof(struct dc_transfer_func_distributed_points));
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (srf_update->func_shaper &&
+ (surface->in_shaper_func !=
+ srf_update->func_shaper))
+@@ -1855,6 +1878,7 @@ static void copy_surface_update_to_plane(
+ srf_update->blend_tf))
+ memcpy(surface->blend_tf, srf_update->blend_tf,
+ sizeof(*surface->blend_tf));
++#endif
+
+ if (srf_update->input_csc_color_matrix)
+ surface->input_csc_color_matrix =
+@@ -1932,6 +1956,7 @@ static void copy_stream_update_to_stream(struct dc *dc,
+
+ if (update->dither_option)
+ stream->dither_option = *update->dither_option;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* update current stream with writeback info */
+ if (update->wb_update) {
+ int i;
+@@ -1942,6 +1967,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ stream->writeback_info[i] =
+ update->wb_update->writeback_info[i];
+ }
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ if (update->dsc_config) {
+ struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
+ uint32_t old_dsc_enabled = stream->timing.flags.DSC;
+@@ -1968,6 +1995,7 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ update->dsc_config = NULL;
+ }
+ }
++#endif
+ }
+
+ static void commit_planes_do_stream_update(struct dc *dc,
+@@ -2001,6 +2029,12 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ dc->hwss.update_info_frame(pipe_ctx);
+ }
+
++ if (stream_update->hdr_static_metadata &&
++ stream->use_dynamic_meta &&
++ dc->hwss.set_dmdata_attributes &&
++ pipe_ctx->stream->dmdata_address.quad_part != 0)
++ dc->hwss.set_dmdata_attributes(pipe_ctx);
++
+ if (stream_update->gamut_remap)
+ dc_stream_set_gamut_remap(dc, stream);
+
+@@ -2008,25 +2042,30 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ dc_stream_program_csc_matrix(dc, stream);
+
+ if (stream_update->dither_option) {
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
++#endif
+ resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+ &pipe_ctx->stream->bit_depth_params);
+ pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ while (odm_pipe) {
+ odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
++#endif
+ }
+-
++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) {
+ dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true);
+ dp_update_dsc_config(pipe_ctx);
+ dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false);
+ }
++#endif
+ /* Full fe update*/
+ if (update_type == UPDATE_TYPE_FAST)
+ continue;
+@@ -2113,12 +2152,14 @@ static void commit_planes_for_stream(struct dc *dc,
+ */
+ if (dc->hwss.apply_ctx_for_surface)
+ dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx)
+ dc->hwss.program_front_end_for_ctx(dc, context);
+-
++#endif
+ return;
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+ for (i = 0; i < surface_count; i++) {
+ struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2140,6 +2181,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ }
+ }
+ }
++#endif
+
+ // Update Type FULL, Surface updates
+ for (j = 0; j < dc->res_pool->pipe_count; j++) {
+@@ -2160,6 +2202,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ if (update_type == UPDATE_TYPE_FAST)
+ continue;
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
+
+ if (dc->hwss.program_triplebuffer != NULL &&
+@@ -2168,6 +2211,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ dc->hwss.program_triplebuffer(
+ dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
+ }
++#endif
+ stream_status =
+ stream_get_status(context, pipe_ctx->stream);
+
+@@ -2176,6 +2220,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ dc, pipe_ctx->stream, stream_status->plane_count, context);
+ }
+ }
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ dc->hwss.program_front_end_for_ctx(dc, context);
+ #ifdef CONFIG_DRM_AMD_DC_DCN1_0
+@@ -2194,6 +2239,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ }
+ #endif
+ }
++#endif
+
+ // Update Type FAST, Surface updates
+ if (update_type == UPDATE_TYPE_FAST) {
+@@ -2203,6 +2249,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ */
+ dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.set_flip_control_gsl)
+ for (i = 0; i < surface_count; i++) {
+ struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2221,6 +2268,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ plane_state->flip_immediate);
+ }
+ }
++#endif
+ /* Perform requested Updates */
+ for (i = 0; i < surface_count; i++) {
+ struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2233,6 +2281,7 @@ static void commit_planes_for_stream(struct dc *dc,
+
+ if (pipe_ctx->plane_state != plane_state)
+ continue;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /*program triple buffer after lock based on flip type*/
+ if (dc->hwss.program_triplebuffer != NULL &&
+ !dc->debug.disable_tri_buf) {
+@@ -2240,6 +2289,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ dc->hwss.program_triplebuffer(
+ dc, pipe_ctx, plane_state->triplebuffer_flips);
+ }
++#endif
+ if (srf_updates[i].flip_addr)
+ dc->hwss.update_plane_addr(dc, pipe_ctx);
+ }
+@@ -2405,10 +2455,12 @@ void dc_set_power_state(
+
+ dc->hwss.init_hw(dc);
+
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ if (dc->hwss.init_sys_ctx != NULL &&
+ dc->vm_pa_config.valid) {
+ dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
+ }
++#endif
+
+ break;
+ default:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+index 5203159ad519..c371e553a476 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+@@ -33,7 +33,6 @@
+
+ #include "core_status.h"
+ #include "core_types.h"
+-#include "hw_sequencer.h"
+
+ #include "resource.h"
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 67d1c8cc583b..fd9358c11222 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -161,10 +161,11 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
+ res_pool = dcn10_create_resource_pool(init_data, dc);
+ break;
+
+-
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case DCN_VERSION_2_0:
+ res_pool = dcn20_create_resource_pool(init_data, dc);
+ break;
++#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case DCN_VERSION_2_1:
+ res_pool = dcn21_create_resource_pool(init_data, dc);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index a43b4d7d5a50..8eb441388335 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -30,9 +30,6 @@
+ #include "resource.h"
+ #include "ipp.h"
+ #include "timing_generator.h"
+-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+-#include "dcn10/dcn10_hw_sequencer.h"
+-#endif
+
+ #define DC_LOGGER dc->ctx->logger
+
+@@ -106,6 +103,7 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ /* EDID CAP translation for HDMI 2.0 */
+ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
+
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
+ stream->timing.dsc_cfg.num_slices_h = 0;
+ stream->timing.dsc_cfg.num_slices_v = 0;
+@@ -114,6 +112,7 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ stream->timing.dsc_cfg.linebuf_depth = 9;
+ stream->timing.dsc_cfg.version_minor = 2;
+ stream->timing.dsc_cfg.ycbcr422_simple = 0;
++#endif
+
+ update_stream_signal(stream, dc_sink_data);
+
+@@ -363,6 +362,7 @@ bool dc_stream_set_cursor_position(
+ return true;
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_add_writeback(struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_writeback_info *wb_info)
+@@ -475,6 +475,7 @@ bool dc_stream_remove_writeback(struct dc *dc,
+
+ return true;
+ }
++#endif
+
+ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
+ {
+@@ -561,6 +562,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ return ret;
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ {
+ struct pipe_ctx *pipe = NULL;
+@@ -621,6 +623,7 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+
+ return true;
+ }
++#endif
+
+ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+index 0275d6d60da4..e1c5839a80dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+@@ -25,7 +25,7 @@
+
+ #include "dce_hwseq.h"
+ #include "reg_helper.h"
+-#include "hw_sequencer.h"
++#include "hw_sequencer_private.h"
+ #include "core_types.h"
+
+ #define CTX \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 7e3dde764111..a3491fab05f6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -25,7 +25,7 @@
+ #ifndef __DCE_HWSEQ_H__
+ #define __DCE_HWSEQ_H__
+
+-#include "hw_sequencer.h"
++#include "dc_types.h"
+
+ #define BL_REG_LIST()\
+ SR(LVTMA_PWRSEQ_CNTL), \
+@@ -815,6 +815,10 @@ enum blnd_mode {
+ BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ };
+
++struct dce_hwseq;
++struct pipe_ctx;
++struct clock_source;
++
+ void dce_enable_fe_clock(struct dce_hwseq *hwss,
+ unsigned int inst, bool enable);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+index 799d36299c9b..753cb8edd996 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+@@ -26,7 +26,6 @@
+ #include "dc.h"
+ #include "core_types.h"
+ #include "clk_mgr.h"
+-#include "hw_sequencer.h"
+ #include "dce100_hw_sequencer.h"
+ #include "resource.h"
+
+@@ -136,7 +135,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
+ {
+ dce110_hw_sequencer_construct(dc);
+
+- dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
++ dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
+ dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
+ dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+index a6b80fdaa666..34518da20009 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE100_H__
+
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+
+ struct dc;
+ struct dc_state;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index ad53e6727df2..f95c122c197b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -650,10 +650,9 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
+ {
+ enum dc_lane_count lane_count =
+ pipe_ctx->stream->link->cur_link_settings.lane_count;
+-
+ struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
+ struct dc_link *link = pipe_ctx->stream->link;
+-
++ const struct dc *dc = link->dc;
+
+ uint32_t active_total_with_borders;
+ uint32_t early_control = 0;
+@@ -666,7 +665,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
+ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+ pipe_ctx->stream_res.stream_enc->id, true);
+
+- link->dc->hwss.update_info_frame(pipe_ctx);
++ dc->hwss.update_info_frame(pipe_ctx);
+
+ /* enable early control to avoid corruption on DP monitor*/
+ active_total_with_borders =
+@@ -1046,6 +1045,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
+ struct encoder_unblank_param params = { { 0 } };
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct dc_link *link = stream->link;
++ struct dce_hwseq *hws = link->dc->hwseq;
+
+ /* only 3 items below are used by unblank */
+ params.timing = pipe_ctx->stream->timing;
+@@ -1055,7 +1055,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
+ pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
+
+ if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+- link->dc->hwss.edp_backlight_control(link, true);
++ hws->funcs.edp_backlight_control(link, true);
+ }
+ }
+
+@@ -1063,9 +1063,10 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
+ {
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct dc_link *link = stream->link;
++ struct dce_hwseq *hws = link->dc->hwseq;
+
+ if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+- link->dc->hwss.edp_backlight_control(link, false);
++ hws->funcs.edp_backlight_control(link, false);
+ dc_link_set_abm_disable(link);
+ }
+
+@@ -1321,10 +1322,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct drr_params params = {0};
+ unsigned int event_triggers = 0;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
++#endif
++ struct dce_hwseq *hws = dc->hwseq;
+
+- if (dc->hwss.disable_stream_gating) {
+- dc->hwss.disable_stream_gating(dc, pipe_ctx);
++ if (hws->funcs.disable_stream_gating) {
++ hws->funcs.disable_stream_gating(dc, pipe_ctx);
+ }
+
+ if (pipe_ctx->stream_res.audio != NULL) {
+@@ -1354,10 +1358,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ /* */
+ /* Do not touch stream timing on seamless boot optimization. */
+ if (!pipe_ctx->stream->apply_seamless_boot_optimization)
+- dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
++ hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
+
+- if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++ if (hws->funcs.setup_vupdate_interrupt)
++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
+@@ -1387,6 +1391,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ pipe_ctx->stream_res.opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ while (odm_pipe) {
+ odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
+ odm_pipe->stream_res.opp,
+@@ -1400,6 +1405,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ &stream->clamping);
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
++#endif
+
+ if (!stream->dpms_off)
+ core_link_enable_stream(context, pipe_ctx);
+@@ -1550,9 +1556,10 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
+ bool can_apply_edp_fast_boot = false;
+ bool can_apply_seamless_boot = false;
+ bool keep_edp_vdd_on = false;
++ struct dce_hwseq *hws = dc->hwseq;
+
+- if (dc->hwss.init_pipes)
+- dc->hwss.init_pipes(dc, context);
++ if (hws->funcs.init_pipes)
++ hws->funcs.init_pipes(dc, context);
+
+ edp_stream = get_edp_stream(context);
+
+@@ -1589,7 +1596,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
+ if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
+ if (edp_link_with_sink && !keep_edp_vdd_on) {
+ /*turn off backlight before DP_blank and encoder powered down*/
+- dc->hwss.edp_backlight_control(edp_link_with_sink, false);
++ hws->funcs.edp_backlight_control(edp_link_with_sink, false);
+ }
+ /*resume from S3, no vbios posting, no need to power down again*/
+ power_down_all_hw_blocks(dc);
+@@ -2004,13 +2011,14 @@ enum dc_status dce110_apply_ctx_to_hw(
+ struct dc *dc,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct dc_bios *dcb = dc->ctx->dc_bios;
+ enum dc_status status;
+ int i;
+
+ /* Reset old context */
+ /* look up the targets that have been removed since last commit */
+- dc->hwss.reset_hw_ctx_wrap(dc, context);
++ hws->funcs.reset_hw_ctx_wrap(dc, context);
+
+ /* Skip applying if no targets */
+ if (context->stream_count <= 0)
+@@ -2035,7 +2043,7 @@ enum dc_status dce110_apply_ctx_to_hw(
+ continue;
+ }
+
+- dc->hwss.enable_display_power_gating(
++ hws->funcs.enable_display_power_gating(
+ dc, i, dc->ctx->dc_bios,
+ PIPE_GATING_CONTROL_DISABLE);
+ }
+@@ -2344,19 +2352,20 @@ static void init_hw(struct dc *dc)
+ struct transform *xfm;
+ struct abm *abm;
+ struct dmcu *dmcu;
++ struct dce_hwseq *hws = dc->hwseq;
+
+ bp = dc->ctx->dc_bios;
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ xfm = dc->res_pool->transforms[i];
+ xfm->funcs->transform_reset(xfm);
+
+- dc->hwss.enable_display_power_gating(
++ hws->funcs.enable_display_power_gating(
+ dc, i, bp,
+ PIPE_GATING_CONTROL_INIT);
+- dc->hwss.enable_display_power_gating(
++ hws->funcs.enable_display_power_gating(
+ dc, i, bp,
+ PIPE_GATING_CONTROL_DISABLE);
+- dc->hwss.enable_display_pipe_clock_gating(
++ hws->funcs.enable_display_pipe_clock_gating(
+ dc->ctx,
+ true);
+ }
+@@ -2442,6 +2451,8 @@ static void dce110_program_front_end_for_pipe(
+ struct xfm_grph_csc_adjustment adjust;
+ struct out_csc_color_matrix tbl_entry;
+ unsigned int i;
++ struct dce_hwseq *hws = dc->hwseq;
++
+ DC_LOGGER_INIT();
+ memset(&tbl_entry, 0, sizeof(tbl_entry));
+
+@@ -2500,10 +2511,10 @@ static void dce110_program_front_end_for_pipe(
+ if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+- dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
++ hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+- dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
++ hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+
+ DC_LOG_SURFACE(
+ "Pipe:%d %p: addr hi:0x%x, "
+@@ -2606,6 +2617,7 @@ static void dce110_apply_ctx_for_surface(
+
+ static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ int fe_idx = pipe_ctx->plane_res.mi ?
+ pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
+
+@@ -2613,7 +2625,7 @@ static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
+ return;
+
+- dc->hwss.enable_display_power_gating(
++ hws->funcs.enable_display_power_gating(
+ dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
+
+ dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
+@@ -2702,14 +2714,10 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ .program_gamut_remap = program_gamut_remap,
+ .program_output_csc = program_output_csc,
+ .init_hw = init_hw,
+- .init_pipes = init_pipes,
+ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
+ .update_plane_addr = update_plane_addr,
+ .update_pending_status = dce110_update_pending_status,
+- .set_input_transfer_func = dce110_set_input_transfer_func,
+- .set_output_transfer_func = dce110_set_output_transfer_func,
+- .power_down = dce110_power_down,
+ .enable_accelerated_mode = dce110_enable_accelerated_mode,
+ .enable_timing_synchronization = dce110_enable_timing_synchronization,
+ .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
+@@ -2720,8 +2728,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ .blank_stream = dce110_blank_stream,
+ .enable_audio_stream = dce110_enable_audio_stream,
+ .disable_audio_stream = dce110_disable_audio_stream,
+- .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
+- .enable_display_power_gating = dce110_enable_display_power_gating,
+ .disable_plane = dce110_power_down_fe,
+ .pipe_control_lock = dce_pipe_control_lock,
+ .prepare_bandwidth = dce110_prepare_bandwidth,
+@@ -2729,22 +2735,33 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ .set_drr = set_drr,
+ .get_position = get_position,
+ .set_static_screen_control = set_static_screen_control,
+- .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
+- .enable_stream_timing = dce110_enable_stream_timing,
+- .disable_stream_gating = NULL,
+- .enable_stream_gating = NULL,
+ .setup_stereo = NULL,
+ .set_avmute = dce110_set_avmute,
+ .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+- .edp_backlight_control = dce110_edp_backlight_control,
+ .edp_power_control = dce110_edp_power_control,
+ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ .set_cursor_position = dce110_set_cursor_position,
+ .set_cursor_attribute = dce110_set_cursor_attribute
+ };
+
++static const struct hwseq_private_funcs dce110_private_funcs = {
++ .init_pipes = init_pipes,
++ .update_plane_addr = update_plane_addr,
++ .set_input_transfer_func = dce110_set_input_transfer_func,
++ .set_output_transfer_func = dce110_set_output_transfer_func,
++ .power_down = dce110_power_down,
++ .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
++ .enable_display_power_gating = dce110_enable_display_power_gating,
++ .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
++ .enable_stream_timing = dce110_enable_stream_timing,
++ .disable_stream_gating = NULL,
++ .enable_stream_gating = NULL,
++ .edp_backlight_control = dce110_edp_backlight_control,
++};
++
+ void dce110_hw_sequencer_construct(struct dc *dc)
+ {
+ dc->hwss = dce110_funcs;
++ dc->hwseq->funcs = dce110_private_funcs;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index c639e1680b7b..26a9c14a58b1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE110_H__
+
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+
+ struct dc;
+ struct dc_state;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 762f97b48f0f..75ffea78c6cc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1095,6 +1095,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
+ struct dc_stream_state *stream)
+ {
+ struct dc *dc = stream->ctx->dc;
++ struct dce_hwseq *hws = dc->hwseq;
+ struct resource_context *res_ctx = &context->res_ctx;
+ unsigned int underlay_idx = pool->underlay_pipe_index;
+ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
+@@ -1115,7 +1116,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
+ struct tg_color black_color = {0};
+ struct dc_bios *dcb = dc->ctx->dc_bios;
+
+- dc->hwss.enable_display_power_gating(
++ hws->funcs.enable_display_power_gating(
+ dc,
+ pipe_ctx->stream_res.tg->inst,
+ dcb, PIPE_GATING_CONTROL_DISABLE);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+index 1e4a7c13f0ed..19873ee1f78d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+@@ -158,6 +158,6 @@ void dce112_hw_sequencer_construct(struct dc *dc)
+ * structure
+ */
+ dce110_hw_sequencer_construct(dc);
+- dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
++ dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+index e646f4a37fa2..943f1b2c5b2f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE112_H__
+
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+
+ struct dc;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+index 1ca30928025e..66a13aa39c95 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+@@ -265,7 +265,7 @@ void dce120_hw_sequencer_construct(struct dc *dc)
+ * structure
+ */
+ dce110_hw_sequencer_construct(dc);
+- dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
++ dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;
+ dc->hwss.update_dchub = dce120_update_dchub;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+index c51afbd0b012..bc024534732f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE120_H__
+
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+
+ struct dc;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+index c4543178ba20..893261c81854 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+@@ -74,7 +74,7 @@ void dce80_hw_sequencer_construct(struct dc *dc)
+ {
+ dce110_hw_sequencer_construct(dc);
+
+- dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
++ dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
+ dc->hwss.pipe_control_lock = dce_pipe_control_lock;
+ dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
+ dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
+index 7a1b31def66f..e43af832d00c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE80_H__
+
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+
+ struct dc;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 1ed26ac33551..528a6a953be4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -641,8 +641,8 @@ static void power_on_plane(
+ if (REG(DC_IP_REQUEST_CNTL)) {
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 1);
+- hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
+- hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
++ hws->funcs.dpp_pg_control(hws, plane_id, true);
++ hws->funcs.hubp_pg_control(hws, plane_id, true);
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 0);
+ DC_LOG_DEBUG(
+@@ -663,7 +663,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 1);
+
+- dc->hwss.hubp_pg_control(hws, 0, false);
++ hws->funcs.hubp_pg_control(hws, 0, false);
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 0);
+
+@@ -692,7 +692,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 1);
+
+- dc->hwss.hubp_pg_control(hws, 0, true);
++ hws->funcs.hubp_pg_control(hws, 0, true);
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 0);
+
+@@ -702,14 +702,16 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+
+ void dcn10_bios_golden_init(struct dc *dc)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct dc_bios *bp = dc->ctx->dc_bios;
+ int i;
+ bool allow_self_fresh_force_enable = true;
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+- if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
++ if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))
+ return;
+ #endif
++
+ if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
+ allow_self_fresh_force_enable =
+ dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
+@@ -1016,6 +1018,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)
+ /* trigger HW to start disconnect plane from stream on the next vsync */
+ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ int dpp_id = pipe_ctx->plane_res.dpp->inst;
+ struct mpc *mpc = dc->res_pool->mpc;
+@@ -1040,7 +1043,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ hubp->funcs->hubp_disconnect(hubp);
+
+ if (dc->debug.sanity_checks)
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+
+ void dcn10_plane_atomic_power_down(struct dc *dc,
+@@ -1053,8 +1056,8 @@ void dcn10_plane_atomic_power_down(struct dc *dc,
+ if (REG(DC_IP_REQUEST_CNTL)) {
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 1);
+- dc->hwss.dpp_pg_control(hws, dpp->inst, false);
+- dc->hwss.hubp_pg_control(hws, hubp->inst, false);
++ hws->funcs.dpp_pg_control(hws, dpp->inst, false);
++ hws->funcs.hubp_pg_control(hws, hubp->inst, false);
+ dpp->funcs->dpp_reset(dpp);
+ REG_SET(DC_IP_REQUEST_CNTL, 0,
+ IP_REQUEST_EN, 0);
+@@ -1068,6 +1071,7 @@ void dcn10_plane_atomic_power_down(struct dc *dc,
+ */
+ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ int opp_id = hubp->opp_id;
+@@ -1086,7 +1090,7 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ hubp->power_gated = true;
+ dc->optimized_required = false; /* We're powering off, no need to optimize */
+
+- dc->hwss.plane_atomic_power_down(dc,
++ hws->funcs.plane_atomic_power_down(dc,
+ pipe_ctx->plane_res.dpp,
+ pipe_ctx->plane_res.hubp);
+
+@@ -1100,12 +1104,13 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+
+ void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
+ return;
+
+- dc->hwss.plane_atomic_disable(dc, pipe_ctx);
++ hws->funcs.plane_atomic_disable(dc, pipe_ctx);
+
+ apply_DEGVIDCN10_253_wa(dc);
+
+@@ -1116,6 +1121,7 @@ void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ {
+ int i;
++ struct dce_hwseq *hws = dc->hwseq;
+ bool can_apply_seamless_boot = false;
+
+ for (i = 0; i < context->stream_count; i++) {
+@@ -1140,8 +1146,8 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ * command table.
+ */
+ if (tg->funcs->is_tg_enabled(tg)) {
+- if (dc->hwss.init_blank != NULL) {
+- dc->hwss.init_blank(dc, tg);
++ if (hws->funcs.init_blank != NULL) {
++ hws->funcs.init_blank(dc, tg);
+ tg->funcs->lock(tg);
+ } else {
+ tg->funcs->lock(tg);
+@@ -1198,7 +1204,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+
+- dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
++ hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
+
+ if (tg->funcs->is_tg_enabled(tg))
+ tg->funcs->unlock(tg);
+@@ -1244,15 +1250,15 @@ void dcn10_init_hw(struct dc *dc)
+ }
+
+ //Enable ability to power gate / don't force power on permanently
+- dc->hwss.enable_power_gating_plane(hws, true);
++ hws->funcs.enable_power_gating_plane(hws, true);
+
+ return;
+ }
+
+ if (!dcb->funcs->is_accelerated_mode(dcb))
+- dc->hwss.disable_vga(dc->hwseq);
++ hws->funcs.disable_vga(dc->hwseq);
+
+- dc->hwss.bios_golden_init(dc);
++ hws->funcs.bios_golden_init(dc);
+ if (dc->ctx->dc_bios->fw_info_valid) {
+ res_pool->ref_clocks.xtalin_clock_inKhz =
+ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+@@ -1293,10 +1299,12 @@ void dcn10_init_hw(struct dc *dc)
+ link->link_status.link_active = true;
+ }
+
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* Power gate DSCs */
+ for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+- if (dc->hwss.dsc_pg_control != NULL)
+- dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++ if (hws->funcs.dsc_pg_control != NULL)
++ hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++#endif
+
+ /* If taking control over from VBIOS, we may want to optimize our first
+ * mode set, so we need to skip powering down pipes until we know which
+@@ -1305,7 +1313,7 @@ void dcn10_init_hw(struct dc *dc)
+ * everything down.
+ */
+ if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+- dc->hwss.init_pipes(dc, dc->current_state);
++ hws->funcs.init_pipes(dc, dc->current_state);
+ }
+
+ for (i = 0; i < res_pool->audio_count; i++) {
+@@ -1337,7 +1345,7 @@ void dcn10_init_hw(struct dc *dc)
+ REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ }
+
+- dc->hwss.enable_power_gating_plane(dc->hwseq, true);
++ hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
+ if (dc->clk_mgr->funcs->notify_wm_ranges)
+ dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
+@@ -1349,6 +1357,7 @@ void dcn10_reset_hw_ctx_wrap(
+ struct dc_state *context)
+ {
+ int i;
++ struct dce_hwseq *hws = dc->hwseq;
+
+ /* Reset Back End*/
+ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
+@@ -1367,8 +1376,8 @@ void dcn10_reset_hw_ctx_wrap(
+ struct clock_source *old_clk = pipe_ctx_old->clock_source;
+
+ dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
+- if (dc->hwss.enable_stream_gating)
+- dc->hwss.enable_stream_gating(dc, pipe_ctx);
++ if (hws->funcs.enable_stream_gating)
++ hws->funcs.enable_stream_gating(dc, pipe_ctx);
+ if (old_clk)
+ old_clk->funcs->cs_power_down(old_clk);
+ }
+@@ -1545,6 +1554,8 @@ void dcn10_pipe_control_lock(
+ struct pipe_ctx *pipe,
+ bool lock)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
++
+ /* use TG master update lock to lock everything on the TG
+ * therefore only top pipe need to lock
+ */
+@@ -1552,7 +1563,7 @@ void dcn10_pipe_control_lock(
+ return;
+
+ if (dc->debug.sanity_checks)
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+
+ if (lock)
+ pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
+@@ -1560,7 +1571,7 @@ void dcn10_pipe_control_lock(
+ pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
+
+ if (dc->debug.sanity_checks)
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+
+ static bool wait_for_reset_trigger_to_occur(
+@@ -1868,7 +1879,7 @@ static void dcn10_enable_plane(
+ struct dce_hwseq *hws = dc->hwseq;
+
+ if (dc->debug.sanity_checks) {
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+
+ undo_DEGVIDCN10_253_wa(dc);
+@@ -1925,7 +1936,7 @@ static void dcn10_enable_plane(
+ dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
+
+ if (dc->debug.sanity_checks) {
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+ }
+
+@@ -2102,6 +2113,7 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state
+
+ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct mpcc_blnd_cfg blnd_cfg = {{0}};
+ bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
+@@ -2111,10 +2123,10 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
+
+ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+- dc->hwss.get_hdr_visual_confirm_color(
++ hws->funcs.get_hdr_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+- dc->hwss.get_surface_visual_confirm_color(
++ hws->funcs.get_surface_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else {
+ color_space_to_black_color(
+@@ -2201,6 +2213,7 @@ static void dcn10_update_dchubp_dpp(
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+@@ -2259,7 +2272,7 @@ static void dcn10_update_dchubp_dpp(
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.per_pixel_alpha_change ||
+ plane_state->update_flags.bits.global_alpha_change)
+- dc->hwss.update_mpcc(dc, pipe_ctx);
++ hws->funcs.update_mpcc(dc, pipe_ctx);
+
+ if (plane_state->update_flags.bits.full_update ||
+ plane_state->update_flags.bits.per_pixel_alpha_change ||
+@@ -2319,7 +2332,7 @@ static void dcn10_update_dchubp_dpp(
+
+ hubp->power_gated = false;
+
+- dc->hwss.update_plane_addr(dc, pipe_ctx);
++ hws->funcs.update_plane_addr(dc, pipe_ctx);
+
+ if (is_pipe_tree_visible(pipe_ctx))
+ hubp->funcs->set_blank(hubp, false);
+@@ -2395,17 +2408,19 @@ void dcn10_program_pipe(
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
++
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ dcn10_enable_plane(dc, pipe_ctx, context);
+
+ dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
+
+- dc->hwss.set_hdr_multiplier(pipe_ctx);
++ hws->funcs.set_hdr_multiplier(pipe_ctx);
+
+ if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+- dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
++ hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+
+ /* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ * only do gamma programming for full update.
+@@ -2414,7 +2429,7 @@ void dcn10_program_pipe(
+ * doing heavy calculation and programming
+ */
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+- dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
++ hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ }
+
+ static void dcn10_program_all_pipe_in_tree(
+@@ -2422,6 +2437,8 @@ static void dcn10_program_all_pipe_in_tree(
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
++
+ if (pipe_ctx->top_pipe == NULL) {
+ bool blank = !is_pipe_tree_visible(pipe_ctx);
+
+@@ -2435,14 +2452,14 @@ static void dcn10_program_all_pipe_in_tree(
+ pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+- if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++ if (hws->funcs.setup_vupdate_interrupt)
++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+
+- dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
++ hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
+ }
+
+ if (pipe_ctx->plane_state != NULL)
+- dc->hwss.program_pipe(dc, pipe_ctx, context);
++ hws->funcs.program_pipe(dc, pipe_ctx, context);
+
+ if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
+ dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+@@ -2478,6 +2495,7 @@ void dcn10_apply_ctx_for_surface(
+ int num_planes,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ int i;
+ struct timing_generator *tg;
+ uint32_t underflow_check_delay_us;
+@@ -2497,8 +2515,8 @@ void dcn10_apply_ctx_for_surface(
+
+ underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
+
+- if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
+- ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
++ if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
++ ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
+
+ if (interdependent_update)
+ dcn10_lock_all_pipes(dc, context, true);
+@@ -2508,12 +2526,12 @@ void dcn10_apply_ctx_for_surface(
+ if (underflow_check_delay_us != 0xFFFFFFFF)
+ udelay(underflow_check_delay_us);
+
+- if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
+- ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
++ if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
++ ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
+
+ if (num_planes == 0) {
+ /* OTG blank before remove all front end */
+- dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
++ hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true);
+ }
+
+ /* Disconnect unused mpcc */
+@@ -2539,7 +2557,7 @@ void dcn10_apply_ctx_for_surface(
+ old_pipe_ctx->plane_state &&
+ old_pipe_ctx->stream_res.tg == tg) {
+
+- dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
++ hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx);
+ removed_pipe[i] = true;
+
+ DC_LOG_DC("Reset mpcc for pipe %d\n",
+@@ -2550,9 +2568,11 @@ void dcn10_apply_ctx_for_surface(
+ if (num_planes > 0)
+ dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* Program secondary blending tree and writeback pipes */
+- if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
+- dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
++ if ((stream->num_wb_info > 0) && (hws->funcs.program_all_writeback_pipes_in_tree))
++ hws->funcs.program_all_writeback_pipes_in_tree(dc, stream, context);
++#endif
+ if (interdependent_update)
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+@@ -2609,10 +2629,11 @@ void dcn10_prepare_bandwidth(
+ struct dc *dc,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubbub *hubbub = dc->res_pool->hubbub;
+
+ if (dc->debug.sanity_checks)
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (context->stream_count == 0)
+@@ -2634,17 +2655,18 @@ void dcn10_prepare_bandwidth(
+ dcn_bw_notify_pplib_of_wm_ranges(dc);
+
+ if (dc->debug.sanity_checks)
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+
+ void dcn10_optimize_bandwidth(
+ struct dc *dc,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubbub *hubbub = dc->res_pool->hubbub;
+
+ if (dc->debug.sanity_checks)
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (context->stream_count == 0)
+@@ -2666,7 +2688,7 @@ void dcn10_optimize_bandwidth(
+ dcn_bw_notify_pplib_of_wm_ranges(dc);
+
+ if (dc->debug.sanity_checks)
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+
+ void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+@@ -2808,10 +2830,11 @@ void dcn10_wait_for_mpcc_disconnect(
+ struct resource_pool *res_pool,
+ struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ int mpcc_inst;
+
+ if (dc->debug.sanity_checks) {
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+
+ if (!pipe_ctx->stream_res.opp)
+@@ -2828,7 +2851,7 @@ void dcn10_wait_for_mpcc_disconnect(
+ }
+
+ if (dc->debug.sanity_checks) {
+- dc->hwss.verify_allow_pstate_change_high(dc);
++ hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+
+ }
+@@ -3127,6 +3150,7 @@ void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ struct encoder_unblank_param params = { { 0 } };
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct dc_link *link = stream->link;
++ struct dce_hwseq *hws = link->dc->hwseq;
+
+ /* only 3 items below are used by unblank */
+ params.timing = pipe_ctx->stream->timing;
+@@ -3140,7 +3164,7 @@ void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ }
+
+ if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+- link->dc->hwss.edp_backlight_control(link, true);
++ hws->funcs.edp_backlight_control(link, true);
+ }
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+index 5aad3922be6c..55b8f3b2fc4e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCN10_H__
+
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+
+ struct dc;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+index 38923f3120ee..e7e5352ec424 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+@@ -23,25 +23,19 @@
+ *
+ */
+
++#include "hw_sequencer_private.h"
+ #include "dce110/dce110_hw_sequencer.h"
+ #include "dcn10_hw_sequencer.h"
+
+ static const struct hw_sequencer_funcs dcn10_funcs = {
+ .program_gamut_remap = dcn10_program_gamut_remap,
+ .init_hw = dcn10_init_hw,
+- .init_pipes = dcn10_init_pipes,
+ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+ .update_plane_addr = dcn10_update_plane_addr,
+- .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+- .program_pipe = dcn10_program_pipe,
+ .update_dchub = dcn10_update_dchub,
+- .update_mpcc = dcn10_update_mpcc,
+ .update_pending_status = dcn10_update_pending_status,
+- .set_input_transfer_func = dcn10_set_input_transfer_func,
+- .set_output_transfer_func = dcn10_set_output_transfer_func,
+ .program_output_csc = dcn10_program_output_csc,
+- .power_down = dce110_power_down,
+ .enable_accelerated_mode = dce110_enable_accelerated_mode,
+ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+@@ -53,14 +47,10 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ .blank_stream = dce110_blank_stream,
+ .enable_audio_stream = dce110_enable_audio_stream,
+ .disable_audio_stream = dce110_disable_audio_stream,
+- .enable_display_power_gating = dcn10_dummy_display_power_gating,
+ .disable_plane = dcn10_disable_plane,
+- .blank_pixel_data = dcn10_blank_pixel_data,
+ .pipe_control_lock = dcn10_pipe_control_lock,
+ .prepare_bandwidth = dcn10_prepare_bandwidth,
+ .optimize_bandwidth = dcn10_optimize_bandwidth,
+- .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
+- .enable_stream_timing = dcn10_enable_stream_timing,
+ .set_drr = dcn10_set_drr,
+ .get_position = dcn10_get_position,
+ .set_static_screen_control = dcn10_set_static_screen_control,
+@@ -70,18 +60,34 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ .get_hw_state = dcn10_get_hw_state,
+ .clear_status_bits = dcn10_clear_status_bits,
+ .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+- .edp_backlight_control = dce110_edp_backlight_control,
+ .edp_power_control = dce110_edp_power_control,
+ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ .set_cursor_position = dcn10_set_cursor_position,
+ .set_cursor_attribute = dcn10_set_cursor_attribute,
+ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+- .disable_stream_gating = NULL,
+- .enable_stream_gating = NULL,
+ .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+- .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ .set_clock = dcn10_set_clock,
+ .get_clock = dcn10_get_clock,
++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++static const struct hwseq_private_funcs dcn10_private_funcs = {
++ .init_pipes = dcn10_init_pipes,
++ .update_plane_addr = dcn10_update_plane_addr,
++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++ .program_pipe = dcn10_program_pipe,
++ .update_mpcc = dcn10_update_mpcc,
++ .set_input_transfer_func = dcn10_set_input_transfer_func,
++ .set_output_transfer_func = dcn10_set_output_transfer_func,
++ .power_down = dce110_power_down,
++ .enable_display_power_gating = dcn10_dummy_display_power_gating,
++ .blank_pixel_data = dcn10_blank_pixel_data,
++ .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
++ .enable_stream_timing = dcn10_enable_stream_timing,
++ .edp_backlight_control = dce110_edp_backlight_control,
++ .disable_stream_gating = NULL,
++ .enable_stream_gating = NULL,
++ .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ .did_underflow_occur = dcn10_did_underflow_occur,
+ .init_blank = NULL,
+ .disable_vga = dcn10_disable_vga,
+@@ -96,10 +102,10 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
+ .set_hdr_multiplier = dcn10_set_hdr_multiplier,
+ .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+- .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+ };
+
+ void dcn10_hw_sequencer_construct(struct dc *dc)
+ {
+ dc->hwss = dcn10_funcs;
++ dc->hwseq->funcs = dcn10_private_funcs;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 937ecb28948d..d99e882bd555 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -276,6 +276,7 @@ void dcn20_init_blank(
+ struct dc *dc,
+ struct timing_generator *tg)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ enum dc_color_space color_space;
+ struct tg_color black_color = {0};
+ struct output_pixel_processor *opp = NULL;
+@@ -323,7 +324,7 @@ void dcn20_init_blank(
+ otg_active_height);
+ }
+
+- dc->hwss.wait_for_blank_complete(opp);
++ hws->funcs.wait_for_blank_complete(opp);
+ }
+
+ void dcn20_dsc_pg_control(
+@@ -556,6 +557,7 @@ void dcn20_hubp_pg_control(
+ */
+ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+
+@@ -576,7 +578,7 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ hubp->power_gated = true;
+ dc->optimized_required = false; /* We're powering off, no need to optimize */
+
+- dc->hwss.plane_atomic_power_down(dc,
++ hws->funcs.plane_atomic_power_down(dc,
+ pipe_ctx->plane_res.dpp,
+ pipe_ctx->plane_res.hubp);
+
+@@ -607,6 +609,7 @@ enum dc_status dcn20_enable_stream_timing(
+ struct dc_state *context,
+ struct dc *dc)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct drr_params params = {0};
+ unsigned int event_triggers = 0;
+@@ -666,7 +669,7 @@ enum dc_status dcn20_enable_stream_timing(
+ pipe_ctx->stream_res.opp,
+ true);
+
+- dc->hwss.blank_pixel_data(dc, pipe_ctx, true);
++ hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
+
+ /* VTG is within DCHUB command block. DCFCLK is always on */
+ if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
+@@ -674,7 +677,7 @@ enum dc_status dcn20_enable_stream_timing(
+ return DC_ERROR_UNEXPECTED;
+ }
+
+- dc->hwss.wait_for_blank_complete(pipe_ctx->stream_res.opp);
++ hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
+
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
+@@ -824,6 +827,7 @@ bool dcn20_set_input_transfer_func(struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ const struct dc_plane_state *plane_state)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+ const struct dc_transfer_func *tf = NULL;
+ bool result = true;
+@@ -832,8 +836,8 @@ bool dcn20_set_input_transfer_func(struct dc *dc,
+ if (dpp_base == NULL || plane_state == NULL)
+ return false;
+
+- dc->hwss.set_shaper_3dlut(pipe_ctx, plane_state);
+- dc->hwss.set_blend_lut(pipe_ctx, plane_state);
++ hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
++ hws->funcs.set_blend_lut(pipe_ctx, plane_state);
+
+ if (plane_state->in_transfer_func)
+ tf = plane_state->in_transfer_func;
+@@ -1296,6 +1300,7 @@ static void dcn20_update_dchubp_dpp(
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+@@ -1360,7 +1365,7 @@ static void dcn20_update_dchubp_dpp(
+ old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
+ }
+ }
+- dc->hwss.update_mpcc(dc, pipe_ctx);
++ hws->funcs.update_mpcc(dc, pipe_ctx);
+ }
+
+ if (pipe_ctx->update_flags.bits.scaler ||
+@@ -1435,7 +1440,7 @@ static void dcn20_update_dchubp_dpp(
+ }
+
+ if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
+- dc->hwss.update_plane_addr(dc, pipe_ctx);
++ hws->funcs.update_plane_addr(dc, pipe_ctx);
+
+ if (pipe_ctx->update_flags.bits.enable)
+ hubp->funcs->set_blank(hubp, false);
+@@ -1447,10 +1452,11 @@ static void dcn20_program_pipe(
+ struct pipe_ctx *pipe_ctx,
+ struct dc_state *context)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ /* Only need to unblank on top pipe */
+ if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
+ && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
+- dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
++ hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
+
+ if (pipe_ctx->update_flags.bits.global_sync) {
+ pipe_ctx->stream_res.tg->funcs->program_global_sync(
+@@ -1463,12 +1469,12 @@ static void dcn20_program_pipe(
+ pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+- if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++ if (hws->funcs.setup_vupdate_interrupt)
++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+ }
+
+ if (pipe_ctx->update_flags.bits.odm)
+- dc->hwss.update_odm(dc, context, pipe_ctx);
++ hws->funcs.update_odm(dc, context, pipe_ctx);
+
+ if (pipe_ctx->update_flags.bits.enable)
+ dcn20_enable_plane(dc, pipe_ctx, context);
+@@ -1478,19 +1484,19 @@ static void dcn20_program_pipe(
+
+ if (pipe_ctx->update_flags.bits.enable
+ || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
+- dc->hwss.set_hdr_multiplier(pipe_ctx);
++ hws->funcs.set_hdr_multiplier(pipe_ctx);
+
+ if (pipe_ctx->update_flags.bits.enable ||
+ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ pipe_ctx->plane_state->update_flags.bits.gamma_change)
+- dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
++ hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+
+ /* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ * only do gamma programming for powering on, internal memcmp to avoid
+ * updating on slave planes
+ */
+ if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
+- dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
++ hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+
+ /* If the pipe has been enabled or has a different opp, we
+ * should reprogram the fmt. This deals with cases where
+@@ -1530,6 +1536,7 @@ void dcn20_program_front_end_for_ctx(
+ {
+ const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
+ int i;
++ struct dce_hwseq *hws = dc->hwseq;
+ bool pipe_locked[MAX_PIPES] = {false};
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+@@ -1561,13 +1568,13 @@ void dcn20_program_front_end_for_ctx(
+ && !context->res_ctx.pipe_ctx[i].top_pipe
+ && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
+ && context->res_ctx.pipe_ctx[i].stream)
+- dc->hwss.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
++ hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
+
+ /* Disconnect mpcc */
+ for (i = 0; i < dc->res_pool->pipe_count; i++)
+ if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
+ || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
+- dc->hwss.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++ hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
+ }
+
+@@ -1587,8 +1594,8 @@ void dcn20_program_front_end_for_ctx(
+ pipe = &context->res_ctx.pipe_ctx[i];
+ if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
+ && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
+- && dc->hwss.program_all_writeback_pipes_in_tree)
+- dc->hwss.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
++ && hws->funcs.program_all_writeback_pipes_in_tree)
++ hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
+ }
+ }
+
+@@ -1673,6 +1680,7 @@ bool dcn20_update_bandwidth(
+ struct dc_state *context)
+ {
+ int i;
++ struct dce_hwseq *hws = dc->hwseq;
+
+ /* recalculate DML parameters */
+ if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
+@@ -1702,10 +1710,10 @@ bool dcn20_update_bandwidth(
+ pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+ if (pipe_ctx->prev_odm_pipe == NULL)
+- dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
++ hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
+
+- if (dc->hwss.setup_vupdate_interrupt)
+- dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++ if (hws->funcs.setup_vupdate_interrupt)
++ hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+ }
+
+ pipe_ctx->plane_res.hubp->funcs->hubp_setup(
+@@ -1942,6 +1950,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ struct encoder_unblank_param params = { { 0 } };
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ struct dc_link *link = stream->link;
++ struct dce_hwseq *hws = link->dc->hwseq;
+ struct pipe_ctx *odm_pipe;
+
+ params.opp_cnt = 1;
+@@ -1962,7 +1971,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ }
+
+ if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+- link->dc->hwss.edp_backlight_control(link, true);
++ hws->funcs.edp_backlight_control(link, true);
+ }
+ }
+
+@@ -2050,6 +2059,7 @@ void dcn20_reset_hw_ctx_wrap(
+ struct dc_state *context)
+ {
+ int i;
++ struct dce_hwseq *hws = dc->hwseq;
+
+ /* Reset Back End*/
+ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
+@@ -2068,8 +2078,8 @@ void dcn20_reset_hw_ctx_wrap(
+ struct clock_source *old_clk = pipe_ctx_old->clock_source;
+
+ dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
+- if (dc->hwss.enable_stream_gating)
+- dc->hwss.enable_stream_gating(dc, pipe_ctx);
++ if (hws->funcs.enable_stream_gating)
++ hws->funcs.enable_stream_gating(dc, pipe_ctx);
+ if (old_clk)
+ old_clk->funcs->cs_power_down(old_clk);
+ }
+@@ -2100,6 +2110,7 @@ void dcn20_get_mpctree_visual_confirm_color(
+
+ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++ struct dce_hwseq *hws = dc->hwseq;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ struct mpcc_blnd_cfg blnd_cfg = { {0} };
+ bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
+@@ -2110,10 +2121,10 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+
+ // input to MPCC is always RGB, by default leave black_color at 0
+ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+- dc->hwss.get_hdr_visual_confirm_color(
++ hws->funcs.get_hdr_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+- dc->hwss.get_surface_visual_confirm_color(
++ hws->funcs.get_surface_visual_confirm_color(
+ pipe_ctx, &blnd_cfg.black_color);
+ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
+ dcn20_get_mpctree_visual_confirm_color(
+@@ -2269,13 +2280,13 @@ void dcn20_fpga_init_hw(struct dc *dc)
+ res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+
+ //Enable ability to power gate / don't force power on permanently
+- dc->hwss.enable_power_gating_plane(hws, true);
++ hws->funcs.enable_power_gating_plane(hws, true);
+
+ // Specific to FPGA dccg and registers
+ REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+ REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+
+- dc->hwss.dccg_init(hws);
++ hws->funcs.dccg_init(hws);
+
+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+@@ -2339,7 +2350,7 @@ void dcn20_fpga_init_hw(struct dc *dc)
+ dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ /*to do*/
+- dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
++ hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
+ }
+
+ /* initialize DWB pointer to MCIF_WB */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index f58b69c1b321..fe23a24c3325 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -26,6 +26,8 @@
+ #ifndef __DC_HWSS_DCN20_H__
+ #define __DC_HWSS_DCN20_H__
+
++#include "hw_sequencer_private.h"
++
+ bool dcn20_set_blend_lut(
+ struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+ bool dcn20_set_shaper_3dlut(
+@@ -111,6 +113,7 @@ void dcn20_disable_writeback(
+ void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
+ void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
++void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
+ void dcn20_init_vm_ctx(
+ struct dce_hwseq *hws,
+ struct dc *dc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+index 10493777d192..7ac145ef165f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+@@ -30,19 +30,13 @@
+ static const struct hw_sequencer_funcs dcn20_funcs = {
+ .program_gamut_remap = dcn10_program_gamut_remap,
+ .init_hw = dcn10_init_hw,
+- .init_pipes = dcn10_init_pipes,
+ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ .apply_ctx_for_surface = NULL,
+ .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ .update_plane_addr = dcn20_update_plane_addr,
+- .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+ .update_dchub = dcn10_update_dchub,
+- .update_mpcc = dcn20_update_mpcc,
+ .update_pending_status = dcn10_update_pending_status,
+- .set_input_transfer_func = dcn20_set_input_transfer_func,
+- .set_output_transfer_func = dcn20_set_output_transfer_func,
+ .program_output_csc = dcn20_program_output_csc,
+- .power_down = dce110_power_down,
+ .enable_accelerated_mode = dce110_enable_accelerated_mode,
+ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+@@ -54,16 +48,12 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ .blank_stream = dce110_blank_stream,
+ .enable_audio_stream = dce110_enable_audio_stream,
+ .disable_audio_stream = dce110_disable_audio_stream,
+- .enable_display_power_gating = dcn10_dummy_display_power_gating,
+ .disable_plane = dcn20_disable_plane,
+- .blank_pixel_data = dcn20_blank_pixel_data,
+ .pipe_control_lock = dcn20_pipe_control_lock,
+ .pipe_control_lock_global = dcn20_pipe_control_lock_global,
+ .prepare_bandwidth = dcn20_prepare_bandwidth,
+ .optimize_bandwidth = dcn20_optimize_bandwidth,
+ .update_bandwidth = dcn20_update_bandwidth,
+- .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+- .enable_stream_timing = dcn20_enable_stream_timing,
+ .set_drr = dcn10_set_drr,
+ .get_position = dcn10_get_position,
+ .set_static_screen_control = dcn10_set_static_screen_control,
+@@ -73,18 +63,42 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ .get_hw_state = dcn10_get_hw_state,
+ .clear_status_bits = dcn10_clear_status_bits,
+ .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+- .edp_backlight_control = dce110_edp_backlight_control,
+ .edp_power_control = dce110_edp_power_control,
+ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ .set_cursor_position = dcn10_set_cursor_position,
+ .set_cursor_attribute = dcn10_set_cursor_attribute,
+ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+- .disable_stream_gating = dcn20_disable_stream_gating,
+- .enable_stream_gating = dcn20_enable_stream_gating,
+ .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+- .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ .set_clock = dcn10_set_clock,
+ .get_clock = dcn10_get_clock,
++ .program_triplebuffer = dcn20_program_triple_buffer,
++ .enable_writeback = dcn20_enable_writeback,
++ .disable_writeback = dcn20_disable_writeback,
++ .dmdata_status_done = dcn20_dmdata_status_done,
++ .program_dmdata_engine = dcn20_program_dmdata_engine,
++ .set_dmdata_attributes = dcn20_set_dmdata_attributes,
++ .init_sys_ctx = dcn20_init_sys_ctx,
++ .init_vm_ctx = dcn20_init_vm_ctx,
++ .set_flip_control_gsl = dcn20_set_flip_control_gsl,
++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++static const struct hwseq_private_funcs dcn20_private_funcs = {
++ .init_pipes = dcn10_init_pipes,
++ .update_plane_addr = dcn20_update_plane_addr,
++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++ .update_mpcc = dcn20_update_mpcc,
++ .set_input_transfer_func = dcn20_set_input_transfer_func,
++ .set_output_transfer_func = dcn20_set_output_transfer_func,
++ .power_down = dce110_power_down,
++ .enable_display_power_gating = dcn10_dummy_display_power_gating,
++ .blank_pixel_data = dcn20_blank_pixel_data,
++ .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++ .enable_stream_timing = dcn20_enable_stream_timing,
++ .edp_backlight_control = dce110_edp_backlight_control,
++ .disable_stream_gating = dcn20_disable_stream_gating,
++ .enable_stream_gating = dcn20_enable_stream_gating,
++ .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ .did_underflow_occur = dcn10_did_underflow_occur,
+ .init_blank = dcn20_init_blank,
+ .disable_vga = dcn20_disable_vga,
+@@ -95,15 +109,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ .dpp_pg_control = dcn20_dpp_pg_control,
+ .hubp_pg_control = dcn20_hubp_pg_control,
+ .dsc_pg_control = NULL,
+- .program_triplebuffer = dcn20_program_triple_buffer,
+- .enable_writeback = dcn20_enable_writeback,
+- .disable_writeback = dcn20_disable_writeback,
+ .update_odm = dcn20_update_odm,
+- .dmdata_status_done = dcn20_dmdata_status_done,
+- .program_dmdata_engine = dcn20_program_dmdata_engine,
+- .init_sys_ctx = dcn20_init_sys_ctx,
+- .init_vm_ctx = dcn20_init_vm_ctx,
+- .set_flip_control_gsl = dcn20_set_flip_control_gsl,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .dsc_pg_control = dcn20_dsc_pg_control,
+ #else
+@@ -117,15 +123,15 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ .dccg_init = dcn20_dccg_init,
+ .set_blend_lut = dcn20_set_blend_lut,
+ .set_shaper_3dlut = dcn20_set_shaper_3dlut,
+- .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+ };
+
+ void dcn20_hw_sequencer_construct(struct dc *dc)
+ {
+ dc->hwss = dcn20_funcs;
++ dc->hwseq->funcs = dcn20_private_funcs;
+
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ dc->hwss.init_hw = dcn20_fpga_init_hw;
+- dc->hwss.init_pipes = NULL;
++ dc->hwseq->funcs.init_pipes = NULL;
+ }
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+index 005894dcabc9..081ad8e43d58 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+@@ -28,6 +28,7 @@
+ #include "core_types.h"
+ #include "resource.h"
+ #include "dce/dce_hwseq.h"
++#include "dcn21_hwseq.h"
+ #include "vmid.h"
+ #include "reg_helper.h"
+ #include "hw/clk_mgr.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+index 2f7b8a220eb9..182736096123 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+@@ -26,6 +26,8 @@
+ #ifndef __DC_HWSS_DCN21_H__
+ #define __DC_HWSS_DCN21_H__
+
++#include "hw_sequencer_private.h"
++
+ struct dc;
+
+ int dcn21_init_sys_ctx(struct dce_hwseq *hws,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+index cbd55037a04a..45e79a8b7070 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+@@ -31,19 +31,13 @@
+ static const struct hw_sequencer_funcs dcn21_funcs = {
+ .program_gamut_remap = dcn10_program_gamut_remap,
+ .init_hw = dcn10_init_hw,
+- .init_pipes = dcn10_init_pipes,
+ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ .apply_ctx_for_surface = NULL,
+ .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ .update_plane_addr = dcn20_update_plane_addr,
+- .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+ .update_dchub = dcn10_update_dchub,
+- .update_mpcc = dcn20_update_mpcc,
+ .update_pending_status = dcn10_update_pending_status,
+- .set_input_transfer_func = dcn20_set_input_transfer_func,
+- .set_output_transfer_func = dcn20_set_output_transfer_func,
+ .program_output_csc = dcn20_program_output_csc,
+- .power_down = dce110_power_down,
+ .enable_accelerated_mode = dce110_enable_accelerated_mode,
+ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+@@ -55,16 +49,12 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ .blank_stream = dce110_blank_stream,
+ .enable_audio_stream = dce110_enable_audio_stream,
+ .disable_audio_stream = dce110_disable_audio_stream,
+- .enable_display_power_gating = dcn10_dummy_display_power_gating,
+ .disable_plane = dcn20_disable_plane,
+- .blank_pixel_data = dcn20_blank_pixel_data,
+ .pipe_control_lock = dcn20_pipe_control_lock,
+ .pipe_control_lock_global = dcn20_pipe_control_lock_global,
+ .prepare_bandwidth = dcn20_prepare_bandwidth,
+ .optimize_bandwidth = dcn20_optimize_bandwidth,
+ .update_bandwidth = dcn20_update_bandwidth,
+- .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+- .enable_stream_timing = dcn20_enable_stream_timing,
+ .set_drr = dcn10_set_drr,
+ .get_position = dcn10_get_position,
+ .set_static_screen_control = dcn10_set_static_screen_control,
+@@ -74,18 +64,49 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ .get_hw_state = dcn10_get_hw_state,
+ .clear_status_bits = dcn10_clear_status_bits,
+ .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+- .edp_backlight_control = dce110_edp_backlight_control,
+ .edp_power_control = dce110_edp_power_control,
+ .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ .set_cursor_position = dcn10_set_cursor_position,
+ .set_cursor_attribute = dcn10_set_cursor_attribute,
+ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+- .disable_stream_gating = dcn20_disable_stream_gating,
+- .enable_stream_gating = dcn20_enable_stream_gating,
+ .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+- .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ .set_clock = dcn10_set_clock,
+ .get_clock = dcn10_get_clock,
++ .program_triplebuffer = dcn20_program_triple_buffer,
++ .enable_writeback = dcn20_enable_writeback,
++ .disable_writeback = dcn20_disable_writeback,
++ .dmdata_status_done = dcn20_dmdata_status_done,
++ .program_dmdata_engine = dcn20_program_dmdata_engine,
++ .set_dmdata_attributes = dcn20_set_dmdata_attributes,
++ .init_sys_ctx = dcn21_init_sys_ctx,
++ .init_vm_ctx = dcn20_init_vm_ctx,
++ .set_flip_control_gsl = dcn20_set_flip_control_gsl,
++ .optimize_pwr_state = dcn21_optimize_pwr_state,
++ .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
++ .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++ .set_cursor_position = dcn10_set_cursor_position,
++ .set_cursor_attribute = dcn10_set_cursor_attribute,
++ .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++ .optimize_pwr_state = dcn21_optimize_pwr_state,
++ .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
++};
++
++static const struct hwseq_private_funcs dcn21_private_funcs = {
++ .init_pipes = dcn10_init_pipes,
++ .update_plane_addr = dcn20_update_plane_addr,
++ .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++ .update_mpcc = dcn20_update_mpcc,
++ .set_input_transfer_func = dcn20_set_input_transfer_func,
++ .set_output_transfer_func = dcn20_set_output_transfer_func,
++ .power_down = dce110_power_down,
++ .enable_display_power_gating = dcn10_dummy_display_power_gating,
++ .blank_pixel_data = dcn20_blank_pixel_data,
++ .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++ .enable_stream_timing = dcn20_enable_stream_timing,
++ .edp_backlight_control = dce110_edp_backlight_control,
++ .disable_stream_gating = dcn20_disable_stream_gating,
++ .enable_stream_gating = dcn20_enable_stream_gating,
++ .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ .did_underflow_occur = dcn10_did_underflow_occur,
+ .init_blank = dcn20_init_blank,
+ .disable_vga = dcn20_disable_vga,
+@@ -96,15 +117,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ .dpp_pg_control = dcn20_dpp_pg_control,
+ .hubp_pg_control = dcn20_hubp_pg_control,
+ .dsc_pg_control = NULL,
+- .program_triplebuffer = dcn20_program_triple_buffer,
+- .enable_writeback = dcn20_enable_writeback,
+- .disable_writeback = dcn20_disable_writeback,
+ .update_odm = dcn20_update_odm,
+- .dmdata_status_done = dcn20_dmdata_status_done,
+- .program_dmdata_engine = dcn20_program_dmdata_engine,
+- .init_sys_ctx = dcn21_init_sys_ctx,
+- .init_vm_ctx = dcn20_init_vm_ctx,
+- .set_flip_control_gsl = dcn20_set_flip_control_gsl,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .dsc_pg_control = dcn20_dsc_pg_control,
+ #else
+@@ -115,21 +128,19 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ .set_hdr_multiplier = dcn10_set_hdr_multiplier,
+ .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+ .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
+- .optimize_pwr_state = dcn21_optimize_pwr_state,
+- .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
+ .wait_for_blank_complete = dcn20_wait_for_blank_complete,
+ .dccg_init = dcn20_dccg_init,
+ .set_blend_lut = dcn20_set_blend_lut,
+ .set_shaper_3dlut = dcn20_set_shaper_3dlut,
+- .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+ };
+
+ void dcn21_hw_sequencer_construct(struct dc *dc)
+ {
+ dc->hwss = dcn21_funcs;
++ dc->hwseq->funcs = dcn21_private_funcs;
+
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ dc->hwss.init_hw = dcn20_fpga_init_hw;
+- dc->hwss.init_pipes = NULL;
++ dc->hwseq->funcs.init_pipes = NULL;
+ }
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 937a02d02f18..54b3e88bf0d3 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -32,294 +32,137 @@
+ #include "inc/hw/link_encoder.h"
+ #include "core_status.h"
+
+-enum pipe_gating_control {
+- PIPE_GATING_CONTROL_DISABLE = 0,
+- PIPE_GATING_CONTROL_ENABLE,
+- PIPE_GATING_CONTROL_INIT
+-};
+-
+ enum vline_select {
+ VLINE0,
+ VLINE1
+ };
+
+-struct dce_hwseq_wa {
+- bool blnd_crtc_trigger;
+- bool DEGVIDCN10_253;
+- bool false_optc_underflow;
+- bool DEGVIDCN10_254;
+- bool DEGVIDCN21;
+-};
+-
+-struct hwseq_wa_state {
+- bool DEGVIDCN10_253_applied;
+-};
+-
+-struct dce_hwseq {
+- struct dc_context *ctx;
+- const struct dce_hwseq_registers *regs;
+- const struct dce_hwseq_shift *shifts;
+- const struct dce_hwseq_mask *masks;
+- struct dce_hwseq_wa wa;
+- struct hwseq_wa_state wa_state;
+-};
+-
+ struct pipe_ctx;
+ struct dc_state;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_stream_status;
+ struct dc_writeback_info;
++#endif
+ struct dchub_init_data;
+ struct dc_static_screen_events;
+ struct resource_pool;
+-struct resource_context;
+-struct stream_resource;
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config;
+ struct dc_virtual_addr_space_config;
+-struct hubp;
++#endif
+ struct dpp;
++struct dce_hwseq;
+
+ struct hw_sequencer_funcs {
++ /* Embedded Display Related */
++ void (*edp_power_control)(struct dc_link *link, bool enable);
++ void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+
+- void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+- void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
++ /* Pipe Programming Related */
+ void (*init_hw)(struct dc *dc);
+-
+- void (*init_pipes)(struct dc *dc, struct dc_state *context);
+-
+- enum dc_status (*apply_ctx_to_hw)(
+- struct dc *dc, struct dc_state *context);
+-
+- void (*reset_hw_ctx_wrap)(
+- struct dc *dc, struct dc_state *context);
+-
+- void (*apply_ctx_for_surface)(
+- struct dc *dc,
++ void (*enable_accelerated_mode)(struct dc *dc,
++ struct dc_state *context);
++ enum dc_status (*apply_ctx_to_hw)(struct dc *dc,
++ struct dc_state *context);
++ void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++ void (*apply_ctx_for_surface)(struct dc *dc,
+ const struct dc_stream_state *stream,
+- int num_planes,
++ int num_planes, struct dc_state *context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++ void (*program_front_end_for_ctx)(struct dc *dc,
+ struct dc_state *context);
+-
+- void (*program_gamut_remap)(
++#endif
++ void (*update_plane_addr)(const struct dc *dc,
+ struct pipe_ctx *pipe_ctx);
+-
+- void (*program_output_csc)(struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- enum dc_color_space colorspace,
+- uint16_t *matrix,
+- int opp_id);
+-
+- void (*program_front_end_for_ctx)(
+- struct dc *dc,
+- struct dc_state *context);
+- void (*program_triplebuffer)(
+- const struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- bool enableTripleBuffer);
+- void (*set_flip_control_gsl)(
+- struct pipe_ctx *pipe_ctx,
+- bool flip_immediate);
+-
+- void (*update_plane_addr)(
+- const struct dc *dc,
+- struct pipe_ctx *pipe_ctx);
+-
+- void (*plane_atomic_disconnect)(
+- struct dc *dc,
+- struct pipe_ctx *pipe_ctx);
+-
+- void (*update_dchub)(
+- struct dce_hwseq *hws,
+- struct dchub_init_data *dh_data);
+-
+- int (*init_sys_ctx)(
+- struct dce_hwseq *hws,
+- struct dc *dc,
+- struct dc_phy_addr_space_config *pa_config);
+- void (*init_vm_ctx)(
+- struct dce_hwseq *hws,
+- struct dc *dc,
+- struct dc_virtual_addr_space_config *va_config,
+- int vmid);
+- void (*update_mpcc)(
+- struct dc *dc,
+- struct pipe_ctx *pipe_ctx);
+-
+- void (*update_pending_status)(
++ void (*update_dchub)(struct dce_hwseq *hws,
++ struct dchub_init_data *dh_data);
++ void (*wait_for_mpcc_disconnect)(struct dc *dc,
++ struct resource_pool *res_pool,
+ struct pipe_ctx *pipe_ctx);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++ void (*program_triplebuffer)(const struct dc *dc,
++ struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
++#endif
++ void (*update_pending_status)(struct pipe_ctx *pipe_ctx);
++
++ /* Pipe Lock Related */
++ void (*pipe_control_lock_global)(struct dc *dc,
++ struct pipe_ctx *pipe, bool lock);
++ void (*pipe_control_lock)(struct dc *dc,
++ struct pipe_ctx *pipe, bool lock);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++ void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
++ bool flip_immediate);
++#endif
+
+- bool (*set_input_transfer_func)(struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- const struct dc_plane_state *plane_state);
+-
+- bool (*set_output_transfer_func)(struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- const struct dc_stream_state *stream);
+-
+- void (*power_down)(struct dc *dc);
+-
+- void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
+-
+- void (*enable_timing_synchronization)(
+- struct dc *dc,
+- int group_index,
+- int group_size,
+- struct pipe_ctx *grouped_pipes[]);
+-
+- void (*enable_per_frame_crtc_position_reset)(
+- struct dc *dc,
+- int group_size,
++ /* Timing Related */
++ void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
++ struct crtc_position *position);
++ int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
++ void (*enable_per_frame_crtc_position_reset)(struct dc *dc,
++ int group_size, struct pipe_ctx *grouped_pipes[]);
++ void (*enable_timing_synchronization)(struct dc *dc,
++ int group_index, int group_size,
+ struct pipe_ctx *grouped_pipes[]);
++ void (*setup_periodic_interrupt)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ enum vline_select vline);
++ void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
++ unsigned int vmin, unsigned int vmax,
++ unsigned int vmid, unsigned int vmid_frame_number);
++ void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
++ int num_pipes,
++ const struct dc_static_screen_events *events);
+
+- void (*enable_display_pipe_clock_gating)(
+- struct dc_context *ctx,
+- bool clock_gating);
+-
+- bool (*enable_display_power_gating)(
+- struct dc *dc,
+- uint8_t controller_id,
+- struct dc_bios *dcb,
+- enum pipe_gating_control power_gating);
+-
+- void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+- void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
+-
+- void (*send_immediate_sdp_message)(
+- struct pipe_ctx *pipe_ctx,
+- const uint8_t *custom_sdp_message,
+- unsigned int sdp_message_size);
+-
++ /* Stream Related */
+ void (*enable_stream)(struct pipe_ctx *pipe_ctx);
+-
+ void (*disable_stream)(struct pipe_ctx *pipe_ctx);
+-
++ void (*blank_stream)(struct pipe_ctx *pipe_ctx);
+ void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
+ struct dc_link_settings *link_settings);
+
+- void (*blank_stream)(struct pipe_ctx *pipe_ctx);
+-
+- void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
+-
+- void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
+-
+- void (*pipe_control_lock)(
+- struct dc *dc,
+- struct pipe_ctx *pipe,
+- bool lock);
++ /* Bandwidth Related */
++ void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++ bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);
++#endif
++ void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);
+
+- void (*pipe_control_lock_global)(
+- struct dc *dc,
+- struct pipe_ctx *pipe,
+- bool lock);
+- void (*blank_pixel_data)(
+- struct dc *dc,
++ /* Infopacket Related */
++ void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
++ void (*send_immediate_sdp_message)(
+ struct pipe_ctx *pipe_ctx,
+- bool blank);
+-
+- void (*prepare_bandwidth)(
+- struct dc *dc,
+- struct dc_state *context);
+- void (*optimize_bandwidth)(
+- struct dc *dc,
+- struct dc_state *context);
+-
+- void (*exit_optimized_pwr_state)(
+- const struct dc *dc,
+- struct dc_state *context);
+- void (*optimize_pwr_state)(
+- const struct dc *dc,
+- struct dc_state *context);
+-
+- bool (*update_bandwidth)(
+- struct dc *dc,
+- struct dc_state *context);
++ const uint8_t *custom_sdp_message,
++ unsigned int sdp_message_size);
++ void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
++ void (*set_dmdata_attributes)(struct pipe_ctx *pipe);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
+ bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
++#endif
+
+- void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
+- unsigned int vmin, unsigned int vmax,
+- unsigned int vmid, unsigned int vmid_frame_number);
+-
+- void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
+- struct crtc_position *position);
+-
+- void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
+- int num_pipes, const struct dc_static_screen_events *events);
+-
+- enum dc_status (*enable_stream_timing)(
+- struct pipe_ctx *pipe_ctx,
+- struct dc_state *context,
+- struct dc *dc);
+-
+- void (*setup_stereo)(
+- struct pipe_ctx *pipe_ctx,
+- struct dc *dc);
+-
+- void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
+-
+- void (*log_hw_state)(struct dc *dc,
+- struct dc_log_buffer_ctx *log_ctx);
+- void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
+- void (*clear_status_bits)(struct dc *dc, unsigned int mask);
+-
+- void (*wait_for_mpcc_disconnect)(struct dc *dc,
+- struct resource_pool *res_pool,
+- struct pipe_ctx *pipe_ctx);
+-
+- void (*edp_power_control)(
+- struct dc_link *link,
+- bool enable);
+- void (*edp_backlight_control)(
+- struct dc_link *link,
+- bool enable);
+- void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+-
++ /* Cursor Related */
+ void (*set_cursor_position)(struct pipe_ctx *pipe);
+ void (*set_cursor_attribute)(struct pipe_ctx *pipe);
+ void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
+
+- void (*setup_periodic_interrupt)(struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
+- enum vline_select vline);
+- void (*setup_vupdate_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+- bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+- void (*init_blank)(struct dc *dc, struct timing_generator *tg);
+- void (*disable_vga)(struct dce_hwseq *hws);
+- void (*bios_golden_init)(struct dc *dc);
+- void (*plane_atomic_power_down)(struct dc *dc,
+- struct dpp *dpp,
+- struct hubp *hubp);
+-
+- void (*plane_atomic_disable)(
+- struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+- void (*enable_power_gating_plane)(
+- struct dce_hwseq *hws,
+- bool enable);
+-
+- void (*dpp_pg_control)(
+- struct dce_hwseq *hws,
+- unsigned int dpp_inst,
+- bool power_on);
+-
+- void (*hubp_pg_control)(
+- struct dce_hwseq *hws,
+- unsigned int hubp_inst,
+- bool power_on);
+-
+- void (*dsc_pg_control)(
+- struct dce_hwseq *hws,
+- unsigned int dsc_inst,
+- bool power_on);
+-
++ /* Colour Related */
++ void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);
++ void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,
++ enum dc_color_space colorspace,
++ uint16_t *matrix, int opp_id);
+
+- void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+- void (*program_all_writeback_pipes_in_tree)(
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++ /* VM Related */
++ int (*init_sys_ctx)(struct dce_hwseq *hws,
+ struct dc *dc,
+- const struct dc_stream_state *stream,
+- struct dc_state *context);
++ struct dc_phy_addr_space_config *pa_config);
++ void (*init_vm_ctx)(struct dce_hwseq *hws,
++ struct dc *dc,
++ struct dc_virtual_addr_space_config *va_config,
++ int vmid);
++
++ /* Writeback Related */
+ void (*update_writeback)(struct dc *dc,
+ const struct dc_stream_status *stream_status,
+ struct dc_writeback_info *wb_info,
+@@ -330,48 +173,34 @@ struct hw_sequencer_funcs {
+ struct dc_state *context);
+ void (*disable_writeback)(struct dc *dc,
+ unsigned int dwb_pipe_inst);
+- enum dc_status (*set_clock)(struct dc *dc,
+- enum dc_clock_type clock_type,
+- uint32_t clk_khz,
+- uint32_t stepping);
++#endif
+
+- void (*get_clock)(struct dc *dc,
++ /* Clock Related */
++ enum dc_status (*set_clock)(struct dc *dc,
+ enum dc_clock_type clock_type,
++ uint32_t clk_khz, uint32_t stepping);
++ void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg);
+
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+- bool (*s0i3_golden_init_wa)(struct dc *dc);
+-#endif
+-
+- void (*get_surface_visual_confirm_color)(
+- const struct pipe_ctx *pipe_ctx,
+- struct tg_color *color);
+-
+- void (*get_hdr_visual_confirm_color)(
+- struct pipe_ctx *pipe_ctx,
+- struct tg_color *color);
+-
+- void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
+-
+- void (*verify_allow_pstate_change_high)(struct dc *dc);
+-
+- void (*program_pipe)(
+- struct dc *dc,
+- struct pipe_ctx *pipe_ctx,
++ void (*optimize_pwr_state)(const struct dc *dc,
++ struct dc_state *context);
++ void (*exit_optimized_pwr_state)(const struct dc *dc,
+ struct dc_state *context);
+
+- bool (*wait_for_blank_complete)(
+- struct output_pixel_processor *opp);
++ /* Audio Related */
++ void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
++ void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
+
+- void (*dccg_init)(struct dce_hwseq *hws);
++ /* Stereo 3D Related */
++ void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);
+
+- bool (*set_blend_lut)(
+- struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++ /* HW State Logging Related */
++ void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);
++ void (*get_hw_state)(struct dc *dc, char *pBuf,
++ unsigned int bufSize, unsigned int mask);
++ void (*clear_status_bits)(struct dc *dc, unsigned int mask);
+
+- bool (*set_shaper_3dlut)(
+- struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+
+- int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
+ };
+
+ void color_space_to_black_color(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+new file mode 100644
+index 000000000000..8ba06f015975
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+@@ -0,0 +1,156 @@
++/*
++ * Copyright 2015 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_HW_SEQUENCER_PRIVATE_H__
++#define __DC_HW_SEQUENCER_PRIVATE_H__
++
++#include "dc_types.h"
++
++enum pipe_gating_control {
++ PIPE_GATING_CONTROL_DISABLE = 0,
++ PIPE_GATING_CONTROL_ENABLE,
++ PIPE_GATING_CONTROL_INIT
++};
++
++struct dce_hwseq_wa {
++ bool blnd_crtc_trigger;
++ bool DEGVIDCN10_253;
++ bool false_optc_underflow;
++ bool DEGVIDCN10_254;
++ bool DEGVIDCN21;
++};
++
++struct hwseq_wa_state {
++ bool DEGVIDCN10_253_applied;
++};
++
++struct pipe_ctx;
++struct dc_state;
++struct dc_stream_status;
++struct dc_writeback_info;
++struct dchub_init_data;
++struct dc_static_screen_events;
++struct resource_pool;
++struct resource_context;
++struct stream_resource;
++struct dc_phy_addr_space_config;
++struct dc_virtual_addr_space_config;
++struct hubp;
++struct dpp;
++struct dce_hwseq;
++struct timing_generator;
++struct tg_color;
++struct output_pixel_processor;
++
++struct hwseq_private_funcs {
++
++ void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++ void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++ void (*init_pipes)(struct dc *dc, struct dc_state *context);
++ void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
++ void (*update_plane_addr)(const struct dc *dc,
++ struct pipe_ctx *pipe_ctx);
++ void (*plane_atomic_disconnect)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx);
++ void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++ bool (*set_input_transfer_func)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ const struct dc_plane_state *plane_state);
++ bool (*set_output_transfer_func)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ const struct dc_stream_state *stream);
++ void (*power_down)(struct dc *dc);
++ void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
++ bool clock_gating);
++ bool (*enable_display_power_gating)(struct dc *dc,
++ uint8_t controller_id,
++ struct dc_bios *dcb,
++ enum pipe_gating_control power_gating);
++ void (*blank_pixel_data)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ bool blank);
++ enum dc_status (*enable_stream_timing)(
++ struct pipe_ctx *pipe_ctx,
++ struct dc_state *context,
++ struct dc *dc);
++ void (*edp_backlight_control)(struct dc_link *link,
++ bool enable);
++ void (*setup_vupdate_interrupt)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx);
++ bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++ void (*init_blank)(struct dc *dc, struct timing_generator *tg);
++ void (*disable_vga)(struct dce_hwseq *hws);
++ void (*bios_golden_init)(struct dc *dc);
++ void (*plane_atomic_power_down)(struct dc *dc,
++ struct dpp *dpp,
++ struct hubp *hubp);
++ void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++ void (*enable_power_gating_plane)(struct dce_hwseq *hws,
++ bool enable);
++ void (*dpp_pg_control)(struct dce_hwseq *hws,
++ unsigned int dpp_inst,
++ bool power_on);
++ void (*hubp_pg_control)(struct dce_hwseq *hws,
++ unsigned int hubp_inst,
++ bool power_on);
++ void (*dsc_pg_control)(struct dce_hwseq *hws,
++ unsigned int dsc_inst,
++ bool power_on);
++ void (*update_odm)(struct dc *dc, struct dc_state *context,
++ struct pipe_ctx *pipe_ctx);
++ void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
++ const struct dc_stream_state *stream,
++ struct dc_state *context);
++ bool (*s0i3_golden_init_wa)(struct dc *dc);
++ void (*get_surface_visual_confirm_color)(
++ const struct pipe_ctx *pipe_ctx,
++ struct tg_color *color);
++ void (*get_hdr_visual_confirm_color)(struct pipe_ctx *pipe_ctx,
++ struct tg_color *color);
++ void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
++ void (*verify_allow_pstate_change_high)(struct dc *dc);
++ void (*program_pipe)(struct dc *dc,
++ struct pipe_ctx *pipe_ctx,
++ struct dc_state *context);
++ bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
++ void (*dccg_init)(struct dce_hwseq *hws);
++ bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
++ const struct dc_plane_state *plane_state);
++ bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
++ const struct dc_plane_state *plane_state);
++};
++
++struct dce_hwseq {
++ struct dc_context *ctx;
++ const struct dce_hwseq_registers *regs;
++ const struct dce_hwseq_shift *shifts;
++ const struct dce_hwseq_mask *masks;
++ struct dce_hwseq_wa wa;
++ struct hwseq_wa_state wa_state;
++ struct hwseq_private_funcs funcs;
++
++};
++
++#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4669-drm-amd-display-Fix-Dali-clk-mgr-construct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4669-drm-amd-display-Fix-Dali-clk-mgr-construct.patch
new file mode 100644
index 00000000..d7efc9d9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4669-drm-amd-display-Fix-Dali-clk-mgr-construct.patch
@@ -0,0 +1,72 @@
+From 74ad82d1beb22c28091571a377d8f5709655591b Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Mon, 4 Nov 2019 13:39:20 -0500
+Subject: [PATCH 4669/4736] drm/amd/display: Fix Dali clk mgr construct
+
+[WHY]
+Dali is currently being misinterpreted as Renoir,
+as a result uses wrong clk mgr constructor
+
+[HOW]
+Add check to init Dali as Raven2 before it can be misidentified
+Clean up & fix Raven2 & Dali ASIC checks
+
+Change-Id: I56de017317487ab06085f56ca590680eb7a01be1
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 7 +++++++
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 11 +++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+index 3d42bb4355f8..5f64036982fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+@@ -134,6 +134,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case FAMILY_RV:
++ if (ASICREV_IS_DALI(asic_id.hw_internal_rev)) {
++ /* TEMP: this check has to come before ASICREV_IS_RENOIR */
++ /* which also incorrectly returns true for Dali */
++ rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
++ break;
++ }
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
+ rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index d51fe99349ed..0b4f5fde387b 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -134,18 +134,17 @@
+ /* DCN1_01 */
+ #define PICASSO_A0 0x41
+ #define RAVEN2_A0 0x81
++#define RAVEN2_15D8_REV_E3 0xE3
++#define RAVEN2_15D8_REV_E4 0xE4
+ #define RAVEN1_F0 0xF0
+ #define RAVEN_UNKNOWN 0xFF
+
+-#define PICASSO_15D8_REV_E3 0xE3
+-#define PICASSO_15D8_REV_E4 0xE4
+-
+ #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
+ #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
+-#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < PICASSO_15D8_REV_E3))
+-#define ASICREV_IS_DALI(eChipRev) ((eChipRev >= PICASSO_15D8_REV_E3) && (eChipRev < RAVEN1_F0))
+-
++#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RAVEN1_F0))
+ #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
++#define ASICREV_IS_DALI(eChipRev) ((eChipRev == RAVEN2_15D8_REV_E3) \
++ || (eChipRev == RAVEN2_15D8_REV_E4))
+
+ #define FAMILY_RV 142 /* DCN 1*/
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch
new file mode 100644
index 00000000..3b5227d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch
@@ -0,0 +1,72 @@
+From 9666c46fe746cf775aef8e3a8470ab4e62c15f00 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 7 Nov 2019 13:06:48 -0500
+Subject: [PATCH 4670/4736] drm/amd/display: Map DSC resources 1-to-1 if
+ numbers of OPPs and DSCs are equal
+
+[why]
+On ASICs where number of DSCs is the same as OPPs there's no need
+for DSC resource management. Mappping 1-to-1 fixes mode-set- or S3-
+-related issues for such platforms.
+
+[how]
+Map DSC resources 1-to-1 to pipes only if number of OPPs is the same
+as number of DSCs. This will still keep other ASICs working.
+A follow-up patch to fix mode-set issues on those ASICs will be
+required if testing shows issues with mode set.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index b000d5289684..2e03ff357746 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1524,13 +1524,20 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state
+
+ static void acquire_dsc(struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+- struct display_stream_compressor **dsc)
++ struct display_stream_compressor **dsc,
++ int pipe_idx)
+ {
+ int i;
+
+ ASSERT(*dsc == NULL);
+ *dsc = NULL;
+
++ if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
++ *dsc = pool->dscs[pipe_idx];
++ res_ctx->is_dsc_acquired[pipe_idx] = true;
++ return;
++ }
++
+ /* Find first free DSC */
+ for (i = 0; i < pool->res_cap->num_dsc; i++)
+ if (!res_ctx->is_dsc_acquired[i]) {
+@@ -1571,7 +1578,7 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+ if (pipe_ctx->stream != dc_stream)
+ continue;
+
+- acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
++ acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
+
+ /* The number of DSCs can be less than the number of pipes */
+ if (!pipe_ctx->stream_res.dsc) {
+@@ -1763,7 +1770,7 @@ bool dcn20_split_stream_for_odm(
+ }
+ next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+ if (next_odm_pipe->stream->timing.flags.DSC == 1) {
+- acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
++ acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
+ ASSERT(next_odm_pipe->stream_res.dsc);
+ if (next_odm_pipe->stream_res.dsc == NULL)
+ return false;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4671-drm-amd-display-fix-DalDramClockChangeLatencyNs-over.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4671-drm-amd-display-fix-DalDramClockChangeLatencyNs-over.patch
new file mode 100644
index 00000000..e8896e93
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4671-drm-amd-display-fix-DalDramClockChangeLatencyNs-over.patch
@@ -0,0 +1,41 @@
+From 44cfb929dce3ec82a8c4072e8a49547dc301f2ba Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Mon, 4 Nov 2019 16:39:35 -0500
+Subject: [PATCH 4671/4736] drm/amd/display: fix DalDramClockChangeLatencyNs
+ override
+
+[why]
+pstate_latency_us never gets updated from the hard coded value
+in rn_clk_mgr.c
+
+[how]
+update the wm table's values before we do calculations with them
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 94a5611972cc..23727c3f2e01 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1013,9 +1013,12 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
+ }
+
+ if (dc->bb_overrides.dram_clock_change_latency_ns) {
+- bb->dram_clock_change_latency_us =
++ for (i = 0; i < WM_SET_COUNT; i++) {
++ dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
+ dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
++ }
+ }
++
+ kernel_fpu_end();
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4672-drm-amd-display-Wrong-ifdef-guards-were-used-around-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4672-drm-amd-display-Wrong-ifdef-guards-were-used-around-.patch
new file mode 100644
index 00000000..babf33e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4672-drm-amd-display-Wrong-ifdef-guards-were-used-around-.patch
@@ -0,0 +1,62 @@
+From 3a072edc709fb45c1ca84d4a9d73ec153c9d8562 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Thu, 7 Nov 2019 11:16:49 -0500
+Subject: [PATCH 4672/4736] drm/amd/display: Wrong ifdef guards were used
+ around DML validation
+
+[Why]
+Wrong guards were causing the debug option not to run.
+
+[How]
+Changed the guard to the correct one, matching the rq, ttu, dlg regs struct
+members that need to be guarded. Also log a message when validation starts.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index e5cbc5bf3290..1e4919687ece 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2223,7 +2223,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ dc->hwss.program_front_end_for_ctx(dc, context);
+-#ifdef CONFIG_DRM_AMD_DC_DCN1_0
++#ifdef CONFIG_DRM_AMD_DC_DCN
+ if (dc->debug.validate_dml_output) {
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 2823be75b071..84d7ac5dd206 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -1257,6 +1257,7 @@ void hubp2_validate_dml_output(struct hubp *hubp,
+ struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
+ struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
+ DC_LOGGER_INIT(ctx->logger);
++ DC_LOG_DEBUG("DML Validation | Running Validation");
+
+ /* Requestor Regs */
+ REG_GET(HUBPRET_CONTROL,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 0be1c917b242..4408aed5087b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -267,6 +267,7 @@ void hubp21_validate_dml_output(struct hubp *hubp,
+ struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
+ struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
+ DC_LOGGER_INIT(ctx->logger);
++ DC_LOG_DEBUG("DML Validation | Running Validation");
+
+ /* Requester - Per hubp */
+ REG_GET(HUBPRET_CONTROL,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4673-drm-amd-display-Reset-PHY-in-link-re-training.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4673-drm-amd-display-Reset-PHY-in-link-re-training.patch
new file mode 100644
index 00000000..6b893f04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4673-drm-amd-display-Reset-PHY-in-link-re-training.patch
@@ -0,0 +1,222 @@
+From 82e02f0a49cee28db7f5c7f222e03ab31527e8be Mon Sep 17 00:00:00 2001
+From: Paul Hsieh <paul.hsieh@amd.com>
+Date: Fri, 1 Nov 2019 14:41:37 +0800
+Subject: [PATCH 4673/4736] drm/amd/display: Reset PHY in link re-training
+
+[Why]
+Link training failed randomly when plugging USB-C display in/out.
+
+[How]
+If link training failed, reset PHY in link re-training.
+
+Change-Id: Ic0f8c50e5da346777e96fa73f1137e6c4abef9f2
+Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 31 ++-------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 68 +++++++++++++++----
+ .../drm/amd/display/dc/core/dc_link_hwss.c | 14 +---
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 5 +-
+ 4 files changed, 66 insertions(+), 52 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 9f53cbcc7152..1c056a687161 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1529,40 +1529,17 @@ static enum dc_status enable_link_dp(
+ if (state->clk_mgr && !apply_seamless_boot_optimization)
+ state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
+
+- dp_enable_link_phy(
+- link,
+- pipe_ctx->stream->signal,
+- pipe_ctx->clock_source->id,
+- &link_settings);
+-
+- if (stream->sink_patches.dppowerup_delay > 0) {
+- int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
+-
+- msleep(delay_dp_power_up_in_ms);
+- }
+-
+- panel_mode = dp_get_panel_mode(link);
+- dp_set_panel_mode(link, panel_mode);
+-
+- /* We need to do this before the link training to ensure the idle pattern in SST
+- * mode will be sent right after the link training */
+- link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+- pipe_ctx->stream_res.stream_enc->id, true);
+ skip_video_pattern = true;
+
+ if (link_settings.link_rate == LINK_RATE_LOW)
+ skip_video_pattern = false;
+
+- if (link->aux_access_disabled) {
+- dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
+-
+- link->cur_link_settings = link_settings;
+- status = DC_OK;
+- } else if (perform_link_training_with_retries(
+- link,
++ if (perform_link_training_with_retries(
+ &link_settings,
+ skip_video_pattern,
+- LINK_TRAINING_ATTEMPTS)) {
++ LINK_TRAINING_ATTEMPTS,
++ pipe_ctx,
++ pipe_ctx->stream->signal)) {
+ link->cur_link_settings = link_settings;
+ status = DC_OK;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 272261192e82..537b4dee8f22 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1433,23 +1433,58 @@ enum link_training_result dc_link_dp_perform_link_training(
+ }
+
+ bool perform_link_training_with_retries(
+- struct dc_link *link,
+ const struct dc_link_settings *link_setting,
+ bool skip_video_pattern,
+- int attempts)
++ int attempts,
++ struct pipe_ctx *pipe_ctx,
++ enum signal_type signal)
+ {
+ uint8_t j;
+ uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
++ struct dc_stream_state *stream = pipe_ctx->stream;
++ struct dc_link *link = stream->link;
++ enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
+
+ for (j = 0; j < attempts; ++j) {
+
+- if (dc_link_dp_perform_link_training(
++ dp_enable_link_phy(
++ link,
++ signal,
++ pipe_ctx->clock_source->id,
++ link_setting);
++
++ if (stream->sink_patches.dppowerup_delay > 0) {
++ int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
++
++ msleep(delay_dp_power_up_in_ms);
++ }
++
++ dp_set_panel_mode(link, panel_mode);
++
++ /* We need to do this before the link training to ensure the idle pattern in SST
++ * mode will be sent right after the link training
++ */
++ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
++ pipe_ctx->stream_res.stream_enc->id, true);
++
++ if (link->aux_access_disabled) {
++ dc_link_dp_perform_link_training_skip_aux(link, link_setting);
++ return true;
++ } else if (dc_link_dp_perform_link_training(
+ link,
+ link_setting,
+ skip_video_pattern) == LINK_TRAINING_SUCCESS)
+ return true;
+
++ /* latest link training still fail, skip delay and keep PHY on
++ */
++ if (j == (attempts - 1))
++ break;
++
++ dp_disable_link_phy(link, signal);
++
+ msleep(delay_between_attempts);
++
+ delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
+ }
+
+@@ -2770,17 +2805,26 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ sizeof(hpd_irq_dpcd_data),
+ "Status: ");
+
+- perform_link_training_with_retries(link,
+- &link->cur_link_settings,
+- true, LINK_TRAINING_ATTEMPTS);
+-
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
+- if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link &&
+- pipe_ctx->stream->dpms_off == false &&
+- pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+- dc_link_allocate_mst_payload(pipe_ctx);
+- }
++ if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
++ break;
++ }
++
++ if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
++ return false;
++
++ dp_disable_link_phy(link, pipe_ctx->stream->signal);
++
++ perform_link_training_with_retries(&link->cur_link_settings,
++ true, LINK_TRAINING_ATTEMPTS,
++ pipe_ctx,
++ pipe_ctx->stream->signal);
++
++ if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link &&
++ pipe_ctx->stream->dpms_off == false &&
++ pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
++ dc_link_allocate_mst_payload(pipe_ctx);
+ }
+
+ status = false;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 67ce12df23f1..548aac02ca11 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -333,20 +333,12 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ memset(&link->cur_link_settings, 0,
+ sizeof(link->cur_link_settings));
+
+- link->link_enc->funcs->enable_dp_output(
+- link->link_enc,
+- link_setting,
+- pipes[i].clock_source->id);
+- link->cur_link_settings = *link_setting;
+-
+- dp_receiver_power_ctrl(link, true);
+-
+ perform_link_training_with_retries(
+- link,
+ link_setting,
+ skip_video_pattern,
+- LINK_TRAINING_ATTEMPTS);
+-
++ LINK_TRAINING_ATTEMPTS,
++ &pipes[i],
++ SIGNAL_TYPE_DISPLAY_PORT);
+
+ link->dc->hwss.enable_stream(&pipes[i]);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 4879cf54d8f1..6198bccd6199 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -57,10 +57,11 @@ void decide_link_settings(
+ struct dc_link_settings *link_setting);
+
+ bool perform_link_training_with_retries(
+- struct dc_link *link,
+ const struct dc_link_settings *link_setting,
+ bool skip_video_pattern,
+- int attempts);
++ int attempts,
++ struct pipe_ctx *pipe_ctx,
++ enum signal_type signal);
+
+ bool is_mst_supported(struct dc_link *link);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4674-drm-amd-display-Disable-link-before-reenable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4674-drm-amd-display-Disable-link-before-reenable.patch
new file mode 100644
index 00000000..9353d982
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4674-drm-amd-display-Disable-link-before-reenable.patch
@@ -0,0 +1,160 @@
+From 3c4dd133170621e51501ff2a16471573b918241e Mon Sep 17 00:00:00 2001
+From: Lucy Li <lucy.li@amd.com>
+Date: Fri, 25 Oct 2019 17:59:32 -0400
+Subject: [PATCH 4674/4736] drm/amd/display: Disable link before reenable
+
+[Why]
+Black screen seen after display is disabled then re-enabled.
+Caused by difference in link settings when
+switching between different resolutions.
+
+[How]
+In PnP case, or whenever the display is
+still enabled but the driver is unloaded,
+disable link before re-enabling with new link settings.
+
+Change-Id: I049a0b164daa0a2e3009227f15b4e7f1aa3e8472
+Signed-off-by: Lucy Li <lucy.li@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 101 ++++++++++--------
+ 1 file changed, 54 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 1c056a687161..2accc35996cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1510,15 +1510,6 @@ static enum dc_status enable_link_dp(
+ decide_link_settings(stream, &link_settings);
+
+ if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
+- /* If link settings are different than current and link already enabled
+- * then need to disable before programming to new rate.
+- */
+- if (link->link_status.link_active &&
+- (link->cur_link_settings.lane_count != link_settings.lane_count ||
+- link->cur_link_settings.link_rate != link_settings.link_rate)) {
+- dp_disable_link_phy(link, pipe_ctx->stream->signal);
+- }
+-
+ /*in case it is not on*/
+ link->dc->hwss.edp_power_control(link, true);
+ link->dc->hwss.edp_wait_for_hpd_ready(link, true);
+@@ -2038,6 +2029,47 @@ static void write_i2c_redriver_setting(
+ ASSERT(i2c_success);
+ }
+
++static void disable_link(struct dc_link *link, enum signal_type signal)
++{
++ /*
++ * TODO: implement call for dp_set_hw_test_pattern
++ * it is needed for compliance testing
++ */
++
++ /* Here we need to specify that encoder output settings
++ * need to be calculated as for the set mode,
++ * it will lead to querying dynamic link capabilities
++ * which should be done before enable output
++ */
++
++ if (dc_is_dp_signal(signal)) {
++ /* SST DP, eDP */
++ if (dc_is_dp_sst_signal(signal))
++ dp_disable_link_phy(link, signal);
++ else
++ dp_disable_link_phy_mst(link, signal);
++#if CONFIG_DRM_AMD_DC_DSC_SUPPORT
++
++ if (dc_is_dp_sst_signal(signal) ||
++ link->mst_stream_alloc_table.stream_count == 0) {
++ dp_set_fec_enable(link, false);
++ dp_set_fec_ready(link, false);
++ }
++#endif
++ } else {
++ if (signal != SIGNAL_TYPE_VIRTUAL)
++ link->link_enc->funcs->disable_output(link->link_enc, signal);
++ }
++
++ if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
++ /* MST disable link only when no stream use the link */
++ if (link->mst_stream_alloc_table.stream_count <= 0)
++ link->link_status.link_active = false;
++ } else {
++ link->link_status.link_active = false;
++ }
++}
++
+ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
+ {
+ struct dc_stream_state *stream = pipe_ctx->stream;
+@@ -2122,6 +2154,19 @@ static enum dc_status enable_link(
+ struct pipe_ctx *pipe_ctx)
+ {
+ enum dc_status status = DC_ERROR_UNEXPECTED;
++ struct dc_stream_state *stream = pipe_ctx->stream;
++ struct dc_link *link = stream->link;
++
++ /* There's some scenarios where driver is unloaded with display
++ * still enabled. When driver is reloaded, it may cause a display
++ * to not light up if there is a mismatch between old and new
++ * link settings. Need to call disable first before enabling at
++ * new link settings.
++ */
++ if (link->link_status.link_active) {
++ disable_link(link, pipe_ctx->stream->signal);
++ }
++
+ switch (pipe_ctx->stream->signal) {
+ case SIGNAL_TYPE_DISPLAY_PORT:
+ status = enable_link_dp(state, pipe_ctx);
+@@ -2156,44 +2201,6 @@ static enum dc_status enable_link(
+ return status;
+ }
+
+-static void disable_link(struct dc_link *link, enum signal_type signal)
+-{
+- /*
+- * TODO: implement call for dp_set_hw_test_pattern
+- * it is needed for compliance testing
+- */
+-
+- /* here we need to specify that encoder output settings
+- * need to be calculated as for the set mode,
+- * it will lead to querying dynamic link capabilities
+- * which should be done before enable output */
+-
+- if (dc_is_dp_signal(signal)) {
+- /* SST DP, eDP */
+- if (dc_is_dp_sst_signal(signal))
+- dp_disable_link_phy(link, signal);
+- else
+- dp_disable_link_phy_mst(link, signal);
+-
+- if (dc_is_dp_sst_signal(signal) ||
+- link->mst_stream_alloc_table.stream_count == 0) {
+- dp_set_fec_enable(link, false);
+- dp_set_fec_ready(link, false);
+- }
+- } else {
+- if (signal != SIGNAL_TYPE_VIRTUAL)
+- link->link_enc->funcs->disable_output(link->link_enc, signal);
+- }
+-
+- if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+- /* MST disable link only when no stream use the link */
+- if (link->mst_stream_alloc_table.stream_count <= 0)
+- link->link_status.link_active = false;
+- } else {
+- link->link_status.link_active = false;
+- }
+-}
+-
+ static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
+ {
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4675-drm-amd-display-Add-DMCUB__PG_DONE-trace-code-enum.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4675-drm-amd-display-Add-DMCUB__PG_DONE-trace-code-enum.patch
new file mode 100644
index 00000000..d6e6f8cb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4675-drm-amd-display-Add-DMCUB__PG_DONE-trace-code-enum.patch
@@ -0,0 +1,27 @@
+From c19ec949b364f286216abec57bf877a785b8684d Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Thu, 7 Nov 2019 14:41:06 -0500
+Subject: [PATCH 4675/4736] drm/amd/display: Add DMCUB__PG_DONE trace code enum
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+index b0ee099d8a6e..6b3ee42db350 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+@@ -45,6 +45,7 @@ enum dmucb_trace_code {
+ DMCUB__DMCU_ISR_LOAD_END,
+ DMCUB__MAIN_IDLE,
+ DMCUB__PERF_TRACE,
++ DMCUB__PG_DONE,
+ };
+
+ struct dmcub_trace_buf_entry {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch
new file mode 100644
index 00000000..e3c108ef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch
@@ -0,0 +1,96 @@
+From 782580b82c79ff0c4f03499165587f81f9166545 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 7 Nov 2019 15:26:14 -0500
+Subject: [PATCH 4676/4736] drm/amd/display: Only wait for DMUB phy init on
+ dcn21
+
+[Why]
+The wait for PHY init won't finish if the firmware doesn't support it.
+
+[How]
+Only hook this functionality up on DCN21 and move it out of DCN20.
+
+For ASIC without support then this should return OK so we don't hang
+while waiting in DC.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 5 -----
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 2 --
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 5 +++++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 2 ++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
+ 5 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index e2b2cf2e01fd..6b7d54572aa3 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -135,8 +135,3 @@ bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
+
+ return supported;
+ }
+-
+-bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub)
+-{
+- return REG_READ(DMCUB_SCRATCH10) == 0;
+-}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+index e1ba748ca594..ca7db03b94f7 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -59,6 +59,4 @@ bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);
+
+ bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
+
+-bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub);
+-
+ #endif /* _DMUB_DCN20_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+index d40a808112e7..b9dc2dd645eb 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+@@ -124,3 +124,8 @@ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
+ {
+ return (REG_READ(DMCUB_SCRATCH0) == 3);
+ }
++
++bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub)
++{
++ return REG_READ(DMCUB_SCRATCH10) == 0;
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+index f57969d8d56f..9e5f195e288f 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+@@ -42,4 +42,6 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+
+ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
+
++bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub);
++
+ #endif /* _DMUB_DCN21_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 60c574a39c6a..3ec26f6af2e1 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -76,13 +76,13 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
+ funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
+ funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
+ funcs->is_supported = dmub_dcn20_is_supported;
+- funcs->is_phy_init = dmub_dcn20_is_phy_init;
+ funcs->is_hw_init = dmub_dcn20_is_hw_init;
+
+ if (asic == DMUB_ASIC_DCN21) {
+ funcs->backdoor_load = dmub_dcn21_backdoor_load;
+ funcs->setup_windows = dmub_dcn21_setup_windows;
+ funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
++ funcs->is_phy_init = dmub_dcn21_is_phy_init;
+ }
+ break;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4677-drm-amd-display-Return-DMUB_STATUS_OK-when-autoload-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4677-drm-amd-display-Return-DMUB_STATUS_OK-when-autoload-.patch
new file mode 100644
index 00000000..236a3b43
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4677-drm-amd-display-Return-DMUB_STATUS_OK-when-autoload-.patch
@@ -0,0 +1,55 @@
+From c13b68221785174927af4bfa3b0fbd3a16f422d4 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 7 Nov 2019 15:29:20 -0500
+Subject: [PATCH 4677/4736] drm/amd/display: Return DMUB_STATUS_OK when
+ autoload unsupported
+
+[Why]
+Not having support for autoload isn't an error. If the DMUB firmware
+doesn't support it then don't return DMUB_STATUS_INVALID.
+
+[How]
+Return DMUB_STATUS_OK when ->is_auto_load_done is NULL.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 3ec26f6af2e1..70c7a4be9ccc 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -379,9 +379,12 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
+ {
+ uint32_t i;
+
+- if (!dmub->hw_init || !dmub->hw_funcs.is_auto_load_done)
++ if (!dmub->hw_init)
+ return DMUB_STATUS_INVALID;
+
++ if (!dmub->hw_funcs.is_auto_load_done)
++ return DMUB_STATUS_OK;
++
+ for (i = 0; i <= timeout_us; i += 100) {
+ if (dmub->hw_funcs.is_auto_load_done(dmub))
+ return DMUB_STATUS_OK;
+@@ -397,9 +400,12 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
+ {
+ uint32_t i = 0;
+
+- if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
++ if (!dmub->hw_init)
+ return DMUB_STATUS_INVALID;
+
++ if (!dmub->hw_funcs.is_phy_init)
++ return DMUB_STATUS_OK;
++
+ for (i = 0; i <= timeout_us; i += 10) {
+ if (dmub->hw_funcs.is_phy_init(dmub))
+ return DMUB_STATUS_OK;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4678-drm-amd-display-Program-CW5-for-tracebuffer-for-dcn2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4678-drm-amd-display-Program-CW5-for-tracebuffer-for-dcn2.patch
new file mode 100644
index 00000000..8ef818c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4678-drm-amd-display-Program-CW5-for-tracebuffer-for-dcn2.patch
@@ -0,0 +1,44 @@
+From 707425f3dc83a06cc415181f5feaeb564a8c06ae Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 7 Nov 2019 15:47:46 -0500
+Subject: [PATCH 4678/4736] drm/amd/display: Program CW5 for tracebuffer for
+ dcn20
+
+[Why]
+On dcn21 this is programmed for tracebuffer support but isn't being
+programmed on dcn20.
+
+DMCUB execution hits an undefined address 65000000 on tracebuffer
+access.
+
+[How]
+Program CW5.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 6b7d54572aa3..302dd3d4b77d 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -99,6 +99,13 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
+ cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
+ 1);
++
++ REG_WRITE(DMCUB_REGION3_CW5_OFFSET, cw5->offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, cw5->offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
++ REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
++ DMCUB_REGION3_CW5_ENABLE, 1);
+ }
+
+ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4679-drm-amd-display-populate-bios-integrated-info-for-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4679-drm-amd-display-populate-bios-integrated-info-for-re.patch
new file mode 100644
index 00000000..ad12328e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4679-drm-amd-display-populate-bios-integrated-info-for-re.patch
@@ -0,0 +1,75 @@
+From fb7ee5165ca7e7f7a2e32db8335f71b73550d8ff Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Thu, 7 Nov 2019 19:20:00 -0500
+Subject: [PATCH 4679/4736] drm/amd/display: populate bios integrated info for
+ renoir
+
+[Why]
+When video_memory_type bw_params->vram_type
+is assigned, wedistinguish between Ddr4MemType and LpDdr4MemType.
+Because of this we will never report that we are using
+LpDdr4MemType and never re-purpose WM set D
+
+[How]
+populate bios integrated info for renoir by adding the
+revision number for renoir and use that integrated info
+table instead of of asic_id to get the vram type
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 +
+ .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 10 ++++++----
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 453ac65c7ee3..8b2426f14519 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1636,6 +1636,7 @@ static enum bp_result construct_integrated_info(
+ /* Don't need to check major revision as they are all 1 */
+ switch (revision.minor) {
+ case 11:
++ case 12:
+ result = get_integrated_info_v11(bp, info);
+ break;
+ default:
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 841095d09d3c..9f0381c68844 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -569,7 +569,7 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi
+ return 0;
+ }
+
+-static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
+ {
+ int i, j = 0;
+
+@@ -601,8 +601,8 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params
+ bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
+ }
+
+- bw_params->vram_type = asic_id->vram_type;
+- bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH;
++ bw_params->vram_type = bios_info->memory_type;
++ bw_params->num_channels = bios_info->ma_channel_number;
+
+ for (i = 0; i < WM_SET_COUNT; i++) {
+ bw_params->wm_table.entries[i].wm_inst = i;
+@@ -685,7 +685,9 @@ void rn_clk_mgr_construct(
+
+ if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
+ pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
+- rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
++ if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
++ rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
++ }
+ }
+
+ if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4680-drm-amd-display-Fixed-kernel-panic-when-booting-with.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4680-drm-amd-display-Fixed-kernel-panic-when-booting-with.patch
new file mode 100644
index 00000000..9c6914bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4680-drm-amd-display-Fixed-kernel-panic-when-booting-with.patch
@@ -0,0 +1,37 @@
+From 05e89b05c79f619ba3a3cedf91309d8bcd76b61d Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Thu, 7 Nov 2019 17:18:20 -0500
+Subject: [PATCH 4680/4736] drm/amd/display: Fixed kernel panic when booting
+ with DP-to-HDMI dongle
+
+[Why]
+In dc_link_is_dp_sink_present, if dal_ddc_open fails, then
+dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They
+are created only on dc_construct, and next aux access will cause a panic.
+
+[How]
+Instead of calling dal_gpio_destroy_ddc, call dal_ddc_close.
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 2accc35996cd..40d6415ba54d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -370,7 +370,7 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
+
+ if (GPIO_RESULT_OK != dal_ddc_open(
+ ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
+- dal_gpio_destroy_ddc(&ddc);
++ dal_ddc_close(ddc);
+
+ return present;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch
new file mode 100644
index 00000000..f7407cc3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch
@@ -0,0 +1,164 @@
+From 14f863bbcbc727e06ca1257e9802fb6cf74a0b60 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Fri, 8 Nov 2019 14:30:34 -0500
+Subject: [PATCH 4681/4736] drm/amd/display: have two different sr and pstate
+ latency tables for renoir
+
+[Why]
+new sr and pstate latencies are optimized for the case when we are not
+using lpddr4 memory
+
+[How]
+have two different wm tables, one for the lpddr case and one for
+non lpddr case
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 114 ++++++++++++------
+ 1 file changed, 80 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 9f0381c68844..89ed230cdb26 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -518,44 +518,83 @@ struct clk_bw_params rn_bw_params = {
+ .num_entries = 4,
+ },
+
+- .wm_table = {
+- .entries = {
+- {
+- .wm_inst = WM_A,
+- .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 11.72,
+- .sr_exit_time_us = 6.09,
+- .sr_enter_plus_exit_time_us = 7.14,
+- .valid = true,
+- },
+- {
+- .wm_inst = WM_B,
+- .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 11.72,
+- .sr_exit_time_us = 10.12,
+- .sr_enter_plus_exit_time_us = 11.48,
+- .valid = true,
+- },
+- {
+- .wm_inst = WM_C,
+- .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 11.72,
+- .sr_exit_time_us = 10.12,
+- .sr_enter_plus_exit_time_us = 11.48,
+- .valid = true,
+- },
+- {
+- .wm_inst = WM_D,
+- .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 11.72,
+- .sr_exit_time_us = 10.12,
+- .sr_enter_plus_exit_time_us = 11.48,
+- .valid = true,
+- },
++};
++
++struct wm_table ddr4_wm_table = {
++ .entries = {
++ {
++ .wm_inst = WM_A,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 6.09,
++ .sr_enter_plus_exit_time_us = 7.14,
++ .valid = true,
++ },
++ {
++ .wm_inst = WM_B,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 10.12,
++ .sr_enter_plus_exit_time_us = 11.48,
++ .valid = true,
++ },
++ {
++ .wm_inst = WM_C,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 10.12,
++ .sr_enter_plus_exit_time_us = 11.48,
++ .valid = true,
++ },
++ {
++ .wm_inst = WM_D,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 11.72,
++ .sr_exit_time_us = 10.12,
++ .sr_enter_plus_exit_time_us = 11.48,
++ .valid = true,
+ },
+ }
+ };
+
++struct wm_table lpddr4_wm_table = {
++ .entries = {
++ {
++ .wm_inst = WM_A,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 23.84,
++ .sr_exit_time_us = 12.5,
++ .sr_enter_plus_exit_time_us = 17.0,
++ .valid = true,
++ },
++ {
++ .wm_inst = WM_B,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 23.84,
++ .sr_exit_time_us = 12.5,
++ .sr_enter_plus_exit_time_us = 17.0,
++ .valid = true,
++ },
++ {
++ .wm_inst = WM_C,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 23.84,
++ .sr_exit_time_us = 12.5,
++ .sr_enter_plus_exit_time_us = 17.0,
++ .valid = true,
++ },
++ {
++ .wm_inst = WM_D,
++ .wm_type = WM_TYPE_PSTATE_CHG,
++ .pstate_latency_us = 23.84,
++ .sr_exit_time_us = 12.5,
++ .sr_enter_plus_exit_time_us = 17.0,
++ .valid = true,
++ },
++ }
++};
++
++
+ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
+ {
+ int i;
+@@ -677,10 +716,17 @@ void rn_clk_mgr_construct(
+ ASSERT(clk_mgr->base.dprefclk_khz == 600000);
+ clk_mgr->base.dprefclk_khz = 600000;
+ }
++
++ if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
++ rn_bw_params.wm_table = lpddr4_wm_table;
++ } else {
++ rn_bw_params.wm_table = ddr4_wm_table;
++ }
+ }
+
+ dce_clock_read_ss_info(clk_mgr);
+
++
+ clk_mgr->base.bw_params = &rn_bw_params;
+
+ if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch
new file mode 100644
index 00000000..f6319283
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch
@@ -0,0 +1,103 @@
+From 05da4bf83601928e4f9292175592c4cbf74ef0cd Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Sun, 10 Nov 2019 12:08:02 -0500
+Subject: [PATCH 4682/4736] drm/amd/display: fix dprefclk and ss percentage
+ reading on RN
+
+[Why]
+Before was using HW counter value to determine the dprefclk. Which
+take into account ss, but has large variation, not good enough for
+generating audio dto. Also, the bios parser code to get the ss
+percentage was not working.
+
+[How]
+After this change, dprefclk is hard coded, same as on RV. We don't
+expect this to change on Renoir. Modified bios parser code to get
+the right ss percentage.
+
+Change-Id: Ifed07a5d523b213769b6f7ed4f207cf2dc0108cd
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 +
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 +++-------------
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 +
+ 3 files changed, 5 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 8b2426f14519..42babd82ce6b 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -832,6 +832,7 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
+ case 1:
+ return get_ss_info_v4_1(bp, signal, index, ss_info);
+ case 2:
++ case 3:
+ return get_ss_info_v4_2(bp, signal, index, ss_info);
+ default:
+ break;
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 89ed230cdb26..307c8540e36f 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -675,7 +675,6 @@ void rn_clk_mgr_construct(
+ {
+ struct dc_debug_options *debug = &ctx->dc->debug;
+ struct dpm_clocks clock_table = { 0 };
+- struct clk_state_registers_and_bypass s = { 0 };
+
+ clk_mgr->base.ctx = ctx;
+ clk_mgr->base.funcs = &dcn21_funcs;
+@@ -695,7 +694,6 @@ void rn_clk_mgr_construct(
+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
+ clk_mgr->base.dentist_vco_freq_khz = 3600000;
+- clk_mgr->base.dprefclk_khz = 600000;
+ } else {
+ struct clk_log_info log_info = {0};
+
+@@ -706,24 +704,16 @@ void rn_clk_mgr_construct(
+ if (clk_mgr->base.dentist_vco_freq_khz == 0)
+ clk_mgr->base.dentist_vco_freq_khz = 3600000;
+
+- rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
+- /* Convert dprefclk units from MHz to KHz */
+- /* Value already divided by 10, some resolution lost */
+- clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
+-
+- /* in case we don't get a value from the register, use default */
+- if (clk_mgr->base.dprefclk_khz == 0) {
+- ASSERT(clk_mgr->base.dprefclk_khz == 600000);
+- clk_mgr->base.dprefclk_khz = 600000;
+- }
+-
+ if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
+ rn_bw_params.wm_table = lpddr4_wm_table;
+ } else {
+ rn_bw_params.wm_table = ddr4_wm_table;
+ }
++ /* Saved clocks configured at boot for debug purposes */
++ rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
+ }
+
++ clk_mgr->base.dprefclk_khz = 600000;
+ dce_clock_read_ss_info(clk_mgr);
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 026e6a2a2c44..c10cb4b54fae 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -196,6 +196,7 @@ struct clk_mgr {
+ int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
+ int dentist_vco_freq_khz;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
++ struct clk_state_registers_and_bypass boot_snapshot;
+ struct clk_bw_params *bw_params;
+ #endif
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4683-drm-amd-display-3.2.61.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4683-drm-amd-display-3.2.61.patch
new file mode 100644
index 00000000..b7a20366
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4683-drm-amd-display-3.2.61.patch
@@ -0,0 +1,28 @@
+From a2504978d354a7bfe97b5cac99b19d55edb728ee Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 11 Nov 2019 10:07:50 -0500
+Subject: [PATCH 4683/4736] drm/amd/display: 3.2.61
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index d710e123b53a..df833b6937a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.60"
++#define DC_VER "3.2.61"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch
new file mode 100644
index 00000000..2f211973
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch
@@ -0,0 +1,47 @@
+From 9dfa55f00ad9fc538d374cfc59d35b63b51f653a Mon Sep 17 00:00:00 2001
+From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
+Date: Thu, 7 Nov 2019 16:30:04 -0500
+Subject: [PATCH 4684/4736] drm/amd/display: Change the delay time before
+ enabling FEC
+
+[why]
+DP spec requires 1000 symbols delay between the end of link training
+and enabling FEC in the stream. Currently we are using 1 miliseconds
+delay which is not accurate.
+
+[how]
+One lane RBR should have the maximum time for transmitting 1000 LL
+codes which is 6.173 us. So using 7 microseconds delay instead of
+1 miliseconds.
+
+Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 537b4dee8f22..b10019106030 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -3951,7 +3951,14 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
+ if (link_enc->funcs->fec_set_enable &&
+ link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
+ if (link->fec_state == dc_link_fec_ready && enable) {
+- msleep(1);
++ /* Accord to DP spec, FEC enable sequence can first
++ * be transmitted anytime after 1000 LL codes have
++ * been transmitted on the link after link training
++ * completion. Using 1 lane RBR should have the maximum
++ * time for transmitting 1000 LL codes which is 6.173 us.
++ * So use 7 microseconds delay instead.
++ */
++ udelay(7);
+ link_enc->funcs->fec_set_enable(link_enc, true);
+ link->fec_state = dc_link_fec_enabled;
+ } else if (link->fec_state == dc_link_fec_enabled && !enable) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4685-drm-amd-display-fixed-that-I2C-over-AUX-didn-t-read-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4685-drm-amd-display-fixed-that-I2C-over-AUX-didn-t-read-.patch
new file mode 100644
index 00000000..578655ea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4685-drm-amd-display-fixed-that-I2C-over-AUX-didn-t-read-.patch
@@ -0,0 +1,49 @@
+From a6dc8c5b31899bb6da79f3537291a92e16fd2007 Mon Sep 17 00:00:00 2001
+From: Brandon Syu <Brandon.Syu@amd.com>
+Date: Fri, 8 Nov 2019 11:26:06 +0800
+Subject: [PATCH 4685/4736] drm/amd/display: fixed that I2C over AUX didn't
+ read data issue
+
+[Why]
+The variable mismatch assignment error.
+
+[How]
+To use uint32_t replace it.
+
+Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
+ drivers/gpu/drm/amd/display/include/i2caux_interface.h | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 60d3c164495d..c4950c735485 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -587,7 +587,7 @@ bool dal_ddc_service_query_ddc_data(
+ bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
+ struct aux_payload *payload)
+ {
+- uint8_t retrieved = 0;
++ uint32_t retrieved = 0;
+ bool ret = 0;
+
+ if (!ddc)
+diff --git a/drivers/gpu/drm/amd/display/include/i2caux_interface.h b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
+index bb012cb1a9f5..c7fbb9c3ad6b 100644
+--- a/drivers/gpu/drm/amd/display/include/i2caux_interface.h
++++ b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
+@@ -42,7 +42,7 @@ struct aux_payload {
+ bool write;
+ bool mot;
+ uint32_t address;
+- uint8_t length;
++ uint32_t length;
+ uint8_t *data;
+ /*
+ * used to return the reply type of the transaction
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4686-drm-amd-display-add-log-for-lttpr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4686-drm-amd-display-add-log-for-lttpr.patch
new file mode 100644
index 00000000..de5db3f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4686-drm-amd-display-add-log-for-lttpr.patch
@@ -0,0 +1,214 @@
+From f9251f29e72debc2f3a47f3e9eacf0d6b48bf169 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Wed, 23 Oct 2019 17:16:51 -0400
+Subject: [PATCH 4686/4736] drm/amd/display: add log for lttpr
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 125 +++++++++++++-----
+ 1 file changed, 93 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index b10019106030..486c14e0cd41 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -255,11 +255,18 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
+ = dpcd_pattern.raw;
+
+- DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
+- __func__,
+- dpcd_base_lt_offset,
+- dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
+-
++ if (is_repeater(link, offset)) {
++ DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
++ __func__,
++ offset,
++ dpcd_base_lt_offset,
++ dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
++ } else {
++ DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
++ __func__,
++ dpcd_base_lt_offset,
++ dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
++ }
+ /*****************************************************************
+ * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
+ *****************************************************************/
+@@ -289,14 +296,25 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ dpcd_lane,
+ size_in_bytes);
+
+- DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
+- __func__,
+- dpcd_base_lt_offset,
+- dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+- dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+- dpcd_lane[0].bits.MAX_SWING_REACHED,
+- dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+-
++ if (is_repeater(link, offset)) {
++ DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
++ " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
++ __func__,
++ offset,
++ dpcd_base_lt_offset,
++ dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++ dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++ dpcd_lane[0].bits.MAX_SWING_REACHED,
++ dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++ } else {
++ DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
++ __func__,
++ dpcd_base_lt_offset,
++ dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++ dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++ dpcd_lane[0].bits.MAX_SWING_REACHED,
++ dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++ }
+ if (edp_workaround) {
+ /* for eDP write in 2 parts because the 5-byte burst is
+ * causing issues on some eDP panels (EPR#366724)
+@@ -544,23 +562,42 @@ static void get_lane_status_and_drive_settings(
+
+ ln_status_updated->raw = dpcd_buf[2];
+
+- DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
+- __func__,
+- lane01_status_address, dpcd_buf[0],
+- lane01_status_address + 1, dpcd_buf[1]);
+-
++ if (is_repeater(link, offset)) {
++ DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
++ " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
++ __func__,
++ offset,
++ lane01_status_address, dpcd_buf[0],
++ lane01_status_address + 1, dpcd_buf[1]);
++ } else {
++ DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
++ __func__,
++ lane01_status_address, dpcd_buf[0],
++ lane01_status_address + 1, dpcd_buf[1]);
++ }
+ lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
+
+ if (is_repeater(link, offset))
+ lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
+ ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+
+- DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
+- __func__,
+- lane01_adjust_address,
+- dpcd_buf[lane_adjust_offset],
+- lane01_adjust_address + 1,
+- dpcd_buf[lane_adjust_offset + 1]);
++ if (is_repeater(link, offset)) {
++ DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
++ " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
++ __func__,
++ offset,
++ lane01_adjust_address,
++ dpcd_buf[lane_adjust_offset],
++ lane01_adjust_address + 1,
++ dpcd_buf[lane_adjust_offset + 1]);
++ } else {
++ DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
++ __func__,
++ lane01_adjust_address,
++ dpcd_buf[lane_adjust_offset],
++ lane01_adjust_address + 1,
++ dpcd_buf[lane_adjust_offset + 1]);
++ }
+
+ /*copy to req_settings*/
+ request_settings.link_settings.lane_count =
+@@ -656,14 +693,26 @@ static void dpcd_set_lane_settings(
+ }
+ */
+
+- DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
+- __func__,
+- lane0_set_address,
+- dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+- dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+- dpcd_lane[0].bits.MAX_SWING_REACHED,
+- dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++ if (is_repeater(link, offset)) {
++ DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
++ " 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
++ __func__,
++ offset,
++ lane0_set_address,
++ dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++ dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++ dpcd_lane[0].bits.MAX_SWING_REACHED,
++ dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+
++ } else {
++ DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
++ __func__,
++ lane0_set_address,
++ dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++ dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++ dpcd_lane[0].bits.MAX_SWING_REACHED,
++ dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++ }
+ link->cur_lane_setting = link_training_setting->lane_settings[0];
+
+ }
+@@ -1170,12 +1219,16 @@ static void configure_lttpr_mode(struct dc_link *link)
+ uint8_t repeater_id;
+ uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
+
++ DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
+ core_link_write_dpcd(link,
+ DP_PHY_REPEATER_MODE,
+ (uint8_t *)&repeater_mode,
+ sizeof(repeater_mode));
+
+ if (!link->is_lttpr_mode_transparent) {
++
++ DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
++
+ repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
+ core_link_write_dpcd(link,
+ DP_PHY_REPEATER_MODE,
+@@ -1212,8 +1265,9 @@ static void repeater_training_done(struct dc_link *link, uint32_t offset)
+ &dpcd_pattern.raw,
+ 1);
+
+- DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
++ DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
+ __func__,
++ offset,
+ dpcd_base_lt_offset,
+ dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
+ }
+@@ -1663,6 +1717,11 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
+
+ if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
+ max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
++
++ DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
++ __func__,
++ max_link_cap.lane_count,
++ max_link_cap.link_rate);
+ }
+ return max_link_cap;
+ }
+@@ -3196,6 +3255,8 @@ static bool retrieve_link_cap(struct dc_link *link)
+ link->is_lttpr_mode_transparent = true;
+ dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
+ }
++
++ CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
+ }
+
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4687-drm-amd-display-Disable-chroma-viewport-w-a-when-rot.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4687-drm-amd-display-Disable-chroma-viewport-w-a-when-rot.patch
new file mode 100644
index 00000000..9682d6fb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4687-drm-amd-display-Disable-chroma-viewport-w-a-when-rot.patch
@@ -0,0 +1,131 @@
+From d3fbb8d0c854c97620eed517bd2b48138144f6cd Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Sun, 10 Nov 2019 15:22:15 -0500
+Subject: [PATCH 4687/4736] drm/amd/display: Disable chroma viewport w/a when
+ rotated 180 degrees
+
+[WHY]
+Previous Renoir chroma viewport workaround fixed an MPO flicker by
+increasing the chroma viewport size. However, when the MPO plane is
+rotated 180 degrees, the viewport is read in reverse. Since the workaround
+increases viewport size, when reading in reverse it causes a vertical
+chroma offset.
+
+[HOW]
+Pass rotation value to viewport set functions
+Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 4 +++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 7 +++++--
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 +++-
+ 6 files changed, 17 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 31b64733d693..4d1301e5eaf5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -810,7 +810,8 @@ static void hubp1_set_vm_context0_settings(struct hubp *hubp,
+ void min_set_viewport(
+ struct hubp *hubp,
+ const struct rect *viewport,
+- const struct rect *viewport_c)
++ const struct rect *viewport_c,
++ enum dc_rotation_angle rotation)
+ {
+ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index 780af5b3c16f..e44eaae5033b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -749,7 +749,9 @@ void hubp1_set_blank(struct hubp *hubp, bool blank);
+
+ void min_set_viewport(struct hubp *hubp,
+ const struct rect *viewport,
+- const struct rect *viewport_c);
++ const struct rect *viewport_c,
++ enum dc_rotation_angle rotation);
++/* rotation angle added for use by hubp21_set_viewport */
+
+ void hubp1_clk_cntl(struct hubp *hubp, bool enable);
+ void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 528a6a953be4..24bebec84316 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2288,7 +2288,8 @@ static void dcn10_update_dchubp_dpp(
+ hubp->funcs->mem_program_viewport(
+ hubp,
+ &pipe_ctx->plane_res.scl_data.viewport,
+- &pipe_ctx->plane_res.scl_data.viewport_c);
++ &pipe_ctx->plane_res.scl_data.viewport_c,
++ plane_state->rotation);
+ }
+
+ if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index d99e882bd555..3e016a57f1ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1386,7 +1386,8 @@ static void dcn20_update_dchubp_dpp(
+ hubp->funcs->mem_program_viewport(
+ hubp,
+ &pipe_ctx->plane_res.scl_data.viewport,
+- &pipe_ctx->plane_res.scl_data.viewport_c);
++ &pipe_ctx->plane_res.scl_data.viewport_c,
++ plane_state->rotation);
+
+ /* Any updates are handled in dc interface, just need to apply existing for plane enable */
+ if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 4408aed5087b..38661b9c61f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -169,7 +169,8 @@ static void hubp21_setup(
+ void hubp21_set_viewport(
+ struct hubp *hubp,
+ const struct rect *viewport,
+- const struct rect *viewport_c)
++ const struct rect *viewport_c,
++ enum dc_rotation_angle rotation)
+ {
+ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
+ int patched_viewport_height = 0;
+@@ -196,9 +197,11 @@ void hubp21_set_viewport(
+ * Work around for underflow issue with NV12 + rIOMMU translation
+ * + immediate flip. This will cause hubp underflow, but will not
+ * be user visible since underflow is in blank region
++ * Disable w/a when rotated 180 degrees, causes vertical chroma offset
+ */
+ patched_viewport_height = viewport_c->height;
+- if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) {
++ if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa &&
++ rotation != ROTATION_ANGLE_180) {
+ int pte_row_height = 0;
+ int pte_rows = 0;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 9793da0f3c7e..85a34dde8526 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -82,7 +82,9 @@ struct hubp_funcs {
+ void (*mem_program_viewport)(
+ struct hubp *hubp,
+ const struct rect *viewport,
+- const struct rect *viewport_c);
++ const struct rect *viewport_c,
++ enum dc_rotation_angle rotation);
++ /* rotation needed for Renoir workaround */
+
+ bool (*hubp_program_surface_flip_and_addr)(
+ struct hubp *hubp,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4688-drm-amd-display-fix-dml20-min_dst_y_next_start-calcu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4688-drm-amd-display-fix-dml20-min_dst_y_next_start-calcu.patch
new file mode 100644
index 00000000..241017f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4688-drm-amd-display-fix-dml20-min_dst_y_next_start-calcu.patch
@@ -0,0 +1,32 @@
+From 3203b77954977f6e42bd469ce6cf8bfaaa3d07d1 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 8 Nov 2019 16:20:36 -0500
+Subject: [PATCH 4688/4736] drm/amd/display: fix dml20 min_dst_y_next_start
+ calculation
+
+Bring this calculation in line with HW programming guide.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+index 2c7455e22a65..9df24ececcec 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+@@ -929,8 +929,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
+ min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
+ dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
+
+- disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
+- + min_dst_y_ttu_vblank) * dml_pow(2, 2));
++ disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2));
+ ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
+
+ dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n",
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch
new file mode 100644
index 00000000..1d5fcbee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch
@@ -0,0 +1,56 @@
+From fc58a25e03e6f56115fda22aab113533d1932c93 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Mon, 11 Nov 2019 18:03:59 -0500
+Subject: [PATCH 4689/4736] drm/amd/display: Reset steer fifo before unblanking
+ the stream
+
+[why]
+During mode transition steer fifo could overflow. Quite often it
+recovers by itself, but sometimes it doesn't.
+
+[how]
+Add steer fifo reset before unblanking the stream. Also add a short
+delay when resetting dig resync fifo to make sure register writes
+don't end up back-to-back, in which case the HW might miss the reset
+request.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 3549c81b20b7..99f33c7ae528 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -486,15 +486,23 @@ void enc2_stream_encoder_dp_unblank(
+ DP_VID_N_MUL, n_multiply);
+ }
+
+- /* set DIG_START to 0x1 to reset FIFO */
++ /* make sure stream is disabled before resetting steer fifo */
++ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
++ REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
+
++ /* set DIG_START to 0x1 to reset FIFO */
+ REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
++ udelay(1);
+
+ /* write 0 to take the FIFO out of reset */
+
+ REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
+
+- /* switch DP encoder to CRTC data */
++ /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
++ * that it overflows during mode transition, and sometimes doesn't recover.
++ */
++ REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
++ udelay(10);
+
+ REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4690-drm-amd-display-Implement-DePQ-for-DCN1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4690-drm-amd-display-Implement-DePQ-for-DCN1.patch
new file mode 100644
index 00000000..7a67aef7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4690-drm-amd-display-Implement-DePQ-for-DCN1.patch
@@ -0,0 +1,120 @@
+From 64560f50a8b042c94320253268f0611beee3ead8 Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Thu, 7 Nov 2019 10:10:45 -0500
+Subject: [PATCH 4690/4736] drm/amd/display: Implement DePQ for DCN1
+
+[Why]
+Need support for more color management in 10bit
+surface.
+
+[How]
+Provide support for DePQ for 10bit surface
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 3 ++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +++
+ .../amd/display/modules/color/color_gamma.c | 39 ++++++++++++++-----
+ 3 files changed, 38 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index 6b7593dd0c77..935c892622a0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -628,6 +628,9 @@ void dpp1_set_degamma(
+ case IPP_DEGAMMA_MODE_HW_xvYCC:
+ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
+ break;
++ case IPP_DEGAMMA_MODE_USER_PWL:
++ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
++ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 24bebec84316..0e1e3dcf4112 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1467,6 +1467,11 @@ bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
+ break;
+ case TRANSFER_FUNCTION_PQ:
++ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
++ cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
++ dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
++ result = true;
++ break;
+ default:
+ result = false;
+ break;
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 3f467c98b02f..3ab6cb3a09d6 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -151,6 +151,7 @@ static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
+
+ struct fixed31_32 l_pow_m1;
+ struct fixed31_32 base, div;
++ struct fixed31_32 base2;
+
+
+ if (dc_fixpt_lt(in_x, dc_fixpt_zero))
+@@ -160,13 +161,15 @@ static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
+ dc_fixpt_div(dc_fixpt_one, m2));
+ base = dc_fixpt_sub(l_pow_m1, c1);
+
+- if (dc_fixpt_lt(base, dc_fixpt_zero))
+- base = dc_fixpt_zero;
+-
+ div = dc_fixpt_sub(c2, dc_fixpt_mul(c3, l_pow_m1));
+
+- *out_y = dc_fixpt_pow(dc_fixpt_div(base, div),
+- dc_fixpt_div(dc_fixpt_one, m1));
++ base2 = dc_fixpt_div(base, div);
++ //avoid complex numbers
++ if (dc_fixpt_lt(base2, dc_fixpt_zero))
++ base2 = dc_fixpt_sub(dc_fixpt_zero, base2);
++
++
++ *out_y = dc_fixpt_pow(base2, dc_fixpt_div(dc_fixpt_one, m1));
+
+ }
+
+@@ -1995,10 +1998,28 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
+ tf_pts->x_point_at_y1_green = 1;
+ tf_pts->x_point_at_y1_blue = 1;
+
+- map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
+- coordinates_x, axis_x, curve,
+- MAX_HW_POINTS, tf_pts,
+- mapUserRamp && ramp && ramp->type == GAMMA_RGB_256);
++ if (input_tf->tf == TRANSFER_FUNCTION_PQ) {
++ /* just copy current rgb_regamma into tf_pts */
++ struct pwl_float_data_ex *curvePt = curve;
++ int i = 0;
++
++ while (i <= MAX_HW_POINTS) {
++ tf_pts->red[i] = curvePt->r;
++ tf_pts->green[i] = curvePt->g;
++ tf_pts->blue[i] = curvePt->b;
++ ++curvePt;
++ ++i;
++ }
++ } else {
++ //clamps to 0-1
++ map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
++ coordinates_x, axis_x, curve,
++ MAX_HW_POINTS, tf_pts,
++ mapUserRamp && ramp && ramp->type == GAMMA_RGB_256);
++ }
++
++
++
+ if (ramp->type == GAMMA_CUSTOM)
+ apply_lut_1d(ramp, MAX_HW_POINTS, tf_pts);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4691-drm-amd-display-update-p-state-latency-for-renoir-wh.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4691-drm-amd-display-update-p-state-latency-for-renoir-wh.patch
new file mode 100644
index 00000000..dd1a4f16
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4691-drm-amd-display-update-p-state-latency-for-renoir-wh.patch
@@ -0,0 +1,63 @@
+From 8968f964b88aa9e59aa07885e016a8c4acf9216f Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Tue, 12 Nov 2019 15:36:57 -0500
+Subject: [PATCH 4691/4736] drm/amd/display: update p-state latency for renoir
+ when using lpddr4
+
+[Why]
+DF team has produced more optimized latency numbers, for lpddr4
+
+[How]
+change the p-state laency in the lpddr4 wm table to the new latency
+number
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 307c8540e36f..901e7035bf8e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -562,7 +562,7 @@ struct wm_table lpddr4_wm_table = {
+ {
+ .wm_inst = WM_A,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 12.5,
+ .sr_enter_plus_exit_time_us = 17.0,
+ .valid = true,
+@@ -570,7 +570,7 @@ struct wm_table lpddr4_wm_table = {
+ {
+ .wm_inst = WM_B,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 12.5,
+ .sr_enter_plus_exit_time_us = 17.0,
+ .valid = true,
+@@ -578,7 +578,7 @@ struct wm_table lpddr4_wm_table = {
+ {
+ .wm_inst = WM_C,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 12.5,
+ .sr_enter_plus_exit_time_us = 17.0,
+ .valid = true,
+@@ -586,7 +586,7 @@ struct wm_table lpddr4_wm_table = {
+ {
+ .wm_inst = WM_D,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+- .pstate_latency_us = 23.84,
++ .pstate_latency_us = 11.65333,
+ .sr_exit_time_us = 12.5,
+ .sr_enter_plus_exit_time_us = 17.0,
+ .valid = true,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4692-drm-amd-display-add-DP-protocol-version.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4692-drm-amd-display-add-DP-protocol-version.patch
new file mode 100644
index 00000000..e75d2606
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4692-drm-amd-display-add-DP-protocol-version.patch
@@ -0,0 +1,61 @@
+From fe8a3a4343e0503c30cb22f11ebd949daab072b2 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Wed, 13 Nov 2019 14:04:56 -0500
+Subject: [PATCH 4692/4736] drm/amd/display: add DP protocol version
+
+[Why]
+We want to know DP protocol version
+
+[How]
+In DC create we initialize a cap to indicate the max
+DP protocol version supported
+
+Change-Id: I9a5a356fa1ec008037ce3c27fc2872da83855f1f
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
+ drivers/gpu/drm/amd/display/dc/dc.h | 5 +++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 1e4919687ece..97da6384348a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -820,6 +820,8 @@ struct dc *dc_create(const struct dc_init_data *init_params)
+ dc->caps.max_audios = dc->res_pool->audio_count;
+ dc->caps.linear_pitch_alignment = 64;
+
++ dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
++
+ /* Populate versioning information */
+ dc->versions.dc_ver = DC_VER;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index df833b6937a1..f4884548e77e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -54,6 +54,10 @@ struct dc_versions {
+ struct dmcu_version dmcu_version;
+ };
+
++enum dp_protocol_version {
++ DP_VERSION_1_4,
++};
++
+ enum dc_plane_type {
+ DC_PLANE_TYPE_INVALID,
+ DC_PLANE_TYPE_DCE_RGB,
+@@ -114,6 +118,7 @@ struct dc_caps {
+ bool extended_aux_timeout_support;
+ bool dmcub_support;
+ bool hw_3d_lut;
++ enum dp_protocol_version max_dp_protocol_version;
+ struct dc_plane_cap planes[MAX_PLANES];
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4693-drm-amd-display-Save-restore-link-setting-for-disabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4693-drm-amd-display-Save-restore-link-setting-for-disabl.patch
new file mode 100644
index 00000000..c1ff8623
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4693-drm-amd-display-Save-restore-link-setting-for-disabl.patch
@@ -0,0 +1,50 @@
+From 427f0e33f6917ce94cf794568d357bbe66bf4d7f Mon Sep 17 00:00:00 2001
+From: Hugo Hu <hugo.hu@amd.com>
+Date: Wed, 13 Nov 2019 16:18:09 -0500
+Subject: [PATCH 4693/4736] drm/amd/display: Save/restore link setting for
+ disable phy when link retraining
+
+[Why]
+The link setting will be modify after disable phy
+and due to DP Compliance Fails.
+
+[How]
+Save and resotre link setting for disable link phy when link retraining.
+
+Signed-off-by: Hugo Hu <hugo.hu@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 486c14e0cd41..015fa0c52746 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2788,9 +2788,9 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
+ union device_service_irq device_service_clear = { { 0 } };
+ enum dc_status result;
+-
+ bool status = false;
+ struct pipe_ctx *pipe_ctx;
++ struct dc_link_settings previous_link_settings;
+ int i;
+
+ if (out_link_loss)
+@@ -2873,9 +2873,10 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
+ return false;
+
++ previous_link_settings = link->cur_link_settings;
+ dp_disable_link_phy(link, pipe_ctx->stream->signal);
+
+- perform_link_training_with_retries(&link->cur_link_settings,
++ perform_link_training_with_retries(&previous_link_settings,
+ true, LINK_TRAINING_ATTEMPTS,
+ pipe_ctx,
+ pipe_ctx->stream->signal);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4694-drm-amd-display-Return-a-correct-error-value.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4694-drm-amd-display-Return-a-correct-error-value.patch
new file mode 100644
index 00000000..e024377a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4694-drm-amd-display-Return-a-correct-error-value.patch
@@ -0,0 +1,47 @@
+From 1fecf0d6ffc9c8935672cacb6f2ccbdbbea1afaa Mon Sep 17 00:00:00 2001
+From: Mikita Lipski <mikita.lipski@amd.com>
+Date: Tue, 12 Nov 2019 13:58:32 -0500
+Subject: [PATCH 4694/4736] drm/amd/display: Return a correct error value
+
+[why]
+The function is expected to return instance of the timing generator
+therefore we shouldn't be returning boolean in integer function,
+and we shouldn't be returning zero so changing it to -1.
+
+Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
+Reviewed-by: Martin Leung <Martin.Leung@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index fd9358c11222..d4273527a371 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1870,7 +1870,7 @@ static int acquire_resource_from_hw_enabled_state(
+ inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+
+ if (inst == ENGINE_ID_UNKNOWN)
+- return false;
++ return -1;
+
+ for (i = 0; i < pool->stream_enc_count; i++) {
+ if (pool->stream_enc[i]->id == inst) {
+@@ -1882,10 +1882,10 @@ static int acquire_resource_from_hw_enabled_state(
+
+ // tg_inst not found
+ if (i == pool->stream_enc_count)
+- return false;
++ return -1;
+
+ if (tg_inst >= pool->timing_generator_count)
+- return false;
++ return -1;
+
+ if (!res_ctx->pipe_ctx[tg_inst].stream) {
+ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch
new file mode 100644
index 00000000..6919ae0e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch
@@ -0,0 +1,286 @@
+From 71f9dce3ab7c375280dbc36c00eb1787083b71ec Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 12 Nov 2019 15:33:37 -0500
+Subject: [PATCH 4695/4736] drm/amd/display: Split DMUB cmd type into
+ type/subtype
+
+[Why]
+Commands will be considered a stable ABI between driver and firmware.
+
+Commands are also split between DC commands, DAL feature commands,
+and VBIOS commands.
+
+Commands are currently not designated to a specific ID and the enum
+does not provide a stable ABI.
+
+We currently group all of these into a single command type of 8-bits.
+With the stable ABI consideration in mind it's not unreasonable to
+run out of command IDs.
+
+For cleaner separation and versioning split the commands into a main
+type and a subtype.
+
+[How]
+For commands where performance matters (like reg sequences) these
+are still considered main commands.
+
+Sub commands will be split by ownership/feature.
+
+Update existing command sequences to reflect new changes.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/bios/command_table2.c | 13 +++--
+ drivers/gpu/drm/amd/display/dc/dc_helper.c | 3 ++
+ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 48 +++++++------------
+ .../drm/amd/display/dmub/inc/dmub_cmd_dal.h | 41 ++++++++++++++++
+ .../drm/amd/display/dmub/inc/dmub_cmd_vbios.h | 41 ++++++++++++++++
+ 5 files changed, 112 insertions(+), 34 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+index 1836f16bb7fe..2cb7a4288cb7 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+@@ -111,7 +111,8 @@ static void encoder_control_dmcub(
+ {
+ struct dmub_rb_cmd_digx_encoder_control encoder_control = { 0 };
+
+- encoder_control.header.type = DMUB_CMD__DIGX_ENCODER_CONTROL;
++ encoder_control.header.type = DMUB_CMD__VBIOS;
++ encoder_control.header.sub_type = DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL;
+ encoder_control.encoder_control.dig.stream_param = *dig;
+
+ dc_dmub_srv_cmd_queue(dmcub, &encoder_control.header);
+@@ -219,7 +220,9 @@ static void transmitter_control_dmcub(
+ {
+ struct dmub_rb_cmd_dig1_transmitter_control transmitter_control;
+
+- transmitter_control.header.type = DMUB_CMD__DIG1_TRANSMITTER_CONTROL;
++ transmitter_control.header.type = DMUB_CMD__VBIOS;
++ transmitter_control.header.sub_type =
++ DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL;
+ transmitter_control.transmitter_control.dig = *dig;
+
+ dc_dmub_srv_cmd_queue(dmcub, &transmitter_control.header);
+@@ -302,7 +305,8 @@ static void set_pixel_clock_dmcub(
+ {
+ struct dmub_rb_cmd_set_pixel_clock pixel_clock = { 0 };
+
+- pixel_clock.header.type = DMUB_CMD__SET_PIXEL_CLOCK;
++ pixel_clock.header.type = DMUB_CMD__VBIOS;
++ pixel_clock.header.sub_type = DMUB_CMD__VBIOS_SET_PIXEL_CLOCK;
+ pixel_clock.pixel_clock.clk = *clk;
+
+ dc_dmub_srv_cmd_queue(dmcub, &pixel_clock.header);
+@@ -650,7 +654,8 @@ static void enable_disp_power_gating_dmcub(
+ {
+ struct dmub_rb_cmd_enable_disp_power_gating power_gating;
+
+- power_gating.header.type = DMUB_CMD__ENABLE_DISP_POWER_GATING;
++ power_gating.header.type = DMUB_CMD__VBIOS;
++ power_gating.header.sub_type = DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING;
+ power_gating.power_gating.pwr = *pwr;
+
+ dc_dmub_srv_cmd_queue(dmcub, &power_gating.header);
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index acdedd889716..5f59aeeac231 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -175,6 +175,7 @@ static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t
+ }
+
+ cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE;
++ cmd_buf->header.sub_type = 0;
+ cmd_buf->addr = addr;
+ cmd_buf->write_values[offload->reg_seq_count] = reg_val;
+ offload->reg_seq_count++;
+@@ -203,6 +204,7 @@ static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,
+
+ /* pack commands */
+ cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
++ cmd_buf->header.sub_type = 0;
+ seq = &cmd_buf->seq[offload->reg_seq_count];
+
+ if (offload->reg_seq_count) {
+@@ -227,6 +229,7 @@ static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
+ struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
+
+ cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT;
++ cmd_buf->header.sub_type = 0;
+ cmd_buf->reg_wait.addr = addr;
+ cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);
+ cmd_buf->reg_wait.mask = mask;
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+index 43f1cd647aab..b10728f33f62 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+@@ -27,6 +27,8 @@
+ #define _DMUB_CMD_H_
+
+ #include "dmub_types.h"
++#include "dmub_cmd_dal.h"
++#include "dmub_cmd_vbios.h"
+ #include "atomfirmware.h"
+
+ #define DMUB_RB_CMD_SIZE 64
+@@ -34,43 +36,29 @@
+ #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
+ #define REG_SET_MASK 0xFFFF
+
++/*
++ * Command IDs should be treated as stable ABI.
++ * Do not reuse or modify IDs.
++ */
++
+ enum dmub_cmd_type {
+- DMUB_CMD__NULL,
+- DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE,
+- DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ,
+- DMUB_CMD__REG_SEQ_BURST_WRITE,
+- DMUB_CMD__REG_REG_WAIT,
+- DMUB_CMD__DIGX_ENCODER_CONTROL,
+- DMUB_CMD__SET_PIXEL_CLOCK,
+- DMUB_CMD__ENABLE_DISP_POWER_GATING,
+- DMUB_CMD__DPPHY_INIT,
+- DMUB_CMD__DIG1_TRANSMITTER_CONTROL,
+- DMUB_CMD__SETUP_DISPLAY_MODE,
+- DMUB_CMD__BLANK_CRTC,
+- DMUB_CMD__ENABLE_DISPPATH,
+- DMUB_CMD__DISABLE_DISPPATH,
+- DMUB_CMD__DISABLE_DISPPATH_OUTPUT,
+- DMUB_CMD__READ_DISPPATH_EDID,
+- DMUB_CMD__DP_PRE_LINKTRAINING,
+- DMUB_CMD__INIT_CONTROLLER,
+- DMUB_CMD__RESET_CONTROLLER,
+- DMUB_CMD__SET_BRI_LEVEL,
+- DMUB_CMD__LVTMA_CONTROL,
+-
+- // PSR
+- DMUB_CMD__PSR_ENABLE,
+- DMUB_CMD__PSR_DISABLE,
+- DMUB_CMD__PSR_COPY_SETTINGS,
+- DMUB_CMD__PSR_SET_LEVEL,
++ DMUB_CMD__NULL = 0,
++ DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
++ DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
++ DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
++ DMUB_CMD__REG_REG_WAIT = 4,
++ DMUB_CMD__PSR = 64,
++ DMUB_CMD__VBIOS = 128,
+ };
+
+ #pragma pack(push, 1)
+
+ struct dmub_cmd_header {
+- enum dmub_cmd_type type : 8;
+- unsigned int reserved0 : 16;
++ unsigned int type : 8;
++ unsigned int sub_type : 8;
++ unsigned int reserved0 : 8;
+ unsigned int payload_bytes : 6; /* up to 60 bytes */
+- unsigned int reserved : 2;
++ unsigned int reserved1 : 2;
+ };
+
+ /*
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
+new file mode 100644
+index 000000000000..14f13e8a6f3b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_CMD_DAL_H_
++#define _DMUB_CMD_DAL_H_
++
++/*
++ * Command IDs should be treated as stable ABI.
++ * Do not reuse or modify IDs.
++ */
++
++enum dmub_cmd_psr_type {
++ DMUB_CMD__PSR_ENABLE = 0,
++ DMUB_CMD__PSR_DISABLE = 1,
++ DMUB_CMD__PSR_COPY_SETTINGS = 2,
++ DMUB_CMD__PSR_SET_LEVEL = 3,
++};
++
++#endif /* _DMUB_CMD_DAL_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h
+new file mode 100644
+index 000000000000..b6deb8e2590f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_CMD_VBIOS_H_
++#define _DMUB_CMD_VBIOS_H_
++
++/*
++ * Command IDs should be treated as stable ABI.
++ * Do not reuse or modify IDs.
++ */
++
++enum dmub_cmd_vbios_type {
++ DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
++ DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
++ DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
++ DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
++};
++
++#endif /* _DMUB_CMD_VBIOS_H_ */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4696-drm-amd-display-Add-shared-DMCUB-driver-firmware-sta.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4696-drm-amd-display-Add-shared-DMCUB-driver-firmware-sta.patch
new file mode 100644
index 00000000..358f5acc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4696-drm-amd-display-Add-shared-DMCUB-driver-firmware-sta.patch
@@ -0,0 +1,333 @@
+From 740f33a5fe33c62249db788bd90ce46dcbe72499 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 12 Nov 2019 13:46:34 -0500
+Subject: [PATCH 4696/4736] drm/amd/display: Add shared DMCUB/driver firmware
+ state cache window
+
+[Why]
+Scratch registers are limited on the DMCUB and we have an expanding
+list of state to track between driver and DMCUB.
+
+[How]
+Place shared state in cache window 6. The cache window size is aligned
+to the size of the cache line on the DMCUB to make it easy to
+invalidate.
+
+The shared state is intended to be read only from driver side so
+it's been marked as const.
+
+The use of volatile is intentional. The memory for the shared firmware
+state is memory mapped from the framebuffer memory. The DMCUB will
+flush its cache after modifying the region. There's no way for x86
+to known whether this data is stale or not so we want to intentionally
+disable optimization to force the read at every access.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dmub/inc/dmub_fw_state.h | 73 +++++++++++++++++++
+ .../gpu/drm/amd/display/dmub/inc/dmub_srv.h | 8 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 10 ++-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 3 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 12 ++-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 3 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 27 +++++--
+ 7 files changed, 125 insertions(+), 11 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+new file mode 100644
+index 000000000000..c87b1ba7590e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+@@ -0,0 +1,73 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_FW_STATE_H_
++#define _DMUB_FW_STATE_H_
++
++#include "dmub_types.h"
++
++#pragma pack(push, 1)
++
++struct dmub_fw_state {
++ /**
++ * @phy_initialized_during_fw_boot:
++ *
++ * Detects if VBIOS/VBL has ran before firmware boot.
++ * A value of 1 will usually mean S0i3 boot.
++ */
++ uint8_t phy_initialized_during_fw_boot;
++
++ /**
++ * @intialized_phy:
++ *
++ * Bit vector of initialized PHY.
++ */
++ uint8_t initialized_phy;
++
++ /**
++ * @enabled_phy:
++ *
++ * Bit vector of enabled PHY for DP alt mode switch tracking.
++ */
++ uint8_t enabled_phy;
++
++ /**
++ * @dmcu_fw_loaded:
++ *
++ * DMCU auto load state.
++ */
++ uint8_t dmcu_fw_loaded;
++
++ /**
++ * @psr_state:
++ *
++ * PSR state tracking.
++ */
++ uint8_t psr_state;
++};
++
++#pragma pack(pop)
++
++#endif /* _DMUB_FW_STATE_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+index 046885940dba..d678b6f0313f 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -67,6 +67,7 @@
+ #include "dmub_types.h"
+ #include "dmub_cmd.h"
+ #include "dmub_rb.h"
++#include "dmub_fw_state.h"
+
+ #if defined(__cplusplus)
+ extern "C" {
+@@ -102,7 +103,7 @@ enum dmub_window_id {
+ DMUB_WINDOW_3_VBIOS,
+ DMUB_WINDOW_4_MAILBOX,
+ DMUB_WINDOW_5_TRACEBUFF,
+- DMUB_WINDOW_6_RESERVED,
++ DMUB_WINDOW_6_FW_STATE,
+ DMUB_WINDOW_7_RESERVED,
+ DMUB_WINDOW_TOTAL,
+ };
+@@ -241,7 +242,8 @@ struct dmub_srv_hw_funcs {
+ const struct dmub_window *cw2,
+ const struct dmub_window *cw3,
+ const struct dmub_window *cw4,
+- const struct dmub_window *cw5);
++ const struct dmub_window *cw5,
++ const struct dmub_window *cw6);
+
+ void (*setup_mailbox)(struct dmub_srv *dmub,
+ const struct dmub_region *inbox1);
+@@ -296,11 +298,13 @@ struct dmub_srv_hw_params {
+ * @asic: dmub asic identifier
+ * @user_ctx: user provided context for the dmub_srv
+ * @is_virtual: false if hardware support only
++ * @fw_state: dmub firmware state pointer
+ */
+ struct dmub_srv {
+ enum dmub_asic asic;
+ void *user_ctx;
+ bool is_virtual;
++ volatile const struct dmub_fw_state *fw_state;
+
+ /* private: internal use only */
+ struct dmub_srv_base_funcs funcs;
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 302dd3d4b77d..951ea7053c7e 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -76,7 +76,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ const struct dmub_window *cw2,
+ const struct dmub_window *cw3,
+ const struct dmub_window *cw4,
+- const struct dmub_window *cw5)
++ const struct dmub_window *cw5,
++ const struct dmub_window *cw6)
+ {
+ REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part);
+@@ -106,6 +107,13 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+ DMCUB_REGION3_CW5_ENABLE, 1);
++
++ REG_WRITE(DMCUB_REGION3_CW6_OFFSET, cw6->offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, cw6->offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
++ REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
++ DMCUB_REGION3_CW6_ENABLE, 1);
+ }
+
+ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+index ca7db03b94f7..e70a57573467 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -46,7 +46,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ const struct dmub_window *cw2,
+ const struct dmub_window *cw3,
+ const struct dmub_window *cw4,
+- const struct dmub_window *cw5);
++ const struct dmub_window *cw5,
++ const struct dmub_window *cw6);
+
+ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
+ const struct dmub_region *inbox1);
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+index b9dc2dd645eb..9cea7a2d8dbf 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+@@ -78,7 +78,8 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+ const struct dmub_window *cw2,
+ const struct dmub_window *cw3,
+ const struct dmub_window *cw4,
+- const struct dmub_window *cw5)
++ const struct dmub_window *cw5,
++ const struct dmub_window *cw6)
+ {
+ union dmub_addr offset;
+ uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+@@ -118,6 +119,15 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+ REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+ DMCUB_REGION3_CW5_ENABLE, 1);
++
++ dmub_dcn21_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
++
++ REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
++ REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
++ REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
++ REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
++ DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
++ DMCUB_REGION3_CW6_ENABLE, 1);
+ }
+
+ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+index 9e5f195e288f..f7a93a5dcfa5 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+@@ -38,7 +38,8 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+ const struct dmub_window *cw2,
+ const struct dmub_window *cw3,
+ const struct dmub_window *cw4,
+- const struct dmub_window *cw5);
++ const struct dmub_window *cw5,
++ const struct dmub_window *cw6);
+
+ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 70c7a4be9ccc..5f39166d3c08 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -48,13 +48,14 @@
+
+
+ /* Number of windows in use. */
+-#define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1)
++#define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1)
+ /* Base addresses. */
+
+ #define DMUB_CW0_BASE (0x60000000)
+ #define DMUB_CW1_BASE (0x61000000)
+ #define DMUB_CW3_BASE (0x63000000)
+ #define DMUB_CW5_BASE (0x65000000)
++#define DMUB_CW6_BASE (0x66000000)
+
+ static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
+ {
+@@ -158,6 +159,7 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
+ struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
+ struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
+ struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
++ struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
+
+ if (!dmub->sw_init)
+ return DMUB_STATUS_INVALID;
+@@ -184,7 +186,13 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
+ trace_buff->base = dmub_align(mail->top, 256);
+ trace_buff->top = trace_buff->base + TRACE_BUF_SIZE;
+
+- out->fb_size = dmub_align(trace_buff->top, 4096);
++ fw_state->base = dmub_align(trace_buff->top, 256);
++
++ /* Align firmware state to size of cache line. */
++ fw_state->top =
++ fw_state->base + dmub_align(sizeof(struct dmub_fw_state), 64);
++
++ out->fb_size = dmub_align(fw_state->top, 4096);
+
+ return DMUB_STATUS_OK;
+ }
+@@ -258,9 +266,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
+ struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
+ struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
++ struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
+
+ struct dmub_rb_init_params rb_params;
+- struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5;
++ struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
+ struct dmub_region inbox1;
+
+ if (!dmub->sw_init)
+@@ -286,7 +295,8 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ if (dmub->hw_funcs.reset)
+ dmub->hw_funcs.reset(dmub);
+
+- if (inst_fb && data_fb && bios_fb && mail_fb) {
++ if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb &&
++ fw_state_fb) {
+ cw2.offset.quad_part = data_fb->gpu_addr;
+ cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
+ cw2.region.top = cw2.region.base + data_fb->size;
+@@ -306,8 +316,15 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ cw5.region.base = DMUB_CW5_BASE;
+ cw5.region.top = cw5.region.base + tracebuff_fb->size;
+
++ cw6.offset.quad_part = fw_state_fb->gpu_addr;
++ cw6.region.base = DMUB_CW6_BASE;
++ cw6.region.top = cw6.region.base + fw_state_fb->size;
++
++ dmub->fw_state = fw_state_fb->cpu_addr;
++
+ if (dmub->hw_funcs.setup_windows)
+- dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5);
++ dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4,
++ &cw5, &cw6);
+
+ if (dmub->hw_funcs.setup_mailbox)
+ dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch
new file mode 100644
index 00000000..6f15b44f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch
@@ -0,0 +1,68 @@
+From ef14a8387788a849b24a54f954dbc14a807f10d4 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Tue, 12 Nov 2019 17:48:36 -0500
+Subject: [PATCH 4697/4736] drm/amd/display: update sr latency for renoir when
+ using lpddr4
+
+[Why]
+DF team has produced more optimized sr latency numbers, for lpddr4
+
+[How]
+change the sr laency in the lpddr4 wm table to the new latency
+number
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 901e7035bf8e..37230d3d94a0 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -563,32 +563,32 @@ struct wm_table lpddr4_wm_table = {
+ .wm_inst = WM_A,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+- .sr_exit_time_us = 12.5,
+- .sr_enter_plus_exit_time_us = 17.0,
++ .sr_exit_time_us = 5.32,
++ .sr_enter_plus_exit_time_us = 6.38,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_B,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+- .sr_exit_time_us = 12.5,
+- .sr_enter_plus_exit_time_us = 17.0,
++ .sr_exit_time_us = 9.82,
++ .sr_enter_plus_exit_time_us = 11.196,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_C,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+- .sr_exit_time_us = 12.5,
+- .sr_enter_plus_exit_time_us = 17.0,
++ .sr_exit_time_us = 9.89,
++ .sr_enter_plus_exit_time_us = 11.24,
+ .valid = true,
+ },
+ {
+ .wm_inst = WM_D,
+ .wm_type = WM_TYPE_PSTATE_CHG,
+ .pstate_latency_us = 11.65333,
+- .sr_exit_time_us = 12.5,
+- .sr_enter_plus_exit_time_us = 17.0,
++ .sr_exit_time_us = 9.748,
++ .sr_enter_plus_exit_time_us = 11.102,
+ .valid = true,
+ },
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4698-drm-amd-display-Remove-flag-check-in-mpcc-update.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4698-drm-amd-display-Remove-flag-check-in-mpcc-update.patch
new file mode 100644
index 00000000..4683a59d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4698-drm-amd-display-Remove-flag-check-in-mpcc-update.patch
@@ -0,0 +1,43 @@
+From 231d52771b240b2224e4f1c2198f7870dfc4844e Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Wed, 13 Nov 2019 13:55:53 -0500
+Subject: [PATCH 4698/4736] drm/amd/display: Remove flag check in mpcc update
+
+[Why]
+MPCC programming was being missed during certain split pipe enables due
+to full_update flag not being true. This caused a momentary flash on
+half the screen. After discussion, determined we should not have that
+flag check within update_mpcc, as it should always perform full
+programming when called.
+
+[How]
+Remove flag check. We call update_blending within insert_plane, so we
+do not need to replace its call from the if block.
+
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 3e016a57f1ac..53b719c75071 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -2162,12 +2162,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ */
+ mpcc_id = hubp->inst;
+
+- /* If there is no full update, don't need to touch MPC tree*/
+- if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
+- mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
+- return;
+- }
+-
+ /* check if this MPCC is already being used */
+ new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
+ /* remove MPCC if being used */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4699-drm-amd-display-check-for-repeater-when-setting-aux_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4699-drm-amd-display-check-for-repeater-when-setting-aux_.patch
new file mode 100644
index 00000000..911c1ae4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4699-drm-amd-display-check-for-repeater-when-setting-aux_.patch
@@ -0,0 +1,43 @@
+From 7f899298da256db5ad49f3183e4a771eddc75344 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Tue, 12 Nov 2019 11:07:24 -0500
+Subject: [PATCH 4699/4736] drm/amd/display: check for repeater when setting
+ aux_rd_interval.
+
+[Why]
+When training with repeater the aux read interval must be set to
+repeater specific aux_red_interval. This value is always 100us for CR.
+
+[How]
+Check for repeater when setting the aux_rd_interval in channel
+equalization.
+Use the right offset in the aux_rd_interval array
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: George Shen <George.Shen@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 015fa0c52746..dfcd6421ee01 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -906,10 +906,10 @@ static enum link_training_result perform_channel_equalization_sequence(
+ /* 3. wait for receiver to lock-on*/
+ wait_time_microsec = lt_settings->eq_pattern_time;
+
+- if (!link->is_lttpr_mode_transparent)
++ if (is_repeater(link, offset))
+ wait_time_microsec =
+ translate_training_aux_read_interval(
+- link->dpcd_caps.lttpr_caps.aux_rd_interval[offset]);
++ link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
+
+ wait_for_training_aux_rd_interval(
+ link,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4700-drm-amd-display-Modify-logic-for-when-to-wait-for-mp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4700-drm-amd-display-Modify-logic-for-when-to-wait-for-mp.patch
new file mode 100644
index 00000000..7e61a4b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4700-drm-amd-display-Modify-logic-for-when-to-wait-for-mp.patch
@@ -0,0 +1,54 @@
+From 1cfb31a1c8f703da4269ad762e6c42961149f361 Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Wed, 13 Nov 2019 16:56:06 -0500
+Subject: [PATCH 4700/4736] drm/amd/display: Modify logic for when to wait for
+ mpcc idle
+
+[Why]
+I was advised that we may need to check for mpcc idle in more cases
+than just when opp_changed is true. Also, mpcc_inst is equal to
+pipe_idx, so remove for loop.
+
+[How]
+Remove opp_changed flag check and mpcc_inst loop.
+
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 53b719c75071..036a43717a47 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1353,16 +1353,16 @@ static void dcn20_update_dchubp_dpp(
+ if (pipe_ctx->update_flags.bits.mpcc
+ || plane_state->update_flags.bits.global_alpha_change
+ || plane_state->update_flags.bits.per_pixel_alpha_change) {
+- /* Need mpcc to be idle if changing opp */
+- if (pipe_ctx->update_flags.bits.opp_changed) {
+- struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
+- int mpcc_inst;
+-
+- for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
+- if (!old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst])
+- continue;
++ // MPCC inst is equal to pipe index in practice
++ int mpcc_inst = pipe_ctx->pipe_idx;
++ int opp_inst;
++ int opp_count = dc->res_pool->res_cap->num_opp;
++
++ for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
++ if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
+ dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
+- old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
++ dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
++ break;
+ }
+ }
+ hws->funcs.update_mpcc(dc, pipe_ctx);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4701-drm-amd-display-Remove-redundant-call.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4701-drm-amd-display-Remove-redundant-call.patch
new file mode 100644
index 00000000..d4239504
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4701-drm-amd-display-Remove-redundant-call.patch
@@ -0,0 +1,38 @@
+From b16e3871c5e322e23ec7ef4a669eea2ed83acb4d Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Wed, 13 Nov 2019 17:06:40 -0500
+Subject: [PATCH 4701/4736] drm/amd/display: Remove redundant call
+
+[Why]
+I was advised that we don't need this call of program_front_end, as
+earlier and later calls in the same sequence are sufficient.
+
+[How]
+Remove first call of program_front_end in dc_commit_state_no_check.
+
+Change-Id: I4a552fdd06c05a4c0ffa243c59f99b45c06a1fdd
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 97da6384348a..0c75ee6bbdf2 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1178,10 +1178,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ context->stream_status[i].plane_count,
+ context); /* use new pipe config in new context */
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+- if (dc->hwss.program_front_end_for_ctx)
+- dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+
+ /* Program hardware */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4702-drm-amd-display-add-dc-dsc-functions-to-return-bpp-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4702-drm-amd-display-add-dc-dsc-functions-to-return-bpp-r.patch
new file mode 100644
index 00000000..79ccc215
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4702-drm-amd-display-add-dc-dsc-functions-to-return-bpp-r.patch
@@ -0,0 +1,135 @@
+From ac462cfeea247e416a918528d11b62e6beb60e4a Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Wed, 13 Nov 2019 17:03:37 -0500
+Subject: [PATCH 4702/4736] drm/amd/display: add dc dsc functions to return bpp
+ range for pixel encoding
+
+[why]
+Need to support 6 bpp for 420 pixel encoding only.
+
+[how]
+Add a dc function to determine what bpp range can be supported
+for given pixel encoding.
+
+Change-Id: I438dd2e234457ab28fefd249a0f9ed17ef0dbae5
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h | 8 +++--
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 40 +++++++++++++++++----
+ 2 files changed, 39 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index cc9915e545cd..d98b89bad353 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -52,8 +52,8 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+ bool dc_dsc_compute_bandwidth_range(
+ const struct display_stream_compressor *dsc,
+ const uint32_t dsc_min_slice_height_override,
+- const uint32_t min_kbps,
+- const uint32_t max_kbps,
++ const uint32_t min_bpp,
++ const uint32_t max_bpp,
+ const struct dsc_dec_dpcd_caps *dsc_sink_caps,
+ const struct dc_crtc_timing *timing,
+ struct dc_dsc_bw_range *range);
+@@ -65,4 +65,8 @@ bool dc_dsc_compute_config(
+ uint32_t target_bandwidth_kbps,
+ const struct dc_crtc_timing *timing,
+ struct dc_dsc_config *dsc_cfg);
++
++bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
++ uint32_t *min_bpp,
++ uint32_t *max_bpp);
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index ec86ba73a039..f2b724d7e372 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -31,16 +31,12 @@ struct dc_dsc_policy {
+ bool use_min_slices_h;
+ int max_slices_h; // Maximum available if 0
+ int min_sice_height; // Must not be less than 8
+- int max_target_bpp;
+- int min_target_bpp; // Minimum target bits per pixel
+ };
+
+ const struct dc_dsc_policy dsc_policy = {
+ .use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
+ .max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
+ .min_sice_height = 108, // DSC Policy: Use slice height recommended by VESA DSC Spreadsheet user guide
+- .max_target_bpp = 16,
+- .min_target_bpp = 8,
+ };
+
+
+@@ -374,7 +370,6 @@ static void get_dsc_bandwidth_range(
+ * or if it couldn't be applied based on DSC policy.
+ */
+ static bool decide_dsc_target_bpp_x16(
+- const struct dc_dsc_policy *policy,
+ const struct dsc_enc_caps *dsc_common_caps,
+ const int target_bandwidth_kbps,
+ const struct dc_crtc_timing *timing,
+@@ -382,10 +377,13 @@ static bool decide_dsc_target_bpp_x16(
+ {
+ bool should_use_dsc = false;
+ struct dc_dsc_bw_range range;
++ uint32_t min_target_bpp = 0;
++ uint32_t max_target_bpp = 0;
+
+ memset(&range, 0, sizeof(range));
+
+- get_dsc_bandwidth_range(policy->min_target_bpp, policy->max_target_bpp,
++ dc_dsc_get_bpp_range_for_pixel_encoding(timing->pixel_encoding, &min_target_bpp, &max_target_bpp);
++ get_dsc_bandwidth_range(min_target_bpp, max_target_bpp,
+ dsc_common_caps, timing, &range);
+ if (target_bandwidth_kbps >= range.stream_kbps) {
+ /* enough bandwidth without dsc */
+@@ -599,7 +597,7 @@ static bool setup_dsc_config(
+ goto done;
+
+ if (target_bandwidth_kbps > 0) {
+- is_dsc_possible = decide_dsc_target_bpp_x16(&dsc_policy, &dsc_common_caps, target_bandwidth_kbps, timing, &target_bpp);
++ is_dsc_possible = decide_dsc_target_bpp_x16(&dsc_common_caps, target_bandwidth_kbps, timing, &target_bpp);
+ dsc_cfg->bits_per_pixel = target_bpp;
+ }
+ if (!is_dsc_possible)
+@@ -906,3 +904,31 @@ bool dc_dsc_compute_config(
+ timing, dsc_min_slice_height_override, dsc_cfg);
+ return is_dsc_possible;
+ }
++
++
++bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
++ uint32_t *min_bpp,
++ uint32_t *max_bpp)
++{
++ bool result = true;
++
++ switch (pixel_enc) {
++ case PIXEL_ENCODING_RGB:
++ case PIXEL_ENCODING_YCBCR444:
++ case PIXEL_ENCODING_YCBCR422:
++ *min_bpp = 8;
++ *max_bpp = 16;
++ break;
++ case PIXEL_ENCODING_YCBCR420:
++ *min_bpp = 6;
++ *max_bpp = 16;
++ break;
++ default:
++ *min_bpp = 0;
++ *max_bpp = 0;
++ result = false;
++ }
++
++ return result;
++}
++
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4703-drm-amd-display-remove-spam-DSC-log.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4703-drm-amd-display-remove-spam-DSC-log.patch
new file mode 100644
index 00000000..15331837
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4703-drm-amd-display-remove-spam-DSC-log.patch
@@ -0,0 +1,36 @@
+From 06eba75bcead2659aa35a315723b1df23d978b2f Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Wed, 13 Nov 2019 15:59:51 -0500
+Subject: [PATCH 4703/4736] drm/amd/display: remove spam DSC log
+
+[why]
+add_dsc_to_stream_resource could be called for validation.
+Failing validation is completely fine.
+However failing it inside commit streams is bad.
+This code could be triggered for both contexts.
+The function itself cannot distinguish the caller, which
+makes it impossible to output the log only in the
+meaningful case (commit streams).
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2e03ff357746..5c00223b279e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1582,7 +1582,6 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+
+ /* The number of DSCs can be less than the number of pipes */
+ if (!pipe_ctx->stream_res.dsc) {
+- dm_output_to_console("No DSCs available\n");
+ result = DC_NO_DSC_RESOURCE;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4704-drm-amd-display-add-dsc-policy-getter.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4704-drm-amd-display-add-dsc-policy-getter.patch
new file mode 100644
index 00000000..5f335a3e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4704-drm-amd-display-add-dsc-policy-getter.patch
@@ -0,0 +1,235 @@
+From 564a7172d20f0f68566d58fd9278058ca1e93291 Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Fri, 15 Nov 2019 11:24:54 -0500
+Subject: [PATCH 4704/4736] drm/amd/display: add dsc policy getter
+
+dc needs to expose its internal dsc policy.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h | 14 ++-
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 103 ++++++++++++--------
+ 2 files changed, 75 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index d98b89bad353..8ec09813ee17 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -45,6 +45,14 @@ struct display_stream_compressor {
+ int inst;
+ };
+
++struct dc_dsc_policy {
++ bool use_min_slices_h;
++ int max_slices_h; // Maximum available if 0
++ int min_slice_height; // Must not be less than 8
++ uint32_t max_target_bpp;
++ uint32_t min_target_bpp;
++};
++
+ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+ const uint8_t *dpcd_dsc_ext_data,
+ struct dsc_dec_dpcd_caps *dsc_sink_caps);
+@@ -66,7 +74,7 @@ bool dc_dsc_compute_config(
+ const struct dc_crtc_timing *timing,
+ struct dc_dsc_config *dsc_cfg);
+
+-bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
+- uint32_t *min_bpp,
+- uint32_t *max_bpp);
++void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
++ struct dc_dsc_policy *policy);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index f2b724d7e372..7469315144c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -27,19 +27,6 @@
+ #include <drm/drm_dp_helper.h>
+ #include "dc.h"
+
+-struct dc_dsc_policy {
+- bool use_min_slices_h;
+- int max_slices_h; // Maximum available if 0
+- int min_sice_height; // Must not be less than 8
+-};
+-
+-const struct dc_dsc_policy dsc_policy = {
+- .use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
+- .max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
+- .min_sice_height = 108, // DSC Policy: Use slice height recommended by VESA DSC Spreadsheet user guide
+-};
+-
+-
+ /* This module's internal functions */
+
+ static uint32_t dc_dsc_bandwidth_in_kbps_from_timing(
+@@ -370,6 +357,7 @@ static void get_dsc_bandwidth_range(
+ * or if it couldn't be applied based on DSC policy.
+ */
+ static bool decide_dsc_target_bpp_x16(
++ const struct dc_dsc_policy *policy,
+ const struct dsc_enc_caps *dsc_common_caps,
+ const int target_bandwidth_kbps,
+ const struct dc_crtc_timing *timing,
+@@ -377,13 +365,10 @@ static bool decide_dsc_target_bpp_x16(
+ {
+ bool should_use_dsc = false;
+ struct dc_dsc_bw_range range;
+- uint32_t min_target_bpp = 0;
+- uint32_t max_target_bpp = 0;
+
+ memset(&range, 0, sizeof(range));
+
+- dc_dsc_get_bpp_range_for_pixel_encoding(timing->pixel_encoding, &min_target_bpp, &max_target_bpp);
+- get_dsc_bandwidth_range(min_target_bpp, max_target_bpp,
++ get_dsc_bandwidth_range(policy->min_target_bpp, policy->max_target_bpp,
+ dsc_common_caps, timing, &range);
+ if (target_bandwidth_kbps >= range.stream_kbps) {
+ /* enough bandwidth without dsc */
+@@ -579,9 +564,11 @@ static bool setup_dsc_config(
+ bool is_dsc_possible = false;
+ int pic_height;
+ int slice_height;
++ struct dc_dsc_policy policy;
+
+ memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
+
++ dc_dsc_get_policy_for_timing(timing, &policy);
+ pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+ pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
+
+@@ -597,7 +584,12 @@ static bool setup_dsc_config(
+ goto done;
+
+ if (target_bandwidth_kbps > 0) {
+- is_dsc_possible = decide_dsc_target_bpp_x16(&dsc_common_caps, target_bandwidth_kbps, timing, &target_bpp);
++ is_dsc_possible = decide_dsc_target_bpp_x16(
++ &policy,
++ &dsc_common_caps,
++ target_bandwidth_kbps,
++ timing,
++ &target_bpp);
+ dsc_cfg->bits_per_pixel = target_bpp;
+ }
+ if (!is_dsc_possible)
+@@ -699,20 +691,20 @@ static bool setup_dsc_config(
+ if (!is_dsc_possible)
+ goto done;
+
+- if (dsc_policy.use_min_slices_h) {
++ if (policy.use_min_slices_h) {
+ if (min_slices_h > 0)
+ num_slices_h = min_slices_h;
+ else if (max_slices_h > 0) { // Fall back to max slices if min slices is not working out
+- if (dsc_policy.max_slices_h)
+- num_slices_h = min(dsc_policy.max_slices_h, max_slices_h);
++ if (policy.max_slices_h)
++ num_slices_h = min(policy.max_slices_h, max_slices_h);
+ else
+ num_slices_h = max_slices_h;
+ } else
+ is_dsc_possible = false;
+ } else {
+ if (max_slices_h > 0) {
+- if (dsc_policy.max_slices_h)
+- num_slices_h = min(dsc_policy.max_slices_h, max_slices_h);
++ if (policy.max_slices_h)
++ num_slices_h = min(policy.max_slices_h, max_slices_h);
+ else
+ num_slices_h = max_slices_h;
+ } else if (min_slices_h > 0) // Fall back to min slices if max slices is not possible
+@@ -734,7 +726,7 @@ static bool setup_dsc_config(
+ // Slice height (i.e. number of slices per column): start with policy and pick the first one that height is divisible by.
+ // For 4:2:0 make sure the slice height is divisible by 2 as well.
+ if (min_slice_height_override == 0)
+- slice_height = min(dsc_policy.min_sice_height, pic_height);
++ slice_height = min(policy.min_slice_height, pic_height);
+ else
+ slice_height = min(min_slice_height_override, pic_height);
+
+@@ -906,29 +898,62 @@ bool dc_dsc_compute_config(
+ }
+
+
+-bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
+- uint32_t *min_bpp,
+- uint32_t *max_bpp)
++void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc_dsc_policy *policy)
+ {
+- bool result = true;
++ uint32_t bpc = 0;
++
++ policy->min_target_bpp = 0;
++ policy->max_target_bpp = 0;
++
++ /* DSC Policy: Use minimum number of slices that fits the pixel clock */
++ policy->use_min_slices_h = true;
+
+- switch (pixel_enc) {
++ /* DSC Policy: Use max available slices
++ * (in our case 4 for or 8, depending on the mode)
++ */
++ policy->max_slices_h = 0;
++
++ /* DSC Policy: Use slice height recommended
++ * by VESA DSC Spreadsheet user guide
++ */
++ policy->min_slice_height = 108;
++
++ /* DSC Policy: follow DP specs with an internal upper limit to 16 bpp
++ * for better interoperability
++ */
++ switch (timing->display_color_depth) {
++ case COLOR_DEPTH_888:
++ bpc = 8;
++ break;
++ case COLOR_DEPTH_101010:
++ bpc = 10;
++ break;
++ case COLOR_DEPTH_121212:
++ bpc = 12;
++ break;
++ default:
++ return;
++ }
++ switch (timing->pixel_encoding) {
+ case PIXEL_ENCODING_RGB:
+ case PIXEL_ENCODING_YCBCR444:
+- case PIXEL_ENCODING_YCBCR422:
+- *min_bpp = 8;
+- *max_bpp = 16;
++ case PIXEL_ENCODING_YCBCR422: /* assume no YCbCr422 native support */
++ /* DP specs limits to 8 */
++ policy->min_target_bpp = 8;
++ /* DP specs limits to 3 x bpc */
++ policy->max_target_bpp = 3 * bpc;
+ break;
+ case PIXEL_ENCODING_YCBCR420:
+- *min_bpp = 6;
+- *max_bpp = 16;
++ /* DP specs limits to 6 */
++ policy->min_target_bpp = 6;
++ /* DP specs limits to 1.5 x bpc assume bpc is an even number */
++ policy->max_target_bpp = bpc * 3 / 2;
+ break;
+ default:
+- *min_bpp = 0;
+- *max_bpp = 0;
+- result = false;
++ return;
+ }
+-
+- return result;
++ /* internal upper limit to 16 bpp */
++ if (policy->max_target_bpp > 16)
++ policy->max_target_bpp = 16;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4705-drm-amd-display-fix-cursor-positioning-for-multiplan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4705-drm-amd-display-fix-cursor-positioning-for-multiplan.patch
new file mode 100644
index 00000000..bc9d5d05
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4705-drm-amd-display-fix-cursor-positioning-for-multiplan.patch
@@ -0,0 +1,67 @@
+From 460d5ac8ad145c412be735e1593b57eaa4098b19 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sat, 9 Nov 2019 18:30:40 -0500
+Subject: [PATCH 4705/4736] drm/amd/display: fix cursor positioning for
+ multiplane cases
+
+[Why]
+Cursor position needs to take into account plane scaling as well.
+
+[How]
+Translate cursor coords from stream space to plane space.
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 33 ++++++++++++++-----
+ 1 file changed, 24 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 0e1e3dcf4112..c085a561b24c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2917,15 +2917,30 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+ .rotation = pipe_ctx->plane_state->rotation,
+ .mirror = pipe_ctx->plane_state->horizontal_mirror
+ };
+- uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
+- uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
+- uint32_t x_offset = min(x_plane, pos_cpy.x);
+- uint32_t y_offset = min(y_plane, pos_cpy.y);
+-
+- pos_cpy.x -= x_offset;
+- pos_cpy.y -= y_offset;
+- pos_cpy.x_hotspot += (x_plane - x_offset);
+- pos_cpy.y_hotspot += (y_plane - y_offset);
++
++ int x_plane = pipe_ctx->plane_state->dst_rect.x;
++ int y_plane = pipe_ctx->plane_state->dst_rect.y;
++ int x_pos = pos_cpy.x;
++ int y_pos = pos_cpy.y;
++
++ // translate cursor from stream space to plane space
++ x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
++ pipe_ctx->plane_state->dst_rect.width;
++ y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
++ pipe_ctx->plane_state->dst_rect.height;
++
++ if (x_pos < 0) {
++ pos_cpy.x_hotspot -= x_pos;
++ x_pos = 0;
++ }
++
++ if (y_pos < 0) {
++ pos_cpy.y_hotspot -= y_pos;
++ y_pos = 0;
++ }
++
++ pos_cpy.x = (uint32_t)x_pos;
++ pos_cpy.y = (uint32_t)y_pos;
+
+ if (pipe_ctx->plane_state->address.type
+ == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4706-drm-amd-display-Fix-screen-tearing-on-vrr-tests.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4706-drm-amd-display-Fix-screen-tearing-on-vrr-tests.patch
new file mode 100644
index 00000000..6cf94fae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4706-drm-amd-display-Fix-screen-tearing-on-vrr-tests.patch
@@ -0,0 +1,122 @@
+From 55df5456b6e72138acecde21cccf513b9315655d Mon Sep 17 00:00:00 2001
+From: Amanda Liu <amanda.liu@amd.com>
+Date: Fri, 15 Nov 2019 17:07:27 -0500
+Subject: [PATCH 4706/4736] drm/amd/display: Fix screen tearing on vrr tests
+
+[Why]
+Screen tearing is present in tests when setting the frame rate to
+certain fps
+
+[How]
+Revert previous optimizations for low frame rates.
+
+Signed-off-by: Amanda Liu <amanda.liu@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/modules/freesync/freesync.c | 32 ++++++++-----------
+ .../amd/display/modules/inc/mod_freesync.h | 1 -
+ 2 files changed, 13 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 52c8edbde2c4..40ffed098e79 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -35,8 +35,8 @@
+ #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
+ /* Number of elements in the render times cache array */
+ #define RENDER_TIMES_MAX_COUNT 10
+-/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
+-#define BTR_MAX_MARGIN 2500
++/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
++#define BTR_EXIT_MARGIN 2000
+ /* Threshold to change BTR multiplier (to avoid frequent changes) */
+ #define BTR_DRIFT_MARGIN 2000
+ /*Threshold to exit fixed refresh rate*/
+@@ -252,22 +252,24 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
+ unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
+ unsigned int frames_to_insert = 0;
++ unsigned int min_frame_duration_in_ns = 0;
++ unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
+ unsigned int delta_from_mid_point_delta_in_us;
+- unsigned int max_render_time_in_us =
+- in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
++
++ min_frame_duration_in_ns = ((unsigned int) (div64_u64(
++ (1000000000ULL * 1000000),
++ in_out_vrr->max_refresh_in_uhz)));
+
+ /* Program BTR */
+- if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
++ if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
+ /* Exit Below the Range */
+ if (in_out_vrr->btr.btr_active) {
+ in_out_vrr->btr.frame_counter = 0;
+ in_out_vrr->btr.btr_active = false;
+ }
+- } else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
++ } else if (last_render_time_in_us > max_render_time_in_us) {
+ /* Enter Below the Range */
+- if (!in_out_vrr->btr.btr_active) {
+- in_out_vrr->btr.btr_active = true;
+- }
++ in_out_vrr->btr.btr_active = true;
+ }
+
+ /* BTR set to "not active" so disengage */
+@@ -323,9 +325,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ /* Choose number of frames to insert based on how close it
+ * can get to the mid point of the variable range.
+ */
+- if ((frame_time_in_us / mid_point_frames_ceil) > in_out_vrr->min_duration_in_us &&
+- (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2 ||
+- mid_point_frames_floor < 2)) {
++ if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
+ frames_to_insert = mid_point_frames_ceil;
+ delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
+ delta_from_mid_point_in_us_1;
+@@ -341,7 +341,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ if (in_out_vrr->btr.frames_to_insert != 0 &&
+ delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
+ if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
+- max_render_time_in_us) &&
++ in_out_vrr->max_duration_in_us) &&
+ ((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
+ in_out_vrr->min_duration_in_us))
+ frames_to_insert = in_out_vrr->btr.frames_to_insert;
+@@ -794,11 +794,6 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ refresh_range = in_out_vrr->max_refresh_in_uhz -
+ in_out_vrr->min_refresh_in_uhz;
+
+- in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
+- 2 * in_out_vrr->min_duration_in_us;
+- if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
+- in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
+-
+ in_out_vrr->supported = true;
+ }
+
+@@ -814,7 +809,6 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ in_out_vrr->btr.inserted_duration_in_us = 0;
+ in_out_vrr->btr.frames_to_insert = 0;
+ in_out_vrr->btr.frame_counter = 0;
+-
+ in_out_vrr->btr.mid_point_in_us =
+ (in_out_vrr->min_duration_in_us +
+ in_out_vrr->max_duration_in_us) / 2;
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+index dbe7835aabcf..dc187844d10b 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+@@ -92,7 +92,6 @@ struct mod_vrr_params_btr {
+ uint32_t inserted_duration_in_us;
+ uint32_t frames_to_insert;
+ uint32_t frame_counter;
+- uint32_t margin_in_us;
+ };
+
+ struct mod_vrr_params_fixed_refresh {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4707-drm-amd-display-update-dispclk-and-dppclk-vco-freque.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4707-drm-amd-display-update-dispclk-and-dppclk-vco-freque.patch
new file mode 100644
index 00000000..f8c681de
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4707-drm-amd-display-update-dispclk-and-dppclk-vco-freque.patch
@@ -0,0 +1,33 @@
+From 40c811e3469cfcdf491ec358906752e99f71b56c Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Fri, 15 Nov 2019 12:04:25 -0500
+Subject: [PATCH 4707/4736] drm/amd/display: update dispclk and dppclk vco
+ frequency
+
+Value obtained from DV is not allowing 8k60 CTA mode with DSC to
+pass, after checking real value being used in hw, find out that
+correct value is 3600, which will allow that mode.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 23727c3f2e01..dd66be12321a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -255,7 +255,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
+ .vmm_page_size_bytes = 4096,
+ .dram_clock_change_latency_us = 23.84,
+ .return_bus_width_bytes = 64,
+- .dispclk_dppclk_vco_speed_mhz = 3550,
++ .dispclk_dppclk_vco_speed_mhz = 3600,
+ .xfc_bus_transport_time_us = 4,
+ .xfc_xbuf_latency_tolerance_us = 4,
+ .use_urgent_burst_bw = 1,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4708-drm-amd-display-Implement-DePQ-for-DCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4708-drm-amd-display-Implement-DePQ-for-DCN2.patch
new file mode 100644
index 00000000..859472a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4708-drm-amd-display-Implement-DePQ-for-DCN2.patch
@@ -0,0 +1,53 @@
+From f86e6c9ce2835a5764e92b6a71e875937d773c6f Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Fri, 15 Nov 2019 17:39:12 -0500
+Subject: [PATCH 4708/4736] drm/amd/display: Implement DePQ for DCN2
+
+[Why]
+Need support for more color management in 10bit
+surface.
+
+[How]
+Provide support for DePQ for 10bit surface
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 +++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+index 2d112c316424..05a3e7f97ef0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+@@ -149,6 +149,9 @@ void dpp2_set_degamma(
+ case IPP_DEGAMMA_MODE_HW_xvYCC:
+ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
+ break;
++ case IPP_DEGAMMA_MODE_USER_PWL:
++ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
++ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 036a43717a47..8b04c18057d3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -882,6 +882,11 @@ bool dcn20_set_input_transfer_func(struct dc *dc,
+ IPP_DEGAMMA_MODE_BYPASS);
+ break;
+ case TRANSFER_FUNCTION_PQ:
++ dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
++ cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
++ dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
++ result = true;
++ break;
+ default:
+ result = false;
+ break;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4709-drm-amd-display-3.2.62.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4709-drm-amd-display-3.2.62.patch
new file mode 100644
index 00000000..9e853c54
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4709-drm-amd-display-3.2.62.patch
@@ -0,0 +1,28 @@
+From 56b1d473452a38d614af51fc1831a18c42b88e26 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 18 Nov 2019 08:33:34 -0500
+Subject: [PATCH 4709/4736] drm/amd/display: 3.2.62
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index f4884548e77e..f71f1e5734d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+
+-#define DC_VER "3.2.61"
++#define DC_VER "3.2.62"
+
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4710-drm-amd-display-Change-HDR_MULT-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4710-drm-amd-display-Change-HDR_MULT-check.patch
new file mode 100644
index 00000000..9d9cfc50
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4710-drm-amd-display-Change-HDR_MULT-check.patch
@@ -0,0 +1,47 @@
+From d0bde5aa157cf73ba730a8c950acbeface6e6318 Mon Sep 17 00:00:00 2001
+From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Date: Fri, 15 Nov 2019 10:00:46 -0500
+Subject: [PATCH 4710/4736] drm/amd/display: Change HDR_MULT check
+
+[Why]
+Currently we require HDR_MULT >= 1.0
+There are scenarios where we need < 1.0
+
+[How]
+Only guard against 0 - it will black-screen image.
+It is up to higher-level logic to decide what HDR_MULT
+values are allowed in each particular case.
+
+Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index c085a561b24c..35599d4ba6f6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2392,17 +2392,13 @@ void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
+ struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
+ uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
+ struct custom_float_format fmt;
+- bool mult_negative; // True if fixed31_32 sign bit indicates negative value
+- uint32_t mult_int; // int component of fixed31_32
+
+ fmt.exponenta_bits = 6;
+ fmt.mantissa_bits = 12;
+ fmt.sign = true;
+
+- mult_negative = multiplier.value >> 63 != 0;
+- mult_int = multiplier.value >> 32;
+
+- if (mult_int && !mult_negative) // Check if greater than 1
++ if (!dc_fixpt_eq(multiplier, dc_fixpt_from_int(0))) // check != 0
+ convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
+
+ pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4711-drm-amd-display-Increase-the-number-of-retries-after.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4711-drm-amd-display-Increase-the-number-of-retries-after.patch
new file mode 100644
index 00000000..baa1bce5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4711-drm-amd-display-Increase-the-number-of-retries-after.patch
@@ -0,0 +1,84 @@
+From 84f4c6b08f0e37320574201bfa16302a000cecdc Mon Sep 17 00:00:00 2001
+From: George Shen <george.shen@amd.com>
+Date: Fri, 15 Nov 2019 18:56:57 -0500
+Subject: [PATCH 4711/4736] drm/amd/display: Increase the number of retries
+ after AUX DEFER
+
+[Why]
+When a timeout occurs after a DEFER, some devices require more retries
+than in the case of a regular timeout.
+
+[How]
+In a timeout occurrence, check whether a DEFER has occurred before the
+timeout and retry MAX_DEFER_RETRIES retries times instead of
+MAX_TIMEOUT_RETRIES.
+
+Signed-off-by: George Shen <george.shen@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 32 ++++++++++++++------
+ 1 file changed, 22 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 0b9d8c5b9323..5bf6068da717 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -608,6 +608,8 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ uint8_t reply;
+ bool payload_reply = true;
+ enum aux_channel_operation_result operation_result;
++ bool retry_on_defer = false;
++
+ int aux_ack_retries = 0,
+ aux_defer_retries = 0,
+ aux_i2c_defer_retries = 0,
+@@ -638,8 +640,9 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ break;
+
+ case AUX_TRANSACTION_REPLY_AUX_DEFER:
+- case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+ case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
++ retry_on_defer = true;
++ case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+ if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) {
+ goto fail;
+ } else {
+@@ -672,15 +675,24 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ break;
+
+ case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
+- if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES)
+- goto fail;
+- else {
+- /*
+- * DP 1.4, 2.8.2: AUX Transaction Response/Reply Timeouts
+- * According to the DP spec there should be 3 retries total
+- * with a 400us wait inbetween each. Hardware already waits
+- * for 550us therefore no wait is required here.
+- */
++ // Check whether a DEFER had occurred before the timeout.
++ // If so, treat timeout as a DEFER.
++ if (retry_on_defer) {
++ if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES)
++ goto fail;
++ else if (payload->defer_delay > 0)
++ msleep(payload->defer_delay);
++ } else {
++ if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES)
++ goto fail;
++ else {
++ /*
++ * DP 1.4, 2.8.2: AUX Transaction Response/Reply Timeouts
++ * According to the DP spec there should be 3 retries total
++ * with a 400us wait inbetween each. Hardware already waits
++ * for 550us therefore no wait is required here.
++ */
++ }
+ }
+ break;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4712-drm-amd-display-Compare-clock-state-member-to-determ.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4712-drm-amd-display-Compare-clock-state-member-to-determ.patch
new file mode 100644
index 00000000..2530ccef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4712-drm-amd-display-Compare-clock-state-member-to-determ.patch
@@ -0,0 +1,58 @@
+From 2796f186fe4fe681f0ed1e70941a9c461a5896bb Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Mon, 18 Nov 2019 13:45:50 -0500
+Subject: [PATCH 4712/4736] drm/amd/display: Compare clock state member to
+ determine optimization.
+
+[Why]
+It seems always request passive flip on RN due to incorrect compare
+clock state to determine optization.
+
+[How]
+Instead of calling memcmp, compare clock state member to determine the
+condition.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 18 +++++++++++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 37230d3d94a0..de51ef12e33a 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -471,12 +471,28 @@ static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+
+ }
+
++static bool rn_are_clock_states_equal(struct dc_clocks *a,
++ struct dc_clocks *b)
++{
++ if (a->dispclk_khz != b->dispclk_khz)
++ return false;
++ else if (a->dppclk_khz != b->dppclk_khz)
++ return false;
++ else if (a->dcfclk_khz != b->dcfclk_khz)
++ return false;
++ else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
++ return false;
++
++ return true;
++}
++
++
+ static struct clk_mgr_funcs dcn21_funcs = {
+ .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ .update_clocks = rn_update_clocks,
+ .init_clocks = rn_init_clocks,
+ .enable_pme_wa = rn_enable_pme_wa,
+- /* .dump_clk_registers = rn_dump_clk_registers, */
++ .are_clock_states_equal = rn_are_clock_states_equal,
+ .notify_wm_ranges = rn_notify_wm_ranges
+ };
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4713-drm-amd-display-update-dml-related-structs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4713-drm-amd-display-update-dml-related-structs.patch
new file mode 100644
index 00000000..a895b8b5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4713-drm-amd-display-update-dml-related-structs.patch
@@ -0,0 +1,80 @@
+From a071cf5aaedf11c10cee75867b8c72d869ed3323 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Mon, 28 Oct 2019 15:42:29 -0400
+Subject: [PATCH 4713/4736] drm/amd/display: update dml related structs
+
+In preparation for further changes
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 3 +++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 +-
+ 3 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 5c00223b279e..51336b5c38ef 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2033,6 +2033,7 @@ int dcn20_populate_dml_pipes_from_context(
+ pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
+ if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
+ pipes[pipe_cnt].pipe.src.viewport_height = 1080;
++ pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
+ pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
+ pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
+ pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
+@@ -2066,6 +2067,7 @@ int dcn20_populate_dml_pipes_from_context(
+ pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
+ pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
+ pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
++ pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
+ if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+ pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
+ pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index 516396d53d01..220d5e610f1f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -99,6 +99,7 @@ struct _vcs_dpi_soc_bounding_box_st {
+ unsigned int num_chans;
+ unsigned int vmm_page_size_bytes;
+ unsigned int hostvm_min_page_size_bytes;
++ unsigned int gpuvm_min_page_size_bytes;
+ double dram_clock_change_latency_us;
+ double dummy_pstate_latency_us;
+ double writeback_dram_clock_change_latency_us;
+@@ -224,6 +225,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
+ int source_scan;
+ int sw_mode;
+ int macro_tile_size;
++ unsigned int surface_height_y;
+ unsigned int viewport_width;
+ unsigned int viewport_height;
+ unsigned int viewport_y_y;
+@@ -400,6 +402,7 @@ struct _vcs_dpi_display_rq_misc_params_st {
+ struct _vcs_dpi_display_rq_params_st {
+ unsigned char yuv420;
+ unsigned char yuv420_10bpc;
++ unsigned char rgbe_alpha;
+ display_rq_misc_params_st misc;
+ display_rq_sizing_params_st sizing;
+ display_rq_dlg_params_st dlg;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index b1c2b79e42b6..15b72a8b5174 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -231,7 +231,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading = soc->dcn_downspread_percent; // new
+ mode_lib->vba.DISPCLKDPPCLKVCOSpeed = soc->dispclk_dppclk_vco_speed_mhz; // new
+ mode_lib->vba.VMMPageSize = soc->vmm_page_size_bytes;
+- mode_lib->vba.GPUVMMinPageSize = soc->vmm_page_size_bytes / 1024;
++ mode_lib->vba.GPUVMMinPageSize = soc->gpuvm_min_page_size_bytes / 1024;
+ mode_lib->vba.HostVMMinPageSize = soc->hostvm_min_page_size_bytes / 1024;
+ // Set the voltage scaling clocks as the defaults. Most of these will
+ // be set to different values by the test
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4714-drm-amd-display-correct-log-message-for-lttpr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4714-drm-amd-display-correct-log-message-for-lttpr.patch
new file mode 100644
index 00000000..9c7f9b0a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4714-drm-amd-display-correct-log-message-for-lttpr.patch
@@ -0,0 +1,43 @@
+From 15578bf41c09dbff12183fe17d59459f40274040 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Mon, 18 Nov 2019 12:22:06 -0500
+Subject: [PATCH 4714/4736] drm/amd/display: correct log message for lttpr
+
+[Why]
+When setting lttpr mode, the new mode to bet is not logged properly.
+
+[How]
+Update log message to show the right mode.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: George Shen <George.Shen@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index dfcd6421ee01..42aa889fd0f5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1219,7 +1219,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+ uint8_t repeater_id;
+ uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
+
+- DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
++ DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
+ core_link_write_dpcd(link,
+ DP_PHY_REPEATER_MODE,
+ (uint8_t *)&repeater_mode,
+@@ -1227,7 +1227,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+
+ if (!link->is_lttpr_mode_transparent) {
+
+- DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
++ DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
+
+ repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
+ core_link_write_dpcd(link,
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch
new file mode 100644
index 00000000..4aed01d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch
@@ -0,0 +1,51 @@
+From d691a52f1ffe68a039c5f235860fef167ba339b8 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 18 Nov 2019 13:31:04 -0500
+Subject: [PATCH 4715/4736] drm/amd/display: Extend DMCUB offload testing into
+ dcn20/21
+
+[Why]
+To quickly validate whether DMCUB is running and accepting commands for
+offload testing we want to intercept a common sequence as part of
+modeset programming.
+
+[How]
+OTG enable will cause the most impact in terms of golden register
+changes and it's a single register write.
+
+This approach was previously done in dcn10 code when it was shared with
+dcn20 but it wasn't ported over to the dcn20 code.
+
+Port over start, execute and wait sequence into dcn20_optc.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index f5854a5d2b76..673c83e2afd4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -59,11 +59,16 @@ bool optc2_enable_crtc(struct timing_generator *optc)
+ REG_UPDATE(CONTROL,
+ VTG0_ENABLE, 1);
+
++ REG_SEQ_START();
++
+ /* Enable CRTC */
+ REG_UPDATE_2(OTG_CONTROL,
+ OTG_DISABLE_POINT_CNTL, 3,
+ OTG_MASTER_EN, 1);
+
++ REG_SEQ_SUBMIT();
++ REG_SEQ_WAIT_DONE();
++
+ return true;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch
new file mode 100644
index 00000000..ea8a267e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch
@@ -0,0 +1,31 @@
+From e16b88c7c8f840222dca7dfbf9bf6bb4f25505fc Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 5 Dec 2019 14:21:31 -0500
+Subject: [PATCH 4716/4736] drm/amdgpu: Fix BACO entry failure in NAVI10.
+
+BACO feature must be kept enabled to allow entry into
+BACO state in SMU during runtime suspend.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Tested-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 2dd960e85a24..4ed8bdc82fea 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1383,7 +1383,7 @@ static int smu_suspend(void *handle)
+ if (ret)
+ return ret;
+
+- if (adev->in_gpu_reset && baco_feature_is_enabled) {
++ if (baco_feature_is_enabled) {
+ ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
+ if (ret) {
+ pr_warn("set BACO feature enabled failed, return %d\n", ret);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch
new file mode 100644
index 00000000..81355fd2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch
@@ -0,0 +1,34 @@
+From 50044c3bd38a50919359d7ed31b2a9eec299170c Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 26 Nov 2019 15:05:07 +0800
+Subject: [PATCH 4717/4736] drm/amd/powerplay: drop unnecessary warning prompt
+
+As the check may be done with purpose and the warning
+output will be confusing.
+
+Change-Id: Ie0928c324a8161d44068f8ce648d56f6d9e8cd3d
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 3a793c6ccbf0..42a7478964eb 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -280,10 +280,8 @@ static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER
+ return -EINVAL;
+
+ mapping = arcturus_workload_map[profile];
+- if (!(mapping.valid_mapping)) {
+- pr_warn("Unsupported SMU power source: %d\n", profile);
++ if (!(mapping.valid_mapping))
+ return -EINVAL;
+- }
+
+ return mapping.map_to;
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch
new file mode 100644
index 00000000..c9ef1e20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch
@@ -0,0 +1,95 @@
+From cfa7c454a7f8b3e20067bf4b6e8084c40d5bab3c Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 4 Dec 2019 17:29:52 +0800
+Subject: [PATCH 4718/4736] drm/amd/powerplay: pre-check the SMU state before
+ issuing message
+
+Abort the message issuing if the SMU was not in the right state.
+
+Change-Id: Ida9f911e051f6e78de4f475956c78637e56e6ea3
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++--------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 16 ++++++++--------
+ 2 files changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 9e405a60ee6e..d65187993ef9 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -77,15 +77,13 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
+ for (i = 0; i < timeout; i++) {
+ cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+ if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
+- break;
++ return cur_value == 0x1 ? 0 : -EIO;
++
+ udelay(1);
+ }
+
+ /* timeout means wrong logic */
+- if (i == timeout)
+- return -ETIME;
+-
+- return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
++ return -ETIME;
+ }
+
+ int
+@@ -101,9 +99,11 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
+ return index;
+
+ ret = smu_v11_0_wait_for_response(smu);
+- if (ret)
+- pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
+- smu_get_message_name(smu, msg), index, param, ret);
++ if (ret) {
++ pr_err("Msg issuing pre-check failed and "
++ "SMU may be not in the right state!\n");
++ return ret;
++ }
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 269a7d73b58d..951aa4570a04 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -66,15 +66,13 @@ int smu_v12_0_wait_for_response(struct smu_context *smu)
+ for (i = 0; i < adev->usec_timeout; i++) {
+ cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+ if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
+- break;
++ return cur_value == 0x1 ? 0 : -EIO;
++
+ udelay(1);
+ }
+
+ /* timeout means wrong logic */
+- if (i == adev->usec_timeout)
+- return -ETIME;
+-
+- return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
++ return -ETIME;
+ }
+
+ int
+@@ -90,9 +88,11 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu,
+ return index;
+
+ ret = smu_v12_0_wait_for_response(smu);
+- if (ret)
+- pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
+- index, ret, param);
++ if (ret) {
++ pr_err("Msg issuing pre-check failed and "
++ "SMU may be not in the right state!\n");
++ return ret;
++ }
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch
new file mode 100644
index 00000000..6fb07e55
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch
@@ -0,0 +1,68 @@
+From 167d845d08e4d436ea15f98bce4ccc24aecad582 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 6 Dec 2019 18:09:19 +0800
+Subject: [PATCH 4719/4736] drm/amdgpu: fix resume failures due to psp fw
+ loading sequence change (v3)
+
+this fix the regression caused by asd/ta loading sequence
+adjustment recently. asd/ta loading was move out from
+hw_start and should also be applied to psp_resume.
+otherwise those fw loading will be ignored in resume phase.
+
+v2: add the mutex unlock for asd loading failure case
+v3: merge the error handling to failed tag
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 728f53ea2ad6..9b869fa9b594 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1723,6 +1723,39 @@ static int psp_resume(void *handle)
+ if (ret)
+ goto failed;
+
++ ret = psp_asd_load(psp);
++ if (ret) {
++ DRM_ERROR("PSP load asd failed!\n");
++ goto failed;
++ }
++
++ if (adev->gmc.xgmi.num_physical_nodes > 1) {
++ ret = psp_xgmi_initialize(psp);
++ /* Warning the XGMI seesion initialize failure
++ * Instead of stop driver initialization
++ */
++ if (ret)
++ dev_err(psp->adev->dev,
++ "XGMI: Failed to initialize XGMI session\n");
++ }
++
++ if (psp->adev->psp.ta_fw) {
++ ret = psp_ras_initialize(psp);
++ if (ret)
++ dev_err(psp->adev->dev,
++ "RAS: Failed to initialize RAS\n");
++
++ ret = psp_hdcp_initialize(psp);
++ if (ret)
++ dev_err(psp->adev->dev,
++ "HDCP: Failed to initialize HDCP\n");
++
++ ret = psp_dtm_initialize(psp);
++ if (ret)
++ dev_err(psp->adev->dev,
++ "DTM: Failed to initialize DTM\n");
++ }
++
+ mutex_unlock(&adev->firmware.mutex);
+
+ return 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch
new file mode 100644
index 00000000..03e077e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch
@@ -0,0 +1,104 @@
+From 2ee4b662abfe96542dfd01f2013e4c509d579c57 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Wed, 4 Dec 2019 21:23:08 -0500
+Subject: [PATCH 4720/4736] drm/amdkfd: Improve kfd_process lookup in kfd_ioctl
+
+Use filep->private_data to store a pointer to the kfd_process data
+structure. Take an extra reference for that, which gets released in
+the kfd_release callback. Check that the process calling kfd_ioctl
+is the same that opened the file descriptor. Return -EBADF if it's
+not, so that this error can be distinguished in user mode.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Philip Yang <Philip.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 30 ++++++++++++++++++++----
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 ++
+ 2 files changed, 28 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index d9cdb25974f9..1946ac4c95dd 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -50,6 +50,7 @@
+
+ static long kfd_ioctl(struct file *, unsigned int, unsigned long);
+ static int kfd_open(struct inode *, struct file *);
++static int kfd_release(struct inode *, struct file *);
+ static int kfd_mmap(struct file *, struct vm_area_struct *);
+
+ static const char kfd_dev_name[] = "kfd";
+@@ -59,6 +60,7 @@ static const struct file_operations kfd_fops = {
+ .unlocked_ioctl = kfd_ioctl,
+ .compat_ioctl = kfd_ioctl,
+ .open = kfd_open,
++ .release = kfd_release,
+ .mmap = kfd_mmap,
+ };
+
+@@ -142,8 +144,13 @@ static int kfd_open(struct inode *inode, struct file *filep)
+ if (IS_ERR(process))
+ return PTR_ERR(process);
+
+- if (kfd_is_locked())
++ if (kfd_is_locked()) {
++ kfd_unref_process(process);
+ return -EAGAIN;
++ }
++
++ /* filep now owns the reference returned by kfd_create_process */
++ filep->private_data = process;
+
+ dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
+ process->pasid, process->is_32bit_user_mode);
+@@ -151,6 +158,16 @@ static int kfd_open(struct inode *inode, struct file *filep)
+ return 0;
+ }
+
++static int kfd_release(struct inode *inode, struct file *filep)
++{
++ struct kfd_process *process = filep->private_data;
++
++ if (process)
++ kfd_unref_process(process);
++
++ return 0;
++}
++
+ static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
+ void *data)
+ {
+@@ -2996,9 +3013,14 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+
+ dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
+
+- process = kfd_get_process(current);
+- if (IS_ERR(process)) {
+- dev_dbg(kfd_device, "no process\n");
++ /* Get the process struct from the filep. Only the process
++ * that opened /dev/kfd can use the file descriptor. Child
++ * processes need to create their own KFD device context.
++ */
++ process = filep->private_data;
++ if (process->lead_thread != current->group_leader) {
++ dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
++ retcode = -EBADF;
+ goto err_i1;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index d78c36ba54e3..ca7b80bd0114 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -328,6 +328,8 @@ struct kfd_process *kfd_create_process(struct file *filep)
+ (int)process->lead_thread->pid);
+ }
+ out:
++ if (!IS_ERR(process))
++ kref_get(&process->ref);
+ mutex_unlock(&kfd_processes_mutex);
+
+ return process;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4721-drm-amdgpu-display-add-fallthrough-comment.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4721-drm-amdgpu-display-add-fallthrough-comment.patch
new file mode 100644
index 00000000..3273b68f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4721-drm-amdgpu-display-add-fallthrough-comment.patch
@@ -0,0 +1,29 @@
+From 3e8aa1c890d1f39d366f5606b7051f4e9464dc67 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 5 Dec 2019 16:38:01 -0500
+Subject: [PATCH 4721/4736] drm/amdgpu/display: add fallthrough comment
+
+To avoid a compiler warning.
+
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 5bf6068da717..282d7f4225d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -642,6 +642,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ case AUX_TRANSACTION_REPLY_AUX_DEFER:
+ case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
+ retry_on_defer = true;
++ /* fall through */
+ case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+ if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) {
+ goto fail;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch
new file mode 100644
index 00000000..54f6b383
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch
@@ -0,0 +1,86 @@
+From b15d2a4a2436144a11919630bde2a8d37e2b9cb8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 28 Nov 2019 14:51:46 +0100
+Subject: [PATCH 4722/4736] drm/amdgpu: move VM eviction decision into
+ amdgpu_vm.c
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When a page tables needs to be evicted the VM code should
+decide if that is possible or not.
+
+Change-Id: Ib9a934b37a39f06caeb15d7375fb1c4fc8f9b51c
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 +----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
+ 3 files changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index d93bfaca5daf..4e36ce46455f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1624,11 +1624,8 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
+ struct dma_fence *f;
+ int i;
+
+- /* Don't evict VM page tables while they are busy, otherwise we can't
+- * cleanly handle page faults.
+- */
+ if (bo->type == ttm_bo_type_kernel &&
+- !reservation_object_test_signaled_rcu(bo->resv, true))
++ !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
+ return false;
+
+ /* If bo is a KFD BO, check if the bo belongs to the current process.
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 90ac5390ecdf..f47158087b83 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2504,6 +2504,28 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
+ kfree(bo_va);
+ }
+
++/**
++ * amdgpu_vm_evictable - check if we can evict a VM
++ *
++ * @bo: A page table of the VM.
++ *
++ * Check if it is possible to evict a VM.
++ */
++bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
++{
++ struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
++
++ /* Page tables of a destroyed VM can go away immediately */
++ if (!bo_base || !bo_base->vm)
++ return true;
++
++ /* Don't evict VM page tables while they are busy */
++ if (!reservation_object_test_signaled_rcu(bo->tbo.resv, true))
++ return false;
++
++ return true;
++}
++
+ /**
+ * amdgpu_vm_bo_invalidate - mark the bo as invalid
+ *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 76fcf853035c..db561765453b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -381,6 +381,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
+ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
+ struct amdgpu_bo_va *bo_va,
+ bool clear);
++bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
+ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
+ struct amdgpu_bo *bo, bool evicted);
+ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch
new file mode 100644
index 00000000..d97d306d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch
@@ -0,0 +1,359 @@
+From df1e3b51e41af0ed53e425f748a2a63cefcfa62d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 29 Nov 2019 11:33:54 +0100
+Subject: [PATCH 4723/4736] drm/amdgpu: explicitely sync to VM updates v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Allows us to reduce the overhead while syncing to fences a bit.
+
+v2: also drop adev parameter from the functions
+
+Change-Id: I0828d0691fb87f0b9ae9205b15e18e6509c86d61
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 19 +++-------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 13 +++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 38 ++++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h | 8 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +-
+ 8 files changed, 52 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 3d7d6b5f423e..a21201e579b1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -392,7 +392,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
+ if (ret)
+ return ret;
+
+- return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
++ return amdgpu_sync_fence(sync, vm->last_update, false);
+ }
+
+ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
+@@ -807,7 +807,7 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
+
+ amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
+
+- amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
++ amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
+
+ return 0;
+ }
+@@ -826,7 +826,7 @@ static int update_gpuvm_pte(struct amdgpu_device *adev,
+ return ret;
+ }
+
+- return amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
++ return amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
+ }
+
+ static int map_bo_to_gpuvm(struct amdgpu_device *adev,
+@@ -2337,7 +2337,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
+ pr_debug("Memory eviction: Validate BOs failed. Try again\n");
+ goto validate_map_fail;
+ }
+- ret = amdgpu_sync_fence(NULL, &sync_obj, bo->tbo.moving, false);
++ ret = amdgpu_sync_fence(&sync_obj, bo->tbo.moving, false);
+ if (ret) {
+ pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
+ goto validate_map_fail;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index e8dfbcfad034..2c570274b5a6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -790,29 +790,23 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
+ if (r)
+ return r;
+
+- r = amdgpu_sync_fence(adev, &p->job->sync,
+- fpriv->prt_va->last_pt_update, false);
++ r = amdgpu_sync_vm_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
+ if (r)
+ return r;
+
+ if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
+- struct dma_fence *f;
+-
+ bo_va = fpriv->csa_va;
+ BUG_ON(!bo_va);
+ r = amdgpu_vm_bo_update(adev, bo_va, false);
+ if (r)
+ return r;
+
+- f = bo_va->last_pt_update;
+- r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
++ r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
+ if (r)
+ return r;
+ }
+
+ amdgpu_bo_list_for_each_entry(e, p->bo_list) {
+- struct dma_fence *f;
+-
+ /* ignore duplicates */
+ bo = ttm_to_amdgpu_bo(e->tv.bo);
+ if (!bo)
+@@ -826,8 +820,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
+ if (r)
+ return r;
+
+- f = bo_va->last_pt_update;
+- r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
++ r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
+ if (r)
+ return r;
+ }
+@@ -840,7 +833,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
+ if (r)
+ return r;
+
+- r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
++ r = amdgpu_sync_vm_fence(&p->job->sync, vm->last_update);
+ if (r)
+ return r;
+
+@@ -982,7 +975,7 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
+ dma_fence_put(old);
+ }
+
+- r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
++ r = amdgpu_sync_fence(&p->job->sync, fence, true);
+ dma_fence_put(fence);
+ if (r)
+ return r;
+@@ -1003,7 +996,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
+
+ return r;
+ }
+- r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
++ r = amdgpu_sync_fence(&p->job->sync, fence, true);
+ dma_fence_put(fence);
+
+ return r;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+index dfe155566571..dc2ea2b60ed8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+@@ -206,7 +206,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
+ int r;
+
+ if (ring->vmid_wait && !dma_fence_is_signaled(ring->vmid_wait))
+- return amdgpu_sync_fence(adev, sync, ring->vmid_wait, false);
++ return amdgpu_sync_fence(sync, ring->vmid_wait, false);
+
+ fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
+ if (!fences)
+@@ -241,7 +241,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
+ return -ENOMEM;
+ }
+
+- r = amdgpu_sync_fence(adev, sync, &array->base, false);
++ r = amdgpu_sync_fence(sync, &array->base, false);
+ dma_fence_put(ring->vmid_wait);
+ ring->vmid_wait = &array->base;
+ return r;
+@@ -294,7 +294,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
+ tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
+ if (tmp) {
+ *id = NULL;
+- r = amdgpu_sync_fence(adev, sync, tmp, false);
++ r = amdgpu_sync_fence(sync, tmp, false);
+ return r;
+ }
+ needs_flush = true;
+@@ -303,7 +303,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
+ /* Good we can use this VMID. Remember this submission as
+ * user of the VMID.
+ */
+- r = amdgpu_sync_fence(ring->adev, &(*id)->active, fence, false);
++ r = amdgpu_sync_fence(&(*id)->active, fence, false);
+ if (r)
+ return r;
+
+@@ -375,7 +375,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
+ /* Good, we can use this VMID. Remember this submission as
+ * user of the VMID.
+ */
+- r = amdgpu_sync_fence(ring->adev, &(*id)->active, fence, false);
++ r = amdgpu_sync_fence(&(*id)->active, fence, false);
+ if (r)
+ return r;
+
+@@ -435,8 +435,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
+ id = idle;
+
+ /* Remember this submission as user of the VMID */
+- r = amdgpu_sync_fence(ring->adev, &id->active,
+- fence, false);
++ r = amdgpu_sync_fence(&id->active, fence, false);
+ if (r)
+ goto error;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+index 71fd9bb7ead7..8b7fce7c811f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -193,8 +193,7 @@ static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
+ fence = amdgpu_sync_get_fence(&job->sync, &explicit);
+ if (fence && explicit) {
+ if (drm_sched_dependency_optimized(fence, s_entity)) {
+- r = amdgpu_sync_fence(ring->adev, &job->sched_sync,
+- fence, false);
++ r = amdgpu_sync_fence(&job->sched_sync, fence, false);
+ if (r)
+ DRM_ERROR("Error adding fence (%d)\n", r);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
+index 3d5beb00b0db..a467b177543b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
+@@ -408,7 +408,7 @@ int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity,
+ mutex_lock(&centity->sem_lock);
+ list_for_each_entry_safe(dep, tmp, &centity->sem_dep_list,
+ list) {
+- r = amdgpu_sync_fence(ctx->adev, sync, dep->fence, true);
++ r = amdgpu_sync_fence(sync, dep->fence, true);
+ if (r)
+ goto err;
+ dma_fence_put(dep->fence);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+index 2d6f5ec77a68..17f017fc8fcb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+@@ -130,7 +130,8 @@ static void amdgpu_sync_keep_later(struct dma_fence **keep,
+ * Tries to add the fence to an existing hash entry. Returns true when an entry
+ * was found, false otherwise.
+ */
+-static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f, bool explicit)
++static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f,
++ bool explicit)
+ {
+ struct amdgpu_sync_entry *e;
+
+@@ -152,19 +153,18 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f,
+ * amdgpu_sync_fence - remember to sync to this fence
+ *
+ * @sync: sync object to add fence to
+- * @fence: fence to sync to
++ * @f: fence to sync to
++ * @explicit: if this is an explicit dependency
+ *
++ * Add the fence to the sync object.
+ */
+-int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
+- struct dma_fence *f, bool explicit)
++int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f,
++ bool explicit)
+ {
+ struct amdgpu_sync_entry *e;
+
+ if (!f)
+ return 0;
+- if (amdgpu_sync_same_dev(adev, f) &&
+- amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
+- amdgpu_sync_keep_later(&sync->last_vm_update, f);
+
+ if (amdgpu_sync_add_later(sync, f, explicit))
+ return 0;
+@@ -180,6 +180,24 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
+ return 0;
+ }
+
++/**
++ * amdgpu_sync_vm_fence - remember to sync to this VM fence
++ *
++ * @adev: amdgpu device
++ * @sync: sync object to add fence to
++ * @fence: the VM fence to add
++ *
++ * Add the fence to the sync object and remember it as VM update.
++ */
++int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence)
++{
++ if (!fence)
++ return 0;
++
++ amdgpu_sync_keep_later(&sync->last_vm_update, fence);
++ return amdgpu_sync_fence(sync, fence, false);
++}
++
+ /**
+ * amdgpu_sync_resv - sync to a reservation object
+ *
+@@ -205,7 +223,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
+
+ /* always sync to the exclusive fence */
+ f = reservation_object_get_excl(resv);
+- r = amdgpu_sync_fence(adev, sync, f, false);
++ r = amdgpu_sync_fence(sync, f, false);
+
+ flist = reservation_object_get_list(resv);
+ if (!flist || r)
+@@ -240,7 +258,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
+ continue;
+ }
+
+- r = amdgpu_sync_fence(adev, sync, f, false);
++ r = amdgpu_sync_fence(sync, f, false);
+ if (r)
+ break;
+ }
+@@ -341,7 +359,7 @@ int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone)
+ hash_for_each_safe(source->fences, i, tmp, e, node) {
+ f = e->fence;
+ if (!dma_fence_is_signaled(f)) {
+- r = amdgpu_sync_fence(NULL, clone, f, e->explicit);
++ r = amdgpu_sync_fence(clone, f, e->explicit);
+ if (r)
+ return r;
+ } else {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
+index 10cf23a57f17..7ca71b306301 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
+@@ -40,8 +40,9 @@ struct amdgpu_sync {
+ };
+
+ void amdgpu_sync_create(struct amdgpu_sync *sync);
+-int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
+- struct dma_fence *f, bool explicit);
++int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f,
++ bool explicit);
++int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence);
+ int amdgpu_sync_resv(struct amdgpu_device *adev,
+ struct amdgpu_sync *sync,
+ struct reservation_object *resv,
+@@ -49,7 +50,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
+ bool explicit_sync);
+ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
+ struct amdgpu_ring *ring);
+-struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit);
++struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync,
++ bool *explicit);
+ int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone);
+ int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
+ void amdgpu_sync_free(struct amdgpu_sync *sync);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+index e8db1467a71d..107def9c3611 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+@@ -71,7 +71,7 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
+ p->num_dw_left = ndw;
+
+ /* Wait for moves to be completed */
+- r = amdgpu_sync_fence(p->adev, &p->job->sync, exclusive, false);
++ r = amdgpu_sync_fence(&p->job->sync, exclusive, false);
+ if (r)
+ return r;
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch
new file mode 100644
index 00000000..4857af18
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch
@@ -0,0 +1,60 @@
+From 09a07770eb015b075f2f1914e972f12ccb471e3c Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 26 Nov 2019 17:56:58 +0800
+Subject: [PATCH 4724/4736] drm/amdgpu: add condition to enable baco for ras
+ recovery
+
+Switch to baco reset method for ras recovery if the PMFW supported.
+If not, keep the original reset method.
+
+v2: revise the condition
+
+Change-Id: I07c3e6862be03e068745c73db8ea71f428ecba6b
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 18 ++++++++----------
+ 1 file changed, 8 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 3a2ec932c0bb..512d42b23603 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -556,7 +556,8 @@ static int soc15_mode2_reset(struct amdgpu_device *adev)
+ static enum amd_reset_method
+ soc15_asic_reset_method(struct amdgpu_device *adev)
+ {
+- bool baco_reset;
++ bool baco_reset = false;
++ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+@@ -570,18 +571,15 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
+ case CHIP_VEGA20:
+ if (adev->psp.sos_fw_version >= 0x80067)
+ soc15_asic_get_baco_capability(adev, &baco_reset);
+- else
+- baco_reset = false;
+- if (baco_reset) {
+- struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
+- struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+
+- if (hive || (ras && ras->supported))
+- baco_reset = false;
+- }
++ /*
++ * 1. PMFW version > 0x284300: all cases use baco
++ * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
++ */
++ if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
++ baco_reset = false;
+ break;
+ default:
+- baco_reset = false;
+ break;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4725-drm-amdgpu-Add-RAS-dbg-print-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4725-drm-amdgpu-Add-RAS-dbg-print-support.patch
new file mode 100644
index 00000000..59455bdc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4725-drm-amdgpu-Add-RAS-dbg-print-support.patch
@@ -0,0 +1,124 @@
+From eaa700cb57a23278d319c888d78d597db3a35a24 Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Tue, 3 Dec 2019 11:12:34 +0800
+Subject: [PATCH 4725/4736] drm/amdgpu: Add RAS dbg print support
+
+Leverage host to TA shared memory to capture dbg log information from RAS TA
+
+Change-Id: I5e287560a6d493edf9bc6ac9ebbcbaeca0017dc8
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +-
+ drivers/gpu/drm/amd/amdgpu/ta_ras_if.h | 16 ++++++++++++
+ 3 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 9b869fa9b594..f91da0b43e8c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -616,6 +616,36 @@ static int psp_xgmi_initialize(struct psp_context *psp)
+ }
+
+ // ras begin
++void psp_ras_print_dbg_msg(struct psp_context *psp)
++{
++ struct ta_ras_shared_memory *ras_cmd;
++ struct ta_dbg_msg_list *dbg_msgs;
++ struct ta_dbg_msg* msg;
++ uint32_t mem_offset;
++ int i, sec, m_sec;
++
++ ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
++ dbg_msgs = &ras_cmd->debug_messages;
++ msg = &dbg_msgs->msg;
++
++ for (i = 0; i < dbg_msgs->msg_cnt; i++)
++ {
++ mem_offset = (uint8_t*)msg - (uint8_t*)ras_cmd;
++
++ /* Validate memory access does not overflow shared region */
++ if (mem_offset >= PSP_RAS_SHARED_MEM_SIZE)
++ break;
++
++ /* Time stamp = seconds*1000000 + milli-seconds*1000 */
++ sec = (int)msg->time_stamp/1000000;
++ m_sec = ((int)msg->time_stamp - sec*1000000) / 1000;
++
++ DRM_INFO("[RAS] %d.%d : %s\n", sec, m_sec, msg->msg);
++
++ msg = (struct ta_dbg_msg*)((uint8_t*)msg + SIZE_OF_MSG_STRUCT(msg));
++ }
++}
++
+ static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ uint64_t ras_ta_mc, uint64_t ras_mc_shared,
+ uint32_t ras_ta_size, uint32_t shared_size)
+@@ -679,6 +709,8 @@ static int psp_ras_load(struct psp_context *psp)
+
+ kfree(cmd);
+
++ psp_ras_print_dbg_msg(psp);
++
+ return ret;
+ }
+
+@@ -747,6 +779,8 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
+
+ kfree(cmd);
+
++ psp_ras_print_dbg_msg(psp);
++
+ return ret;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 5f8fd3e3535b..a4d7690ea577 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -33,7 +33,7 @@
+ #define PSP_FENCE_BUFFER_SIZE 0x1000
+ #define PSP_CMD_BUFFER_SIZE 0x1000
+ #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
+-#define PSP_RAS_SHARED_MEM_SIZE 0x4000
++#define PSP_RAS_SHARED_MEM_SIZE 0x8000
+ #define PSP_1_MEG 0x100000
+ #define PSP_TMR_SIZE 0x400000
+ #define PSP_HDCP_SHARED_MEM_SIZE 0x4000
+diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+index ca7d05993ca2..bf1c4c55ce58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
++++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+@@ -97,6 +97,21 @@ struct ta_ras_trigger_error_input {
+ uint64_t value; // method if error injection. i.e persistent, coherent etc.
+ };
+
++#define SIZE_OF_MSG_STRUCT(msg_ptr) ((msg_ptr)->msg_size + sizeof(struct ta_dbg_msg) - sizeof(char))
++struct __attribute__((__packed__)) ta_dbg_msg
++{
++ uint16_t msg_size; // Not including string terminator
++ uint64_t time_stamp;
++ char msg[1]; // string of size determined by msg_size
++};
++
++struct ta_dbg_msg_list
++{
++ uint32_t total_buf_size;
++ uint32_t msg_cnt;
++ struct ta_dbg_msg msg;
++};
++
+ /* Common input structure for RAS callbacks */
+ /**********************************************************/
+ union ta_ras_cmd_input {
+@@ -113,6 +128,7 @@ struct ta_ras_shared_memory {
+ enum ta_ras_status ras_status;
+ uint32_t reserved;
+ union ta_ras_cmd_input ras_in_message;
++ struct ta_dbg_msg_list debug_messages;
+ };
+
+ #endif // TL_RAS_IF_H_
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch
new file mode 100644
index 00000000..c91ce0bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch
@@ -0,0 +1,175 @@
+From b314adff2767fe2e6fdbfba1149f29d6aed845de Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Wed, 11 Dec 2019 10:18:55 +0800
+Subject: [PATCH 4726/4736] drm/amdgpu: Added RAS UMC error query support for
+ Arcturus
+
+Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices
+
+Change-Id: I7b106328d24aba5ab93a8f4cddb1635392eecd0f
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 +++-
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 78 ++++++++++++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 3 +-
+ 3 files changed, 74 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index b051ede2fb83..a2d1016ce81a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -692,11 +692,18 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ adev->umc.funcs = &umc_v6_0_funcs;
+ break;
+ case CHIP_VEGA20:
++ adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
++ adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
++ adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
++ adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
++ adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
++ adev->umc.funcs = &umc_v6_1_funcs;
++ break;
+ case CHIP_ARCTURUS:
+ adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
+ adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
+ adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
+- adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;
++ adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
+ adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
+ adev->umc.funcs = &umc_v6_1_funcs;
+ break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 47c4b96b14d1..515eb50cd0f8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -31,6 +31,14 @@
+
+ #define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10
+
++/* UMC 6_1_2 register offsets */
++#define mmUMCCH0_0_EccErrCntSel_ARCT 0x0360
++#define mmUMCCH0_0_EccErrCntSel_ARCT_BASE_IDX 1
++#define mmUMCCH0_0_EccErrCnt_ARCT 0x0361
++#define mmUMCCH0_0_EccErrCnt_ARCT_BASE_IDX 1
++#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT 0x03c2
++#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT_BASE_IDX 1
++
+ /*
+ * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
+ * is the index of 8KB block
+@@ -95,12 +103,25 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
+ uint64_t mc_umc_status;
+ uint32_t mc_umc_status_addr;
+
+- ecc_err_cnt_sel_addr =
+- SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
+- ecc_err_cnt_addr =
+- SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
+- mc_umc_status_addr =
+- SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++ if (adev->asic_type == CHIP_ARCTURUS) {
++ /* UMC 6_1_2 registers */
++
++ ecc_err_cnt_sel_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
++ ecc_err_cnt_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
++ mc_umc_status_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
++ } else {
++ /* UMC 6_1_1 registers */
++
++ ecc_err_cnt_sel_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
++ ecc_err_cnt_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++ mc_umc_status_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++ }
+
+ /* select the lower chip and check the error count */
+ ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
+@@ -141,8 +162,17 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
+ uint64_t mc_umc_status;
+ uint32_t mc_umc_status_addr;
+
+- mc_umc_status_addr =
+- SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++ if (adev->asic_type == CHIP_ARCTURUS) {
++ /* UMC 6_1_2 registers */
++
++ mc_umc_status_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
++ } else {
++ /* UMC 6_1_1 registers */
++
++ mc_umc_status_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++ }
+
+ /* check the MCUMC_STATUS */
+ mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
+@@ -179,8 +209,17 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ uint64_t mc_umc_status, err_addr, retired_page;
+ struct eeprom_table_record *err_rec;
+
+- mc_umc_status_addr =
+- SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++ if (adev->asic_type == CHIP_ARCTURUS) {
++ /* UMC 6_1_2 registers */
++
++ mc_umc_status_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
++ } else {
++ /* UMC 6_1_1 registers */
++
++ mc_umc_status_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++ }
+
+ /* skip error address process if -ENOMEM */
+ if (!err_data->err_addr) {
+@@ -241,10 +280,21 @@ static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
+ uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
+ uint32_t ecc_err_cnt_addr;
+
+- ecc_err_cnt_sel_addr =
+- SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
+- ecc_err_cnt_addr =
+- SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++ if (adev->asic_type == CHIP_ARCTURUS) {
++ /* UMC 6_1_2 registers */
++
++ ecc_err_cnt_sel_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
++ ecc_err_cnt_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
++ } else {
++ /* UMC 6_1_1 registers */
++
++ ecc_err_cnt_sel_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
++ ecc_err_cnt_addr =
++ SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++ }
+
+ /* select the lower chip and check the error count */
+ ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+index dab9cbd292c5..0ce1d323cfdd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+@@ -35,7 +35,8 @@
+ /* total channel instances in one umc block */
+ #define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
+ /* UMC regiser per channel offset */
+-#define UMC_V6_1_PER_CHANNEL_OFFSET 0x800
++#define UMC_V6_1_PER_CHANNEL_OFFSET_VG20 0x800
++#define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT 0x400
+
+ /* EccErrCnt max value */
+ #define UMC_V6_1_CE_CNT_MAX 0xffff
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch
new file mode 100644
index 00000000..53191b48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch
@@ -0,0 +1,42 @@
+From 96860e79942a5f30e0234e04755c69cb6b7ea160 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 6 Dec 2019 11:30:45 +0800
+Subject: [PATCH 4727/4736] drm/amd/powerplay: clear VBIOS scratchs on baco
+ exit V2
+
+This is needed for coming asic init on performing gpu reset.
+
+V2: use non-asic specific programing way
+
+Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index d65187993ef9..83113cb2524c 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1675,10 +1675,17 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ }
+ } else {
+ ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
++ if (ret)
++ goto out;
++
+ bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
+ BIF_DOORBELL_INT_CNTL,
+ DOORBELL_INTERRUPT_DISABLE, 0);
+ WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++
++ /* clear vbios scratch 6 and 7 for coming asic reinit */
++ WREG32(adev->bios_scratch_reg_offset + 6, 0);
++ WREG32(adev->bios_scratch_reg_offset + 7, 0);
+ }
+ if (ret)
+ goto out;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch
new file mode 100644
index 00000000..b57c928e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch
@@ -0,0 +1,58 @@
+From 8dcca48dd79c24e8c92a42282025116ca5205299 Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 13:35:18 +0800
+Subject: [PATCH 4728/4736] drm/amd/powerplay: implement interface to retrieve
+ gpu temperature for renoir
+
+add sensor interface of get gpu temperature for debugfs.
+
+Change-Id: I2499b6652fad6d5d776b6ed4cd5157636583ed39
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index c982f69065ae..be3c996728b1 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -412,6 +412,24 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ return ret;
+ }
+
++static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
++{
++ int ret = 0;
++ SmuMetrics_t metrics;
++
++ if (!value)
++ return -EINVAL;
++
++ ret = renoir_get_metrics_table(smu, &metrics);
++ if (ret)
++ return ret;
++
++ *value = (metrics.GfxTemperature / 100) *
++ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++
++ return 0;
++}
++
+ static int renoir_get_current_activity_percent(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ uint32_t *value)
+@@ -767,6 +785,10 @@ static int renoir_read_sensor(struct smu_context *smu,
+ ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
+ *size = 4;
+ break;
++ case AMDGPU_PP_SENSOR_GPU_TEMP:
++ ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
++ *size = 4;
++ break;
+ default:
+ ret = smu_v12_0_read_sensor(smu, sensor, data, size);
+ }
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch
new file mode 100644
index 00000000..d2902008
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch
@@ -0,0 +1,169 @@
+From dd90194758a70456d1de08bd83f6d4fdfd682e44 Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 15:17:38 +0800
+Subject: [PATCH 4729/4736] drm/amd/powerplay: implement interface to retrieve
+ clock freq for renoir
+
+implement smu12 get_clk_freq interface to get clock frequency like
+MCLK/SCLK.
+
+Change-Id: I2481d649811c15cd2d8e2741242b2928a32413fc
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 4 ++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 49 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 20 ++++++++
+ 3 files changed, 73 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 922973b7e29f..ad68a5623033 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -75,6 +75,10 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu);
+
+ int smu_v12_0_populate_smc_tables(struct smu_context *smu);
+
++int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
++ enum smu_clk_type clk_id,
++ uint32_t *value);
++
+ int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *min, uint32_t *max);
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index be3c996728b1..861445f66e3e 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -31,6 +31,9 @@
+ #include "renoir_ppt.h"
+
+
++#define CLK_MAP(clk, index) \
++ [SMU_##clk] = {1, (index)}
++
+ #define MSG_MAP(msg, index) \
+ [SMU_MSG_##msg] = {1, (index)}
+
+@@ -104,6 +107,14 @@ static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] =
+ MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq),
+ };
+
++static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = {
++ CLK_MAP(GFXCLK, CLOCK_GFXCLK),
++ CLK_MAP(SCLK, CLOCK_GFXCLK),
++ CLK_MAP(SOCCLK, CLOCK_SOCCLK),
++ CLK_MAP(UCLK, CLOCK_UMCCLK),
++ CLK_MAP(MCLK, CLOCK_UMCCLK),
++};
++
+ static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
+ TAB_MAP_VALID(WATERMARKS),
+ TAB_MAP_INVALID(CUSTOM_DPM),
+@@ -125,6 +136,21 @@ static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ return mapping.map_to;
+ }
+
++static int renoir_get_smu_clk_index(struct smu_context *smc, uint32_t index)
++{
++ struct smu_12_0_cmn2aisc_mapping mapping;
++
++ if (index >= SMU_CLK_COUNT)
++ return -EINVAL;
++
++ mapping = renoir_clk_map[index];
++ if (!(mapping.valid_mapping)) {
++ return -EINVAL;
++ }
++
++ return mapping.map_to;
++}
++
+ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ {
+ struct smu_12_0_cmn2aisc_mapping mapping;
+@@ -352,6 +378,26 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+ return ret;
+ }
+
++static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
++ enum smu_clk_type clk_type,
++ uint32_t *value)
++{
++ int ret = 0, clk_id = 0;
++ SmuMetrics_t metrics;
++
++ ret = renoir_get_metrics_table(smu, &metrics);
++ if (ret)
++ return ret;
++
++ clk_id = smu_clk_get_index(smu, clk_type);
++ if (clk_id < 0)
++ return clk_id;
++
++ *value = metrics.ClockFrequency[clk_id];
++
++ return ret;
++}
++
+ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ {
+ int ret = 0, i = 0;
+@@ -799,6 +845,7 @@ static int renoir_read_sensor(struct smu_context *smu,
+
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_smu_msg_index = renoir_get_smu_msg_index,
++ .get_smu_clk_index = renoir_get_smu_clk_index,
+ .get_smu_table_index = renoir_get_smu_table_index,
+ .tables_init = renoir_tables_init,
+ .set_power_state = NULL,
+@@ -807,6 +854,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_current_power_state = renoir_get_current_power_state,
+ .dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
+ .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
++ .get_current_clk_freq_by_table = renoir_get_current_clk_freq_by_table,
+ .force_dpm_limit_value = renoir_force_dpm_limit_value,
+ .unforce_dpm_levels = renoir_unforce_dpm_levels,
+ .get_workload_type = renoir_get_workload_type,
+@@ -830,6 +878,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .init_smc_tables = smu_v12_0_init_smc_tables,
+ .fini_smc_tables = smu_v12_0_fini_smc_tables,
+ .populate_smc_tables = smu_v12_0_populate_smc_tables,
++ .get_current_clk_freq = smu_v12_0_get_current_clk_freq,
+ .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ .mode2_reset = smu_v12_0_mode2_reset,
+ .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 951aa4570a04..0e10cec5e9c3 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -330,6 +330,26 @@ int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+ }
+
++int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
++ enum smu_clk_type clk_id,
++ uint32_t *value)
++{
++ int ret = 0;
++ uint32_t freq = 0;
++
++ if (clk_id >= SMU_CLK_COUNT || !value)
++ return -EINVAL;
++
++ ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
++ if (ret)
++ return ret;
++
++ freq *= 100;
++ *value = freq;
++
++ return ret;
++}
++
+ int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ uint32_t *min, uint32_t *max)
+ {
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch
new file mode 100644
index 00000000..6156d4fe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch
@@ -0,0 +1,86 @@
+From 54649e5391dfd485199180fea93fbd8ba2165421 Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 16:16:30 +0800
+Subject: [PATCH 4730/4736] drm/amd/powerplay: implement the get_enabled_mask
+ callback for smu12
+
+implement sensor interface of feature mask for debugfs.
+
+Change-Id: Ia085aab4c82b978e1e8c8ddc3ca6278b9dec8005
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 ++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 29 +++++++++++++++++++
+ 3 files changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index ad68a5623033..3f1cd06e273c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -75,6 +75,9 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu);
+
+ int smu_v12_0_populate_smc_tables(struct smu_context *smu);
+
++int smu_v12_0_get_enabled_mask(struct smu_context *smu,
++ uint32_t *feature_mask, uint32_t num);
++
+ int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
+ enum smu_clk_type clk_id,
+ uint32_t *value);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 861445f66e3e..5fdfbf5a1ed5 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -878,6 +878,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ .init_smc_tables = smu_v12_0_init_smc_tables,
+ .fini_smc_tables = smu_v12_0_fini_smc_tables,
+ .populate_smc_tables = smu_v12_0_populate_smc_tables,
++ .get_enabled_mask = smu_v12_0_get_enabled_mask,
+ .get_current_clk_freq = smu_v12_0_get_current_clk_freq,
+ .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ .mode2_reset = smu_v12_0_mode2_reset,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 0e10cec5e9c3..2ac7f2f231b6 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -330,6 +330,35 @@ int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+ }
+
++int smu_v12_0_get_enabled_mask(struct smu_context *smu,
++ uint32_t *feature_mask, uint32_t num)
++{
++ uint32_t feature_mask_high = 0, feature_mask_low = 0;
++ int ret = 0;
++
++ if (!feature_mask || num < 2)
++ return -EINVAL;
++
++ ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
++ if (ret)
++ return ret;
++ ret = smu_read_smc_arg(smu, &feature_mask_high);
++ if (ret)
++ return ret;
++
++ ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
++ if (ret)
++ return ret;
++ ret = smu_read_smc_arg(smu, &feature_mask_low);
++ if (ret)
++ return ret;
++
++ feature_mask[0] = feature_mask_low;
++ feature_mask[1] = feature_mask_high;
++
++ return ret;
++}
++
+ int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
+ enum smu_clk_type clk_id,
+ uint32_t *value)
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch
new file mode 100644
index 00000000..24f2c366
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch
@@ -0,0 +1,33 @@
+From d56aca934ff8f012a2aa4ec00575975a22e97d2e Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 17:01:21 +0800
+Subject: [PATCH 4731/4736] drm/amd/powerplay: correct the value retrieved
+ through GPU_LOAD sensor interface
+
+the unit of variable AverageGfxActivity defined in smu12 metrics
+struct is centi, so the retrieved value should be divided by 100 before
+return.
+
+Change-Id: Ia7873597977cb5479b015d632ab24a7aa20a1cfb
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 5fdfbf5a1ed5..0d8ea56731e4 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -492,7 +492,7 @@ static int renoir_get_current_activity_percent(struct smu_context *smu,
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+- *value = metrics.AverageGfxActivity;
++ *value = metrics.AverageGfxActivity / 100;
+ break;
+ default:
+ pr_err("Invalid sensor for retrieving clock activity\n");
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch
new file mode 100644
index 00000000..803f26ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch
@@ -0,0 +1,51 @@
+From 632865701bdeaa26154bbd51bb351d73e7df5370 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Wed, 11 Dec 2019 17:30:26 +0800
+Subject: [PATCH 4732/4736] drm/amdgpu: enable gfxoff feature for navi10 asic
+
+enable gfxoff feature for some navi10 asics
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ed630d37c32c..6b8f21574c7c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -605,11 +605,29 @@ static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
+ le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
+ }
+
++static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
++{
++ bool ret = false;
++
++ switch (adev->pdev->revision) {
++ case 0xc2:
++ case 0xc3:
++ ret = true;
++ break;
++ default:
++ ret = false;
++ break;
++ }
++
++ return ret ;
++}
++
+ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
+ {
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+- adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
++ if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
++ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ break;
+ default:
+ break;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
new file mode 100644
index 00000000..d541ea59
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
@@ -0,0 +1,27 @@
+From 62eb0590d363fe0eddf856e41fc7be7fe2e95828 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 10:43:07 +0800
+Subject: [PATCH 4733/4736] drm/amdgpu/gfx10: update gfx golden settings
+
+add registers: mmSPI_CONFIG_CNTL
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 6b8f21574c7c..2eb18f41a8fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -114,6 +114,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..3e86dd28
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,29 @@
+From 2b3d2a997a2ed76f04e518975153278200274a28 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 10:52:14 +0800
+Subject: [PATCH 4734/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi14
+
+add registers: mmSPI_CONFIG_CNTL
+
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 2eb18f41a8fc..2b91e542a778 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -160,6 +160,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070105),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
new file mode 100644
index 00000000..90b742b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
@@ -0,0 +1,32 @@
+From ff2ef41fc95bb1da4878b2f8cfd3f9cfc79560b2 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 19:55:49 +0800
+Subject: [PATCH 4735/4736] drm/amdgpu/gfx10: update gfx golden settings
+
+add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2
+
+Change-Id: I23dabb0e706af0b5376f9749200832e894944eca
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 2b91e542a778..443d7277162f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -110,8 +110,10 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..586063da
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,33 @@
+From 54482cb8cb5014d349c5cf5df33dedda7b134392 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 19:57:43 +0800
+Subject: [PATCH 4736/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi14
+
+add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2
+
+Change-Id: I1fc3fb481b2d9edc482a32497242a8be6cd6b8d7
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 443d7277162f..cfa2c3d81d87 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -158,8 +158,10 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070105),
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc
index e51bfa5d..9e28dba7 100755
--- a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc
@@ -4100,3 +4100,638 @@ patch 4099-Removing-the-AMDGPU-VERSION-print.patch
patch 4100-drm-amdgpu-enable-VCN-DPG-on-Raven-and-Raven2.patch
patch 4101-drm-amd-amdkfd-This-patch-does-not-initialize-kfd-fo.patch
patch 4102-drm-amd-display-Fixes-the-unigine-heaven-hang-when.patch
+patch 4103-modifying-link-and-led-state-with-respect-to-cable-c.patch
+patch 4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch
+patch 4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch
+patch 4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch
+patch 4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch
+patch 4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch
+patch 4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch
+patch 4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch
+patch 4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch
+patch 4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch
+patch 4113-drm-amdgpu-fix-memory-leak.patch
+patch 4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch
+patch 4115-drm-Add-link-training-repeaters-addresses.patch
+patch 4116-drm-amdkfd-update-for-drmP.h-removal.patch
+patch 4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch
+patch 4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch
+patch 4119-drm-amd-display-Use-swap-where-appropriate.patch
+patch 4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch
+patch 4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch
+patch 4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch
+patch 4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch
+patch 4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch
+patch 4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch
+patch 4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch
+patch 4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch
+patch 4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch
+patch 4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch
+patch 4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch
+patch 4131-drm-amdgpu-fix-potential-VM-faults.patch
+patch 4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch
+patch 4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch
+patch 4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch
+patch 4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch
+patch 4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch
+patch 4137-drm-amd-display-change-PP_SM-defs-to-8.patch
+patch 4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch
+patch 4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch
+patch 4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch
+patch 4141-drm-amdgpu-set-debug-register-values-at-init-time.patch
+patch 4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch
+patch 4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch
+patch 4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch
+patch 4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch
+patch 4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch
+patch 4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch
+patch 4148-drm-amdgpu-remove-in_baco_reset-hack.patch
+patch 4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch
+patch 4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch
+patch 4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch
+patch 4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch
+patch 4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch
+patch 4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
+patch 4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch
+patch 4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch
+patch 4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch
+patch 4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch
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+patch 4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch
+patch 4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch
+patch 4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch
+patch 4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch
+patch 4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch
+patch 4721-drm-amdgpu-display-add-fallthrough-comment.patch
+patch 4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch
+patch 4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch
+patch 4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch
+patch 4725-drm-amdgpu-Add-RAS-dbg-print-support.patch
+patch 4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch
+patch 4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch
+patch 4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch
+patch 4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch
+patch 4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch
+patch 4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch
+patch 4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch
+patch 4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
+patch 4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
+patch 4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
+patch 4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
+