diff options
86 files changed, 7568 insertions, 7 deletions
diff --git a/common/conf/machine/include/amd-common-configurations.inc b/common/conf/machine/include/amd-common-configurations.inc index 13dcce64..b6d52110 100644 --- a/common/conf/machine/include/amd-common-configurations.inc +++ b/common/conf/machine/include/amd-common-configurations.inc @@ -77,6 +77,11 @@ do_image_wic[depends] += "${IMAGE_BASENAME}:do_bootimg" IMAGE_OVERHEAD_FACTOR = "1.1" +IOT_PACKAGES_mel ?= "packagegroup-xmpp \ + packagegroup-mqtt \ + packagegroup-ble \ + packagegroup-http-restful" + MACHINE_FEATURES_append_amdgpu := " ${@bb.utils.contains("EXTRA_IMAGE_FEATURES", "graphics", "x11", "", d)}" MACHINE_FEATURES_append_radeon := " ${@bb.utils.contains("EXTRA_IMAGE_FEATURES", "graphics", "x11", "", d)}" diff --git a/common/recipes-core/systemd/files/0001-dissect-Don-t-count-RPMB-and-boot-partitions-8609.patch b/common/recipes-core/systemd/files/0001-dissect-Don-t-count-RPMB-and-boot-partitions-8609.patch new file mode 100644 index 00000000..ed50663e --- /dev/null +++ b/common/recipes-core/systemd/files/0001-dissect-Don-t-count-RPMB-and-boot-partitions-8609.patch @@ -0,0 +1,85 @@ +From d6586055923f0b04df64b197f213804681c8200b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jo=C3=A3o=20Paulo=20Rechi=20Vita?= <jprvita@gmail.com> +Date: Tue, 3 Apr 2018 05:51:18 -0700 +Subject: [PATCH] dissect: Don't count RPMB and boot partitions (#8609) + +Filter-out RPMB partitions and boot partitions from MMC devices when +counting partitions enumerated by the kernel. Also factor out the now +duplicated code into a separate function. + +This complement the previous fixes to the problem reported in +https://github.com/systemd/systemd/issues/5806 +--- + src/shared/dissect-image.c | 34 ++++++++++++++++++++++++++-------- + 1 file changed, 26 insertions(+), 8 deletions(-) + +diff --git a/src/shared/dissect-image.c b/src/shared/dissect-image.c +index 86114e3dd1..c74fcb4db0 100644 +--- a/src/shared/dissect-image.c ++++ b/src/shared/dissect-image.c +@@ -108,7 +108,20 @@ not_found: + #endif + } + +-int dissect_image(int fd, const void *root_hash, size_t root_hash_size, DissectImageFlags flags, DissectedImage **ret) { ++/* Detect RPMB and Boot partitions, which are not listed by blkid. ++ * See https://github.com/systemd/systemd/issues/5806. */ ++static bool device_is_mmc_special_partition(struct udev_device *d) { ++ const char *sysname = udev_device_get_sysname(d); ++ return (sysname && startswith(sysname, "mmcblk") && ++ (endswith(sysname, "rpmb") || endswith(sysname, "boot0") || endswith(sysname, "boot1"))); ++} ++ ++int dissect_image( ++ int fd, ++ const void *root_hash, ++ size_t root_hash_size, ++ DissectImageFlags flags, ++ DissectedImage **ret) { + + #if HAVE_BLKID + sd_id128_t root_uuid = SD_ID128_NULL, verity_uuid = SD_ID128_NULL; +@@ -277,8 +290,17 @@ int dissect_image(int fd, const void *root_hash, size_t root_hash_size, DissectI + /* Count the partitions enumerated by the kernel */ + n = 0; + first = udev_enumerate_get_list_entry(e); +- udev_list_entry_foreach(item, first) ++ udev_list_entry_foreach(item, first) { ++ _cleanup_udev_device_unref_ struct udev_device *q; ++ ++ q = udev_device_new_from_syspath(udev, udev_list_entry_get_name(item)); ++ if (!q) ++ return -errno; ++ ++ if (device_is_mmc_special_partition(q)) ++ continue; + n++; ++ } + + /* Count the partitions enumerated by blkid */ + z = blkid_partlist_numof_partitions(pl); +@@ -337,7 +359,7 @@ int dissect_image(int fd, const void *root_hash, size_t root_hash_size, DissectI + _cleanup_udev_device_unref_ struct udev_device *q; + unsigned long long pflags; + blkid_partition pp; +- const char *node, *sysname; ++ const char *node; + dev_t qn; + int nr; + +@@ -352,11 +374,7 @@ int dissect_image(int fd, const void *root_hash, size_t root_hash_size, DissectI + if (st.st_rdev == qn) + continue; + +- /* Filter out weird MMC RPMB partitions, which cannot reasonably be read, see +- * https://github.com/systemd/systemd/issues/5806 */ +- sysname = udev_device_get_sysname(q); +- if (sysname && startswith(sysname, "mmcblk") && +- (endswith(sysname, "rpmb") || endswith(sysname, "boot0" ) || endswith(sysname, "boot1"))) ++ if (device_is_mmc_special_partition(q)) + continue; + + node = udev_device_get_devnode(q); +-- +2.11.1 + diff --git a/common/recipes-core/systemd/systemd_%.bbappend b/common/recipes-core/systemd/systemd_%.bbappend index 2198b747..182d7b56 100644 --- a/common/recipes-core/systemd/systemd_%.bbappend +++ b/common/recipes-core/systemd/systemd_%.bbappend @@ -1,3 +1,6 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" +SRC_URI_append_amd = " file://0001-dissect-Don-t-count-RPMB-and-boot-partitions-8609.patch" + pkg_postinst_udev-hwdb_amd () { } pkg_postinst_ontarget_udev-hwdb_amd () { diff --git a/common/recipes-graphics/drm/libdrm_git.bb b/common/recipes-graphics/drm/libdrm_git.bb index 4c775af7..cbca6b72 100644 --- a/common/recipes-graphics/drm/libdrm_git.bb +++ b/common/recipes-graphics/drm/libdrm_git.bb @@ -9,7 +9,8 @@ SECTION = "x11/base" LICENSE = "MIT" LIC_FILES_CHKSUM = "file://xf86drm.c;beginline=9;endline=32;md5=c8a3b961af7667c530816761e949dc71" PROVIDES = "drm" -PV = "git" +DRM_VERSION = "2.4.91" +PV = "${DRM_VERSION}+git${SRCPV}" inherit autotools pkgconfig diff --git a/meta-r1000/recipes-core/llvm/files/0002-llvm-allow-env-override-of-exe-path.patch b/meta-r1000/recipes-core/llvm/files/0002-llvm-allow-env-override-of-exe-path.patch new file mode 100644 index 00000000..7b490a81 --- /dev/null +++ b/meta-r1000/recipes-core/llvm/files/0002-llvm-allow-env-override-of-exe-path.patch @@ -0,0 +1,35 @@ +From ac39269933a9011567722e69c02734beaa1191b3 Mon Sep 17 00:00:00 2001 +From: Martin Kelly <mkelly@xevo.com> +Date: Fri, 19 May 2017 00:22:57 -0700 +Subject: [PATCH] llvm: allow env override of exe path + +When using a native llvm-config from inside a sysroot, we need llvm-config to +return the libraries, include directories, etc. from inside the sysroot rather +than from the native sysroot. Thus provide an env override for calling +llvm-config from a target sysroot. + +Signed-off-by: Martin Kelly <mkelly@xevo.com> +Signed-off-by: Khem Raj <raj.khem@gmail.com> + +--- + tools/llvm-config/llvm-config.cpp | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/tools/llvm-config/llvm-config.cpp b/tools/llvm-config/llvm-config.cpp +index 892adc3b9dd..73b6989fa9e 100644 +--- a/tools/llvm-config/llvm-config.cpp ++++ b/tools/llvm-config/llvm-config.cpp +@@ -226,6 +226,13 @@ Typical components:\n\ + + /// Compute the path to the main executable. + std::string GetExecutablePath(const char *Argv0) { ++ // Hack for Yocto: we need to override the root path when we are using ++ // llvm-config from within a target sysroot. ++ const char *Sysroot = std::getenv("YOCTO_ALTERNATE_EXE_PATH"); ++ if (Sysroot != nullptr) { ++ return Sysroot; ++ } ++ + // This just needs to be some symbol in the binary; C++ doesn't + // allow taking the address of ::main however. + void *P = (void *)(intptr_t)GetExecutablePath; diff --git a/meta-r1000/recipes-core/llvm/llvm_git.bbappend b/meta-r1000/recipes-core/llvm/llvm_git.bbappend index 5062b068..1f2c4ffe 100644 --- a/meta-r1000/recipes-core/llvm/llvm_git.bbappend +++ b/meta-r1000/recipes-core/llvm/llvm_git.bbappend @@ -1,3 +1,4 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" LIC_FILES_CHKSUM = "file://LICENSE.TXT;md5=c520ed40e11887bb1d24d86f7f5b1f05" SRCREV = "4a059213dd6f034147e9083c21133dc1b57b3a8a" diff --git a/meta-r1000/recipes-graphics/drm/libdrm_git.bbappend b/meta-r1000/recipes-graphics/drm/libdrm_git.bbappend index 7ac76cd3..d14d9e46 100644 --- a/meta-r1000/recipes-graphics/drm/libdrm_git.bbappend +++ b/meta-r1000/recipes-graphics/drm/libdrm_git.bbappend @@ -1,2 +1,3 @@ SRCREV_r1000 = "5a3bdc7add2f30f7673052376514c91dbcd1b64a" +DRM_VERSION_r1000 = "2.4.96" SRC_URI_remove_r1000 = "file://0001-headers-sync-up-amdgpu_drm.h-with-drm-next.patch" diff --git a/meta-r1000/recipes-graphics/mesa/files/0001-gallium-add-missing-PIPE_CAP_SURFACE_SAMPLE_COUNT-de.patch b/meta-r1000/recipes-graphics/mesa/files/0001-gallium-add-missing-PIPE_CAP_SURFACE_SAMPLE_COUNT-de.patch new file mode 100644 index 00000000..d40aaa98 --- /dev/null +++ b/meta-r1000/recipes-graphics/mesa/files/0001-gallium-add-missing-PIPE_CAP_SURFACE_SAMPLE_COUNT-de.patch @@ -0,0 +1,33 @@ +From ad0ef93a61be1ccd00e3b48bf6913bc2bffb3143 Mon Sep 17 00:00:00 2001 +From: Samuel Pitoiset <samuel.pitoiset@gmail.com> +Date: Fri, 7 Dec 2018 10:08:38 +0100 +Subject: [PATCH] gallium: add missing PIPE_CAP_SURFACE_SAMPLE_COUNT default + value +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Fixes: 2710c40e3c8 ("gallium: Add new PIPE_CAP_SURFACE_SAMPLE_COUNT") +Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> +Tested-by: Michel Dänzer <michel.daenzer@amd.com> +--- + src/gallium/auxiliary/util/u_screen.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/gallium/auxiliary/util/u_screen.c b/src/gallium/auxiliary/util/u_screen.c +index 95d2a7d5701..6ca3992ecd1 100644 +--- a/src/gallium/auxiliary/util/u_screen.c ++++ b/src/gallium/auxiliary/util/u_screen.c +@@ -328,6 +328,9 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen, + case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET: + return 2047; + ++ case PIPE_CAP_SURFACE_SAMPLE_COUNT: ++ return 0; ++ + default: + unreachable("bad PIPE_CAP_*"); + } +-- +2.11.1 + diff --git a/meta-r1000/recipes-graphics/mesa/mesa_git.bbappend b/meta-r1000/recipes-graphics/mesa/mesa_git.bbappend index a2a798fa..e21af4fa 100644 --- a/meta-r1000/recipes-graphics/mesa/mesa_git.bbappend +++ b/meta-r1000/recipes-graphics/mesa/mesa_git.bbappend @@ -1,3 +1,4 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" SRCREV_r1000 = "0144bbdb98f515cce31688fce57d769e7fd82d52" LIC_FILES_CHKSUM_r1000 = "file://docs/license.html;md5=725f991a1cc322aa7a0cd3a2016621c4" PV_r1000 = "19.0.0+git${SRCPV}" @@ -5,12 +6,8 @@ PV_r1000 = "19.0.0+git${SRCPV}" MESA_LLVM_RELEASE_r1000 = "7" SRC_URI_remove_r1000 = "git://anongit.freedesktop.org/mesa/mesa;branch=18.1" -SRC_URI_append_r1000 = " git://anongit.freedesktop.org/mesa/mesa;branch=master" - -# mesa dri drivers fail to load with -O2 -# which is what is used unless debug build -# is enabled. -DEBUG_BUILD = "1" +SRC_URI_append_r1000 = " git://anongit.freedesktop.org/mesa/mesa;branch=master \ + file://0001-gallium-add-missing-PIPE_CAP_SURFACE_SAMPLE_COUNT-de.patch" PACKAGECONFIG_append_r1000 = " dri3" diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5726-amd-i2s-fix-to-the-fage-fault-when-iommu-is-enabled.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5726-amd-i2s-fix-to-the-fage-fault-when-iommu-is-enabled.patch new file mode 100644 index 00000000..28dd5c17 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5726-amd-i2s-fix-to-the-fage-fault-when-iommu-is-enabled.patch @@ -0,0 +1,156 @@ +From 4f19dca18de5c5d3dc374c946f5d42c3e8f3d396 Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Tue, 12 Feb 2019 19:00:21 +0530 +Subject: [PATCH 5726/5758] amd-i2s fix to the fage fault when iommu is enabled + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + sound/soc/amd/raven/acp3x-pcm-dma.c | 27 +++++++++++++++------------ + sound/soc/soc-core.c | 13 +++++++++++-- + 2 files changed, 26 insertions(+), 14 deletions(-) + mode change 100644 => 100755 sound/soc/amd/raven/acp3x-pcm-dma.c + mode change 100644 => 100755 sound/soc/soc-core.c + +diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c +old mode 100644 +new mode 100755 +index 7ed9d0e..3abdf1f +--- a/sound/soc/amd/raven/acp3x-pcm-dma.c ++++ b/sound/soc/amd/raven/acp3x-pcm-dma.c +@@ -22,9 +22,12 @@ + #include <sound/pcm_params.h> + #include <sound/soc.h> + #include <sound/soc-dai.h> ++#include <linux/pci.h> + #include <linux/io.h> + #include "acp3x.h" + ++#define DRV_NAME "acp3x-i2s-audio" ++ + struct i2s_dev_data { + bool tdm_mode; + unsigned int i2s_irq; +@@ -39,7 +42,7 @@ struct i2s_stream_instance { + u16 channels; + u32 xfer_resolution; + u32 val; +- struct page *pg; ++ dma_addr_t dma_addr; + void __iomem *acp3x_base; + }; + +@@ -223,10 +226,10 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id) + static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction) + { + u16 page_idx; +- u64 addr; + u32 low, high, val, acp_fifo_addr; +- struct page *pg = rtd->pg; ++ dma_addr_t addr; + ++ addr = rtd->dma_addr; + /* 8 scratch registers used to map one 64 bit address. + * For 2 pages (4096 * 2 bytes), it will be 16 registers. + */ +@@ -243,7 +246,6 @@ static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction) + + for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) { + /* Load the low address of page int ACP SRAM through SRBM */ +- addr = page_to_phys(pg); + low = lower_32_bits(addr); + high = upper_32_bits(addr); + +@@ -253,7 +255,7 @@ static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction) + + 4); + /* Move to next physically contiguos page */ + val += 8; +- pg++; ++ addr += PAGE_SIZE; + } + + if (direction == SNDRV_PCM_STREAM_PLAYBACK) { +@@ -339,7 +341,6 @@ static int acp3x_dma_hw_params(struct snd_pcm_substream *substream, + int status; + uint64_t size; + struct snd_dma_buffer *dma_buffer; +- struct page *pg; + struct i2s_stream_instance *rtd = substream->runtime->private_data; + + if (rtd == NULL) +@@ -352,9 +353,8 @@ static int acp3x_dma_hw_params(struct snd_pcm_substream *substream, + return status; + + memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); +- pg = virt_to_page(substream->dma_buffer.area); +- if (pg != NULL) { +- rtd->pg = pg; ++ if (substream->dma_buffer.area) { ++ rtd->dma_addr = substream->dma_buffer.addr; + rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT); + config_acp3x_dma(rtd, substream->stream); + status = 0; +@@ -384,9 +384,12 @@ static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_pcm_substream *substream) + + static int acp3x_dma_new(struct snd_soc_pcm_runtime *rtd) + { ++ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, ++ DRV_NAME); ++ struct device *parent = component->dev->parent; + return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, + SNDRV_DMA_TYPE_DEV, +- NULL, MIN_BUFFER, ++ parent, MIN_BUFFER, + MAX_BUFFER); + } + +@@ -611,7 +614,7 @@ static struct snd_soc_dai_driver acp3x_i2s_dai_driver = { + }; + + static const struct snd_soc_component_driver acp3x_i2s_component = { +- .name = "acp3x_i2s", ++ .name = DRV_NAME, + }; + + static int acp3x_audio_probe(struct platform_device *pdev) +@@ -802,4 +805,4 @@ module_platform_driver(acp3x_dma_driver); + MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); + MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver"); + MODULE_LICENSE("GPL v2"); +-MODULE_ALIAS("platform:acp3x-i2s-audio"); ++MODULE_ALIAS("platform:"DRV_NAME); +diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c +old mode 100644 +new mode 100755 +index fee4b0e..719416c +--- a/sound/soc/soc-core.c ++++ b/sound/soc/soc-core.c +@@ -590,14 +590,23 @@ struct snd_soc_component *snd_soc_rtdcom_lookup(struct snd_soc_pcm_runtime *rtd, + { + struct snd_soc_rtdcom_list *rtdcom; + ++ if (!driver_name) ++ return NULL; ++ + for_each_rtdcom(rtd, rtdcom) { +- if ((rtdcom->component->driver->name == driver_name) || +- strcmp(rtdcom->component->driver->name, driver_name) == 0) ++ const char *component_name = rtdcom->component->driver->name; ++ ++ if (!component_name) ++ continue; ++ ++ if ((component_name == driver_name) || ++ strcmp(component_name, driver_name) == 0) + return rtdcom->component; + } + + return NULL; + } ++EXPORT_SYMBOL_GPL(snd_soc_rtdcom_lookup); + + struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card, + const char *dai_link, int stream) +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5727-amd-i2s-dma-pointer-uses-Link-position-counter.This-.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5727-amd-i2s-dma-pointer-uses-Link-position-counter.This-.patch new file mode 100644 index 00000000..3ce63541 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5727-amd-i2s-dma-pointer-uses-Link-position-counter.This-.patch @@ -0,0 +1,117 @@ +From e0c036d4aad50e29f3a2217324e4faf729f59839 Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Tue, 8 Jan 2019 12:05:52 +0530 +Subject: [PATCH 5727/5758] amd-i2s dma pointer uses Link position counter.This + has been changed to Linear position counter and this rectifies underruns. + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + sound/soc/amd/raven/acp3x-pcm-dma.c | 64 ++++++++++++++++++++++++++++++------- + 1 file changed, 53 insertions(+), 11 deletions(-) + +diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c +index 3abdf1f..3bb4ad3 100755 +--- a/sound/soc/amd/raven/acp3x-pcm-dma.c ++++ b/sound/soc/amd/raven/acp3x-pcm-dma.c +@@ -37,12 +37,24 @@ struct i2s_dev_data { + struct snd_pcm_substream *capture_stream; + }; + ++union acp3x_dma_count { ++ struct { ++ u32 low; ++ u32 high; ++ } bcount; ++ u64 bytescount; ++}; ++ ++ + struct i2s_stream_instance { + u16 num_pages; + u16 channels; + u32 xfer_resolution; + u32 val; + dma_addr_t dma_addr; ++ u32 byte_cnt_high_reg_offset; ++ u32 byte_cnt_low_reg_offset; ++ u64 bytescount; + void __iomem *acp3x_base; + }; + +@@ -335,6 +347,25 @@ static int acp3x_dma_open(struct snd_pcm_substream *substream) + return 0; + } + ++static u64 acp_get_byte_count(struct i2s_stream_instance *rtd, int direction) ++{ ++ union acp3x_dma_count byte_count; ++ ++ if (direction == SNDRV_PCM_STREAM_PLAYBACK) { ++ byte_count.bcount.high = rv_readl(rtd->acp3x_base + ++ mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH); ++ byte_count.bcount.low = rv_readl(rtd->acp3x_base + ++ mmACP_BT_TX_LINEARPOSITIONCNTR_LOW); ++ } else { ++ byte_count.bcount.high = rv_readl(rtd->acp3x_base + ++ mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH); ++ byte_count.bcount.low = rv_readl(rtd->acp3x_base + ++ mmACP_BT_RX_LINEARPOSITIONCNTR_LOW); ++ } ++ return byte_count.bytescount; ++} ++ ++ + static int acp3x_dma_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) + { +@@ -366,18 +397,28 @@ static int acp3x_dma_hw_params(struct snd_pcm_substream *substream, + + static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_pcm_substream *substream) + { ++ u64 bytescount = 0; + u32 pos = 0; +- struct i2s_stream_instance *rtd = substream->runtime->private_data; +- +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) +- pos = rv_readl(rtd->acp3x_base + +- mmACP_BT_TX_LINKPOSITIONCNTR); +- else +- pos = rv_readl(rtd->acp3x_base + +- mmACP_BT_RX_LINKPOSITIONCNTR); +- +- if (pos >= MAX_BUFFER) +- pos = 0; ++ u32 buffersize = 0; ++ struct i2s_stream_instance *rtd = ++ substream->runtime->private_data; ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ buffersize = frames_to_bytes(substream->runtime, ++ substream->runtime->buffer_size); ++ bytescount = acp_get_byte_count(rtd, substream->stream); ++ if (bytescount > rtd->bytescount) ++ bytescount -= rtd->bytescount; ++ pos = do_div(bytescount, buffersize); ++ } else { ++ buffersize = frames_to_bytes(substream->runtime, ++ substream->runtime->buffer_size); ++ bytescount = acp_get_byte_count(rtd, substream->stream); ++ if (bytescount > rtd->bytescount) ++ bytescount -= rtd->bytescount; ++ pos = do_div(bytescount, buffersize); ++ } ++ if (pos >= MAX_BUFFER) ++ pos %= buffersize; + + return bytes_to_frames(substream->runtime, pos); + } +@@ -545,6 +586,7 @@ static int acp3x_dai_i2s_trigger(struct snd_pcm_substream *substream, + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ rtd->bytescount = acp_get_byte_count(rtd, substream->stream); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER); + val = val | BIT(0); +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5728-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5728-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch new file mode 100644 index 00000000..e4c306b0 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5728-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch @@ -0,0 +1,50 @@ +From 5a52cf8e775283cd8bb279baa6039e7c168fa1da Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Tue, 22 May 2018 16:26:26 +0200 +Subject: [PATCH 5728/5758] mmc: core: Move calls to ->prepare_hs400_tuning() + closer to mmc code + +Move the calls to ->prepare_hs400_tuning(), from mmc_retune() into +mmc_hs400_to_hs200(), as it better belongs there, rather than being generic +to all type of cards. + +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/core/host.c | 3 --- + drivers/mmc/core/mmc.c | 4 ++++ + 2 files changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c +index ad88deb..4651e9b 100644 +--- a/drivers/mmc/core/host.c ++++ b/drivers/mmc/core/host.c +@@ -148,9 +148,6 @@ int mmc_retune(struct mmc_host *host) + goto out; + + return_to_hs400 = true; +- +- if (host->ops->prepare_hs400_tuning) +- host->ops->prepare_hs400_tuning(host, &host->ios); + } + + err = mmc_execute_tuning(host->card); +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +index 29bba1e..c768d08 100755 +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1283,6 +1283,10 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + + mmc_set_bus_speed(card); + ++ /* Prepare tuning for HS400 mode. */ ++ if (host->ops->prepare_hs400_tuning) ++ host->ops->prepare_hs400_tuning(host, &host->ios); ++ + return 0; + + out_err: +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5729-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5729-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch new file mode 100644 index 00000000..4bf16a6d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5729-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch @@ -0,0 +1,89 @@ +From d6e5823c602272567f80cffdcafbf715192d43fc Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Tue, 12 Feb 2019 19:07:08 +0530 +Subject: [PATCH 5729/5758] mmc: core: more fine-grained hooks for HS400 tuning + +This adds two new HS400 tuning operations: +* hs400_downgrade +* hs400_complete + +These supplement the existing HS400 operation: +* prepare_hs400_tuning + +This is motivated by a requirement of Renesas SDHI for the following: +1. Disabling SCC before selecting to HS if selection of HS400 has occurred. + This can be done in an implementation of prepare_hs400_tuning_downgrade +2. Updating registers after switching to HS400 + This can be done in an implementation of complete_hs400_tuning + +If hs400_downgrade or hs400_complete are not implemented then they are not +called. Thus means there should be no affect for existing drivers as none +implemt these ops. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> + +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + drivers/mmc/core/mmc.c | 11 +++++++++++ + include/linux/mmc/host.h | 7 +++++++ + 2 files changed, 18 insertions(+) + +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +index c768d08..cd3604d 100755 +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1165,6 +1165,11 @@ static int mmc_select_hs400(struct mmc_card *card) + if (!host->ops->set_hs400_dll) { + /* Set host controller to HS timing */ + mmc_set_timing(card->host, MMC_TIMING_MMC_HS); ++ ++ /* Prepare host to downgrade to HS timing */ ++ if (host->ops->hs400_downgrade) ++ host->ops->hs400_downgrade(host); ++ + /* Reduce frequency to HS frequency */ + max_dtr = card->ext_csd.hs_max_dtr; + mmc_set_clock(host, max_dtr); +@@ -1257,6 +1262,9 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + + mmc_set_timing(host, MMC_TIMING_MMC_HS); + ++ if (host->ops->hs400_downgrade) ++ host->ops->hs400_downgrade(host); ++ + err = mmc_switch_status(card); + if (err) + goto out_err; +@@ -1394,6 +1402,9 @@ static int mmc_select_hs400es(struct mmc_card *card) + if (err) + goto out_err; + ++ if (host->ops->hs400_complete) ++ host->ops->hs400_complete(host); ++ + return 0; + + out_err: +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +index b7d5611..ba4af38 100755 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -145,6 +145,13 @@ struct mmc_host_ops { + + /* Prepare HS400 target operating frequency depending host driver */ + int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); ++ ++ /* Prepare for switching from HS400 to HS200 */ ++ void (*hs400_downgrade)(struct mmc_host *host); ++ ++ /* Complete selection of HS400 */ ++ void (*hs400_complete)(struct mmc_host *host); ++ + /* Prepare enhanced strobe depending host driver */ + void (*hs400_enhanced_strobe)(struct mmc_host *host, + struct mmc_ios *ios); +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5730-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5730-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch new file mode 100644 index 00000000..9de66ac8 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5730-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch @@ -0,0 +1,91 @@ +From 7b0182dd9999843427374c2a0ae7d009786d16d6 Mon Sep 17 00:00:00 2001 +From: "ernest.zhang" <ernest.zhang@bayhubtech.com> +Date: Mon, 16 Jul 2018 14:26:53 +0800 +Subject: [PATCH 5730/5758] mmc: sdhci: Export sdhci tuning function symbol + +Export sdhci tuning function symbols which are used by other SD Host +controller driver modules. + +Signed-off-by: ernest.zhang <ernest.zhang@bayhubtech.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 12 ++++++++---- + drivers/mmc/host/sdhci.h | 5 +++++ + 2 files changed, 13 insertions(+), 4 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 8837d45..53f6b2a 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -2041,7 +2041,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) + return 0; + } + +-static void sdhci_start_tuning(struct sdhci_host *host) ++void sdhci_start_tuning(struct sdhci_host *host) + { + u16 ctrl; + +@@ -2064,14 +2064,16 @@ static void sdhci_start_tuning(struct sdhci_host *host) + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); + } ++EXPORT_SYMBOL_GPL(sdhci_start_tuning); + +-static void sdhci_end_tuning(struct sdhci_host *host) ++void sdhci_end_tuning(struct sdhci_host *host) + { + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + } ++EXPORT_SYMBOL_GPL(sdhci_end_tuning); + +-static void sdhci_reset_tuning(struct sdhci_host *host) ++void sdhci_reset_tuning(struct sdhci_host *host) + { + u16 ctrl; + +@@ -2080,6 +2082,7 @@ static void sdhci_reset_tuning(struct sdhci_host *host) + ctrl &= ~SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } ++EXPORT_SYMBOL_GPL(sdhci_reset_tuning); + + static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) + { +@@ -2100,7 +2103,7 @@ static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) + * interrupt setup is different to other commands and there is no timeout + * interrupt so special handling is needed. + */ +-static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) ++void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) + { + struct mmc_host *mmc = host->mmc; + struct mmc_command cmd = {}; +@@ -2150,6 +2153,7 @@ static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) + msecs_to_jiffies(50)); + + } ++EXPORT_SYMBOL_GPL(sdhci_send_tuning); + + static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) + { +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index b5fd294..983b7df 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -735,4 +735,9 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, + + void sdhci_dumpregs(struct sdhci_host *host); + ++void sdhci_start_tuning(struct sdhci_host *host); ++void sdhci_end_tuning(struct sdhci_host *host); ++void sdhci_reset_tuning(struct sdhci_host *host); ++void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); ++ + #endif /* __SDHCI_HW_H */ +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5731-mmc-sdhci-Export-sdhci_request.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5731-mmc-sdhci-Export-sdhci_request.patch new file mode 100644 index 00000000..a41cb1a2 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5731-mmc-sdhci-Export-sdhci_request.patch @@ -0,0 +1,53 @@ +From 344895043e849dddc9ab272172c7b867227c32ba Mon Sep 17 00:00:00 2001 +From: Aapo Vienamo <avienamo@nvidia.com> +Date: Mon, 20 Aug 2018 12:23:32 +0300 +Subject: [PATCH 5731/5758] mmc: sdhci: Export sdhci_request() + +Allow SDHCI drivers to hook code before and after sdhci_request() by +making it externally visible. + +Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 3 ++- + drivers/mmc/host/sdhci.h | 1 + + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 53f6b2a..677815e 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1558,7 +1558,7 @@ EXPORT_SYMBOL_GPL(sdhci_set_power); + * * + \*****************************************************************************/ + +-static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) ++void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) + { + struct sdhci_host *host; + int present; +@@ -1597,6 +1597,7 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); + } ++EXPORT_SYMBOL_GPL(sdhci_request); + + void sdhci_set_bus_width(struct sdhci_host *host, int width) + { +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 983b7df..ba5227c 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -711,6 +711,7 @@ void sdhci_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd); + void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, + unsigned short vdd); ++void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); + void sdhci_set_bus_width(struct sdhci_host *host, int width); + void sdhci_reset(struct sdhci_host *host, u8 mask); + void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5732-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5732-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch new file mode 100644 index 00000000..f2c83301 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5732-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch @@ -0,0 +1,77 @@ +From 3eeaf018781d1c0203d25400b12041c3238768d3 Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Wed, 16 Jan 2019 11:23:47 +0530 +Subject: [PATCH 5732/5758] mmc: sdhci: add adma_table_cnt member to struct + sdhci_host + +This patch adds adma_table_cnt member to struct sdhci_host to give more +flexibility to drivers to control the ADMA table count. + +Default value of adma_table_cnt is set to (SDHCI_MAX_SEGS * 2 + 1). + +Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 17 +++++++++-------- + drivers/mmc/host/sdhci.h | 3 +++ + 2 files changed, 12 insertions(+), 8 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 677815e..f4b7c6e 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -3237,6 +3237,13 @@ struct sdhci_host *sdhci_alloc_host(struct device *dev, + + host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG; + ++ /* ++ * The DMA table descriptor count is calculated as the maximum ++ * number of segments times 2, to allow for an alignment ++ * descriptor for each segment, plus 1 for a nop end descriptor. ++ */ ++ host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1; ++ + return host; + } + +@@ -3488,18 +3495,12 @@ int sdhci_setup_host(struct sdhci_host *host) + dma_addr_t dma; + void *buf; + +- /* +- * The DMA descriptor table size is calculated as the maximum +- * number of segments times 2, to allow for an alignment +- * descriptor for each segment, plus 1 for a nop end descriptor, +- * all multipled by the descriptor size. +- */ + if (host->flags & SDHCI_USE_64_BIT_DMA) { +- host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * ++ host->adma_table_sz = host->adma_table_cnt * + SDHCI_ADMA2_64_DESC_SZ; + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + } else { +- host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * ++ host->adma_table_sz = host->adma_table_cnt * + SDHCI_ADMA2_32_DESC_SZ; + host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; + } +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index ba5227c..f72697d 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -550,6 +550,9 @@ struct sdhci_host { + /* Host SDMA buffer boundary. */ + u32 sdma_boundary; + ++ /* Host ADMA table count */ ++ u32 adma_table_cnt; ++ + unsigned long private[0] ____cacheline_aligned; + }; + +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5733-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5733-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch new file mode 100644 index 00000000..06720733 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5733-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch @@ -0,0 +1,128 @@ +From 8411fdf67af6dc346f3b47008b48e978a4832213 Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang <Jisheng.Zhang@synaptics.com> +Date: Tue, 28 Aug 2018 17:47:23 +0800 +Subject: [PATCH 5733/5758] mmc: sdhci: introduce adma_write_desc() hook to + struct sdhci_ops + +Add this hook so that it can be overridden with driver specific +implementations. We also let the original sdhci_adma_write_desc() +accept &desc so that the function can set its new value. Then export +the function so that it could be reused by driver's specific +implementations. + +Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 37 +++++++++++++++++++++++-------------- + drivers/mmc/host/sdhci.h | 4 ++++ + 2 files changed, 27 insertions(+), 14 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index f4b7c6e..05cd6c0 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -554,10 +554,10 @@ static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) + local_irq_restore(*flags); + } + +-static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, +- dma_addr_t addr, int len, unsigned cmd) ++void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, ++ dma_addr_t addr, int len, unsigned int cmd) + { +- struct sdhci_adma2_64_desc *dma_desc = desc; ++ struct sdhci_adma2_64_desc *dma_desc = *desc; + + /* 32-bit and 64-bit descriptors have these members in same position */ + dma_desc->cmd = cpu_to_le16(cmd); +@@ -566,6 +566,19 @@ static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, + + if (host->flags & SDHCI_USE_64_BIT_DMA) + dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); ++ ++ *desc += host->desc_sz; ++} ++EXPORT_SYMBOL_GPL(sdhci_adma_write_desc); ++ ++static inline void __sdhci_adma_write_desc(struct sdhci_host *host, ++ void **desc, dma_addr_t addr, ++ int len, unsigned int cmd) ++{ ++ if (host->ops->adma_write_desc) ++ host->ops->adma_write_desc(host, desc, addr, len, cmd); ++ ++ sdhci_adma_write_desc(host, desc, addr, len, cmd); + } + + static void sdhci_adma_mark_end(void *desc) +@@ -618,28 +631,24 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, + } + + /* tran, valid */ +- sdhci_adma_write_desc(host, desc, align_addr, offset, +- ADMA2_TRAN_VALID); ++ __sdhci_adma_write_desc(host, &desc, align_addr, ++ offset, ADMA2_TRAN_VALID); + + BUG_ON(offset > 65536); + + align += SDHCI_ADMA2_ALIGN; + align_addr += SDHCI_ADMA2_ALIGN; + +- desc += host->desc_sz; +- + addr += offset; + len -= offset; + } + + BUG_ON(len > 65536); + +- if (len) { +- /* tran, valid */ +- sdhci_adma_write_desc(host, desc, addr, len, +- ADMA2_TRAN_VALID); +- desc += host->desc_sz; +- } ++ /* tran, valid */ ++ if (len) ++ __sdhci_adma_write_desc(host, &desc, addr, len, ++ ADMA2_TRAN_VALID); + + /* + * If this triggers then we have a calculation bug +@@ -656,7 +665,7 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, + } + } else { + /* Add a terminating entry - nop, end, valid */ +- sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); ++ __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID); + } + } + +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index f72697d..bb57fa0 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -592,6 +592,8 @@ struct sdhci_ops { + void (*adma_workaround)(struct sdhci_host *host, u32 intmask); + void (*card_event)(struct sdhci_host *host); + void (*voltage_switch)(struct sdhci_host *host); ++ void (*adma_write_desc)(struct sdhci_host *host, void **desc, ++ dma_addr_t addr, int len, unsigned int cmd); + }; + + #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS +@@ -723,6 +725,8 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); + int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios); + void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); ++void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, ++ dma_addr_t addr, int len, unsigned int cmd); + + #ifdef CONFIG_PM + int sdhci_suspend_host(struct sdhci_host *host); +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5734-mmc-sdhci-Add-version-V4-definition.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5734-mmc-sdhci-Add-version-V4-definition.patch new file mode 100644 index 00000000..4a400142 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5734-mmc-sdhci-Add-version-V4-definition.patch @@ -0,0 +1,46 @@ +From 6850c5d0e288e198475c2ad18d393065a49bbd29 Mon Sep 17 00:00:00 2001 +From: Chunyan Zhang <zhang.chunyan@linaro.org> +Date: Thu, 30 Aug 2018 16:21:37 +0800 +Subject: [PATCH 5734/5758] mmc: sdhci: Add version V4 definition + +Added definitions for v400, v410, v420. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 2 +- + drivers/mmc/host/sdhci.h | 3 +++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 05cd6c0..e698218 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -3443,7 +3443,7 @@ int sdhci_setup_host(struct sdhci_host *host) + + override_timeout_clk = host->timeout_clk; + +- if (host->version > SDHCI_SPEC_300) { ++ if (host->version > SDHCI_SPEC_420) { + pr_err("%s: Unknown controller version (%d). You may experience problems.\n", + mmc_hostname(mmc), host->version); + } +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index bb57fa0..6bafe26 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -270,6 +270,9 @@ + #define SDHCI_SPEC_100 0 + #define SDHCI_SPEC_200 1 + #define SDHCI_SPEC_300 2 ++#define SDHCI_SPEC_400 3 ++#define SDHCI_SPEC_410 4 ++#define SDHCI_SPEC_420 5 + + /* + * End of controller registers. +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5735-mmc-sdhci-Add-sd-host-v4-mode.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5735-mmc-sdhci-Add-sd-host-v4-mode.patch new file mode 100644 index 00000000..bcf7fb09 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5735-mmc-sdhci-Add-sd-host-v4-mode.patch @@ -0,0 +1,105 @@ +From 8ba06e5eab7b0da6a1f5083d80cbcbde066556ff Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Wed, 16 Jan 2019 11:47:52 +0530 +Subject: [PATCH 5735/5758] mmc: sdhci: Add sd host v4 mode + +For SD host controller version 4.00 or later ones, there're two +modes of implementation - Version 3.00 compatible mode or +Version 4 mode. This patch introduced an interface to enable +v4 mode. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 29 +++++++++++++++++++++++++++++ + drivers/mmc/host/sdhci.h | 3 +++ + 2 files changed, 32 insertions(+) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index e698218..1feecbe 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -123,6 +123,29 @@ EXPORT_SYMBOL_GPL(sdhci_dumpregs); + * * + \*****************************************************************************/ + ++static void sdhci_do_enable_v4_mode(struct sdhci_host *host) ++{ ++ u16 ctrl2; ++ ++ ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2); ++ if (ctrl2 & SDHCI_CTRL_V4_MODE) ++ return; ++ ++ ctrl2 |= SDHCI_CTRL_V4_MODE; ++ sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL); ++} ++ ++/* ++ * This can be called before sdhci_add_host() by Vendor's host controller ++ * driver to enable v4 mode if supported. ++ */ ++void sdhci_enable_v4_mode(struct sdhci_host *host) ++{ ++ host->v4_mode = true; ++ sdhci_do_enable_v4_mode(host); ++} ++EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); ++ + static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) + { + return cmd->data || cmd->flags & MMC_RSP_BUSY; +@@ -252,6 +275,9 @@ static void sdhci_init(struct sdhci_host *host, int soft) + else + sdhci_do_reset(host, SDHCI_RESET_ALL); + ++ if (host->v4_mode) ++ sdhci_do_enable_v4_mode(host); ++ + sdhci_set_default_irqs(host); + + host->cqe_on = false; +@@ -3307,6 +3333,9 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) + + sdhci_do_reset(host, SDHCI_RESET_ALL); + ++ if (host->v4_mode) ++ sdhci_do_enable_v4_mode(host); ++ + of_property_read_u64(mmc_dev(host->mmc)->of_node, + "sdhci-caps-mask", &dt_caps_mask); + of_property_read_u64(mmc_dev(host->mmc)->of_node, +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 6bafe26..63c7d61 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -184,6 +184,7 @@ + #define SDHCI_CTRL_DRV_TYPE_D 0x0030 + #define SDHCI_CTRL_EXEC_TUNING 0x0040 + #define SDHCI_CTRL_TUNED_CLK 0x0080 ++#define SDHCI_CTRL_V4_MODE 0x1000 + #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + + #define SDHCI_CAPABILITIES 0x40 +@@ -491,6 +492,7 @@ struct sdhci_host { + bool bus_on; /* Bus power prevents runtime suspend */ + bool preset_enabled; /* Preset is enabled */ + bool pending_reset; /* Cmd/data reset is pending */ ++ bool v4_mode; /* Host Version 4 Enable */ + + struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ + struct mmc_command *cmd; /* Current command */ +@@ -745,6 +747,7 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, + int *data_error); + + void sdhci_dumpregs(struct sdhci_host *host); ++void sdhci_enable_v4_mode(struct sdhci_host *host); + + void sdhci_start_tuning(struct sdhci_host *host); + void sdhci_end_tuning(struct sdhci_host *host); +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5736-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5736-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch new file mode 100644 index 00000000..c872c0b3 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5736-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch @@ -0,0 +1,211 @@ +From 227ef7c1031e63d5ebdc50df75f2e3eb01a837ea Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Tue, 12 Feb 2019 19:12:31 +0530 +Subject: [PATCH 5736/5758] mmc: sdhci: Add ADMA2 64-bit addressing support + for V4 mode + +ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. +So there are two kinds of descriptors for ADMA2 64-bit addressing +i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 +mode. 128-bit Descriptor is aligned to 8-byte. + +For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 +register. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +[Ulf: Fixed conflict while applying] +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + drivers/mmc/host/sdhci.c | 92 +++++++++++++++++++++++++++++++++++------------- + drivers/mmc/host/sdhci.h | 12 +++++-- + 2 files changed, 78 insertions(+), 26 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 1feecbe..0cd4b1e 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + } + ++static void sdhci_config_dma(struct sdhci_host *host) ++{ ++ u8 ctrl; ++ u16 ctrl2; ++ ++ if (host->version < SDHCI_SPEC_200) ++ return; ++ ++ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ++ ++ /* ++ * Always adjust the DMA selection as some controllers ++ * (e.g. JMicron) can't do PIO properly when the selection ++ * is ADMA. ++ */ ++ ctrl &= ~SDHCI_CTRL_DMA_MASK; ++ if (!(host->flags & SDHCI_REQ_USE_DMA)) ++ goto out; ++ ++ /* Note if DMA Select is zero then SDMA is selected */ ++ if (host->flags & SDHCI_USE_ADMA) ++ ctrl |= SDHCI_CTRL_ADMA32; ++ ++ if (host->flags & SDHCI_USE_64_BIT_DMA) { ++ /* ++ * If v4 mode, all supported DMA can be 64-bit addressing if ++ * controller supports 64-bit system address, otherwise only ++ * ADMA can support 64-bit addressing. ++ */ ++ if (host->v4_mode) { ++ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ ctrl2 |= SDHCI_CTRL_64BIT_ADDR; ++ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); ++ } else if (host->flags & SDHCI_USE_ADMA) { ++ /* ++ * Don't need to undo SDHCI_CTRL_ADMA32 in order to ++ * set SDHCI_CTRL_ADMA64. ++ */ ++ ctrl |= SDHCI_CTRL_ADMA64; ++ } ++ } ++ ++out: ++ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); ++} ++ + static void sdhci_init(struct sdhci_host *host, int soft) + { + struct mmc_host *mmc = host->mmc; +@@ -839,7 +885,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) + + static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) + { +- u8 ctrl; + struct mmc_data *data = cmd->data; + + if (sdhci_data_line_cmd(cmd)) +@@ -934,25 +979,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) + } + } + +- /* +- * Always adjust the DMA selection as some controllers +- * (e.g. JMicron) can't do PIO properly when the selection +- * is ADMA. +- */ +- if (host->version >= SDHCI_SPEC_200) { +- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); +- ctrl &= ~SDHCI_CTRL_DMA_MASK; +- if ((host->flags & SDHCI_REQ_USE_DMA) && +- (host->flags & SDHCI_USE_ADMA)) { +- if (host->flags & SDHCI_USE_64_BIT_DMA) +- ctrl |= SDHCI_CTRL_ADMA64; +- else +- ctrl |= SDHCI_CTRL_ADMA32; +- } else { +- ctrl |= SDHCI_CTRL_SDMA; +- } +- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +- } ++ sdhci_config_dma(host); + + if (!(host->flags & SDHCI_REQ_USE_DMA)) { + int flags; +@@ -3436,6 +3463,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) + return 0; + } + ++static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) ++{ ++ /* ++ * According to SD Host Controller spec v4.10, bit[27] added from ++ * version 4.10 in Capabilities Register is used as 64-bit System ++ * Address support for V4 mode. ++ */ ++ if (host->version >= SDHCI_SPEC_410 && host->v4_mode) ++ return host->caps & SDHCI_CAN_64BIT_V4; ++ ++ return host->caps & SDHCI_CAN_64BIT; ++} ++ + int sdhci_setup_host(struct sdhci_host *host) + { + struct mmc_host *mmc; +@@ -3507,7 +3547,7 @@ int sdhci_setup_host(struct sdhci_host *host) + * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to + * implement. + */ +- if (host->caps & SDHCI_CAN_64BIT) ++ if (sdhci_can_64bit_dma(host)) + host->flags |= SDHCI_USE_64_BIT_DMA; + + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { +@@ -3535,8 +3575,8 @@ int sdhci_setup_host(struct sdhci_host *host) + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + host->adma_table_sz = host->adma_table_cnt * +- SDHCI_ADMA2_64_DESC_SZ; +- host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; ++ SDHCI_ADMA2_64_DESC_SZ(host); ++ host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); + } else { + host->adma_table_sz = host->adma_table_cnt * + SDHCI_ADMA2_32_DESC_SZ; +@@ -3544,7 +3584,11 @@ int sdhci_setup_host(struct sdhci_host *host) + } + + host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; +- buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + ++ /* ++ * Use zalloc to zero the reserved high 32-bits of 128-bit ++ * descriptors so that they never need to be written. ++ */ ++ buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + host->adma_table_sz, &dma, GFP_KERNEL); + if (!buf) { + pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 63c7d61..2763970 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -185,6 +185,7 @@ + #define SDHCI_CTRL_EXEC_TUNING 0x0040 + #define SDHCI_CTRL_TUNED_CLK 0x0080 + #define SDHCI_CTRL_V4_MODE 0x1000 ++#define SDHCI_CTRL_64BIT_ADDR 0x2000 + #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + + #define SDHCI_CAPABILITIES 0x40 +@@ -205,6 +206,7 @@ + #define SDHCI_CAN_VDD_330 0x01000000 + #define SDHCI_CAN_VDD_300 0x02000000 + #define SDHCI_CAN_VDD_180 0x04000000 ++#define SDHCI_CAN_64BIT_V4 0x08000000 + #define SDHCI_CAN_64BIT 0x10000000 + + #define SDHCI_SUPPORT_SDR50 0x00000001 +@@ -309,8 +311,14 @@ struct sdhci_adma2_32_desc { + */ + #define SDHCI_ADMA2_DESC_ALIGN 8 + +-/* ADMA2 64-bit DMA descriptor size */ +-#define SDHCI_ADMA2_64_DESC_SZ 12 ++/* ++ * ADMA2 64-bit DMA descriptor size ++ * According to SD Host Controller spec v4.10, there are two kinds of ++ * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit ++ * Descriptor, if Host Version 4 Enable is set in the Host Control 2 ++ * register, 128-bit Descriptor will be selected. ++ */ ++#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) + + /* + * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5737-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5737-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch new file mode 100644 index 00000000..66f28f72 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5737-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch @@ -0,0 +1,80 @@ +From 7d08c14012602dc43c5b92b4fe0848801d6d54c1 Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Tue, 12 Feb 2019 19:14:24 +0530 +Subject: [PATCH 5737/5758] mmc: sdhci: Add 32-bit block count support for v4 + mode + +Host Controller Version 4.10 re-defines SDMA System Address register +as 32-bit Block Count for v4 mode, and SDMA uses ADMA System +Address register (05Fh-058h) instead if v4 mode is enabled. Also +when using 32-bit block count, 16-bit block count register need +to be set to zero. + +Since using 32-bit Block Count would cause problems for auto-cmd23, +it can be chosen via host->quirk2. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + drivers/mmc/host/sdhci.c | 14 +++++++++++++- + drivers/mmc/host/sdhci.h | 8 ++++++++ + 2 files changed, 21 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 0cd4b1e..a082614 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -998,7 +998,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) + /* Set the DMA boundary value and block size */ + sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), + SDHCI_BLOCK_SIZE); +- sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); ++ ++ /* ++ * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count ++ * can be supported, in that case 16-bit block count register must be 0. ++ */ ++ if (host->version >= SDHCI_SPEC_410 && host->v4_mode && ++ (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { ++ if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) ++ sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); ++ sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); ++ } else { ++ sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); ++ } + } + + static inline bool sdhci_auto_cmd12(struct sdhci_host *host, +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 2763970..73ae5f8 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -28,6 +28,7 @@ + + #define SDHCI_DMA_ADDRESS 0x00 + #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS ++#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS + + #define SDHCI_BLOCK_SIZE 0x04 + #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) +@@ -449,6 +450,13 @@ struct sdhci_host { + #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) + /* Controller has CRC in 136 bit Command Response */ + #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) ++/* ++ * 32-bit block count may not support eMMC where upper bits of CMD23 are used ++ * for other purposes. Consequently we support 16-bit block count by default. ++ * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit ++ * block count. ++ */ ++#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) + + #define SDHCI_QUIRK2_BROKEN_TUNING_WA (1<<17) + int irq; /* Device IRQ */ +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5738-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5738-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch new file mode 100644 index 00000000..c24ff3b9 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5738-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch @@ -0,0 +1,117 @@ +From 2ccce2251f92f8978382dd8c75cc6ccae1b6d97f Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Tue, 12 Feb 2019 19:15:20 +0530 +Subject: [PATCH 5738/5758] mmc: sdhci: Add Auto CMD Auto Select support + +As SD Host Controller Specification v4.10 documents: +Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. +Selection of Auto CMD depends on setting of CMD23 Enable in the Host +Control 2 register which indicates whether card supports CMD23. If CMD23 +Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is +used. In case of Version 4.10 or later, use of Auto CMD Auto Select is +recommended rather than use of Auto CMD12 Enable or Auto CMD23 +Enable. + +This patch add this new mode support. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + drivers/mmc/host/sdhci.c | 49 ++++++++++++++++++++++++++++++++++++++---------- + drivers/mmc/host/sdhci.h | 2 ++ + 2 files changed, 41 insertions(+), 10 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index a082614..d7c9274 100755 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1020,6 +1020,43 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host *host, + !mrq->cap_cmd_during_tfr; + } + ++static inline void sdhci_auto_cmd_select(struct sdhci_host *host, ++ struct mmc_command *cmd, ++ u16 *mode) ++{ ++ bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && ++ (cmd->opcode != SD_IO_RW_EXTENDED); ++ bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); ++ u16 ctrl2; ++ ++ /* ++ * In case of Version 4.10 or later, use of 'Auto CMD Auto ++ * Select' is recommended rather than use of 'Auto CMD12 ++ * Enable' or 'Auto CMD23 Enable'. ++ */ ++ if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { ++ *mode |= SDHCI_TRNS_AUTO_SEL; ++ ++ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ if (use_cmd23) ++ ctrl2 |= SDHCI_CMD23_ENABLE; ++ else ++ ctrl2 &= ~SDHCI_CMD23_ENABLE; ++ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); ++ ++ return; ++ } ++ ++ /* ++ * If we are sending CMD23, CMD12 never gets sent ++ * on successful completion (so no Auto-CMD12). ++ */ ++ if (use_cmd12) ++ *mode |= SDHCI_TRNS_AUTO_CMD12; ++ else if (use_cmd23) ++ *mode |= SDHCI_TRNS_AUTO_CMD23; ++} ++ + static void sdhci_set_transfer_mode(struct sdhci_host *host, + struct mmc_command *cmd) + { +@@ -1046,17 +1083,9 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, + + if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { + mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; +- /* +- * If we are sending CMD23, CMD12 never gets sent +- * on successful completion (so no Auto-CMD12). +- */ +- if (sdhci_auto_cmd12(host, cmd->mrq) && +- (cmd->opcode != SD_IO_RW_EXTENDED)) +- mode |= SDHCI_TRNS_AUTO_CMD12; +- else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { +- mode |= SDHCI_TRNS_AUTO_CMD23; ++ sdhci_auto_cmd_select(host, cmd, &mode); ++ if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) + sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); +- } + } + + if (data->flags & MMC_DATA_READ) +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 73ae5f8..dd3219e 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -42,6 +42,7 @@ + #define SDHCI_TRNS_BLK_CNT_EN 0x02 + #define SDHCI_TRNS_AUTO_CMD12 0x04 + #define SDHCI_TRNS_AUTO_CMD23 0x08 ++#define SDHCI_TRNS_AUTO_SEL 0x0C + #define SDHCI_TRNS_READ 0x10 + #define SDHCI_TRNS_MULTI 0x20 + +@@ -185,6 +186,7 @@ + #define SDHCI_CTRL_DRV_TYPE_D 0x0030 + #define SDHCI_CTRL_EXEC_TUNING 0x0040 + #define SDHCI_CTRL_TUNED_CLK 0x0080 ++#define SDHCI_CMD23_ENABLE 0x0800 + #define SDHCI_CTRL_V4_MODE 0x1000 + #define SDHCI_CTRL_64BIT_ADDR 0x2000 + #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5739-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5739-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch new file mode 100644 index 00000000..6a2cf4f5 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5739-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch @@ -0,0 +1,45 @@ +From 814a991d5e22411b1ca2bf47c7c25aa07042de38 Mon Sep 17 00:00:00 2001 +From: YueHaibing <yuehaibing@huawei.com> +Date: Thu, 26 Jul 2018 09:51:27 +0800 +Subject: [PATCH 5739/5758] amd-xgbe: use dma_mapping_error to check map errors + +The dma_mapping_error() returns true or false, but we want +to return -ENOMEM if there was an error. + +Fixes: 174fd2597b0b ("amd-xgbe: Implement split header receive support") +Signed-off-by: YueHaibing <yuehaibing@huawei.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-desc.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c +index cc1e4f8..5330942 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c +@@ -289,7 +289,7 @@ static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, + struct page *pages = NULL; + dma_addr_t pages_dma; + gfp_t gfp; +- int order, ret; ++ int order; + + again: + order = alloc_order; +@@ -316,10 +316,9 @@ static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, + /* Map the pages */ + pages_dma = dma_map_page(pdata->dev, pages, 0, + PAGE_SIZE << order, DMA_FROM_DEVICE); +- ret = dma_mapping_error(pdata->dev, pages_dma); +- if (ret) { ++ if (dma_mapping_error(pdata->dev, pages_dma)) { + put_page(pages); +- return ret; ++ return -ENOMEM; + } + + pa->pages = pages; +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5740-lib-crc-Move-polynomial-definition-to-separate-heade.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5740-lib-crc-Move-polynomial-definition-to-separate-heade.patch new file mode 100644 index 00000000..0b3384e8 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5740-lib-crc-Move-polynomial-definition-to-separate-heade.patch @@ -0,0 +1,96 @@ +From f52e39a9b26ab160a1195daaaa195cc018793588 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Tue, 17 Jul 2018 18:05:36 +0200 +Subject: [PATCH 5740/5758] lib/crc: Move polynomial definition to separate + header + +Allow other drivers and parts of kernel to use the same define for +CRC32 polynomial, instead of duplicating it in many places. This code +does not bring any functional changes, except moving existing code. + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + include/linux/crc32poly.h | 20 ++++++++++++++++++++ + lib/crc32.c | 1 + + lib/crc32defs.h | 14 -------------- + lib/gen_crc32table.c | 1 + + 4 files changed, 22 insertions(+), 14 deletions(-) + create mode 100644 include/linux/crc32poly.h + +diff --git a/include/linux/crc32poly.h b/include/linux/crc32poly.h +new file mode 100644 +index 0000000..7ad5aa9 +--- /dev/null ++++ b/include/linux/crc32poly.h +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _LINUX_CRC32_POLY_H ++#define _LINUX_CRC32_POLY_H ++ ++/* ++ * There are multiple 16-bit CRC polynomials in common use, but this is ++ * *the* standard CRC-32 polynomial, first popularized by Ethernet. ++ * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 ++ */ ++#define CRCPOLY_LE 0xedb88320 ++#define CRCPOLY_BE 0x04c11db7 ++ ++/* ++ * This is the CRC32c polynomial, as outlined by Castagnoli. ++ * x^32+x^28+x^27+x^26+x^25+x^23+x^22+x^20+x^19+x^18+x^14+x^13+x^11+x^10+x^9+ ++ * x^8+x^6+x^0 ++ */ ++#define CRC32C_POLY_LE 0x82F63B78 ++ ++#endif /* _LINUX_CRC32_POLY_H */ +diff --git a/lib/crc32.c b/lib/crc32.c +index 6ddc92b..82bfc053 100644 +--- a/lib/crc32.c ++++ b/lib/crc32.c +@@ -27,6 +27,7 @@ + /* see: Documentation/crc32.txt for a description of algorithms */ + + #include <linux/crc32.h> ++#include <linux/crc32poly.h> + #include <linux/module.h> + #include <linux/types.h> + #include <linux/sched.h> +diff --git a/lib/crc32defs.h b/lib/crc32defs.h +index cb275a2..0c8fb59 100644 +--- a/lib/crc32defs.h ++++ b/lib/crc32defs.h +@@ -1,18 +1,4 @@ + /* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * There are multiple 16-bit CRC polynomials in common use, but this is +- * *the* standard CRC-32 polynomial, first popularized by Ethernet. +- * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 +- */ +-#define CRCPOLY_LE 0xedb88320 +-#define CRCPOLY_BE 0x04c11db7 +- +-/* +- * This is the CRC32c polynomial, as outlined by Castagnoli. +- * x^32+x^28+x^27+x^26+x^25+x^23+x^22+x^20+x^19+x^18+x^14+x^13+x^11+x^10+x^9+ +- * x^8+x^6+x^0 +- */ +-#define CRC32C_POLY_LE 0x82F63B78 + + /* Try to choose an implementation variant via Kconfig */ + #ifdef CONFIG_CRC32_SLICEBY8 +diff --git a/lib/gen_crc32table.c b/lib/gen_crc32table.c +index 8f26660..34c3bc8 100644 +--- a/lib/gen_crc32table.c ++++ b/lib/gen_crc32table.c +@@ -1,5 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + #include <stdio.h> ++#include "../include/linux/crc32poly.h" + #include "../include/generated/autoconf.h" + #include "crc32defs.h" + #include <inttypes.h> +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5741-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5741-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch new file mode 100644 index 00000000..8739c59c --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5741-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch @@ -0,0 +1,105 @@ +From 73207c21e8dd4efdc4c7914f73590ab7b5211e5e Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Tue, 17 Jul 2018 18:05:37 +0200 +Subject: [PATCH 5741/5758] lib/crc: Use consistent naming for CRC-32 + polynomials + +Header was defining CRCPOLY_LE/BE and CRC32C_POLY_LE but in fact all of +them are CRC-32 polynomials so use consistent naming. + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + include/linux/crc32poly.h | 4 ++-- + lib/crc32.c | 10 +++++----- + lib/gen_crc32table.c | 4 ++-- + 3 files changed, 9 insertions(+), 9 deletions(-) + +diff --git a/include/linux/crc32poly.h b/include/linux/crc32poly.h +index 7ad5aa9..62c4b77 100644 +--- a/include/linux/crc32poly.h ++++ b/include/linux/crc32poly.h +@@ -7,8 +7,8 @@ + * *the* standard CRC-32 polynomial, first popularized by Ethernet. + * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 + */ +-#define CRCPOLY_LE 0xedb88320 +-#define CRCPOLY_BE 0x04c11db7 ++#define CRC32_POLY_LE 0xedb88320 ++#define CRC32_POLY_BE 0x04c11db7 + + /* + * This is the CRC32c polynomial, as outlined by Castagnoli. +diff --git a/lib/crc32.c b/lib/crc32.c +index 82bfc053..7111c44 100644 +--- a/lib/crc32.c ++++ b/lib/crc32.c +@@ -185,7 +185,7 @@ static inline u32 __pure crc32_le_generic(u32 crc, unsigned char const *p, + #if CRC_LE_BITS == 1 + u32 __pure crc32_le(u32 crc, unsigned char const *p, size_t len) + { +- return crc32_le_generic(crc, p, len, NULL, CRCPOLY_LE); ++ return crc32_le_generic(crc, p, len, NULL, CRC32_POLY_LE); + } + u32 __pure __crc32c_le(u32 crc, unsigned char const *p, size_t len) + { +@@ -195,7 +195,7 @@ u32 __pure __crc32c_le(u32 crc, unsigned char const *p, size_t len) + u32 __pure crc32_le(u32 crc, unsigned char const *p, size_t len) + { + return crc32_le_generic(crc, p, len, +- (const u32 (*)[256])crc32table_le, CRCPOLY_LE); ++ (const u32 (*)[256])crc32table_le, CRC32_POLY_LE); + } + u32 __pure __crc32c_le(u32 crc, unsigned char const *p, size_t len) + { +@@ -269,7 +269,7 @@ static u32 __attribute_const__ crc32_generic_shift(u32 crc, size_t len, + + u32 __attribute_const__ crc32_le_shift(u32 crc, size_t len) + { +- return crc32_generic_shift(crc, len, CRCPOLY_LE); ++ return crc32_generic_shift(crc, len, CRC32_POLY_LE); + } + + u32 __attribute_const__ __crc32c_le_shift(u32 crc, size_t len) +@@ -331,13 +331,13 @@ static inline u32 __pure crc32_be_generic(u32 crc, unsigned char const *p, + #if CRC_LE_BITS == 1 + u32 __pure crc32_be(u32 crc, unsigned char const *p, size_t len) + { +- return crc32_be_generic(crc, p, len, NULL, CRCPOLY_BE); ++ return crc32_be_generic(crc, p, len, NULL, CRC32_POLY_BE); + } + #else + u32 __pure crc32_be(u32 crc, unsigned char const *p, size_t len) + { + return crc32_be_generic(crc, p, len, +- (const u32 (*)[256])crc32table_be, CRCPOLY_BE); ++ (const u32 (*)[256])crc32table_be, CRC32_POLY_BE); + } + #endif + EXPORT_SYMBOL(crc32_be); +diff --git a/lib/gen_crc32table.c b/lib/gen_crc32table.c +index 34c3bc8..f755b99 100644 +--- a/lib/gen_crc32table.c ++++ b/lib/gen_crc32table.c +@@ -58,7 +58,7 @@ static void crc32init_le_generic(const uint32_t polynomial, + + static void crc32init_le(void) + { +- crc32init_le_generic(CRCPOLY_LE, crc32table_le); ++ crc32init_le_generic(CRC32_POLY_LE, crc32table_le); + } + + static void crc32cinit_le(void) +@@ -77,7 +77,7 @@ static void crc32init_be(void) + crc32table_be[0][0] = 0; + + for (i = 1; i < BE_TABLE_SIZE; i <<= 1) { +- crc = (crc << 1) ^ ((crc & 0x80000000) ? CRCPOLY_BE : 0); ++ crc = (crc << 1) ^ ((crc & 0x80000000) ? CRC32_POLY_BE : 0); + for (j = 0; j < i; j++) + crc32table_be[0][i + j] = crc ^ crc32table_be[0][j]; + } +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5742-net-ethernet-Use-existing-define-with-polynomial.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5742-net-ethernet-Use-existing-define-with-polynomial.patch new file mode 100644 index 00000000..fdc6f000 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5742-net-ethernet-Use-existing-define-with-polynomial.patch @@ -0,0 +1,46 @@ +From 43467fc009a72c1efba2f0d6806584b805685fc0 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Tue, 17 Jul 2018 18:05:39 +0200 +Subject: [PATCH 5742/5758] net: ethernet: Use existing define with polynomial + +Do not define again the polynomial but use header with existing define. + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +index e107e18..1e929a1 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +@@ -119,6 +119,7 @@ + #include <linux/clk.h> + #include <linux/bitrev.h> + #include <linux/crc32.h> ++#include <linux/crc32poly.h> + + #include "xgbe.h" + #include "xgbe-common.h" +@@ -887,7 +888,6 @@ static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) + + static u32 xgbe_vid_crc32_le(__le16 vid_le) + { +- u32 poly = 0xedb88320; /* CRCPOLY_LE */ + u32 crc = ~0; + u32 temp = 0; + unsigned char *data = (unsigned char *)&vid_le; +@@ -904,7 +904,7 @@ static u32 xgbe_vid_crc32_le(__le16 vid_le) + data_byte >>= 1; + + if (temp) +- crc ^= poly; ++ crc ^= CRC32_POLY_LE; + } + + return crc; +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5743-net-amd-fix-return-type-of-ndo_start_xmit-function.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5743-net-amd-fix-return-type-of-ndo_start_xmit-function.patch new file mode 100644 index 00000000..77dba6a6 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5743-net-amd-fix-return-type-of-ndo_start_xmit-function.patch @@ -0,0 +1,45 @@ +From 56abff6d96f7b1f48e2f01b062d14613846275b7 Mon Sep 17 00:00:00 2001 +From: YueHaibing <yuehaibing@huawei.com> +Date: Wed, 19 Sep 2018 18:50:17 +0800 +Subject: [PATCH 5743/5758] net: amd: fix return type of ndo_start_xmit + function + +The method ndo_start_xmit() is defined as returning an 'netdev_tx_t', +which is a typedef for an enum type, so make sure the implementation in +this driver has returns 'netdev_tx_t' value, and change the function +return type to netdev_tx_t. + +Found by coccinelle. + +Signed-off-by: YueHaibing <yuehaibing@huawei.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index 093e2fd..93b4048 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -2009,7 +2009,7 @@ static int xgbe_close(struct net_device *netdev) + return 0; + } + +-static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) ++static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) + { + struct xgbe_prv_data *pdata = netdev_priv(netdev); + struct xgbe_hw_if *hw_if = &pdata->hw_if; +@@ -2018,7 +2018,7 @@ static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) + struct xgbe_ring *ring; + struct xgbe_packet_data *packet; + struct netdev_queue *txq; +- int ret; ++ netdev_tx_t ret; + + DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); + +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5744-net-phy-Add-helper-for-advertise-to-lcl-value.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5744-net-phy-Add-helper-for-advertise-to-lcl-value.patch new file mode 100644 index 00000000..bb0f4363 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5744-net-phy-Add-helper-for-advertise-to-lcl-value.patch @@ -0,0 +1,71 @@ +From 8bdf040cce4c23fb86265d962915c8cee6abe5a7 Mon Sep 17 00:00:00 2001 +From: Andrew Lunn <andrew@lunn.ch> +Date: Sat, 29 Sep 2018 23:04:13 +0200 +Subject: [PATCH 5744/5758] net: phy: Add helper for advertise to lcl value + +Add a helper to convert the local advertising to an LCL capabilities, +which is then used to resolve pause flow control settings. + +Signed-off-by: Andrew Lunn <andrew@lunn.ch> +Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> +Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 5 +---- + include/linux/mii.h | 20 ++++++++++++++++++++ + 2 files changed, 21 insertions(+), 4 deletions(-) + mode change 100644 => 100755 include/linux/mii.h + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +index 194ec27..151bdb6 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -1497,10 +1497,7 @@ static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) + if (!phy_data->phydev) + return; + +- if (phy_data->phydev->advertising & ADVERTISED_Pause) +- lcl_adv |= ADVERTISE_PAUSE_CAP; +- if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause) +- lcl_adv |= ADVERTISE_PAUSE_ASYM; ++ lcl_adv = ethtool_adv_to_lcl_adv_t(phy_data->phydev->advertising); + + if (phy_data->phydev->pause) { + XGBE_SET_LP_ADV(lks, Pause); +diff --git a/include/linux/mii.h b/include/linux/mii.h +old mode 100644 +new mode 100755 +index 55000ee..63cd587 +--- a/include/linux/mii.h ++++ b/include/linux/mii.h +@@ -302,6 +302,26 @@ static inline u32 mii_lpa_to_ethtool_lpa_x(u32 lpa) + return result | mii_adv_to_ethtool_adv_x(lpa); + } + ++ ++/** ++ * ethtool_adv_to_lcl_adv_t ++ * @advertising:pointer to ethtool advertising ++ * ++ * A small helper function that translates ethtool advertising to LVL ++ * pause capabilities. ++ */ ++static inline u32 ethtool_adv_to_lcl_adv_t(u32 advertising) ++{ ++ u32 lcl_adv = 0; ++ ++ if (advertising & ADVERTISED_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_CAP; ++ if (advertising & ADVERTISED_Asym_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_ASYM; ++ ++ return lcl_adv; ++} ++ + /** + * mii_advertise_flowctrl - get flow control advertisement flags + * @cap: Flow control capabilities (FLOW_CTRL_RX, FLOW_CTRL_TX or both) +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5745-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5745-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch new file mode 100644 index 00000000..7a1e240d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5745-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch @@ -0,0 +1,35 @@ +From 5c6a31fed9eb8e880f669369e269a4c347cf1355 Mon Sep 17 00:00:00 2001 +From: Eric Dumazet <edumazet@google.com> +Date: Thu, 25 Oct 2018 06:42:12 -0700 +Subject: [PATCH 5745/5758] drivers: net: remove <net/busy_poll.h> inclusion + when not needed + +Drivers using generic NAPI interface no longer need to include +<net/busy_poll.h>, since busy polling was moved to core networking +stack long ago. + +See commit 79e7fff47b7b ("net: remove support for per driver +ndo_busy_poll()") for reference. + +Signed-off-by: Eric Dumazet <edumazet@google.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index 93b4048..e1c0fea 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -119,7 +119,6 @@ + #include <linux/tcp.h> + #include <linux/if_vlan.h> + #include <linux/interrupt.h> +-#include <net/busy_poll.h> + #include <linux/clk.h> + #include <linux/if_ether.h> + #include <linux/net_tstamp.h> +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5746-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5746-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch new file mode 100644 index 00000000..e66372cb --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5746-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch @@ -0,0 +1,103 @@ +From 527e0c11bf326ce3e14cc85a79f0cf95cbcff7af Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Tue, 12 Feb 2019 20:08:46 +0530 +Subject: [PATCH 5746/5758] amd-eMMC sdhci HS400 workaround for ZP + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + drivers/mmc/core/mmc.c | 2 ++ + drivers/mmc/host/sdhci-acpi.c | 1 - + drivers/mmc/host/sdhci.c | 9 --------- + drivers/mmc/host/sdhci.h | 1 - + include/linux/mmc/host.h | 1 - + 5 files changed, 2 insertions(+), 12 deletions(-) + mode change 100755 => 100644 drivers/mmc/host/sdhci-acpi.c + mode change 100755 => 100644 drivers/mmc/host/sdhci.c + mode change 100755 => 100644 include/linux/mmc/host.h + +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +index cd3604d..20be475 100755 +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1405,6 +1405,8 @@ static int mmc_select_hs400es(struct mmc_card *card) + if (host->ops->hs400_complete) + host->ops->hs400_complete(host); + ++ if (host->ops->set_hs400_dll) ++ host->ops->set_hs400_dll(host); + return 0; + + out_err: +diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c +old mode 100755 +new mode 100644 +index 33592a6..b01e906 +--- a/drivers/mmc/host/sdhci-acpi.c ++++ b/drivers/mmc/host/sdhci-acpi.c +@@ -411,7 +411,6 @@ static const struct sdhci_ops sdhci_acpi_ops_amd = { + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +- .set_hs400_dll = sdhci_acpi_amd_hs400_dll, + }; + + static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = { +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +old mode 100755 +new mode 100644 +index d7c9274..46346ec +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1983,14 +1983,6 @@ static void sdhci_hw_reset(struct mmc_host *mmc) + host->ops->hw_reset(host); + } + +-static void sdhci_set_hs400_dll(struct mmc_host *mmc) +-{ +- struct sdhci_host *host = mmc_priv(mmc); +- +- if (host->ops && host->ops->set_hs400_dll) +- host->ops->set_hs400_dll(host); +-} +- + static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) + { + if (!(host->flags & SDHCI_DEVICE_DEAD)) { +@@ -2478,7 +2470,6 @@ static const struct mmc_host_ops sdhci_ops = { + .get_cd = sdhci_get_cd, + .get_ro = sdhci_get_ro, + .hw_reset = sdhci_hw_reset, +- .set_hs400_dll = sdhci_set_hs400_dll, + .enable_sdio_irq = sdhci_enable_sdio_irq, + .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, + .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index dd3219e..027d85a 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -611,7 +611,6 @@ struct sdhci_ops { + int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); + void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); + void (*hw_reset)(struct sdhci_host *host); +- void (*set_hs400_dll)(struct sdhci_host *host); + void (*adma_workaround)(struct sdhci_host *host, u32 intmask); + void (*card_event)(struct sdhci_host *host); + void (*voltage_switch)(struct sdhci_host *host); +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +old mode 100755 +new mode 100644 +index ba4af38..843c38f +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -159,7 +159,6 @@ struct mmc_host_ops { + unsigned int max_dtr, int host_drv, + int card_drv, int *drv_type); + void (*hw_reset)(struct mmc_host *host); +- void (*set_hs400_dll)(struct mmc_host *host); + void (*card_event)(struct mmc_host *host); + + /* +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5747-drm-amd-display-Raise-dispclk-value-for-CZ.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5747-drm-amd-display-Raise-dispclk-value-for-CZ.patch new file mode 100644 index 00000000..8a75719f --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5747-drm-amd-display-Raise-dispclk-value-for-CZ.patch @@ -0,0 +1,48 @@ +From 0a5c7924cab22adc4f0e062850072402c53e8c27 Mon Sep 17 00:00:00 2001 +From: Kalyan Alle <kalyan.alle@amd.com> +Date: Tue, 20 Nov 2018 16:50:29 -0500 +Subject: [PATCH 5747/5758] drm/amd/display: Raise dispclk value for CZ. + +[Why] +The visual corruption due to low display clock value. +Observed on 4k@60Hz. + +[How] +There was earlier patch for dspclk: +'drm/amd/display: Raise dispclk value for dce_update_clocks' +Adding +15% workaround also to to dce11_update_clocks + +Signed-off-by: Roman Li <Roman.Li@amd.com> +Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +index 493e2f4..1dfe93e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +@@ -648,6 +648,10 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr, + { + struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); + struct dm_pp_power_level_change_request level_change_req; ++ int unpatched_disp_clk = context->bw.dce.dispclk_khz; ++ ++ if (!clk_mgr_dce->dfs_bypass_active) ++ context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100; + + level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); + /* get max clock state from PPLIB */ +@@ -662,6 +666,8 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr, + clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz; + } + dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); ++ ++ context->bw.dce.dispclk_khz = unpatched_disp_clk; + } + + static void dce112_update_clocks(struct clk_mgr *clk_mgr, +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5748-drm-amdgpu-gfx8-disable-EDC.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5748-drm-amdgpu-gfx8-disable-EDC.patch new file mode 100644 index 00000000..0de9769a --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5748-drm-amdgpu-gfx8-disable-EDC.patch @@ -0,0 +1,38 @@ +From 241cbaf30db2728ec005607a659358174cb3a486 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 23 Aug 2016 17:37:36 -0400 +Subject: [PATCH 5748/5758] drm/amdgpu/gfx8: disable EDC + +This if fixing the unigine heaven application soft hang +while running in extreme preset mode + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 90cbf66..43272fb 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -1665,7 +1665,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + goto fail; + } +- ++#if 0 + tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); + tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); + WREG32(mmGB_EDC_MODE, tmp); +@@ -1673,6 +1673,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + tmp = RREG32(mmCC_GC_EDC_CONFIG); + tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; + WREG32(mmCC_GC_EDC_CONFIG, tmp); ++#endif + + /* read back registers to clear the counters */ + for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5749-net-phy-Also-request-modules-for-C45-IDs.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5749-net-phy-Also-request-modules-for-C45-IDs.patch new file mode 100644 index 00000000..d9ae9e3c --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5749-net-phy-Also-request-modules-for-C45-IDs.patch @@ -0,0 +1,56 @@ +From 061b7fcf0d45da2dc816a58f0c01c35c59113871 Mon Sep 17 00:00:00 2001 +From: Jose Abreu <jose.abreu@synopsys.com> +Date: Sun, 2 Dec 2018 16:33:14 +0100 +Subject: [PATCH 5749/5758] net: phy: Also request modules for C45 IDs + +Logic of phy_device_create() requests PHY modules according to PHY ID +but for C45 PHYs we use different field for the IDs. + +Let's also request the modules for these IDs. + +Changes from v1: +- Only request C22 modules if C45 are not present (Andrew) + +Signed-off-by: Jose Abreu <joabreu@synopsys.com> +Cc: Andrew Lunn <andrew@lunn.ch> +Cc: Florian Fainelli <f.fainelli@gmail.com> +Cc: "David S. Miller" <davem@davemloft.net> +Cc: Joao Pinto <joao.pinto@synopsys.com> +Reviewed-by: Andrew Lunn <andrew@lunn.ch> +Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/phy/phy_device.c | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c +index f16af99..a711f62 100755 +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -402,7 +402,21 @@ struct phy_device *phy_device_create(struct mii_bus *bus, int addr, int phy_id, + * driver will get bored and give up as soon as it finds that + * there's no driver _already_ loaded. + */ +- request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, MDIO_ID_ARGS(phy_id)); ++ if (is_c45 && c45_ids) { ++ const int num_ids = ARRAY_SIZE(c45_ids->device_ids); ++ int i; ++ ++ for (i = 1; i < num_ids; i++) { ++ if (!(c45_ids->devices_in_package & (1 << i))) ++ continue; ++ ++ request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, ++ MDIO_ID_ARGS(c45_ids->device_ids[i])); ++ } ++ } else { ++ request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, ++ MDIO_ID_ARGS(phy_id)); ++ } + + device_initialize(&mdiodev->dev); + +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5750-amd-xgbe-Fix-mdio-access-for-non-zero-ports-and-clau.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5750-amd-xgbe-Fix-mdio-access-for-non-zero-ports-and-clau.patch new file mode 100644 index 00000000..8097ea4d --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5750-amd-xgbe-Fix-mdio-access-for-non-zero-ports-and-clau.patch @@ -0,0 +1,94 @@ +From 92270fde5c8ff319d5839315d934f73717bfb358 Mon Sep 17 00:00:00 2001 +From: "Lendacky, Thomas" <Thomas.Lendacky@amd.com> +Date: Thu, 17 Jan 2019 14:20:14 +0000 +Subject: [PATCH 5750/5758] amd-xgbe: Fix mdio access for non-zero ports and + clause 45 PHYs + +The XGBE hardware has support for performing MDIO operations using an +MDIO command request. The driver mistakenly uses the mdio port address +as the MDIO command request device address instead of the MDIO command +request port address. Additionally, the driver does not properly check +for and create a clause 45 MDIO command. + +Check the supplied MDIO register to determine if the request is a clause +45 operation (MII_ADDR_C45). For a clause 45 operation, extract the device +address and register number from the supplied MDIO register and use them +to set the MDIO command request device address and register number fields. +For a clause 22 operation, the MDIO request device address is set to zero +and the MDIO command request register number is set to the supplied MDIO +register. In either case, the supplied MDIO port address is used as the +MDIO command request port address. + +Fixes: 732f2ab7afb9 ("amd-xgbe: Add support for MDIO attached PHYs") +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Tested-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-common.h | 2 -- + drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 22 ++++++++++++++++------ + 2 files changed, 16 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h +index d272dc6..b40d437 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h +@@ -431,8 +431,6 @@ + #define MAC_MDIOSCAR_PA_WIDTH 5 + #define MAC_MDIOSCAR_RA_INDEX 0 + #define MAC_MDIOSCAR_RA_WIDTH 16 +-#define MAC_MDIOSCAR_REG_INDEX 0 +-#define MAC_MDIOSCAR_REG_WIDTH 21 + #define MAC_MDIOSCCDR_BUSY_INDEX 22 + #define MAC_MDIOSCCDR_BUSY_WIDTH 1 + #define MAC_MDIOSCCDR_CMD_INDEX 16 +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +index 1e929a1..4666084 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +@@ -1284,6 +1284,20 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, + } + } + ++static unsigned int xgbe_create_mdio_sca(int port, int reg) ++{ ++ unsigned int mdio_sca, da; ++ ++ da = (reg & MII_ADDR_C45) ? reg >> 16 : 0; ++ ++ mdio_sca = 0; ++ XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); ++ XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); ++ XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da); ++ ++ return mdio_sca; ++} ++ + static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, + int reg, u16 val) + { +@@ -1291,9 +1305,7 @@ static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, + + reinit_completion(&pdata->mdio_complete); + +- mdio_sca = 0; +- XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); +- XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); ++ mdio_sca = xgbe_create_mdio_sca(addr, reg); + XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); + + mdio_sccd = 0; +@@ -1317,9 +1329,7 @@ static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, + + reinit_completion(&pdata->mdio_complete); + +- mdio_sca = 0; +- XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, REG, reg); +- XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, addr); ++ mdio_sca = xgbe_create_mdio_sca(addr, reg); + XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); + + mdio_sccd = 0; +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5751-Revert-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5751-Revert-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode.patch new file mode 100644 index 00000000..7f4bd6c4 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5751-Revert-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode.patch @@ -0,0 +1,36 @@ +From 824b82e5e9352acec85917a8e400e472f55a07d9 Mon Sep 17 00:00:00 2001 +From: Raveendra Talabattula <raveendra.talabattula@amd.com> +Date: Thu, 10 Jan 2019 16:22:35 +0530 +Subject: [PATCH 5751/5758] Revert drm/amdgpu: make gfx9 enter into rlc safe + mode when set + +Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index ce4bb14..ac2a843 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3605,8 +3605,6 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + { + uint32_t data, def; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); +- + /* It is disabled by HW by default */ + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { + /* 1 - RLC_CGTT_MGCG_OVERRIDE */ +@@ -3671,8 +3669,6 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); + } + } +- +- amdgpu_gfx_rlc_exit_safe_mode(adev); + } + + static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5752-Revert-drm-amdgpu-abstract-the-function-of-enter-exi.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5752-Revert-drm-amdgpu-abstract-the-function-of-enter-exi.patch new file mode 100644 index 00000000..a710b553 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5752-Revert-drm-amdgpu-abstract-the-function-of-enter-exi.patch @@ -0,0 +1,1446 @@ +From f3f4335f739ced7a8c0545b5455893a8a85387f4 Mon Sep 17 00:00:00 2001 +From: Raveendra Talabattula <raveendra.talabattula@amd.com> +Date: Thu, 10 Jan 2019 16:23:30 +0530 +Subject: [PATCH 5752/5758] Revert drm/amdgpu: abstract the function of + enter/exit safe mode + +Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 229 +-------------------- + drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 33 ++- + drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 +- + drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 24 ++- + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 148 ++++++++++--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 201 ++++++++++++------ + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 183 ++++++++++++---- + drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 6 +- + .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 12 +- + .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 36 ++-- + 10 files changed, 470 insertions(+), 408 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c +index c8793e6..c5459ab 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c +@@ -1,3 +1,4 @@ ++ + /* + * Copyright 2014 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. +@@ -22,238 +23,12 @@ + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +-#include <linux/firmware.h> ++ + #include "amdgpu.h" + #include "amdgpu_gfx.h" + #include "amdgpu_rlc.h" + + /** +- * amdgpu_gfx_rlc_enter_safe_mode - Set RLC into safe mode +- * +- * @adev: amdgpu_device pointer +- * +- * Set RLC enter into safe mode if RLC is enabled and haven't in safe mode. +- */ +-void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev) +-{ +- if (adev->gfx.rlc.in_safe_mode) +- return; +- +- /* if RLC is not enabled, do nothing */ +- if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) +- return; +- +- if (adev->cg_flags & +- (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | +- AMD_CG_SUPPORT_GFX_3D_CGCG)) { +- adev->gfx.rlc.funcs->set_safe_mode(adev); +- adev->gfx.rlc.in_safe_mode = true; +- } +-} +- +-/** +- * amdgpu_gfx_rlc_exit_safe_mode - Set RLC out of safe mode +- * +- * @adev: amdgpu_device pointer +- * +- * Set RLC exit safe mode if RLC is enabled and have entered into safe mode. +- */ +-void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev) +-{ +- if (!(adev->gfx.rlc.in_safe_mode)) +- return; +- +- /* if RLC is not enabled, do nothing */ +- if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) +- return; +- +- if (adev->cg_flags & +- (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | +- AMD_CG_SUPPORT_GFX_3D_CGCG)) { +- adev->gfx.rlc.funcs->unset_safe_mode(adev); +- adev->gfx.rlc.in_safe_mode = false; +- } +-} +- +-/** +- * amdgpu_gfx_rlc_init_sr - Init save restore block +- * +- * @adev: amdgpu_device pointer +- * @dws: the size of save restore block +- * +- * Allocate and setup value to save restore block of rlc. +- * Returns 0 on succeess or negative error code if allocate failed. +- */ +-int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws) +-{ +- const u32 *src_ptr; +- volatile u32 *dst_ptr; +- u32 i; +- int r; +- +- /* allocate save restore block */ +- r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, +- AMDGPU_GEM_DOMAIN_VRAM, +- &adev->gfx.rlc.save_restore_obj, +- &adev->gfx.rlc.save_restore_gpu_addr, +- (void **)&adev->gfx.rlc.sr_ptr); +- if (r) { +- dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); +- amdgpu_gfx_rlc_fini(adev); +- return r; +- } +- +- /* write the sr buffer */ +- src_ptr = adev->gfx.rlc.reg_list; +- dst_ptr = adev->gfx.rlc.sr_ptr; +- for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) +- dst_ptr[i] = cpu_to_le32(src_ptr[i]); +- amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); +- amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); +- +- return 0; +-} +- +-/** +- * amdgpu_gfx_rlc_init_csb - Init clear state block +- * +- * @adev: amdgpu_device pointer +- * +- * Allocate and setup value to clear state block of rlc. +- * Returns 0 on succeess or negative error code if allocate failed. +- */ +-int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev) +-{ +- volatile u32 *dst_ptr; +- u32 dws; +- int r; +- +- /* allocate clear state block */ +- adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); +- r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, +- AMDGPU_GEM_DOMAIN_VRAM, +- &adev->gfx.rlc.clear_state_obj, +- &adev->gfx.rlc.clear_state_gpu_addr, +- (void **)&adev->gfx.rlc.cs_ptr); +- if (r) { +- dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", r); +- amdgpu_gfx_rlc_fini(adev); +- return r; +- } +- +- /* set up the cs buffer */ +- dst_ptr = adev->gfx.rlc.cs_ptr; +- adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr); +- amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); +- amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); +- amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); +- +- return 0; +-} +- +-/** +- * amdgpu_gfx_rlc_init_cpt - Init cp table +- * +- * @adev: amdgpu_device pointer +- * +- * Allocate and setup value to cp table of rlc. +- * Returns 0 on succeess or negative error code if allocate failed. +- */ +-int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev) +-{ +- int r; +- +- r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, +- PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, +- &adev->gfx.rlc.cp_table_obj, +- &adev->gfx.rlc.cp_table_gpu_addr, +- (void **)&adev->gfx.rlc.cp_table_ptr); +- if (r) { +- dev_err(adev->dev, "(%d) failed to create cp table bo\n", r); +- amdgpu_gfx_rlc_fini(adev); +- return r; +- } +- +- /* set up the cp table */ +- amdgpu_gfx_rlc_setup_cp_table(adev); +- amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); +- amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); +- +- return 0; +-} +- +-/** +- * amdgpu_gfx_rlc_setup_cp_table - setup cp the buffer of cp table +- * +- * @adev: amdgpu_device pointer +- * +- * Write cp firmware data into cp table. +- */ +-void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev) +-{ +- const __le32 *fw_data; +- volatile u32 *dst_ptr; +- int me, i, max_me; +- u32 bo_offset = 0; +- u32 table_offset, table_size; +- +- max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev); +- +- /* write the cp table buffer */ +- dst_ptr = adev->gfx.rlc.cp_table_ptr; +- for (me = 0; me < max_me; me++) { +- if (me == 0) { +- const struct gfx_firmware_header_v1_0 *hdr = +- (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; +- fw_data = (const __le32 *) +- (adev->gfx.ce_fw->data + +- le32_to_cpu(hdr->header.ucode_array_offset_bytes)); +- table_offset = le32_to_cpu(hdr->jt_offset); +- table_size = le32_to_cpu(hdr->jt_size); +- } else if (me == 1) { +- const struct gfx_firmware_header_v1_0 *hdr = +- (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; +- fw_data = (const __le32 *) +- (adev->gfx.pfp_fw->data + +- le32_to_cpu(hdr->header.ucode_array_offset_bytes)); +- table_offset = le32_to_cpu(hdr->jt_offset); +- table_size = le32_to_cpu(hdr->jt_size); +- } else if (me == 2) { +- const struct gfx_firmware_header_v1_0 *hdr = +- (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; +- fw_data = (const __le32 *) +- (adev->gfx.me_fw->data + +- le32_to_cpu(hdr->header.ucode_array_offset_bytes)); +- table_offset = le32_to_cpu(hdr->jt_offset); +- table_size = le32_to_cpu(hdr->jt_size); +- } else if (me == 3) { +- const struct gfx_firmware_header_v1_0 *hdr = +- (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; +- fw_data = (const __le32 *) +- (adev->gfx.mec_fw->data + +- le32_to_cpu(hdr->header.ucode_array_offset_bytes)); +- table_offset = le32_to_cpu(hdr->jt_offset); +- table_size = le32_to_cpu(hdr->jt_size); +- } else if (me == 4) { +- const struct gfx_firmware_header_v1_0 *hdr = +- (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; +- fw_data = (const __le32 *) +- (adev->gfx.mec2_fw->data + +- le32_to_cpu(hdr->header.ucode_array_offset_bytes)); +- table_offset = le32_to_cpu(hdr->jt_offset); +- table_size = le32_to_cpu(hdr->jt_size); +- } +- +- for (i = 0; i < table_size; i ++) { +- dst_ptr[bo_offset + i] = +- cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); +- } +- +- bo_offset += table_size; +- } +-} +- +-/** + * amdgpu_gfx_rlc_fini - Free BO which used for RLC + * + * @adev: amdgpu_device pointer +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +index 49a8ab5..b3b0920 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +@@ -1,3 +1,4 @@ ++ + /* + * Copyright 2014 Advanced Micro Devices, Inc. + * +@@ -27,13 +28,9 @@ + #include "clearstate_defs.h" + + struct amdgpu_rlc_funcs { +- bool (*is_rlc_enabled)(struct amdgpu_device *adev); +- void (*set_safe_mode)(struct amdgpu_device *adev); +- void (*unset_safe_mode)(struct amdgpu_device *adev); ++ void (*enter_safe_mode)(struct amdgpu_device *adev); ++ void (*exit_safe_mode)(struct amdgpu_device *adev); + int (*init)(struct amdgpu_device *adev); +- u32 (*get_csb_size)(struct amdgpu_device *adev); +- void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer); +- int (*get_cp_table_num)(struct amdgpu_device *adev); + int (*resume)(struct amdgpu_device *adev); + void (*stop)(struct amdgpu_device *adev); + void (*reset)(struct amdgpu_device *adev); +@@ -42,21 +39,21 @@ struct amdgpu_rlc_funcs { + + struct amdgpu_rlc { + /* for power gating */ +- struct amdgpu_bo *save_restore_obj; +- uint64_t save_restore_gpu_addr; +- volatile uint32_t *sr_ptr; ++ struct amdgpu_bo *save_restore_obj; ++ uint64_t save_restore_gpu_addr; ++ volatile uint32_t *sr_ptr; + const u32 *reg_list; + u32 reg_list_size; + /* for clear state */ +- struct amdgpu_bo *clear_state_obj; +- uint64_t clear_state_gpu_addr; +- volatile uint32_t *cs_ptr; ++ struct amdgpu_bo *clear_state_obj; ++ uint64_t clear_state_gpu_addr; ++ volatile uint32_t *cs_ptr; + const struct cs_section_def *cs_data; + u32 clear_state_size; + /* for cp tables */ +- struct amdgpu_bo *cp_table_obj; +- uint64_t cp_table_gpu_addr; +- volatile uint32_t *cp_table_ptr; ++ struct amdgpu_bo *cp_table_obj; ++ uint64_t cp_table_gpu_addr; ++ volatile uint32_t *cp_table_ptr; + u32 cp_table_size; + + /* safe mode for updating CG/PG state */ +@@ -87,12 +84,6 @@ struct amdgpu_rlc { + bool is_rlc_v2_1; + }; + +-void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev); +-void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev); +-int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws); +-int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev); +-int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev); +-void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev); + void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev); + + #endif +diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +index e02631d..ecd69ab 100644 +--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +@@ -743,19 +743,19 @@ static int ci_enable_didt(struct amdgpu_device *adev, bool enable) + + if (pi->caps_sq_ramping || pi->caps_db_ramping || + pi->caps_td_ramping || pi->caps_tcp_ramping) { +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + if (enable) { + ret = ci_program_pt_config_registers(adev, didt_config_ci); + if (ret) { +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + return ret; + } + } + + ci_do_enable_didt(adev, enable); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +index 075407e..abc8ec6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +@@ -2401,7 +2401,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) + { + const u32 *src_ptr; + volatile u32 *dst_ptr; +- u32 dws; ++ u32 dws, i; + u64 reg_list_mc_addr; + const struct cs_section_def *cs_data; + int r; +@@ -2416,10 +2416,26 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) + cs_data = adev->gfx.rlc.cs_data; + + if (src_ptr) { +- /* init save restore block */ +- r = amdgpu_gfx_rlc_init_sr(adev, dws); +- if (r) ++ /* save restore block */ ++ r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, ++ AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.save_restore_obj, ++ &adev->gfx.rlc.save_restore_gpu_addr, ++ (void **)&adev->gfx.rlc.sr_ptr); ++ if (r) { ++ dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", ++ r); ++ amdgpu_gfx_rlc_fini(adev); + return r; ++ } ++ ++ /* write the sr buffer */ ++ dst_ptr = adev->gfx.rlc.sr_ptr; ++ for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) ++ dst_ptr[i] = cpu_to_le32(src_ptr[i]); ++ ++ amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); + } + + if (cs_data) { +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +index 6815153..19a0e4f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +@@ -882,6 +882,7 @@ static const u32 kalindi_rlc_save_restore_register_list[] = + + static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); + static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); ++static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); + static void gfx_v7_0_init_pg(struct amdgpu_device *adev); + static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); + +@@ -3290,7 +3291,8 @@ static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, + static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) + { + const u32 *src_ptr; +- u32 dws; ++ volatile u32 *dst_ptr; ++ u32 dws, i; + const struct cs_section_def *cs_data; + int r; + +@@ -3317,23 +3319,66 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) + cs_data = adev->gfx.rlc.cs_data; + + if (src_ptr) { +- /* init save restore block */ +- r = amdgpu_gfx_rlc_init_sr(adev, dws); +- if (r) ++ /* save restore block */ ++ r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, ++ AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.save_restore_obj, ++ &adev->gfx.rlc.save_restore_gpu_addr, ++ (void **)&adev->gfx.rlc.sr_ptr); ++ if (r) { ++ dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r); ++ amdgpu_gfx_rlc_fini(adev); + return r; ++ } ++ ++ /* write the sr buffer */ ++ dst_ptr = adev->gfx.rlc.sr_ptr; ++ for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) ++ dst_ptr[i] = cpu_to_le32(src_ptr[i]); ++ amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); + } + + if (cs_data) { +- /* init clear state block */ +- r = amdgpu_gfx_rlc_init_csb(adev); +- if (r) ++ /* clear state block */ ++ adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); ++ ++ r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, ++ AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.clear_state_obj, ++ &adev->gfx.rlc.clear_state_gpu_addr, ++ (void **)&adev->gfx.rlc.cs_ptr); ++ if (r) { ++ dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); ++ amdgpu_gfx_rlc_fini(adev); + return r; ++ } ++ ++ /* set up the cs buffer */ ++ dst_ptr = adev->gfx.rlc.cs_ptr; ++ gfx_v7_0_get_csb_buffer(adev, dst_ptr); ++ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + } + + if (adev->gfx.rlc.cp_table_size) { +- r = amdgpu_gfx_rlc_init_cpt(adev); +- if (r) ++ ++ r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, ++ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.cp_table_obj, ++ &adev->gfx.rlc.cp_table_gpu_addr, ++ (void **)&adev->gfx.rlc.cp_table_ptr); ++ if (r) { ++ dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); ++ amdgpu_gfx_rlc_fini(adev); + return r; ++ } ++ ++ gfx_v7_0_init_cp_pg_table(adev); ++ ++ amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); ++ + } + + return 0; +@@ -3414,12 +3459,7 @@ static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) + return orig; + } + +-static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) +-{ +- return true; +-} +- +-static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev) ++static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) + { + u32 tmp, i, mask; + +@@ -3441,7 +3481,7 @@ static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev) + } + } + +-static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev) ++static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) + { + u32 tmp; + +@@ -3757,12 +3797,72 @@ static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) + WREG32(mmRLC_PG_CNTL, data); + } + +-static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev) ++static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) + { ++ const __le32 *fw_data; ++ volatile u32 *dst_ptr; ++ int me, i, max_me = 4; ++ u32 bo_offset = 0; ++ u32 table_offset, table_size; ++ + if (adev->asic_type == CHIP_KAVERI) +- return 5; +- else +- return 4; ++ max_me = 5; ++ ++ if (adev->gfx.rlc.cp_table_ptr == NULL) ++ return; ++ ++ /* write the cp table buffer */ ++ dst_ptr = adev->gfx.rlc.cp_table_ptr; ++ for (me = 0; me < max_me; me++) { ++ if (me == 0) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.ce_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 1) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.pfp_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 2) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.me_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 3) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.mec_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.mec2_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } ++ ++ for (i = 0; i < table_size; i ++) { ++ dst_ptr[bo_offset + i] = ++ cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); ++ } ++ ++ bo_offset += table_size; ++ } + } + + static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, +@@ -4201,12 +4301,8 @@ static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { + }; + + static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { +- .is_rlc_enabled = gfx_v7_0_is_rlc_enabled, +- .set_safe_mode = gfx_v7_0_set_safe_mode, +- .unset_safe_mode = gfx_v7_0_unset_safe_mode, +- .get_csb_size = gfx_v7_0_get_csb_size, +- .get_csb_buffer = gfx_v7_0_get_csb_buffer, +- .get_cp_table_num = gfx_v7_0_cp_pg_table_num, ++ .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode, ++ .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode + }; + + static int gfx_v7_0_early_init(void *handle) +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 43272fb..3ec5832 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -1298,16 +1298,75 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, + buffer[count++] = cpu_to_le32(0); + } + +-static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev) ++static void cz_init_cp_jump_table(struct amdgpu_device *adev) + { ++ const __le32 *fw_data; ++ volatile u32 *dst_ptr; ++ int me, i, max_me = 4; ++ u32 bo_offset = 0; ++ u32 table_offset, table_size; ++ + if (adev->asic_type == CHIP_CARRIZO) +- return 5; +- else +- return 4; ++ max_me = 5; ++ ++ /* write the cp table buffer */ ++ dst_ptr = adev->gfx.rlc.cp_table_ptr; ++ for (me = 0; me < max_me; me++) { ++ if (me == 0) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.ce_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 1) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.pfp_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 2) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.me_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 3) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.mec_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 4) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.mec2_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } ++ ++ for (i = 0; i < table_size; i ++) { ++ dst_ptr[bo_offset + i] = ++ cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); ++ } ++ ++ bo_offset += table_size; ++ } + } + + static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) + { ++ volatile u32 *dst_ptr; ++ u32 dws; + const struct cs_section_def *cs_data; + int r; + +@@ -1316,18 +1375,44 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) + cs_data = adev->gfx.rlc.cs_data; + + if (cs_data) { +- /* init clear state block */ +- r = amdgpu_gfx_rlc_init_csb(adev); +- if (r) ++ /* clear state block */ ++ adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); ++ ++ r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, ++ AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.clear_state_obj, ++ &adev->gfx.rlc.clear_state_gpu_addr, ++ (void **)&adev->gfx.rlc.cs_ptr); ++ if (r) { ++ dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); ++ amdgpu_gfx_rlc_fini(adev); + return r; ++ } ++ ++ /* set up the cs buffer */ ++ dst_ptr = adev->gfx.rlc.cs_ptr; ++ gfx_v8_0_get_csb_buffer(adev, dst_ptr); ++ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + } + + if ((adev->asic_type == CHIP_CARRIZO) || + (adev->asic_type == CHIP_STONEY)) { + adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ +- r = amdgpu_gfx_rlc_init_cpt(adev); +- if (r) ++ r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, ++ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.cp_table_obj, ++ &adev->gfx.rlc.cp_table_gpu_addr, ++ (void **)&adev->gfx.rlc.cp_table_ptr); ++ if (r) { ++ dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); + return r; ++ } ++ ++ cz_init_cp_jump_table(adev); ++ ++ amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); + } + + return 0; +@@ -4880,7 +4965,7 @@ static int gfx_v8_0_hw_fini(void *handle) + pr_debug("For SRIOV client, shouldn't do anything.\n"); + return 0; + } +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + if (!gfx_v8_0_wait_for_idle(adev)) + gfx_v8_0_cp_enable(adev, false); + else +@@ -4889,7 +4974,7 @@ static int gfx_v8_0_hw_fini(void *handle) + gfx_v8_0_rlc_stop(adev); + else + pr_err("rlc is busy, skip halt rlc\n"); +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + return 0; + } + +@@ -5352,7 +5437,7 @@ static int gfx_v8_0_set_powergating_state(void *handle, + AMD_PG_SUPPORT_RLC_SMU_HS | + AMD_PG_SUPPORT_CP | + AMD_PG_SUPPORT_GFX_DMG)) +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + switch (adev->asic_type) { + case CHIP_CARRIZO: + case CHIP_STONEY: +@@ -5406,7 +5491,7 @@ static int gfx_v8_0_set_powergating_state(void *handle, + AMD_PG_SUPPORT_RLC_SMU_HS | + AMD_PG_SUPPORT_CP | + AMD_PG_SUPPORT_GFX_DMG)) +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + return 0; + } + +@@ -5500,53 +5585,57 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev, + #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001 + #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e + +-static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev) ++static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev) + { +- uint32_t rlc_setting; ++ u32 data; ++ unsigned i; + +- rlc_setting = RREG32(mmRLC_CNTL); +- if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) +- return false; ++ data = RREG32(mmRLC_CNTL); ++ if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK)) ++ return; + +- return true; +-} ++ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { ++ data |= RLC_SAFE_MODE__CMD_MASK; ++ data &= ~RLC_SAFE_MODE__MESSAGE_MASK; ++ data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); ++ WREG32(mmRLC_SAFE_MODE, data); + +-static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev) +-{ +- uint32_t data; +- unsigned i; +- data = RREG32(mmRLC_CNTL); +- data |= RLC_SAFE_MODE__CMD_MASK; +- data &= ~RLC_SAFE_MODE__MESSAGE_MASK; +- data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); +- WREG32(mmRLC_SAFE_MODE, data); ++ for (i = 0; i < adev->usec_timeout; i++) { ++ if ((RREG32(mmRLC_GPM_STAT) & ++ (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | ++ RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) == ++ (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | ++ RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ++ break; ++ udelay(1); ++ } + +- /* wait for RLC_SAFE_MODE */ +- for (i = 0; i < adev->usec_timeout; i++) { +- if ((RREG32(mmRLC_GPM_STAT) & +- (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | +- RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) == +- (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | +- RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) +- break; +- udelay(1); +- } +- for (i = 0; i < adev->usec_timeout; i++) { +- if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) +- break; +- udelay(1); ++ for (i = 0; i < adev->usec_timeout; i++) { ++ if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) ++ break; ++ udelay(1); ++ } ++ adev->gfx.rlc.in_safe_mode = true; + } + } + +-static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev) ++static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev) + { +- uint32_t data; ++ u32 data = 0; + unsigned i; + + data = RREG32(mmRLC_CNTL); +- data |= RLC_SAFE_MODE__CMD_MASK; +- data &= ~RLC_SAFE_MODE__MESSAGE_MASK; +- WREG32(mmRLC_SAFE_MODE, data); ++ if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK)) ++ return; ++ ++ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { ++ if (adev->gfx.rlc.in_safe_mode) { ++ data |= RLC_SAFE_MODE__CMD_MASK; ++ data &= ~RLC_SAFE_MODE__MESSAGE_MASK; ++ WREG32(mmRLC_SAFE_MODE, data); ++ adev->gfx.rlc.in_safe_mode = false; ++ } ++ } + + for (i = 0; i < adev->usec_timeout; i++) { + if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) +@@ -5556,12 +5645,8 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev) + } + + static const struct amdgpu_rlc_funcs iceland_rlc_funcs = { +- .is_rlc_enabled = gfx_v8_0_is_rlc_enabled, +- .set_safe_mode = gfx_v8_0_set_safe_mode, +- .unset_safe_mode = gfx_v8_0_unset_safe_mode, +- .get_csb_size = gfx_v8_0_get_csb_size, +- .get_csb_buffer = gfx_v8_0_get_csb_buffer, +- .get_cp_table_num = gfx_v8_0_cp_jump_table_num, ++ .enter_safe_mode = iceland_enter_rlc_safe_mode, ++ .exit_safe_mode = iceland_exit_rlc_safe_mode + }; + + static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, +@@ -5569,7 +5654,7 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + { + uint32_t temp, data; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + /* It is disabled by HW by default */ + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { +@@ -5665,7 +5750,7 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + gfx_v8_0_wait_for_rlc_serdes(adev); + } + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, +@@ -5675,7 +5760,7 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev + + temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL); + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { + temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); +@@ -5758,7 +5843,7 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev + + gfx_v8_0_wait_for_rlc_serdes(adev); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev, + bool enable) +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index ac2a843..69fcc77 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1079,13 +1079,72 @@ static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) + WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); + } + +-static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) ++static void rv_init_cp_jump_table(struct amdgpu_device *adev) + { +- return 5; ++ const __le32 *fw_data; ++ volatile u32 *dst_ptr; ++ int me, i, max_me = 5; ++ u32 bo_offset = 0; ++ u32 table_offset, table_size; ++ ++ /* write the cp table buffer */ ++ dst_ptr = adev->gfx.rlc.cp_table_ptr; ++ for (me = 0; me < max_me; me++) { ++ if (me == 0) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.ce_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 1) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.pfp_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 2) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.me_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 3) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.mec_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } else if (me == 4) { ++ const struct gfx_firmware_header_v1_0 *hdr = ++ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; ++ fw_data = (const __le32 *) ++ (adev->gfx.mec2_fw->data + ++ le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ table_offset = le32_to_cpu(hdr->jt_offset); ++ table_size = le32_to_cpu(hdr->jt_size); ++ } ++ ++ for (i = 0; i < table_size; i ++) { ++ dst_ptr[bo_offset + i] = ++ cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); ++ } ++ ++ bo_offset += table_size; ++ } + } + + static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) + { ++ volatile u32 *dst_ptr; ++ u32 dws; + const struct cs_section_def *cs_data; + int r; + +@@ -1094,18 +1153,45 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) + cs_data = adev->gfx.rlc.cs_data; + + if (cs_data) { +- /* init clear state block */ +- r = amdgpu_gfx_rlc_init_csb(adev); +- if (r) ++ /* clear state block */ ++ adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); ++ r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, ++ AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.clear_state_obj, ++ &adev->gfx.rlc.clear_state_gpu_addr, ++ (void **)&adev->gfx.rlc.cs_ptr); ++ if (r) { ++ dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", ++ r); ++ amdgpu_gfx_rlc_fini(adev); + return r; ++ } ++ /* set up the cs buffer */ ++ dst_ptr = adev->gfx.rlc.cs_ptr; ++ gfx_v9_0_get_csb_buffer(adev, dst_ptr); ++ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); ++ amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + } + + if (adev->asic_type == CHIP_RAVEN) { + /* TODO: double check the cp_table_size for RV */ + adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ +- r = amdgpu_gfx_rlc_init_cpt(adev); +- if (r) ++ r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, ++ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, ++ &adev->gfx.rlc.cp_table_obj, ++ &adev->gfx.rlc.cp_table_gpu_addr, ++ (void **)&adev->gfx.rlc.cp_table_ptr); ++ if (r) { ++ dev_err(adev->dev, ++ "(%d) failed to create cp table bo\n", r); ++ amdgpu_gfx_rlc_fini(adev); + return r; ++ } ++ ++ rv_init_cp_jump_table(adev); ++ amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); + } + + switch (adev->asic_type) { +@@ -3527,47 +3613,64 @@ static int gfx_v9_0_late_init(void *handle) + return 0; + } + +-static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) ++static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev) + { +- uint32_t rlc_setting; ++ uint32_t rlc_setting, data; ++ unsigned i; ++ ++ if (adev->gfx.rlc.in_safe_mode) ++ return; + + /* if RLC is not enabled, do nothing */ + rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); + if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) +- return false; +- +- return true; +-} +- +-static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) +-{ +- uint32_t data; +- unsigned i; ++ return; + +- data = RLC_SAFE_MODE__CMD_MASK; +- data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); +- WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); ++ if (adev->cg_flags & ++ (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | ++ AMD_CG_SUPPORT_GFX_3D_CGCG)) { ++ data = RLC_SAFE_MODE__CMD_MASK; ++ data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); ++ WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); + +- /* wait for RLC_SAFE_MODE */ +- for (i = 0; i < adev->usec_timeout; i++) { +- if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) +- break; +- udelay(1); ++ /* wait for RLC_SAFE_MODE */ ++ for (i = 0; i < adev->usec_timeout; i++) { ++ if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) ++ break; ++ udelay(1); ++ } ++ adev->gfx.rlc.in_safe_mode = true; + } + } + +-static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) ++static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) + { +- uint32_t data; ++ uint32_t rlc_setting, data; ++ ++ if (!adev->gfx.rlc.in_safe_mode) ++ return; ++ ++ /* if RLC is not enabled, do nothing */ ++ rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); ++ if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) ++ return; + +- data = RLC_SAFE_MODE__CMD_MASK; +- WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); ++ if (adev->cg_flags & ++ (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { ++ /* ++ * Try to exit safe mode only if it is already in safe ++ * mode. ++ */ ++ data = RLC_SAFE_MODE__CMD_MASK; ++ WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); ++ adev->gfx.rlc.in_safe_mode = false; ++ } + } + + static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, + bool enable) + { +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ gfx_v9_0_enter_rlc_safe_mode(adev); + + if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { + gfx_v9_0_enable_gfx_cg_power_gating(adev, true); +@@ -3578,7 +3681,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, + gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); + } + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ gfx_v9_0_exit_rlc_safe_mode(adev); + } + + static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, +@@ -3676,7 +3779,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, + { + uint32_t data, def; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + /* Enable 3D CGCG/CGLS */ + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { +@@ -3716,7 +3819,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, + WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); + } + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, +@@ -3724,7 +3827,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev + { + uint32_t def, data; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { + def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); +@@ -3764,7 +3867,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev + WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); + } + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, +@@ -3793,12 +3896,8 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, + } + + static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { +- .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, +- .set_safe_mode = gfx_v9_0_set_safe_mode, +- .unset_safe_mode = gfx_v9_0_unset_safe_mode, +- .get_csb_size = gfx_v9_0_get_csb_size, +- .get_csb_buffer = gfx_v9_0_get_csb_buffer, +- .get_cp_table_num = gfx_v9_0_cp_jump_table_num, ++ .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, ++ .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode + }; + + static int gfx_v9_0_set_powergating_state(void *handle, +diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +index 36bcba96..faf06fd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +@@ -508,19 +508,19 @@ static int kv_enable_didt(struct amdgpu_device *adev, bool enable) + pi->caps_db_ramping || + pi->caps_td_ramping || + pi->caps_tcp_ramping) { +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + if (enable) { + ret = kv_program_pt_config_registers(adev, didt_config_kv); + if (ret) { +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + return ret; + } + } + + kv_do_enable_didt(adev, enable); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + return 0; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +index d138ddae..5e19f59 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +@@ -967,7 +967,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) + PP_CAP(PHM_PlatformCaps_TDRamping) || + PP_CAP(PHM_PlatformCaps_TCPRamping)) { + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + mutex_lock(&adev->grbm_idx_mutex); + value = 0; + value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); +@@ -1014,13 +1014,13 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr) + "Failed to enable DPM DIDT.", goto error); + } + mutex_unlock(&adev->grbm_idx_mutex); +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + return 0; + error: + mutex_unlock(&adev->grbm_idx_mutex); +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + return result; + } + +@@ -1034,7 +1034,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) + PP_CAP(PHM_PlatformCaps_TDRamping) || + PP_CAP(PHM_PlatformCaps_TCPRamping)) { + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + result = smu7_enable_didt(hwmgr, false); + PP_ASSERT_WITH_CODE((result == 0), +@@ -1046,12 +1046,12 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) + PP_ASSERT_WITH_CODE((0 == result), + "Failed to disable DPM DIDT.", goto error); + } +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + return 0; + error: +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + return result; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +index 6f26cb2..2d88abf 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +@@ -937,7 +937,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) + + num_se = adev->gfx.config.max_shader_engines; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + mutex_lock(&adev->grbm_idx_mutex); + for (count = 0; count < num_se; count++) { +@@ -962,7 +962,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) + + vega10_didt_set_mask(hwmgr, true); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + return 0; + } +@@ -971,11 +971,11 @@ static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) + { + struct amdgpu_device *adev = hwmgr->adev; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + vega10_didt_set_mask(hwmgr, false); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + return 0; + } +@@ -988,7 +988,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) + + num_se = adev->gfx.config.max_shader_engines; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + mutex_lock(&adev->grbm_idx_mutex); + for (count = 0; count < num_se; count++) { +@@ -1007,7 +1007,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) + + vega10_didt_set_mask(hwmgr, true); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10); + if (PP_CAP(PHM_PlatformCaps_GCEDC)) +@@ -1024,11 +1024,11 @@ static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) + struct amdgpu_device *adev = hwmgr->adev; + uint32_t data; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + vega10_didt_set_mask(hwmgr, false); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + if (PP_CAP(PHM_PlatformCaps_GCEDC)) { + data = 0x00000000; +@@ -1049,7 +1049,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) + + num_se = adev->gfx.config.max_shader_engines; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + mutex_lock(&adev->grbm_idx_mutex); + for (count = 0; count < num_se; count++) { +@@ -1070,7 +1070,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) + + vega10_didt_set_mask(hwmgr, true); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + return 0; + } +@@ -1079,11 +1079,11 @@ static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr) + { + struct amdgpu_device *adev = hwmgr->adev; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + vega10_didt_set_mask(hwmgr, false); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + return 0; + } +@@ -1097,7 +1097,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) + + num_se = adev->gfx.config.max_shader_engines; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); + +@@ -1118,7 +1118,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) + + vega10_didt_set_mask(hwmgr, true); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10); + +@@ -1138,11 +1138,11 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) + struct amdgpu_device *adev = hwmgr->adev; + uint32_t data; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + vega10_didt_set_mask(hwmgr, false); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + if (PP_CAP(PHM_PlatformCaps_GCEDC)) { + data = 0x00000000; +@@ -1160,7 +1160,7 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) + struct amdgpu_device *adev = hwmgr->adev; + int result; + +- amdgpu_gfx_rlc_enter_safe_mode(adev); ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); + + mutex_lock(&adev->grbm_idx_mutex); + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); +@@ -1173,7 +1173,7 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) + + vega10_didt_set_mask(hwmgr, false); + +- amdgpu_gfx_rlc_exit_safe_mode(adev); ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + + return 0; + } +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5753-Revert-drm-amdgpu-separate-amdgpu_rlc-into-a-single-.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5753-Revert-drm-amdgpu-separate-amdgpu_rlc-into-a-single-.patch new file mode 100644 index 00000000..efa60695 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5753-Revert-drm-amdgpu-separate-amdgpu_rlc-into-a-single-.patch @@ -0,0 +1,454 @@ +From bfaff79812373e4bb7f52dc09bb21a2c5a6e7d2f Mon Sep 17 00:00:00 2001 +From: Raveendra Talabattula <raveendra.talabattula@amd.com> +Date: Thu, 10 Jan 2019 16:24:27 +0530 +Subject: [PATCH 5753/5758] Revert drm/amdgpu: separate amdgpu_rlc into a + single file + +Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 1 - + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 1 - + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 54 +++++++++++++++++++- + drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 57 --------------------- + drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 89 --------------------------------- + drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 13 +++-- + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 15 ++++-- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 ++++++- + 9 files changed, 97 insertions(+), 160 deletions(-) + delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c + delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 467125d..0b967d9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -105,7 +105,6 @@ amdgpu-y += \ + # add GFX block + amdgpu-y += \ + amdgpu_gfx.o \ +- amdgpu_rlc.o \ + gfx_v8_0.o \ + gfx_v9_0.o + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +index 54ee584..a750242 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +@@ -25,7 +25,6 @@ + #include <drm/drmP.h> + #include "amdgpu.h" + #include "amdgpu_gfx.h" +-#include "amdgpu_rlc.h" + + /* delay 0.1 second to enable gfx off feature */ + #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +index f790e15..b61b5c1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +@@ -29,7 +29,6 @@ + */ + #include "clearstate_defs.h" + #include "amdgpu_ring.h" +-#include "amdgpu_rlc.h" + + /* GFX current status */ + #define AMDGPU_GFX_NORMAL_MODE 0x00000000L +@@ -38,6 +37,59 @@ + #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L + #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L + ++ ++struct amdgpu_rlc_funcs { ++ void (*enter_safe_mode)(struct amdgpu_device *adev); ++ void (*exit_safe_mode)(struct amdgpu_device *adev); ++}; ++ ++struct amdgpu_rlc { ++ /* for power gating */ ++ struct amdgpu_bo *save_restore_obj; ++ uint64_t save_restore_gpu_addr; ++ volatile uint32_t *sr_ptr; ++ const u32 *reg_list; ++ u32 reg_list_size; ++ /* for clear state */ ++ struct amdgpu_bo *clear_state_obj; ++ uint64_t clear_state_gpu_addr; ++ volatile uint32_t *cs_ptr; ++ const struct cs_section_def *cs_data; ++ u32 clear_state_size; ++ /* for cp tables */ ++ struct amdgpu_bo *cp_table_obj; ++ uint64_t cp_table_gpu_addr; ++ volatile uint32_t *cp_table_ptr; ++ u32 cp_table_size; ++ ++ /* safe mode for updating CG/PG state */ ++ bool in_safe_mode; ++ const struct amdgpu_rlc_funcs *funcs; ++ ++ /* for firmware data */ ++ u32 save_and_restore_offset; ++ u32 clear_state_descriptor_offset; ++ u32 avail_scratch_ram_locations; ++ u32 reg_restore_list_size; ++ u32 reg_list_format_start; ++ u32 reg_list_format_separate_start; ++ u32 starting_offsets_start; ++ u32 reg_list_format_size_bytes; ++ u32 reg_list_size_bytes; ++ u32 reg_list_format_direct_reg_list_length; ++ u32 save_restore_list_cntl_size_bytes; ++ u32 save_restore_list_gpm_size_bytes; ++ u32 save_restore_list_srm_size_bytes; ++ ++ u32 *register_list_format; ++ u32 *register_restore; ++ u8 *save_restore_list_cntl; ++ u8 *save_restore_list_gpm; ++ u8 *save_restore_list_srm; ++ ++ bool is_rlc_v2_1; ++}; ++ + #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES + + struct amdgpu_mec { +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c +deleted file mode 100644 +index c5459ab..0000000 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c ++++ /dev/null +@@ -1,57 +0,0 @@ +- +-/* +- * Copyright 2014 Advanced Micro Devices, Inc. +- * Copyright 2008 Red Hat Inc. +- * Copyright 2009 Jerome Glisse. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "amdgpu.h" +-#include "amdgpu_gfx.h" +-#include "amdgpu_rlc.h" +- +-/** +- * amdgpu_gfx_rlc_fini - Free BO which used for RLC +- * +- * @adev: amdgpu_device pointer +- * +- * Free three BO which is used for rlc_save_restore_block, rlc_clear_state_block +- * and rlc_jump_table_block. +- */ +-void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev) +-{ +- /* save restore block */ +- if (adev->gfx.rlc.save_restore_obj) { +- amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, +- &adev->gfx.rlc.save_restore_gpu_addr, +- (void **)&adev->gfx.rlc.sr_ptr); +- } +- +- /* clear state block */ +- amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, +- &adev->gfx.rlc.clear_state_gpu_addr, +- (void **)&adev->gfx.rlc.cs_ptr); +- +- /* jump table block */ +- amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, +- &adev->gfx.rlc.cp_table_gpu_addr, +- (void **)&adev->gfx.rlc.cp_table_ptr); +-} +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +deleted file mode 100644 +index b3b0920..0000000 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h ++++ /dev/null +@@ -1,89 +0,0 @@ +- +-/* +- * Copyright 2014 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __AMDGPU_RLC_H__ +-#define __AMDGPU_RLC_H__ +- +-#include "clearstate_defs.h" +- +-struct amdgpu_rlc_funcs { +- void (*enter_safe_mode)(struct amdgpu_device *adev); +- void (*exit_safe_mode)(struct amdgpu_device *adev); +- int (*init)(struct amdgpu_device *adev); +- int (*resume)(struct amdgpu_device *adev); +- void (*stop)(struct amdgpu_device *adev); +- void (*reset)(struct amdgpu_device *adev); +- void (*start)(struct amdgpu_device *adev); +-}; +- +-struct amdgpu_rlc { +- /* for power gating */ +- struct amdgpu_bo *save_restore_obj; +- uint64_t save_restore_gpu_addr; +- volatile uint32_t *sr_ptr; +- const u32 *reg_list; +- u32 reg_list_size; +- /* for clear state */ +- struct amdgpu_bo *clear_state_obj; +- uint64_t clear_state_gpu_addr; +- volatile uint32_t *cs_ptr; +- const struct cs_section_def *cs_data; +- u32 clear_state_size; +- /* for cp tables */ +- struct amdgpu_bo *cp_table_obj; +- uint64_t cp_table_gpu_addr; +- volatile uint32_t *cp_table_ptr; +- u32 cp_table_size; +- +- /* safe mode for updating CG/PG state */ +- bool in_safe_mode; +- const struct amdgpu_rlc_funcs *funcs; +- +- /* for firmware data */ +- u32 save_and_restore_offset; +- u32 clear_state_descriptor_offset; +- u32 avail_scratch_ram_locations; +- u32 reg_restore_list_size; +- u32 reg_list_format_start; +- u32 reg_list_format_separate_start; +- u32 starting_offsets_start; +- u32 reg_list_format_size_bytes; +- u32 reg_list_size_bytes; +- u32 reg_list_format_direct_reg_list_length; +- u32 save_restore_list_cntl_size_bytes; +- u32 save_restore_list_gpm_size_bytes; +- u32 save_restore_list_srm_size_bytes; +- +- u32 *register_list_format; +- u32 *register_restore; +- u8 *save_restore_list_cntl; +- u8 *save_restore_list_gpm; +- u8 *save_restore_list_srm; +- +- bool is_rlc_v2_1; +-}; +- +-void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev); +- +-#endif +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +index abc8ec6..4f8d6a2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +@@ -2397,6 +2397,13 @@ static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, val); + } + ++static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev) ++{ ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); ++} ++ + static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) + { + const u32 *src_ptr; +@@ -2425,7 +2432,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) + if (r) { + dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", + r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v6_0_rlc_fini(adev); + return r; + } + +@@ -2450,7 +2457,7 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) + (void **)&adev->gfx.rlc.cs_ptr); + if (r) { + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v6_0_rlc_fini(adev); + return r; + } + +@@ -3187,7 +3194,7 @@ static int gfx_v6_0_sw_fini(void *handle) + for (i = 0; i < adev->gfx.num_compute_rings; i++) + amdgpu_ring_fini(&adev->gfx.compute_ring[i]); + +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v6_0_rlc_fini(adev); + + return 0; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +index 19a0e4f..05f7a29 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +@@ -3288,6 +3288,13 @@ static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, + * The RLC is a multi-purpose microengine that handles a + * variety of functions. + */ ++static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) ++{ ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); ++} ++ + static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) + { + const u32 *src_ptr; +@@ -3327,7 +3334,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) + (void **)&adev->gfx.rlc.sr_ptr); + if (r) { + dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v7_0_rlc_fini(adev); + return r; + } + +@@ -3350,7 +3357,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) + (void **)&adev->gfx.rlc.cs_ptr); + if (r) { + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v7_0_rlc_fini(adev); + return r; + } + +@@ -3370,7 +3377,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) + (void **)&adev->gfx.rlc.cp_table_ptr); + if (r) { + dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v7_0_rlc_fini(adev); + return r; + } + +@@ -4617,7 +4624,7 @@ static int gfx_v7_0_sw_fini(void *handle) + amdgpu_ring_fini(&adev->gfx.compute_ring[i]); + + gfx_v7_0_cp_compute_fini(adev); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v7_0_rlc_fini(adev); + gfx_v7_0_mec_fini(adev); + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 3ec5832..9619369 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -1363,6 +1363,12 @@ static void cz_init_cp_jump_table(struct amdgpu_device *adev) + } + } + ++static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) ++{ ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); ++} ++ + static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) + { + volatile u32 *dst_ptr; +@@ -1385,7 +1391,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) + (void **)&adev->gfx.rlc.cs_ptr); + if (r) { + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v8_0_rlc_fini(adev); + return r; + } + +@@ -2175,7 +2181,7 @@ static int gfx_v8_0_sw_fini(void *handle) + amdgpu_gfx_kiq_fini(adev); + + gfx_v8_0_mec_fini(adev); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v8_0_rlc_fini(adev); + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 69fcc77..0481e21 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1141,6 +1141,19 @@ static void rv_init_cp_jump_table(struct amdgpu_device *adev) + } + } + ++static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev) ++{ ++ /* clear state block */ ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, ++ &adev->gfx.rlc.clear_state_gpu_addr, ++ (void **)&adev->gfx.rlc.cs_ptr); ++ ++ /* jump table block */ ++ amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, ++ &adev->gfx.rlc.cp_table_gpu_addr, ++ (void **)&adev->gfx.rlc.cp_table_ptr); ++} ++ + static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) + { + volatile u32 *dst_ptr; +@@ -1163,7 +1176,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) + if (r) { + dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", + r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v9_0_rlc_fini(adev); + return r; + } + /* set up the cs buffer */ +@@ -1185,7 +1198,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) + if (r) { + dev_err(adev->dev, + "(%d) failed to create cp table bo\n", r); +- amdgpu_gfx_rlc_fini(adev); ++ gfx_v9_0_rlc_fini(adev); + return r; + } + +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5754-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode-when-s.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5754-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode-when-s.patch new file mode 100644 index 00000000..b5d33fb0 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5754-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode-when-s.patch @@ -0,0 +1,39 @@ +From 0c68f4fffe18d5894cb4ac2111001999f747c96e Mon Sep 17 00:00:00 2001 +From: Likun Gao <Likun.Gao@amd.com> +Date: Wed, 9 Jan 2019 10:46:48 +0800 +Subject: [PATCH 5754/5758] drm/amdgpu: make gfx9 enter into rlc safe mode when + set MGCG + +MGCG should RLC enter into safe mode first. + +Signed-off-by: Likun Gao <Likun.Gao@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 0481e21..c7db271 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3721,6 +3721,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + { + uint32_t data, def; + ++ adev->gfx.rlc.funcs->enter_safe_mode(adev); ++ + /* It is disabled by HW by default */ + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { + /* 1 - RLC_CGTT_MGCG_OVERRIDE */ +@@ -3785,6 +3787,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev + WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); + } + } ++ ++ adev->gfx.rlc.funcs->exit_safe_mode(adev); + } + + static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5755-Revert-drm-amdgpu-revert-the-commit-interim-disable-.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5755-Revert-drm-amdgpu-revert-the-commit-interim-disable-.patch new file mode 100644 index 00000000..8b6186a9 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5755-Revert-drm-amdgpu-revert-the-commit-interim-disable-.patch @@ -0,0 +1,32 @@ +From bed5590326e22b00ac99f5836c4c2f5c117fbfac Mon Sep 17 00:00:00 2001 +From: Raveendra Talabattula <raveendra.talabattula@amd.com> +Date: Thu, 10 Jan 2019 16:25:14 +0530 +Subject: [PATCH 5755/5758] Revert drm/amdgpu: revert the commit interim + disable RV2 GFX CG + +Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index a741913..5614c2b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -705,12 +705,9 @@ static int soc15_common_early_init(void *handle) + adev->external_rev_id = 0x1; + + if (adev->rev_id >= 0x8) { +- adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | +- AMD_CG_SUPPORT_GFX_MGLS | ++ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CP_LS | +- AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | +- AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_BIF_LS | + AMD_CG_SUPPORT_HDP_LS | +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5756-Revert-drm-amdgpu-revert-psp-firmware-load-status-ch.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5756-Revert-drm-amdgpu-revert-psp-firmware-load-status-ch.patch new file mode 100644 index 00000000..73e5485a --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5756-Revert-drm-amdgpu-revert-psp-firmware-load-status-ch.patch @@ -0,0 +1,32 @@ +From 0989b02cc7c434d41af054096dcf43c6b1eea297 Mon Sep 17 00:00:00 2001 +From: Raveendra Talabattula <raveendra.talabattula@amd.com> +Date: Thu, 7 Feb 2019 11:45:55 +0530 +Subject: [PATCH 5756/5758] Revert drm/amdgpu: revert psp firmware load status + check + +Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +index a70657d..a176706 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +@@ -134,6 +134,13 @@ psp_cmd_submit_buf(struct psp_context *psp, + msleep(1); + } + ++ /* the status field must be 0 after FW is loaded */ ++ if (ucode && psp->cmd_buf_mem->resp.status) { ++ DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n", ++ psp->cmd_buf_mem->resp.status, ucode->ucode_id); ++ return -EINVAL; ++ } ++ + if (ucode) { + ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; + ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5757-drm-amdgpu-psp-ignore-psp-response-status.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5757-drm-amdgpu-psp-ignore-psp-response-status.patch new file mode 100644 index 00000000..cb4024bb --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5757-drm-amdgpu-psp-ignore-psp-response-status.patch @@ -0,0 +1,54 @@ +From b54e241076bd705560bd6f262846a40a0c3dbeed Mon Sep 17 00:00:00 2001 +From: Aaron Liu <aaron.liu@amd.com> +Date: Mon, 14 Jan 2019 16:08:32 +0800 +Subject: [PATCH 5757/5758] drm/amdgpu/psp: ignore psp response status +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +In some cases, psp response status is not 0 even there is no +problem while the command is submitted. Some version of PSP FW +doesn't write 0 to that field. +So here we would like to only print a warning instead of an error +during psp initialization to avoid breaking hw_init and it doesn't +return -EINVAL. + +Change-Id: I680679983f972b6969f4949f1faafaf17fe996a6 +Signed-off-by: Aaron Liu <aaron.liu@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Xiangliang Yu<Xiangliang.Yu@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Paul Menzel <pmenzel+amd-gfx@molgen.mpg.de> +Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +index a176706..78e7469 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +@@ -134,11 +134,16 @@ psp_cmd_submit_buf(struct psp_context *psp, + msleep(1); + } + +- /* the status field must be 0 after FW is loaded */ ++ /* In some cases, psp response status is not 0 even there is no ++ * problem while the command is submitted. Some version of PSP FW ++ * doesn't write 0 to that field. ++ * So here we would like to only print a warning instead of an error ++ * during psp initialization to avoid breaking hw_init and it doesn't ++ * return -EINVAL. ++ */ + if (ucode && psp->cmd_buf_mem->resp.status) { +- DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n", ++ DRM_WARN("failed loading with status (%d) and ucode id (%d)\n", + psp->cmd_buf_mem->resp.status, ucode->ucode_id); +- return -EINVAL; + } + + if (ucode) { +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5758-RTQA4-Fix-build-error-for-hs400-and-hs200.patch b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5758-RTQA4-Fix-build-error-for-hs400-and-hs200.patch new file mode 100644 index 00000000..286d4a24 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/5758-RTQA4-Fix-build-error-for-hs400-and-hs200.patch @@ -0,0 +1,81 @@ +From 80bfa93f2f180dd45284f0d4fc75f0b934fcc329 Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Thu, 14 Feb 2019 13:02:47 +0530 +Subject: [PATCH 5758/5758] RTQA4 : Fix build error for hs400 and hs200 + +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + drivers/mmc/host/sdhci-acpi.c | 1 + + drivers/mmc/host/sdhci.c | 11 +++++++++++ + drivers/mmc/host/sdhci.h | 1 + + include/linux/mmc/host.h | 1 + + 4 files changed, 14 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c +index b01e906..d13a177 100644 +--- a/drivers/mmc/host/sdhci-acpi.c ++++ b/drivers/mmc/host/sdhci-acpi.c +@@ -411,6 +411,7 @@ static const struct sdhci_ops sdhci_acpi_ops_amd = { + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, ++ .set_hs400_dll = sdhci_acpi_amd_hs400_dll, + }; + + static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = { +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 46346ec..7e29a39 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1983,6 +1983,16 @@ static void sdhci_hw_reset(struct mmc_host *mmc) + host->ops->hw_reset(host); + } + ++static void sdhci_set_hs400_dll(struct mmc_host *mmc) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ ++ if (host->ops && host->ops->set_hs400_dll) ++ host->ops->set_hs400_dll(host); ++} ++ ++ ++ + static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) + { + if (!(host->flags & SDHCI_DEVICE_DEAD)) { +@@ -2470,6 +2480,7 @@ static const struct mmc_host_ops sdhci_ops = { + .get_cd = sdhci_get_cd, + .get_ro = sdhci_get_ro, + .hw_reset = sdhci_hw_reset, ++ .set_hs400_dll = sdhci_set_hs400_dll, + .enable_sdio_irq = sdhci_enable_sdio_irq, + .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, + .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 027d85a..dd3219e 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -611,6 +611,7 @@ struct sdhci_ops { + int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); + void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); + void (*hw_reset)(struct sdhci_host *host); ++ void (*set_hs400_dll)(struct sdhci_host *host); + void (*adma_workaround)(struct sdhci_host *host, u32 intmask); + void (*card_event)(struct sdhci_host *host); + void (*voltage_switch)(struct sdhci_host *host); +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +index 843c38f..95a1452 100644 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -159,6 +159,7 @@ struct mmc_host_ops { + unsigned int max_dtr, int host_drv, + int card_drv, int *drv_type); + void (*hw_reset)(struct mmc_host *host); ++ void (*set_hs400_dll)(struct mmc_host *host); + void (*card_event)(struct mmc_host *host); + + /* +-- +2.7.4 + diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-amdgpu-patches.scc b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-amdgpu-patches.scc index 2ca9963e..3d5998ab 100644 --- a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-amdgpu-patches.scc +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-amdgpu-patches.scc @@ -1591,3 +1591,12 @@ patch 5722-Code-cleanup.patch patch 5723-drm-amdgpu-vcn-Fixed-S3-hung-issue.patch patch 5724-drm-amdgpu-change-VEGA-booting-with-firmware-loaded-.patch patch 5725-Fix-compilation-error-for-kfd.patch +patch 5747-drm-amd-display-Raise-dispclk-value-for-CZ.patch +patch 5748-drm-amdgpu-gfx8-disable-EDC.patch +patch 5751-Revert-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode.patch +patch 5752-Revert-drm-amdgpu-abstract-the-function-of-enter-exi.patch +patch 5753-Revert-drm-amdgpu-separate-amdgpu_rlc-into-a-single-.patch +patch 5754-drm-amdgpu-make-gfx9-enter-into-rlc-safe-mode-when-s.patch +patch 5755-Revert-drm-amdgpu-revert-the-commit-interim-disable-.patch +patch 5756-Revert-drm-amdgpu-revert-psp-firmware-load-status-ch.patch +patch 5757-drm-amdgpu-psp-ignore-psp-response-status.patch diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-misc-patches.scc b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-misc-patches.scc new file mode 100644 index 00000000..2bb80703 --- /dev/null +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-4.14.71/r1000-misc-patches.scc @@ -0,0 +1,24 @@ +patch 5726-amd-i2s-fix-to-the-fage-fault-when-iommu-is-enabled.patch +patch 5727-amd-i2s-dma-pointer-uses-Link-position-counter.This-.patch +patch 5728-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch +patch 5729-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch +patch 5730-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch +patch 5731-mmc-sdhci-Export-sdhci_request.patch +patch 5732-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch +patch 5733-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch +patch 5734-mmc-sdhci-Add-version-V4-definition.patch +patch 5735-mmc-sdhci-Add-sd-host-v4-mode.patch +patch 5736-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch +patch 5737-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch +patch 5738-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch +patch 5739-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch +patch 5740-lib-crc-Move-polynomial-definition-to-separate-heade.patch +patch 5741-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch +patch 5742-net-ethernet-Use-existing-define-with-polynomial.patch +patch 5743-net-amd-fix-return-type-of-ndo_start_xmit-function.patch +patch 5744-net-phy-Add-helper-for-advertise-to-lcl-value.patch +patch 5745-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch +patch 5746-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch +patch 5749-net-phy-Also-request-modules-for-C45-IDs.patch +patch 5750-amd-xgbe-Fix-mdio-access-for-non-zero-ports-and-clau.patch +patch 5758-RTQA4-Fix-build-error-for-hs400-and-hs200.patch diff --git a/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc b/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc index 11c54127..fb59ce4c 100644 --- a/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc +++ b/meta-r1000/recipes-kernel/linux/linux-yocto-r1000_4.14.inc @@ -2,6 +2,7 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/linux-yocto-${LINUX_VERSION}:" SRC_URI_append_r1000 += "file://r1000-user-features.scc \ file://r1000-user-patches.scc \ + file://r1000-misc-patches.scc \ file://r1000.cfg \ file://r1000-user-config.cfg \ file://r1000-gpu-config.cfg \ diff --git a/meta-snowyowl/recipes-applications/spi-test/files/0001-Modified-the-spi-driver-test-application-to-support-.patch b/meta-snowyowl/recipes-applications/spi-test/files/0001-Modified-the-spi-driver-test-application-to-support-.patch new file mode 100644 index 00000000..ebc648e0 --- /dev/null +++ b/meta-snowyowl/recipes-applications/spi-test/files/0001-Modified-the-spi-driver-test-application-to-support-.patch @@ -0,0 +1,47 @@ +From a059c0737d9f75ce4e62acf3644708e32dc34fc2 Mon Sep 17 00:00:00 2001 +From: smavila <smavila@wallaby.amd.com> +Date: Mon, 3 Dec 2018 06:21:04 +0000 +Subject: [PATCH] Modified the spi driver test application to support SPI ROM + Flash in Wallaby platform + +Signed-off-by: smavila <smavila@wallaby.amd.com> +Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com> +--- + spirom-test.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + mode change 100644 => 100755 spirom-test.c + +diff --git a/spirom-test.c b/spirom-test.c +old mode 100644 +new mode 100755 +index 22c9003..2f10309 +--- a/spirom-test.c ++++ b/spirom-test.c +@@ -243,8 +243,23 @@ void parse_cmd(const char *cmdline) + return; + } + ++ /* read device ID Command with response */ ++ tr.buf[0] = ROM_RDID; ++ tr.direction = RECEIVE; ++ tr.addr_present = 0; ++ tr.len = 3; ++ ++ ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); ++ if (ret < 1) { ++ printf("\nError executing RDID command\n\n"); ++ return; ++ } ++ ++ if( (tr.buf[1] == 0x20) && (tr.buf[2] == 0xbb) && (tr.buf[3] == 0x18)) ++ tr.buf[0] = 0xC7; /* N25Q128A SPI ROM needs 0xC7 as erase command */ ++ else ++ tr.buf[0] = ROM_CHIP_ERASE; + /* Command without data */ +- tr.buf[0] = ROM_CHIP_ERASE; + tr.direction = 0; + tr.len = 0; + tr.addr_present = 0; +-- +2.17.1 + diff --git a/meta-snowyowl/recipes-applications/spi-test/spi-test_1.0.bb b/meta-snowyowl/recipes-applications/spi-test/spi-test_1.0.bb index 764f112a..8d56376e 100644 --- a/meta-snowyowl/recipes-applications/spi-test/spi-test_1.0.bb +++ b/meta-snowyowl/recipes-applications/spi-test/spi-test_1.0.bb @@ -6,6 +6,7 @@ LIC_FILES_CHKSUM = "file://spirom-test.c;endline=29;md5=8e7a9706367d146e5073510a SRC_URI = "file://spirom-test.c \ file://spirom.h \ + file://0001-Modified-the-spi-driver-test-application-to-support-.patch \ " S = "${WORKDIR}" diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0096-Revert-eMMC-patch-4.14.48.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0096-Revert-eMMC-patch-4.14.48.patch new file mode 100755 index 00000000..6957eef8 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0096-Revert-eMMC-patch-4.14.48.patch @@ -0,0 +1,221 @@ +From d433eff73ff15a790c2f6872d57ecd54f8694f7a Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Tue, 22 Jan 2019 16:17:11 +0530 +Subject: [PATCH 096/131] Revert "eMMC patch 4.14.48" + +This reverts commit 925f75997af85adaea92b1771b24764787e4d4ce. + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/acpi/resource.c | 5 ----- + drivers/mmc/core/mmc.c | 25 ++++++++++--------------- + drivers/mmc/host/sdhci-acpi.c | 2 -- + drivers/mmc/host/sdhci.c | 21 --------------------- + drivers/mmc/host/sdhci.h | 2 -- + include/linux/mmc/host.h | 1 - + 6 files changed, 10 insertions(+), 46 deletions(-) + mode change 100755 => 100644 drivers/acpi/resource.c + mode change 100755 => 100644 drivers/mmc/core/mmc.c + mode change 100755 => 100644 drivers/mmc/host/sdhci-acpi.c + mode change 100755 => 100644 drivers/mmc/host/sdhci.c + mode change 100755 => 100644 drivers/mmc/host/sdhci.h + mode change 100755 => 100644 include/linux/mmc/host.h + +diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c +old mode 100755 +new mode 100644 +index e82b5a7..d85e010 +--- a/drivers/acpi/resource.c ++++ b/drivers/acpi/resource.c +@@ -425,11 +425,6 @@ static void acpi_dev_get_irqresource(struct resource *res, u32 gsi, + triggering = trig; + polarity = pol; + } +- if (gsi == 5) { +- polarity = ACPI_ACTIVE_LOW; +- pr_warning("ACPI: IRQ %d do not override to %s, %s\n", gsi, +- t ? "level" : "edge", p ? "low" : "high"); +- } + } + + res->flags = acpi_dev_irq_flags(triggering, polarity, shareable); +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +old mode 100755 +new mode 100644 +index 29bba1e..bad5c1b +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1161,14 +1161,14 @@ static int mmc_select_hs400(struct mmc_card *card) + mmc_hostname(host), err); + return err; + } +- /*In AMD Platform due to hardware ip issue this fails*/ +- if (!host->ops->set_hs400_dll) { +- /* Set host controller to HS timing */ +- mmc_set_timing(card->host, MMC_TIMING_MMC_HS); +- /* Reduce frequency to HS frequency */ +- max_dtr = card->ext_csd.hs_max_dtr; +- mmc_set_clock(host, max_dtr); +- } ++ ++ /* Set host controller to HS timing */ ++ mmc_set_timing(card->host, MMC_TIMING_MMC_HS); ++ ++ /* Reduce frequency to HS frequency */ ++ max_dtr = card->ext_csd.hs_max_dtr; ++ mmc_set_clock(host, max_dtr); ++ + err = mmc_switch_status(card); + if (err) + goto out_err; +@@ -1204,8 +1204,7 @@ static int mmc_select_hs400(struct mmc_card *card) + err = mmc_switch_status(card); + if (err) + goto out_err; +- if (host->ops->set_hs400_dll) +- host->ops->set_hs400_dll(host); ++ + return 0; + + out_err: +@@ -1228,7 +1227,6 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + + /* Reduce frequency to HS */ + max_dtr = card->ext_csd.hs_max_dtr; +- if (!host->ops->set_hs400_dll) + mmc_set_clock(host, max_dtr); + + /* Switch HS400 to HS DDR */ +@@ -1238,15 +1236,12 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + true, false, true); + if (err) + goto out_err; +- /*In AMD Platform due to hardware ip issue this fails*/ +- if (!host->ops->set_hs400_dll) +- { ++ + mmc_set_timing(host, MMC_TIMING_MMC_DDR52); + + err = mmc_switch_status(card); + if (err) + goto out_err; +- } + + /* Switch HS DDR to HS */ + err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, +diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c +old mode 100755 +new mode 100644 +index 33592a6..c2e7048 +--- a/drivers/mmc/host/sdhci-acpi.c ++++ b/drivers/mmc/host/sdhci-acpi.c +@@ -411,7 +411,6 @@ static const struct sdhci_ops sdhci_acpi_ops_amd = { + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +- .set_hs400_dll = sdhci_acpi_amd_hs400_dll, + }; + + static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = { +@@ -442,7 +441,6 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = { + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, + .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_32BIT_DMA_SIZE | + SDHCI_QUIRK_32BIT_ADMA_SIZE, +- .quirks2 = SDHCI_QUIRK2_BROKEN_TUNING_WA, + .probe_slot = sdhci_acpi_emmc_amd_probe_slot, + }; + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +old mode 100755 +new mode 100644 +index 8837d45..d35deb7 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1207,12 +1207,6 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) + flags |= SDHCI_CMD_DATA; + + sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); +- +- if (cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 && (host->quirks2 & SDHCI_QUIRK2_BROKEN_TUNING_WA)) { +- mdelay(10); +- sdhci_writel(host, 0x8803040a, 0x8b8); +- mdelay(10); +- } + } + EXPORT_SYMBOL_GPL(sdhci_send_command); + +@@ -1879,14 +1873,6 @@ static void sdhci_hw_reset(struct mmc_host *mmc) + host->ops->hw_reset(host); + } + +-static void sdhci_set_hs400_dll(struct mmc_host *mmc) +-{ +- struct sdhci_host *host = mmc_priv(mmc); +- +- if (host->ops && host->ops->set_hs400_dll) +- host->ops->set_hs400_dll(host); +-} +- + static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) + { + if (!(host->flags & SDHCI_DEVICE_DEAD)) { +@@ -2370,7 +2356,6 @@ static const struct mmc_host_ops sdhci_ops = { + .get_cd = sdhci_get_cd, + .get_ro = sdhci_get_ro, + .hw_reset = sdhci_hw_reset, +- .set_hs400_dll = sdhci_set_hs400_dll, + .enable_sdio_irq = sdhci_enable_sdio_irq, + .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, + .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, +@@ -3315,12 +3300,6 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) + host->caps1 &= ~upper_32_bits(dt_caps_mask); + host->caps1 |= upper_32_bits(dt_caps); + } +- +- if ((host->caps1 & SDHCI_SUPPORT_SDR104) && (host->caps1 & SDHCI_SUPPORT_DDR50) && +- (host->quirks2 & SDHCI_QUIRK2_BROKEN_TUNING_WA)) +- { +- host->mmc->caps2 = MMC_CAP2_HS400_1_8V; +- } + } + EXPORT_SYMBOL_GPL(__sdhci_read_caps); + +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +old mode 100755 +new mode 100644 +index b5fd294..1d7d61e +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -438,7 +438,6 @@ struct sdhci_host { + /* Controller has CRC in 136 bit Command Response */ + #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) + +-#define SDHCI_QUIRK2_BROKEN_TUNING_WA (1<<17) + int irq; /* Device IRQ */ + void __iomem *ioaddr; /* Mapped address */ + char *bounce_buffer; /* For packing SDMA reads/writes */ +@@ -585,7 +584,6 @@ struct sdhci_ops { + int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); + void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); + void (*hw_reset)(struct sdhci_host *host); +- void (*set_hs400_dll)(struct sdhci_host *host); + void (*adma_workaround)(struct sdhci_host *host, u32 intmask); + void (*card_event)(struct sdhci_host *host); + void (*voltage_switch)(struct sdhci_host *host); +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +old mode 100755 +new mode 100644 +index b7d5611..9a43763 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -152,7 +152,6 @@ struct mmc_host_ops { + unsigned int max_dtr, int host_drv, + int card_drv, int *drv_type); + void (*hw_reset)(struct mmc_host *host); +- void (*set_hs400_dll)(struct mmc_host *host); + void (*card_event)(struct mmc_host *host); + + /* +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0097-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0097-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch new file mode 100755 index 00000000..5dcdadeb --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0097-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch @@ -0,0 +1,50 @@ +From b81f61d97f8e479d3ee3cc8fe428accbaf3a5cf6 Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Tue, 22 May 2018 16:26:26 +0200 +Subject: [PATCH 097/131] mmc: core: Move calls to ->prepare_hs400_tuning() + closer to mmc code + +Move the calls to ->prepare_hs400_tuning(), from mmc_retune() into +mmc_hs400_to_hs200(), as it better belongs there, rather than being generic +to all type of cards. + +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/core/host.c | 3 --- + drivers/mmc/core/mmc.c | 4 ++++ + 2 files changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c +index ad88deb..4651e9b 100644 +--- a/drivers/mmc/core/host.c ++++ b/drivers/mmc/core/host.c +@@ -148,9 +148,6 @@ int mmc_retune(struct mmc_host *host) + goto out; + + return_to_hs400 = true; +- +- if (host->ops->prepare_hs400_tuning) +- host->ops->prepare_hs400_tuning(host, &host->ios); + } + + err = mmc_execute_tuning(host->card); +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +index bad5c1b..16845a8 100644 +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1278,6 +1278,10 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + + mmc_set_bus_speed(card); + ++ /* Prepare tuning for HS400 mode. */ ++ if (host->ops->prepare_hs400_tuning) ++ host->ops->prepare_hs400_tuning(host, &host->ios); ++ + return 0; + + out_err: +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0098-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0098-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch new file mode 100755 index 00000000..8017ef7b --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0098-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch @@ -0,0 +1,86 @@ +From 3f3089099ceefd39f728a341fb57ca48f0fbc163 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Mon, 18 Jun 2018 14:57:49 +0200 +Subject: [PATCH 098/131] mmc: core: more fine-grained hooks for HS400 tuning + +This adds two new HS400 tuning operations: +* hs400_downgrade +* hs400_complete + +These supplement the existing HS400 operation: +* prepare_hs400_tuning + +This is motivated by a requirement of Renesas SDHI for the following: +1. Disabling SCC before selecting to HS if selection of HS400 has occurred. + This can be done in an implementation of prepare_hs400_tuning_downgrade +2. Updating registers after switching to HS400 + This can be done in an implementation of complete_hs400_tuning + +If hs400_downgrade or hs400_complete are not implemented then they are not +called. Thus means there should be no affect for existing drivers as none +implemt these ops. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/core/mmc.c | 10 ++++++++++ + include/linux/mmc/host.h | 7 +++++++ + 2 files changed, 17 insertions(+) + +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +index 16845a8..16b22d7 100644 +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1165,6 +1165,10 @@ static int mmc_select_hs400(struct mmc_card *card) + /* Set host controller to HS timing */ + mmc_set_timing(card->host, MMC_TIMING_MMC_HS); + ++ /* Prepare host to downgrade to HS timing */ ++ if (host->ops->hs400_downgrade) ++ host->ops->hs400_downgrade(host); ++ + /* Reduce frequency to HS frequency */ + max_dtr = card->ext_csd.hs_max_dtr; + mmc_set_clock(host, max_dtr); +@@ -1205,6 +1209,9 @@ static int mmc_select_hs400(struct mmc_card *card) + if (err) + goto out_err; + ++ if (host->ops->hs400_complete) ++ host->ops->hs400_complete(host); ++ + return 0; + + out_err: +@@ -1252,6 +1259,9 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + + mmc_set_timing(host, MMC_TIMING_MMC_HS); + ++ if (host->ops->hs400_downgrade) ++ host->ops->hs400_downgrade(host); ++ + err = mmc_switch_status(card); + if (err) + goto out_err; +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +index 9a43763..843c38f 100644 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -145,6 +145,13 @@ struct mmc_host_ops { + + /* Prepare HS400 target operating frequency depending host driver */ + int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); ++ ++ /* Prepare for switching from HS400 to HS200 */ ++ void (*hs400_downgrade)(struct mmc_host *host); ++ ++ /* Complete selection of HS400 */ ++ void (*hs400_complete)(struct mmc_host *host); ++ + /* Prepare enhanced strobe depending host driver */ + void (*hs400_enhanced_strobe)(struct mmc_host *host, + struct mmc_ios *ios); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0099-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0099-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch new file mode 100755 index 00000000..ed092c65 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0099-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch @@ -0,0 +1,91 @@ +From d988bfe2ade0b5c288f350708a8cc3e916b5f286 Mon Sep 17 00:00:00 2001 +From: "ernest.zhang" <ernest.zhang@bayhubtech.com> +Date: Mon, 16 Jul 2018 14:26:53 +0800 +Subject: [PATCH 099/131] mmc: sdhci: Export sdhci tuning function symbol + +Export sdhci tuning function symbols which are used by other SD Host +controller driver modules. + +Signed-off-by: ernest.zhang <ernest.zhang@bayhubtech.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 12 ++++++++---- + drivers/mmc/host/sdhci.h | 5 +++++ + 2 files changed, 13 insertions(+), 4 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index d35deb7..9b65a38 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -2027,7 +2027,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) + return 0; + } + +-static void sdhci_start_tuning(struct sdhci_host *host) ++void sdhci_start_tuning(struct sdhci_host *host) + { + u16 ctrl; + +@@ -2050,14 +2050,16 @@ static void sdhci_start_tuning(struct sdhci_host *host) + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); + } ++EXPORT_SYMBOL_GPL(sdhci_start_tuning); + +-static void sdhci_end_tuning(struct sdhci_host *host) ++void sdhci_end_tuning(struct sdhci_host *host) + { + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + } ++EXPORT_SYMBOL_GPL(sdhci_end_tuning); + +-static void sdhci_reset_tuning(struct sdhci_host *host) ++void sdhci_reset_tuning(struct sdhci_host *host) + { + u16 ctrl; + +@@ -2066,6 +2068,7 @@ static void sdhci_reset_tuning(struct sdhci_host *host) + ctrl &= ~SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } ++EXPORT_SYMBOL_GPL(sdhci_reset_tuning); + + static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) + { +@@ -2086,7 +2089,7 @@ static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) + * interrupt setup is different to other commands and there is no timeout + * interrupt so special handling is needed. + */ +-static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) ++void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) + { + struct mmc_host *mmc = host->mmc; + struct mmc_command cmd = {}; +@@ -2136,6 +2139,7 @@ static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) + msecs_to_jiffies(50)); + + } ++EXPORT_SYMBOL_GPL(sdhci_send_tuning); + + static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) + { +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 1d7d61e..6386709 100644 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -733,4 +733,9 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, + + void sdhci_dumpregs(struct sdhci_host *host); + ++void sdhci_start_tuning(struct sdhci_host *host); ++void sdhci_end_tuning(struct sdhci_host *host); ++void sdhci_reset_tuning(struct sdhci_host *host); ++void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); ++ + #endif /* __SDHCI_HW_H */ +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0100-mmc-sdhci-add-tuning-error-codes.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0100-mmc-sdhci-add-tuning-error-codes.patch new file mode 100755 index 00000000..d2076a54 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0100-mmc-sdhci-add-tuning-error-codes.patch @@ -0,0 +1,78 @@ +From f0cbc1d2216360846eec53fe7ff93f583f6ee6ac Mon Sep 17 00:00:00 2001 +From: Yinbo Zhu <yinbo.zhu@nxp.com> +Date: Thu, 23 Aug 2018 16:48:31 +0800 +Subject: [PATCH 100/131] mmc: sdhci: add tuning error codes + +This patch is to add tuning error codes to +judge tuning state + +Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 9 +++++---- + drivers/mmc/host/sdhci.h | 1 + + 2 files changed, 6 insertions(+), 4 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 9b65a38..730cfa7 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -2141,7 +2141,7 @@ void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) + } + EXPORT_SYMBOL_GPL(sdhci_send_tuning); + +-static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) ++static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) + { + int i; + +@@ -2158,13 +2158,13 @@ static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) + pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + sdhci_abort_tuning(host, opcode); +- return; ++ return -ETIMEDOUT; + } + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { + if (ctrl & SDHCI_CTRL_TUNED_CLK) +- return; /* Success! */ ++ return 0; /* Success! */ + break; + } + +@@ -2176,6 +2176,7 @@ static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) + pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", + mmc_hostname(host->mmc)); + sdhci_reset_tuning(host); ++ return -EAGAIN; + } + + int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) +@@ -2237,7 +2238,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) + + sdhci_start_tuning(host); + +- __sdhci_execute_tuning(host, opcode); ++ host->tuning_err = __sdhci_execute_tuning(host, opcode); + + sdhci_end_tuning(host); + out: +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 6386709..d38abce 100644 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -540,6 +540,7 @@ struct sdhci_host { + + unsigned int tuning_count; /* Timer count for re-tuning */ + unsigned int tuning_mode; /* Re-tuning mode supported by host */ ++ unsigned int tuning_err; /* Error code for re-tuning */ + #define SDHCI_TUNING_MODE_1 0 + #define SDHCI_TUNING_MODE_2 1 + #define SDHCI_TUNING_MODE_3 2 +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0101-mmc-sdhci-Export-sdhci_request.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0101-mmc-sdhci-Export-sdhci_request.patch new file mode 100755 index 00000000..d8bc986d --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0101-mmc-sdhci-Export-sdhci_request.patch @@ -0,0 +1,53 @@ +From 4561d29b62ca137f268f19fadd098db381af0402 Mon Sep 17 00:00:00 2001 +From: Aapo Vienamo <avienamo@nvidia.com> +Date: Mon, 20 Aug 2018 12:23:32 +0300 +Subject: [PATCH 101/131] mmc: sdhci: Export sdhci_request() + +Allow SDHCI drivers to hook code before and after sdhci_request() by +making it externally visible. + +Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 3 ++- + drivers/mmc/host/sdhci.h | 1 + + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 730cfa7..0819b85 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1552,7 +1552,7 @@ EXPORT_SYMBOL_GPL(sdhci_set_power); + * * + \*****************************************************************************/ + +-static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) ++void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) + { + struct sdhci_host *host; + int present; +@@ -1591,6 +1591,7 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); + } ++EXPORT_SYMBOL_GPL(sdhci_request); + + void sdhci_set_bus_width(struct sdhci_host *host, int width) + { +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index d38abce..e093037 100644 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -710,6 +710,7 @@ void sdhci_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd); + void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, + unsigned short vdd); ++void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); + void sdhci_set_bus_width(struct sdhci_host *host, int width); + void sdhci_reset(struct sdhci_host *host, u8 mask); + void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0102-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0102-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch new file mode 100755 index 00000000..7679f318 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0102-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch @@ -0,0 +1,80 @@ +From 1d2f6e2bf771658f2865a0931aa71ce4a861a8b2 Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Wed, 16 Jan 2019 11:23:47 +0530 +Subject: [PATCH 102/131] mmc: sdhci: add adma_table_cnt member to struct + sdhci_host + +This patch adds adma_table_cnt member to struct sdhci_host to give more +flexibility to drivers to control the ADMA table count. + +Default value of adma_table_cnt is set to (SDHCI_MAX_SEGS * 2 + 1). + +Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 17 +++++++++-------- + drivers/mmc/host/sdhci.h | 3 +++ + 2 files changed, 12 insertions(+), 8 deletions(-) + mode change 100644 => 100755 drivers/mmc/host/sdhci.h + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 0819b85..075253f 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -3223,6 +3223,13 @@ struct sdhci_host *sdhci_alloc_host(struct device *dev, + + host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG; + ++ /* ++ * The DMA table descriptor count is calculated as the maximum ++ * number of segments times 2, to allow for an alignment ++ * descriptor for each segment, plus 1 for a nop end descriptor. ++ */ ++ host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1; ++ + return host; + } + +@@ -3468,18 +3475,12 @@ int sdhci_setup_host(struct sdhci_host *host) + dma_addr_t dma; + void *buf; + +- /* +- * The DMA descriptor table size is calculated as the maximum +- * number of segments times 2, to allow for an alignment +- * descriptor for each segment, plus 1 for a nop end descriptor, +- * all multipled by the descriptor size. +- */ + if (host->flags & SDHCI_USE_64_BIT_DMA) { +- host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * ++ host->adma_table_sz = host->adma_table_cnt * + SDHCI_ADMA2_64_DESC_SZ; + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + } else { +- host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * ++ host->adma_table_sz = host->adma_table_cnt * + SDHCI_ADMA2_32_DESC_SZ; + host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; + } +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +old mode 100644 +new mode 100755 +index e093037..17193f4 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -550,6 +550,9 @@ struct sdhci_host { + /* Host SDMA buffer boundary. */ + u32 sdma_boundary; + ++ /* Host ADMA table count */ ++ u32 adma_table_cnt; ++ + unsigned long private[0] ____cacheline_aligned; + }; + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0103-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0103-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch new file mode 100755 index 00000000..bea876fd --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0103-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch @@ -0,0 +1,128 @@ +From d564e134441916f5275e277146471997443d0aad Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang <Jisheng.Zhang@synaptics.com> +Date: Tue, 28 Aug 2018 17:47:23 +0800 +Subject: [PATCH 103/131] mmc: sdhci: introduce adma_write_desc() hook to + struct sdhci_ops + +Add this hook so that it can be overridden with driver specific +implementations. We also let the original sdhci_adma_write_desc() +accept &desc so that the function can set its new value. Then export +the function so that it could be reused by driver's specific +implementations. + +Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 37 +++++++++++++++++++++++-------------- + drivers/mmc/host/sdhci.h | 4 ++++ + 2 files changed, 27 insertions(+), 14 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 075253f..f345a31 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -554,10 +554,10 @@ static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) + local_irq_restore(*flags); + } + +-static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, +- dma_addr_t addr, int len, unsigned cmd) ++void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, ++ dma_addr_t addr, int len, unsigned int cmd) + { +- struct sdhci_adma2_64_desc *dma_desc = desc; ++ struct sdhci_adma2_64_desc *dma_desc = *desc; + + /* 32-bit and 64-bit descriptors have these members in same position */ + dma_desc->cmd = cpu_to_le16(cmd); +@@ -566,6 +566,19 @@ static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, + + if (host->flags & SDHCI_USE_64_BIT_DMA) + dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); ++ ++ *desc += host->desc_sz; ++} ++EXPORT_SYMBOL_GPL(sdhci_adma_write_desc); ++ ++static inline void __sdhci_adma_write_desc(struct sdhci_host *host, ++ void **desc, dma_addr_t addr, ++ int len, unsigned int cmd) ++{ ++ if (host->ops->adma_write_desc) ++ host->ops->adma_write_desc(host, desc, addr, len, cmd); ++ ++ sdhci_adma_write_desc(host, desc, addr, len, cmd); + } + + static void sdhci_adma_mark_end(void *desc) +@@ -618,28 +631,24 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, + } + + /* tran, valid */ +- sdhci_adma_write_desc(host, desc, align_addr, offset, +- ADMA2_TRAN_VALID); ++ __sdhci_adma_write_desc(host, &desc, align_addr, ++ offset, ADMA2_TRAN_VALID); + + BUG_ON(offset > 65536); + + align += SDHCI_ADMA2_ALIGN; + align_addr += SDHCI_ADMA2_ALIGN; + +- desc += host->desc_sz; +- + addr += offset; + len -= offset; + } + + BUG_ON(len > 65536); + +- if (len) { +- /* tran, valid */ +- sdhci_adma_write_desc(host, desc, addr, len, +- ADMA2_TRAN_VALID); +- desc += host->desc_sz; +- } ++ /* tran, valid */ ++ if (len) ++ __sdhci_adma_write_desc(host, &desc, addr, len, ++ ADMA2_TRAN_VALID); + + /* + * If this triggers then we have a calculation bug +@@ -656,7 +665,7 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, + } + } else { + /* Add a terminating entry - nop, end, valid */ +- sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); ++ __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID); + } + } + +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 17193f4..14e6545 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -591,6 +591,8 @@ struct sdhci_ops { + void (*adma_workaround)(struct sdhci_host *host, u32 intmask); + void (*card_event)(struct sdhci_host *host); + void (*voltage_switch)(struct sdhci_host *host); ++ void (*adma_write_desc)(struct sdhci_host *host, void **desc, ++ dma_addr_t addr, int len, unsigned int cmd); + }; + + #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS +@@ -722,6 +724,8 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); + int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios); + void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); ++void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, ++ dma_addr_t addr, int len, unsigned int cmd); + + #ifdef CONFIG_PM + int sdhci_suspend_host(struct sdhci_host *host); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0104-mmc-sdhci-Add-version-V4-definition.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0104-mmc-sdhci-Add-version-V4-definition.patch new file mode 100755 index 00000000..2aff580c --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0104-mmc-sdhci-Add-version-V4-definition.patch @@ -0,0 +1,46 @@ +From e4e3401cfb668960c78f4969a89521f6d55746e9 Mon Sep 17 00:00:00 2001 +From: Chunyan Zhang <zhang.chunyan@linaro.org> +Date: Thu, 30 Aug 2018 16:21:37 +0800 +Subject: [PATCH 104/131] mmc: sdhci: Add version V4 definition + +Added definitions for v400, v410, v420. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 2 +- + drivers/mmc/host/sdhci.h | 3 +++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index f345a31..e47f1aa 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -3423,7 +3423,7 @@ int sdhci_setup_host(struct sdhci_host *host) + + override_timeout_clk = host->timeout_clk; + +- if (host->version > SDHCI_SPEC_300) { ++ if (host->version > SDHCI_SPEC_420) { + pr_err("%s: Unknown controller version (%d). You may experience problems.\n", + mmc_hostname(mmc), host->version); + } +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 14e6545..5bd6aa4 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -270,6 +270,9 @@ + #define SDHCI_SPEC_100 0 + #define SDHCI_SPEC_200 1 + #define SDHCI_SPEC_300 2 ++#define SDHCI_SPEC_400 3 ++#define SDHCI_SPEC_410 4 ++#define SDHCI_SPEC_420 5 + + /* + * End of controller registers. +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0105-mmc-sdhci-Add-sd-host-v4-mode.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0105-mmc-sdhci-Add-sd-host-v4-mode.patch new file mode 100755 index 00000000..60f06cef --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0105-mmc-sdhci-Add-sd-host-v4-mode.patch @@ -0,0 +1,105 @@ +From f1eb47a120122349dd60aeec4fe787fcb18f470a Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Wed, 16 Jan 2019 11:47:52 +0530 +Subject: [PATCH 105/131] mmc: sdhci: Add sd host v4 mode + +For SD host controller version 4.00 or later ones, there're two +modes of implementation - Version 3.00 compatible mode or +Version 4 mode. This patch introduced an interface to enable +v4 mode. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 29 +++++++++++++++++++++++++++++ + drivers/mmc/host/sdhci.h | 3 +++ + 2 files changed, 32 insertions(+) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index e47f1aa..5cc756a 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -123,6 +123,29 @@ EXPORT_SYMBOL_GPL(sdhci_dumpregs); + * * + \*****************************************************************************/ + ++static void sdhci_do_enable_v4_mode(struct sdhci_host *host) ++{ ++ u16 ctrl2; ++ ++ ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2); ++ if (ctrl2 & SDHCI_CTRL_V4_MODE) ++ return; ++ ++ ctrl2 |= SDHCI_CTRL_V4_MODE; ++ sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL); ++} ++ ++/* ++ * This can be called before sdhci_add_host() by Vendor's host controller ++ * driver to enable v4 mode if supported. ++ */ ++void sdhci_enable_v4_mode(struct sdhci_host *host) ++{ ++ host->v4_mode = true; ++ sdhci_do_enable_v4_mode(host); ++} ++EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); ++ + static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) + { + return cmd->data || cmd->flags & MMC_RSP_BUSY; +@@ -252,6 +275,9 @@ static void sdhci_init(struct sdhci_host *host, int soft) + else + sdhci_do_reset(host, SDHCI_RESET_ALL); + ++ if (host->v4_mode) ++ sdhci_do_enable_v4_mode(host); ++ + sdhci_set_default_irqs(host); + + host->cqe_on = false; +@@ -3293,6 +3319,9 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) + + sdhci_do_reset(host, SDHCI_RESET_ALL); + ++ if (host->v4_mode) ++ sdhci_do_enable_v4_mode(host); ++ + of_property_read_u64(mmc_dev(host->mmc)->of_node, + "sdhci-caps-mask", &dt_caps_mask); + of_property_read_u64(mmc_dev(host->mmc)->of_node, +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 5bd6aa4..cc40ddc 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -184,6 +184,7 @@ + #define SDHCI_CTRL_DRV_TYPE_D 0x0030 + #define SDHCI_CTRL_EXEC_TUNING 0x0040 + #define SDHCI_CTRL_TUNED_CLK 0x0080 ++#define SDHCI_CTRL_V4_MODE 0x1000 + #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + + #define SDHCI_CAPABILITIES 0x40 +@@ -490,6 +491,7 @@ struct sdhci_host { + bool bus_on; /* Bus power prevents runtime suspend */ + bool preset_enabled; /* Preset is enabled */ + bool pending_reset; /* Cmd/data reset is pending */ ++ bool v4_mode; /* Host Version 4 Enable */ + + struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ + struct mmc_command *cmd; /* Current command */ +@@ -744,6 +746,7 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, + int *data_error); + + void sdhci_dumpregs(struct sdhci_host *host); ++void sdhci_enable_v4_mode(struct sdhci_host *host); + + void sdhci_start_tuning(struct sdhci_host *host); + void sdhci_end_tuning(struct sdhci_host *host); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0106-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0106-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch new file mode 100755 index 00000000..2223b777 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0106-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch @@ -0,0 +1,210 @@ +From c2398060f0982a65582b59636777dfec2134fb1c Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Tue, 22 Jan 2019 22:59:45 +0530 +Subject: [PATCH 106/131] mmc: sdhci: Add ADMA2 64-bit addressing support for + V4 mode + +ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. +So there are two kinds of descriptors for ADMA2 64-bit addressing +i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 +mode. 128-bit Descriptor is aligned to 8-byte. + +For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 +register. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +[Ulf: Fixed conflict while applying] +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 92 +++++++++++++++++++++++++++++++++++------------- + drivers/mmc/host/sdhci.h | 12 +++++-- + 2 files changed, 78 insertions(+), 26 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 5cc756a..4b18f3f 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + } + ++static void sdhci_config_dma(struct sdhci_host *host) ++{ ++ u8 ctrl; ++ u16 ctrl2; ++ ++ if (host->version < SDHCI_SPEC_200) ++ return; ++ ++ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ++ ++ /* ++ * Always adjust the DMA selection as some controllers ++ * (e.g. JMicron) can't do PIO properly when the selection ++ * is ADMA. ++ */ ++ ctrl &= ~SDHCI_CTRL_DMA_MASK; ++ if (!(host->flags & SDHCI_REQ_USE_DMA)) ++ goto out; ++ ++ /* Note if DMA Select is zero then SDMA is selected */ ++ if (host->flags & SDHCI_USE_ADMA) ++ ctrl |= SDHCI_CTRL_ADMA32; ++ ++ if (host->flags & SDHCI_USE_64_BIT_DMA) { ++ /* ++ * If v4 mode, all supported DMA can be 64-bit addressing if ++ * controller supports 64-bit system address, otherwise only ++ * ADMA can support 64-bit addressing. ++ */ ++ if (host->v4_mode) { ++ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ ctrl2 |= SDHCI_CTRL_64BIT_ADDR; ++ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); ++ } else if (host->flags & SDHCI_USE_ADMA) { ++ /* ++ * Don't need to undo SDHCI_CTRL_ADMA32 in order to ++ * set SDHCI_CTRL_ADMA64. ++ */ ++ ctrl |= SDHCI_CTRL_ADMA64; ++ } ++ } ++ ++out: ++ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); ++} ++ + static void sdhci_init(struct sdhci_host *host, int soft) + { + struct mmc_host *mmc = host->mmc; +@@ -839,7 +885,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) + + static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) + { +- u8 ctrl; + struct mmc_data *data = cmd->data; + + if (sdhci_data_line_cmd(cmd)) +@@ -934,25 +979,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) + } + } + +- /* +- * Always adjust the DMA selection as some controllers +- * (e.g. JMicron) can't do PIO properly when the selection +- * is ADMA. +- */ +- if (host->version >= SDHCI_SPEC_200) { +- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); +- ctrl &= ~SDHCI_CTRL_DMA_MASK; +- if ((host->flags & SDHCI_REQ_USE_DMA) && +- (host->flags & SDHCI_USE_ADMA)) { +- if (host->flags & SDHCI_USE_64_BIT_DMA) +- ctrl |= SDHCI_CTRL_ADMA64; +- else +- ctrl |= SDHCI_CTRL_ADMA32; +- } else { +- ctrl |= SDHCI_CTRL_SDMA; +- } +- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +- } ++ sdhci_config_dma(host); + + if (!(host->flags & SDHCI_REQ_USE_DMA)) { + int flags; +@@ -3416,6 +3443,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) + return 0; + } + ++static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) ++{ ++ /* ++ * According to SD Host Controller spec v4.10, bit[27] added from ++ * version 4.10 in Capabilities Register is used as 64-bit System ++ * Address support for V4 mode. ++ */ ++ if (host->version >= SDHCI_SPEC_410 && host->v4_mode) ++ return host->caps & SDHCI_CAN_64BIT_V4; ++ ++ return host->caps & SDHCI_CAN_64BIT; ++} ++ + int sdhci_setup_host(struct sdhci_host *host) + { + struct mmc_host *mmc; +@@ -3487,7 +3527,7 @@ int sdhci_setup_host(struct sdhci_host *host) + * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to + * implement. + */ +- if (host->caps & SDHCI_CAN_64BIT) ++ if (sdhci_can_64bit_dma(host)) + host->flags |= SDHCI_USE_64_BIT_DMA; + + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { +@@ -3515,8 +3555,8 @@ int sdhci_setup_host(struct sdhci_host *host) + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + host->adma_table_sz = host->adma_table_cnt * +- SDHCI_ADMA2_64_DESC_SZ; +- host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; ++ SDHCI_ADMA2_64_DESC_SZ(host); ++ host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); + } else { + host->adma_table_sz = host->adma_table_cnt * + SDHCI_ADMA2_32_DESC_SZ; +@@ -3524,7 +3564,11 @@ int sdhci_setup_host(struct sdhci_host *host) + } + + host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; +- buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + ++ /* ++ * Use zalloc to zero the reserved high 32-bits of 128-bit ++ * descriptors so that they never need to be written. ++ */ ++ buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + host->adma_table_sz, &dma, GFP_KERNEL); + if (!buf) { + pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index cc40ddc..0b5ac1c 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -185,6 +185,7 @@ + #define SDHCI_CTRL_EXEC_TUNING 0x0040 + #define SDHCI_CTRL_TUNED_CLK 0x0080 + #define SDHCI_CTRL_V4_MODE 0x1000 ++#define SDHCI_CTRL_64BIT_ADDR 0x2000 + #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + + #define SDHCI_CAPABILITIES 0x40 +@@ -205,6 +206,7 @@ + #define SDHCI_CAN_VDD_330 0x01000000 + #define SDHCI_CAN_VDD_300 0x02000000 + #define SDHCI_CAN_VDD_180 0x04000000 ++#define SDHCI_CAN_64BIT_V4 0x08000000 + #define SDHCI_CAN_64BIT 0x10000000 + + #define SDHCI_SUPPORT_SDR50 0x00000001 +@@ -309,8 +311,14 @@ struct sdhci_adma2_32_desc { + */ + #define SDHCI_ADMA2_DESC_ALIGN 8 + +-/* ADMA2 64-bit DMA descriptor size */ +-#define SDHCI_ADMA2_64_DESC_SZ 12 ++/* ++ * ADMA2 64-bit DMA descriptor size ++ * According to SD Host Controller spec v4.10, there are two kinds of ++ * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit ++ * Descriptor, if Host Version 4 Enable is set in the Host Control 2 ++ * register, 128-bit Descriptor will be selected. ++ */ ++#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) + + /* + * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch new file mode 100755 index 00000000..407c8917 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch @@ -0,0 +1,79 @@ +From 6f5130259bf48630d9bf77359e8f8e4badc55cfe Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Tue, 22 Jan 2019 23:00:26 +0530 +Subject: [PATCH 107/131] mmc: sdhci: Add 32-bit block count support for v4 + mode + +Host Controller Version 4.10 re-defines SDMA System Address register +as 32-bit Block Count for v4 mode, and SDMA uses ADMA System +Address register (05Fh-058h) instead if v4 mode is enabled. Also +when using 32-bit block count, 16-bit block count register need +to be set to zero. + +Since using 32-bit Block Count would cause problems for auto-cmd23, +it can be chosen via host->quirk2. + +Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 14 +++++++++++++- + drivers/mmc/host/sdhci.h | 8 ++++++++ + 2 files changed, 21 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 4b18f3f..da59b0a 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -998,7 +998,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) + /* Set the DMA boundary value and block size */ + sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), + SDHCI_BLOCK_SIZE); +- sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); ++ ++ /* ++ * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count ++ * can be supported, in that case 16-bit block count register must be 0. ++ */ ++ if (host->version >= SDHCI_SPEC_410 && host->v4_mode && ++ (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { ++ if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) ++ sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); ++ sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); ++ } else { ++ sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); ++ } + } + + static inline bool sdhci_auto_cmd12(struct sdhci_host *host, +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 0b5ac1c..5197966 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -28,6 +28,7 @@ + + #define SDHCI_DMA_ADDRESS 0x00 + #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS ++#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS + + #define SDHCI_BLOCK_SIZE 0x04 + #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) +@@ -449,6 +450,13 @@ struct sdhci_host { + #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) + /* Controller has CRC in 136 bit Command Response */ + #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) ++/* ++ * 32-bit block count may not support eMMC where upper bits of CMD23 are used ++ * for other purposes. Consequently we support 16-bit block count by default. ++ * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit ++ * block count. ++ */ ++#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) + + int irq; /* Device IRQ */ + void __iomem *ioaddr; /* Mapped address */ +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0108-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0108-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch new file mode 100755 index 00000000..9242d0bd --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0108-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch @@ -0,0 +1,113 @@ +From f5ec4fb304cea4512e2a321152fa4dd3ba70f6aa Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Tue, 22 Jan 2019 23:01:11 +0530 +Subject: [PATCH 108/131] mmc: sdhci: Add Auto CMD Auto Select support + +As SD Host Controller Specification v4.10 documents: +Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. +Selection of Auto CMD depends on setting of CMD23 Enable in the Host +Control 2 register which indicates whether card supports CMD23. If CMD23 +Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is +used. In case of Version 4.10 or later, use of Auto CMD Auto Select is +recommended rather than use of Auto CMD12 Enable or Auto CMD23 +Enable. + +This patch add this new mode support. + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/host/sdhci.c | 49 ++++++++++++++++++++++++++++++++++++++---------- + drivers/mmc/host/sdhci.h | 2 ++ + 2 files changed, 41 insertions(+), 10 deletions(-) + +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index da59b0a..dc5d75f 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1020,6 +1020,43 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host *host, + !mrq->cap_cmd_during_tfr; + } + ++static inline void sdhci_auto_cmd_select(struct sdhci_host *host, ++ struct mmc_command *cmd, ++ u16 *mode) ++{ ++ bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && ++ (cmd->opcode != SD_IO_RW_EXTENDED); ++ bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); ++ u16 ctrl2; ++ ++ /* ++ * In case of Version 4.10 or later, use of 'Auto CMD Auto ++ * Select' is recommended rather than use of 'Auto CMD12 ++ * Enable' or 'Auto CMD23 Enable'. ++ */ ++ if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { ++ *mode |= SDHCI_TRNS_AUTO_SEL; ++ ++ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ if (use_cmd23) ++ ctrl2 |= SDHCI_CMD23_ENABLE; ++ else ++ ctrl2 &= ~SDHCI_CMD23_ENABLE; ++ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); ++ ++ return; ++ } ++ ++ /* ++ * If we are sending CMD23, CMD12 never gets sent ++ * on successful completion (so no Auto-CMD12). ++ */ ++ if (use_cmd12) ++ *mode |= SDHCI_TRNS_AUTO_CMD12; ++ else if (use_cmd23) ++ *mode |= SDHCI_TRNS_AUTO_CMD23; ++} ++ + static void sdhci_set_transfer_mode(struct sdhci_host *host, + struct mmc_command *cmd) + { +@@ -1046,17 +1083,9 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, + + if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { + mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; +- /* +- * If we are sending CMD23, CMD12 never gets sent +- * on successful completion (so no Auto-CMD12). +- */ +- if (sdhci_auto_cmd12(host, cmd->mrq) && +- (cmd->opcode != SD_IO_RW_EXTENDED)) +- mode |= SDHCI_TRNS_AUTO_CMD12; +- else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { +- mode |= SDHCI_TRNS_AUTO_CMD23; ++ sdhci_auto_cmd_select(host, cmd, &mode); ++ if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) + sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); +- } + } + + if (data->flags & MMC_DATA_READ) +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 5197966..23ddc46 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -42,6 +42,7 @@ + #define SDHCI_TRNS_BLK_CNT_EN 0x02 + #define SDHCI_TRNS_AUTO_CMD12 0x04 + #define SDHCI_TRNS_AUTO_CMD23 0x08 ++#define SDHCI_TRNS_AUTO_SEL 0x0C + #define SDHCI_TRNS_READ 0x10 + #define SDHCI_TRNS_MULTI 0x20 + +@@ -185,6 +186,7 @@ + #define SDHCI_CTRL_DRV_TYPE_D 0x0030 + #define SDHCI_CTRL_EXEC_TUNING 0x0040 + #define SDHCI_CTRL_TUNED_CLK 0x0080 ++#define SDHCI_CMD23_ENABLE 0x0800 + #define SDHCI_CTRL_V4_MODE 0x1000 + #define SDHCI_CTRL_64BIT_ADDR 0x2000 + #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0109-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0109-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch new file mode 100755 index 00000000..50b0433b --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0109-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch @@ -0,0 +1,149 @@ +From c3dcaa45a3f29d943e18bc6470a80b827ac7a115 Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Tue, 22 Jan 2019 23:01:45 +0530 +Subject: [PATCH 109/131] amd-eMMC sdhci HS400 workaround for ZP + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/mmc/core/mmc.c | 12 ++++++++++-- + drivers/mmc/host/sdhci-acpi.c | 1 + + drivers/mmc/host/sdhci.c | 9 +++++++++ + drivers/mmc/host/sdhci.h | 1 + + include/linux/mmc/host.h | 1 + + 5 files changed, 22 insertions(+), 2 deletions(-) + mode change 100644 => 100755 drivers/mmc/core/mmc.c + mode change 100644 => 100755 drivers/mmc/host/sdhci-acpi.c + mode change 100644 => 100755 drivers/mmc/host/sdhci.c + mode change 100644 => 100755 include/linux/mmc/host.h + +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +old mode 100644 +new mode 100755 +index 16b22d7..2313e58 +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1161,7 +1161,9 @@ static int mmc_select_hs400(struct mmc_card *card) + mmc_hostname(host), err); + return err; + } ++ /*In AMD Platform due to hardware ip issue this fails*/ + ++ if (!host->ops->set_hs400_dll) { + /* Set host controller to HS timing */ + mmc_set_timing(card->host, MMC_TIMING_MMC_HS); + +@@ -1172,7 +1174,7 @@ static int mmc_select_hs400(struct mmc_card *card) + /* Reduce frequency to HS frequency */ + max_dtr = card->ext_csd.hs_max_dtr; + mmc_set_clock(host, max_dtr); +- ++ } + err = mmc_switch_status(card); + if (err) + goto out_err; +@@ -1212,6 +1214,8 @@ static int mmc_select_hs400(struct mmc_card *card) + if (host->ops->hs400_complete) + host->ops->hs400_complete(host); + ++ if (host->ops->set_hs400_dll) ++ host->ops->set_hs400_dll(host); + return 0; + + out_err: +@@ -1234,6 +1238,7 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + + /* Reduce frequency to HS */ + max_dtr = card->ext_csd.hs_max_dtr; ++ if (!host->ops->set_hs400_dll) + mmc_set_clock(host, max_dtr); + + /* Switch HS400 to HS DDR */ +@@ -1243,12 +1248,15 @@ int mmc_hs400_to_hs200(struct mmc_card *card) + true, false, true); + if (err) + goto out_err; +- ++ /*In AMD Platform due to hardware ip issue this fails*/ ++ if (!host->ops->set_hs400_dll) ++ { + mmc_set_timing(host, MMC_TIMING_MMC_DDR52); + + err = mmc_switch_status(card); + if (err) + goto out_err; ++ } + + /* Switch HS DDR to HS */ + err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, +diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c +old mode 100644 +new mode 100755 +index c2e7048..558b792 +--- a/drivers/mmc/host/sdhci-acpi.c ++++ b/drivers/mmc/host/sdhci-acpi.c +@@ -411,6 +411,7 @@ static const struct sdhci_ops sdhci_acpi_ops_amd = { + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, ++ .set_hs400_dll = sdhci_acpi_amd_hs400_dll, + }; + + static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = { +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +old mode 100644 +new mode 100755 +index dc5d75f..34c6a81 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1977,6 +1977,14 @@ static void sdhci_hw_reset(struct mmc_host *mmc) + host->ops->hw_reset(host); + } + ++static void sdhci_set_hs400_dll(struct mmc_host *mmc) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ ++ if (host->ops && host->ops->set_hs400_dll) ++ host->ops->set_hs400_dll(host); ++} ++ + static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) + { + if (!(host->flags & SDHCI_DEVICE_DEAD)) { +@@ -2465,6 +2473,7 @@ static const struct mmc_host_ops sdhci_ops = { + .get_cd = sdhci_get_cd, + .get_ro = sdhci_get_ro, + .hw_reset = sdhci_hw_reset, ++ .set_hs400_dll = sdhci_set_hs400_dll, + .enable_sdio_irq = sdhci_enable_sdio_irq, + .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, + .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 23ddc46..492401d 100755 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -611,6 +611,7 @@ struct sdhci_ops { + int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); + void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); + void (*hw_reset)(struct sdhci_host *host); ++ void (*set_hs400_dll)(struct sdhci_host *host); + void (*adma_workaround)(struct sdhci_host *host, u32 intmask); + void (*card_event)(struct sdhci_host *host); + void (*voltage_switch)(struct sdhci_host *host); +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +old mode 100644 +new mode 100755 +index 843c38f..ba4af38 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -159,6 +159,7 @@ struct mmc_host_ops { + unsigned int max_dtr, int host_drv, + int card_drv, int *drv_type); + void (*hw_reset)(struct mmc_host *host); ++ void (*set_hs400_dll)(struct mmc_host *host); + void (*card_event)(struct mmc_host *host); + + /* +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0110-pinctrl-eMMC-and-PinCtrl-is-sharing-the-interrupt-no.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0110-pinctrl-eMMC-and-PinCtrl-is-sharing-the-interrupt-no.patch new file mode 100755 index 00000000..e55c583a --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0110-pinctrl-eMMC-and-PinCtrl-is-sharing-the-interrupt-no.patch @@ -0,0 +1,29 @@ +From 2af564865343fa4b384fdb6c61138c07b8601cba Mon Sep 17 00:00:00 2001 +From: Ayyappa Chandolu <Ayyappa.Chandolu@amd.com> +Date: Fri, 2 Mar 2018 11:25:17 +0530 +Subject: [PATCH 110/131] pinctrl: eMMC and PinCtrl is sharing the interrupt no + 7 for Dibber. So PinCtrl must register the interrupt hadler with SHARED + flags. BUGID : EMBSWDEV-4739 + +Signed-off-by: Ayyappa Chandolu <Ayyappa.Chandolu@amd.com> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/pinctrl/pinctrl-amd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c +index b78f42a..f0e1f7c 100644 +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -896,7 +896,7 @@ static int amd_gpio_probe(struct platform_device *pdev) + goto out2; + } + +- ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, ++ ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, IRQF_SHARED, + KBUILD_MODNAME, gpio_dev); + if (ret) + goto out2; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0111-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0111-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch new file mode 100644 index 00000000..1a902632 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0111-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch @@ -0,0 +1,45 @@ +From a3c0851e777f229877dcd8480b254b2750a601c4 Mon Sep 17 00:00:00 2001 +From: YueHaibing <yuehaibing@huawei.com> +Date: Thu, 26 Jul 2018 09:51:27 +0800 +Subject: [PATCH 111/131] amd-xgbe: use dma_mapping_error to check map errors + +The dma_mapping_error() returns true or false, but we want +to return -ENOMEM if there was an error. + +Fixes: 174fd2597b0b ("amd-xgbe: Implement split header receive support") +Signed-off-by: YueHaibing <yuehaibing@huawei.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-desc.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c +index cc1e4f8..5330942 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c +@@ -289,7 +289,7 @@ static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, + struct page *pages = NULL; + dma_addr_t pages_dma; + gfp_t gfp; +- int order, ret; ++ int order; + + again: + order = alloc_order; +@@ -316,10 +316,9 @@ static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, + /* Map the pages */ + pages_dma = dma_map_page(pdata->dev, pages, 0, + PAGE_SIZE << order, DMA_FROM_DEVICE); +- ret = dma_mapping_error(pdata->dev, pages_dma); +- if (ret) { ++ if (dma_mapping_error(pdata->dev, pages_dma)) { + put_page(pages); +- return ret; ++ return -ENOMEM; + } + + pa->pages = pages; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0112-lib-crc-Move-polynomial-definition-to-separate-heade.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0112-lib-crc-Move-polynomial-definition-to-separate-heade.patch new file mode 100644 index 00000000..307bc389 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0112-lib-crc-Move-polynomial-definition-to-separate-heade.patch @@ -0,0 +1,96 @@ +From 56993bb2133c233893248f4611cdedddcefb9a79 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Tue, 17 Jul 2018 18:05:36 +0200 +Subject: [PATCH 112/131] lib/crc: Move polynomial definition to separate + header + +Allow other drivers and parts of kernel to use the same define for +CRC32 polynomial, instead of duplicating it in many places. This code +does not bring any functional changes, except moving existing code. + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + include/linux/crc32poly.h | 20 ++++++++++++++++++++ + lib/crc32.c | 1 + + lib/crc32defs.h | 14 -------------- + lib/gen_crc32table.c | 1 + + 4 files changed, 22 insertions(+), 14 deletions(-) + create mode 100644 include/linux/crc32poly.h + +diff --git a/include/linux/crc32poly.h b/include/linux/crc32poly.h +new file mode 100644 +index 0000000..7ad5aa9 +--- /dev/null ++++ b/include/linux/crc32poly.h +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _LINUX_CRC32_POLY_H ++#define _LINUX_CRC32_POLY_H ++ ++/* ++ * There are multiple 16-bit CRC polynomials in common use, but this is ++ * *the* standard CRC-32 polynomial, first popularized by Ethernet. ++ * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 ++ */ ++#define CRCPOLY_LE 0xedb88320 ++#define CRCPOLY_BE 0x04c11db7 ++ ++/* ++ * This is the CRC32c polynomial, as outlined by Castagnoli. ++ * x^32+x^28+x^27+x^26+x^25+x^23+x^22+x^20+x^19+x^18+x^14+x^13+x^11+x^10+x^9+ ++ * x^8+x^6+x^0 ++ */ ++#define CRC32C_POLY_LE 0x82F63B78 ++ ++#endif /* _LINUX_CRC32_POLY_H */ +diff --git a/lib/crc32.c b/lib/crc32.c +index 6ddc92b..82bfc053 100644 +--- a/lib/crc32.c ++++ b/lib/crc32.c +@@ -27,6 +27,7 @@ + /* see: Documentation/crc32.txt for a description of algorithms */ + + #include <linux/crc32.h> ++#include <linux/crc32poly.h> + #include <linux/module.h> + #include <linux/types.h> + #include <linux/sched.h> +diff --git a/lib/crc32defs.h b/lib/crc32defs.h +index cb275a2..0c8fb59 100644 +--- a/lib/crc32defs.h ++++ b/lib/crc32defs.h +@@ -1,18 +1,4 @@ + /* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * There are multiple 16-bit CRC polynomials in common use, but this is +- * *the* standard CRC-32 polynomial, first popularized by Ethernet. +- * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 +- */ +-#define CRCPOLY_LE 0xedb88320 +-#define CRCPOLY_BE 0x04c11db7 +- +-/* +- * This is the CRC32c polynomial, as outlined by Castagnoli. +- * x^32+x^28+x^27+x^26+x^25+x^23+x^22+x^20+x^19+x^18+x^14+x^13+x^11+x^10+x^9+ +- * x^8+x^6+x^0 +- */ +-#define CRC32C_POLY_LE 0x82F63B78 + + /* Try to choose an implementation variant via Kconfig */ + #ifdef CONFIG_CRC32_SLICEBY8 +diff --git a/lib/gen_crc32table.c b/lib/gen_crc32table.c +index 8f26660..34c3bc8 100644 +--- a/lib/gen_crc32table.c ++++ b/lib/gen_crc32table.c +@@ -1,5 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + #include <stdio.h> ++#include "../include/linux/crc32poly.h" + #include "../include/generated/autoconf.h" + #include "crc32defs.h" + #include <inttypes.h> +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0113-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0113-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch new file mode 100644 index 00000000..9b5511cd --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0113-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch @@ -0,0 +1,104 @@ +From 42b2ec07bcaa1a833a595937df05a7ee07627ef4 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Tue, 17 Jul 2018 18:05:37 +0200 +Subject: [PATCH 113/131] lib/crc: Use consistent naming for CRC-32 polynomials + +Header was defining CRCPOLY_LE/BE and CRC32C_POLY_LE but in fact all of +them are CRC-32 polynomials so use consistent naming. + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + include/linux/crc32poly.h | 4 ++-- + lib/crc32.c | 10 +++++----- + lib/gen_crc32table.c | 4 ++-- + 3 files changed, 9 insertions(+), 9 deletions(-) + +diff --git a/include/linux/crc32poly.h b/include/linux/crc32poly.h +index 7ad5aa9..62c4b77 100644 +--- a/include/linux/crc32poly.h ++++ b/include/linux/crc32poly.h +@@ -7,8 +7,8 @@ + * *the* standard CRC-32 polynomial, first popularized by Ethernet. + * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 + */ +-#define CRCPOLY_LE 0xedb88320 +-#define CRCPOLY_BE 0x04c11db7 ++#define CRC32_POLY_LE 0xedb88320 ++#define CRC32_POLY_BE 0x04c11db7 + + /* + * This is the CRC32c polynomial, as outlined by Castagnoli. +diff --git a/lib/crc32.c b/lib/crc32.c +index 82bfc053..7111c44 100644 +--- a/lib/crc32.c ++++ b/lib/crc32.c +@@ -185,7 +185,7 @@ static inline u32 __pure crc32_le_generic(u32 crc, unsigned char const *p, + #if CRC_LE_BITS == 1 + u32 __pure crc32_le(u32 crc, unsigned char const *p, size_t len) + { +- return crc32_le_generic(crc, p, len, NULL, CRCPOLY_LE); ++ return crc32_le_generic(crc, p, len, NULL, CRC32_POLY_LE); + } + u32 __pure __crc32c_le(u32 crc, unsigned char const *p, size_t len) + { +@@ -195,7 +195,7 @@ u32 __pure __crc32c_le(u32 crc, unsigned char const *p, size_t len) + u32 __pure crc32_le(u32 crc, unsigned char const *p, size_t len) + { + return crc32_le_generic(crc, p, len, +- (const u32 (*)[256])crc32table_le, CRCPOLY_LE); ++ (const u32 (*)[256])crc32table_le, CRC32_POLY_LE); + } + u32 __pure __crc32c_le(u32 crc, unsigned char const *p, size_t len) + { +@@ -269,7 +269,7 @@ static u32 __attribute_const__ crc32_generic_shift(u32 crc, size_t len, + + u32 __attribute_const__ crc32_le_shift(u32 crc, size_t len) + { +- return crc32_generic_shift(crc, len, CRCPOLY_LE); ++ return crc32_generic_shift(crc, len, CRC32_POLY_LE); + } + + u32 __attribute_const__ __crc32c_le_shift(u32 crc, size_t len) +@@ -331,13 +331,13 @@ static inline u32 __pure crc32_be_generic(u32 crc, unsigned char const *p, + #if CRC_LE_BITS == 1 + u32 __pure crc32_be(u32 crc, unsigned char const *p, size_t len) + { +- return crc32_be_generic(crc, p, len, NULL, CRCPOLY_BE); ++ return crc32_be_generic(crc, p, len, NULL, CRC32_POLY_BE); + } + #else + u32 __pure crc32_be(u32 crc, unsigned char const *p, size_t len) + { + return crc32_be_generic(crc, p, len, +- (const u32 (*)[256])crc32table_be, CRCPOLY_BE); ++ (const u32 (*)[256])crc32table_be, CRC32_POLY_BE); + } + #endif + EXPORT_SYMBOL(crc32_be); +diff --git a/lib/gen_crc32table.c b/lib/gen_crc32table.c +index 34c3bc8..f755b99 100644 +--- a/lib/gen_crc32table.c ++++ b/lib/gen_crc32table.c +@@ -58,7 +58,7 @@ static void crc32init_le_generic(const uint32_t polynomial, + + static void crc32init_le(void) + { +- crc32init_le_generic(CRCPOLY_LE, crc32table_le); ++ crc32init_le_generic(CRC32_POLY_LE, crc32table_le); + } + + static void crc32cinit_le(void) +@@ -77,7 +77,7 @@ static void crc32init_be(void) + crc32table_be[0][0] = 0; + + for (i = 1; i < BE_TABLE_SIZE; i <<= 1) { +- crc = (crc << 1) ^ ((crc & 0x80000000) ? CRCPOLY_BE : 0); ++ crc = (crc << 1) ^ ((crc & 0x80000000) ? CRC32_POLY_BE : 0); + for (j = 0; j < i; j++) + crc32table_be[0][i + j] = crc ^ crc32table_be[0][j]; + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0114-net-ethernet-Use-existing-define-with-polynomial.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0114-net-ethernet-Use-existing-define-with-polynomial.patch new file mode 100644 index 00000000..da9af087 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0114-net-ethernet-Use-existing-define-with-polynomial.patch @@ -0,0 +1,46 @@ +From dd77e87d25cb432b40a5dbc1b6c6dcada717ce69 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Tue, 17 Jul 2018 18:05:39 +0200 +Subject: [PATCH 114/131] net: ethernet: Use existing define with polynomial + +Do not define again the polynomial but use header with existing define. + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +index e107e18..1e929a1 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +@@ -119,6 +119,7 @@ + #include <linux/clk.h> + #include <linux/bitrev.h> + #include <linux/crc32.h> ++#include <linux/crc32poly.h> + + #include "xgbe.h" + #include "xgbe-common.h" +@@ -887,7 +888,6 @@ static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) + + static u32 xgbe_vid_crc32_le(__le16 vid_le) + { +- u32 poly = 0xedb88320; /* CRCPOLY_LE */ + u32 crc = ~0; + u32 temp = 0; + unsigned char *data = (unsigned char *)&vid_le; +@@ -904,7 +904,7 @@ static u32 xgbe_vid_crc32_le(__le16 vid_le) + data_byte >>= 1; + + if (temp) +- crc ^= poly; ++ crc ^= CRC32_POLY_LE; + } + + return crc; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0115-net-amd-fix-return-type-of-ndo_start_xmit-function.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0115-net-amd-fix-return-type-of-ndo_start_xmit-function.patch new file mode 100644 index 00000000..2c9e4bc1 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0115-net-amd-fix-return-type-of-ndo_start_xmit-function.patch @@ -0,0 +1,44 @@ +From 836d2feccaa1e38e4d3c6adab713f9f6d579cd7f Mon Sep 17 00:00:00 2001 +From: YueHaibing <yuehaibing@huawei.com> +Date: Wed, 19 Sep 2018 18:50:17 +0800 +Subject: [PATCH 115/131] net: amd: fix return type of ndo_start_xmit function + +The method ndo_start_xmit() is defined as returning an 'netdev_tx_t', +which is a typedef for an enum type, so make sure the implementation in +this driver has returns 'netdev_tx_t' value, and change the function +return type to netdev_tx_t. + +Found by coccinelle. + +Signed-off-by: YueHaibing <yuehaibing@huawei.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index 8cfba4b..d85272d 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -2009,7 +2009,7 @@ static int xgbe_close(struct net_device *netdev) + return 0; + } + +-static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) ++static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) + { + struct xgbe_prv_data *pdata = netdev_priv(netdev); + struct xgbe_hw_if *hw_if = &pdata->hw_if; +@@ -2018,7 +2018,7 @@ static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) + struct xgbe_ring *ring; + struct xgbe_packet_data *packet; + struct netdev_queue *txq; +- int ret; ++ netdev_tx_t ret; + + DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0116-net-phy-Add-helper-for-advertise-to-lcl-value.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0116-net-phy-Add-helper-for-advertise-to-lcl-value.patch new file mode 100644 index 00000000..4afd6f7d --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0116-net-phy-Add-helper-for-advertise-to-lcl-value.patch @@ -0,0 +1,71 @@ +From 6bb7c3d2ca408f41be6c4a9d51cba757fc53afcb Mon Sep 17 00:00:00 2001 +From: Andrew Lunn <andrew@lunn.ch> +Date: Sat, 29 Sep 2018 23:04:13 +0200 +Subject: [PATCH 116/131] net: phy: Add helper for advertise to lcl value + +Add a helper to convert the local advertising to an LCL capabilities, +which is then used to resolve pause flow control settings. + +Signed-off-by: Andrew Lunn <andrew@lunn.ch> +Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> +Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 5 +---- + include/linux/mii.h | 20 ++++++++++++++++++++ + 2 files changed, 21 insertions(+), 4 deletions(-) + mode change 100644 => 100755 include/linux/mii.h + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +index 3ceb4f9..5f01b36 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -1495,10 +1495,7 @@ static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) + if (!phy_data->phydev) + return; + +- if (phy_data->phydev->advertising & ADVERTISED_Pause) +- lcl_adv |= ADVERTISE_PAUSE_CAP; +- if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause) +- lcl_adv |= ADVERTISE_PAUSE_ASYM; ++ lcl_adv = ethtool_adv_to_lcl_adv_t(phy_data->phydev->advertising); + + if (phy_data->phydev->pause) { + XGBE_SET_LP_ADV(lks, Pause); +diff --git a/include/linux/mii.h b/include/linux/mii.h +old mode 100644 +new mode 100755 +index 55000ee..63cd587 +--- a/include/linux/mii.h ++++ b/include/linux/mii.h +@@ -302,6 +302,26 @@ static inline u32 mii_lpa_to_ethtool_lpa_x(u32 lpa) + return result | mii_adv_to_ethtool_adv_x(lpa); + } + ++ ++/** ++ * ethtool_adv_to_lcl_adv_t ++ * @advertising:pointer to ethtool advertising ++ * ++ * A small helper function that translates ethtool advertising to LVL ++ * pause capabilities. ++ */ ++static inline u32 ethtool_adv_to_lcl_adv_t(u32 advertising) ++{ ++ u32 lcl_adv = 0; ++ ++ if (advertising & ADVERTISED_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_CAP; ++ if (advertising & ADVERTISED_Asym_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_ASYM; ++ ++ return lcl_adv; ++} ++ + /** + * mii_advertise_flowctrl - get flow control advertisement flags + * @cap: Flow control capabilities (FLOW_CTRL_RX, FLOW_CTRL_TX or both) +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0117-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0117-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch new file mode 100644 index 00000000..c86cba1c --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0117-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch @@ -0,0 +1,35 @@ +From e3655f57f50fd9cd92336563a2cfadcda06bad25 Mon Sep 17 00:00:00 2001 +From: Eric Dumazet <edumazet@google.com> +Date: Thu, 25 Oct 2018 06:42:12 -0700 +Subject: [PATCH 117/131] drivers: net: remove <net/busy_poll.h> inclusion when + not needed + +Drivers using generic NAPI interface no longer need to include +<net/busy_poll.h>, since busy polling was moved to core networking +stack long ago. + +See commit 79e7fff47b7b ("net: remove support for per driver +ndo_busy_poll()") for reference. + +Signed-off-by: Eric Dumazet <edumazet@google.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index d85272d..649a283 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -119,7 +119,6 @@ + #include <linux/tcp.h> + #include <linux/if_vlan.h> + #include <linux/interrupt.h> +-#include <net/busy_poll.h> + #include <linux/clk.h> + #include <linux/if_ether.h> + #include <linux/net_tstamp.h> +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0118-net-ethernet-xgbe-expand-PHY_GBIT_FEAUTRES.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0118-net-ethernet-xgbe-expand-PHY_GBIT_FEAUTRES.patch new file mode 100644 index 00000000..9df6d48a --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0118-net-ethernet-xgbe-expand-PHY_GBIT_FEAUTRES.patch @@ -0,0 +1,104 @@ +From f5aaf7afea74803350355aec49db4c4dfed8d55f Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Sun, 11 Nov 2018 23:32:49 +0530 +Subject: [PATCH 118/131] net: ethernet: xgbe: expand PHY_GBIT_FEAUTRES + +From d0939c26c53a2b2cecfbe6953858a58abb0158c7 +The macro PHY_GBIT_FEAUTRES needs to change into a bitmap in order to +support link_modes. Remove its use from xgde by replacing it with its +definition. + +Probably, the current behavior is wrong. It probably should be +ANDing not assigning. + +Signed-off-by: Andrew Lunn <andrew@lunn.ch> +Signed-off-by: David S. Miller <davem@davemloft.net> + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 14 ++++++++------ + drivers/net/phy/phy_device.c | 14 ++++++++++++++ + include/linux/phy.h | 1 + + 3 files changed, 23 insertions(+), 6 deletions(-) + mode change 100644 => 100755 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c + mode change 100644 => 100755 drivers/net/phy/phy_device.c + mode change 100644 => 100755 include/linux/phy.h + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +old mode 100644 +new mode 100755 +index 5f01b36..151bdb6 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -878,9 +878,10 @@ static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) + phy_write(phy_data->phydev, 0x04, 0x0d01); + phy_write(phy_data->phydev, 0x00, 0x9140); + +- phy_data->phydev->supported = PHY_GBIT_FEATURES; +- phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; +- phy_data->phydev->advertising = phy_data->phydev->supported; ++ phy_data->phydev->supported = PHY_10BT_FEATURES | ++ PHY_100BT_FEATURES | ++ PHY_1000BT_FEATURES; ++ phy_support_asym_pause(phy_data->phydev); + + netif_dbg(pdata, drv, pdata->netdev, + "Finisar PHY quirk in place\n"); +@@ -950,9 +951,10 @@ static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) + reg = phy_read(phy_data->phydev, 0x00); + phy_write(phy_data->phydev, 0x00, reg & ~0x00800); + +- phy_data->phydev->supported = PHY_GBIT_FEATURES; +- phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; +- phy_data->phydev->advertising = phy_data->phydev->supported; ++ phy_data->phydev->supported = (PHY_10BT_FEATURES | ++ PHY_100BT_FEATURES | ++ PHY_1000BT_FEATURES); ++ phy_support_asym_pause(phy_data->phydev); + + netif_dbg(pdata, drv, pdata->netdev, + "BelFuse PHY quirk in place\n"); +diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c +old mode 100644 +new mode 100755 +index fe76e2c..f16af99 +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -1736,6 +1736,20 @@ int phy_set_max_speed(struct phy_device *phydev, u32 max_speed) + } + EXPORT_SYMBOL(phy_set_max_speed); + ++/** ++ * phy_support_asym_pause - Enable support of asym pause ++ * @phydev: target phy_device struct ++ * ++ * Description: Called by the MAC to indicate is supports Asym Pause. ++ */ ++void phy_support_asym_pause(struct phy_device *phydev) ++{ ++ phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; ++ phydev->advertising = phydev->supported; ++} ++EXPORT_SYMBOL(phy_support_asym_pause); ++ ++ + static void of_set_phy_supported(struct phy_device *phydev) + { + struct device_node *node = phydev->mdio.dev.of_node; +diff --git a/include/linux/phy.h b/include/linux/phy.h +old mode 100644 +new mode 100755 +index efc04c2..38d36a6 +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -913,6 +913,7 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); + int phy_start_interrupts(struct phy_device *phydev); + void phy_print_status(struct phy_device *phydev); + int phy_set_max_speed(struct phy_device *phydev, u32 max_speed); ++void phy_support_asym_pause(struct phy_device *phydev); + + int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask, + int (*run)(struct phy_device *)); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0119-crypto-ahash-remove-useless-setting-of-type-flags.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0119-crypto-ahash-remove-useless-setting-of-type-flags.patch new file mode 100644 index 00000000..c92bf5fa --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0119-crypto-ahash-remove-useless-setting-of-type-flags.patch @@ -0,0 +1,53 @@ +From 358e73a569470ef44a142ecd1cd096587b5e9da2 Mon Sep 17 00:00:00 2001 +From: Eric Biggers <ebiggers@google.com> +Date: Sat, 30 Jun 2018 15:16:12 -0700 +Subject: [PATCH 119/131] crypto: ahash - remove useless setting of type flags + +Many ahash algorithms set .cra_flags = CRYPTO_ALG_TYPE_AHASH. But this +is redundant with the C structure type ('struct ahash_alg'), and +crypto_register_ahash() already sets the type flag automatically, +clearing any type flag that was already there. Apparently the useless +assignment has just been copy+pasted around. + +So, remove the useless assignment from all the ahash algorithms. + +This patch shouldn't change any actual behavior. + +Signed-off-by: Eric Biggers <ebiggers@google.com> +Acked-by: Gilad Ben-Yossef <gilad@benyossef.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/ccp-crypto-aes-cmac.c | 2 +- + drivers/crypto/ccp/ccp-crypto-sha.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/ccp/ccp-crypto-aes-cmac.c b/drivers/crypto/ccp/ccp-crypto-aes-cmac.c +index 26687f31..bdc2715 100644 +--- a/drivers/crypto/ccp/ccp-crypto-aes-cmac.c ++++ b/drivers/crypto/ccp/ccp-crypto-aes-cmac.c +@@ -399,7 +399,7 @@ int ccp_register_aes_cmac_algs(struct list_head *head) + base = &halg->base; + snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "cmac(aes)"); + snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "cmac-aes-ccp"); +- base->cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC | ++ base->cra_flags = CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK; + base->cra_blocksize = AES_BLOCK_SIZE; +diff --git a/drivers/crypto/ccp/ccp-crypto-sha.c b/drivers/crypto/ccp/ccp-crypto-sha.c +index 871c962..366d3e91 100644 +--- a/drivers/crypto/ccp/ccp-crypto-sha.c ++++ b/drivers/crypto/ccp/ccp-crypto-sha.c +@@ -497,7 +497,7 @@ static int ccp_register_sha_alg(struct list_head *head, + snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); + snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", + def->drv_name); +- base->cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC | ++ base->cra_flags = CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK; + base->cra_blocksize = def->block_size; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0120-crypto-ahash-remove-useless-setting-of-cra_type.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0120-crypto-ahash-remove-useless-setting-of-cra_type.patch new file mode 100644 index 00000000..1bfe42e0 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0120-crypto-ahash-remove-useless-setting-of-cra_type.patch @@ -0,0 +1,50 @@ +From d57a98634e755d7dcee23732946cf1592dde2981 Mon Sep 17 00:00:00 2001 +From: Eric Biggers <ebiggers@google.com> +Date: Sat, 30 Jun 2018 15:16:13 -0700 +Subject: [PATCH 120/131] crypto: ahash - remove useless setting of cra_type + +Some ahash algorithms set .cra_type = &crypto_ahash_type. But this is +redundant with the C structure type ('struct ahash_alg'), and +crypto_register_ahash() already sets the .cra_type automatically. +Apparently the useless assignment has just been copy+pasted around. + +So, remove the useless assignment from all the ahash algorithms. + +This patch shouldn't change any actual behavior. + +Signed-off-by: Eric Biggers <ebiggers@google.com> +Acked-by: Gilad Ben-Yossef <gilad@benyossef.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/ccp-crypto-aes-cmac.c | 1 - + drivers/crypto/ccp/ccp-crypto-sha.c | 1 - + 2 files changed, 2 deletions(-) + +diff --git a/drivers/crypto/ccp/ccp-crypto-aes-cmac.c b/drivers/crypto/ccp/ccp-crypto-aes-cmac.c +index bdc2715..3c6fe57 100644 +--- a/drivers/crypto/ccp/ccp-crypto-aes-cmac.c ++++ b/drivers/crypto/ccp/ccp-crypto-aes-cmac.c +@@ -405,7 +405,6 @@ int ccp_register_aes_cmac_algs(struct list_head *head) + base->cra_blocksize = AES_BLOCK_SIZE; + base->cra_ctxsize = sizeof(struct ccp_ctx); + base->cra_priority = CCP_CRA_PRIORITY; +- base->cra_type = &crypto_ahash_type; + base->cra_init = ccp_aes_cmac_cra_init; + base->cra_exit = ccp_aes_cmac_cra_exit; + base->cra_module = THIS_MODULE; +diff --git a/drivers/crypto/ccp/ccp-crypto-sha.c b/drivers/crypto/ccp/ccp-crypto-sha.c +index 366d3e91..2ca64bb 100644 +--- a/drivers/crypto/ccp/ccp-crypto-sha.c ++++ b/drivers/crypto/ccp/ccp-crypto-sha.c +@@ -503,7 +503,6 @@ static int ccp_register_sha_alg(struct list_head *head, + base->cra_blocksize = def->block_size; + base->cra_ctxsize = sizeof(struct ccp_ctx); + base->cra_priority = CCP_CRA_PRIORITY; +- base->cra_type = &crypto_ahash_type; + base->cra_init = ccp_sha_cra_init; + base->cra_exit = ccp_sha_cra_exit; + base->cra_module = THIS_MODULE; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0121-crypto-ccp-Fix-command-completion-detection-race.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0121-crypto-ccp-Fix-command-completion-detection-race.patch new file mode 100644 index 00000000..f4b839c7 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0121-crypto-ccp-Fix-command-completion-detection-race.patch @@ -0,0 +1,50 @@ +From b17bd890fe5b98844c4fa5d44cc461dd82206d88 Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue, 3 Jul 2018 12:11:33 -0500 +Subject: [PATCH 121/131] crypto: ccp - Fix command completion detection race + +The wait_event() function is used to detect command completion. The +interrupt handler will set the wait condition variable when the interrupt +is triggered. However, the variable used for wait_event() is initialized +after the command has been submitted, which can create a race condition +with the interrupt handler and result in the wait_event() never returning. +Move the initialization of the wait condition variable to just before +command submission. + +Fixes: 200664d5237f ("crypto: ccp: Add Secure Encrypted Virtualization (SEV) command support") +Cc: <stable@vger.kernel.org> # 4.16.x- +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Reviewed-by: Brijesh Singh <brijesh.singh@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index ff478d8..973d683 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -84,8 +84,6 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + + static void sev_wait_cmd_ioc(struct psp_device *psp, unsigned int *reg) + { +- psp->sev_int_rcvd = 0; +- + wait_event(psp->sev_int_queue, psp->sev_int_rcvd); + *reg = ioread32(psp->io_regs + PSP_CMDRESP); + } +@@ -148,6 +146,8 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) + iowrite32(phys_lsb, psp->io_regs + PSP_CMDBUFF_ADDR_LO); + iowrite32(phys_msb, psp->io_regs + PSP_CMDBUFF_ADDR_HI); + ++ psp->sev_int_rcvd = 0; ++ + reg = cmd; + reg <<= PSP_CMDRESP_CMD_SHIFT; + reg |= PSP_CMDRESP_IOC; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0122-crypto-ccp-Add-psp-enabled-message-when-initializati.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0122-crypto-ccp-Add-psp-enabled-message-when-initializati.patch new file mode 100644 index 00000000..70b2329c --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0122-crypto-ccp-Add-psp-enabled-message-when-initializati.patch @@ -0,0 +1,33 @@ +From ab02d4a5788696d7676a31d8e769a6015c1e1d81 Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue, 3 Jul 2018 12:11:42 -0500 +Subject: [PATCH 122/131] crypto: ccp - Add psp enabled message when + initialization succeeds + +Add a dev_notice() message to the PSP initialization to report when the +PSP initialization has succeeded and the PSP is enabled. + +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index 973d683..91ef6ed 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -840,6 +840,8 @@ int psp_dev_init(struct sp_device *sp) + /* Enable interrupt */ + iowrite32(-1, psp->io_regs + PSP_P2CMSG_INTEN); + ++ dev_notice(dev, "psp enabled\n"); ++ + return 0; + + e_irq: +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0123-crypto-ccp-Remove-unused-defines.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0123-crypto-ccp-Remove-unused-defines.patch new file mode 100644 index 00000000..6afd62dd --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0123-crypto-ccp-Remove-unused-defines.patch @@ -0,0 +1,60 @@ +From 485ff2cab884dc2fa30d115411f4e84c3e3378bf Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue, 3 Jul 2018 12:11:52 -0500 +Subject: [PATCH 123/131] crypto: ccp - Remove unused #defines + +Remove some unused #defines for register offsets that are not used. This +will lessen the changes required when register offsets change between +versions of the device. + +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Reviewed-by: Brijesh Singh <brijesh.singh@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 2 +- + drivers/crypto/ccp/psp-dev.h | 10 +--------- + 2 files changed, 2 insertions(+), 10 deletions(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index 91ef6ed..875756d 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -65,7 +65,7 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + status = ioread32(psp->io_regs + PSP_P2CMSG_INTSTS); + + /* Check if it is command completion: */ +- if (!(status & BIT(PSP_CMD_COMPLETE_REG))) ++ if (!(status & PSP_CMD_COMPLETE)) + goto done; + + /* Check if it is SEV command completion: */ +diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h +index c7e9098a..5d46a2b 100644 +--- a/drivers/crypto/ccp/psp-dev.h ++++ b/drivers/crypto/ccp/psp-dev.h +@@ -36,19 +36,11 @@ + #define PSP_CMDBUFF_ADDR_HI PSP_C2PMSG(57) + #define PSP_FEATURE_REG PSP_C2PMSG(63) + +-#define PSP_P2CMSG(_num) ((_num) << 2) +-#define PSP_CMD_COMPLETE_REG 1 +-#define PSP_CMD_COMPLETE PSP_P2CMSG(PSP_CMD_COMPLETE_REG) ++#define PSP_CMD_COMPLETE BIT(1) + + #define PSP_P2CMSG_INTEN 0x0110 + #define PSP_P2CMSG_INTSTS 0x0114 + +-#define PSP_C2PMSG_ATTR_0 0x0118 +-#define PSP_C2PMSG_ATTR_1 0x011c +-#define PSP_C2PMSG_ATTR_2 0x0120 +-#define PSP_C2PMSG_ATTR_3 0x0124 +-#define PSP_P2CMSG_ATTR_0 0x0128 +- + #define PSP_CMDRESP_CMD_SHIFT 16 + #define PSP_CMDRESP_IOC BIT(0) + #define PSP_CMDRESP_RESP BIT(31) +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0124-crypto-ccp-Support-register-differences-between-PSP-.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0124-crypto-ccp-Support-register-differences-between-PSP-.patch new file mode 100644 index 00000000..500fa33f --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0124-crypto-ccp-Support-register-differences-between-PSP-.patch @@ -0,0 +1,174 @@ +From 6360af3cdfe923a6acf0ab33c513b3a3ed517197 Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue, 3 Jul 2018 12:12:03 -0500 +Subject: [PATCH 124/131] crypto: ccp - Support register differences between + PSP devices + +In preparation for adding a new PSP device ID that uses different register +offsets, add support to the PSP version data for register offset values. +And then update the code to use these new register offset values. + +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Reviewed-by: Brijesh Singh <brijesh.singh@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 24 ++++++++++++------------ + drivers/crypto/ccp/psp-dev.h | 9 --------- + drivers/crypto/ccp/sp-dev.h | 7 ++++++- + drivers/crypto/ccp/sp-pci.c | 7 ++++++- + 4 files changed, 24 insertions(+), 23 deletions(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index 875756d..9b59638 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -62,14 +62,14 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + int reg; + + /* Read the interrupt status: */ +- status = ioread32(psp->io_regs + PSP_P2CMSG_INTSTS); ++ status = ioread32(psp->io_regs + psp->vdata->intsts_reg); + + /* Check if it is command completion: */ + if (!(status & PSP_CMD_COMPLETE)) + goto done; + + /* Check if it is SEV command completion: */ +- reg = ioread32(psp->io_regs + PSP_CMDRESP); ++ reg = ioread32(psp->io_regs + psp->vdata->cmdresp_reg); + if (reg & PSP_CMDRESP_RESP) { + psp->sev_int_rcvd = 1; + wake_up(&psp->sev_int_queue); +@@ -77,7 +77,7 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + + done: + /* Clear the interrupt status by writing the same value we read. */ +- iowrite32(status, psp->io_regs + PSP_P2CMSG_INTSTS); ++ iowrite32(status, psp->io_regs + psp->vdata->intsts_reg); + + return IRQ_HANDLED; + } +@@ -85,7 +85,7 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + static void sev_wait_cmd_ioc(struct psp_device *psp, unsigned int *reg) + { + wait_event(psp->sev_int_queue, psp->sev_int_rcvd); +- *reg = ioread32(psp->io_regs + PSP_CMDRESP); ++ *reg = ioread32(psp->io_regs + psp->vdata->cmdresp_reg); + } + + static int sev_cmd_buffer_len(int cmd) +@@ -143,15 +143,15 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) + print_hex_dump_debug("(in): ", DUMP_PREFIX_OFFSET, 16, 2, data, + sev_cmd_buffer_len(cmd), false); + +- iowrite32(phys_lsb, psp->io_regs + PSP_CMDBUFF_ADDR_LO); +- iowrite32(phys_msb, psp->io_regs + PSP_CMDBUFF_ADDR_HI); ++ iowrite32(phys_lsb, psp->io_regs + psp->vdata->cmdbuff_addr_lo_reg); ++ iowrite32(phys_msb, psp->io_regs + psp->vdata->cmdbuff_addr_hi_reg); + + psp->sev_int_rcvd = 0; + + reg = cmd; + reg <<= PSP_CMDRESP_CMD_SHIFT; + reg |= PSP_CMDRESP_IOC; +- iowrite32(reg, psp->io_regs + PSP_CMDRESP); ++ iowrite32(reg, psp->io_regs + psp->vdata->cmdresp_reg); + + /* wait for command completion */ + sev_wait_cmd_ioc(psp, ®); +@@ -789,7 +789,7 @@ static int sev_misc_init(struct psp_device *psp) + static int sev_init(struct psp_device *psp) + { + /* Check if device supports SEV feature */ +- if (!(ioread32(psp->io_regs + PSP_FEATURE_REG) & 1)) { ++ if (!(ioread32(psp->io_regs + psp->vdata->feature_reg) & 1)) { + dev_dbg(psp->dev, "device does not support SEV\n"); + return 1; + } +@@ -817,11 +817,11 @@ int psp_dev_init(struct sp_device *sp) + goto e_err; + } + +- psp->io_regs = sp->io_map + psp->vdata->offset; ++ psp->io_regs = sp->io_map; + + /* Disable and clear interrupts until ready */ +- iowrite32(0, psp->io_regs + PSP_P2CMSG_INTEN); +- iowrite32(-1, psp->io_regs + PSP_P2CMSG_INTSTS); ++ iowrite32(0, psp->io_regs + psp->vdata->inten_reg); ++ iowrite32(-1, psp->io_regs + psp->vdata->intsts_reg); + + /* Request an irq */ + ret = sp_request_psp_irq(psp->sp, psp_irq_handler, psp->name, psp); +@@ -838,7 +838,7 @@ int psp_dev_init(struct sp_device *sp) + sp->set_psp_master_device(sp); + + /* Enable interrupt */ +- iowrite32(-1, psp->io_regs + PSP_P2CMSG_INTEN); ++ iowrite32(-1, psp->io_regs + psp->vdata->inten_reg); + + dev_notice(dev, "psp enabled\n"); + +diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h +index 5d46a2b..8b53a96 100644 +--- a/drivers/crypto/ccp/psp-dev.h ++++ b/drivers/crypto/ccp/psp-dev.h +@@ -30,17 +30,8 @@ + + #include "sp-dev.h" + +-#define PSP_C2PMSG(_num) ((_num) << 2) +-#define PSP_CMDRESP PSP_C2PMSG(32) +-#define PSP_CMDBUFF_ADDR_LO PSP_C2PMSG(56) +-#define PSP_CMDBUFF_ADDR_HI PSP_C2PMSG(57) +-#define PSP_FEATURE_REG PSP_C2PMSG(63) +- + #define PSP_CMD_COMPLETE BIT(1) + +-#define PSP_P2CMSG_INTEN 0x0110 +-#define PSP_P2CMSG_INTSTS 0x0114 +- + #define PSP_CMDRESP_CMD_SHIFT 16 + #define PSP_CMDRESP_IOC BIT(0) + #define PSP_CMDRESP_RESP BIT(31) +diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h +index acb197b..14398ca 100644 +--- a/drivers/crypto/ccp/sp-dev.h ++++ b/drivers/crypto/ccp/sp-dev.h +@@ -44,7 +44,12 @@ struct ccp_vdata { + }; + + struct psp_vdata { +- const unsigned int offset; ++ const unsigned int cmdresp_reg; ++ const unsigned int cmdbuff_addr_lo_reg; ++ const unsigned int cmdbuff_addr_hi_reg; ++ const unsigned int feature_reg; ++ const unsigned int inten_reg; ++ const unsigned int intsts_reg; + }; + + /* Structure to hold SP device data */ +diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c +index f5f43c5..78c1e9d 100644 +--- a/drivers/crypto/ccp/sp-pci.c ++++ b/drivers/crypto/ccp/sp-pci.c +@@ -270,7 +270,12 @@ static int sp_pci_resume(struct pci_dev *pdev) + + #ifdef CONFIG_CRYPTO_DEV_SP_PSP + static const struct psp_vdata psp_entry = { +- .offset = 0x10500, ++ .cmdresp_reg = 0x10580, ++ .cmdbuff_addr_lo_reg = 0x105e0, ++ .cmdbuff_addr_hi_reg = 0x105e4, ++ .feature_reg = 0x105fc, ++ .inten_reg = 0x10610, ++ .intsts_reg = 0x10614, + }; + #endif + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0125-crypto-ccp-Add-support-for-new-CCP-PSP-device-ID.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0125-crypto-ccp-Add-support-for-new-CCP-PSP-device-ID.patch new file mode 100644 index 00000000..7ad5b245 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0125-crypto-ccp-Add-support-for-new-CCP-PSP-device-ID.patch @@ -0,0 +1,91 @@ +From 6c141587c3316d92d7230fa7106a855003c3084b Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue, 3 Jul 2018 12:12:14 -0500 +Subject: [PATCH 125/131] crypto: ccp - Add support for new CCP/PSP device ID + +Add a new CCP/PSP PCI device ID and new PSP register offsets. + +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Reviewed-by: Brijesh Singh <brijesh.singh@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/sp-pci.c | 29 ++++++++++++++++++++++++----- + 1 file changed, 24 insertions(+), 5 deletions(-) + +diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c +index 78c1e9d..7da93e9 100644 +--- a/drivers/crypto/ccp/sp-pci.c ++++ b/drivers/crypto/ccp/sp-pci.c +@@ -269,7 +269,7 @@ static int sp_pci_resume(struct pci_dev *pdev) + #endif + + #ifdef CONFIG_CRYPTO_DEV_SP_PSP +-static const struct psp_vdata psp_entry = { ++static const struct psp_vdata pspv1 = { + .cmdresp_reg = 0x10580, + .cmdbuff_addr_lo_reg = 0x105e0, + .cmdbuff_addr_hi_reg = 0x105e4, +@@ -277,35 +277,54 @@ static const struct psp_vdata psp_entry = { + .inten_reg = 0x10610, + .intsts_reg = 0x10614, + }; ++ ++static const struct psp_vdata pspv2 = { ++ .cmdresp_reg = 0x10980, ++ .cmdbuff_addr_lo_reg = 0x109e0, ++ .cmdbuff_addr_hi_reg = 0x109e4, ++ .feature_reg = 0x109fc, ++ .inten_reg = 0x10690, ++ .intsts_reg = 0x10694, ++}; + #endif + + static const struct sp_dev_vdata dev_vdata[] = { +- { ++ { /* 0 */ + .bar = 2, + #ifdef CONFIG_CRYPTO_DEV_SP_CCP + .ccp_vdata = &ccpv3, + #endif + }, +- { ++ { /* 1 */ + .bar = 2, + #ifdef CONFIG_CRYPTO_DEV_SP_CCP + .ccp_vdata = &ccpv5a, + #endif + #ifdef CONFIG_CRYPTO_DEV_SP_PSP +- .psp_vdata = &psp_entry ++ .psp_vdata = &pspv1, + #endif + }, +- { ++ { /* 2 */ + .bar = 2, + #ifdef CONFIG_CRYPTO_DEV_SP_CCP + .ccp_vdata = &ccpv5b, + #endif + }, ++ { /* 3 */ ++ .bar = 2, ++#ifdef CONFIG_CRYPTO_DEV_SP_CCP ++ .ccp_vdata = &ccpv5a, ++#endif ++#ifdef CONFIG_CRYPTO_DEV_SP_PSP ++ .psp_vdata = &pspv2, ++#endif ++ }, + }; + static const struct pci_device_id sp_pci_table[] = { + { PCI_VDEVICE(AMD, 0x1537), (kernel_ulong_t)&dev_vdata[0] }, + { PCI_VDEVICE(AMD, 0x1456), (kernel_ulong_t)&dev_vdata[1] }, + { PCI_VDEVICE(AMD, 0x1468), (kernel_ulong_t)&dev_vdata[2] }, ++ { PCI_VDEVICE(AMD, 0x1486), (kernel_ulong_t)&dev_vdata[3] }, + /* Last entry must be zero */ + { 0, } + }; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0126-crypto-ccp-Check-for-NULL-PSP-pointer-at-module-unlo.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0126-crypto-ccp-Check-for-NULL-PSP-pointer-at-module-unlo.patch new file mode 100644 index 00000000..07ab1590 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0126-crypto-ccp-Check-for-NULL-PSP-pointer-at-module-unlo.patch @@ -0,0 +1,41 @@ +From cef326f0d3dcb0789fccce84be1777fb102e2694 Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Thu, 26 Jul 2018 09:37:59 -0500 +Subject: [PATCH 126/131] crypto: ccp - Check for NULL PSP pointer at module + unload + +Should the PSP initialization fail, the PSP data structure will be +freed and the value contained in the sp_device struct set to NULL. +At module unload, psp_dev_destroy() does not check if the pointer +value is NULL and will end up dereferencing a NULL pointer. + +Add a pointer check of the psp_data field in the sp_device struct +in psp_dev_destroy() and return immediately if it is NULL. + +Cc: <stable@vger.kernel.org> # 4.16.x- +Fixes: 2a6170dfe755 ("crypto: ccp: Add Platform Security Processor (PSP) device support") +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index 9b59638..218739b 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -858,6 +858,9 @@ void psp_dev_destroy(struct sp_device *sp) + { + struct psp_device *psp = sp->psp_data; + ++ if (!psp) ++ return; ++ + if (psp->sev_misc) + kref_put(&misc_dev->refcount, sev_exit); + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0127-crypto-ccp-add-timeout-support-in-the-SEV-command.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0127-crypto-ccp-add-timeout-support-in-the-SEV-command.patch new file mode 100644 index 00000000..188ad7f8 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0127-crypto-ccp-add-timeout-support-in-the-SEV-command.patch @@ -0,0 +1,121 @@ +From b1aa7fbdaa2a498b8d2e1dab0f95112c83ff18ff Mon Sep 17 00:00:00 2001 +From: Brijesh Singh <brijesh.singh@amd.com> +Date: Wed, 15 Aug 2018 16:11:25 -0500 +Subject: [PATCH 127/131] crypto: ccp - add timeout support in the SEV command + +Currently, the CCP driver assumes that the SEV command issued to the PSP +will always return (i.e. it will never hang). But recently, firmware bugs +have shown that a command can hang. Since of the SEV commands are used +in probe routines, this can cause boot hangs and/or loss of virtualization +capabilities. + +To protect against firmware bugs, add a timeout in the SEV command +execution flow. If a command does not complete within the specified +timeout then return -ETIMEOUT and stop the driver from executing any +further commands since the state of the SEV firmware is unknown. + +Cc: Tom Lendacky <thomas.lendacky@amd.com> +Cc: Gary Hook <Gary.Hook@amd.com> +Cc: Herbert Xu <herbert@gondor.apana.org.au> +Cc: linux-kernel@vger.kernel.org +Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 46 +++++++++++++++++++++++++++++++++++++++----- + 1 file changed, 41 insertions(+), 5 deletions(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index 218739b..72790d8 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -38,6 +38,17 @@ static DEFINE_MUTEX(sev_cmd_mutex); + static struct sev_misc_dev *misc_dev; + static struct psp_device *psp_master; + ++static int psp_cmd_timeout = 100; ++module_param(psp_cmd_timeout, int, 0644); ++MODULE_PARM_DESC(psp_cmd_timeout, " default timeout value, in seconds, for PSP commands"); ++ ++static int psp_probe_timeout = 5; ++module_param(psp_probe_timeout, int, 0644); ++MODULE_PARM_DESC(psp_probe_timeout, " default timeout value, in seconds, during PSP device probe"); ++ ++static bool psp_dead; ++static int psp_timeout; ++ + static struct psp_device *psp_alloc_struct(struct sp_device *sp) + { + struct device *dev = sp->dev; +@@ -82,10 +93,19 @@ static irqreturn_t psp_irq_handler(int irq, void *data) + return IRQ_HANDLED; + } + +-static void sev_wait_cmd_ioc(struct psp_device *psp, unsigned int *reg) ++static int sev_wait_cmd_ioc(struct psp_device *psp, ++ unsigned int *reg, unsigned int timeout) + { +- wait_event(psp->sev_int_queue, psp->sev_int_rcvd); ++ int ret; ++ ++ ret = wait_event_timeout(psp->sev_int_queue, ++ psp->sev_int_rcvd, timeout * HZ); ++ if (!ret) ++ return -ETIMEDOUT; ++ + *reg = ioread32(psp->io_regs + psp->vdata->cmdresp_reg); ++ ++ return 0; + } + + static int sev_cmd_buffer_len(int cmd) +@@ -133,12 +153,15 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) + if (!psp) + return -ENODEV; + ++ if (psp_dead) ++ return -EBUSY; ++ + /* Get the physical address of the command buffer */ + phys_lsb = data ? lower_32_bits(__psp_pa(data)) : 0; + phys_msb = data ? upper_32_bits(__psp_pa(data)) : 0; + +- dev_dbg(psp->dev, "sev command id %#x buffer 0x%08x%08x\n", +- cmd, phys_msb, phys_lsb); ++ dev_dbg(psp->dev, "sev command id %#x buffer 0x%08x%08x timeout %us\n", ++ cmd, phys_msb, phys_lsb, psp_timeout); + + print_hex_dump_debug("(in): ", DUMP_PREFIX_OFFSET, 16, 2, data, + sev_cmd_buffer_len(cmd), false); +@@ -154,7 +177,18 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) + iowrite32(reg, psp->io_regs + psp->vdata->cmdresp_reg); + + /* wait for command completion */ +- sev_wait_cmd_ioc(psp, ®); ++ ret = sev_wait_cmd_ioc(psp, ®, psp_timeout); ++ if (ret) { ++ if (psp_ret) ++ *psp_ret = 0; ++ ++ dev_err(psp->dev, "sev command %#x timed out, disabling PSP \n", cmd); ++ psp_dead = true; ++ ++ return ret; ++ } ++ ++ psp_timeout = psp_cmd_timeout; + + if (psp_ret) + *psp_ret = reg & PSP_CMDRESP_ERR_MASK; +@@ -888,6 +922,8 @@ void psp_pci_init(void) + + psp_master = sp->psp_data; + ++ psp_timeout = psp_probe_timeout; ++ + if (sev_get_api_version()) + goto err; + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0128-crypto-ccp-Fix-static-checker-warning.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0128-crypto-ccp-Fix-static-checker-warning.patch new file mode 100644 index 00000000..2e26578b --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0128-crypto-ccp-Fix-static-checker-warning.patch @@ -0,0 +1,36 @@ +From 50a551e5173aa7299ebb9b538254d512515ad5ce Mon Sep 17 00:00:00 2001 +From: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> +Date: Fri, 14 Sep 2018 17:32:03 -0500 +Subject: [PATCH 128/131] crypto: ccp - Fix static checker warning + +Under certain configuration SEV functions can be defined as no-op. +In such a case error can be uninitialized. + +Initialize the variable to 0. + +Cc: Dan Carpenter <Dan.Carpenter@oracle.com> +Reported-by: Dan Carpenter <Dan.Carpenter@oracle.com> +Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index 72790d8..f541e60 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -423,7 +423,7 @@ EXPORT_SYMBOL_GPL(psp_copy_user_blob); + static int sev_get_api_version(void) + { + struct sev_user_data_status *status; +- int error, ret; ++ int error = 0, ret; + + status = &psp_master->status_cmd_buf; + ret = sev_platform_status(status, &error); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0129-crypto-ccp-Allow-SEV-firmware-to-be-chosen-based-on-.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0129-crypto-ccp-Allow-SEV-firmware-to-be-chosen-based-on-.patch new file mode 100644 index 00000000..a7b50496 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0129-crypto-ccp-Allow-SEV-firmware-to-be-chosen-based-on-.patch @@ -0,0 +1,99 @@ +From 03e12867a4dad629e3b1695a2049ebacd2229134 Mon Sep 17 00:00:00 2001 +From: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> +Date: Fri, 14 Sep 2018 17:32:04 -0500 +Subject: [PATCH 129/131] crypto: ccp - Allow SEV firmware to be chosen based + on Family and Model + +During PSP initialization, there is an attempt to update the SEV firmware +by looking in /lib/firmware/amd/. Currently, sev.fw is the expected name +of the firmware blob. + +This patch will allow for firmware filenames based on the family and +model of the processor. + +Model specific firmware files are given highest priority. Followed by +firmware for a subset of models. Lastly, failing the previous two options, +fallback to looking for sev.fw. + +Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> +Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 44 ++++++++++++++++++++++++++++++++++++++++---- + 1 file changed, 40 insertions(+), 4 deletions(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index f541e60..3571aa2 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -31,8 +31,9 @@ + ((psp_master->api_major) >= _maj && \ + (psp_master->api_minor) >= _min) + +-#define DEVICE_NAME "sev" +-#define SEV_FW_FILE "amd/sev.fw" ++#define DEVICE_NAME "sev" ++#define SEV_FW_FILE "amd/sev.fw" ++#define SEV_FW_NAME_SIZE 64 + + static DEFINE_MUTEX(sev_cmd_mutex); + static struct sev_misc_dev *misc_dev; +@@ -440,6 +441,40 @@ static int sev_get_api_version(void) + return 0; + } + ++int sev_get_firmware(struct device *dev, const struct firmware **firmware) ++{ ++ char fw_name_specific[SEV_FW_NAME_SIZE]; ++ char fw_name_subset[SEV_FW_NAME_SIZE]; ++ ++ snprintf(fw_name_specific, sizeof(fw_name_specific), ++ "amd/amd_sev_fam%.2xh_model%.2xh.sbin", ++ boot_cpu_data.x86, boot_cpu_data.x86_model); ++ ++ snprintf(fw_name_subset, sizeof(fw_name_subset), ++ "amd/amd_sev_fam%.2xh_model%.1xxh.sbin", ++ boot_cpu_data.x86, (boot_cpu_data.x86_model & 0xf0) >> 4); ++ ++ /* Check for SEV FW for a particular model. ++ * Ex. amd_sev_fam17h_model00h.sbin for Family 17h Model 00h ++ * ++ * or ++ * ++ * Check for SEV FW common to a subset of models. ++ * Ex. amd_sev_fam17h_model0xh.sbin for ++ * Family 17h Model 00h -- Family 17h Model 0Fh ++ * ++ * or ++ * ++ * Fall-back to using generic name: sev.fw ++ */ ++ if ((request_firmware(firmware, fw_name_specific, dev) >= 0) || ++ (request_firmware(firmware, fw_name_subset, dev) >= 0) || ++ (request_firmware(firmware, SEV_FW_FILE, dev) >= 0)) ++ return 0; ++ ++ return -ENOENT; ++} ++ + /* Don't fail if SEV FW couldn't be updated. Continue with existing SEV FW */ + static int sev_update_firmware(struct device *dev) + { +@@ -449,9 +484,10 @@ static int sev_update_firmware(struct device *dev) + struct page *p; + u64 data_size; + +- ret = request_firmware(&firmware, SEV_FW_FILE, dev); +- if (ret < 0) ++ if (sev_get_firmware(dev, &firmware) == -ENOENT) { ++ dev_dbg(dev, "No SEV firmware file present\n"); + return -1; ++ } + + /* + * SEV FW expects the physical address given to it to be 32 +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0130-crypto-ccp-Remove-forward-declaration.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0130-crypto-ccp-Remove-forward-declaration.patch new file mode 100644 index 00000000..2d7c97ed --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0130-crypto-ccp-Remove-forward-declaration.patch @@ -0,0 +1,100 @@ +From 363288449f6ef7beea25d397ce91f382875e278d Mon Sep 17 00:00:00 2001 +From: Nathan Chancellor <natechancellor@gmail.com> +Date: Mon, 24 Sep 2018 10:26:15 -0700 +Subject: [PATCH 130/131] crypto: ccp - Remove forward declaration + +Clang emits a warning about this construct: + +drivers/crypto/ccp/sp-platform.c:36:36: warning: tentative array +definition assumed to have one element +static const struct acpi_device_id sp_acpi_match[]; + ^ +1 warning generated. + +Just remove the forward declarations and move the initializations up +so that they can be used in sp_get_of_version and sp_get_acpi_version. + +Reported-by: Nick Desaulniers <ndesaulniers@google.com> +Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> +Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/sp-platform.c | 53 +++++++++++++++++++--------------------- + 1 file changed, 25 insertions(+), 28 deletions(-) + +diff --git a/drivers/crypto/ccp/sp-platform.c b/drivers/crypto/ccp/sp-platform.c +index 71734f2..b75dc7d 100644 +--- a/drivers/crypto/ccp/sp-platform.c ++++ b/drivers/crypto/ccp/sp-platform.c +@@ -33,8 +33,31 @@ struct sp_platform { + unsigned int irq_count; + }; + +-static const struct acpi_device_id sp_acpi_match[]; +-static const struct of_device_id sp_of_match[]; ++static const struct sp_dev_vdata dev_vdata[] = { ++ { ++ .bar = 0, ++#ifdef CONFIG_CRYPTO_DEV_SP_CCP ++ .ccp_vdata = &ccpv3_platform, ++#endif ++ }, ++}; ++ ++#ifdef CONFIG_ACPI ++static const struct acpi_device_id sp_acpi_match[] = { ++ { "AMDI0C00", (kernel_ulong_t)&dev_vdata[0] }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(acpi, sp_acpi_match); ++#endif ++ ++#ifdef CONFIG_OF ++static const struct of_device_id sp_of_match[] = { ++ { .compatible = "amd,ccp-seattle-v1a", ++ .data = (const void *)&dev_vdata[0] }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, sp_of_match); ++#endif + + static struct sp_dev_vdata *sp_get_of_version(struct platform_device *pdev) + { +@@ -201,32 +224,6 @@ static int sp_platform_resume(struct platform_device *pdev) + } + #endif + +-static const struct sp_dev_vdata dev_vdata[] = { +- { +- .bar = 0, +-#ifdef CONFIG_CRYPTO_DEV_SP_CCP +- .ccp_vdata = &ccpv3_platform, +-#endif +- }, +-}; +- +-#ifdef CONFIG_ACPI +-static const struct acpi_device_id sp_acpi_match[] = { +- { "AMDI0C00", (kernel_ulong_t)&dev_vdata[0] }, +- { }, +-}; +-MODULE_DEVICE_TABLE(acpi, sp_acpi_match); +-#endif +- +-#ifdef CONFIG_OF +-static const struct of_device_id sp_of_match[] = { +- { .compatible = "amd,ccp-seattle-v1a", +- .data = (const void *)&dev_vdata[0] }, +- { }, +-}; +-MODULE_DEVICE_TABLE(of, sp_of_match); +-#endif +- + static struct platform_driver sp_platform_driver = { + .driver = { + .name = "ccp", +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0131-crypto-ccp-Make-function-sev_get_firmware-static.patch b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0131-crypto-ccp-Make-function-sev_get_firmware-static.patch new file mode 100644 index 00000000..eac185b9 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/0131-crypto-ccp-Make-function-sev_get_firmware-static.patch @@ -0,0 +1,35 @@ +From a602ed3afc5fc4eb529b9a2e0d55096b72f71f1e Mon Sep 17 00:00:00 2001 +From: Wei Yongjun <weiyongjun1@huawei.com> +Date: Wed, 26 Sep 2018 02:09:23 +0000 +Subject: [PATCH 131/131] crypto: ccp - Make function sev_get_firmware() static + +Fixes the following sparse warning: + +drivers/crypto/ccp/psp-dev.c:444:5: warning: + symbol 'sev_get_firmware' was not declared. Should it be static? + +Fixes: e93720606efd ("crypto: ccp - Allow SEV firmware to be chosen based on Family and Model") +Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/psp-dev.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +index 3571aa2..34b2dc6 100644 +--- a/drivers/crypto/ccp/psp-dev.c ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -441,7 +441,8 @@ static int sev_get_api_version(void) + return 0; + } + +-int sev_get_firmware(struct device *dev, const struct firmware **firmware) ++static int sev_get_firmware(struct device *dev, ++ const struct firmware **firmware) + { + char fw_name_specific[SEV_FW_NAME_SIZE]; + char fw_name_subset[SEV_FW_NAME_SIZE]; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-emmc-patches.scc b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-emmc-patches.scc index e0ec4f7c..3c831cac 100644..100755 --- a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-emmc-patches.scc +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-emmc-patches.scc @@ -1,3 +1,18 @@ patch 0093-check-pci-dev-before-getting-pci-alias.patch patch 0094-mmc-sdhci-acpi-Add-support-for-ACPI-HID-of-AMD-Contr.patch patch 0095-eMMC-patch-4.14.48.patch +patch 0096-Revert-eMMC-patch-4.14.48.patch +patch 0097-mmc-core-Move-calls-to-prepare_hs400_tuning-closer-t.patch +patch 0098-mmc-core-more-fine-grained-hooks-for-HS400-tuning.patch +patch 0099-mmc-sdhci-Export-sdhci-tuning-function-symbol.patch +patch 0100-mmc-sdhci-add-tuning-error-codes.patch +patch 0101-mmc-sdhci-Export-sdhci_request.patch +patch 0102-mmc-sdhci-add-adma_table_cnt-member-to-struct-sdhci_.patch +patch 0103-mmc-sdhci-introduce-adma_write_desc-hook-to-struct-s.patch +patch 0104-mmc-sdhci-Add-version-V4-definition.patch +patch 0105-mmc-sdhci-Add-sd-host-v4-mode.patch +patch 0106-mmc-sdhci-Add-ADMA2-64-bit-addressing-support-for-V4.patch +patch 0107-mmc-sdhci-Add-32-bit-block-count-support-for-v4-mode.patch +patch 0108-mmc-sdhci-Add-Auto-CMD-Auto-Select-support.patch +patch 0109-amd-eMMC-sdhci-HS400-workaround-for-ZP.patch +patch 0110-pinctrl-eMMC-and-PinCtrl-is-sharing-the-interrupt-no.patch diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-xgbe-patches.scc b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-xgbe-patches.scc index c0230523..7b85eda7 100644..100755 --- a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-xgbe-patches.scc +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/amd-xgbe-patches.scc @@ -11,3 +11,11 @@ patch 0010-amd-xgbe-Advertise-FEC-support-with-the-KR-re-driver.patch patch 0011-amd-xgbe-Update-the-BelFuse-quirk-to-support-SGMII.patch patch 0012-amd-xgbe-Improve-SFP-100Mbps-auto-negotiation.patch patch 0013-amd-xgbe-Merged-From-453f85d43fa9ee243f0fc3ac4e1be45.patch +patch 0111-amd-xgbe-use-dma_mapping_error-to-check-map-errors.patch +patch 0112-lib-crc-Move-polynomial-definition-to-separate-heade.patch +patch 0113-lib-crc-Use-consistent-naming-for-CRC-32-polynomials.patch +patch 0114-net-ethernet-Use-existing-define-with-polynomial.patch +patch 0115-net-amd-fix-return-type-of-ndo_start_xmit-function.patch +patch 0116-net-phy-Add-helper-for-advertise-to-lcl-value.patch +patch 0117-drivers-net-remove-net-busy_poll.h-inclusion-when-no.patch +patch 0118-net-ethernet-xgbe-expand-PHY_GBIT_FEAUTRES.patch diff --git a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/snowyowl-user-patches.scc b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/snowyowl-user-patches.scc index f8f52efb..8c882ea1 100755 --- a/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/snowyowl-user-patches.scc +++ b/meta-snowyowl/recipes-kernel/linux/linux-yocto-4.14.71/snowyowl-user-patches.scc @@ -77,3 +77,16 @@ patch 0089-KVM-SVM-install-RSM-intercept.patch patch 0090-KVM-SVM-Fix-SEV-LAUNCH_SECRET-command.patch patch 0091-KVM-x86-define-SVM-VMX-specific-kvm_arch_-alloc-free.patch patch 0092-KVM-SVM-add-struct-kvm_svm-to-hold-SVM-specific-KVM-.patch +patch 0119-crypto-ahash-remove-useless-setting-of-type-flags.patch +patch 0120-crypto-ahash-remove-useless-setting-of-cra_type.patch +patch 0121-crypto-ccp-Fix-command-completion-detection-race.patch +patch 0122-crypto-ccp-Add-psp-enabled-message-when-initializati.patch +patch 0123-crypto-ccp-Remove-unused-defines.patch +patch 0124-crypto-ccp-Support-register-differences-between-PSP-.patch +patch 0125-crypto-ccp-Add-support-for-new-CCP-PSP-device-ID.patch +patch 0126-crypto-ccp-Check-for-NULL-PSP-pointer-at-module-unlo.patch +patch 0127-crypto-ccp-add-timeout-support-in-the-SEV-command.patch +patch 0128-crypto-ccp-Fix-static-checker-warning.patch +patch 0129-crypto-ccp-Allow-SEV-firmware-to-be-chosen-based-on-.patch +patch 0130-crypto-ccp-Remove-forward-declaration.patch +patch 0131-crypto-ccp-Make-function-sev_get_firmware-static.patch |