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authorWade Farnsworth <wfarnsworth@users.noreply.github.com>2019-10-22 08:08:07 -0700
committerGitHub <noreply@github.com>2019-10-22 08:08:07 -0700
commit8e0cf9ee43840bd7ee004412129ba4aa055f5fc8 (patch)
treeb13804093e413307097cd6788ccdc8b062084013 /meta-amdfalconx86
parent9e1e1da00d8ef569d83a7a742a734dbbf5e0bd13 (diff)
parent3f8062a03dc1d1d5fa386e1f1ca59d56b86a85d1 (diff)
downloadmeta-amd-master.tar.gz
meta-amd-master.tar.bz2
meta-amd-master.zip
Merge pull request #661 from ArsalanHAwan/master-merge-warriorHEADmaster
master: merge warrior
Diffstat (limited to 'meta-amdfalconx86')
-rw-r--r--meta-amdfalconx86/.gitignore0
-rw-r--r--meta-amdfalconx86/COPYING.MIT17
-rw-r--r--meta-amdfalconx86/README.md16
-rw-r--r--meta-amdfalconx86/binary/.gitignore0
-rw-r--r--meta-amdfalconx86/conf/layer.conf13
-rw-r--r--meta-amdfalconx86/conf/local.conf.append.amdfalconx8661
-rw-r--r--meta-amdfalconx86/conf/machine/amdfalconx86.conf61
-rw-r--r--meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc16
-rw-r--r--meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c529
-rw-r--r--meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h17
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-rw-r--r--meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c798
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-rw-r--r--meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig3
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-rw-r--r--meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0001-obey-CMAKE_INSTALL_LIBDIR.patch28
-rw-r--r--meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch27
-rw-r--r--meta-amdfalconx86/recipes-devtools/spirv/spirv-tools_git.bb29
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch84
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0003-obey-CMAKE_INSTALL_LIBDIR.patch54
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0004-install-the-vulkan-loader.patch27
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0005-install-demos.patch52
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0006-json-correct-layer-lib-paths.patch114
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0008-demos-make-shader-location-relative.patch261
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch67
-rw-r--r--meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers_1.0.26.bb58
-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb16
-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile14
-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c476
-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h28
-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c554
-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h53
-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-wdt/amd-wdt_1.0.bb14
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-rw-r--r--meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c418
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-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch158
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch40
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/0001-ethernet-integrate-r8168-driver.patch28740
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch55
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/0002-r8168-incorporate-changes-from-the-8.041.01-version.patch243
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch137
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1114-fix-default-UVD-context-size.patch34
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1115-fix-IB-alignment-for-UVD.patch31
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1116-fix-VCE-ib-alignment-value.patch29
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch45
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch106
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1119-move-amdgpu_drm.h-to-driver-include-dir.patch1366
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1120-fix-amdgpu_drm.h-include-problem.patch51
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1121-add-the-interface-of-waiting-multiple-fences-v2.patch281
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1122-Fix-for-vulkan-decode-fail.patch44
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch28
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch77
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch42
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch4049
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch1092
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1128-ASoC-AMD-add-pm-ops.patch106
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch190
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch251
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch383
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1132-drm-amd-Power-management-related-modifications-in-th.patch280
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1133-ASoC-dwc-add-quirk-for-different-register-offset.patch64
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch141
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch34
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch370
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch31
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1138-add-new-semaphore-object-in-kernel-side.patch504
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1139-unify-memory-query-info-interface.patch113
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1140-dma-buf-return-index-of-the-first-signaled-fence.patch188
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1142-add-additional-cached-gca-config-variables.patch51
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1143-implement-raster-configuration-for-gfx-v8.patch262
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1144-cache-rb-config-values.patch46
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1145-use-cached-raster-config-values-in-csb.patch61
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1146-used-cached-gca-values-for-vi_read_register.patch166
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/1147-Removed-extra-parameter.patch26
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-extra-config.cfg433
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-gpu-config.cfg8
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-standard-only.cfg3
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-config.cfg192
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-features.scc0
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc39
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86.cfg61
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/linux-yocto-amdfalconx86_4.4.inc10
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend1
-rw-r--r--meta-amdfalconx86/recipes-kernel/linux/linux-yocto_4.4.bbappend5
108 files changed, 0 insertions, 44947 deletions
diff --git a/meta-amdfalconx86/.gitignore b/meta-amdfalconx86/.gitignore
deleted file mode 100644
index e69de29b..00000000
--- a/meta-amdfalconx86/.gitignore
+++ /dev/null
diff --git a/meta-amdfalconx86/COPYING.MIT b/meta-amdfalconx86/COPYING.MIT
deleted file mode 100644
index 89de3547..00000000
--- a/meta-amdfalconx86/COPYING.MIT
+++ /dev/null
@@ -1,17 +0,0 @@
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
diff --git a/meta-amdfalconx86/README.md b/meta-amdfalconx86/README.md
deleted file mode 100644
index 74d3ff0d..00000000
--- a/meta-amdfalconx86/README.md
+++ /dev/null
@@ -1,16 +0,0 @@
-# meta-amd/meta-amdfalconx86
-
-This is the location for AMD Falcon Family BSP.
-
-Please see the README file contained in the root meta-amd directory
-for general information and usage details.
-
-## Dependencies
-
-This layer depends on:
-
-[bitbake](https://github.com/openembedded/bitbake) layer,
-[oe-core](https://github.com/openembedded/openembedded-core) layer,
-[meta-oe](https://github.com/openembedded/meta-openembedded) layer,
-[meta-python](https://github.com/openembedded/meta-openembedded/meta-python) layer,
-meta-amd/common layer
diff --git a/meta-amdfalconx86/binary/.gitignore b/meta-amdfalconx86/binary/.gitignore
deleted file mode 100644
index e69de29b..00000000
--- a/meta-amdfalconx86/binary/.gitignore
+++ /dev/null
diff --git a/meta-amdfalconx86/conf/layer.conf b/meta-amdfalconx86/conf/layer.conf
deleted file mode 100644
index 13723e5d..00000000
--- a/meta-amdfalconx86/conf/layer.conf
+++ /dev/null
@@ -1,13 +0,0 @@
-# We have a conf and classes directory, add to BBPATH
-BBPATH .= ":${LAYERDIR}"
-
-# We have a recipes-* directories, add to BBFILES
-BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
- ${LAYERDIR}/recipes-*/*/*.bbappend"
-
-BBFILE_COLLECTIONS += "amdfalconx86"
-BBFILE_PATTERN_amdfalconx86 = "^${LAYERDIR}/"
-BBFILE_PRIORITY_amdfalconx86 = "14"
-LAYERSERIES_COMPAT_amdfalconx86 = "sumo"
-
-LAYERDEPENDS_amdfalconx86 = "amd openembedded-layer meta-python"
diff --git a/meta-amdfalconx86/conf/local.conf.append.amdfalconx86 b/meta-amdfalconx86/conf/local.conf.append.amdfalconx86
deleted file mode 100644
index 224e8c60..00000000
--- a/meta-amdfalconx86/conf/local.conf.append.amdfalconx86
+++ /dev/null
@@ -1,61 +0,0 @@
-
-# Set to "yes" to start using the RT Kernel, please
-# run 'bitbake -c clean virtual/kernel' before doing so.
-RT_KERNEL_AMD = "no"
-
-# MEL provides the functionality to build packages with license-restricted
-# algorithms or software. Their configuration variables can be set to
-# "yes" or "no" in the local.conf file to enable or disable the
-# functionality to include them in the build. The option to build these
-# packages is NOT enabled in the default configuration. After enabling the
-# option to build, when you build your target image, the BitBake utility
-# fetches package sources from the canonical upstream location. If you do
-# not have an active network connection, your build with these packages
-# will fail.
-#
-# Building packages with license-restricted algorithms or software may add
-# proprietary IP or functionality with other restrictions to your output.
-# Mentor Graphics has no connection with or responsibility for such
-# license-restricted algorithms or software, and failure to abide by the
-# relevant license terms may have legal consequences.
-#
-# Mentor Graphics does not distribute or endorse sources for license-
-# restricted algorithms or software, and disclaims any liability for their
-# use.
-
-# Using mpv requires the use of license-restricted algorithms
-# or software.
-INCLUDE_MPV ??= "no"
-
-COMMERCIAL_LIC_FLAGS_MPV = "commercial_mpv commercial_ffmpeg commercial_x264"
-LICENSE_FLAGS_WHITELIST_append = "${@' ${COMMERCIAL_LIC_FLAGS_MPV}' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}"
-CORE_IMAGE_EXTRA_INSTALL_append = "${@' mpv' if bb.utils.to_boolean('${INCLUDE_MPV}') else ''}"
-
-# Certain multimedia formats also require license restricted codecs and
-# software components which are not included in MEL build by default.
-INCLUDE_COMMERCIAL_MULTIMEDIA ??= "no"
-
-COMMERCIAL_LIC_FLAGS_MULTIMEDIA = "commercial_gstreamer1.0-plugins-ugly \
- commercial_lame \
- commercial_mpeg2dec \
- commercial_gstreamer1.0-libav \
- commercial_mpg123"
-LICENSE_FLAGS_WHITELIST_append = "${@' ${COMMERCIAL_LIC_FLAGS_MULTIMEDIA}' if bb.utils.to_boolean('${INCLUDE_COMMERCIAL_MULTIMEDIA}') else ''}"
-CORE_IMAGE_EXTRA_INSTALL_append = "${@' packagegroup-multimedia-risky' if bb.utils.to_boolean('${INCLUDE_COMMERCIAL_MULTIMEDIA}') else ''}"
-
-# MEL supports various components that can be enabled by setting the corresponding
-# INCLUDE_<component> to "yes".
-# Following is a list of <components> that can be enabled if you want them to be
-# installed/available on your image.
-# Please change the required INCLUDE_<component> to "yes" before building an image, or
-# generating an ADE that can be used to develop apps for these components (if applicable):
-#
-# - VULKAN - Vulkan driver and Loader Layer.
-# It is required to run Vulkan based applications. Vulkan is a new generation graphics
-# and compute API that provides high-efficiency, cross-platform access to modern GPUs.
-#
-# - CODEXL - CodeXL remote agent and some sample applications to verify the GPU debugging
-# and profiling functionality.
-#
-INCLUDE_VULKAN ??= "no"
-INCLUDE_CODEXL ??= "no"
diff --git a/meta-amdfalconx86/conf/machine/amdfalconx86.conf b/meta-amdfalconx86/conf/machine/amdfalconx86.conf
deleted file mode 100644
index b1e66d54..00000000
--- a/meta-amdfalconx86/conf/machine/amdfalconx86.conf
+++ /dev/null
@@ -1,61 +0,0 @@
-#@TYPE: Machine
-#@NAME: amdfalconx86
-
-#@DESCRIPTION: Machine configuration for amdfalconx86 systems
-
-# BSP and PATCH versions for MEL releases
-BSP_VERSION = "0"
-PATCH_VERSION = "0"
-
-PREFERRED_PROVIDER_virtual/kernel ?= "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "linux-yocto-rt", "linux-yocto", d)}"
-PREFERRED_VERSION_linux-yocto-rt ?= "4.4%"
-
-require conf/machine/include/tune-amdfalconx86.inc
-
-# Add machine specific AMD features and feature pkgs here
-EXTRA_IMAGE_FEATURES += "amd-feature-debug-profile"
-
-VULKAN_PKGS_amdfalconx86 = "glslang spirv-tools vulkan-loader-layers"
-CODEXL_PKGS_amdfalconx86 = "codexl codexl-examples"
-
-include conf/machine/include/amd-common-configurations.inc
-include conf/machine/include/amd-customer-configurations.inc
-
-# Disable GPU if RT kernel is in use
-XSERVER_X86_AMDGPU = "xf86-video-amd \
- ${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'mesa-driver-radeonsi', '', d)} \
- "
-XSERVER_X86_NOGPU = "${@bb.utils.contains('DISTRO_FEATURES', 'opengl', 'mesa-driver-swrast', '', d)}"
-XSERVER_X86_GPU = "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "${XSERVER_X86_NOGPU}", "${XSERVER_X86_AMDGPU}", d)}"
-
-XSERVER ?= "${XSERVER_X86_BASE} \
- ${XSERVER_X86_EXT} \
- ${XSERVER_X86_FBDEV} \
- ${XSERVER_X86_MODESETTING} \
- ${XSERVER_X86_GPU} \
- "
-
-MACHINE_EXTRA_RRECOMMENDS += "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "", "amdgpu-firmware amd-acp-rt286-load", d)}"
-
-KERNEL_MODULE_AUTOLOAD += "${@bb.utils.contains('RT_KERNEL_AMD', 'yes', "", "snd-soc-acp-pcm snd-soc-acp-rt286-mach", d)}"
-
-# Setup a getty on all serial ports
-# ttyS4/ttyS5 are only needed for Bettongs where console doesn't
-# work on ttyS0/ttyS1 so we hope to at least get a getty running
-SERIAL_CONSOLES ?= "115200;ttyS0 115200;ttyUSB0 115200;ttyS4 115200;ttyS5"
-
-# Enable the kernel console on ttyS0/COM0
-KERNEL_SERIAL_CONSOLE ?= "console=ttyS0,115200n8"
-
-# Enable powerplay
-APPEND += "amdgpu.powerplay=1"
-
-# Disable GPU powergating as a workaround
-APPEND += "amdgpu.pg_mask=0"
-
-TOOLCHAIN_HOST_TASK_append_mel = " ${@bb.utils.contains('INCLUDE_VULKAN', 'yes', "nativesdk-glslang", "", d)}"
-
-MACHINEOVERRIDES =. "amd:amdx86:amdgpu:"
-
-# Metadata used by CodeBench for the ADE
-ADE_CB_CPU = "general.cpu.excavator"
diff --git a/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc b/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc
deleted file mode 100644
index dc3911f5..00000000
--- a/meta-amdfalconx86/conf/machine/include/tune-amdfalconx86.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-DEFAULTTUNE ?= "dbfp4"
-
-require conf/machine/include/x86/arch-x86.inc
-require conf/machine/include/x86-base.inc
-
-# AMD DB-FP4 64bit (MerlinFalcon)
-TUNEVALID[dbfp4] = "Enable AMD DB-FP4 (64 bit) specific processor optimizations"
-TUNECONFLICTS[dbfp4] = "m32 mx32"
-TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "dbfp4", " -march=bdver4", "", d)}"
-
-# Extra tune selections
-AVAILTUNES += "dbfp4"
-TUNE_FEATURES_tune-dbfp4 = "m64 dbfp4"
-BASE_LIB_tune-dbfp4 = "lib64"
-TUNE_PKGARCH_tune-dbfp4 = "dbfp4"
-PACKAGE_EXTRA_ARCHS_tune-dbfp4 = "${TUNE_PKGARCH_tune-dbfp4}"
diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c
deleted file mode 100644
index 41a16765..00000000
--- a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.c
+++ /dev/null
@@ -1,529 +0,0 @@
-/*****************************************************************************
-*
-* Copyright (c) 2014, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*
-***************************************************************************/
-#include <unistd.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <fcntl.h>
-#include <signal.h>
-#include <errno.h>
-#include <string.h>
-
-#include <readline/readline.h>
-#include <sys/types.h>
-#include <sys/wait.h>
-#include <sys/ioctl.h>
-
-#include "gpio-test.h"
-
-#define GPIO_APP_VERSION "0.2"
-#define AMD_GPIO_NUM_PINS 184
-static int gpio_in_use[AMD_GPIO_NUM_PINS];
-
-char *show_prompt(void)
-{
- return "$ ";
-}
-
-void sighandler(int sig)
-{
- printf("\n%s", show_prompt());
-}
-
-void show_license(void)
-{
- printf("/*****************************************************************************\n"
- "*\n"
- "* Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
- "* All rights reserved.\n"
- "*\n"
- "* Redistribution and use in source and binary forms, with or without\n"
- "* modification, are permitted provided that the following conditions are met:\n"
- "* * Redistributions of source code must retain the above copyright\n"
- "* notice, this list of conditions and the following disclaimer.\n"
- "* * Redistributions in binary form must reproduce the above copyright\n"
- "* notice, this list of conditions and the following disclaimer in the\n"
- "* documentation and/or other materials provided with the distribution.\n"
- "* * Neither the name of Advanced Micro Devices, Inc. nor the names of\n"
- "* its contributors may be used to endorse or promote products derived\n"
- "* from this software without specific prior written permission.\n"
- "*\n"
- "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n"
- "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n"
- "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n"
- "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n"
- "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n"
- "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n"
- "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n"
- "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n"
- "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n"
- "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
- "*\n"
- "*\n"
- "***************************************************************************/\n");
-}
-
-void print_usage()
-{
- printf("\nCommands Supported ->\n");
- printf(" getgpiomode <gpio> : Gets the mode of GPIO pin\n");
- printf(" setgpiomode <gpio> <in/out/high/low> : Sets the mode of GPIO pin to input or output(high/low)\n");
- printf(" getgpiovalue <gpio> : Gets the value of GPIO pin\n");
- printf(" setgpiovalue <gpio> <high/low> : Sets the value of GPO pin to high or low\n");
- printf(" getnumgpio : Gets the number of GPIO pins supported\n");
- printf(" getgpiobase : Gets the number of first GPIO pin\n");
- printf(" getgpioname : Gets the name of GPIO driver currently in use\n");
- printf(" dmesg : Displays the kernel log messages related to GPIO\n");
- printf(" license : Displays the terms of LICENSE for this application\n");
- printf(" help : Displays help text\n");
- printf(" exit : Exits the application\n\n");
-}
-
-void parse_cmd(const char *cmdline)
-{
- int fd;
-
- if ((cmdline == NULL) || (strncmp(cmdline, "exit", 4) == 0)) {
- int i;
- int ret;
- char gpio[3 + 1];
-
- printf("\nExiting...\n");
-
- /* We need to unexport all the GPIO pins exported earlier */
- for (i = 0; i < AMD_GPIO_NUM_PINS; i++) {
- if (gpio_in_use[i]) {
- int fd;
-
- fd = open("/sys/class/gpio/unexport", O_WRONLY);
- if (fd < 0) {
- printf("\nPlease make sure AMD GPIO driver is loaded\n");
- exit(EXIT_FAILURE);
- }
- memset(gpio, '\0', (3 + 1));
- snprintf(gpio, 4, "%d", i);
-
- ret = write(fd, gpio, strlen(gpio));
- if (ret < 0)
- perror("Error writing to /sys/class/gpio/unexport");
- }
- }
-
- exit(EXIT_SUCCESS);
- } else if (strncmp(cmdline, "help", 4) == 0)
- print_usage();
- else if (strncmp(cmdline, "getnumgpio", 10) == 0) {
- int fd;
- char ngpio[3 + 1];
-
- memset(ngpio, '\0', (3 + 1));
- fd = open("/sys/class/gpio/gpiochip0/ngpio", O_RDONLY);
- if (fd < 0) {
- printf("\nPlease make sure AMD GPIO driver is loaded\n");
- exit(EXIT_FAILURE);
- }
-
- /* Value read from the file is ASCII text */
- if(read(fd, ngpio, 3) < 0)
- perror("Cannot read number of GPIO pins");
-
- printf("\nThe maximum number of GPIO pins supported is %d\n", atoi(ngpio));
- close(fd);
- } else if (strncmp(cmdline, "getgpiobase", 11) == 0) {
- int fd;
- char gpiobase[3 + 1];
-
- memset(gpiobase, '\0', (3 + 1));
- fd = open("/sys/class/gpio/gpiochip0/base", O_RDONLY);
- if (fd < 0) {
- printf("\nPlease make sure AMD GPIO driver is loaded\n");
- exit(EXIT_FAILURE);
- }
-
- if(read(fd, gpiobase, 3) < 0)
- perror("Cannot read GPIO base");
-
- printf("\nGPIO pin numbering starts from %d\n", atoi(gpiobase));
- close(fd);
- } else if (strncmp(cmdline, "getgpioname", 11) == 0) {
- int fd;
- char gpioname[10 + 1]; /* Max 10 characters + NULL character */
-
- /* Zero initialize gpioname array */
- memset(gpioname, '\0', sizeof(gpioname));
-
- fd = open("/sys/class/gpio/gpiochip0/label", O_RDONLY);
- if (fd < 0) {
- printf("\nPlease make sure AMD GPIO driver is loaded\n");
- exit(EXIT_FAILURE);
- }
-
- if(read(fd, gpioname, 10) < 0)
- perror("Cannot read GPIO driver name");
-
- printf("\nGPIO driver loaded is %s\n", gpioname);
- close(fd);
- } else if (strncmp(cmdline, "getgpiovalue", 12) == 0) {
- int fd;
- int gpio_num;
- char gpio[4 + 1];
- char pathname[80];
- int ret = 0;
-
- /* Lets point to the end of first token */
- if (sscanf(cmdline, "getgpiovalue %d", &gpio_num) < 1) {
- printf("Invalid inputs, please try again\n\n");
- return;
- }
-
- fd = open("/sys/class/gpio/export", O_WRONLY);
- if (fd < 0) {
- if (errno == EACCES)
- printf("\nYou do not have correct permission, please run as root\n");
- else
- perror("Error opening /sys/class/gpio/export");
-
- exit(EXIT_FAILURE);
- }
-
- memset(gpio, '\0', (3 + 1));
- if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
- printf("Invalid inputs, please try again\n");
- close(fd);
- return;
- }
-
- ret = write(fd, gpio, strlen(gpio));
- /*
- * There can be two situations ->
- * 1) The GPIO is being exported for the first time.
- * 2) The GPIO is being exported again.
- * In the first case, the write to file descriptor should
- * succeed, and we should still fall into the if clause.
- *
- * In the second case, write will fail and errno will be
- * set to EBUSY, since the GPIO pin is already exported.
- * Rest all is error.
- */
- if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
- /* Close the last file descriptor */
- close(fd);
-
- memset(pathname, '\0', sizeof(pathname));
- sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num);
-
- fd = open(pathname, O_RDONLY);
- if (fd < 0)
- perror("GPIO read error");
- else {
- char value[1 + 1];
-
- memset(value, '\0', 2);
- ret = read(fd, value, 1);
- if (ret < 0)
- perror("Cannot read GPIO pin");
-
- printf("\nGPIO pin %d is at \"%s\"\n", gpio_num,
- (strncmp(value, "1", 1) == 0) ? "high" : "low");
-
- close(fd);
-
- /*
- * Mark the GPIO as already exported, so that we can use
- * unexport them during exit.
- */
- gpio_in_use[gpio_num] = 1;
- }
- } else {
- if (errno == EINVAL)
- printf("\nInvalid GPIO number\n");
- else
- perror("Error exporting GPIO number");
-
- close(fd);
- }
- } else if (strncmp(cmdline, "getgpiomode", 11) == 0) {
- int fd;
- int gpio_num;
- char gpio[4 + 1];
- char pathname[80];
- int ret = 0;
-
- /* Lets point to the end of first token */
- if (sscanf(cmdline, "getgpiomode %d", &gpio_num) < 1) {
- printf("Invalid inputs, please try again\n\n");
- return;
- }
-
- fd = open("/sys/class/gpio/export", O_WRONLY);
- if (fd < 0) {
- if (errno == EACCES)
- printf("\nYou do not have correct permission, please run as root\n");
- else
- perror("Error opening /sys/class/gpio/export");
-
- exit(EXIT_FAILURE);
- }
-
- memset(gpio, '\0', (3 + 1));
- if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
- printf("Invalid inputs, please try again\n");
- close(fd);
- return;
- }
-
- ret = write(fd, gpio, strlen(gpio));
- /*
- * There can be two situations ->
- * 1) The GPIO is being exported for the first time.
- * 2) The GPIO is being exported again.
- * In the first case, the write to file descriptor should
- * succeed, and we should still fall into the if clause.
- *
- * In the second case, write will fail and errno will be
- * set to EBUSY, since the GPIO pin is already exported.
- * Rest all is error.
- */
- if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
- /* Close the last file descriptor */
- close(fd);
-
- memset(pathname, '\0', sizeof(pathname));
- sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num);
-
- fd = open(pathname, O_RDONLY);
- if (fd < 0)
- perror("GPIO read error");
- else {
- char mode[3 + 1];
- int c, i = 0;
-
- memset(mode, '\0', (3 + 1));
- ret = read(fd, mode, 3);
- if (ret < 0)
- perror("Cannot read GPIO pin");
-
- printf("\nGPIO pin %d is in \"%s\" mode\n", gpio_num,
- (strncmp(mode, "in", 2) == 0) ? "input" : "output");
-
- close(fd);
-
- /*
- * Mark the GPIO as already exported, so that we can use
- * unexport them during exit.
- */
- gpio_in_use[gpio_num] = 1;
- }
- } else {
- if (errno == EINVAL)
- printf("\nInvalid GPIO number\n");
- else
- perror("Error exporting GPIO number");
-
- close(fd);
- }
- } else if (strncmp(cmdline, "setgpiomode", 11) == 0) {
- int fd;
- int gpio_num;
- char mode[4 + 1];
- char gpio[3 + 1];
- int ret;
-
- memset(mode, (4 + 1), 0);
- if (sscanf(cmdline, "setgpiomode %d %s", &gpio_num, mode) < 2) {
- printf("Invalid inputs, please try again\n\n");
- return;
- }
-
- memset(gpio, '\0', (3 + 1));
- if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
- printf("Invalid inputs, please try again\n");
- return;
- }
-
- fd = open("/sys/class/gpio/export", O_WRONLY);
- if (fd < 0) {
- if (errno == EACCES)
- printf("\nYou do not have correct permission, please run as root\n");
- else
- perror("Error opening /sys/class/gpio/export");
-
- exit(EXIT_FAILURE);
- }
-
- ret = write(fd, gpio, strlen(gpio));
- if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
- char pathname[80];
-
- /* Close the last file descriptor */
- close(fd);
-
- memset(pathname, '\0', sizeof(pathname));
- sprintf(pathname, "/sys/class/gpio/gpio%d/direction", gpio_num);
-
- fd = open(pathname, O_WRONLY);
- if (fd < 0)
- perror("GPIO read error");
- else {
- /* Sanity check */
- if ((strncmp(mode, "in", 2) == 0) ||
- (strncmp(mode, "out", 3) == 0) ||
- (strncmp(mode, "high", 4) == 0) ||
- (strncmp(mode, "low", 3) == 0)) {
- /* Write mode into /sys/.../direction file */
- ret = write(fd, mode, strlen(mode));
- if (ret < 0)
- perror("Error writing GPIO mode");
- } else
- printf("\nInvalid GPIO mode, please try again\n");
-
- close(fd);
-
- /*
- * Mark the GPIO as exported, so that we can use
- * unexport them during exit.
- */
- gpio_in_use[gpio_num] = 1;
- }
- } else {
- if (errno == EINVAL)
- printf("\nInvalid GPIO number\n");
- else
- perror("Error exporting GPIO number");
-
- close(fd);
- }
- } else if (strncmp(cmdline, "setgpiovalue", 12) == 0) {
- int fd;
- int gpio_num;
- char gpio[3 + 1];
- char value[4 + 1];
- int ret;
-
- memset(value, (4 + 1), 0);
- if (sscanf(cmdline, "setgpiovalue %d %s", &gpio_num, value) < 2) {
- printf("Invalid inputs, please try again\n\n");
- return;
- }
-
- memset(gpio, '\0', (3 + 1));
- if (snprintf(gpio, 3, "%d", gpio_num) < 1) {
- printf("Invalid inputs, please try again\n");
- return;
- }
-
- fd = open("/sys/class/gpio/export", O_WRONLY);
- if (fd < 0) {
- if (errno == EACCES)
- printf("\nYou do not have correct permission, please run as root\n");
- else
- perror("Error opening /sys/class/gpio/export");
-
- exit(EXIT_FAILURE);
- }
-
- ret = write(fd, gpio, strlen(gpio));
- if((ret >= 0) || ((ret < 0) && (errno == EBUSY))) {
- char pathname[80];
-
- /* Close the last file descriptor */
- close(fd);
-
- memset(pathname, '\0', sizeof(pathname));
- sprintf(pathname, "/sys/class/gpio/gpio%d/value", gpio_num);
-
- fd = open(pathname, O_WRONLY);
- if (fd < 0)
- perror("GPIO read error");
- else {
- if (strncmp(value, "high", 4) == 0)
- value[0] = '1';
- else if (strncmp(value, "low", 3) == 0)
- value[0] = '0';
- else {
- printf("\nInvalid input, please try again...\n");
- return;
- }
-
- /* Write mode into /sys/.../direction file */
- ret = write(fd, value, 1);
- if (ret < 0)
- perror("Error writing GPIO mode");
-
- close(fd);
-
- /*
- * Mark the GPIO as exported, so that we can use
- * unexport them during exit.
- */
- gpio_in_use[gpio_num] = 1;
- }
- } else {
- if (errno == EINVAL)
- printf("\nInvalid GPIO number\n");
- else
- perror("Error exporting GPIO number");
-
- close(fd);
- }
- } else if (strncmp(cmdline, "dmesg", 5) == 0) {
- if (system("dmesg | grep GPIO") < 0)
- perror("Error executing \'dmesg | grep GPIO\'");
- } else if (strncmp(cmdline, "license", 7) == 0) {
- show_license();
- } else {
- printf("\nUnknown command\n");
- print_usage();
- }
-}
-
-int main(void)
-{
- char *cmdline= NULL;
-
- printf("GPIO sample application version: %s\n", GPIO_APP_VERSION);
- printf("Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
- "This sample application comes with ABSOLUTELY NO WARRANTY;\n"
- "This is free software, and you are welcome to redistribute it\n"
- "under certain conditions; type `license' for details.\n\n");
-
- /* Handler for Ctrl+C */
- signal(SIGINT, sighandler);
-
- while (1) {
- cmdline = readline(show_prompt());
- parse_cmd(cmdline);
- /* Free the memory malloc'ed by readline */
- free(cmdline);
- cmdline = NULL;
- }
-
- /* Should never reach here */
- return 0;
-}
diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h b/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h
deleted file mode 100644
index af9c3b68..00000000
--- a/meta-amdfalconx86/recipes-applications/gpio-test/files/gpio-test.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _GPIO_TEST_H_
-#define _GPIO_TEST_H_
-
-
-
-/* IOCTL numbers */
-
-typedef struct {
- int offset;
- int value;
-}debug_data;
-
-#define GPIO_TEST_IOC_MAGIC 'k'
-#define GPIO_IOC_SWCTRLIN _IOW(GPIO_TEST_IOC_MAGIC, 1, debug_data)
-#define GPIO_IOC_SWCTRLEN _IOW(GPIO_TEST_IOC_MAGIC, 2, debug_data)
-
-#endif /* _GPIO_TEST_H_ */
diff --git a/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb b/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb
deleted file mode 100644
index 3056c8d2..00000000
--- a/meta-amdfalconx86/recipes-applications/gpio-test/gpio-test_1.0.bb
+++ /dev/null
@@ -1,23 +0,0 @@
-DESCRIPTION = "Sample application for AMD GPIO driver"
-SECTION = "applications"
-LICENSE = "BSD"
-DEPENDS = "readline"
-LIC_FILES_CHKSUM = "file://gpio-test.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2"
-
-SRC_URI = "\
- file://gpio-test.c \
- file://gpio-test.h \
- "
-
-TARGET_CC_ARCH += "${LDFLAGS}"
-
-S = "${WORKDIR}"
-
-do_compile() {
- ${CC} gpio-test.c -o gpio-test -lreadline
-}
-
-do_install() {
- install -d ${D}${bindir}
- install -m 0755 gpio-test ${D}${bindir}
-}
diff --git a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c
deleted file mode 100644
index d1eb4b5c..00000000
--- a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom-test.c
+++ /dev/null
@@ -1,798 +0,0 @@
-/*****************************************************************************
-*
-* Copyright (c) 2014, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*
-***************************************************************************/
-#include <stdint.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <fcntl.h>
-#include <string.h>
-#include <dirent.h>
-#include <signal.h>
-
-#include <sys/types.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-
-#include <readline/readline.h>
-
-#include "spirom.h"
-
-#define SPI_APP_VERSION "1.0"
-
-static int device_opened = 0;
-static char filename[20];
-static int fd = -1;
-
-char *show_prompt(void)
-{
- return "$ ";
-}
-
-void sighandler(int sig)
-{
- /* Do nothing. That is the idea. */
-}
-
-void show_license(void)
-{
- printf("/*****************************************************************************\n"
- "*\n"
- "* Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
- "* All rights reserved.\n"
- "*\n"
- "* Redistribution and use in source and binary forms, with or without\n"
- "* modification, are permitted provided that the following conditions are met:\n"
- "* * Redistributions of source code must retain the above copyright\n"
- "* notice, this list of conditions and the following disclaimer.\n"
- "* * Redistributions in binary form must reproduce the above copyright\n"
- "* notice, this list of conditions and the following disclaimer in the\n"
- "* documentation and/or other materials provided with the distribution.\n"
- "* * Neither the name of Advanced Micro Devices, Inc. nor the names of\n"
- "* its contributors may be used to endorse or promote products derived\n"
- "* from this software without specific prior written permission.\n"
- "*\n"
- "* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n"
- "* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n"
- "* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n"
- "* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY\n"
- "* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n"
- "* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n"
- "* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n"
- "* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n"
- "* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n"
- "* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
- "*\n"
- "*\n"
- "***************************************************************************/\n");
-}
-
-void print_usage(void)
-{
- printf("\nCommands Supported ->\n");
- printf(" enumerate : List all SPI device nodes available\n");
- printf(" setdevice <dev_id> : Set the SPI device number to access\n");
- printf(" wren : Enable Write operation on SPI device\n");
- printf(" wrdi : Disable Write operation on SPI device\n");
- printf(" chiperase : Erase entire ROM chip\n");
- printf(" rdsr : Read status register of ROM device\n");
- printf(" rdid : Read device identification string\n");
- printf(" sectorerase <addr> <num_sectors> : Erase a fixed number of sectors starting at the address\n"
- " specified\n");
- printf(" blockerase <addr> <num_blocks> : Erase a fixed number of blocks starting at the address\n"
- " specified\n");
- printf(" read <addr> <num_bytes> <filename> : Read a fixed number of bytes starting at address\n"
- " specified, and output the contents into file\n");
- printf(" write <addr> <num_bytes> <filename> : Read a fixed number of bytes from file and output\n"
- " the contents to the device starting at the address\n"
- " specified\n");
- printf(" license : Displays the terms of LICENSE for this application\n");
- printf(" help : Displays help text\n");
- printf(" exit : Exits the application\n\n");
-}
-
-void parse_cmd(const char *cmdline)
-{
- struct spi_ioc_transfer tr;
- unsigned int bytes_chunks;
- unsigned int remaining_bytes;
- int addr;
- int ret;
-
- if ((cmdline == NULL) || (strncmp(cmdline, "exit", 4) == 0)) {
- printf("\nExiting...\n");
- close(fd);
- exit(EXIT_SUCCESS);
- } else if (strncmp(cmdline, "enumerate", 9) == 0) {
- DIR *dir;
- struct dirent *dir_entry;
- int device_found = 0;
-
- /* Get the directory handle */
- if ((dir = opendir("/dev")) == NULL) {
- printf("\n\nFailed to open directory /dev. Probably you "
- "do not have right privilege!\n\n");
- exit(EXIT_FAILURE);
- }
-
- /* Iterate over all the directory entries */
- while ((dir_entry = readdir(dir)) != NULL) {
- /*
- * If the file is a character device, and its signature
- * matches spirom, then we print the corresponding file.
- */
- if ((dir_entry->d_type == DT_CHR) &&
- (strncmp(dir_entry->d_name, "spirom", 6) == 0)) {
- printf("/dev/%s\n", dir_entry->d_name);
- device_found = 1;
- }
- }
-
- printf("\n");
-
- /*
- * In case we did not find even a single entry, we print a
- * message and exit.
- */
- if (!device_found) {
- printf("\n\nNo spirom device nodes found, load spirom "
- "kernel module and try again\n\n");
- exit(EXIT_FAILURE);
- }
- } else if (strncmp(cmdline, "setdevice", 9) == 0) {
- char input[2 + 1];
- int file_desc;
-
- cmdline += 10;
- memset(input, 0, 3);
- if (sscanf(cmdline, "%s", input) < 1) {
- printf("\nInvalid inputs, please try again\n\n");
- return;
- }
-
- memset(filename, 0, 20);
- snprintf(filename, 19, "/dev/spirom%s", input);
- file_desc = open(filename, O_RDWR);
- if (file_desc < 0) {
- printf("\nError opening file %s\n\n", filename);
- return;
- }
-
- /* Once we have validated inputs, we store them into the global
- * variables used at other places in the program.
- */
- fd = file_desc;
- device_opened = 1;
- printf("\nSPI device set to /dev/spirom%s\n\n", input);
- } else if (strncmp(cmdline, "wren", 4) == 0) {
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- /* command without data */
- tr.buf[0] = ROM_WREN;
- tr.direction = 0;
- tr.len = 0;
- tr.addr_present = 0;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1)
- printf("\nError executing WREN command\n\n");
- else
- printf("\n...WREN completed successfully\n\n");
- } else if (strncmp(cmdline, "wrdi", 4) == 0) {
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- /* command without data */
- tr.buf[0] = ROM_WRDI;
- tr.direction = 0;
- tr.len = 0;
- tr.addr_present = 0;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1)
- printf("\nError executing WRDI command\n\n");
- else
- printf("\n...WRDI completed successfully\n\n");
- } else if (strncmp(cmdline, "chiperase", 9) == 0) {
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");;
- return;
- } else if ((tr.buf[1] & 0x02) == 0x00) {
- printf("\nCannot execute CHIPERASE command, write is disabled\n\n");
- return;
- }
-
- /* Command without data */
- tr.buf[0] = ROM_CHIP_ERASE;
- tr.direction = 0;
- tr.len = 0;
- tr.addr_present = 0;
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing CHIPERASE command\n\n");
- return;
- }
-
- printf("\n\nCHIPERASE operation in progress, please do not "
- " stop in between.\n\n");
-
- /* Make sure WIP has been reset */
- while (1) {
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- }
-
- if ((tr.buf[1] & 0x01) == 0x00)
- break;
- }
-
- printf("\n\n...CHIPERASE completed successfully\n\n");
- /* Restore signal handler to default */
- } else if (strncmp(cmdline, "rdsr", 4) == 0) {
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- /* Command with response */
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- }
-
- /*
- * The 1-byte response will be stored in tr.buf,
- * so print it out
- */
- printf("\nRDSR command returned: 0x%.2x\n\n", tr.buf[1]);
- } else if (strncmp(cmdline, "rdid", 4) == 0) {
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- /* Command with response */
- tr.buf[0] = ROM_RDID;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 3;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDID command\n\n");
- return;
- }
-
- /*
- * The 3-bytes response will be stored in tr.buf,
- * so print it out
- */
- printf("\nRDID command returned: 0x%.2x%.2x%.2x\n", tr.buf[1],
- tr.buf[2], tr.buf[3]);
- } else if (strncmp(cmdline, "sectorerase", 11) == 0) {
- int nsectors;
- int i;
-
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- cmdline += 12;
- if (sscanf(cmdline, "0x%x 0x%x", &addr, &nsectors) < 2) {
- printf("\nInvalid inputs, please try again\n\n");
- return;
- }
-
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- } else if ((tr.buf[1] & 0x02) == 0x00) {
- printf("\nCannot execute SECTORERASE command, write is disabled\n\n");
- return;
- }
-
- printf("\n\nSECTORERASE operation in progress, please do not "
- " stop in between.\n\n");
-
- for (i = 0; i < nsectors; i++) {
- /* Write Enable before Sector Erase */
- tr.buf[0] = ROM_WREN;
- tr.direction = 0;
- tr.len = 0;
- tr.addr_present = 0;
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing WREN command\n\n");
- return;
- }
-
- /* Command with address but no data */
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_SECTOR_ERASE;
- tr.buf[3] = addr & 0xff;
- tr.buf[2] = (addr >> 8) & 0xff;
- tr.buf[1] = (addr >> 16) & 0xff;
- tr.addr_present = 1;
- tr.direction = 0;
- tr.len = 0;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing SECTORERASE command\n\n");
- return;
- }
-
- /* point to the next 4k sector */
- addr += 4 * 1024;
-
- /*
- * Before the next loop, we need to make sure that WIP
- * bit in the output of RDSR has been reset.
- */
- while (1) {
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- }
-
- if ((tr.buf[1] & 0x01) == 0x00)
- break;
- }
- }
-
- printf("\n\n...SECTORERASE completed successfully\n\n");
- } else if (strncmp(cmdline, "blockerase", 10) == 0) {
- int nblocks;
- int i;
-
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- cmdline += 11;
- if (sscanf(cmdline, "0x%x 0x%x", &addr, &nblocks) < 2) {
- printf("\nInvalid inputs, please try again\n\n");
- return;
- }
-
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- } else if ((tr.buf[1] & 0x02) == 0x00) {
- printf("\nError executing BLOCKERASE command, write is disabled\n\n");
- return;
- }
-
- printf("\n\nBLOCKERASE operation in progress, please do not "
- " stop in between.\n\n");
-
- for (i = 0; i < nblocks; i++) {
- /* Write Enable before Block Erase */
- tr.buf[0] = ROM_WREN;
- tr.direction = 0;
- tr.len = 0;
- tr.addr_present = 0;
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing WREN command\n\n");
- return;
- }
-
- /* Command with address but no data */
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_BLOCK_ERASE;
- tr.buf[3] = addr & 0xff;
- tr.buf[2] = (addr >> 8) & 0xff;
- tr.buf[1] = (addr >> 16) & 0xff;
- tr.addr_present = 1;
- tr.direction = 0;
- tr.len = 0;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing BLOCKERASE command\n\n");
- return;
- }
-
- /* point to the next 64k block */
- addr += 64 * 1024;
-
- /*
- * Before the next loop, we need to make sure that WIP
- * bit in the output of RDSR has been reset.
- */
- while (1) {
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- }
-
- if ((tr.buf[1] & 0x01) == 0x00)
- break;
- }
- }
-
- printf("\n\n...BLOCKERASE completed successfully\n\n");
- } else if (strncmp(cmdline, "read", 4) == 0) {
- int nbytes;
- int outfile_fd;
- int i;
-
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- cmdline += 5;
- memset(filename, 0, 20);
- if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) {
- printf("\nInvalid inputs, please try again\n\n");
- return;
- }
-
- /*
- * Open the output file for writing. Create a new file if not
- * there, and empty the file before writing if file already
- * exists.
- */
- outfile_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, 0644);
- if (outfile_fd < 0) {
- printf("\nError opening file %s for writing\n\n", filename);
- return;
- }
-
- /*
- * We will break down the bytes to be received in chunks of
- * of 64-bytes. Data might not be a even multiple of 64. So
- * in that case, we will have some remaining bytes <4. We
- * handle that separately.
- */
- bytes_chunks = nbytes / 64;
- remaining_bytes = nbytes % 64;
-
- printf("\n\nREAD operation in progress.\n\n");
-
- for (i = 0; i < bytes_chunks; i++) {
- /* Command with address and data */
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_READ;
- tr.direction = RECEIVE;
- /*
- * We will store the address into the buffer in little
- * endian order.
- */
- tr.buf[3] = addr & 0xff;
- tr.buf[2] = (addr >> 8) & 0xff;
- tr.buf[1] = (addr >> 16) & 0xff;
- tr.len = 64;
- tr.addr_present = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing READ command\n\n");
- return;
- }
-
- /* Write the data read to output file */
- if (write(outfile_fd, &tr.buf[4], tr.len) < 0) {
- printf("\nError writing to file %s\n\n", filename);
- return;
- }
- addr += 64;
- }
-
- if (remaining_bytes) {
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_READ;
- tr.direction = RECEIVE;
- tr.buf[3] = addr & 0xff;
- tr.buf[2] = (addr >> 8) & 0xff;
- tr.buf[1] = (addr >> 16) & 0xff;
- tr.len = remaining_bytes;
- tr.addr_present = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing READ command\n\n");
- return;
- }
-
- if (write(outfile_fd, &tr.buf[4], tr.len) < 0) {
- printf("\nError writing to file %s\n\n", filename);
- return;
- }
- }
-
- printf("\n\n...READ completed successfully\n\n");
- close(outfile_fd);
- } else if (strncmp(cmdline, "write", 5) == 0) {
- int nbytes;
- int infile_fd;
- int i;
-
- if (!device_opened) {
- printf("\nSPI device needs to be set before you can "
- "perform this operation\n\n");
- return;
- }
-
- cmdline += 6;
- memset(filename, 0, 20);
- if (sscanf(cmdline, "0x%x 0x%x %s", &addr, &nbytes, filename) < 3) {
- printf("\nInvalid inputs, please try again\n\n");
- return;
- }
-
- /* Open the input file for reading*/
- infile_fd = open(filename, O_RDONLY);
- if (infile_fd < 0) {
- printf("\nError opening file %s for reading\n\n", filename);
- return;
- }
-
- /*
- * We will break down the bytes to be transmitted in chunks of
- * of 64-bytes. Like for read, we might not have data in an
- * even multiple of 64 bytes. So we will handle the remaining
- * bytes in the end.
- */
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- } else if ((tr.buf[1] & 0x02) == 0x00) {
- printf("\nCannot execute WRITE command, write is disabled\n\n");
- return;
- }
-
- bytes_chunks = nbytes / 64;
- remaining_bytes = nbytes % 64;
-
- printf("\n\nWRITE operation in progress, please do not "
- " stop in between.\n\n");
-
- for (i = 0; i < bytes_chunks; i++) {
- tr.buf[0] = ROM_WREN;
- tr.direction = 0;
- tr.len = 0;
- tr.addr_present = 0;
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing WREN command\n\n");
- return;
- }
-
- /* Command with data and address */
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_WRITE;
- tr.direction = TRANSMIT;
- /*
- * We will store the address into the buffer in little
- * endian order.
- */
- tr.buf[3] = addr & 0xff;
- tr.buf[2] = (addr >> 8) & 0xff;
- tr.buf[1] = (addr >> 16) & 0xff;
- tr.len = 64;
- tr.addr_present = 1;
-
- /* Read 64 bytes from input file to buffer */
- if (read(infile_fd, &tr.buf[4], tr.len) < 0) {
- printf("\nError reading from file %s\n\n", filename);
- return;
- }
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing WRITE command\n\n");
- return;
- }
-
- addr += 64;
-
- /*
- * Before the next loop, we need to make sure that WIP
- * bit in the output of RDSR has been reset.
- */
- while (1) {
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- }
-
- if ((tr.buf[1] & 0x01) == 0x00)
- break;
- }
- }
-
- if (remaining_bytes) {
- tr.buf[0] = ROM_WREN;
- tr.direction = 0;
- tr.len = 0;
- tr.addr_present = 0;
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing WREN command\n\n");
- return;
- }
-
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_WRITE;
- tr.direction = TRANSMIT;
- tr.buf[3] = addr & 0xff;
- tr.buf[2] = (addr >> 8) & 0xff;
- tr.buf[1] = (addr >> 16) & 0xff;
- tr.len = remaining_bytes;
- tr.addr_present = 1;
-
- if (read(infile_fd, &tr.buf[4], tr.len) < 0) {
- printf("\nError reading from file %s\n\n", filename);
- return;
- }
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing WRITE command\n\n");
- return;
- }
-
- while (1) {
- memset(&tr, 0, sizeof(struct spi_ioc_transfer));
- tr.buf[0] = ROM_RDSR;
- tr.direction = RECEIVE;
- tr.addr_present = 0;
- tr.len = 1;
-
- ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
- if (ret < 1) {
- printf("\nError executing RDSR command\n\n");
- return;
- }
-
- if ((tr.buf[1] & 0x01) == 0x00)
- break;
- }
- }
-
- printf("\n\n...WRITE completed successfully\n\n");
- close(infile_fd);
- } else if (strncmp(cmdline, "license", 7) == 0) {
- show_license();
- } else if (strncmp(cmdline, "help", 4) == 0) {
- print_usage();
- } else {
- printf("\nUnknown command\n");
- print_usage();
- }
-}
-
-int main(void)
-{
- char *cmdline= NULL;
-
- printf("SPI sample application version: %s\n", SPI_APP_VERSION);
- printf("Copyright (c) 2014, Advanced Micro Devices, Inc.\n"
- "This sample application comes with ABSOLUTELY NO WARRANTY;\n"
- "This is free software, and you are welcome to redistribute it\n"
- "under certain conditions; type `license` for details.\n\n");
-
- /* Set the signal handler */
- signal(SIGINT, sighandler);
-
- while (1) {
- cmdline = readline(show_prompt());
- parse_cmd(cmdline);
- /* Free the memory malloc'ed by readline */
- free(cmdline);
- }
-
- /* Restore the default signal handler */
- signal(SIGINT, SIG_DFL);
-
- /* Should never reach here */
- return 0;
-}
diff --git a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h b/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h
deleted file mode 100644
index f599925f..00000000
--- a/meta-amdfalconx86/recipes-applications/spi-test/files/spirom.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef SPIROM_H
-#define SPIROM_H
-
-#include <linux/types.h>
-
-/*---------------------------------------------------------------------------*/
-
-/* IOCTL commands */
-
-#define SPI_IOC_MAGIC 'k'
-
-#define TRANSMIT 1
-#define RECEIVE 2
-
-/*
- * struct spi_ioc_transfer - interface structure between application and ioctl
- *
- * @buf: Buffer to hold 1-byte command, 3-bytes address, and 4-byte data for
- * transmit or receive. The internal FIFO of our controller can hold a
- * maximum of 8 bytes, including the address. But here we assume the
- * maximum data excluding address to be 4-bytes long.
- *
- * @direction: Direction of data transfer, either TRANSMIT or RECEIVE.
- *
- * @len: Length of data excluding command and address.
- *
- * @addr_present: Flag to indicate whether 'buf' above contains an address.
- */
-struct spi_ioc_transfer {
- __u8 buf[64 + 1 + 3];
- __u8 direction;
- __u8 len;
- __u8 addr_present;
-};
-
-/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
-#define SPI_MSGSIZE(N) \
- ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
- ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
-#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
-
-/* SPI ROM command codes */
-#define ROM_WREN 0x06
-#define ROM_WRDI 0x04
-#define ROM_RDSR 0x05
-#define ROM_RDID 0x9F
-#define ROM_CHIP_ERASE 0x60
-#define ROM_SECTOR_ERASE 0x20
-#define ROM_BLOCK_ERASE 0xD8
-#define ROM_READ 0x03
-#define ROM_WRITE 0x02
-
-#endif /* SPIROM_H */
diff --git a/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb b/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb
deleted file mode 100644
index 764f112a..00000000
--- a/meta-amdfalconx86/recipes-applications/spi-test/spi-test_1.0.bb
+++ /dev/null
@@ -1,22 +0,0 @@
-DESCRIPTION = "Sample application for AMD SPI driver"
-SECTION = "applications"
-LICENSE = "BSD"
-DEPENDS = "readline"
-LIC_FILES_CHKSUM = "file://spirom-test.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2"
-
-SRC_URI = "file://spirom-test.c \
- file://spirom.h \
- "
-
-S = "${WORKDIR}"
-
-TARGET_CC_ARCH += "${LDFLAGS}"
-
-do_compile() {
- ${CC} spirom-test.c -o spirom-test -lreadline
-}
-
-do_install() {
- install -d ${D}${bindir}
- install -m 0755 spirom-test ${D}${bindir}
-}
diff --git a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig
deleted file mode 100644
index 28ca080e..00000000
--- a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor/amdfalconx86/machconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-# Assume a USB mouse and keyboard are connected
-HAVE_TOUCHSCREEN=n
-HAVE_KEYBOARD=y
diff --git a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend b/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend
deleted file mode 100644
index 6d4804d1..00000000
--- a/meta-amdfalconx86/recipes-bsp/formfactor/formfactor_0.0.bbappend
+++ /dev/null
@@ -1,2 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
-
diff --git a/meta-amdfalconx86/recipes-devtools/glslang/glslang/0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch b/meta-amdfalconx86/recipes-devtools/glslang/glslang/0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch
deleted file mode 100644
index cef3e8e6..00000000
--- a/meta-amdfalconx86/recipes-devtools/glslang/glslang/0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 372422ed8ce32e1085cd524156c687df65095237 Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Tue, 25 Oct 2016 14:44:20 +0500
-Subject: [PATCH] CMakeLists.txt: obey CMAKE_INSTALL_LIBDIR
-
-Not using the exact path that is set through cmake
-will end up in a mixed configuration setup where
-files are installed on hard-coded locations.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- OGLCompilersDLL/CMakeLists.txt | 2 +-
- SPIRV/CMakeLists.txt | 2 +-
- glslang/CMakeLists.txt | 2 +-
- glslang/OSDependent/Unix/CMakeLists.txt | 2 +-
- glslang/OSDependent/Windows/CMakeLists.txt | 2 +-
- hlsl/CMakeLists.txt | 2 +-
- 6 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/OGLCompilersDLL/CMakeLists.txt b/OGLCompilersDLL/CMakeLists.txt
-index 4954db9..6b518d9 100644
---- a/OGLCompilersDLL/CMakeLists.txt
-+++ b/OGLCompilersDLL/CMakeLists.txt
-@@ -8,4 +8,4 @@ if(WIN32)
- endif(WIN32)
-
- install(TARGETS OGLCompiler
-- ARCHIVE DESTINATION lib)
-+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
-diff --git a/SPIRV/CMakeLists.txt b/SPIRV/CMakeLists.txt
-index 48a6c46..c657d56 100755
---- a/SPIRV/CMakeLists.txt
-+++ b/SPIRV/CMakeLists.txt
-@@ -41,4 +41,4 @@ if(WIN32)
- endif(WIN32)
-
- install(TARGETS SPIRV SPVRemapper
-- ARCHIVE DESTINATION lib)
-+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
-diff --git a/glslang/CMakeLists.txt b/glslang/CMakeLists.txt
-index ff91135..efb7f15 100644
---- a/glslang/CMakeLists.txt
-+++ b/glslang/CMakeLists.txt
-@@ -89,4 +89,4 @@ if(WIN32)
- endif(WIN32)
-
- install(TARGETS glslang
-- ARCHIVE DESTINATION lib)
-+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
-diff --git a/glslang/OSDependent/Unix/CMakeLists.txt b/glslang/OSDependent/Unix/CMakeLists.txt
-index 174cc91..d98057b 100644
---- a/glslang/OSDependent/Unix/CMakeLists.txt
-+++ b/glslang/OSDependent/Unix/CMakeLists.txt
-@@ -2,4 +2,4 @@ add_library(OSDependent STATIC ossource.cpp ../osinclude.h)
- set_property(TARGET OSDependent PROPERTY FOLDER glslang)
-
- install(TARGETS OSDependent
-- ARCHIVE DESTINATION lib)
-+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
-diff --git a/glslang/OSDependent/Windows/CMakeLists.txt b/glslang/OSDependent/Windows/CMakeLists.txt
-index 399760c..744bcbb 100644
---- a/glslang/OSDependent/Windows/CMakeLists.txt
-+++ b/glslang/OSDependent/Windows/CMakeLists.txt
-@@ -14,4 +14,4 @@ if(WIN32)
- endif(WIN32)
-
- install(TARGETS OSDependent
-- ARCHIVE DESTINATION lib)
-+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
-diff --git a/hlsl/CMakeLists.txt b/hlsl/CMakeLists.txt
-index c7537e2..5111661 100755
---- a/hlsl/CMakeLists.txt
-+++ b/hlsl/CMakeLists.txt
-@@ -23,4 +23,4 @@ if(WIN32)
- endif(WIN32)
-
- install(TARGETS HLSL
-- ARCHIVE DESTINATION lib)
-+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-devtools/glslang/glslang_git.bb b/meta-amdfalconx86/recipes-devtools/glslang/glslang_git.bb
deleted file mode 100644
index 15852cac..00000000
--- a/meta-amdfalconx86/recipes-devtools/glslang/glslang_git.bb
+++ /dev/null
@@ -1,39 +0,0 @@
-SUMMARY = "An OpenGL and OpenGL ES shader front end and validator."
-DESCRIPTION = "Glslang is the official reference compiler front end \
- for the OpenGL ES and OpenGL shading languages. It \
- implements a strict interpretation of the specifications \
- for these languages. It is open and free for anyone to use, \
- either from a command line or programmatically."
-SECTION = "graphics"
-HOMEPAGE = "https://www.khronos.org/opengles/sdk/tools/Reference-Compiler"
-
-inherit cmake
-
-LICENSE = "BSD"
-LIC_FILES_CHKSUM = "file://glslang/Include/Types.h;beginline=1;endline=36;md5=6639a5f9543e833d71e2f4e4ff52f34b"
-
-S = "${WORKDIR}/git"
-
-SRCREV = "81cd764b5ffc475bc73f1fb35f75fd1171bb2343"
-SRC_URI = "git://github.com/KhronosGroup/glslang \
- file://0001-CMakeLists.txt-obey-CMAKE_INSTALL_LIBDIR.patch"
-
-FILES_${PN} += "${libdir}/*"
-
-BBCLASSEXTEND = "native nativesdk"
-
-do_install_append() {
- # Some of the vulkan samples/test require these headers
- install -d ${D}${includedir}/SPIRV
- cp -f ${S}/SPIRV/GlslangToSpv.h ${D}${includedir}/SPIRV
- cp -f ${S}/SPIRV/Logger.h ${D}${includedir}/SPIRV
- cp -f ${S}/SPIRV/SPVRemapper.h ${D}${includedir}/SPIRV
- cp -f ${S}/SPIRV/spvIR.h ${D}${includedir}/SPIRV
-
- install -d ${D}${includedir}/glslang/Include
- cp -f ${S}/glslang/Include/*.h ${D}${includedir}/glslang/Include
- install -d ${D}${includedir}/glslang/Public
- cp -f ${S}/glslang/Public/*.h ${D}${includedir}/glslang/Public
- install -d ${D}${includedir}/glslang/MachineIndependent
- cp -f ${S}/glslang/MachineIndependent/Versions.h ${D}${includedir}/glslang/MachineIndependent
-}
diff --git a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0001-obey-CMAKE_INSTALL_LIBDIR.patch b/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0001-obey-CMAKE_INSTALL_LIBDIR.patch
deleted file mode 100644
index d1f0f3b1..00000000
--- a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0001-obey-CMAKE_INSTALL_LIBDIR.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From a6b250054e5bc27b87414c860c9b808a4beef552 Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Tue, 16 Aug 2016 16:07:45 +0500
-Subject: [PATCH] obey CMAKE_INSTALL_LIBDIR
-
-If the path to CMAKE_INSTALL_LIBDIR is not followed appropriately
-the installation will not work correctly on a multilib platofrm.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- source/CMakeLists.txt | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/source/CMakeLists.txt b/source/CMakeLists.txt
-index de227d6..73672a1 100644
---- a/source/CMakeLists.txt
-+++ b/source/CMakeLists.txt
-@@ -198,5 +198,5 @@ target_include_directories(${SPIRV_TOOLS}
-
- install(TARGETS ${SPIRV_TOOLS}
- RUNTIME DESTINATION bin
-- LIBRARY DESTINATION lib
-- ARCHIVE DESTINATION lib)
-+ LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
-+ ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch b/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch
deleted file mode 100644
index 2d51f2fd..00000000
--- a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools/0002-spirv-lesspipe.sh-allow-using-generic-shells.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 93a770330aa21c91a9b7fce798b73d31cad8f16a Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Tue, 25 Oct 2016 16:12:08 +0500
-Subject: [PATCH] spirv-lesspipe.sh: allow using generic shells
-
-The script is harmless for any type of shell and
-shouldn't be tied with bash to allow catering
-more possibilities.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- tools/lesspipe/spirv-lesspipe.sh | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/tools/lesspipe/spirv-lesspipe.sh b/tools/lesspipe/spirv-lesspipe.sh
-index 05831d1..4e98fee 100644
---- a/tools/lesspipe/spirv-lesspipe.sh
-+++ b/tools/lesspipe/spirv-lesspipe.sh
-@@ -1,4 +1,4 @@
--#!/bin/bash
-+#!/bin/sh
-
- # Copyright (c) 2016 The Khronos Group Inc.
- #
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools_git.bb b/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools_git.bb
deleted file mode 100644
index f9563366..00000000
--- a/meta-amdfalconx86/recipes-devtools/spirv/spirv-tools_git.bb
+++ /dev/null
@@ -1,29 +0,0 @@
-SUMMARY = "SPIR-V Tools"
-DESCRIPTION = "SPIR-V is a binary intermediate language for representing \
- graphical-shader stages and compute kernels for multiple \
- Khronos APIs, such as OpenCL, OpenGL, and Vulkan."
-SECTION = "graphics"
-HOMEPAGE = "https://www.khronos.org/registry/spir-v"
-
-inherit cmake python3native
-
-LICENSE = "MIT"
-LIC_FILES_CHKSUM = "file://LICENSE;md5=ce523927d7bcd789d6c3af579d03ad73"
-
-S = "${WORKDIR}/git"
-SPIRV_HEADERS_LOCATION = "${S}/external/spirv-headers"
-HEADERS_VERSION = "1.1"
-
-SRCREV_spirv-tools = "923a4596b44831a07060df45caacb522613730c9"
-SRCREV_spirv-headers = "33d41376d378761ed3a4c791fc4b647761897f26"
-SRC_URI = "git://github.com/KhronosGroup/SPIRV-Tools;protocol=http;name=spirv-tools \
- git://github.com/KhronosGroup/SPIRV-Headers;name=spirv-headers;destsuffix=${SPIRV_HEADERS_LOCATION} \
- file://0001-obey-CMAKE_INSTALL_LIBDIR.patch \
- file://0002-spirv-lesspipe.sh-allow-using-generic-shells.patch"
-
-do_install_append() {
- if test -d ${SPIRV_HEADERS_LOCATION}/include/spirv/${HEADERS_VERSION}; then
- install -d ${D}/${includedir}/SPIRV
- install -m 0644 ${SPIRV_HEADERS_LOCATION}/include/spirv/${HEADERS_VERSION}/* ${D}/${includedir}/SPIRV
- fi
-}
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch
deleted file mode 100644
index 05fbd360..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 32f2777c9cc8f7dfc8b1e0c6894191167e76d5c4 Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Tue, 16 Aug 2016 19:35:35 +0500
-Subject: [PATCH] CMakeLists: add include path so Xlib.h is found as needed
-
-All the targets including vk_platform.h or directly including
-X11/Xlib.h require to know the directory for the installed
-header. Add the directory to these so the requirements are
-filled in properly.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- CMakeLists.txt | 2 ++
- demos/CMakeLists.txt | 2 +-
- layers/CMakeLists.txt | 1 +
- libs/vkjson/CMakeLists.txt | 1 +
- loader/CMakeLists.txt | 1 +
- 5 files changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/CMakeLists.txt b/CMakeLists.txt
-index 263002e..20e9fd6 100644
---- a/CMakeLists.txt
-+++ b/CMakeLists.txt
-@@ -190,6 +190,8 @@ find_path(SPIRV_TOOLS_INCLUDE_DIR spirv-tools/libspirv.h HINTS "${EXTERNAL_SOURC
- "${EXTERNAL_SOURCE_ROOT}/source/spirv-tools/external/include"
- DOC "Path to spirv-tools/libspirv.h")
-
-+find_path(X11_XLIB_INCLUDE_DIR X11/Xlib.h DOC "Path to X11/Xlib.h")
-+
- find_library(GLSLANG_LIB NAMES glslang
- HINTS ${GLSLANG_SEARCH_PATH} )
-
-diff --git a/demos/CMakeLists.txt b/demos/CMakeLists.txt
-index 26e86fb..9fdabf8 100644
---- a/demos/CMakeLists.txt
-+++ b/demos/CMakeLists.txt
-@@ -92,7 +92,7 @@ if(NOT WIN32)
- link_libraries(${XCB_LIBRARIES})
- endif()
- if(BUILD_WSI_XLIB_SUPPORT)
-- include_directories(${X11_INCLUDE_DIRS})
-+ include_directories(${X11_INCLUDE_DIRS} ${X11_XLIB_INCLUDE_DIR})
- link_libraries(${X11_LIBRARIES})
- endif()
- if(BUILD_WSI_WAYLAND_SUPPORT)
-diff --git a/layers/CMakeLists.txt b/layers/CMakeLists.txt
-index 076b847..b384803 100644
---- a/layers/CMakeLists.txt
-+++ b/layers/CMakeLists.txt
-@@ -90,6 +90,7 @@ include_directories(
- ${CMAKE_CURRENT_SOURCE_DIR}/../loader
- ${CMAKE_CURRENT_SOURCE_DIR}/../include/vulkan
- ${CMAKE_CURRENT_BINARY_DIR}
-+ ${X11_XLIB_INCLUDE_DIR}
- )
-
- if (WIN32)
-diff --git a/libs/vkjson/CMakeLists.txt b/libs/vkjson/CMakeLists.txt
-index fc69bb6..fe5e814 100644
---- a/libs/vkjson/CMakeLists.txt
-+++ b/libs/vkjson/CMakeLists.txt
-@@ -26,6 +26,7 @@ include_directories(
- ${CMAKE_CURRENT_SOURCE_DIR}
- ${CMAKE_CURRENT_SOURCE_DIR}/../../loader
- ${CMAKE_CURRENT_SOURCE_DIR}/../../include/vulkan
-+ ${X11_XLIB_INCLUDE_DIR}
- )
-
- add_library(vkjson STATIC vkjson.cc vkjson_instance.cc ../../loader/cJSON.c)
-diff --git a/loader/CMakeLists.txt b/loader/CMakeLists.txt
-index a4d2b21..227162c 100644
---- a/loader/CMakeLists.txt
-+++ b/loader/CMakeLists.txt
-@@ -1,6 +1,7 @@
- include_directories(
- ${CMAKE_CURRENT_SOURCE_DIR}
- ${CMAKE_CURRENT_BINARY_DIR}
-+ ${X11_XLIB_INCLUDE_DIR}
- )
-
- if (WIN32)
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0003-obey-CMAKE_INSTALL_LIBDIR.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0003-obey-CMAKE_INSTALL_LIBDIR.patch
deleted file mode 100644
index 3ede3bac..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0003-obey-CMAKE_INSTALL_LIBDIR.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 52231c657cb1241cee099ca2626c1eebcc944e4e Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Wed, 17 Aug 2016 13:25:36 +0500
-Subject: [PATCH 1/2] obey CMAKE_INSTALL_LIBDIR
-
-The CMAKE_INSTALL_* directories provide a mechanism to
-relocate installations so rather than doing this through
-hardcoded variable they should be used whereever possible.
-This fixes installation to required directory.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- layers/CMakeLists.txt | 4 ++--
- tests/layers/CMakeLists.txt | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/layers/CMakeLists.txt b/layers/CMakeLists.txt
-index 076b847..cfab1bf 100644
---- a/layers/CMakeLists.txt
-+++ b/layers/CMakeLists.txt
-@@ -81,7 +81,7 @@ else()
- target_link_Libraries(VkLayer_${target} VkLayer_utils)
- add_dependencies(VkLayer_${target} generate_vk_layer_helpers)
- set_target_properties(VkLayer_${target} PROPERTIES LINK_FLAGS "-Wl,-Bsymbolic")
-- install(TARGETS VkLayer_${target} DESTINATION ${PROJECT_BINARY_DIR}/install_staging)
-+ install(TARGETS VkLayer_${target} DESTINATION ${CMAKE_INSTALL_LIBDIR})
- endmacro()
- endif()
-
-@@ -148,7 +148,7 @@ if (WIN32)
- add_library(VkLayer_utils STATIC vk_layer_config.cpp vk_layer_extension_utils.cpp vk_layer_utils.cpp)
- else()
- add_library(VkLayer_utils SHARED vk_layer_config.cpp vk_layer_extension_utils.cpp vk_layer_utils.cpp)
-- install(TARGETS VkLayer_utils DESTINATION ${PROJECT_BINARY_DIR}/install_staging)
-+ install(TARGETS VkLayer_utils DESTINATION ${CMAKE_INSTALL_LIBDIR})
- endif()
-
- add_vk_layer(core_validation core_validation.cpp vk_layer_table.cpp vk_safe_struct.cpp descriptor_sets.cpp)
-diff --git a/tests/layers/CMakeLists.txt b/tests/layers/CMakeLists.txt
-index 87d7793..f62e054 100644
---- a/tests/layers/CMakeLists.txt
-+++ b/tests/layers/CMakeLists.txt
-@@ -49,7 +49,7 @@ else()
- add_library(VkLayer_${target} SHARED ${ARGN})
- add_dependencies(VkLayer_${target} generate_vk_layer_helpers)
- set_target_properties(VkLayer_${target} PROPERTIES LINK_FLAGS "-Wl,-Bsymbolic")
-- install(TARGETS VkLayer_${target} DESTINATION ${PROJECT_BINARY_DIR}/install_staging)
-+ install(TARGETS VkLayer_${target} DESTINATION ${CMAKE_INSTALL_LIBDIR})
- endmacro()
- endif()
-
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0004-install-the-vulkan-loader.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0004-install-the-vulkan-loader.patch
deleted file mode 100644
index 68026245..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0004-install-the-vulkan-loader.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From d30812f7afc355269df0edd5d4f030d470192cad Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Wed, 17 Aug 2016 13:28:32 +0500
-Subject: [PATCH 2/2] install the vulkan loader
-
-The vulkan loader is an essential component so it should
-be installed to the directory that is intended to be
-pushed to the target.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- loader/CMakeLists.txt | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/loader/CMakeLists.txt b/loader/CMakeLists.txt
-index a4d2b21..2790faa 100644
---- a/loader/CMakeLists.txt
-+++ b/loader/CMakeLists.txt
-@@ -84,4 +84,5 @@ else()
- add_library(vulkan SHARED ${LOADER_SRCS})
- set_target_properties(vulkan PROPERTIES SOVERSION "1" VERSION "1.0.26")
- target_link_libraries(vulkan -ldl -lpthread -lm)
-+ install(TARGETS vulkan DESTINATION ${CMAKE_INSTALL_LIBDIR})
- endif()
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0005-install-demos.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0005-install-demos.patch
deleted file mode 100644
index 08f0f8f0..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0005-install-demos.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 15f3a15ce6d65714f7901eab118a13d9d70a9a3b Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Tue, 30 Aug 2016 15:17:55 +0500
-Subject: [PATCH] install demos
-
-Install demos to the target.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- demos/CMakeLists.txt | 2 ++
- demos/smoke/CMakeLists.txt | 2 ++
- 2 files changed, 4 insertions(+)
-
-diff --git a/demos/CMakeLists.txt b/demos/CMakeLists.txt
-index 9fdabf8..42e5499 100644
---- a/demos/CMakeLists.txt
-+++ b/demos/CMakeLists.txt
-@@ -136,5 +136,8 @@ else()
- target_link_libraries(cube ${LIBRARIES} )
- endif()
-
-+install(TARGETS cube DESTINATION ${CMAKE_INSTALL_BINDIR})
-+install(TARGETS tri DESTINATION ${CMAKE_INSTALL_BINDIR})
-+install(TARGETS vulkaninfo DESTINATION ${CMAKE_INSTALL_BINDIR})
- add_subdirectory(smoke)
-
-diff --git a/demos/smoke/CMakeLists.txt b/demos/smoke/CMakeLists.txt
-index 4dc90cd..415ac2f 100644
---- a/demos/smoke/CMakeLists.txt
-+++ b/demos/smoke/CMakeLists.txt
-@@ -85,3 +85,5 @@ add_executable(smoketest ${sources})
- target_compile_definitions(smoketest ${definitions})
- target_include_directories(smoketest ${includes})
- target_link_libraries(smoketest ${libraries})
-+
-+install(TARGETS smoketest DESTINATION ${CMAKE_INSTALL_BINDIR})
-diff --git a/libs/vkjson/CMakeLists.txt b/libs/vkjson/CMakeLists.txt
-index 4c0aef8..9b03d3d 100644
---- a/libs/vkjson/CMakeLists.txt
-+++ b/libs/vkjson/CMakeLists.txt
-@@ -32,6 +32,8 @@ if(UNIX)
- set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-sign-compare")
- add_executable(vkjson_unittest vkjson_unittest.cc)
- add_executable(vkjson_info vkjson_info.cc)
-+ install(TARGETS vkjson_unittest DESTINATION ${CMAKE_INSTALL_BINDIR})
-+ install(TARGETS vkjson_info DESTINATION ${CMAKE_INSTALL_BINDIR})
- else()
- set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D_CRT_SECURE_NO_WARNINGS")
- add_executable(vkjson_unittest vkjson_unittest.cc)
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0006-json-correct-layer-lib-paths.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0006-json-correct-layer-lib-paths.patch
deleted file mode 100644
index 54d092ba..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0006-json-correct-layer-lib-paths.patch
+++ /dev/null
@@ -1,114 +0,0 @@
-From e66538f44c606d9f6c2ada9d78b310343e4386da Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Wed, 31 Aug 2016 15:13:28 +0500
-Subject: [PATCH] json: correct layer lib paths
-
-Rather than using a hardcoded ./ path for the libraries
-we should use loose paths so the system could search
-on its own when the library is required.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- layers/linux/VkLayer_core_validation.json | 2 +-
- layers/linux/VkLayer_image.json | 2 +-
- layers/linux/VkLayer_object_tracker.json | 2 +-
- layers/linux/VkLayer_parameter_validation.json | 2 +-
- layers/linux/VkLayer_swapchain.json | 2 +-
- layers/linux/VkLayer_threading.json | 2 +-
- layers/linux/VkLayer_unique_objects.json | 2 +-
- 7 files changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/layers/linux/VkLayer_core_validation.json b/layers/linux/VkLayer_core_validation.json
-index 3f2162d..c0ef9b7 100644
---- a/layers/linux/VkLayer_core_validation.json
-+++ b/layers/linux/VkLayer_core_validation.json
-@@ -3,7 +3,7 @@
- "layer" : {
- "name": "VK_LAYER_LUNARG_core_validation",
- "type": "GLOBAL",
-- "library_path": "./libVkLayer_core_validation.so",
-+ "library_path": "libVkLayer_core_validation.so",
- "api_version": "1.0.26",
- "implementation_version": "1",
- "description": "LunarG Validation Layer",
-diff --git a/layers/linux/VkLayer_image.json b/layers/linux/VkLayer_image.json
-index 97a250e..6fa3bbd 100644
---- a/layers/linux/VkLayer_image.json
-+++ b/layers/linux/VkLayer_image.json
-@@ -3,7 +3,7 @@
- "layer" : {
- "name": "VK_LAYER_LUNARG_image",
- "type": "GLOBAL",
-- "library_path": "./libVkLayer_image.so",
-+ "library_path": "libVkLayer_image.so",
- "api_version": "1.0.26",
- "implementation_version": "1",
- "description": "LunarG Validation Layer",
-diff --git a/layers/linux/VkLayer_object_tracker.json b/layers/linux/VkLayer_object_tracker.json
-index 1c5d79b..49e5a29 100644
---- a/layers/linux/VkLayer_object_tracker.json
-+++ b/layers/linux/VkLayer_object_tracker.json
-@@ -3,7 +3,7 @@
- "layer" : {
- "name": "VK_LAYER_LUNARG_object_tracker",
- "type": "GLOBAL",
-- "library_path": "./libVkLayer_object_tracker.so",
-+ "library_path": "libVkLayer_object_tracker.so",
- "api_version": "1.0.26",
- "implementation_version": "1",
- "description": "LunarG Validation Layer",
-diff --git a/layers/linux/VkLayer_parameter_validation.json b/layers/linux/VkLayer_parameter_validation.json
-index 899ea88..6df74f8 100644
---- a/layers/linux/VkLayer_parameter_validation.json
-+++ b/layers/linux/VkLayer_parameter_validation.json
-@@ -3,7 +3,7 @@
- "layer" : {
- "name": "VK_LAYER_LUNARG_parameter_validation",
- "type": "GLOBAL",
-- "library_path": "./libVkLayer_parameter_validation.so",
-+ "library_path": "libVkLayer_parameter_validation.so",
- "api_version": "1.0.26",
- "implementation_version": "1",
- "description": "LunarG Validation Layer",
-diff --git a/layers/linux/VkLayer_swapchain.json b/layers/linux/VkLayer_swapchain.json
-index 5fe0ef8..6d0b500 100644
---- a/layers/linux/VkLayer_swapchain.json
-+++ b/layers/linux/VkLayer_swapchain.json
-@@ -3,7 +3,7 @@
- "layer" : {
- "name": "VK_LAYER_LUNARG_swapchain",
- "type": "GLOBAL",
-- "library_path": "./libVkLayer_swapchain.so",
-+ "library_path": "libVkLayer_swapchain.so",
- "api_version": "1.0.26",
- "implementation_version": "1",
- "description": "LunarG Validation Layer",
-diff --git a/layers/linux/VkLayer_threading.json b/layers/linux/VkLayer_threading.json
-index 59feb59..fd6bedf 100644
---- a/layers/linux/VkLayer_threading.json
-+++ b/layers/linux/VkLayer_threading.json
-@@ -3,7 +3,7 @@
- "layer" : {
- "name": "VK_LAYER_GOOGLE_threading",
- "type": "GLOBAL",
-- "library_path": "./libVkLayer_threading.so",
-+ "library_path": "libVkLayer_threading.so",
- "api_version": "1.0.26",
- "implementation_version": "1",
- "description": "Google Validation Layer",
-diff --git a/layers/linux/VkLayer_unique_objects.json b/layers/linux/VkLayer_unique_objects.json
-index 59e1f89..72b77ee 100644
---- a/layers/linux/VkLayer_unique_objects.json
-+++ b/layers/linux/VkLayer_unique_objects.json
-@@ -3,7 +3,7 @@
- "layer" : {
- "name": "VK_LAYER_GOOGLE_unique_objects",
- "type": "GLOBAL",
-- "library_path": "./libVkLayer_unique_objects.so",
-+ "library_path": "libVkLayer_unique_objects.so",
- "api_version": "1.0.26",
- "implementation_version": "1",
- "description": "Google Validation Layer"
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0008-demos-make-shader-location-relative.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0008-demos-make-shader-location-relative.patch
deleted file mode 100644
index 16409b57..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0008-demos-make-shader-location-relative.patch
+++ /dev/null
@@ -1,261 +0,0 @@
-From 4e68da29ebc45a41845d7127979878930b4c170b Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Mon, 5 Sep 2016 15:47:16 +0500
-Subject: [PATCH 1/2] demos: make shader location relative
-
-The demo binaries expect the shader (frag/vert.spv)
-location to be PWD so a user has to cd to /usr/bin
-if the binaries are installed there in order to
-run them correctly.
-This patch tries to find the location of the binary
-and then assumes that the shaders are located in the
-same location as the binary so a user can install
-everything to a single dir and that will work.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- demos/cube.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------
- demos/tri.c | 49 ++++++++++++++++++++++++++++++++++++++++++++--
- 2 files changed, 105 insertions(+), 8 deletions(-)
-
-diff --git a/demos/cube.c b/demos/cube.c
-index 6017444..f79bc59 100644
---- a/demos/cube.c
-+++ b/demos/cube.c
-@@ -29,6 +29,7 @@
- #include <stdbool.h>
- #include <assert.h>
- #include <signal.h>
-+#include <unistd.h>
- #if defined(VK_USE_PLATFORM_XLIB_KHR) || defined(VK_USE_PLATFORM_XCB_KHR)
- #include <X11/Xutil.h>
- #endif
-@@ -415,6 +416,8 @@ struct demo {
-
- uint32_t current_buffer;
- uint32_t queue_count;
-+
-+ char bin_path[255];
- };
-
- VKAPI_ATTR VkBool32 VKAPI_CALL
-@@ -1206,18 +1209,25 @@ static void demo_prepare_textures(struct demo *demo) {
- const VkFormat tex_format = VK_FORMAT_R8G8B8A8_UNORM;
- VkFormatProperties props;
- uint32_t i;
-+ char tex_file[255];
-
- vkGetPhysicalDeviceFormatProperties(demo->gpu, tex_format, &props);
-
- for (i = 0; i < DEMO_TEXTURE_COUNT; i++) {
- VkResult U_ASSERT_ONLY err;
--
-+ if (strlen(demo->bin_path) > 0) {
-+ strcpy(tex_file, demo->bin_path);
-+ strcat(tex_file, "/");
-+ strcat(tex_file, tex_files[i]);
-+ }
-+ else
-+ strcpy(tex_file, tex_files[i]);
- if ((props.linearTilingFeatures &
- VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT) &&
- !demo->use_staging_buffer) {
- /* Device can texture using linear textures */
- demo_prepare_texture_image(
-- demo, tex_files[i], &demo->textures[i], VK_IMAGE_TILING_LINEAR,
-+ demo, tex_file, &demo->textures[i], VK_IMAGE_TILING_LINEAR,
- VK_IMAGE_USAGE_SAMPLED_BIT,
- VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_COHERENT_BIT);
-@@ -1228,13 +1238,13 @@ static void demo_prepare_textures(struct demo *demo) {
-
- memset(&staging_texture, 0, sizeof(staging_texture));
- demo_prepare_texture_image(
-- demo, tex_files[i], &staging_texture, VK_IMAGE_TILING_LINEAR,
-+ demo, tex_file, &staging_texture, VK_IMAGE_TILING_LINEAR,
- VK_IMAGE_USAGE_TRANSFER_SRC_BIT,
- VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
- VK_MEMORY_PROPERTY_HOST_COHERENT_BIT);
-
- demo_prepare_texture_image(
-- demo, tex_files[i], &demo->textures[i], VK_IMAGE_TILING_OPTIMAL,
-+ demo, tex_file, &demo->textures[i], VK_IMAGE_TILING_OPTIMAL,
- (VK_IMAGE_USAGE_TRANSFER_DST_BIT | VK_IMAGE_USAGE_SAMPLED_BIT),
- VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT);
-
-@@ -1557,8 +1567,16 @@ static VkShaderModule demo_prepare_vs(struct demo *demo) {
- #else
- void *vertShaderCode;
- size_t size;
-+ char fname[255];
-+ if (strlen(demo->bin_path) > 0) {
-+ strcpy(fname, demo->bin_path);
-+ strcat(fname, "/");
-+ strcat(fname, "cube-vert.spv");
-+ }
-+ else
-+ strcpy(fname, "cube-vert.spv");
-
-- vertShaderCode = demo_read_spv("cube-vert.spv", &size);
-+ vertShaderCode = demo_read_spv(fname, &size);
-
- demo->vert_shader_module =
- demo_prepare_shader_module(demo, vertShaderCode, size);
-@@ -1582,8 +1600,16 @@ static VkShaderModule demo_prepare_fs(struct demo *demo) {
- #else
- void *fragShaderCode;
- size_t size;
-+ char fname[255];
-+ if (strlen(demo->bin_path) > 0) {
-+ strcpy(fname, demo->bin_path);
-+ strcat(fname, "/");
-+ strcat(fname, "cube-frag.spv");
-+ }
-+ else
-+ strcpy(fname, "cube-frag.spv");
-
-- fragShaderCode = demo_read_spv("cube-frag.spv", &size);
-+ fragShaderCode = demo_read_spv(fname, &size);
-
- demo->frag_shader_module =
- demo_prepare_shader_module(demo, fragShaderCode, size);
-@@ -3034,6 +3060,30 @@ static void demo_init_connection(struct demo *demo) {
- #endif
- }
-
-+static void find_bin_path(char *in_arg, char *ret_path) {
-+ char *ptr = getenv("PATH");
-+ char *pch_temp;
-+ char pch[255];
-+
-+ if (access(in_arg, F_OK ) == 0) {
-+ pch_temp = strrchr(in_arg, '/');
-+ strncpy(ret_path, in_arg, strlen(in_arg) - strlen(pch_temp));
-+ } else if (in_arg[0] != '/') {
-+ pch_temp = strtok(ptr, ":");
-+ while (pch_temp != NULL) {
-+ strcpy(pch, pch_temp);
-+ strcat(pch, "/");
-+ strcat(pch, in_arg);
-+ if ((access(pch, F_OK ) == 0)) {
-+ strcpy(ret_path, pch_temp);
-+ break;
-+ }
-+ else
-+ pch_temp = strtok(NULL, ":");
-+ }
-+ }
-+}
-+
- static void demo_init(struct demo *demo, int argc, char **argv) {
- vec3 eye = {0.0f, 3.0f, 5.0f};
- vec3 origin = {0, 0, 0};
-@@ -3053,6 +3053,8 @@ static void demo_init(struct demo *demo, int argc, char **argv) {
- mat4x4_identity(demo->model_matrix);
-
- demo->projection_matrix[1][1]*=-1; //Flip projection matrix from GL to Vulkan orientation.
-+
-+ find_bin_path(argv[0], demo->bin_path);
- }
-
- #if defined(VK_USE_PLATFORM_WIN32_KHR)
-diff --git a/demos/tri.c b/demos/tri.c
-index 35d33f2..77ee5a1 100644
---- a/demos/tri.c
-+++ b/demos/tri.c
-@@ -39,6 +39,7 @@
- #include <stdbool.h>
- #include <assert.h>
- #include <signal.h>
-+#include <unistd.h>
-
- #ifdef _WIN32
- #pragma comment(linker, "/subsystem:windows")
-@@ -262,6 +263,8 @@ struct demo {
- bool quit;
- uint32_t current_buffer;
- uint32_t queue_count;
-+
-+ char bin_path[255];
- };
-
- VKAPI_ATTR VkBool32 VKAPI_CALL
-@@ -1288,8 +1291,16 @@ static VkShaderModule demo_prepare_vs(struct demo *demo) {
- #else
- void *vertShaderCode;
- size_t size = 0;
-+ char fname[255];
-+ if (strlen(demo->bin_path) > 0) {
-+ strcpy(fname, demo->bin_path);
-+ strcat(fname, "/");
-+ strcat(fname, "tri-vert.spv");
-+ }
-+ else
-+ strcpy(fname, "tri-vert.spv");
-
-- vertShaderCode = demo_read_spv("tri-vert.spv", &size);
-+ vertShaderCode = demo_read_spv(fname, &size);
-
- demo->vert_shader_module =
- demo_prepare_shader_module(demo, vertShaderCode, size);
-@@ -1313,8 +1324,16 @@ static VkShaderModule demo_prepare_fs(struct demo *demo) {
- #else
- void *fragShaderCode;
- size_t size;
-+ char fname[255];
-+ if (strlen(demo->bin_path) > 0) {
-+ strcpy(fname, demo->bin_path);
-+ strcat(fname, "/");
-+ strcat(fname, "tri-frag.spv");
-+ }
-+ else
-+ strcpy(fname, "tri-frag.spv");
-
-- fragShaderCode = demo_read_spv("tri-frag.spv", &size);
-+ fragShaderCode = demo_read_spv(fname, &size);
-
- demo->frag_shader_module =
- demo_prepare_shader_module(demo, fragShaderCode, size);
-@@ -2447,6 +2466,30 @@ static void demo_init_connection(struct demo *demo) {
- #endif // _WIN32
- }
-
-+static void find_bin_path(const char *in_arg, char *ret_path) {
-+ char *ptr = getenv("PATH");
-+ char *pch_temp;
-+ char pch[255];
-+
-+ if (access(in_arg, F_OK ) == 0) {
-+ pch_temp = strrchr(in_arg, '/');
-+ strncpy(ret_path, in_arg, strlen(in_arg) - strlen(pch_temp));
-+ } else if (in_arg[0] != '/') {
-+ pch_temp = strtok(ptr, ":");
-+ while (pch_temp != NULL) {
-+ strcpy(pch, pch_temp);
-+ strcat(pch, "/");
-+ strcat(pch, in_arg);
-+ if ((access(pch, F_OK ) == 0)) {
-+ strcpy(ret_path, pch_temp);
-+ break;
-+ }
-+ else
-+ pch_temp = strtok(NULL, ":");
-+ }
-+ }
-+}
-+
- static void demo_init(struct demo *demo, const int argc, const char *argv[])
- {
- memset(demo, 0, sizeof(*demo));
-@@ -2490,6 +2533,8 @@ static void demo_init(struct demo *demo, const int argc, const char *argv[])
- demo->height = 300;
- demo->depthStencil = 1.0;
- demo->depthIncrement = -0.01f;
-+
-+ find_bin_path(argv[0], demo->bin_path);
- }
-
- static void demo_cleanup(struct demo *demo) {
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch
deleted file mode 100644
index 25785ffb..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers/0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From b73227e97086116e596206b22ce0356bfc9b0a2c Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Fri, 11 Nov 2016 14:48:54 +0500
-Subject: [PATCH] vulkaninfo.c: fix segfault when DISPLAY is not set
-
-Both xlib and xcb interfaces expect the DISPLAY environment
-variable to be set before creation of a window and the
-display creation mechanism would segfault if that is
-not the case and won't provide the user with details on
-what has to be done to correct the problem.
-We now handle such scenarios and exit cleanly after
-providing the user with some details.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- demos/vulkaninfo.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/demos/vulkaninfo.c b/demos/vulkaninfo.c
-index 324720c..da0a7c3 100644
---- a/demos/vulkaninfo.c
-+++ b/demos/vulkaninfo.c
-@@ -900,6 +900,9 @@ static void app_create_xlib_window(struct app_instance *inst) {
- long visualMask = VisualScreenMask;
- int numberOfVisuals;
-
-+ if (inst->xlib_display == NULL)
-+ return;
-+
- XVisualInfo vInfoTemplate={};
- vInfoTemplate.screen = DefaultScreen(inst->xlib_display);
- XVisualInfo *visualInfo = XGetVisualInfo(inst->xlib_display, visualMask,
-@@ -1488,6 +1491,12 @@ int main(int argc, char **argv) {
- app_destroy_win32_window(&inst);
- }
- #endif
-+#if defined(VK_USE_PLATFORM_XCB_KHR) || defined(VK_USE_PLATFORM_XLIB_KHR)
-+ if (getenv("DISPLAY") == NULL) {
-+ printf("'DISPLAY' environment variable not set... Exiting!\n");
-+ goto out;
-+ }
-+#endif
- //--XCB--
- #ifdef VK_USE_PLATFORM_XCB_KHR
- if (has_extension(VK_KHR_XCB_SURFACE_EXTENSION_NAME,
-@@ -1508,6 +1517,10 @@ int main(int argc, char **argv) {
- if (has_extension(VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
- inst.global_extension_count, inst.global_extensions)) {
- app_create_xlib_window(&inst);
-+ if (inst.xlib_display == NULL) {
-+ printf("'DISPLAY' variable not set correctly. Exiting!\n'");
-+ goto out;
-+ }
- for (i = 0; i < gpu_count; i++) {
- app_create_xlib_surface(&inst);
- printf("GPU id : %u (%s)\n", i, gpus[i].props.deviceName);
-@@ -1528,6 +1541,7 @@ int main(int argc, char **argv) {
- printf("\n\n");
- }
-
-+out:
- for (i = 0; i < gpu_count; i++)
- app_gpu_destroy(&gpus[i]);
-
---
-1.9.1
-
diff --git a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers_1.0.26.bb b/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers_1.0.26.bb
deleted file mode 100644
index e8ea2605..00000000
--- a/meta-amdfalconx86/recipes-graphics/vulkan/vulkan-loader-layers_1.0.26.bb
+++ /dev/null
@@ -1,58 +0,0 @@
-SUMMARY = "Vulkan Ecosystem Components - Loader and Validation Layers"
-DESCRIPTION = "Vulkan is a new generation graphics and compute API that \
- provides high-efficiency, cross-platform access to modern \
- GPUs used in a wide variety of devices from PCs and \
- consoles to mobile phones and embedded platforms."
-SECTION = "graphics"
-HOMEPAGE = "https://www.khronos.org/vulkan"
-DEPENDS = "bison-native libx11 libxcb glslang glslang-native spirv-tools \
- libice libxext libsm"
-
-RDEPENDS_${PN} = "${PN}-layer-libs libxcb-sync libxcb-present libxcb-dri3"
-
-inherit cmake python3native
-
-REQUIRED_DISTRO_FEATURES = "x11"
-
-LICENSE = "Apache-2.0"
-LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=99c647ca3d4f6a4b9d8628f757aad156"
-
-S = "${WORKDIR}/git"
-
-SRCREV = "ebf46deb849a2d4cab3382c606a9fe36699dfa78"
-SRC_URI = "git://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers;branch=sdk-${PV} \
- file://0001-CMakeLists-add-include-path-so-Xlib.h-is-found-as-ne.patch \
- file://0003-obey-CMAKE_INSTALL_LIBDIR.patch \
- file://0004-install-the-vulkan-loader.patch \
- file://0005-install-demos.patch \
- file://0006-json-correct-layer-lib-paths.patch \
- file://0008-demos-make-shader-location-relative.patch \
- file://0009-vulkaninfo.c-fix-segfault-when-DISPLAY-is-not-set.patch"
-
-EXTRA_OECMAKE = " \
- -DCUSTOM_GLSLANG_BIN_ROOT=1 \
- -DGLSLANG_BINARY_ROOT=${STAGING_DIR_HOST}/usr \
- -DCUSTOM_SPIRV_TOOLS_BIN_ROOT=1 \
- -DSPIRV_TOOLS_BINARY_ROOT=${STAGING_DIR_HOST}/usr \
- -DBUILD_TESTS=1 \
-"
-
-PACKAGES =+ "${PN}-layer-libs"
-FILES_${PN}-layer-libs = "${libdir}/libVkLayer_*.so"
-
-FILES_SOLIBSDEV = ""
-FILES_${PN} += "${libdir}/libvulkan.so"
-INSANE_SKIP_${PN} = "dev-so"
-
-do_install_append() {
- cp -f ${B}/demos/*.spv ${D}${bindir}
- cp -f ${B}/demos/*.ppm ${D}${bindir}
- mv ${D}${bindir}/tri ${D}${bindir}/tri-vulkan
- mv ${D}${bindir}/cube ${D}${bindir}/cube-vulkan
-
- install -d ${D}${sysconfdir}/vulkan/explicit_layer.d
- cp -f ${B}/layers/*.json ${D}${sysconfdir}/vulkan/explicit_layer.d
-
- install -d ${D}${includedir}
- cp -rf ${S}/include/vulkan ${D}${includedir}
-}
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb
deleted file mode 100644
index b23e5ce6..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-spi/amd-spi_1.0.bb
+++ /dev/null
@@ -1,16 +0,0 @@
-DESCRIPTION = "This kernel module provides support for AMD SPI controller driver"
-LICENSE = "BSD | GPLv2"
-LIC_FILES_CHKSUM = "file://spi_amd.c;endline=29;md5=e9fdf6da58412e619d89ec9e135a1be3"
-
-inherit module
-
-SRC_URI = "file://Makefile \
- file://spi_amd.c \
- file://spi_amd.h \
- file://spirom.c \
- file://spirom.h \
- "
-
-S = "${WORKDIR}"
-
-# The inherit of module.bbclass will take care of the rest
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile b/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile
deleted file mode 100644
index f778a69a..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-obj-m := spi_amd.o spirom.o
-
-SRC := $(shell pwd)
-
-all:
- $(MAKE) -C $(KERNEL_SRC) M=$(SRC)
-
-modules_install:
- $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
-
-clean:
- rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
- rm -f Module.markers Module.symvers modules.order
- rm -rf .tmp_versions Modules.symvers
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c
deleted file mode 100644
index 76c08cec..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*****************************************************************************
-*
-* Copyright (c) 2013, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*
-***************************************************************************/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/spi/spi.h>
-#include <linux/kthread.h>
-
-#include "spi_amd.h"
-
-struct amd_platform_data {
- u8 chip_select;
-};
-
-struct amd_spi {
- void __iomem *io_remap_addr;
- unsigned long io_base_addr;
- u32 rom_addr;
- struct spi_master *master;
- struct amd_platform_data controller_data;
- struct task_struct *kthread_spi;
- struct list_head msg_queue;
- wait_queue_head_t wq;
-};
-
-static struct pci_device_id amd_spi_pci_device_id[] = {
- { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE) },
- {}
-};
-MODULE_DEVICE_TABLE(pci, amd_spi_pci_device_id);
-
-static inline u8 amd_spi_readreg8(struct spi_master *master, int idx)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
-
- return ioread8((u8 *)amd_spi->io_remap_addr + idx);
-}
-
-static inline void amd_spi_writereg8(struct spi_master *master, int idx,
- u8 val)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
-
- iowrite8(val, ((u8 *)amd_spi->io_remap_addr + idx));
-}
-
-static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx,
- u8 set, u8 clear)
-{
- u8 tmp = amd_spi_readreg8(master, idx);
- tmp = (tmp & ~clear) | set;
- amd_spi_writereg8(master, idx, tmp);
-}
-
-static inline u32 amd_spi_readreg32(struct spi_master *master, int idx)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
-
- return ioread32((u8 *)amd_spi->io_remap_addr + idx);
-}
-
-static inline void amd_spi_writereg32(struct spi_master *master, int idx,
- u32 val)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
-
- iowrite32(val, ((u8 *)amd_spi->io_remap_addr + idx));
-}
-
-static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx,
- u32 set, u32 clear)
-{
- u32 tmp = amd_spi_readreg32(master, idx);
- tmp = (tmp & ~clear) | set;
- amd_spi_writereg32(master, idx, tmp);
-}
-
-static void amd_spi_select_chip(struct spi_master *master)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
- u8 chip_select = amd_spi->controller_data.chip_select;
-
- amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select,
- AMD_SPI_ALT_CS_MASK);
-}
-
-
-static void amd_spi_clear_fifo_ptr(struct spi_master *master)
-{
- amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR,
- AMD_SPI_FIFO_CLEAR);
-}
-
-static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode)
-{
- amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode,
- AMD_SPI_OPCODE_MASK);
-}
-
-static inline void amd_spi_set_rx_count(struct spi_master *master,
- u8 rx_count)
-{
- amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
-}
-
-static inline void amd_spi_set_tx_count(struct spi_master *master,
- u8 tx_count)
-{
- amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
-}
-
-static void amd_spi_execute_opcode(struct spi_master *master)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
- bool spi_busy;
-
- /* Set ExecuteOpCode bit in the CTRL0 register */
- amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
- AMD_SPI_EXEC_CMD);
-
- /* poll for SPI bus to become idle */
- spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr +
- AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
- while (spi_busy) {
- set_current_state(TASK_INTERRUPTIBLE);
- schedule();
- set_current_state(TASK_RUNNING);
- spi_busy = (ioread32((u8 *)amd_spi->io_remap_addr +
- AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
- }
-}
-
-/* Helper function */
-#ifdef CONFIG_SPI_DEBUG
-static void amd_spi_dump_reg(struct spi_master *master)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
-
- printk(KERN_DEBUG DRIVER_NAME ": SPI CTRL 0 registers: 0x%.8x\n",
- ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_CTRL0_REG));
- /*
- * We cannot read CTRL1 register, because reading it would
- * inadvertently increment the FIFO pointer.
- */
- printk(KERN_DEBUG DRIVER_NAME ": SPI ALT CS registers: 0x%.2x\n",
- ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_ALT_CS_REG));
- printk(KERN_DEBUG DRIVER_NAME ": SPI Tx Byte Count: 0x%.2x\n",
- ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_TX_COUNT_REG));
- printk(KERN_DEBUG DRIVER_NAME ": SPI Rx Byte Count: 0x%.2x\n",
- ioread8((u8 *)amd_spi->io_remap_addr + AMD_SPI_RX_COUNT_REG));
- printk(KERN_DEBUG DRIVER_NAME ": SPI Status registers: 0x%.8x\n",
- ioread32((u8 *)amd_spi->io_remap_addr + AMD_SPI_STATUS_REG));
-}
-#else
-static void amd_spi_dump_reg(struct spi_master *master) {}
-#endif
-
-
-static int amd_spi_master_setup(struct spi_device *spi)
-{
- struct spi_master *master = spi->master;
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
-
- amd_spi->controller_data.chip_select = spi->chip_select;
-
- amd_spi_select_chip(master);
-
- return 0;
-}
-
-static int amd_spi_master_transfer(struct spi_master *master,
- struct spi_message *msg)
-{
- struct amd_spi *amd_spi = spi_master_get_devdata(master);
-
- /*
- * Add new message to the queue and let the kernel thread know
- * about it.
- */
- list_add_tail(&msg->queue, &amd_spi->msg_queue);
- wake_up_interruptible(&amd_spi->wq);
-
- return 0;
-}
-static int amd_spi_thread(void *t)
-{
- struct amd_spi *amd_spi = t;
- struct spi_master *master = amd_spi->master;
- struct spi_transfer *transfer = NULL;
- struct spi_message *message = NULL;
- int direction = 0,i = 0,saved_index = 0;
- int opcode_found = 0,recv_flag = 0,tx_len = 0,rx_len = 0;
- u8 cmd_opcode = 0;
- u8 *buffer = NULL;
-
- /*
- * What we do here is actually pretty simple. We pick one message
- * at a time from the message queue set up by the controller, and
- * then process all the spi_transfers of that spi_message in one go.
- * We then remove the message from the queue, and complete the
- * transaction. This might not be the best approach, but this is how
- * we chose to implement this. Note that out SPI controller has FIFO
- * size of 70 bytes, but we consider it to contain a maximum of
- * 64-bytes of data and 3-bytes of address.
- */
- while (1) {
- /*
- * Let us wait on a wait queue till the message queue is empty.
- */
- wait_event_interruptible(amd_spi->wq,
- !list_empty(&amd_spi->msg_queue));
-
- /* stop condition */
- if (kthread_should_stop()) {
- set_current_state(TASK_RUNNING);
- break;
- }
-
- /*
- * Else, pull the very first message from the queue and process
- * all transfers within that message. And process the messages
- * in a pure linear fashion. We also remove the spi_message
- * from the queue.
- */
- message = list_entry(amd_spi->msg_queue.next,
- struct spi_message, queue);
- list_del_init(&message->queue);
-
- /* We store the CS# line to be used for this spi_message */
- amd_spi->controller_data.chip_select =
- message->spi->chip_select;
-
- /* Setting all variables to default value. */
- direction = i = 0;
- opcode_found = 0;
- recv_flag = tx_len = rx_len = 0;
- cmd_opcode = 0;
- buffer = NULL;
- saved_index = 0;
-
- amd_spi_select_chip(master);
-
- /*
- * This loop extracts spi_transfers from the spi message,
- * programs the command into command register. Pointer variable
- * *buffer* points to either tx_buf or rx_buf of spi_transfer
- * depending on direction of transfer. Also programs FIFO of
- * controller if data has to be transmitted.
- */
- list_for_each_entry(transfer, &message->transfers,
- transfer_list)
- {
- if(transfer->rx_buf != NULL)
- direction = RECEIVE;
- else if(transfer->tx_buf != NULL)
- direction = TRANSMIT;
-
- switch (direction) {
- case TRANSMIT:
- buffer = (u8 *)transfer->tx_buf;
-
- if(opcode_found != 1) {
- /* Store no. of bytes to be sent into
- * FIFO */
- tx_len = transfer->len - 1;
- /* Store opcode */
- cmd_opcode = *(u8 *)transfer->tx_buf;
- /* Pointing to start of TX data */
- buffer++;
- /* Program the command register*/
- amd_spi_set_opcode(master, cmd_opcode);
- opcode_found = 1;
- } else {
- /* Store no. of bytes to be sent into
- * FIFO */
- tx_len = transfer->len;
- }
-
- /* Write data into the FIFO. */
- for (i = 0; i < tx_len; i++) {
- iowrite8(buffer[i],
- ((u8 *)amd_spi->io_remap_addr +
- AMD_SPI_FIFO_BASE +
- i + saved_index));
- }
-
- /* Set no. of bytes to be transmitted */
- amd_spi_set_tx_count(master,
- tx_len + saved_index);
-
- /*
- * Saving the index, from where next
- * spi_transfer's data will be stored in FIFO.
- */
- saved_index = i;
- break;
- case RECEIVE:
- /* Store no. of bytes to be received from
- * FIFO */
- rx_len = transfer->len;
- buffer = (u8 *)transfer->rx_buf;
- recv_flag=1;
- break;
- }
- }
-
- /* Set the RX count to the number of bytes to expect in
- * response */
- amd_spi_set_rx_count(master, rx_len );
- amd_spi_clear_fifo_ptr(master);
- amd_spi_dump_reg(master);
- /* Executing command */
- amd_spi_execute_opcode(master);
- amd_spi_dump_reg(master);
-
- if(recv_flag == 1) {
- /* Read data from FIFO to receive buffer */
- for (i = 0; i < rx_len; i++) {
- buffer[i] = ioread8((u8 *)amd_spi->io_remap_addr
- + AMD_SPI_FIFO_BASE
- + tx_len + i);
- }
-
- recv_flag = 0;
- }
-
- /* Update statistics */
- message->actual_length = tx_len + rx_len + 1 ;
- /* complete the transaction */
- message->status = 0;
- spi_finalize_current_message(master);
- }
-
- return 0;
-}
-
-static int amd_spi_pci_probe(struct pci_dev *pdev,
- const struct pci_device_id *id)
-{
- struct device *dev = &pdev->dev;
- struct spi_master *master;
- struct amd_spi *amd_spi;
- u32 io_base_addr;
- int err = 0;
-
- /* Allocate storage for spi_master and driver private data */
- master = spi_alloc_master(dev, sizeof(struct amd_spi));
- if (master == NULL) {
- dev_err(dev, "Error allocating SPI master\n");
- return -ENOMEM;
- }
-
- amd_spi = spi_master_get_devdata(master);
- amd_spi->master = master;
-
- /*
- * Lets first get the base address of SPI registers. The SPI Base
- * Address is stored at offset 0xA0 into the LPC PCI configuration
- * space. As per the specification, it is stored at bits 6:31 of the
- * register. The address is aligned at 64-byte boundary,
- * so we should just mask the lower 6 bits and get the address.
- */
- pci_read_config_dword(pdev, AMD_PCI_LPC_SPI_BASE_ADDR_REG,
- &io_base_addr);
- amd_spi->io_base_addr = io_base_addr & AMD_SPI_BASE_ADDR_MASK;
- amd_spi->io_remap_addr = ioremap_nocache(amd_spi->io_base_addr,
- AMD_SPI_MEM_SIZE);
- if (amd_spi->io_remap_addr == NULL) {
- dev_err(dev, "ioremap of SPI registers failed\n");
- err = -ENOMEM;
- goto err_free_master;
- }
- dev_dbg(dev, "io_base_addr: 0x%.8lx, io_remap_address: %p\n",
- amd_spi->io_base_addr, amd_spi->io_remap_addr);
- INIT_LIST_HEAD(&amd_spi->msg_queue);
- init_waitqueue_head(&amd_spi->wq);
- amd_spi->kthread_spi = kthread_run(amd_spi_thread, amd_spi,
- "amd_spi_thread");
-
- /* Now lets initialize the fields of spi_master */
- master->bus_num = 0; /*
- * This should be the same as passed in
- * spi_board_info structure
- */
- master->num_chipselect = 4; /* Can be overwritten later during setup */
- master->mode_bits = 0;
- master->flags = 0;
- master->setup = amd_spi_master_setup;
- master->transfer_one_message = amd_spi_master_transfer;
- /* Register the controller with SPI framework */
- err = spi_register_master(master);
- if (err) {
- dev_err(dev, "error registering SPI controller\n");
- goto err_iounmap;
- }
- pci_set_drvdata(pdev, amd_spi);
-
- return 0;
-
-err_iounmap:
- iounmap(amd_spi->io_remap_addr);
-err_free_master:
- spi_master_put(master);
-
- return 0;
-}
-
-static void amd_spi_pci_remove(struct pci_dev *pdev)
-{
- struct amd_spi *amd_spi = pci_get_drvdata(pdev);
-
- kthread_stop(amd_spi->kthread_spi);
- iounmap(amd_spi->io_remap_addr);
- spi_unregister_master(amd_spi->master);
- spi_master_put(amd_spi->master);
- pci_set_drvdata(pdev, NULL);
-}
-
-static struct pci_driver amd_spi_pci_driver = {
- .name = "amd_spi",
- .id_table = amd_spi_pci_device_id,
- .probe = amd_spi_pci_probe,
- .remove = amd_spi_pci_remove,
-};
-
-static int __init amd_spi_init(void)
-{
- int ret;
-
- pr_info("AMD SPI Driver v%s\n", SPI_VERSION);
-
- ret = pci_register_driver(&amd_spi_pci_driver);
- if (ret)
- return ret;
-
- return 0;
-}
-module_init(amd_spi_init);
-
-static void __exit amd_spi_exit(void)
-{
- pci_unregister_driver(&amd_spi_pci_driver);
-}
-module_exit(amd_spi_exit);
-
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
-MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
-MODULE_DESCRIPTION("AMD SPI Master Controller Driver");
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h
deleted file mode 100644
index ec58b9a8..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spi_amd.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef SPI_AMD_H
-#define SPI_AMD_H
-
-#define DRIVER_NAME "spi_amd"
-#define SPI_VERSION "1.0"
-
-#define AMD_SPI_CTRL0_REG 0x00
- #define AMD_SPI_EXEC_CMD (0x1 << 16)
- #define AMD_SPI_OPCODE_MASK 0xFF
- #define AMD_SPI_FIFO_CLEAR (0x1 << 20)
- #define AMD_SPI_BUSY (0x1 << 31)
-#define AMD_SPI_ALT_CS_REG 0x1D
- #define AMD_SPI_ALT_CS_MASK 0x3
-#define AMD_SPI_FIFO_BASE 0x80
-#define AMD_SPI_TX_COUNT_REG 0x48
-#define AMD_SPI_RX_COUNT_REG 0x4B
-#define AMD_SPI_STATUS_REG 0x4C
-
-#define AMD_PCI_LPC_SPI_BASE_ADDR_REG 0xA0
-#define AMD_SPI_BASE_ADDR_MASK ~0x3F
-#define AMD_SPI_MEM_SIZE 200
-
-#define PCI_DEVICE_ID_AMD_LPC_BRIDGE 0x790E
-
-#define TRANSMIT 1
-#define RECEIVE 2
-
-#endif /* SPI_AMD_H */
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c
deleted file mode 100644
index 1a41681a..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.c
+++ /dev/null
@@ -1,554 +0,0 @@
-/*****************************************************************************
-*
-* spirom.c - SPI ROM client driver
-*
-* Copyright (c) 2014, Advanced Micro Devices, Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*
-***************************************************************************/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/ioctl.h>
-#include <linux/fs.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/mutex.h>
-#include <linux/slab.h>
-#include <linux/spi/spi.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/amd_imc.h>
-
-#include <asm/uaccess.h>
-
-#include "spirom.h"
-
-#define SPIROM_VERSION "0.2"
-
-/*
- * SPI has a character major number assigned. We allocate minor numbers
- * dynamically using a bitmask. You must use hotplug tools, such as udev
- * (or mdev with busybox) to create and destroy the /dev/spiromB.C device
- * nodes, since there is no fixed association of minor numbers with any
- * particular SPI bus or device.
- */
-#define SPIROM_MAJOR 153 /* assigned */
-#define N_SPI_MINORS 32 /* ... up to 256 */
-
-#define SPI_BUS 0
-#define SPI_BUS_CS1 0
-
-static unsigned long minors[N_SPI_MINORS / BITS_PER_LONG];
-
-
-struct spirom_data {
- dev_t devt;
- spinlock_t spi_lock;
- struct spi_device *spi;
- struct list_head device_entry;
- struct completion done;
-
- struct mutex buf_lock;
- unsigned users;
-};
-
-static LIST_HEAD(device_list);
-static DEFINE_MUTEX(device_list_lock);
-
-/*-------------------------------------------------------------------------*/
-
-/* We need to keep the device pointer because we explicity add the device
- * by using spi_new_device at the end of spirom_init. In order to confirm
- * a clean exit we need to unregister the device while exiting.
- * This cannot be done in the driver's remove call as that would generate
- * a recursive loop.
- */
-
-static struct spi_device *spirom_device;
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * We can't use the standard synchronous wrappers for file I/O; we
- * need to protect against async removal of the underlying spi_device.
- */
-static void spirom_complete(void *arg)
-{
- complete(arg);
-}
-
-static ssize_t
-spirom_sync(struct spirom_data *spirom, struct spi_message *message)
-{
- int status;
-
- message->complete = spirom_complete;
- message->context = &spirom->done;
-
- spin_lock_irq(&spirom->spi_lock);
- if (spirom->spi == NULL)
- status = -ESHUTDOWN;
- else
- status = spi_async(spirom->spi, message);
- spin_unlock_irq(&spirom->spi_lock);
-
- if (status == 0) {
- /*
- * There might be cases where the controller driver has been
- * unloaded in the middle of a transaction. So we might end up
- * in a situation where we will be waiting for an event which
- * will never happen. So we provide a timeout of 1 second for
- * situations like this.
- */
- wait_for_completion_timeout(&spirom->done, HZ);
- status = message->status;
- if (status == 0)
- status = message->actual_length;
- }
- return status;
-}
-
-static int spirom_message(struct spirom_data *spirom,
- struct spi_ioc_transfer *u_trans, unsigned long arg)
-{
- struct spi_message msg;
- struct spi_transfer *transfer;
- u8 *buffer;
- int status = u_trans->len;
-
- buffer = u_trans->buf;
- spi_message_init(&msg);
-
- /* The very first spi_transfer will contain the command only */
- transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL);
- if (!transfer)
- return -ENOMEM;
-
- transfer->tx_buf = buffer;
- transfer->len = 1;
- buffer += transfer->len;
- spi_message_add_tail(transfer, &msg);
-
- /*
- * If the command expects an address as its argument, we populate
- * it in the very next spi_transfer.
- */
- if (u_trans->addr_present) {
- transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL);
- if (!transfer)
- return -ENOMEM;
-
- transfer->tx_buf = buffer;
- transfer->len = 3; // 3-byte address
- buffer += transfer->len;
- spi_message_add_tail(transfer, &msg);
- }
-
- /*
- * Next is data, which can have a maximum of 64-bytes, the size limited
- * by the number of bytes that can stored in the controller FIFO.
- */
- if (u_trans->len) {
- transfer = kzalloc(sizeof(struct spi_transfer), GFP_KERNEL);
- if (!transfer)
- return -ENOMEM;
-
- if (u_trans->direction == TRANSMIT)
- transfer->tx_buf = buffer;
- else if (u_trans->direction == RECEIVE)
- transfer->rx_buf = buffer;
-
- transfer->len = u_trans->len;
- /* No need to increment buffer pointer */
- spi_message_add_tail(transfer, &msg);
- }
-
- status = spirom_sync(spirom, &msg);
-
- if (u_trans->direction == RECEIVE) {
- /*
- * The received data should have been populated in
- * u_trans->buf, so we just need to copy it into the
- * user-space buffer.
- */
- buffer = u_trans->buf;
- if (u_trans->addr_present) {
- buffer += 4; // 1-byte command and 3-byte address
- if(__copy_to_user((u8 __user *)
- (((struct spi_ioc_transfer *)arg)->buf) + 4,
- buffer, u_trans->len)) {
- status = -EFAULT;
- }
- } else {
- buffer += 1; // 1-byte command only
- if(__copy_to_user((u8 __user *)
- (((struct spi_ioc_transfer *)arg)->buf) + 1,
- buffer, u_trans->len)) {
- status = -EFAULT;
- }
- }
- }
-
- /* Done with everything, free the memory taken by spi_transfer */
- while (msg.transfers.next != &msg.transfers) {
- transfer = list_entry(msg.transfers.next, struct spi_transfer,
- transfer_list);
- msg.transfers.next = transfer->transfer_list.next;
- transfer->transfer_list.next->prev = &msg.transfers;
- kfree(transfer);
- }
-
- return status;
-}
-
-static long
-spirom_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- int err = 0;
- int retval = 0;
- struct spirom_data *spirom;
- struct spi_device *spi;
- u32 tmp;
- struct spi_ioc_transfer *ioc;
-
- /* Check type and command number */
- if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC)
- return -ENOTTY;
-
- /* Check access direction once here; don't repeat below.
- * IOC_DIR is from the user perspective, while access_ok is
- * from the kernel perspective; so they look reversed.
- */
- if (_IOC_DIR(cmd) & _IOC_READ)
- err = !access_ok(VERIFY_WRITE,
- (void __user *)arg, _IOC_SIZE(cmd));
- if (err == 0 && _IOC_DIR(cmd) & _IOC_WRITE)
- err = !access_ok(VERIFY_READ,
- (void __user *)arg, _IOC_SIZE(cmd));
- if (err)
- return -EFAULT;
-
- /* guard against device removal before, or while,
- * we issue this ioctl.
- */
- spirom = filp->private_data;
- spin_lock_irq(&spirom->spi_lock);
- spi = spi_dev_get(spirom->spi);
- spin_unlock_irq(&spirom->spi_lock);
-
- if (spi == NULL)
- return -ESHUTDOWN;
-
- /* use the buffer lock here for triple duty:
- * - prevent I/O (from us) so calling spi_setup() is safe;
- * - prevent concurrent SPI_IOC_WR_* from morphing
- * data fields while SPI_IOC_RD_* reads them;
- * - SPI_IOC_MESSAGE needs the buffer locked "normally".
- */
- mutex_lock(&spirom->buf_lock);
-
- /* segmented and/or full-duplex I/O request */
- if (_IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) ||
- _IOC_DIR(cmd) !=_IOC_WRITE) {
- retval = -ENOTTY;
- goto out;
- }
-
- tmp = sizeof(struct spi_ioc_transfer);
-
- /* copy into scratch area */
- ioc = kzalloc(tmp, GFP_KERNEL);
- if (!ioc) {
- retval = -ENOMEM;
- goto out;
- }
- if (__copy_from_user(ioc, (struct spi_ioc_transfer __user *)arg,
- tmp)) {
- kfree(ioc);
- retval = -EFAULT;
- goto out;
- }
-
- /* translate to spi_message, execute */
- retval = spirom_message(spirom, ioc, arg);
- kfree(ioc);
-
-out:
- mutex_unlock(&spirom->buf_lock);
- spi_dev_put(spi);
- return retval;
-}
-
-static int spirom_open(struct inode *inode, struct file *filp)
-{
- struct spirom_data *spirom;
- int status = -ENXIO;
-
- mutex_lock(&device_list_lock);
-
- list_for_each_entry(spirom, &device_list, device_entry) {
- if (spirom->devt == inode->i_rdev) {
- status = 0;
- break;
- }
- }
- if (status == 0) {
- if (status == 0) {
- spirom->users++;
- filp->private_data = spirom;
- nonseekable_open(inode, filp);
- }
- } else
- pr_debug("spirom: nothing for minor %d\n", iminor(inode));
-
- mutex_unlock(&device_list_lock);
-
- /*
- * In case IMC is enabled, we need to inform IMC to stop
- * fetching code from the BIOS ROM. We will inform IMC when
- * it is safe to start fetching from ROM again once we are
- * done with our SPI transactions.
- */
- amd_imc_enter_scratch_ram();
-
- return status;
-}
-
-static int spirom_release(struct inode *inode, struct file *filp)
-{
- struct spirom_data *spirom;
- int status = 0;
-
- mutex_lock(&device_list_lock);
- spirom = filp->private_data;
- filp->private_data = NULL;
-
- /* last close? */
- spirom->users--;
- if (!spirom->users) {
- int dofree;
-
- /* ... after we unbound from the underlying device? */
- spin_lock_irq(&spirom->spi_lock);
- dofree = (spirom->spi == NULL);
- spin_unlock_irq(&spirom->spi_lock);
-
- if (dofree)
- kfree(spirom);
- }
- mutex_unlock(&device_list_lock);
-
- /*
- * In case IMC is enabled, we would have instructed IMC to stop
- * fetching from ROM BIOS earlier in the code path. Now that we
- * are done, we can safely inform IMC to start fetching from ROM
- * again.
- */
- amd_imc_exit_scratch_ram();
-
- return status;
-}
-
-static const struct file_operations spirom_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = spirom_ioctl,
- .open = spirom_open,
- .release = spirom_release,
-};
-
-static int __init add_spi_device_to_bus(void)
-{
- struct spi_master *spi_master;
- struct spi_board_info spi_info;
-
- spi_master = spi_busnum_to_master(SPI_BUS);
- if (!spi_master) {
- printk(KERN_ALERT "Please make sure to \'modprobe "
- "spi_amd\' driver first\n");
- return -1;
- }
- memset(&spi_info, 0, sizeof(struct spi_board_info));
-
- strlcpy(spi_info.modalias, "spirom", SPI_NAME_SIZE);
- spi_info.bus_num = SPI_BUS; //Bus number of SPI master
- spi_info.chip_select = SPI_BUS_CS1; //CS on which SPI device is connected
-
- spirom_device = spi_new_device(spi_master, &spi_info);
- if (!spirom_device)
- return -ENODEV;
-
- return 0;
-}
-
-static void remove_spi_device_from_bus(void)
-{
- if (spirom_device)
- spi_unregister_device(spirom_device);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* The main reason to have this class is to make mdev/udev create the
- * /dev/spiromB.C character device nodes exposing our userspace API.
- * It also simplifies memory management.
- */
-
-static struct class *spirom_class;
-
-/*-------------------------------------------------------------------------*/
-
-static int spirom_probe(struct spi_device *spi)
-{
- struct spirom_data *spirom;
- int status;
- unsigned long minor;
-
- /* Allocate driver data */
- spirom = kzalloc(sizeof(*spirom), GFP_KERNEL);
- if (!spirom)
- return -ENOMEM;
-
- /* Initialize the driver data */
- spirom->spi = spi;
- spin_lock_init(&spirom->spi_lock);
- mutex_init(&spirom->buf_lock);
-
- INIT_LIST_HEAD(&spirom->device_entry);
- init_completion(&spirom->done);
-
- /* If we can allocate a minor number, hook up this device.
- * Reusing minors is fine so long as udev or mdev is working.
- */
- mutex_lock(&device_list_lock);
- minor = find_first_zero_bit(minors, N_SPI_MINORS);
- if (minor < N_SPI_MINORS) {
- struct device *dev;
-
- spirom->devt = MKDEV(SPIROM_MAJOR, minor);
- dev = device_create(spirom_class, &spi->dev, spirom->devt,
- spirom, "spirom%d.%d",
- spi->master->bus_num, spi->chip_select);
- status = IS_ERR(dev) ? PTR_ERR(dev) : 0;
- } else {
- dev_dbg(&spi->dev, "no minor number available!\n");
- status = -ENODEV;
- }
- if (status == 0) {
- set_bit(minor, minors);
- list_add(&spirom->device_entry, &device_list);
- }
- mutex_unlock(&device_list_lock);
-
- if (status == 0)
- spi_set_drvdata(spi, spirom);
- else
- kfree(spirom);
-
- return status;
-}
-
-static int spirom_remove(struct spi_device *spi)
-{
- struct spirom_data *spirom = spi_get_drvdata(spi);
-
- /* make sure ops on existing fds can abort cleanly */
- spin_lock_irq(&spirom->spi_lock);
- spirom->spi = NULL;
- spi_set_drvdata(spi, NULL);
- spin_unlock_irq(&spirom->spi_lock);
-
- /* prevent new opens */
- mutex_lock(&device_list_lock);
- list_del(&spirom->device_entry);
- clear_bit(MINOR(spirom->devt), minors);
- device_destroy(spirom_class, spirom->devt);
- if (spirom->users == 0)
- kfree(spirom);
- mutex_unlock(&device_list_lock);
-
- return 0;
-}
-
-static struct spi_driver spirom_spi = {
- .driver = {
- .name = "spirom",
- .owner = THIS_MODULE,
- },
- .probe = spirom_probe,
- .remove = spirom_remove,
-
- /* NOTE: suspend/resume methods are not necessary here.
- * We don't do anything except pass the requests to/from
- * the underlying controller. The refrigerator handles
- * most issues; the controller driver handles the rest.
- */
-};
-
-/*-------------------------------------------------------------------------*/
-
-static int __init spirom_init(void)
-{
- int status;
-
- pr_info("AMD SPIROM Driver v%s\n", SPIROM_VERSION);
-
- /* Claim our 256 reserved device numbers. Then register a class
- * that will key udev/mdev to add/remove /dev nodes. Last, register
- * the driver which manages those device numbers.
- */
- BUILD_BUG_ON(N_SPI_MINORS > 256);
- status = register_chrdev(SPIROM_MAJOR, "spi", &spirom_fops);
- if (status < 0)
- return status;
-
- spirom_class = class_create(THIS_MODULE, "spirom");
- if (IS_ERR(spirom_class)) {
- unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
- return PTR_ERR(spirom_class);
- }
-
- status = spi_register_driver(&spirom_spi);
- if (status < 0) {
- class_destroy(spirom_class);
- unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
- }
-
- status = add_spi_device_to_bus();
- if (status < 0) {
- spi_unregister_driver(&spirom_spi);
- class_destroy(spirom_class);
- unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
- }
-
- return status;
-}
-module_init(spirom_init);
-
-static void __exit spirom_exit(void)
-{
- remove_spi_device_from_bus();
- spi_unregister_driver(&spirom_spi);
- class_destroy(spirom_class);
- unregister_chrdev(SPIROM_MAJOR, spirom_spi.driver.name);
-}
-module_exit(spirom_exit);
-
-MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
-MODULE_DESCRIPTION("User mode SPI ROM interface");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("spi:spirom");
diff --git a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h b/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h
deleted file mode 100644
index 941b357a..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-spi/files/spirom.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef SPIROM_H
-#define SPIROM_H
-
-#include <linux/types.h>
-
-/*---------------------------------------------------------------------------*/
-
-/* IOCTL commands */
-
-#define SPI_IOC_MAGIC 'k'
-
-#define TRANSMIT 1
-#define RECEIVE 2
-
-/*
- * struct spi_ioc_transfer - interface structure between application and ioctl
- *
- * @buf: Buffer to hold 1-byte command, 3-bytes address, and 64-byte data for
- * transmit or receive. The internal FIFO of our controller can hold a
- * maximum of 70 bytes, including the address. But here we assume the
- * maximum data excluding address to be 64-bytes long.
- *
- * @direction: Direction of data transfer, either TRANSMIT or RECEIVE.
- *
- * @len: Length of data excluding command and address.
- *
- * @addr_present: Flag to indicate whether 'buf' above contains an address.
- */
-struct spi_ioc_transfer {
- __u8 buf[64 + 1 + 3];
- __u8 direction;
- __u8 len;
- __u8 addr_present;
-};
-
-/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
-#define SPI_MSGSIZE(N) \
- ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
- ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
-#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
-
-/* SPI ROM command codes */
-#define ROM_WREN 0x06
-#define ROM_WRDI 0x04
-#define ROM_RDSR 0x05
-#define ROM_RDID 0x9F
-#define ROM_CHIP_ERASE 0x60
-#define ROM_SECTOR_ERASE 0x20
-#define ROM_BLOCK_ERASE 0xD8
-#define ROM_READ 0x03
-#define ROM_WRITE 0x02
-
-#endif /* SPIROM_H */
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/amd-wdt_1.0.bb b/meta-amdfalconx86/recipes-kernel/amd-wdt/amd-wdt_1.0.bb
deleted file mode 100644
index edaecf5a..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-wdt/amd-wdt_1.0.bb
+++ /dev/null
@@ -1,14 +0,0 @@
-DESCRIPTION = "This kernel module provides support for AMD Watchdog driver"
-LICENSE = "BSD | GPLv2"
-LIC_FILES_CHKSUM = "file://amd_wdt.c;endline=29;md5=8e7a9706367d146e5073510a6e176dc2"
-
-inherit module
-
-SRC_URI = "file://Makefile \
- file://amd_wdt.c \
- file://amd_wdt.h \
- "
-
-S = "${WORKDIR}"
-
-# The inherit of module.bbclass will take care of the rest
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile
deleted file mode 100644
index 36b32f87..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-obj-m := amd_wdt.o
-
-SRC := $(shell pwd)
-
-all:
- $(MAKE) -C $(KERNEL_SRC) M=$(SRC)
-
-modules_install:
- $(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
-
-clean:
- rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
- rm -f Module.markers Module.symvers modules.order
- rm -rf .tmp_versions Modules.symvers
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c
deleted file mode 100644
index 82329fe3..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.c
+++ /dev/null
@@ -1,418 +0,0 @@
-/*****************************************************************************
-*
-* Copyright (c) 2014, Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*
-***************************************************************************/
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-#include <linux/watchdog.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include "amd_wdt.h"
-
-/* internal variables */
-static u32 wdtbase_phys;
-static void __iomem *wdtbase;
-static DEFINE_SPINLOCK(wdt_lock);
-static struct pci_dev *amd_wdt_pci;
-
-/* watchdog platform device */
-static struct platform_device *amd_wdt_platform_device;
-
-/* module parameters */
-static int heartbeat = AMD_WDT_DEFAULT_TIMEOUT;
-module_param(heartbeat, int, 0);
-MODULE_PARM_DESC(heartbeat, "Watchdog timeout in frequency units. "
- "(default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
-
-static char frequency[MAX_LENGTH] = "1s";
-module_param_string(frequency, frequency, MAX_LENGTH, 0);
-MODULE_PARM_DESC(frequency, "Watchdog timer frequency units (32us, "
- "10ms, 100ms, 1s). (default=1s)");
-
-static bool nowayout = WATCHDOG_NOWAYOUT;
-module_param(nowayout, bool, 0);
-MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"
- " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-
-static char action[MAX_LENGTH] = "reboot";
-module_param_string(action, action, MAX_LENGTH, 0);
-MODULE_PARM_DESC(action, "Watchdog action (reboot/shutdown). (default=reboot) ");
-
-/*
- * Watchdog specific functions
- */
-static int amd_wdt_set_timeout(struct watchdog_device *wdt_dev, unsigned int t)
-{
- unsigned long flags;
-
- /*
- * In ideal cases the limits will be checked by Watchdog core itself,
- * but there might be cases when we call this function directly from
- * somewhere else. So check the limits here.
- */
- if (t < AMD_WDT_MIN_TIMEOUT)
- heartbeat = t = AMD_WDT_MIN_TIMEOUT;
- else if (t > AMD_WDT_MAX_TIMEOUT)
- heartbeat = t = AMD_WDT_MAX_TIMEOUT;
-
- /* Write new timeout value to watchdog */
- spin_lock_irqsave(&wdt_lock, flags);
- writel(t, AMD_WDT_COUNT(wdtbase));
- spin_unlock_irqrestore(&wdt_lock, flags);
-
- wdt_dev->timeout = t;
-
- return 0;
-}
-
-static int amd_wdt_ping(struct watchdog_device *wdt_dev)
-{
- u32 val;
- unsigned long flags;
-
- /* Trigger watchdog */
- spin_lock_irqsave(&wdt_lock, flags);
-
- val = readl(AMD_WDT_CONTROL(wdtbase));
- val |= AMD_WDT_TRIGGER_BIT;
- writel(val, AMD_WDT_CONTROL(wdtbase));
-
- spin_unlock_irqrestore(&wdt_lock, flags);
-
- return 0;
-}
-
-static int amd_wdt_start(struct watchdog_device *wdt_dev)
-{
- u32 val;
- unsigned long flags;
-
- /* Enable the watchdog timer */
- spin_lock_irqsave(&wdt_lock, flags);
-
- val = readl(AMD_WDT_CONTROL(wdtbase));
- val |= AMD_WDT_START_STOP_BIT;
- writel(val, AMD_WDT_CONTROL(wdtbase));
-
- spin_unlock_irqrestore(&wdt_lock, flags);
-
- /* Trigger the watchdog timer */
- amd_wdt_ping(wdt_dev);
-
- return 0;
-}
-
-static int amd_wdt_stop(struct watchdog_device *wdt_dev)
-{
- u32 val;
- unsigned long flags;
-
- /* Disable the watchdog timer */
- spin_lock_irqsave(&wdt_lock, flags);
-
- val = readl(AMD_WDT_CONTROL(wdtbase));
- val &= ~AMD_WDT_START_STOP_BIT;
- writel(val, AMD_WDT_CONTROL(wdtbase));
-
- spin_unlock_irqrestore(&wdt_lock, flags);
-
- return 0;
-}
-
-static unsigned int amd_wdt_get_timeleft(struct watchdog_device *wdt_dev)
-{
- u32 val;
- unsigned long flags;
-
- spin_lock_irqsave(&wdt_lock, flags);
- val = readl(AMD_WDT_COUNT(wdtbase));
- spin_unlock_irqrestore(&wdt_lock, flags);
-
- /* Mask out the upper 16-bits and return */
- return val & AMD_WDT_COUNT_MASK;
-}
-
-static unsigned int amd_wdt_status(struct watchdog_device *wdt_dev)
-{
- return wdt_dev->status;
-}
-
-static struct watchdog_ops amd_wdt_ops = {
- .owner = THIS_MODULE,
- .start = amd_wdt_start,
- .stop = amd_wdt_stop,
- .ping = amd_wdt_ping,
- .status = amd_wdt_status,
- .set_timeout = amd_wdt_set_timeout,
- .get_timeleft = amd_wdt_get_timeleft,
-};
-static struct watchdog_info amd_wdt_info = {
- .options = WDIOF_SETTIMEOUT |
- WDIOF_MAGICCLOSE |
- WDIOF_KEEPALIVEPING,
- .firmware_version = 0,
- .identity = WDT_MODULE_NAME,
-};
-
-static struct watchdog_device amd_wdt_dev = {
- .info = &amd_wdt_info,
- .ops = &amd_wdt_ops,
-};
-
-/*
- * The PCI Device ID table below is used to identify the platform
- * the driver is supposed to work for. Since this is a platform
- * device, we need a way for us to be able to find the correct
- * platform when the driver gets loaded, otherwise we should
- * bail out.
- */
-static DEFINE_PCI_DEVICE_TABLE(amd_wdt_pci_tbl) = {
- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CARRIZO_SMBUS, PCI_ANY_ID,
- PCI_ANY_ID, },
- { 0, },
-};
-MODULE_DEVICE_TABLE(pci, amd_wdt_pci_tbl);
-
-static unsigned char amd_wdt_setupdevice(void)
-{
- struct pci_dev *dev = NULL;
- u32 val;
-
- /* Match the PCI device */
- for_each_pci_dev(dev) {
- if (pci_match_id(amd_wdt_pci_tbl, dev) != NULL) {
- amd_wdt_pci = dev;
- break;
- }
- }
-
- if (!amd_wdt_pci)
- return 0;
-
- /* Watchdog Base Address starts from ACPI MMIO Base Address + 0xB00 */
- wdtbase_phys = AMD_ACPI_MMIO_BASE + AMD_WDT_MEM_MAP_OFFSET;
- if (!request_mem_region_exclusive(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE,
- "AMD Watchdog")) {
- pr_err("mmio address 0x%04x already in use\n", wdtbase_phys);
- goto exit;
- }
-
- wdtbase = ioremap(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
- if (!wdtbase) {
- pr_err("failed to get wdtbase address\n");
- goto unreg_mem_region;
- }
-
- /* Enable watchdog timer and decode bit */
- outb(AMD_PM_WATCHDOG_EN_REG, AMD_IO_PM_INDEX_REG);
- val = inb(AMD_IO_PM_DATA_REG);
- val |= AMD_PM_WATCHDOG_TIMER_EN;
- outb(val, AMD_IO_PM_DATA_REG);
-
- /* Set the watchdog timer resolution */
- outb(AMD_PM_WATCHDOG_CONFIG_REG, AMD_IO_PM_INDEX_REG);
- val = inb(AMD_IO_PM_DATA_REG);
- /* Clear the previous frequency setting, if any */
- val &= ~AMD_PM_WATCHDOG_CONFIG_MASK;
-
- /*
- * Now set the frequency depending on the module load parameter.
- * In case the user passes an invalid argument, we consider the
- * frequency to be of 1 second resolution.
- */
- if (strncmp(frequency, "32us", 4) == 0)
- val |= AMD_PM_WATCHDOG_32USEC_RES;
- else if (strncmp(frequency, "10ms", 4) == 0)
- val |= AMD_PM_WATCHDOG_10MSEC_RES;
- else if (strncmp(frequency, "100ms", 5) == 0)
- val |= AMD_PM_WATCHDOG_100MSEC_RES;
- else {
- val |= AMD_PM_WATCHDOG_1SEC_RES;
- if (strncmp(frequency, "1s", 2) != 0)
- strncpy(frequency, "1s", 2);
- }
-
- outb(val, AMD_IO_PM_DATA_REG);
-
- /* Check to see if last reboot was due to watchdog timeout */
- val = readl(AMD_WDT_CONTROL(wdtbase));
- if (val & AMD_WDT_FIRED_BIT)
- amd_wdt_dev.bootstatus |= WDIOF_CARDRESET;
- else
- amd_wdt_dev.bootstatus &= ~WDIOF_CARDRESET;
-
- pr_info("Watchdog reboot %sdetected\n",
- (val & AMD_WDT_FIRED_BIT) ? "" : "not ");
-
- /* Clear out the old status */
- val |= AMD_WDT_FIRED_BIT;
-
- /*
- * Set the watchdog action depending on module load parameter.
- *
- * If action is specified anything other than reboot or shutdown,
- * we default it to reboot.
- */
- if (strncmp(action, "shutdown", 8) == 0)
- val |= AMD_WDT_ACTION_RESET_BIT;
- else {
- val &= ~AMD_WDT_ACTION_RESET_BIT;
- /* The statement below is required for when the action
- * is set anything other than reboot.
- */
- if (strncmp(action, "reboot", 6) != 0)
- strncpy(action, "reboot", 6);
- }
-
- writel(val, AMD_WDT_CONTROL(wdtbase));
-
- return 1;
-
-unreg_mem_region:
- release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
-exit:
- return 0;
-}
-
-static int amd_wdt_init(struct platform_device *dev)
-{
- int ret;
- u32 val;
-
- /* Identify our device and initialize watchdog hardware */
- if (!amd_wdt_setupdevice())
- return -ENODEV;
-
- amd_wdt_dev.timeout = heartbeat;
- amd_wdt_dev.min_timeout = AMD_WDT_MIN_TIMEOUT;
- amd_wdt_dev.max_timeout = AMD_WDT_MAX_TIMEOUT;
- watchdog_set_nowayout(&amd_wdt_dev, nowayout);
-
- /* Make sure watchdog is not running */
- amd_wdt_stop(&amd_wdt_dev);
-
- /* Set Watchdog timeout */
- amd_wdt_set_timeout(&amd_wdt_dev, heartbeat);
-
- ret = watchdog_register_device(&amd_wdt_dev);
- if (ret != 0) {
- pr_err("Watchdog timer: cannot register watchdog device"
- " (err=%d)\n", ret);
- goto exit;
- }
-
- pr_info("initialized (0x%p). (timeout=%d units) (frequency=%s) "
- "(nowayout=%d) (action=%s)\n", wdtbase, heartbeat, frequency,
- nowayout, action);
-
- return 0;
-
-exit:
- iounmap(wdtbase);
- release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
- return ret;
-}
-
-static void amd_wdt_cleanup(void)
-{
- /* Stop the timer before we leave */
- if (!nowayout)
- amd_wdt_stop(NULL);
-
- watchdog_unregister_device(&amd_wdt_dev);
- iounmap(wdtbase);
- release_mem_region(wdtbase_phys, AMD_WDT_MEM_MAP_SIZE);
-}
-
-static int amd_wdt_remove(struct platform_device *dev)
-{
- if (wdtbase)
- amd_wdt_cleanup();
-
- return 0;
-}
-
-static void amd_wdt_shutdown(struct platform_device *dev)
-{
- amd_wdt_stop(NULL);
-}
-
-static struct platform_driver amd_wdt_driver = {
- .probe = amd_wdt_init,
- .remove = amd_wdt_remove,
- .shutdown = amd_wdt_shutdown,
- .driver = {
- .owner = THIS_MODULE,
- .name = WDT_MODULE_NAME,
- },
-};
-
-static int __init amd_wdt_init_module(void)
-{
- int err;
-
- pr_info("AMD WatchDog Timer Driver v%s\n", WDT_VERSION);
-
- err = platform_driver_register(&amd_wdt_driver);
- if (err)
- return err;
-
- amd_wdt_platform_device = platform_device_register_simple(
- WDT_MODULE_NAME, -1, NULL, 0);
- if (IS_ERR(amd_wdt_platform_device)) {
- err = PTR_ERR(amd_wdt_platform_device);
- goto unreg_platform_driver;
- }
-
- return 0;
-
-unreg_platform_driver:
- platform_driver_unregister(&amd_wdt_driver);
- return err;
-}
-
-static void __exit amd_wdt_cleanup_module(void)
-{
- platform_device_unregister(amd_wdt_platform_device);
- platform_driver_unregister(&amd_wdt_driver);
- pr_info("AMD Watchdog Module Unloaded\n");
-}
-
-module_init(amd_wdt_init_module);
-module_exit(amd_wdt_cleanup_module);
-
-MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
-MODULE_DESCRIPTION("Watchdog timer driver for AMD chipsets");
-MODULE_LICENSE("Dual BSD/GPL");
diff --git a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h b/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h
deleted file mode 100644
index 855e6810..00000000
--- a/meta-amdfalconx86/recipes-kernel/amd-wdt/files/amd_wdt.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef _AMD_WDT_H_
-#define _AMD_WDT_H_
-
-/* Module and version information */
-#define WDT_VERSION "1.0"
-#define WDT_MODULE_NAME "AMD watchdog timer"
-#define WDT_DRIVER_NAME WDT_MODULE_NAME ", v" WDT_VERSION
-
-#define AMD_WDT_DEFAULT_TIMEOUT 60 /* 60 units default heartbeat. */
-#define AMD_WDT_MIN_TIMEOUT 0x0001 /* minimum timeout value */
-#define AMD_WDT_MAX_TIMEOUT 0xFFFF /* maximum timeout value */
-#define MAX_LENGTH (8 + 1) /* shutdown has 8 characters + NULL character */
-
-/* Watchdog register definitions */
-#define AMD_ACPI_MMIO_BASE 0xFED80000
-#define AMD_WDT_MEM_MAP_OFFSET 0xB00
-#define AMD_WDT_MEM_MAP_SIZE 0x100
-
-#define AMD_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
- #define AMD_WDT_START_STOP_BIT (1 << 0)
- #define AMD_WDT_FIRED_BIT (1 << 1)
- #define AMD_WDT_ACTION_RESET_BIT (1 << 2)
- #define AMD_WDT_DISABLE_BIT (1 << 3)
- /* 6:4 bits Reserved */
- #define AMD_WDT_TRIGGER_BIT (1 << 7)
-#define AMD_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
- #define AMD_WDT_COUNT_MASK 0xFFFF
-
-#define AMD_PM_WATCHDOG_EN_REG 0x00
- #define AMD_PM_WATCHDOG_TIMER_EN (0x01 << 7)
-
-#define AMD_PM_WATCHDOG_CONFIG_REG 0x03
- #define AMD_PM_WATCHDOG_32USEC_RES 0x0
- #define AMD_PM_WATCHDOG_10MSEC_RES 0x1
- #define AMD_PM_WATCHDOG_100MSEC_RES 0x2
- #define AMD_PM_WATCHDOG_1SEC_RES 0x3
-#define AMD_PM_WATCHDOG_CONFIG_MASK 0x3
-
-/* IO port address for indirect access using ACPI PM registers */
-#define AMD_IO_PM_INDEX_REG 0xCD6
-#define AMD_IO_PM_DATA_REG 0xCD7
-
-#define AMD_ACPI_MMIO_ADDR_MASK ~0x1FFF
-#define PCI_DEVICE_ID_AMD_CARRIZO_SMBUS 0x790B
-
-#endif /* _AMD_WDT_H_ */
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb
deleted file mode 100644
index 1d4ea646..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware.bb
+++ /dev/null
@@ -1,43 +0,0 @@
-DESCRIPTION = "These binaries provide kernel support for newer AMD GPUs"
-SECTION = "kernel"
-LICENSE = "Firmware-amd"
-
-SRC_URI = "file://carrizo_ce.bin \
- file://carrizo_me.bin \
- file://carrizo_mec2.bin \
- file://carrizo_mec.bin \
- file://carrizo_pfp.bin \
- file://carrizo_rlc.bin \
- file://carrizo_sdma1.bin \
- file://carrizo_sdma.bin \
- file://carrizo_uvd.bin \
- file://carrizo_vce.bin \
- file://stoney_ce.bin \
- file://stoney_me.bin \
- file://stoney_mec.bin \
- file://stoney_pfp.bin \
- file://stoney_rlc.bin \
- file://stoney_sdma.bin \
- file://stoney_uvd.bin \
- file://stoney_vce.bin \
- file://LICENSE \
- "
-
-LIC_FILES_CHKSUM = "file://LICENSE;md5=07b0c31777bd686d8e1609c6940b5e74"
-
-S = "${WORKDIR}"
-
-# Since, no binaries are generated for a specific target,
-# inherit allarch to simply populate prebuilt binaries
-inherit allarch
-
-do_compile() {
- :
-}
-
-do_install() {
- install -v -m 444 -D ${S}/LICENSE ${D}/lib/firmware/amdgpu/LICENSE
- install -v -m 0644 ${S}/*.bin ${D}/lib/firmware/amdgpu
-}
-
-FILES_${PN} = "/lib/firmware/*"
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE
deleted file mode 100644
index fe3780b3..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/LICENSE
+++ /dev/null
@@ -1,51 +0,0 @@
-Copyright (C) 2009-2014 Advanced Micro Devices, Inc. All rights reserved.
-
-REDISTRIBUTION: Permission is hereby granted, free of any license fees,
-to any person obtaining a copy of this microcode (the "Software"), to
-install, reproduce, copy and distribute copies, in binary form only, of
-the Software and to permit persons to whom the Software is provided to
-do the same, provided that the following conditions are met:
-
-No reverse engineering, decompilation, or disassembly of this Software
-is permitted.
-
-Redistributions must reproduce the above copyright notice, this
-permission notice, and the following disclaimers and notices in the
-Software documentation and/or other materials provided with the
-Software.
-
-DISCLAIMER: THE USE OF THE SOFTWARE IS AT YOUR SOLE RISK. THE SOFTWARE
-IS PROVIDED "AS IS" AND WITHOUT WARRANTY OF ANY KIND AND COPYRIGHT
-HOLDER AND ITS LICENSORS EXPRESSLY DISCLAIM ALL WARRANTIES, EXPRESS AND
-IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
-COPYRIGHT HOLDER AND ITS LICENSORS DO NOT WARRANT THAT THE SOFTWARE WILL
-MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THE SOFTWARE WILL BE
-UNINTERRUPTED OR ERROR-FREE. THE ENTIRE RISK ASSOCIATED WITH THE USE OF
-THE SOFTWARE IS ASSUMED BY YOU. FURTHERMORE, COPYRIGHT HOLDER AND ITS
-LICENSORS DO NOT WARRANT OR MAKE ANY REPRESENTATIONS REGARDING THE USE
-OR THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
-ACCURACY, RELIABILITY, CURRENTNESS, OR OTHERWISE.
-
-DISCLAIMER: UNDER NO CIRCUMSTANCES INCLUDING NEGLIGENCE, SHALL COPYRIGHT
-HOLDER AND ITS LICENSORS OR ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS
-("AUTHORIZED REPRESENTATIVES") BE LIABLE FOR ANY INCIDENTAL, INDIRECT,
-SPECIAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF BUSINESS
-PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, AND THE
-LIKE) ARISING OUT OF THE USE, MISUSE OR INABILITY TO USE THE SOFTWARE,
-BREACH OR DEFAULT, INCLUDING THOSE ARISING FROM INFRINGEMENT OR ALLEGED
-INFRINGEMENT OF ANY PATENT, TRADEMARK, COPYRIGHT OR OTHER INTELLECTUAL
-PROPERTY RIGHT EVEN IF COPYRIGHT HOLDER AND ITS AUTHORIZED
-REPRESENTATIVES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN
-NO EVENT SHALL COPYRIGHT HOLDER OR ITS AUTHORIZED REPRESENTATIVES TOTAL
-LIABILITY FOR ALL DAMAGES, LOSSES, AND CAUSES OF ACTION (WHETHER IN
-CONTRACT, TORT (INCLUDING NEGLIGENCE) OR OTHERWISE) EXCEED THE AMOUNT OF
-US$10.
-
-Notice: The Software is subject to United States export laws and
-regulations. You agree to comply with all domestic and international
-export laws and regulations that apply to the Software, including but
-not limited to the Export Administration Regulations administered by the
-U.S. Department of Commerce and International Traffic in Arm Regulations
-administered by the U.S. Department of State. These laws include
-restrictions on destinations, end users and end use.
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin
deleted file mode 100644
index 6153fcb7..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_ce.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin
deleted file mode 100644
index 57a9f8a1..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_me.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin
deleted file mode 100644
index a5f3a2e4..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec2.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec2.bin
deleted file mode 100644
index c467fc91..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_mec2.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_pfp.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_pfp.bin
deleted file mode 100644
index ad3c549c..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_pfp.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_rlc.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_rlc.bin
deleted file mode 100644
index b1deb84c..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_rlc.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma.bin
deleted file mode 100644
index 5c4be064..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma1.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma1.bin
deleted file mode 100644
index 5c4be064..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_sdma1.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_uvd.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_uvd.bin
deleted file mode 100644
index 8f7f2f54..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_uvd.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_vce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_vce.bin
deleted file mode 100644
index 1631fb1e..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/carrizo_vce.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_ce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_ce.bin
deleted file mode 100644
index 5e35ccd9..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_ce.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_me.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_me.bin
deleted file mode 100644
index 775b752c..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_me.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_mec.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_mec.bin
deleted file mode 100644
index bdec08f0..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_mec.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_pfp.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_pfp.bin
deleted file mode 100644
index 84b5b0fb..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_pfp.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_rlc.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_rlc.bin
deleted file mode 100644
index 7002e730..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_rlc.bin
+++ /dev/null
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diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_sdma.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_sdma.bin
deleted file mode 100644
index 95663d69..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_sdma.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_uvd.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_uvd.bin
deleted file mode 100644
index 3fe546de..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_uvd.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_vce.bin b/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_vce.bin
deleted file mode 100644
index ff54327c..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux-firmware/amdgpu-firmware/stoney_vce.bin
+++ /dev/null
Binary files differ
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch
deleted file mode 100644
index 506f127f..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux/files/0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch
+++ /dev/null
@@ -1,158 +0,0 @@
-From 195d9672a2766fca3c0495884e2ef6a4f133ebb7 Mon Sep 17 00:00:00 2001
-From: Ahsan Hussain <ahsan_hussain@mentor.com>
-Date: Wed, 19 Apr 2017 21:01:50 +0500
-Subject: [PATCH] [PATCH] amdgpu: get maximum and used UVD handles
-
-Change History
---------------
-
-v4: Changes suggested by Emil, Christian
-- return -ENODATA for asics with unlimited sessions
-
-v3: changes suggested by Christian
-- Add a check for UVD IP block using AMDGPU_HW_IP_UVD
- query type.
-- Add a check for asic_type to be less than
- CHIP_POLARIS10 since starting Polaris, we support
- unlimited UVD instances.
-- Add kerneldoc style comment for
- amdgpu_uvd_used_handles().
-
-v2: as suggested by Christian
-- Add a new query AMDGPU_INFO_NUM_HANDLES
-- Create a helper function to return the number
- of currently used UVD handles.
-- Modify the logic to count the number of used
- UVD handles since handles can be freed in
- non-linear fashion.
-
-v1:
-- User might want to query the maximum number of UVD
- instances supported by firmware. In addition to that,
- if there are multiple applications using UVD handles
- at the same time, he might also want to query the
- currently used number of handles.
-
- For this we add two variables max_handles and
- used_handles inside drm_amdgpu_info_hw_ip. So now
- an application (or libdrm) can use AMDGPU_INFO IOCTL
- with AMDGPU_INFO_HW_IP_INFO query type to get these
- values.
-
-Signed-off-by: Ahsan Hussain <ahsan_hussain@mentor.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 21 +++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 25 +++++++++++++++++++++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 +
- drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 9 ++++++++
- 4 files changed, 56 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-index a48783e50..e7ab49d49 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
-@@ -505,6 +505,27 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
- return copy_to_user(out, &dev_info,
- min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
- }
-+ case AMDGPU_INFO_NUM_HANDLES: {
-+ struct drm_amdgpu_info_num_handles handle;
-+
-+ switch (info->query_hw_ip.type) {
-+ case AMDGPU_HW_IP_UVD:
-+ /* Starting Polaris, we support unlimited UVD handles */
-+ if (adev->asic_type < CHIP_POLARIS10) {
-+ handle.uvd_max_handles = adev->uvd.max_handles;
-+ handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
-+
-+ return copy_to_user(out, &handle,
-+ min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
-+ } else {
-+ return -ENODATA;
-+ }
-+
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ }
- default:
- DRM_DEBUG_KMS("Invalid request %d\n", info->query);
- return -EINVAL;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-index 849c7959c..20960e82a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
-@@ -940,6 +940,31 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
- return 0;
- }
-
-+/**
-+ * amdgpu_uvd_used_handles - returns used UVD handles
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Returns the number of UVD handles in use
-+ */
-+uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
-+{
-+ unsigned i;
-+ uint32_t used_handles = 0;
-+
-+ for (i = 0; i < adev->uvd.max_handles; ++i) {
-+ /*
-+ * Handles can be freed in any order, and not
-+ * necessarily linear. So we need to count
-+ * all non-zero handles.
-+ */
-+ if (atomic_read(&adev->uvd.handles[i]))
-+ used_handles++;
-+ }
-+
-+ return used_handles;
-+}
-+
- static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
- bool direct, struct fence **fence)
- {
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
-index 9a3b44908..19250d69d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
-@@ -35,5 +35,6 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- void amdgpu_uvd_free_handles(struct amdgpu_device *adev,
- struct drm_file *filp);
- int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx);
-+uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev);
-
- #endif
-diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h
-index c2f06eba3..c4f903d61 100644
---- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h
-+++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h
-@@ -549,6 +549,8 @@ struct drm_amdgpu_cs_chunk_data {
- #define AMDGPU_INFO_CAPABILITY 0x50
- /* query pin memory capability */
- #define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0)
-+/* Query UVD handles */
-+#define AMDGPU_INFO_NUM_HANDLES 0x1C
-
- #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
- #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
-@@ -710,6 +712,13 @@ struct drm_amdgpu_info_hw_ip {
- __u32 _pad;
- };
-
-+struct drm_amdgpu_info_num_handles {
-+ /** Max handles as supported by firmware for UVD */
-+ __u32 uvd_max_handles;
-+ /** Handles currently in use for UVD */
-+ __u32 uvd_used_handles;
-+};
-+
- struct drm_amdgpu_heap_info {
- /** max. physical memory */
- __u64 total_heap_size;
---
-2.11.1
-
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch
deleted file mode 100644
index 91aa2bb5..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 480e54e78f3df2bbc21f7977d3f55dc5aef5317e Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Wed, 13 Jul 2016 15:18:23 -0700
-Subject: [PATCH] amdgpu: fix various compilation issues
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
-Signed-off-by: Drew Moseley <drew_moseley@mentor.com>
----
- drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 2 +-
- drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 1 -
- 2 files changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-index f39499a..e995f9b 100644
---- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
-@@ -3181,7 +3181,7 @@ static void calculate_bandwidth(
- bw_int_to_fixed(
- 2),
- vbios->mcifwrmc_urgent_latency),
-- results->dmif_burst_time[i][j]),
-+ results->dmif_burst_time[results->y_clk_level][results->sclk_level]),
- results->mcifwr_burst_time[results->y_clk_level][results->sclk_level])),
- results->dispclk),
- bw_int_to_fixed(
-diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-index 698a34e..13a1449 100644
---- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
-@@ -41,7 +41,6 @@
- #define CV_SMART_DONGLE_ADDRESS 0x20
- /* DVI-HDMI dongle slave address for retrieving dongle signature*/
- #define DVI_HDMI_DONGLE_ADDRESS 0x68
--static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
- struct dvi_hdmi_dongle_signature_data {
- int8_t vendor[3];/* "AMD" */
- uint8_t version[2];
---
-2.9.1
-
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-ethernet-integrate-r8168-driver.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-ethernet-integrate-r8168-driver.patch
deleted file mode 100644
index 78a33e47..00000000
--- a/meta-amdfalconx86/recipes-kernel/linux/files/0001-ethernet-integrate-r8168-driver.patch
+++ /dev/null
@@ -1,28740 +0,0 @@
-From 1a424d423823ae97080922348408e2377eaaca76 Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Fri, 28 Aug 2015 15:08:31 +0500
-Subject: [PATCH] ethernet: integrate r8168 driver
-
-The NIC on AMD Falcon x86 family requires the r8168 driver
-to function properly otherwise conflicts with the on-board
-DASH controller are observed which results in a failure
-to bring up the ethernet interface.
-
-Signed-off-by: Awais Belal <awais_belal@mentor.com>
----
- drivers/net/ethernet/realtek/Kconfig | 9 +
- drivers/net/ethernet/realtek/Makefile | 3 +
- drivers/net/ethernet/realtek/r8168.h | 1524 ++
- drivers/net/ethernet/realtek/r8168_asf.c | 419 +
- drivers/net/ethernet/realtek/r8168_asf.h | 294 +
- drivers/net/ethernet/realtek/r8168_dash.h | 193 +
- drivers/net/ethernet/realtek/r8168_n.c | 25364 +++++++++++++++++++++++++
- drivers/net/ethernet/realtek/r8168_realwow.h | 117 +
- drivers/net/ethernet/realtek/rtl_eeprom.c | 291 +
- drivers/net/ethernet/realtek/rtl_eeprom.h | 55 +
- drivers/net/ethernet/realtek/rtltool.c | 304 +
- drivers/net/ethernet/realtek/rtltool.h | 49 +
- 12 files changed, 28622 insertions(+)
- create mode 100755 drivers/net/ethernet/realtek/r8168.h
- create mode 100755 drivers/net/ethernet/realtek/r8168_asf.c
- create mode 100755 drivers/net/ethernet/realtek/r8168_asf.h
- create mode 100755 drivers/net/ethernet/realtek/r8168_dash.h
- create mode 100755 drivers/net/ethernet/realtek/r8168_n.c
- create mode 100755 drivers/net/ethernet/realtek/r8168_realwow.h
- create mode 100755 drivers/net/ethernet/realtek/rtl_eeprom.c
- create mode 100755 drivers/net/ethernet/realtek/rtl_eeprom.h
- create mode 100755 drivers/net/ethernet/realtek/rtltool.c
- create mode 100755 drivers/net/ethernet/realtek/rtltool.h
-
-diff --git a/drivers/net/ethernet/realtek/Kconfig b/drivers/net/ethernet/realtek/Kconfig
-index ae5d027..54667fb 100644
---- a/drivers/net/ethernet/realtek/Kconfig
-+++ b/drivers/net/ethernet/realtek/Kconfig
-@@ -112,4 +112,13 @@ config R8169
- To compile this driver as a module, choose M here: the module
- will be called r8169. This is recommended.
-
-+config R8168
-+ tristate "Realtek 8168 gigabit ethernet support"
-+ depends on PCI
-+ ---help---
-+ Say Y here if you have a Realtek 8168 PCI Gigabit Ethernet adapter.
-+
-+ To compile this driver as a module, choose M here: the module
-+ will be called r8168. This is recommended.
-+
- endif # NET_VENDOR_REALTEK
-diff --git a/drivers/net/ethernet/realtek/Makefile b/drivers/net/ethernet/realtek/Makefile
-index 71b1da3..2de09ca 100644
---- a/drivers/net/ethernet/realtek/Makefile
-+++ b/drivers/net/ethernet/realtek/Makefile
-@@ -6,3 +6,6 @@ obj-$(CONFIG_8139CP) += 8139cp.o
- obj-$(CONFIG_8139TOO) += 8139too.o
- obj-$(CONFIG_ATP) += atp.o
- obj-$(CONFIG_R8169) += r8169.o
-+
-+r8168-y += r8168_n.o r8168_asf.o rtl_eeprom.o rtltool.o
-+obj-$(CONFIG_R8168) += r8168.o
-diff --git a/drivers/net/ethernet/realtek/r8168.h b/drivers/net/ethernet/realtek/r8168.h
-new file mode 100755
-index 0000000..95dec0e
---- /dev/null
-+++ b/drivers/net/ethernet/realtek/r8168.h
-@@ -0,0 +1,1524 @@
-+/*
-+################################################################################
-+#
-+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
-+# controllers with PCI-Express interface.
-+#
-+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved.
-+#
-+# This program is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by the Free
-+# Software Foundation; either version 2 of the License, or (at your option)
-+# any later version.
-+#
-+# This program is distributed in the hope that it will be useful, but WITHOUT
-+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+# more details.
-+#
-+# You should have received a copy of the GNU General Public License along with
-+# this program; if not, see <http://www.gnu.org/licenses/>.
-+#
-+# Author:
-+# Realtek NIC software team <nicfae@realtek.com>
-+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
-+#
-+################################################################################
-+*/
-+
-+/************************************************************************************
-+ * This product is covered by one or more of the following patents:
-+ * US6,570,884, US6,115,776, and US6,327,625.
-+ ***********************************************************************************/
-+
-+#include "r8168_dash.h"
-+#include "r8168_realwow.h"
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37)
-+#define ENABLE_R8168_PROCFS
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+#define NETIF_F_HW_VLAN_RX NETIF_F_HW_VLAN_CTAG_RX
-+#define NETIF_F_HW_VLAN_TX NETIF_F_HW_VLAN_CTAG_TX
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)
-+#define __devinit
-+#define __devexit
-+#define __devexit_p(func) func
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
-+#define CHECKSUM_PARTIAL CHECKSUM_HW
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-+#define irqreturn_t void
-+#define IRQ_HANDLED 1
-+#define IRQ_NONE 0
-+#define IRQ_RETVAL(x)
-+#endif
-+
-+#ifndef HAVE_FREE_NETDEV
-+#define free_netdev(x) kfree(x)
-+#endif
-+
-+#ifndef SET_NETDEV_DEV
-+#define SET_NETDEV_DEV(net, pdev)
-+#endif
-+
-+#ifndef SET_MODULE_OWNER
-+#define SET_MODULE_OWNER(dev)
-+#endif
-+
-+#ifndef SA_SHIRQ
-+#define SA_SHIRQ IRQF_SHARED
-+#endif
-+
-+#ifndef NETIF_F_GSO
-+#define gso_size tso_size
-+#define gso_segs tso_segs
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
-+#ifdef CONFIG_NET_POLL_CONTROLLER
-+#define RTL_NET_POLL_CONTROLLER dev->poll_controller=rtl8168_netpoll
-+#else
-+#define RTL_NET_POLL_CONTROLLER
-+#endif
-+
-+#ifdef CONFIG_R8168_VLAN
-+#define RTL_SET_VLAN dev->vlan_rx_register=rtl8168_vlan_rx_register
-+#else
-+#define RTL_SET_VLAN
-+#endif
-+
-+#define RTL_NET_DEVICE_OPS(ops) dev->open=rtl8168_open; \
-+ dev->hard_start_xmit=rtl8168_start_xmit; \
-+ dev->get_stats=rtl8168_get_stats; \
-+ dev->stop=rtl8168_close; \
-+ dev->tx_timeout=rtl8168_tx_timeout; \
-+ dev->set_multicast_list=rtl8168_set_rx_mode; \
-+ dev->change_mtu=rtl8168_change_mtu; \
-+ dev->set_mac_address=rtl8168_set_mac_address; \
-+ dev->do_ioctl=rtl8168_do_ioctl; \
-+ RTL_NET_POLL_CONTROLLER; \
-+ RTL_SET_VLAN;
-+#else
-+#define RTL_NET_DEVICE_OPS(ops) dev->netdev_ops=&ops
-+#endif
-+
-+#ifndef FALSE
-+#define FALSE 0
-+#endif
-+
-+#ifndef TRUE
-+#define TRUE 1
-+#endif
-+
-+#ifndef false
-+#define false 0
-+#endif
-+
-+#ifndef true
-+#define true 1
-+#endif
-+
-+//Hardware will continue interrupt 10 times after interrupt finished.
-+#define RTK_KEEP_INTERRUPT_COUNT (10)
-+
-+//Due to the hardware design of RTL8111B, the low 32 bit address of receive
-+//buffer must be 8-byte alignment.
-+#ifndef NET_IP_ALIGN
-+#define NET_IP_ALIGN 2
-+#endif
-+#define RTK_RX_ALIGN 8
-+
-+#ifdef CONFIG_R8168_NAPI
-+#define NAPI_SUFFIX "-NAPI"
-+#else
-+#define NAPI_SUFFIX ""
-+#endif
-+
-+#define RTL8168_VERSION "8.040.00" NAPI_SUFFIX
-+#define MODULENAME "r8168"
-+#define PFX MODULENAME ": "
-+
-+#define GPL_CLAIM "\
-+r8168 Copyright (C) 2015 Realtek NIC software team <nicfae@realtek.com> \n \
-+This program comes with ABSOLUTELY NO WARRANTY; for details, please see <http://www.gnu.org/licenses/>. \n \
-+This is free software, and you are welcome to redistribute it under certain conditions; see <http://www.gnu.org/licenses/>. \n"
-+
-+#ifdef RTL8168_DEBUG
-+#define assert(expr) \
-+ if(!(expr)) { \
-+ printk( "Assertion failed! %s,%s,%s,line=%d\n", \
-+ #expr,__FILE__,__FUNCTION__,__LINE__); \
-+ }
-+#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
-+#else
-+#define assert(expr) do {} while (0)
-+#define dprintk(fmt, args...) do {} while (0)
-+#endif /* RTL8168_DEBUG */
-+
-+#define R8168_MSG_DEFAULT \
-+ (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
-+
-+#define TX_BUFFS_AVAIL(tp) \
-+ (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
-+
-+#ifdef CONFIG_R8168_NAPI
-+#define rtl8168_rx_hwaccel_skb vlan_hwaccel_receive_skb
-+#define rtl8168_rx_quota(count, quota) min(count, quota)
-+#else
-+#define rtl8168_rx_hwaccel_skb vlan_hwaccel_rx
-+#define rtl8168_rx_quota(count, quota) count
-+#endif
-+
-+/* MAC address length */
-+#ifndef MAC_ADDR_LEN
-+#define MAC_ADDR_LEN 6
-+#endif
-+
-+#ifndef MAC_PROTOCOL_LEN
-+#define MAC_PROTOCOL_LEN 2
-+#endif
-+
-+#define Reserved2_data 7
-+#define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
-+#define TX_DMA_BURST_unlimited 7
-+#define TX_DMA_BURST_1024 6
-+#define TX_DMA_BURST_512 5
-+#define TX_DMA_BURST_256 4
-+#define TX_DMA_BURST_128 3
-+#define TX_DMA_BURST_64 2
-+#define TX_DMA_BURST_32 1
-+#define TX_DMA_BURST_16 0
-+#define Reserved1_data 0x3F
-+#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
-+#define Jumbo_Frame_2k (2 * 1024)
-+#define Jumbo_Frame_3k (3 * 1024)
-+#define Jumbo_Frame_4k (4 * 1024)
-+#define Jumbo_Frame_5k (5 * 1024)
-+#define Jumbo_Frame_6k (6 * 1024)
-+#define Jumbo_Frame_7k (7 * 1024)
-+#define Jumbo_Frame_8k (8 * 1024)
-+#define Jumbo_Frame_9k (9 * 1024)
-+#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
-+#define RxEarly_off_V1 (0x07 << 11)
-+#define RxEarly_off_V2 (1 << 11)
-+#define Rx_Single_fetch_V2 (1 << 14)
-+
-+#define R8168_REGS_SIZE (256)
-+#define R8168_MAC_REGS_SIZE (256)
-+#define R8168_PHY_REGS_SIZE (16*2)
-+#define R8168_EPHY_REGS_SIZE (31*2)
-+#define R8168_ERI_REGS_SIZE (0x100)
-+#define R8168_REGS_DUMP_SIZE (0x400)
-+#define R8168_NAPI_WEIGHT 64
-+
-+#define RTL8168_TX_TIMEOUT (6 * HZ)
-+#define RTL8168_LINK_TIMEOUT (1 * HZ)
-+#define RTL8168_ESD_TIMEOUT (2 * HZ)
-+
-+#define NUM_TX_DESC 1024 /* Number of Tx descriptor registers */
-+#define NUM_RX_DESC 1024 /* Number of Rx descriptor registers */
-+
-+#define RX_BUF_SIZE 0x05F3 /* 0x05F3 = 1522bye + 1 */
-+#define R8168_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
-+#define R8168_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
-+
-+#define NODE_ADDRESS_SIZE 6
-+
-+#define SHORT_PACKET_PADDING_BUF_SIZE 256
-+
-+/* write/read MMIO register */
-+#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
-+#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
-+#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
-+#define RTL_R8(reg) readb (ioaddr + (reg))
-+#define RTL_R16(reg) readw (ioaddr + (reg))
-+#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
-+
-+#ifndef DMA_64BIT_MASK
-+#define DMA_64BIT_MASK 0xffffffffffffffffULL
-+#endif
-+
-+#ifndef DMA_32BIT_MASK
-+#define DMA_32BIT_MASK 0x00000000ffffffffULL
-+#endif
-+
-+#ifndef NETDEV_TX_OK
-+#define NETDEV_TX_OK 0 /* driver took care of packet */
-+#endif
-+
-+#ifndef NETDEV_TX_BUSY
-+#define NETDEV_TX_BUSY 1 /* driver tx path was busy*/
-+#endif
-+
-+#ifndef NETDEV_TX_LOCKED
-+#define NETDEV_TX_LOCKED -1 /* driver tx lock was already taken */
-+#endif
-+
-+#ifndef ADVERTISED_Pause
-+#define ADVERTISED_Pause (1 << 13)
-+#endif
-+
-+#ifndef ADVERTISED_Asym_Pause
-+#define ADVERTISED_Asym_Pause (1 << 14)
-+#endif
-+
-+#ifndef ADVERTISE_PAUSE_CAP
-+#define ADVERTISE_PAUSE_CAP 0x400
-+#endif
-+
-+#ifndef ADVERTISE_PAUSE_ASYM
-+#define ADVERTISE_PAUSE_ASYM 0x800
-+#endif
-+
-+#ifndef MII_CTRL1000
-+#define MII_CTRL1000 0x09
-+#endif
-+
-+#ifndef ADVERTISE_1000FULL
-+#define ADVERTISE_1000FULL 0x200
-+#endif
-+
-+#ifndef ADVERTISE_1000HALF
-+#define ADVERTISE_1000HALF 0x100
-+#endif
-+
-+/*****************************************************************************/
-+
-+//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3)
-+#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \
-+ (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \
-+ ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )))
-+/* copied from linux kernel 2.6.20 include/linux/netdev.h */
-+#define NETDEV_ALIGN 32
-+#define NETDEV_ALIGN_CONST (NETDEV_ALIGN - 1)
-+
-+static inline void *netdev_priv(struct net_device *dev)
-+{
-+ return (char *)dev + ((sizeof(struct net_device)
-+ + NETDEV_ALIGN_CONST)
-+ & ~NETDEV_ALIGN_CONST);
-+}
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3)
-+
-+/*****************************************************************************/
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
-+#define RTLDEV tp
-+#else
-+#define RTLDEV dev
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
-+/*****************************************************************************/
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
-+typedef struct net_device *napi_ptr;
-+typedef int *napi_budget;
-+
-+#define napi dev
-+#define RTL_NAPI_CONFIG(ndev, priv, function, weig) ndev->poll=function; \
-+ ndev->weight=weig;
-+#define RTL_NAPI_DEL(priv)
-+#define RTL_NAPI_QUOTA(budget, ndev) min(*budget, ndev->quota)
-+#define RTL_GET_PRIV(stuct_ptr, priv_struct) netdev_priv(stuct_ptr)
-+#define RTL_GET_NETDEV(priv_ptr)
-+#define RTL_RX_QUOTA(ndev, budget) ndev->quota
-+#define RTL_NAPI_QUOTA_UPDATE(ndev, work_done, budget) *budget -= work_done; \
-+ ndev->quota -= work_done;
-+#define RTL_NETIF_RX_COMPLETE(dev, napi) netif_rx_complete(dev)
-+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(dev)
-+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(dev)
-+#define RTL_NAPI_RETURN_VALUE work_done >= work_to_do
-+#define RTL_NAPI_ENABLE(dev, napi) netif_poll_enable(dev)
-+#define RTL_NAPI_DISABLE(dev, napi) netif_poll_disable(dev)
-+#define DMA_BIT_MASK(value) ((1ULL << value) - 1)
-+#else
-+typedef struct napi_struct *napi_ptr;
-+typedef int napi_budget;
-+
-+#define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add(ndev, &priv->napi, function, weight)
-+#define RTL_NAPI_DEL(priv) netif_napi_del(&priv->napi)
-+#define RTL_NAPI_QUOTA(budget, ndev) min(budget, budget)
-+#define RTL_GET_PRIV(stuct_ptr, priv_struct) container_of(stuct_ptr, priv_struct, stuct_ptr)
-+#define RTL_GET_NETDEV(priv_ptr) struct net_device *dev = priv_ptr->dev;
-+#define RTL_RX_QUOTA(ndev, budget) budget
-+#define RTL_NAPI_QUOTA_UPDATE(ndev, work_done, budget)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
-+#define RTL_NETIF_RX_COMPLETE(dev, napi) netif_rx_complete(dev, napi)
-+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(dev, napi)
-+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(dev, napi)
-+#endif
-+#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,29)
-+#define RTL_NETIF_RX_COMPLETE(dev, napi) netif_rx_complete(napi)
-+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) netif_rx_schedule_prep(napi)
-+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __netif_rx_schedule(napi)
-+#endif
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29)
-+#define RTL_NETIF_RX_COMPLETE(dev, napi) napi_complete(napi)
-+#define RTL_NETIF_RX_SCHEDULE_PREP(dev, napi) napi_schedule_prep(napi)
-+#define __RTL_NETIF_RX_SCHEDULE(dev, napi) __napi_schedule(napi)
-+#endif
-+#define RTL_NAPI_RETURN_VALUE work_done
-+#define RTL_NAPI_ENABLE(dev, napi) napi_enable(napi)
-+#define RTL_NAPI_DISABLE(dev, napi) napi_disable(napi)
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
-+
-+/*****************************************************************************/
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
-+#ifdef __CHECKER__
-+#define __iomem __attribute__((noderef, address_space(2)))
-+extern void __chk_io_ptr(void __iomem *);
-+#define __bitwise __attribute__((bitwise))
-+#else
-+#define __iomem
-+#define __chk_io_ptr(x) (void)0
-+#define __bitwise
-+#endif
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
-+
-+/*****************************************************************************/
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8)
-+#ifdef __CHECKER__
-+#define __force __attribute__((force))
-+#else
-+#define __force
-+#endif
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8)
-+
-+#ifndef module_param
-+#define module_param(v,t,p) MODULE_PARM(v, "i");
-+#endif
-+
-+#ifndef PCI_DEVICE
-+#define PCI_DEVICE(vend,dev) \
-+ .vendor = (vend), .device = (dev), \
-+ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
-+#endif
-+
-+/*****************************************************************************/
-+/* 2.5.28 => 2.4.23 */
-+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )
-+
-+static inline void _kc_synchronize_irq(void)
-+{
-+ synchronize_irq();
-+}
-+#undef synchronize_irq
-+#define synchronize_irq(X) _kc_synchronize_irq()
-+
-+#include <linux/tqueue.h>
-+#define work_struct tq_struct
-+#undef INIT_WORK
-+#define INIT_WORK(a,b,c) INIT_TQUEUE(a,(void (*)(void *))b,c)
-+#undef container_of
-+#define container_of list_entry
-+#define schedule_work schedule_task
-+#define flush_scheduled_work flush_scheduled_tasks
-+#endif /* 2.5.28 => 2.4.17 */
-+
-+/*****************************************************************************/
-+/* 2.6.4 => 2.6.0 */
-+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )
-+#define MODULE_VERSION(_version) MODULE_INFO(version, _version)
-+#endif /* 2.6.4 => 2.6.0 */
-+/*****************************************************************************/
-+/* 2.6.0 => 2.5.28 */
-+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )
-+#define MODULE_INFO(version, _version)
-+#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
-+#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1
-+#endif
-+
-+#define pci_set_consistent_dma_mask(dev,mask) 1
-+
-+#undef dev_put
-+#define dev_put(dev) __dev_put(dev)
-+
-+#ifndef skb_fill_page_desc
-+#define skb_fill_page_desc _kc_skb_fill_page_desc
-+extern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size);
-+#endif
-+
-+#ifndef pci_dma_mapping_error
-+#define pci_dma_mapping_error _kc_pci_dma_mapping_error
-+static inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr)
-+{
-+ return dma_addr == 0;
-+}
-+#endif
-+
-+#undef ALIGN
-+#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1))
-+
-+#endif /* 2.6.0 => 2.5.28 */
-+
-+/*****************************************************************************/
-+/* 2.4.22 => 2.4.17 */
-+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )
-+#define pci_name(x) ((x)->slot_name)
-+#endif /* 2.4.22 => 2.4.17 */
-+
-+/*****************************************************************************/
-+/* 2.6.5 => 2.6.0 */
-+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) )
-+#define pci_dma_sync_single_for_cpu pci_dma_sync_single
-+#define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu
-+#endif /* 2.6.5 => 2.6.0 */
-+
-+/*****************************************************************************/
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-+/*
-+ * initialize a work-struct's func and data pointers:
-+ */
-+#define PREPARE_WORK(_work, _func, _data) \
-+ do { \
-+ (_work)->func = _func; \
-+ (_work)->data = _data; \
-+ } while (0)
-+
-+#endif
-+/*****************************************************************************/
-+/* 2.6.4 => 2.6.0 */
-+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \
-+ ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \
-+ LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) )
-+#define ETHTOOL_OPS_COMPAT
-+#endif /* 2.6.4 => 2.6.0 */
-+
-+/*****************************************************************************/
-+/* Installations with ethtool version without eeprom, adapter id, or statistics
-+ * support */
-+
-+#ifndef ETH_GSTRING_LEN
-+#define ETH_GSTRING_LEN 32
-+#endif
-+
-+#ifndef ETHTOOL_GSTATS
-+#define ETHTOOL_GSTATS 0x1d
-+#undef ethtool_drvinfo
-+#define ethtool_drvinfo k_ethtool_drvinfo
-+struct k_ethtool_drvinfo {
-+ u32 cmd;
-+ char driver[32];
-+ char version[32];
-+ char fw_version[32];
-+ char bus_info[32];
-+ char reserved1[32];
-+ char reserved2[16];
-+ u32 n_stats;
-+ u32 testinfo_len;
-+ u32 eedump_len;
-+ u32 regdump_len;
-+};
-+
-+struct ethtool_stats {
-+ u32 cmd;
-+ u32 n_stats;
-+ u64 data[0];
-+};
-+#endif /* ETHTOOL_GSTATS */
-+
-+#ifndef ETHTOOL_PHYS_ID
-+#define ETHTOOL_PHYS_ID 0x1c
-+#endif /* ETHTOOL_PHYS_ID */
-+
-+#ifndef ETHTOOL_GSTRINGS
-+#define ETHTOOL_GSTRINGS 0x1b
-+enum ethtool_stringset {
-+ ETH_SS_TEST = 0,
-+ ETH_SS_STATS,
-+};
-+struct ethtool_gstrings {
-+ u32 cmd; /* ETHTOOL_GSTRINGS */
-+ u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/
-+ u32 len; /* number of strings in the string set */
-+ u8 data[0];
-+};
-+#endif /* ETHTOOL_GSTRINGS */
-+
-+#ifndef ETHTOOL_TEST
-+#define ETHTOOL_TEST 0x1a
-+enum ethtool_test_flags {
-+ ETH_TEST_FL_OFFLINE = (1 << 0),
-+ ETH_TEST_FL_FAILED = (1 << 1),
-+};
-+struct ethtool_test {
-+ u32 cmd;
-+ u32 flags;
-+ u32 reserved;
-+ u32 len;
-+ u64 data[0];
-+};
-+#endif /* ETHTOOL_TEST */
-+
-+#ifndef ETHTOOL_GEEPROM
-+#define ETHTOOL_GEEPROM 0xb
-+#undef ETHTOOL_GREGS
-+struct ethtool_eeprom {
-+ u32 cmd;
-+ u32 magic;
-+ u32 offset;
-+ u32 len;
-+ u8 data[0];
-+};
-+
-+struct ethtool_value {
-+ u32 cmd;
-+ u32 data;
-+};
-+#endif /* ETHTOOL_GEEPROM */
-+
-+#ifndef ETHTOOL_GLINK
-+#define ETHTOOL_GLINK 0xa
-+#endif /* ETHTOOL_GLINK */
-+
-+#ifndef ETHTOOL_GREGS
-+#define ETHTOOL_GREGS 0x00000004 /* Get NIC registers */
-+#define ethtool_regs _kc_ethtool_regs
-+/* for passing big chunks of data */
-+struct _kc_ethtool_regs {
-+ u32 cmd;
-+ u32 version; /* driver-specific, indicates different chips/revs */
-+ u32 len; /* bytes */
-+ u8 data[0];
-+};
-+#endif /* ETHTOOL_GREGS */
-+
-+#ifndef ETHTOOL_GMSGLVL
-+#define ETHTOOL_GMSGLVL 0x00000007 /* Get driver message level */
-+#endif
-+#ifndef ETHTOOL_SMSGLVL
-+#define ETHTOOL_SMSGLVL 0x00000008 /* Set driver msg level, priv. */
-+#endif
-+#ifndef ETHTOOL_NWAY_RST
-+#define ETHTOOL_NWAY_RST 0x00000009 /* Restart autonegotiation, priv */
-+#endif
-+#ifndef ETHTOOL_GLINK
-+#define ETHTOOL_GLINK 0x0000000a /* Get link status */
-+#endif
-+#ifndef ETHTOOL_GEEPROM
-+#define ETHTOOL_GEEPROM 0x0000000b /* Get EEPROM data */
-+#endif
-+#ifndef ETHTOOL_SEEPROM
-+#define ETHTOOL_SEEPROM 0x0000000c /* Set EEPROM data */
-+#endif
-+#ifndef ETHTOOL_GCOALESCE
-+#define ETHTOOL_GCOALESCE 0x0000000e /* Get coalesce config */
-+/* for configuring coalescing parameters of chip */
-+#define ethtool_coalesce _kc_ethtool_coalesce
-+struct _kc_ethtool_coalesce {
-+ u32 cmd; /* ETHTOOL_{G,S}COALESCE */
-+
-+ /* How many usecs to delay an RX interrupt after
-+ * a packet arrives. If 0, only rx_max_coalesced_frames
-+ * is used.
-+ */
-+ u32 rx_coalesce_usecs;
-+
-+ /* How many packets to delay an RX interrupt after
-+ * a packet arrives. If 0, only rx_coalesce_usecs is
-+ * used. It is illegal to set both usecs and max frames
-+ * to zero as this would cause RX interrupts to never be
-+ * generated.
-+ */
-+ u32 rx_max_coalesced_frames;
-+
-+ /* Same as above two parameters, except that these values
-+ * apply while an IRQ is being serviced by the host. Not
-+ * all cards support this feature and the values are ignored
-+ * in that case.
-+ */
-+ u32 rx_coalesce_usecs_irq;
-+ u32 rx_max_coalesced_frames_irq;
-+
-+ /* How many usecs to delay a TX interrupt after
-+ * a packet is sent. If 0, only tx_max_coalesced_frames
-+ * is used.
-+ */
-+ u32 tx_coalesce_usecs;
-+
-+ /* How many packets to delay a TX interrupt after
-+ * a packet is sent. If 0, only tx_coalesce_usecs is
-+ * used. It is illegal to set both usecs and max frames
-+ * to zero as this would cause TX interrupts to never be
-+ * generated.
-+ */
-+ u32 tx_max_coalesced_frames;
-+
-+ /* Same as above two parameters, except that these values
-+ * apply while an IRQ is being serviced by the host. Not
-+ * all cards support this feature and the values are ignored
-+ * in that case.
-+ */
-+ u32 tx_coalesce_usecs_irq;
-+ u32 tx_max_coalesced_frames_irq;
-+
-+ /* How many usecs to delay in-memory statistics
-+ * block updates. Some drivers do not have an in-memory
-+ * statistic block, and in such cases this value is ignored.
-+ * This value must not be zero.
-+ */
-+ u32 stats_block_coalesce_usecs;
-+
-+ /* Adaptive RX/TX coalescing is an algorithm implemented by
-+ * some drivers to improve latency under low packet rates and
-+ * improve throughput under high packet rates. Some drivers
-+ * only implement one of RX or TX adaptive coalescing. Anything
-+ * not implemented by the driver causes these values to be
-+ * silently ignored.
-+ */
-+ u32 use_adaptive_rx_coalesce;
-+ u32 use_adaptive_tx_coalesce;
-+
-+ /* When the packet rate (measured in packets per second)
-+ * is below pkt_rate_low, the {rx,tx}_*_low parameters are
-+ * used.
-+ */
-+ u32 pkt_rate_low;
-+ u32 rx_coalesce_usecs_low;
-+ u32 rx_max_coalesced_frames_low;
-+ u32 tx_coalesce_usecs_low;
-+ u32 tx_max_coalesced_frames_low;
-+
-+ /* When the packet rate is below pkt_rate_high but above
-+ * pkt_rate_low (both measured in packets per second) the
-+ * normal {rx,tx}_* coalescing parameters are used.
-+ */
-+
-+ /* When the packet rate is (measured in packets per second)
-+ * is above pkt_rate_high, the {rx,tx}_*_high parameters are
-+ * used.
-+ */
-+ u32 pkt_rate_high;
-+ u32 rx_coalesce_usecs_high;
-+ u32 rx_max_coalesced_frames_high;
-+ u32 tx_coalesce_usecs_high;
-+ u32 tx_max_coalesced_frames_high;
-+
-+ /* How often to do adaptive coalescing packet rate sampling,
-+ * measured in seconds. Must not be zero.
-+ */
-+ u32 rate_sample_interval;
-+};
-+#endif /* ETHTOOL_GCOALESCE */
-+
-+#ifndef ETHTOOL_SCOALESCE
-+#define ETHTOOL_SCOALESCE 0x0000000f /* Set coalesce config. */
-+#endif
-+#ifndef ETHTOOL_GRINGPARAM
-+#define ETHTOOL_GRINGPARAM 0x00000010 /* Get ring parameters */
-+/* for configuring RX/TX ring parameters */
-+#define ethtool_ringparam _kc_ethtool_ringparam
-+struct _kc_ethtool_ringparam {
-+ u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */
-+
-+ /* Read only attributes. These indicate the maximum number
-+ * of pending RX/TX ring entries the driver will allow the
-+ * user to set.
-+ */
-+ u32 rx_max_pending;
-+ u32 rx_mini_max_pending;
-+ u32 rx_jumbo_max_pending;
-+ u32 tx_max_pending;
-+
-+ /* Values changeable by the user. The valid values are
-+ * in the range 1 to the "*_max_pending" counterpart above.
-+ */
-+ u32 rx_pending;
-+ u32 rx_mini_pending;
-+ u32 rx_jumbo_pending;
-+ u32 tx_pending;
-+};
-+#endif /* ETHTOOL_GRINGPARAM */
-+
-+#ifndef ETHTOOL_SRINGPARAM
-+#define ETHTOOL_SRINGPARAM 0x00000011 /* Set ring parameters, priv. */
-+#endif
-+#ifndef ETHTOOL_GPAUSEPARAM
-+#define ETHTOOL_GPAUSEPARAM 0x00000012 /* Get pause parameters */
-+/* for configuring link flow control parameters */
-+#define ethtool_pauseparam _kc_ethtool_pauseparam
-+struct _kc_ethtool_pauseparam {
-+ u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */
-+
-+ /* If the link is being auto-negotiated (via ethtool_cmd.autoneg
-+ * being true) the user may set 'autonet' here non-zero to have the
-+ * pause parameters be auto-negotiated too. In such a case, the
-+ * {rx,tx}_pause values below determine what capabilities are
-+ * advertised.
-+ *
-+ * If 'autoneg' is zero or the link is not being auto-negotiated,
-+ * then {rx,tx}_pause force the driver to use/not-use pause
-+ * flow control.
-+ */
-+ u32 autoneg;
-+ u32 rx_pause;
-+ u32 tx_pause;
-+};
-+#endif /* ETHTOOL_GPAUSEPARAM */
-+
-+#ifndef ETHTOOL_SPAUSEPARAM
-+#define ETHTOOL_SPAUSEPARAM 0x00000013 /* Set pause parameters. */
-+#endif
-+#ifndef ETHTOOL_GRXCSUM
-+#define ETHTOOL_GRXCSUM 0x00000014 /* Get RX hw csum enable (ethtool_value) */
-+#endif
-+#ifndef ETHTOOL_SRXCSUM
-+#define ETHTOOL_SRXCSUM 0x00000015 /* Set RX hw csum enable (ethtool_value) */
-+#endif
-+#ifndef ETHTOOL_GTXCSUM
-+#define ETHTOOL_GTXCSUM 0x00000016 /* Get TX hw csum enable (ethtool_value) */
-+#endif
-+#ifndef ETHTOOL_STXCSUM
-+#define ETHTOOL_STXCSUM 0x00000017 /* Set TX hw csum enable (ethtool_value) */
-+#endif
-+#ifndef ETHTOOL_GSG
-+#define ETHTOOL_GSG 0x00000018 /* Get scatter-gather enable
-+* (ethtool_value) */
-+#endif
-+#ifndef ETHTOOL_SSG
-+#define ETHTOOL_SSG 0x00000019 /* Set scatter-gather enable
-+* (ethtool_value). */
-+#endif
-+#ifndef ETHTOOL_TEST
-+#define ETHTOOL_TEST 0x0000001a /* execute NIC self-test, priv. */
-+#endif
-+#ifndef ETHTOOL_GSTRINGS
-+#define ETHTOOL_GSTRINGS 0x0000001b /* get specified string set */
-+#endif
-+#ifndef ETHTOOL_PHYS_ID
-+#define ETHTOOL_PHYS_ID 0x0000001c /* identify the NIC */
-+#endif
-+#ifndef ETHTOOL_GSTATS
-+#define ETHTOOL_GSTATS 0x0000001d /* get NIC-specific statistics */
-+#endif
-+#ifndef ETHTOOL_GTSO
-+#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */
-+#endif
-+#ifndef ETHTOOL_STSO
-+#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */
-+#endif
-+
-+#ifndef ETHTOOL_BUSINFO_LEN
-+#define ETHTOOL_BUSINFO_LEN 32
-+#endif
-+
-+/*****************************************************************************/
-+
-+enum RTL8168_DSM_STATE {
-+ DSM_MAC_INIT = 1,
-+ DSM_NIC_GOTO_D3 = 2,
-+ DSM_IF_DOWN = 3,
-+ DSM_NIC_RESUME_D3 = 4,
-+ DSM_IF_UP = 5,
-+};
-+
-+enum RTL8168_registers {
-+ MAC0 = 0x00, /* Ethernet hardware address. */
-+ MAC4 = 0x04,
-+ MAR0 = 0x08, /* Multicast filter. */
-+ CounterAddrLow = 0x10,
-+ CounterAddrHigh = 0x14,
-+ CustomLED = 0x18,
-+ TxDescStartAddrLow = 0x20,
-+ TxDescStartAddrHigh = 0x24,
-+ TxHDescStartAddrLow = 0x28,
-+ TxHDescStartAddrHigh = 0x2c,
-+ FLASH = 0x30,
-+ ERSR = 0x36,
-+ ChipCmd = 0x37,
-+ TxPoll = 0x38,
-+ IntrMask = 0x3C,
-+ IntrStatus = 0x3E,
-+ TxConfig = 0x40,
-+ RxConfig = 0x44,
-+ TCTR = 0x48,
-+ Cfg9346 = 0x50,
-+ Config0 = 0x51,
-+ Config1 = 0x52,
-+ Config2 = 0x53,
-+ Config3 = 0x54,
-+ Config4 = 0x55,
-+ Config5 = 0x56,
-+ TDFNR = 0x57,
-+ TimeInt0 = 0x58,
-+ TimeInt1 = 0x5C,
-+ PHYAR = 0x60,
-+ CSIDR = 0x64,
-+ CSIAR = 0x68,
-+ PHYstatus = 0x6C,
-+ MACDBG = 0x6D,
-+ GPIO = 0x6E,
-+ PMCH = 0x6F,
-+ ERIDR = 0x70,
-+ ERIAR = 0x74,
-+ EPHY_RXER_NUM = 0x7C,
-+ EPHYAR = 0x80,
-+ TimeInt2 = 0x8C,
-+ OCPDR = 0xB0,
-+ MACOCP = 0xB0,
-+ OCPAR = 0xB4,
-+ SecMAC0 = 0xB4,
-+ SecMAC4 = 0xB8,
-+ PHYOCP = 0xB8,
-+ DBG_reg = 0xD1,
-+ TwiCmdReg = 0xD2,
-+ MCUCmd_reg = 0xD3,
-+ RxMaxSize = 0xDA,
-+ EFUSEAR = 0xDC,
-+ CPlusCmd = 0xE0,
-+ IntrMitigate = 0xE2,
-+ RxDescAddrLow = 0xE4,
-+ RxDescAddrHigh = 0xE8,
-+ MTPS = 0xEC,
-+ FuncEvent = 0xF0,
-+ PPSW = 0xF2,
-+ FuncEventMask = 0xF4,
-+ TimeInt3 = 0xF4,
-+ FuncPresetState = 0xF8,
-+ IBCR0 = 0xF8,
-+ IBCR2 = 0xF9,
-+ IBIMR0 = 0xFA,
-+ IBISR0 = 0xFB,
-+ FuncForceEvent = 0xFC,
-+};
-+
-+enum RTL8168_register_content {
-+ /* InterruptStatusBits */
-+ SYSErr = 0x8000,
-+ PCSTimeout = 0x4000,
-+ SWInt = 0x0100,
-+ TxDescUnavail = 0x0080,
-+ RxFIFOOver = 0x0040,
-+ LinkChg = 0x0020,
-+ RxDescUnavail = 0x0010,
-+ TxErr = 0x0008,
-+ TxOK = 0x0004,
-+ RxErr = 0x0002,
-+ RxOK = 0x0001,
-+
-+ /* RxStatusDesc */
-+ RxRWT = (1 << 22),
-+ RxRES = (1 << 21),
-+ RxRUNT = (1 << 20),
-+ RxCRC = (1 << 19),
-+
-+ /* ChipCmdBits */
-+ StopReq = 0x80,
-+ CmdReset = 0x10,
-+ CmdRxEnb = 0x08,
-+ CmdTxEnb = 0x04,
-+ RxBufEmpty = 0x01,
-+
-+ /* Cfg9346Bits */
-+ Cfg9346_Lock = 0x00,
-+ Cfg9346_Unlock = 0xC0,
-+ Cfg9346_EEDO = (1 << 0),
-+ Cfg9346_EEDI = (1 << 1),
-+ Cfg9346_EESK = (1 << 2),
-+ Cfg9346_EECS = (1 << 3),
-+ Cfg9346_EEM0 = (1 << 6),
-+ Cfg9346_EEM1 = (1 << 7),
-+
-+ /* rx_mode_bits */
-+ AcceptErr = 0x20,
-+ AcceptRunt = 0x10,
-+ AcceptBroadcast = 0x08,
-+ AcceptMulticast = 0x04,
-+ AcceptMyPhys = 0x02,
-+ AcceptAllPhys = 0x01,
-+
-+ /* Transmit Priority Polling*/
-+ HPQ = 0x80,
-+ NPQ = 0x40,
-+ FSWInt = 0x01,
-+
-+ /* RxConfigBits */
-+ Reserved2_shift = 13,
-+ RxCfgDMAShift = 8,
-+ RxCfg_128_int_en = (1 << 15),
-+ RxCfg_fet_multi_en = (1 << 14),
-+ RxCfg_half_refetch = (1 << 13),
-+ RxCfg_9356SEL = (1 << 6),
-+
-+ /* TxConfigBits */
-+ TxInterFrameGapShift = 24,
-+ TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
-+ TxMACLoopBack = (1 << 17), /* MAC loopback */
-+
-+ /* Config1 register */
-+ LEDS1 = (1 << 7),
-+ LEDS0 = (1 << 6),
-+ Speed_down = (1 << 4),
-+ MEMMAP = (1 << 3),
-+ IOMAP = (1 << 2),
-+ VPD = (1 << 1),
-+ PMEnable = (1 << 0), /* Power Management Enable */
-+
-+ /* Config2 register */
-+ PMSTS_En = (1 << 5),
-+
-+ /* Config3 register */
-+ Isolate_en = (1 << 12), /* Isolate enable */
-+ MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
-+ LinkUp = (1 << 4), /* This bit is reserved in RTL8168B.*/
-+ /* Wake up when the cable connection is re-established */
-+ ECRCEN = (1 << 3), /* This bit is reserved in RTL8168B*/
-+ Jumbo_En0 = (1 << 2), /* This bit is reserved in RTL8168B*/
-+ RDY_TO_L23 = (1 << 1), /* This bit is reserved in RTL8168B*/
-+ Beacon_en = (1 << 0), /* This bit is reserved in RTL8168B*/
-+
-+ /* Config4 register */
-+ Jumbo_En1 = (1 << 1), /* This bit is reserved in RTL8168B*/
-+
-+ /* Config5 register */
-+ BWF = (1 << 6), /* Accept Broadcast wakeup frame */
-+ MWF = (1 << 5), /* Accept Multicast wakeup frame */
-+ UWF = (1 << 4), /* Accept Unicast wakeup frame */
-+ LanWake = (1 << 1), /* LanWake enable/disable */
-+ PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
-+
-+ /* CPlusCmd */
-+ EnableBist = (1 << 15),
-+ Macdbgo_oe = (1 << 14),
-+ Normal_mode = (1 << 13),
-+ Force_halfdup = (1 << 12),
-+ Force_rxflow_en = (1 << 11),
-+ Force_txflow_en = (1 << 10),
-+ Cxpl_dbg_sel = (1 << 9),//This bit is reserved in RTL8168B
-+ ASF = (1 << 8),//This bit is reserved in RTL8168C
-+ PktCntrDisable = (1 << 7),
-+ RxVlan = (1 << 6),
-+ RxChkSum = (1 << 5),
-+ Macdbgo_sel = 0x001C,
-+ INTT_0 = 0x0000,
-+ INTT_1 = 0x0001,
-+ INTT_2 = 0x0002,
-+ INTT_3 = 0x0003,
-+
-+ /* rtl8168_PHYstatus */
-+ PowerSaveStatus = 0x80,
-+ TxFlowCtrl = 0x40,
-+ RxFlowCtrl = 0x20,
-+ _1000bpsF = 0x10,
-+ _100bps = 0x08,
-+ _10bps = 0x04,
-+ LinkStatus = 0x02,
-+ FullDup = 0x01,
-+
-+ /* DBG_reg */
-+ Fix_Nak_1 = (1 << 4),
-+ Fix_Nak_2 = (1 << 3),
-+ DBGPIN_E2 = (1 << 0),
-+
-+ /* DumpCounterCommand */
-+ CounterDump = 0x8,
-+
-+ /* PHY access */
-+ PHYAR_Flag = 0x80000000,
-+ PHYAR_Write = 0x80000000,
-+ PHYAR_Read = 0x00000000,
-+ PHYAR_Reg_Mask = 0x1f,
-+ PHYAR_Reg_shift = 16,
-+ PHYAR_Data_Mask = 0xffff,
-+
-+ /* EPHY access */
-+ EPHYAR_Flag = 0x80000000,
-+ EPHYAR_Write = 0x80000000,
-+ EPHYAR_Read = 0x00000000,
-+ EPHYAR_Reg_Mask = 0x1f,
-+ EPHYAR_Reg_shift = 16,
-+ EPHYAR_Data_Mask = 0xffff,
-+
-+ /* CSI access */
-+ CSIAR_Flag = 0x80000000,
-+ CSIAR_Write = 0x80000000,
-+ CSIAR_Read = 0x00000000,
-+ CSIAR_ByteEn = 0x0f,
-+ CSIAR_ByteEn_shift = 12,
-+ CSIAR_Addr_Mask = 0x0fff,
-+
-+ /* ERI access */
-+ ERIAR_Flag = 0x80000000,
-+ ERIAR_Write = 0x80000000,
-+ ERIAR_Read = 0x00000000,
-+ ERIAR_Addr_Align = 4, /* ERI access register address must be 4 byte alignment */
-+ ERIAR_ExGMAC = 0,
-+ ERIAR_MSIX = 1,
-+ ERIAR_ASF = 2,
-+ ERIAR_OOB = 2,
-+ ERIAR_Type_shift = 16,
-+ ERIAR_ByteEn = 0x0f,
-+ ERIAR_ByteEn_shift = 12,
-+
-+ /* OCP GPHY access */
-+ OCPDR_Write = 0x80000000,
-+ OCPDR_Read = 0x00000000,
-+ OCPDR_Reg_Mask = 0xFF,
-+ OCPDR_Data_Mask = 0xFFFF,
-+ OCPDR_GPHY_Reg_shift = 16,
-+ OCPAR_Flag = 0x80000000,
-+ OCPAR_GPHY_Write = 0x8000F060,
-+ OCPAR_GPHY_Read = 0x0000F060,
-+ OCPR_Write = 0x80000000,
-+ OCPR_Read = 0x00000000,
-+ OCPR_Addr_Reg_shift = 16,
-+ OCPR_Flag = 0x80000000,
-+ OCP_STD_PHY_BASE_PAGE = 0x0A40,
-+
-+ /* MCU Command */
-+ Now_is_oob = (1 << 7),
-+ Txfifo_empty = (1 << 5),
-+ Rxfifo_empty = (1 << 4),
-+
-+ /* E-FUSE access */
-+ EFUSE_WRITE = 0x80000000,
-+ EFUSE_WRITE_OK = 0x00000000,
-+ EFUSE_READ = 0x00000000,
-+ EFUSE_READ_OK = 0x80000000,
-+ EFUSE_Reg_Mask = 0x03FF,
-+ EFUSE_Reg_Shift = 8,
-+ EFUSE_Check_Cnt = 300,
-+ EFUSE_READ_FAIL = 0xFF,
-+ EFUSE_Data_Mask = 0x000000FF,
-+
-+ /* GPIO */
-+ GPIO_en = (1 << 0),
-+
-+};
-+
-+enum _DescStatusBit {
-+ DescOwn = (1 << 31), /* Descriptor is owned by NIC */
-+ RingEnd = (1 << 30), /* End of descriptor ring */
-+ FirstFrag = (1 << 29), /* First segment of a packet */
-+ LastFrag = (1 << 28), /* Final segment of a packet */
-+
-+ /* Tx private */
-+ /*------ offset 0 of tx descriptor ------*/
-+ LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
-+ LargeSend_DP = (1 << 16), /* TCP Large Send Offload (TSO) */
-+ MSSShift = 16, /* MSS value position */
-+ MSSMask = 0x7FFU, /* MSS value 11 bits */
-+ TxIPCS = (1 << 18), /* Calculate IP checksum */
-+ TxUDPCS = (1 << 17), /* Calculate UDP/IP checksum */
-+ TxTCPCS = (1 << 16), /* Calculate TCP/IP checksum */
-+ TxVlanTag = (1 << 17), /* Add VLAN tag */
-+
-+ /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only begin @@@@@@*/
-+ TxUDPCS_C = (1 << 31), /* Calculate UDP/IP checksum */
-+ TxTCPCS_C = (1 << 30), /* Calculate TCP/IP checksum */
-+ TxIPCS_C = (1 << 29), /* Calculate IP checksum */
-+ /*@@@@@@ offset 4 of tx descriptor => bits for RTL8168C/CP only end @@@@@@*/
-+
-+
-+ /* Rx private */
-+ /*------ offset 0 of rx descriptor ------*/
-+ PID1 = (1 << 18), /* Protocol ID bit 1/2 */
-+ PID0 = (1 << 17), /* Protocol ID bit 2/2 */
-+
-+#define RxProtoUDP (PID1)
-+#define RxProtoTCP (PID0)
-+#define RxProtoIP (PID1 | PID0)
-+#define RxProtoMask RxProtoIP
-+
-+ RxIPF = (1 << 16), /* IP checksum failed */
-+ RxUDPF = (1 << 15), /* UDP/IP checksum failed */
-+ RxTCPF = (1 << 14), /* TCP/IP checksum failed */
-+ RxVlanTag = (1 << 16), /* VLAN tag available */
-+
-+ /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only begin @@@@@@*/
-+ RxUDPT = (1 << 18),
-+ RxTCPT = (1 << 17),
-+ /*@@@@@@ offset 0 of rx descriptor => bits for RTL8168C/CP only end @@@@@@*/
-+
-+ /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only begin @@@@@@*/
-+ RxV6F = (1 << 31),
-+ RxV4F = (1 << 30),
-+ /*@@@@@@ offset 4 of rx descriptor => bits for RTL8168C/CP only end @@@@@@*/
-+};
-+
-+enum features {
-+// RTL_FEATURE_WOL = (1 << 0),
-+ RTL_FEATURE_MSI = (1 << 1),
-+};
-+
-+enum wol_capability {
-+ WOL_DISABLED = 0,
-+ WOL_ENABLED = 1
-+};
-+
-+enum bits {
-+ BIT_0 = (1 << 0),
-+ BIT_1 = (1 << 1),
-+ BIT_2 = (1 << 2),
-+ BIT_3 = (1 << 3),
-+ BIT_4 = (1 << 4),
-+ BIT_5 = (1 << 5),
-+ BIT_6 = (1 << 6),
-+ BIT_7 = (1 << 7),
-+ BIT_8 = (1 << 8),
-+ BIT_9 = (1 << 9),
-+ BIT_10 = (1 << 10),
-+ BIT_11 = (1 << 11),
-+ BIT_12 = (1 << 12),
-+ BIT_13 = (1 << 13),
-+ BIT_14 = (1 << 14),
-+ BIT_15 = (1 << 15),
-+ BIT_16 = (1 << 16),
-+ BIT_17 = (1 << 17),
-+ BIT_18 = (1 << 18),
-+ BIT_19 = (1 << 19),
-+ BIT_20 = (1 << 20),
-+ BIT_21 = (1 << 21),
-+ BIT_22 = (1 << 22),
-+ BIT_23 = (1 << 23),
-+ BIT_24 = (1 << 24),
-+ BIT_25 = (1 << 25),
-+ BIT_26 = (1 << 26),
-+ BIT_27 = (1 << 27),
-+ BIT_28 = (1 << 28),
-+ BIT_29 = (1 << 29),
-+ BIT_30 = (1 << 30),
-+ BIT_31 = (1 << 31)
-+};
-+
-+enum effuse {
-+ EFUSE_NOT_SUPPORT = 0,
-+ EFUSE_SUPPORT_V1,
-+ EFUSE_SUPPORT_V2,
-+ EFUSE_SUPPORT_V3,
-+};
-+#define RsvdMask 0x3fffc000
-+
-+struct TxDesc {
-+ u32 opts1;
-+ u32 opts2;
-+ u64 addr;
-+};
-+
-+struct RxDesc {
-+ u32 opts1;
-+ u32 opts2;
-+ u64 addr;
-+};
-+
-+struct ring_info {
-+ struct sk_buff *skb;
-+ u32 len;
-+ u8 __pad[sizeof(void *) - sizeof(u32)];
-+};
-+
-+struct pci_resource {
-+ u8 cmd;
-+ u8 cls;
-+ u16 io_base_h;
-+ u16 io_base_l;
-+ u16 mem_base_h;
-+ u16 mem_base_l;
-+ u8 ilr;
-+ u16 resv_0x1c_h;
-+ u16 resv_0x1c_l;
-+ u16 resv_0x20_h;
-+ u16 resv_0x20_l;
-+ u16 resv_0x24_h;
-+ u16 resv_0x24_l;
-+ u16 resv_0x2c_h;
-+ u16 resv_0x2c_l;
-+ u32 pci_sn_l;
-+ u32 pci_sn_h;
-+};
-+
-+struct rtl8168_private {
-+ void __iomem *mmio_addr; /* memory map physical address */
-+ struct pci_dev *pci_dev; /* Index of PCI device */
-+ struct net_device *dev;
-+#ifdef CONFIG_R8168_NAPI
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
-+ struct napi_struct napi;
-+#endif
-+#endif
-+ struct net_device_stats stats; /* statistics of net device */
-+ spinlock_t lock; /* spin lock flag */
-+ spinlock_t phy_lock; /* spin lock flag for GPHY */
-+ u32 msg_enable;
-+ u32 tx_tcp_csum_cmd;
-+ u32 tx_udp_csum_cmd;
-+ u32 tx_ip_csum_cmd;
-+ int max_jumbo_frame_size;
-+ int chipset;
-+ u32 mcfg;
-+ u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
-+ u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
-+ u32 dirty_rx;
-+ u32 dirty_tx;
-+ struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
-+ struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
-+ dma_addr_t TxPhyAddr;
-+ dma_addr_t RxPhyAddr;
-+ struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
-+ struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
-+ unsigned rx_buf_sz;
-+ struct timer_list esd_timer;
-+ struct timer_list link_timer;
-+ struct pci_resource pci_cfg_space;
-+ unsigned int esd_flag;
-+ unsigned int pci_cfg_is_read;
-+ unsigned int rtl8168_rx_config;
-+ u16 cp_cmd;
-+ u16 intr_mask;
-+ u16 timer_intr_mask;
-+ int phy_auto_nego_reg;
-+ int phy_1000_ctrl_reg;
-+ u8 org_mac_addr[NODE_ADDRESS_SIZE];
-+ struct rtl8168_counters *tally_vaddr;
-+ dma_addr_t tally_paddr;
-+
-+#ifdef CONFIG_R8168_VLAN
-+ struct vlan_group *vlgrp;
-+#endif
-+ u8 wol_enabled;
-+ u32 wol_opts;
-+ u8 efuse_ver;
-+ u8 eeprom_type;
-+ u8 autoneg;
-+ u8 duplex;
-+ u16 speed;
-+ u16 eeprom_len;
-+ u16 cur_page;
-+ u32 bios_setting;
-+
-+ int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
-+ void (*get_settings)(struct net_device *, struct ethtool_cmd *);
-+ void (*phy_reset_enable)(struct net_device *);
-+ unsigned int (*phy_reset_pending)(struct net_device *);
-+ unsigned int (*link_ok)(struct net_device *);
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+ struct work_struct task;
-+#else
-+ struct delayed_work task;
-+#endif
-+ unsigned features;
-+
-+ u8 org_pci_offset_99;
-+ u8 org_pci_offset_180;
-+ u8 issue_offset_99_event;
-+
-+ u8 org_pci_offset_80;
-+ u8 org_pci_offset_81;
-+ u8 use_timer_interrrupt;
-+
-+ u32 keep_intr_cnt;
-+
-+ u8 HwIcVerUnknown;
-+ u8 NotWrRamCodeToMicroP;
-+ u8 NotWrMcuPatchCode;
-+ u8 HwHasWrRamCodeToMicroP;
-+
-+ u16 sw_ram_code_ver;
-+ u16 hw_ram_code_ver;
-+
-+ u8 rtk_enable_diag;
-+
-+ u8 ShortPacketSwChecksum;
-+
-+ u8 UseSwPaddingShortPkt;
-+
-+ void *ShortPacketEmptyBuffer;
-+ dma_addr_t ShortPacketEmptyBufferPhy;
-+
-+ u8 RequireAdcBiasPatch;
-+ u16 AdcBiasPatchIoffset;
-+
-+ u8 RequireAdjustUpsTxLinkPulseTiming;
-+ u16 SwrCnt1msIni;
-+
-+ u8 HwSuppNowIsOobVer;
-+
-+ u8 RequiredSecLanDonglePatch;
-+
-+ //Dash+++++++++++++++++
-+ u8 HwSuppDashVer;
-+ u8 DASH;
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+ u16 AfterRecvFromFwBufLen;
-+ u8 AfterRecvFromFwBuf[RECV_FROM_FW_BUF_SIZE];
-+ u16 AfterSendToFwBufLen;
-+ u8 AfterSendToFwBuf[SEND_TO_FW_BUF_SIZE];
-+ u16 SendToFwBufferLen;
-+ u32 SizeOfSendToFwBuffer ;
-+ u32 SizeOfSendToFwBufferMemAlloc ;
-+ u32 NumOfSendToFwBuffer ;
-+
-+ u8 OobReq;
-+ u8 OobAck;
-+ u32 OobReqComplete;
-+ u32 OobAckComplete;
-+
-+ u8 RcvFwReqSysOkEvt;
-+ u8 RcvFwDashOkEvt;
-+ u8 SendFwHostOkEvt;
-+
-+ u8 DashFwDisableRx;
-+
-+ void *UnalignedSendToFwBufferVa;
-+ void *SendToFwBuffer ;
-+ u64 SendToFwBufferPhy ;
-+ u8 SendingToFw;
-+ u64 UnalignedSendToFwBufferPa;
-+ PTX_DASH_SEND_FW_DESC TxDashSendFwDesc;
-+ u64 TxDashSendFwDescPhy;
-+ u8 *UnalignedTxDashSendFwDescVa;
-+ u32 SizeOfTxDashSendFwDescMemAlloc;
-+ u32 SizeOfTxDashSendFwDesc ;
-+ u32 NumTxDashSendFwDesc ;
-+ u32 CurrNumTxDashSendFwDesc ;
-+ u64 UnalignedTxDashSendFwDescPa;
-+
-+ u32 NumRecvFromFwBuffer ;
-+ u32 SizeOfRecvFromFwBuffer ;
-+ u32 SizeOfRecvFromFwBufferMemAlloc ;
-+ void *RecvFromFwBuffer ;
-+ u64 RecvFromFwBufferPhy ;
-+
-+ void *UnalignedRecvFromFwBufferVa;
-+ u64 UnalignedRecvFromFwBufferPa;
-+ PRX_DASH_FROM_FW_DESC RxDashRecvFwDesc;
-+ u64 RxDashRecvFwDescPhy;
-+ u8 *UnalignedRxDashRecvFwDescVa;
-+ u32 SizeOfRxDashRecvFwDescMemAlloc;
-+ u32 SizeOfRxDashRecvFwDesc ;
-+ u32 NumRxDashRecvFwDesc ;
-+ u32 CurrNumRxDashRecvFwDesc ;
-+ u64 UnalignedRxDashRecvFwDescPa;
-+ u8 DashReqRegValue;
-+ u16 HostReqValue;
-+
-+ u32 CmacResetIsrCounter;
-+ u8 CmacResetIsr1st ;
-+ u8 CmacResetIsr2nd ;
-+ u8 CmacResetting ;
-+ u8 CmacOobIssueCmacReset ;
-+ //Dash-----------------
-+#endif //ENABLE_DASH_SUPPORT
-+
-+ //Realwow++++++++++++++
-+ u8 HwSuppKCPOffloadVer;
-+
-+ u8 EnableDhcpTimeoutWake;
-+ u8 EnableTeredoOffload;
-+ u8 EnableKCPOffload;
-+#ifdef ENABLE_REALWOW_SUPPORT
-+ u32 DhcpTimeout;
-+ MP_KCP_INFO MpKCPInfo;
-+ //Realwow--------------
-+#endif //ENABLE_REALWOW_SUPPORT
-+
-+#ifdef ENABLE_R8168_PROCFS
-+ //Procfs support
-+ struct proc_dir_entry *proc_dir;
-+#endif
-+};
-+
-+enum eetype {
-+ EEPROM_TYPE_NONE=0,
-+ EEPROM_TYPE_93C46,
-+ EEPROM_TYPE_93C56,
-+ EEPROM_TWSI
-+};
-+
-+enum mcfg {
-+ CFG_METHOD_1=0,
-+ CFG_METHOD_2,
-+ CFG_METHOD_3,
-+ CFG_METHOD_4,
-+ CFG_METHOD_5,
-+ CFG_METHOD_6,
-+ CFG_METHOD_7,
-+ CFG_METHOD_8,
-+ CFG_METHOD_9 ,
-+ CFG_METHOD_10,
-+ CFG_METHOD_11,
-+ CFG_METHOD_12,
-+ CFG_METHOD_13,
-+ CFG_METHOD_14,
-+ CFG_METHOD_15,
-+ CFG_METHOD_16,
-+ CFG_METHOD_17,
-+ CFG_METHOD_18,
-+ CFG_METHOD_19,
-+ CFG_METHOD_20,
-+ CFG_METHOD_21,
-+ CFG_METHOD_22,
-+ CFG_METHOD_23,
-+ CFG_METHOD_24,
-+ CFG_METHOD_25,
-+ CFG_METHOD_26,
-+ CFG_METHOD_27,
-+ CFG_METHOD_28,
-+ CFG_METHOD_29,
-+ CFG_METHOD_30,
-+ CFG_METHOD_MAX,
-+ CFG_METHOD_DEFAULT = 0xFF
-+};
-+
-+#define OOB_CMD_RESET 0x00
-+#define OOB_CMD_DRIVER_START 0x05
-+#define OOB_CMD_DRIVER_STOP 0x06
-+#define OOB_CMD_SET_IPMAC 0x41
-+
-+
-+//Ram Code Version
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_14 (0x0057)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_16 (0x0055)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_18 (0x0044)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_20 (0x0044)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_21 (0x0042)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_24 (0x0001)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_23 (0x0015)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_26 (0x0012)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_28 (0x0010)
-+#define NIC_RAMCODE_VERSION_CFG_METHOD_29 (0x0018)
-+
-+//hwoptimize
-+#define HW_PATCH_SAMSUNG_LAN_DONGLE (BIT_2)
-+
-+void mdio_write(struct rtl8168_private *tp, u32 RegAddr, u32 value);
-+void mdio_prot_write(struct rtl8168_private *tp, u32 RegAddr, u32 value);
-+void rtl8168_ephy_write(void __iomem *ioaddr, int RegAddr, int value);
-+void mac_ocp_write(struct rtl8168_private *tp, u16 reg_addr, u16 value);
-+u16 mac_ocp_read(struct rtl8168_private *tp, u16 reg_addr);
-+void ClearEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask);
-+void SetEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask);
-+void OCP_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 data);
-+void OOB_notify(struct rtl8168_private *tp, u8 cmd);
-+void rtl8168_init_ring_indexes(struct rtl8168_private *tp);
-+void rtl8168_wait_ll_share_fifo_ready(struct net_device *dev);
-+int rtl8168_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type);
-+void OOB_mutex_lock(struct rtl8168_private *tp);
-+u32 mdio_read(struct rtl8168_private *tp, u32 RegAddr);
-+u32 OCP_read(struct rtl8168_private *tp, u16 addr, u8 len);
-+u32 rtl8168_eri_read(void __iomem *ioaddr, int addr, int len, int type);
-+u16 rtl8168_ephy_read(void __iomem *ioaddr, int RegAddr);
-+void rtl8168_hw_disable_mac_mcu_bps(struct net_device *dev);
-+void rtl8168_wait_txrx_fifo_empty(struct net_device *dev);
-+void EnableNowIsOob(struct rtl8168_private *tp);
-+void DisableNowIsOob(struct rtl8168_private *tp);
-+void OOB_mutex_unlock(struct rtl8168_private *tp);
-+void Dash2DisableTx(struct rtl8168_private *tp);
-+void Dash2EnableTx(struct rtl8168_private *tp);
-+void Dash2DisableRx(struct rtl8168_private *tp);
-+void Dash2EnableRx(struct rtl8168_private *tp);
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
-+#define netdev_mc_count(dev) ((dev)->mc_count)
-+#define netdev_mc_empty(dev) (netdev_mc_count(dev) == 0)
-+#define netdev_for_each_mc_addr(mclist, dev) \
-+ for (mclist = dev->mc_list; mclist; mclist = mclist->next)
-+#endif
-diff --git a/drivers/net/ethernet/realtek/r8168_asf.c b/drivers/net/ethernet/realtek/r8168_asf.c
-new file mode 100755
-index 0000000..ac7e343
---- /dev/null
-+++ b/drivers/net/ethernet/realtek/r8168_asf.c
-@@ -0,0 +1,419 @@
-+/*
-+################################################################################
-+#
-+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
-+# controllers with PCI-Express interface.
-+#
-+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved.
-+#
-+# This program is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by the Free
-+# Software Foundation; either version 2 of the License, or (at your option)
-+# any later version.
-+#
-+# This program is distributed in the hope that it will be useful, but WITHOUT
-+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+# more details.
-+#
-+# You should have received a copy of the GNU General Public License along with
-+# this program; if not, see <http://www.gnu.org/licenses/>.
-+#
-+# Author:
-+# Realtek NIC software team <nicfae@realtek.com>
-+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
-+#
-+################################################################################
-+*/
-+
-+/************************************************************************************
-+ * This product is covered by one or more of the following patents:
-+ * US6,570,884, US6,115,776, and US6,327,625.
-+ ***********************************************************************************/
-+
-+#include <linux/module.h>
-+#include <linux/version.h>
-+#include <linux/pci.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/delay.h>
-+#include <linux/ethtool.h>
-+#include <linux/mii.h>
-+#include <linux/if_vlan.h>
-+#include <linux/crc32.h>
-+#include <linux/in.h>
-+#include <linux/ip.h>
-+#include <linux/tcp.h>
-+#include <linux/init.h>
-+#include <linux/rtnetlink.h>
-+
-+#include <asm/uaccess.h>
-+
-+#include "r8168.h"
-+#include "r8168_asf.h"
-+#include "rtl_eeprom.h"
-+
-+int rtl8168_asf_ioctl(struct net_device *dev,
-+ struct ifreq *ifr)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ void *user_data = ifr->ifr_data;
-+ struct asf_ioctl_struct asf_usrdata;
-+
-+ if (tp->mcfg != CFG_METHOD_7 && tp->mcfg != CFG_METHOD_8)
-+ return -EOPNOTSUPP;
-+
-+ if (copy_from_user(&asf_usrdata, user_data, sizeof(struct asf_ioctl_struct)))
-+ return -EFAULT;
-+
-+ switch (asf_usrdata.offset) {
-+ case HBPeriod:
-+ rtl8168_asf_hbperiod(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
-+ break;
-+ case WD8Timer:
-+ break;
-+ case WD16Rst:
-+ rtl8168_asf_wd16rst(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
-+ break;
-+ case WD8Rst:
-+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, WD8Rst, asf_usrdata.u.data);
-+ break;
-+ case LSnsrPollCycle:
-+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, LSnsrPollCycle, asf_usrdata.u.data);
-+ break;
-+ case ASFSnsrPollPrd:
-+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, ASFSnsrPollPrd, asf_usrdata.u.data);
-+ break;
-+ case AlertReSendItvl:
-+ rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, AlertReSendItvl, asf_usrdata.u.data);
-+ break;
-+ case SMBAddr:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, SMBAddr, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case ASFConfigR0:
-+ rtl8168_asf_config_regs(ioaddr, asf_usrdata.arg, ASFConfigR0, asf_usrdata.u.data);
-+ break;
-+ case ASFConfigR1:
-+ rtl8168_asf_config_regs(ioaddr, asf_usrdata.arg, ASFConfigR1, asf_usrdata.u.data);
-+ break;
-+ case ConsoleMA:
-+ rtl8168_asf_console_mac(tp, asf_usrdata.arg, asf_usrdata.u.data);
-+ break;
-+ case ConsoleIP:
-+ rtl8168_asf_ip_address(ioaddr, asf_usrdata.arg, ConsoleIP, asf_usrdata.u.data);
-+ break;
-+ case IPAddr:
-+ rtl8168_asf_ip_address(tp, asf_usrdata.arg, IPAddr, asf_usrdata.u.data);
-+ break;
-+ case UUID:
-+ rtl8168_asf_rw_uuid(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
-+ break;
-+ case IANA:
-+ rtl8168_asf_rw_iana(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
-+ break;
-+ case SysID:
-+ rtl8168_asf_rw_systemid(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
-+ break;
-+ case Community:
-+ rtl8168_asf_community_string(ioaddr, asf_usrdata.arg, asf_usrdata.u.string);
-+ break;
-+ case StringLength:
-+ rtl8168_asf_community_string_len(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
-+ break;
-+ case FmCapMsk:
-+ rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, FmCapMsk, asf_usrdata.u.data);
-+ break;
-+ case SpCMDMsk:
-+ rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, SpCMDMsk, asf_usrdata.u.data);
-+ break;
-+ case SysCapMsk:
-+ rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, SysCapMsk, asf_usrdata.u.data);
-+ break;
-+ case RmtRstAddr:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstAddr, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtRstCmd:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstCmd, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtRstData:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstData, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPwrOffAddr:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffAddr, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPwrOffCmd:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffCmd, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPwrOffData:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffData, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPwrOnAddr:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnAddr, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPwrOnCmd:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnCmd, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPwrOnData:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnData, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPCRAddr:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRAddr, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPCRCmd:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRCmd, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case RmtPCRData:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRData, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case ASFSnsr0Addr:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, ASFSnsr0Addr, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case LSnsrAddr0:
-+ rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, LSnsrAddr0, RW_ONE_BYTE, asf_usrdata.u.data);
-+ break;
-+ case KO:
-+ /* Get/Set Key Operation */
-+ rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KO, asf_usrdata.u.data);
-+ break;
-+ case KA:
-+ /* Get/Set Key Administrator */
-+ rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KA, asf_usrdata.u.data);
-+ break;
-+ case KG:
-+ /* Get/Set Key Generation */
-+ rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KG, asf_usrdata.u.data);
-+ break;
-+ case KR:
-+ /* Get/Set Key Random */
-+ rtl8168_asf_key_access(tp, asf_usrdata.arg, KR, asf_usrdata.u.data);
-+ break;
-+ default:
-+ return -EOPNOTSUPP;
-+ }
-+
-+ if (copy_to_user(user_data, &asf_usrdata, sizeof(struct asf_ioctl_struct)))
-+ return -EFAULT;
-+
-+ return 0;
-+}
-+
-+void rtl8168_asf_hbperiod(void __iomem *ioaddr, int arg, unsigned int *data)
-+{
-+ if (arg == ASF_GET)
-+ data[ASFHBPERIOD] = rtl8168_eri_read(ioaddr, HBPeriod, RW_TWO_BYTES, ERIAR_ASF);
-+ else if (arg == ASF_SET) {
-+ rtl8168_eri_write(ioaddr, HBPeriod, RW_TWO_BYTES, data[ASFHBPERIOD], ERIAR_ASF);
-+ rtl8168_eri_write(ioaddr, 0x1EC, RW_ONE_BYTE, 0x07, ERIAR_ASF);
-+ }
-+}
-+
-+void rtl8168_asf_wd16rst(void __iomem *ioaddr, int arg, unsigned int *data)
-+{
-+ data[ASFWD16RST] = rtl8168_eri_read(ioaddr, WD16Rst, RW_TWO_BYTES, ERIAR_ASF);
-+}
-+
-+void rtl8168_asf_console_mac(struct rtl8168_private *tp, int arg, unsigned int *data)
-+{
-+ void __iomem *ioaddr=tp->mmio_addr;
-+ int i;
-+
-+ if (arg == ASF_GET) {
-+ for (i = 0; i < 6; i++)
-+ data[i] = rtl8168_eri_read(ioaddr, ConsoleMA + i, RW_ONE_BYTE, ERIAR_ASF);
-+ } else if (arg == ASF_SET) {
-+ for (i = 0; i < 6; i++)
-+ rtl8168_eri_write(ioaddr, ConsoleMA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
-+
-+ /* write the new console MAC address to EEPROM */
-+ rtl_eeprom_write_sc(tp, 70, (data[1] << 8) | data[0]);
-+ rtl_eeprom_write_sc(tp, 71, (data[3] << 8) | data[2]);
-+ rtl_eeprom_write_sc(tp, 72, (data[5] << 8) | data[4]);
-+ }
-+}
-+
-+void rtl8168_asf_ip_address(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
-+{
-+ void __iomem *ioaddr=tp->mmio_addr;
-+ int i;
-+ int eeprom_off = 0;
-+
-+ if (arg == ASF_GET) {
-+ for (i = 0; i < 4; i++)
-+ data[i] = rtl8168_eri_read(ioaddr, offset + i, RW_ONE_BYTE, ERIAR_ASF);
-+ } else if (arg == ASF_SET) {
-+ for (i = 0; i < 4; i++)
-+ rtl8168_eri_write(ioaddr, offset + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
-+
-+ if (offset == ConsoleIP)
-+ eeprom_off = 73;
-+ else if (offset == IPAddr)
-+ eeprom_off = 75;
-+
-+ /* write the new IP address to EEPROM */
-+ rtl_eeprom_write_sc(tp, eeprom_off, (data[1] << 8) | data[0]);
-+ rtl_eeprom_write_sc(tp, eeprom_off + 1, (data[3] << 8) | data[2]);
-+
-+ }
-+}
-+
-+void rtl8168_asf_config_regs(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
-+{
-+ unsigned int value;
-+
-+ if (arg == ASF_GET) {
-+ data[ASFCAPABILITY] = (rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF) & data[ASFCONFIG]) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
-+ } else if (arg == ASF_SET) {
-+ value = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF);
-+
-+ if (data[ASFCAPABILITY] == FUNCTION_ENABLE)
-+ value |= data[ASFCONFIG];
-+ else if (data[ASFCAPABILITY] == FUNCTION_DISABLE)
-+ value &= ~data[ASFCONFIG];
-+
-+ rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, value, ERIAR_ASF);
-+ }
-+}
-+
-+void rtl8168_asf_capability_masks(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
-+{
-+ unsigned int len, bit_mask;
-+
-+ bit_mask = DISABLE_MASK;
-+
-+ if (offset == FmCapMsk) {
-+ /* System firmware capabilities */
-+ len = RW_FOUR_BYTES;
-+ if (data[ASFCAPMASK] == FUNCTION_ENABLE)
-+ bit_mask = FMW_CAP_MASK;
-+ } else if (offset == SpCMDMsk) {
-+ /* Special commands */
-+ len = RW_TWO_BYTES;
-+ if (data[ASFCAPMASK] == FUNCTION_ENABLE)
-+ bit_mask = SPC_CMD_MASK;
-+ } else {
-+ /* System capability (offset == SysCapMsk)*/
-+ len = RW_ONE_BYTE;
-+ if (data[ASFCAPMASK] == FUNCTION_ENABLE)
-+ bit_mask = SYS_CAP_MASK;
-+ }
-+
-+ if (arg == ASF_GET)
-+ data[ASFCAPMASK] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
-+ else /* arg == ASF_SET */
-+ rtl8168_eri_write(ioaddr, offset, len, bit_mask, ERIAR_ASF);
-+}
-+
-+void rtl8168_asf_community_string(void __iomem *ioaddr, int arg, char *string)
-+{
-+ int i;
-+
-+ if (arg == ASF_GET) {
-+ for (i = 0; i < COMMU_STR_MAX_LEN; i++)
-+ string[i] = rtl8168_eri_read(ioaddr, Community + i, RW_ONE_BYTE, ERIAR_ASF);
-+ } else { /* arg == ASF_SET */
-+ for (i = 0; i < COMMU_STR_MAX_LEN; i++)
-+ rtl8168_eri_write(ioaddr, Community + i, RW_ONE_BYTE, string[i], ERIAR_ASF);
-+ }
-+}
-+
-+void rtl8168_asf_community_string_len(void __iomem *ioaddr, int arg, unsigned int *data)
-+{
-+ if (arg == ASF_GET)
-+ data[ASFCOMMULEN] = rtl8168_eri_read(ioaddr, StringLength, RW_ONE_BYTE, ERIAR_ASF);
-+ else /* arg == ASF_SET */
-+ rtl8168_eri_write(ioaddr, StringLength, RW_ONE_BYTE, data[ASFCOMMULEN], ERIAR_ASF);
-+}
-+
-+void rtl8168_asf_time_period(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
-+{
-+ int pos = 0;
-+
-+ if (offset == WD8Rst)
-+ pos = ASFWD8RESET;
-+ else if (offset == LSnsrPollCycle)
-+ pos = ASFLSNRPOLLCYC;
-+ else if (offset == ASFSnsrPollPrd)
-+ pos = ASFSNRPOLLCYC;
-+ else if (offset == AlertReSendItvl)
-+ pos = ASFALERTRESND;
-+
-+ if (arg == ASF_GET)
-+ data[pos] = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF);
-+ else /* arg == ASF_SET */
-+ rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, data[pos], ERIAR_ASF);
-+
-+}
-+
-+void rtl8168_asf_key_access(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
-+{
-+ void __iomem *ioaddr=tp->mmio_addr;
-+ int i, j;
-+ int key_off = 0;
-+
-+ if (arg == ASF_GET) {
-+ for (i = 0; i < KEY_LEN; i++)
-+ data[i] = rtl8168_eri_read(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, ERIAR_ASF);
-+ } else {
-+ if (offset == KO)
-+ key_off = 162;
-+ else if (offset == KA)
-+ key_off = 172;
-+ else if (offset == KG)
-+ key_off = 182;
-+ else if (offset == KR)
-+ key_off = 192;
-+
-+ /* arg == ASF_SET */
-+ for (i = 0; i < KEY_LEN; i++)
-+ rtl8168_eri_write(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, data[i], ERIAR_ASF);
-+
-+ /* write the new key to EEPROM */
-+ for (i = 0, j = 19; i < 10; i++, j = j - 2)
-+ rtl_eeprom_write_sc(tp, key_off + i, (data[j - 1] << 8) | data[j]);
-+ }
-+}
-+
-+void rtl8168_asf_rw_hexadecimal(void __iomem *ioaddr, int arg, int offset, int len, unsigned int *data)
-+{
-+ if (arg == ASF_GET)
-+ data[ASFRWHEXNUM] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF);
-+ else /* arg == ASF_SET */
-+ rtl8168_eri_write(ioaddr, offset, len, data[ASFRWHEXNUM], ERIAR_ASF);
-+}
-+
-+void rtl8168_asf_rw_systemid(void __iomem *ioaddr, int arg, unsigned int *data)
-+{
-+ int i;
-+
-+ if (arg == ASF_GET)
-+ for (i = 0; i < SYSID_LEN ; i++)
-+ data[i] = rtl8168_eri_read(ioaddr, SysID + i, RW_ONE_BYTE, ERIAR_ASF);
-+ else /* arg == ASF_SET */
-+ for (i = 0; i < SYSID_LEN ; i++)
-+ rtl8168_eri_write(ioaddr, SysID + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
-+}
-+
-+void rtl8168_asf_rw_iana(void __iomem *ioaddr, int arg, unsigned int *data)
-+{
-+ int i;
-+
-+ if (arg == ASF_GET)
-+ for (i = 0; i < RW_FOUR_BYTES; i++)
-+ data[i] = rtl8168_eri_read(ioaddr, IANA + i, RW_ONE_BYTE, ERIAR_ASF);
-+ else /* arg == ASF_SET */
-+ for (i = 0; i < RW_FOUR_BYTES; i++)
-+ rtl8168_eri_write(ioaddr, IANA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
-+}
-+
-+void rtl8168_asf_rw_uuid(void __iomem *ioaddr, int arg, unsigned int *data)
-+{
-+ int i, j;
-+
-+ if (arg == ASF_GET)
-+ for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++)
-+ data[j] = rtl8168_eri_read(ioaddr, UUID + i, RW_ONE_BYTE, ERIAR_ASF);
-+ else /* arg == ASF_SET */
-+ for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++)
-+ rtl8168_eri_write(ioaddr, UUID + i, RW_ONE_BYTE, data[j], ERIAR_ASF);
-+}
-diff --git a/drivers/net/ethernet/realtek/r8168_asf.h b/drivers/net/ethernet/realtek/r8168_asf.h
-new file mode 100755
-index 0000000..e4097f2
---- /dev/null
-+++ b/drivers/net/ethernet/realtek/r8168_asf.h
-@@ -0,0 +1,294 @@
-+/*
-+################################################################################
-+#
-+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
-+# controllers with PCI-Express interface.
-+#
-+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved.
-+#
-+# This program is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by the Free
-+# Software Foundation; either version 2 of the License, or (at your option)
-+# any later version.
-+#
-+# This program is distributed in the hope that it will be useful, but WITHOUT
-+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+# more details.
-+#
-+# You should have received a copy of the GNU General Public License along with
-+# this program; if not, see <http://www.gnu.org/licenses/>.
-+#
-+# Author:
-+# Realtek NIC software team <nicfae@realtek.com>
-+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
-+#
-+################################################################################
-+*/
-+
-+/************************************************************************************
-+ * This product is covered by one or more of the following patents:
-+ * US6,570,884, US6,115,776, and US6,327,625.
-+ ***********************************************************************************/
-+
-+#define SIOCDEVPRIVATE_RTLASF SIOCDEVPRIVATE
-+
-+#define FUNCTION_ENABLE 1
-+#define FUNCTION_DISABLE 0
-+
-+#define ASFCONFIG 0
-+#define ASFCAPABILITY 1
-+#define ASFCOMMULEN 0
-+#define ASFHBPERIOD 0
-+#define ASFWD16RST 0
-+#define ASFCAPMASK 0
-+#define ASFALERTRESND 0
-+#define ASFLSNRPOLLCYC 0
-+#define ASFSNRPOLLCYC 0
-+#define ASFWD8RESET 0
-+#define ASFRWHEXNUM 0
-+
-+#define FMW_CAP_MASK 0x0000F867
-+#define SPC_CMD_MASK 0x1F00
-+#define SYS_CAP_MASK 0xFF
-+#define DISABLE_MASK 0x00
-+
-+#define MAX_DATA_LEN 200
-+#define MAX_STR_LEN 200
-+
-+#define COMMU_STR_MAX_LEN 23
-+
-+#define KEY_LEN 20
-+#define UUID_LEN 16
-+#define SYSID_LEN 2
-+
-+#define RW_ONE_BYTE 1
-+#define RW_TWO_BYTES 2
-+#define RW_FOUR_BYTES 4
-+
-+enum asf_registers {
-+ HBPeriod = 0x0000,
-+ WD8Rst = 0x0002,
-+ WD8Timer = 0x0003,
-+ WD16Rst = 0x0004,
-+ LSnsrPollCycle = 0x0006,
-+ ASFSnsrPollPrd = 0x0007,
-+ AlertReSendCnt = 0x0008,
-+ AlertReSendItvl = 0x0009,
-+ SMBAddr = 0x000A,
-+ SMBCap = 0x000B,
-+ ASFConfigR0 = 0x000C,
-+ ASFConfigR1 = 0x000D,
-+ WD16Timer = 0x000E,
-+ ConsoleMA = 0x0010,
-+ ConsoleIP = 0x0016,
-+ IPAddr = 0x001A,
-+
-+ UUID = 0x0020,
-+ IANA = 0x0030,
-+ SysID = 0x0034,
-+ Community = 0x0036,
-+ StringLength = 0x004D,
-+ LC = 0x004E,
-+ EntityInst = 0x004F,
-+ FmCapMsk = 0x0050,
-+ SpCMDMsk = 0x0054,
-+ SysCapMsk = 0x0056,
-+ WDSysSt = 0x0057,
-+ RxMsgType = 0x0058,
-+ RxSpCMD = 0x0059,
-+ RxSpCMDPa = 0x005A,
-+ RxBtOpMsk = 0x005C,
-+ RmtRstAddr = 0x005E,
-+ RmtRstCmd = 0x005F,
-+ RmtRstData = 0x0060,
-+ RmtPwrOffAddr = 0x0061,
-+ RmtPwrOffCmd = 0x0062,
-+ RmtPwrOffData = 0x0063,
-+ RmtPwrOnAddr = 0x0064,
-+ RmtPwrOnCmd = 0x0065,
-+ RmtPwrOnData = 0x0066,
-+ RmtPCRAddr = 0x0067,
-+ RmtPCRCmd = 0x0068,
-+ RmtPCRData = 0x0069,
-+ RMCP_IANA = 0x006A,
-+ RMCP_OEM = 0x006E,
-+ ASFSnsr0Addr = 0x0070,
-+
-+ ASFSnsrEvSt = 0x0073,
-+ ASFSnsrEvAlert = 0x0081,
-+
-+ LSnsrNo = 0x00AD,
-+ AssrtEvntMsk = 0x00AE,
-+ DeAssrtEvntMsk = 0x00AF,
-+
-+ LSnsrAddr0 = 0x00B0,
-+ LAlertCMD0 = 0x00B1,
-+ LAlertDataMsk0 = 0x00B2,
-+ LAlertCmp0 = 0x00B3,
-+ LAlertESnsrT0 = 0x00B4,
-+ LAlertET0 = 0x00B5,
-+ LAlertEOffset0 = 0x00B6,
-+ LAlertES0 = 0x00B7,
-+ LAlertSN0 = 0x00B8,
-+ LAlertEntity0 = 0x00B9,
-+ LAlertEI0 = 0x00BA,
-+ LSnsrState0 = 0x00BB,
-+
-+ LSnsrAddr1 = 0x00BD,
-+ LAlertCMD1 = 0x00BE,
-+ LAlertDataMsk1 = 0x00BF,
-+ LAlertCmp1 = 0x00C0,
-+ LAlertESnsrT1 = 0x00C1,
-+ LAlertET1 = 0x00C2,
-+ LAlertEOffset1 = 0x00C3,
-+ LAlertES1 = 0x00C4,
-+ LAlertSN1 = 0x00C5,
-+ LAlertEntity1 = 0x00C6,
-+ LAlertEI1 = 0x00C7,
-+ LSnsrState1 = 0x00C8,
-+
-+ LSnsrAddr2 = 0x00CA,
-+ LAlertCMD2 = 0x00CB,
-+ LAlertDataMsk2 = 0x00CC,
-+ LAlertCmp2 = 0x00CD,
-+ LAlertESnsrT2 = 0x00CE,
-+ LAlertET2 = 0x00CF,
-+ LAlertEOffset2 = 0x00D0,
-+ LAlertES2 = 0x00D1,
-+ LAlertSN2 = 0x00D2,
-+ LAlertEntity2 = 0x00D3,
-+ LAlertEI2 = 0x00D4,
-+ LSnsrState2 = 0x00D5,
-+
-+ LSnsrAddr3 = 0x00D7,
-+ LAlertCMD3 = 0x00D8,
-+ LAlertDataMsk3 = 0x00D9,
-+ LAlertCmp3 = 0x00DA,
-+ LAlertESnsrT3 = 0x00DB,
-+ LAlertET3 = 0x00DC,
-+ LAlertEOffset3 = 0x00DD,
-+ LAlertES3 = 0x00DE,
-+ LAlertSN3 = 0x00DF,
-+ LAlertEntity3 = 0x00E0,
-+ LAlertEI3 = 0x00E1,
-+ LSnsrState3 = 0x00E2,
-+
-+ LSnsrAddr4 = 0x00E4,
-+ LAlertCMD4 = 0x00E5,
-+ LAlertDataMsk4 = 0x00E6,
-+ LAlertCmp4 = 0x00E7,
-+ LAlertESnsrT4 = 0x00E8,
-+ LAlertET4 = 0x00E9,
-+ LAlertEOffset4 = 0x00EA,
-+ LAlertES4 = 0x00EB,
-+ LAlertSN4 = 0x00EC,
-+ LAlertEntity4 = 0x00ED,
-+ LAlertEI4 = 0x00EE,
-+ LSnsrState4 = 0x00EF,
-+
-+ LSnsrAddr5 = 0x00F1,
-+ LAlertCMD5 = 0x00F2,
-+ LAlertDataMsk5 = 0x00F3,
-+ LAlertCmp5 = 0x00F4,
-+ LAlertESnsrT5 = 0x00F5,
-+ LAlertET5 = 0x00F6,
-+ LAlertEOffset5 = 0x00F7,
-+ LAlertES5 = 0x00F8,
-+ LAlertSN5 = 0x00F9,
-+ LAlertEntity5 = 0x00FA,
-+ LAlertEI5 = 0x00FB,
-+ LSnsrState5 = 0x00FC,
-+
-+ LSnsrAddr6 = 0x00FE,
-+ LAlertCMD6 = 0x00FF,
-+ LAlertDataMsk6 = 0x0100,
-+ LAlertCmp6 = 0x0101,
-+ LAlertESnsrT6 = 0x0102,
-+ LAlertET6 = 0x0103,
-+ LAlertEOffset6 = 0x0104,
-+ LAlertES6 = 0x0105,
-+ LAlertSN6 = 0x0106,
-+ LAlertEntity6 = 0x0107,
-+ LAlertEI6 = 0x0108,
-+ LSnsrState6 = 0x0109,
-+
-+ LSnsrAddr7 = 0x010B,
-+ LAlertCMD7 = 0x010C,
-+ LAlertDataMsk7 = 0x010D,
-+ LAlertCmp7 = 0x010E,
-+ LAlertESnsrT7 = 0x010F,
-+ LAlertET7 = 0x0110,
-+ LAlertEOffset7 = 0x0111,
-+ LAlertES7 = 0x0112,
-+ LAlertSN7 = 0x0113,
-+ LAlertEntity7 = 0x0114,
-+ LAlertEI7 = 0x0115,
-+ LSnsrState7 = 0x0116,
-+ LAssert = 0x0117,
-+ LDAssert = 0x0118,
-+ IPServiceType = 0x0119,
-+ IPIdfr = 0x011A,
-+ FlagFOffset = 0x011C,
-+ TTL = 0x011E,
-+ HbtEI = 0x011F,
-+ MgtConSID1 = 0x0120,
-+ MgtConSID2 = 0x0124,
-+ MgdCltSID = 0x0128,
-+ StCd = 0x012C,
-+ MgtConUR = 0x012D,
-+ MgtConUNL = 0x012E,
-+
-+ AuthPd = 0x0130,
-+ IntyPd = 0x0138,
-+ MgtConRN = 0x0140,
-+ MgdCtlRN = 0x0150,
-+ MgtConUN = 0x0160,
-+ Rakp2IntCk = 0x0170,
-+ KO = 0x017C,
-+ KA = 0x0190,
-+ KG = 0x01A4,
-+ KR = 0x01B8,
-+ CP = 0x01CC,
-+ CQ = 0x01D0,
-+ KC = 0x01D4,
-+ ConsoleSid = 0x01E8,
-+
-+ SIK1 = 0x01FC,
-+ SIK2 = 0x0210,
-+ Udpsrc_port = 0x0224,
-+ Udpdes_port = 0x0226,
-+ Asf_debug_mux = 0x0228
-+};
-+
-+enum asf_cmdln_opt {
-+ ASF_GET,
-+ ASF_SET,
-+ ASF_HELP
-+};
-+
-+struct asf_ioctl_struct {
-+ unsigned int arg;
-+ unsigned int offset;
-+ union {
-+ unsigned int data[MAX_DATA_LEN];
-+ char string[MAX_STR_LEN];
-+ } u;
-+};
-+
-+int rtl8168_asf_ioctl(struct net_device *dev, struct ifreq *ifr);
-+void rtl8168_asf_hbperiod(void __iomem *ioaddr, int arg, unsigned int *data);
-+void rtl8168_asf_wd16rst(void __iomem *ioaddr, int arg, unsigned int *data);
-+void rtl8168_asf_console_mac(struct rtl8168_private *, int arg, unsigned int *data);
-+void rtl8168_asf_ip_address(struct rtl8168_private *, int arg, int offset, unsigned int *data);
-+void rtl8168_asf_config_regs(void __iomem *ioaddr, int arg, int offset, unsigned int *data);
-+void rtl8168_asf_capability_masks(void __iomem *ioaddr, int arg, int offset, unsigned int *data);
-+void rtl8168_asf_community_string(void __iomem *ioaddr, int arg, char *string);
-+void rtl8168_asf_community_string_len(void __iomem *ioaddr, int arg, unsigned int *data);
-+void rtl8168_asf_alert_resend_interval(void __iomem *ioaddr, int arg, unsigned int *data);
-+void rtl8168_asf_time_period(void __iomem *ioaddr, int arg, int offset, unsigned int *data);
-+void rtl8168_asf_key_access(struct rtl8168_private *, int arg, int offset, unsigned int *data);
-+void rtl8168_asf_rw_hexadecimal(void __iomem *ioaddr, int arg, int offset, int len, unsigned int *data);
-+void rtl8168_asf_rw_iana(void __iomem *ioaddr, int arg, unsigned int *data);
-+void rtl8168_asf_rw_uuid(void __iomem *ioaddr, int arg, unsigned int *data);
-+void rtl8168_asf_rw_systemid(void __iomem *ioaddr, int arg, unsigned int *data);
-diff --git a/drivers/net/ethernet/realtek/r8168_dash.h b/drivers/net/ethernet/realtek/r8168_dash.h
-new file mode 100755
-index 0000000..19fac01
---- /dev/null
-+++ b/drivers/net/ethernet/realtek/r8168_dash.h
-@@ -0,0 +1,193 @@
-+/*
-+################################################################################
-+#
-+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
-+# controllers with PCI-Express interface.
-+#
-+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved.
-+#
-+# This program is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by the Free
-+# Software Foundation; either version 2 of the License, or (at your option)
-+# any later version.
-+#
-+# This program is distributed in the hope that it will be useful, but WITHOUT
-+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+# more details.
-+#
-+# You should have received a copy of the GNU General Public License along with
-+# this program; if not, see <http://www.gnu.org/licenses/>.
-+#
-+# Author:
-+# Realtek NIC software team <nicfae@realtek.com>
-+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
-+#
-+################################################################################
-+*/
-+
-+/************************************************************************************
-+ * This product is covered by one or more of the following patents:
-+ * US6,570,884, US6,115,776, and US6,327,625.
-+ ***********************************************************************************/
-+
-+#ifndef _LINUX_R8168_DASH_H
-+#define _LINUX_R8168_DASH_H
-+
-+#define SIOCDEVPRIVATE_RTLDASH SIOCDEVPRIVATE+2
-+
-+enum rtl_dash_cmd {
-+
-+ RTL_DASH_ARP_NS_OFFLOAD=0,
-+ RTL_DASH_SET_OOB_IPMAC,
-+ RTL_DASH_NOTIFY_OOB,
-+
-+ RTL_DASH_SEND_BUFFER_DATA_TO_DASH_FW,
-+ RTL_DASH_CHECK_SEND_BUFFER_TO_DASH_FW_COMPLETE,
-+ RTL_DASH_GET_RCV_FROM_FW_BUFFER_DATA,
-+
-+ RTLT_DASH_COMMAND_INVALID
-+};
-+
-+struct rtl_dash_ip_mac {
-+ struct sockaddr ifru_addr;
-+ struct sockaddr ifru_netmask;
-+ struct sockaddr ifru_hwaddr;
-+};
-+
-+struct rtl_dash_ioctl_struct {
-+ __u32 cmd;
-+ __u32 offset;
-+ __u32 len;
-+ union {
-+ __u32 data;
-+ void *data_buffer;
-+ };
-+};
-+
-+typedef struct _RX_DASH_FROM_FW_DESC {
-+ u16 length;
-+ u8 statusLowByte;
-+ u8 statusHighByte;
-+ u32 resv;
-+ u64 BufferAddress;
-+}
-+RX_DASH_FROM_FW_DESC, *PRX_DASH_FROM_FW_DESC;
-+
-+typedef struct _TX_DASH_SEND_FW_DESC {
-+ u16 length;
-+ u8 statusLowByte;
-+ u8 statusHighByte;
-+ u32 resv;
-+ u64 BufferAddress;
-+}
-+TX_DASH_SEND_FW_DESC, *PTX_DASH_SEND_FW_DESC;
-+
-+typedef struct _OSOOBHdr {
-+ u32 len;
-+ u8 type;
-+ u8 flag;
-+ u8 hostReqV;
-+ u8 res;
-+}
-+OSOOBHdr, *POSOOBHdr;
-+
-+typedef struct _RX_DASH_BUFFER_TYPE_2 {
-+ OSOOBHdr oobhdr;
-+ void *RxDataBuffer;
-+}
-+RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2;
-+
-+#define ALIGN_8 (0x7)
-+#define ALIGN_16 (0xf)
-+#define ALIGN_32 (0x1f)
-+#define ALIGN_64 (0x3f)
-+#define ALIGN_256 (0xff)
-+#define ALIGN_4096 (0xfff)
-+
-+#define OCP_REG_CONFIG0 (0x10)
-+#define OCP_REG_CONFIG0_REV_F (0xB8)
-+#define OCP_REG_DASH_POLL (0x30)
-+#define OCP_REG_HOST_REQ (0x34)
-+#define OCP_REG_DASH_REQ (0x35)
-+#define OCP_REG_CR (0x36)
-+#define OCP_REG_DMEMSTA (0x38)
-+#define OCP_REG_GPHYAR (0x60)
-+
-+
-+#define OCP_REG_CONFIG0_DASHEN BIT_15
-+#define OCP_REG_CONFIG0_OOBRESET BIT_14
-+#define OCP_REG_CONFIG0_APRDY BIT_13
-+#define OCP_REG_CONFIG0_FIRMWARERDY BIT_12
-+#define OCP_REG_CONFIG0_DRIVERRDY BIT_11
-+#define OCP_REG_CONFIG0_OOB_WDT BIT_9
-+#define OCP_REG_CONFIG0_DRV_WAIT_OOB BIT_8
-+#define OCP_REG_CONFIG0_TLSEN BIT_7
-+
-+#define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0 )
-+#define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1 )
-+#define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2 )
-+
-+#define RECV_FROM_FW_BUF_SIZE (1518)
-+#define SEND_TO_FW_BUF_SIZE (1518)
-+
-+#define RX_DASH_FROM_FW_OWN BIT_15
-+#define TX_DASH_SEND_FW_OWN BIT_15
-+#define TX_DASH_SEND_FW_OWN_HIGHBYTE BIT_7
-+
-+#define TXS_CC3_0 (BIT_0|BIT_1|BIT_2|BIT_3)
-+#define TXS_EXC BIT_4
-+#define TXS_LNKF BIT_5
-+#define TXS_OWC BIT_6
-+#define TXS_TES BIT_7
-+#define TXS_UNF BIT_9
-+#define TXS_LGSEN BIT_11
-+#define TXS_LS BIT_12
-+#define TXS_FS BIT_13
-+#define TXS_EOR BIT_14
-+#define TXS_OWN BIT_15
-+
-+#define TPPool_HRDY 0x20
-+
-+#define HostReqReg (0xC0)
-+#define SystemMasterDescStartAddrLow (0xF0)
-+#define SystemMasterDescStartAddrHigh (0xF4)
-+#define SystemSlaveDescStartAddrLow (0xF8)
-+#define SystemSlaveDescStartAddrHigh (0xFC)
-+
-+//DASH Request Type
-+#define WSMANREG 0x01
-+#define OSPUSHDATA 0x02
-+
-+#define RXS_OWN BIT_15
-+#define RXS_EOR BIT_14
-+#define RXS_FS BIT_13
-+#define RXS_LS BIT_12
-+
-+#define ISRIMR_DP_DASH_OK BIT_15
-+#define ISRIMR_DP_HOST_OK BIT_13
-+#define ISRIMR_DP_REQSYS_OK BIT_11
-+
-+#define ISRIMR_DASH_INTR_EN BIT_12
-+#define ISRIMR_DASH_INTR_CMAC_RESET BIT_15
-+
-+#define ISRIMR_DASH_TYPE2_ROK BIT_0
-+#define ISRIMR_DASH_TYPE2_RDU BIT_1
-+#define ISRIMR_DASH_TYPE2_TOK BIT_2
-+#define ISRIMR_DASH_TYPE2_TDU BIT_3
-+#define ISRIMR_DASH_TYPE2_TX_FIFO_FULL BIT_4
-+#define ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE BIT_5
-+#define ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE BIT_6
-+
-+#define CMAC_OOB_STOP 0x25
-+#define CMAC_OOB_INIT 0x26
-+#define CMAC_OOB_RESET 0x2a
-+
-+int rtl8168_dash_ioctl(struct net_device *dev, struct ifreq *ifr);
-+void HandleDashInterrupt(struct net_device *dev);
-+int AllocateDashShareMemory(struct net_device *dev);
-+void FreeAllocatedDashShareMemory(struct net_device *dev);
-+void DashHwInit(struct net_device *dev);
-+
-+
-+#endif /* _LINUX_R8168_DASH_H */
-\ No newline at end of file
-diff --git a/drivers/net/ethernet/realtek/r8168_n.c b/drivers/net/ethernet/realtek/r8168_n.c
-new file mode 100755
-index 0000000..8b08e63
---- /dev/null
-+++ b/drivers/net/ethernet/realtek/r8168_n.c
-@@ -0,0 +1,25364 @@
-+/*
-+################################################################################
-+#
-+# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
-+# controllers with PCI-Express interface.
-+#
-+# Copyright(c) 2015 Realtek Semiconductor Corp. All rights reserved.
-+#
-+# This program is free software; you can redistribute it and/or modify it
-+# under the terms of the GNU General Public License as published by the Free
-+# Software Foundation; either version 2 of the License, or (at your option)
-+# any later version.
-+#
-+# This program is distributed in the hope that it will be useful, but WITHOUT
-+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+# more details.
-+#
-+# You should have received a copy of the GNU General Public License along with
-+# this program; if not, see <http://www.gnu.org/licenses/>.
-+#
-+# Author:
-+# Realtek NIC software team <nicfae@realtek.com>
-+# No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
-+#
-+################################################################################
-+*/
-+
-+/************************************************************************************
-+ * This product is covered by one or more of the following patents:
-+ * US6,570,884, US6,115,776, and US6,327,625.
-+ ***********************************************************************************/
-+
-+/*
-+ * This driver is modified from r8169.c in Linux kernel 2.6.18
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/version.h>
-+#include <linux/pci.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/delay.h>
-+#include <linux/ethtool.h>
-+#include <linux/mii.h>
-+#include <linux/if_vlan.h>
-+#include <linux/crc32.h>
-+#include <linux/interrupt.h>
-+#include <linux/in.h>
-+#include <linux/ip.h>
-+#include <linux/tcp.h>
-+#include <linux/init.h>
-+#include <linux/rtnetlink.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
-+#include <linux/pci-aspm.h>
-+#endif
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37)
-+#include <linux/prefetch.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-+#define dev_printk(A,B,fmt,args...) printk(A fmt,##args)
-+#else
-+#include <linux/dma-mapping.h>
-+#include <linux/moduleparam.h>
-+#endif
-+
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/uaccess.h>
-+
-+#include "r8168.h"
-+#include "r8168_asf.h"
-+#include "rtl_eeprom.h"
-+#include "rtltool.h"
-+
-+#ifdef ENABLE_R8168_PROCFS
-+#include <linux/proc_fs.h>
-+#include <linux/seq_file.h>
-+#endif
-+
-+/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
-+static const int max_interrupt_work = 20;
-+
-+/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
-+ The RTL chips use a 64 element hash table based on the Ethernet CRC. */
-+static const int multicast_filter_limit = 32;
-+
-+#define _R(NAME,MAC,RCR,MASK, JumFrameSz) \
-+ { .name = NAME, .mcfg = MAC, .RCR_Cfg = RCR, .RxConfigMask = MASK, .jumbo_frame_sz = JumFrameSz }
-+
-+static const struct {
-+ const char *name;
-+ u8 mcfg;
-+ u32 RCR_Cfg;
-+ u32 RxConfigMask; /* Clears the bits supported by this chip */
-+ u32 jumbo_frame_sz;
-+} rtl_chip_info[] = {
-+ _R("RTL8168B/8111B",
-+ CFG_METHOD_1,
-+ (Reserved2_data << Reserved2_shift) | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_4k),
-+
-+ _R("RTL8168B/8111B",
-+ CFG_METHOD_2,
-+ (Reserved2_data << Reserved2_shift) | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_4k),
-+
-+ _R("RTL8168B/8111B",
-+ CFG_METHOD_3,
-+ (Reserved2_data << Reserved2_shift) | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_4k),
-+
-+ _R("RTL8168C/8111C",
-+ CFG_METHOD_4,
-+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_6k),
-+
-+ _R("RTL8168C/8111C",
-+ CFG_METHOD_5,
-+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_6k),
-+
-+ _R("RTL8168C/8111C",
-+ CFG_METHOD_6,
-+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_6k),
-+
-+ _R("RTL8168CP/8111CP",
-+ CFG_METHOD_7,
-+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_6k),
-+
-+ _R("RTL8168CP/8111CP",
-+ CFG_METHOD_8,
-+ RxCfg_128_int_en | RxCfg_fet_multi_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_6k),
-+
-+ _R("RTL8168D/8111D",
-+ CFG_METHOD_9,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168D/8111D",
-+ CFG_METHOD_10,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168DP/8111DP",
-+ CFG_METHOD_11,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168DP/8111DP",
-+ CFG_METHOD_12,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168DP/8111DP",
-+ CFG_METHOD_13,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168E/8111E",
-+ CFG_METHOD_14,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168E/8111E",
-+ CFG_METHOD_15,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168E-VL/8111E-VL",
-+ CFG_METHOD_16,
-+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e0080,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168E-VL/8111E-VL",
-+ CFG_METHOD_17,
-+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168F/8111F",
-+ CFG_METHOD_18,
-+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168F/8111F",
-+ CFG_METHOD_19,
-+ RxCfg_128_int_en | RxEarly_off_V1 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8411",
-+ CFG_METHOD_20,
-+ RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e1880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168G/8111G",
-+ CFG_METHOD_21,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168G/8111G",
-+ CFG_METHOD_22,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168EP/8111EP",
-+ CFG_METHOD_23,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168GU/8111GU",
-+ CFG_METHOD_24,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168GU/8111GU",
-+ CFG_METHOD_25,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("8411B",
-+ CFG_METHOD_26,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168EP/8111EP",
-+ CFG_METHOD_27,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168EP/8111EP",
-+ CFG_METHOD_28,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168H/8111H",
-+ CFG_METHOD_29,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("RTL8168H/8111H",
-+ CFG_METHOD_30,
-+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ Jumbo_Frame_9k),
-+
-+ _R("Unknown",
-+ CFG_METHOD_DEFAULT,
-+ (RX_DMA_BURST << RxCfgDMAShift),
-+ 0xff7e5880,
-+ RX_BUF_SIZE)
-+};
-+#undef _R
-+
-+#ifndef PCI_VENDOR_ID_DLINK
-+#define PCI_VENDOR_ID_DLINK 0x1186
-+#endif
-+
-+static struct pci_device_id rtl8168_pci_tbl[] = {
-+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), },
-+ { PCI_VENDOR_ID_DLINK, 0x4300, 0x1186, 0x4b10,},
-+ {0,},
-+};
-+
-+MODULE_DEVICE_TABLE(pci, rtl8168_pci_tbl);
-+
-+static int rx_copybreak = 200;
-+static int timer_count = 0x2600;
-+
-+static struct {
-+ u32 msg_enable;
-+} debug = { -1 };
-+
-+static unsigned short speed = SPEED_1000;
-+static int duplex = DUPLEX_FULL;
-+static int autoneg = AUTONEG_ENABLE;
-+#ifdef CONFIG_ASPM
-+static int aspm = 1;
-+#else
-+static int aspm = 0;
-+#endif
-+#ifdef ENABLE_S5WOL
-+static int s5wol = 1;
-+#else
-+static int s5wol = 0;
-+#endif
-+#ifdef ENABLE_EEE
-+static int eee_enable = 1;
-+#else
-+static int eee_enable = 0;
-+#endif
-+static ulong hwoptimize = 0;
-+
-+MODULE_AUTHOR("Realtek and the Linux r8168 crew <netdev@vger.kernel.org>");
-+MODULE_DESCRIPTION("RealTek RTL-8168 Gigabit Ethernet driver");
-+
-+module_param(speed, ushort, 0);
-+MODULE_PARM_DESC(speed, "force phy operation. Deprecated by ethtool (8).");
-+
-+module_param(duplex, int, 0);
-+MODULE_PARM_DESC(duplex, "force phy operation. Deprecated by ethtool (8).");
-+
-+module_param(autoneg, int, 0);
-+MODULE_PARM_DESC(autoneg, "force phy operation. Deprecated by ethtool (8).");
-+
-+module_param(aspm, int, 0);
-+MODULE_PARM_DESC(aspm, "Enable ASPM.");
-+
-+module_param(s5wol, int, 0);
-+MODULE_PARM_DESC(s5wol, "Enable Shutdown Wake On Lan.");
-+
-+module_param(rx_copybreak, int, 0);
-+MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
-+
-+module_param(timer_count, int, 0);
-+MODULE_PARM_DESC(timer_count, "Timer Interrupt Interval.");
-+
-+module_param(eee_enable, int, 0);
-+MODULE_PARM_DESC(eee_enable, "Enable Energy Efficient Ethernet.");
-+
-+module_param(hwoptimize, ulong, 0);
-+MODULE_PARM_DESC(hwoptimize, "Enable HW optimization function.");
-+
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
-+module_param_named(debug, debug.msg_enable, int, 0);
-+MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
-+#endif//LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
-+
-+MODULE_LICENSE("GPL");
-+
-+MODULE_VERSION(RTL8168_VERSION);
-+
-+static void rtl8168_sleep_rx_enable(struct net_device *dev);
-+static void rtl8168_dsm(struct net_device *dev, int dev_state);
-+
-+static void rtl8168_esd_timer(unsigned long __opaque);
-+static void rtl8168_link_timer(unsigned long __opaque);
-+static void rtl8168_tx_clear(struct rtl8168_private *tp);
-+static void rtl8168_rx_clear(struct rtl8168_private *tp);
-+
-+static int rtl8168_open(struct net_device *dev);
-+static int rtl8168_start_xmit(struct sk_buff *skb, struct net_device *dev);
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
-+static irqreturn_t rtl8168_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
-+#else
-+static irqreturn_t rtl8168_interrupt(int irq, void *dev_instance);
-+#endif
-+static void rtl8168_rx_desc_offset0_init(struct rtl8168_private *, int);
-+static int rtl8168_init_ring(struct net_device *dev);
-+static void rtl8168_hw_config(struct net_device *dev);
-+static void rtl8168_hw_start(struct net_device *dev);
-+static int rtl8168_close(struct net_device *dev);
-+static void rtl8168_set_rx_mode(struct net_device *dev);
-+static void rtl8168_tx_timeout(struct net_device *dev);
-+static struct net_device_stats *rtl8168_get_stats(struct net_device *dev);
-+static int rtl8168_rx_interrupt(struct net_device *, struct rtl8168_private *, void __iomem *, u32 budget);
-+static int rtl8168_change_mtu(struct net_device *dev, int new_mtu);
-+static void rtl8168_down(struct net_device *dev);
-+
-+static int rtl8168_set_mac_address(struct net_device *dev, void *p);
-+void rtl8168_rar_set(struct rtl8168_private *tp, uint8_t *addr);
-+static void rtl8168_desc_addr_fill(struct rtl8168_private *);
-+static void rtl8168_tx_desc_init(struct rtl8168_private *tp);
-+static void rtl8168_rx_desc_init(struct rtl8168_private *tp);
-+
-+static void rtl8168_hw_reset(struct net_device *dev);
-+
-+static void rtl8168_phy_power_up(struct net_device *dev);
-+static void rtl8168_phy_power_down(struct net_device *dev);
-+static int rtl8168_set_speed(struct net_device *dev, u8 autoneg, u16 speed, u8 duplex);
-+
-+#ifdef CONFIG_R8168_NAPI
-+static int rtl8168_poll(napi_ptr napi, napi_budget budget);
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-+#undef ethtool_ops
-+#define ethtool_ops _kc_ethtool_ops
-+
-+struct _kc_ethtool_ops {
-+ int (*get_settings)(struct net_device *, struct ethtool_cmd *);
-+ int (*set_settings)(struct net_device *, struct ethtool_cmd *);
-+ void (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
-+ int (*get_regs_len)(struct net_device *);
-+ void (*get_regs)(struct net_device *, struct ethtool_regs *, void *);
-+ void (*get_wol)(struct net_device *, struct ethtool_wolinfo *);
-+ int (*set_wol)(struct net_device *, struct ethtool_wolinfo *);
-+ u32 (*get_msglevel)(struct net_device *);
-+ void (*set_msglevel)(struct net_device *, u32);
-+ int (*nway_reset)(struct net_device *);
-+ u32 (*get_link)(struct net_device *);
-+ int (*get_eeprom_len)(struct net_device *);
-+ int (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);
-+ int (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);
-+ int (*get_coalesce)(struct net_device *, struct ethtool_coalesce *);
-+ int (*set_coalesce)(struct net_device *, struct ethtool_coalesce *);
-+ void (*get_ringparam)(struct net_device *, struct ethtool_ringparam *);
-+ int (*set_ringparam)(struct net_device *, struct ethtool_ringparam *);
-+ void (*get_pauseparam)(struct net_device *,
-+ struct ethtool_pauseparam*);
-+ int (*set_pauseparam)(struct net_device *,
-+ struct ethtool_pauseparam*);
-+ u32 (*get_rx_csum)(struct net_device *);
-+ int (*set_rx_csum)(struct net_device *, u32);
-+ u32 (*get_tx_csum)(struct net_device *);
-+ int (*set_tx_csum)(struct net_device *, u32);
-+ u32 (*get_sg)(struct net_device *);
-+ int (*set_sg)(struct net_device *, u32);
-+ u32 (*get_tso)(struct net_device *);
-+ int (*set_tso)(struct net_device *, u32);
-+ int (*self_test_count)(struct net_device *);
-+ void (*self_test)(struct net_device *, struct ethtool_test *, u64 *);
-+ void (*get_strings)(struct net_device *, u32 stringset, u8 *);
-+ int (*phys_id)(struct net_device *, u32);
-+ int (*get_stats_count)(struct net_device *);
-+ void (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *,
-+ u64 *);
-+} *ethtool_ops = NULL;
-+
-+#undef SET_ETHTOOL_OPS
-+#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops))
-+
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
-+#ifndef SET_ETHTOOL_OPS
-+#define SET_ETHTOOL_OPS(netdev,ops) \
-+ ( (netdev)->ethtool_ops = (ops) )
-+#endif //SET_ETHTOOL_OPS
-+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
-+
-+//#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
-+#ifndef netif_msg_init
-+#define netif_msg_init _kc_netif_msg_init
-+/* copied from linux kernel 2.6.20 include/linux/netdevice.h */
-+static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits)
-+{
-+ /* use default */
-+ if (debug_value < 0 || debug_value >= (sizeof(u32) * 8))
-+ return default_msg_enable_bits;
-+ if (debug_value == 0) /* no output */
-+ return 0;
-+ /* set low N bits */
-+ return (1 << debug_value) - 1;
-+}
-+
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
-+
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
-+static inline void eth_copy_and_sum (struct sk_buff *dest,
-+ const unsigned char *src,
-+ int len, int base)
-+{
-+ memcpy (dest->data, src, len);
-+}
-+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7)
-+/* copied from linux kernel 2.6.20 /include/linux/time.h */
-+/* Parameters used to convert the timespec values: */
-+#define MSEC_PER_SEC 1000L
-+
-+/* copied from linux kernel 2.6.20 /include/linux/jiffies.h */
-+/*
-+ * Change timeval to jiffies, trying to avoid the
-+ * most obvious overflows..
-+ *
-+ * And some not so obvious.
-+ *
-+ * Note that we don't want to return MAX_LONG, because
-+ * for various timeout reasons we often end up having
-+ * to wait "jiffies+1" in order to guarantee that we wait
-+ * at _least_ "jiffies" - so "jiffies+1" had better still
-+ * be positive.
-+ */
-+#define MAX_JIFFY_OFFSET ((~0UL >> 1)-1)
-+
-+/*
-+ * Convert jiffies to milliseconds and back.
-+ *
-+ * Avoid unnecessary multiplications/divisions in the
-+ * two most common HZ cases:
-+ */
-+static inline unsigned int _kc_jiffies_to_msecs(const unsigned long j)
-+{
-+#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
-+ return (MSEC_PER_SEC / HZ) * j;
-+#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
-+ return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);
-+#else
-+ return (j * MSEC_PER_SEC) / HZ;
-+#endif
-+}
-+
-+static inline unsigned long _kc_msecs_to_jiffies(const unsigned int m)
-+{
-+ if (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET))
-+ return MAX_JIFFY_OFFSET;
-+#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
-+ return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);
-+#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
-+ return m * (HZ / MSEC_PER_SEC);
-+#else
-+ return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC;
-+#endif
-+}
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7)
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
-+
-+/* copied from linux kernel 2.6.12.6 /include/linux/pm.h */
-+typedef int __bitwise pci_power_t;
-+
-+/* copied from linux kernel 2.6.12.6 /include/linux/pci.h */
-+typedef u32 __bitwise pm_message_t;
-+
-+#define PCI_D0 ((pci_power_t __force) 0)
-+#define PCI_D1 ((pci_power_t __force) 1)
-+#define PCI_D2 ((pci_power_t __force) 2)
-+#define PCI_D3hot ((pci_power_t __force) 3)
-+#define PCI_D3cold ((pci_power_t __force) 4)
-+#define PCI_POWER_ERROR ((pci_power_t __force) -1)
-+
-+/* copied from linux kernel 2.6.12.6 /drivers/pci/pci.c */
-+/**
-+ * pci_choose_state - Choose the power state of a PCI device
-+ * @dev: PCI device to be suspended
-+ * @state: target sleep state for the whole system. This is the value
-+ * that is passed to suspend() function.
-+ *
-+ * Returns PCI power state suitable for given device and given system
-+ * message.
-+ */
-+
-+pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
-+{
-+ if (!pci_find_capability(dev, PCI_CAP_ID_PM))
-+ return PCI_D0;
-+
-+ switch (state) {
-+ case 0:
-+ return PCI_D0;
-+ case 3:
-+ return PCI_D3hot;
-+ default:
-+ printk("They asked me for state %d\n", state);
-+// BUG();
-+ }
-+ return PCI_D0;
-+}
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
-+/**
-+ * msleep_interruptible - sleep waiting for waitqueue interruptions
-+ * @msecs: Time in milliseconds to sleep for
-+ */
-+#define msleep_interruptible _kc_msleep_interruptible
-+unsigned long _kc_msleep_interruptible(unsigned int msecs)
-+{
-+ unsigned long timeout = _kc_msecs_to_jiffies(msecs);
-+
-+ while (timeout && !signal_pending(current)) {
-+ set_current_state(TASK_INTERRUPTIBLE);
-+ timeout = schedule_timeout(timeout);
-+ }
-+ return _kc_jiffies_to_msecs(timeout);
-+}
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7)
-+/* copied from linux kernel 2.6.20 include/linux/sched.h */
-+#ifndef __sched
-+#define __sched __attribute__((__section__(".sched.text")))
-+#endif
-+
-+/* copied from linux kernel 2.6.20 kernel/timer.c */
-+signed long __sched schedule_timeout_uninterruptible(signed long timeout)
-+{
-+ __set_current_state(TASK_UNINTERRUPTIBLE);
-+ return schedule_timeout(timeout);
-+}
-+
-+/* copied from linux kernel 2.6.20 include/linux/mii.h */
-+#undef if_mii
-+#define if_mii _kc_if_mii
-+static inline struct mii_ioctl_data *if_mii(struct ifreq *rq)
-+{
-+ return (struct mii_ioctl_data *) &rq->ifr_ifru;
-+}
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7)
-+
-+static const char rtl8168_gstrings[][ETH_GSTRING_LEN] = {
-+ "tx_packets",
-+ "rx_packets",
-+ "tx_errors",
-+ "rx_errors",
-+ "rx_missed",
-+ "align_errors",
-+ "tx_single_collisions",
-+ "tx_multi_collisions",
-+ "unicast",
-+ "broadcast",
-+ "multicast",
-+ "tx_aborted",
-+ "tx_underrun",
-+};
-+
-+struct rtl8168_counters {
-+ u64 tx_packets;
-+ u64 rx_packets;
-+ u64 tx_errors;
-+ u32 rx_errors;
-+ u16 rx_missed;
-+ u16 align_errors;
-+ u32 tx_one_collision;
-+ u32 tx_multi_collision;
-+ u64 rx_unicast;
-+ u64 rx_broadcast;
-+ u32 rx_multicast;
-+ u16 tx_aborted;
-+ u16 tx_underun;
-+};
-+
-+#ifdef ENABLE_R8168_PROCFS
-+/****************************************************************************
-+* -----------------------------PROCFS STUFF-------------------------
-+*****************************************************************************
-+*/
-+
-+static struct proc_dir_entry *rtl8168_proc;
-+static int proc_init_num = 0;
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+static int proc_get_driver_variable(struct seq_file *m, void *v)
-+{
-+ struct net_device *dev = m->private;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ seq_puts(m, "\nDump Driver Variable\n");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ seq_puts(m, "Variable\tValue\n----------\t-----\n");
-+ seq_printf(m, "MODULENAME\t%s\n", MODULENAME);
-+ seq_printf(m, "driver version\t%s\n", RTL8168_VERSION);
-+ seq_printf(m, "chipset\t%d\n", tp->chipset);
-+ seq_printf(m, "chipset_name\t%s\n", rtl_chip_info[tp->chipset].name);
-+ seq_printf(m, "mtu\t%d\n", dev->mtu);
-+ seq_printf(m, "NUM_RX_DESC\t0x%x\n", NUM_RX_DESC);
-+ seq_printf(m, "cur_rx\t0x%x\n", tp->cur_rx);
-+ seq_printf(m, "dirty_rx\t0x%x\n", tp->dirty_rx);
-+ seq_printf(m, "NUM_TX_DESC\t0x%x\n", NUM_TX_DESC);
-+ seq_printf(m, "cur_tx\t0x%x\n", tp->cur_tx);
-+ seq_printf(m, "dirty_tx\t0x%x\n", tp->dirty_tx);
-+ seq_printf(m, "rx_buf_sz\t0x%x\n", tp->rx_buf_sz);
-+ seq_printf(m, "esd_flag\t0x%x\n", tp->esd_flag);
-+ seq_printf(m, "pci_cfg_is_read\t0x%x\n", tp->pci_cfg_is_read);
-+ seq_printf(m, "rtl8168_rx_config\t0x%x\n", tp->rtl8168_rx_config);
-+ seq_printf(m, "cp_cmd\t0x%x\n", tp->cp_cmd);
-+ seq_printf(m, "intr_mask\t0x%x\n", tp->intr_mask);
-+ seq_printf(m, "timer_intr_mask\t0x%x\n", tp->timer_intr_mask);
-+ seq_printf(m, "wol_enabled\t0x%x\n", tp->wol_enabled);
-+ seq_printf(m, "wol_opts\t0x%x\n", tp->wol_opts);
-+ seq_printf(m, "efuse_ver\t0x%x\n", tp->efuse_ver);
-+ seq_printf(m, "eeprom_type\t0x%x\n", tp->eeprom_type);
-+ seq_printf(m, "autoneg\t0x%x\n", tp->autoneg);
-+ seq_printf(m, "duplex\t0x%x\n", tp->duplex);
-+ seq_printf(m, "speed\t%d\n", tp->speed);
-+ seq_printf(m, "eeprom_len\t0x%x\n", tp->eeprom_len);
-+ seq_printf(m, "cur_page\t0x%x\n", tp->cur_page);
-+ seq_printf(m, "bios_setting\t0x%x\n", tp->bios_setting);
-+ seq_printf(m, "features\t0x%x\n", tp->features);
-+ seq_printf(m, "org_pci_offset_99\t0x%x\n", tp->org_pci_offset_99);
-+ seq_printf(m, "org_pci_offset_180\t0x%x\n", tp->org_pci_offset_180);
-+ seq_printf(m, "issue_offset_99_event\t0x%x\n", tp->issue_offset_99_event);
-+ seq_printf(m, "org_pci_offset_80\t0x%x\n", tp->org_pci_offset_80);
-+ seq_printf(m, "org_pci_offset_81\t0x%x\n", tp->org_pci_offset_81);
-+ seq_printf(m, "use_timer_interrrupt\t0x%x\n", tp->use_timer_interrrupt);
-+ seq_printf(m, "HwIcVerUnknown\t0x%x\n", tp->HwIcVerUnknown);
-+ seq_printf(m, "NotWrRamCodeToMicroP\t0x%x\n", tp->NotWrRamCodeToMicroP);
-+ seq_printf(m, "NotWrMcuPatchCode\t0x%x\n", tp->NotWrMcuPatchCode);
-+ seq_printf(m, "HwHasWrRamCodeToMicroP\t0x%x\n", tp->HwHasWrRamCodeToMicroP);
-+ seq_printf(m, "sw_ram_code_ver\t0x%x\n", tp->sw_ram_code_ver);
-+ seq_printf(m, "hw_ram_code_ver\t0x%x\n", tp->hw_ram_code_ver);
-+ seq_printf(m, "rtk_enable_diag\t0x%x\n", tp->rtk_enable_diag);
-+ seq_printf(m, "ShortPacketSwChecksum\t0x%x\n", tp->ShortPacketSwChecksum);
-+ seq_printf(m, "UseSwPaddingShortPkt\t0x%x\n", tp->UseSwPaddingShortPkt);
-+ seq_printf(m, "RequireAdcBiasPatch\t0x%x\n", tp->RequireAdcBiasPatch);
-+ seq_printf(m, "AdcBiasPatchIoffset\t0x%x\n", tp->AdcBiasPatchIoffset);
-+ seq_printf(m, "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n", tp->RequireAdjustUpsTxLinkPulseTiming);
-+ seq_printf(m, "SwrCnt1msIni\t0x%x\n", tp->SwrCnt1msIni);
-+ seq_printf(m, "HwSuppNowIsOobVer\t0x%x\n", tp->HwSuppNowIsOobVer);
-+ seq_printf(m, "RequiredSecLanDonglePatch\t0x%x\n", tp->RequiredSecLanDonglePatch);
-+ seq_printf(m, "HwSuppDashVer\t0x%x\n", tp->HwSuppDashVer);
-+ seq_printf(m, "DASH\t0x%x\n", tp->DASH);
-+ seq_printf(m, "HwSuppKCPOffloadVer\t0x%x\n", tp->HwSuppKCPOffloadVer);
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ seq_putc(m, '\n');
-+ return 0;
-+}
-+
-+static int proc_get_tally_counter(struct seq_file *m, void *v)
-+{
-+ struct net_device *dev = m->private;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ struct rtl8168_counters *counters;
-+ dma_addr_t paddr;
-+ u32 cmd;
-+ u32 WaitCnt;
-+ unsigned long flags;
-+
-+ seq_puts(m, "\nDump Tally Counter\n");
-+
-+ ASSERT_RTNL();
-+
-+ counters = tp->tally_vaddr;
-+ paddr = tp->tally_paddr;
-+ if (!counters) {
-+ seq_puts(m, "\nDump Tally Counter Fail\n");
-+ return 0;
-+ }
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
-+ cmd = (u64)paddr & DMA_BIT_MASK(32);
-+ RTL_W32(CounterAddrLow, cmd);
-+ RTL_W32(CounterAddrLow, cmd | CounterDump);
-+
-+ WaitCnt = 0;
-+ while (RTL_R32(CounterAddrLow) & CounterDump) {
-+ udelay(10);
-+
-+ WaitCnt++;
-+ if (WaitCnt > 20)
-+ break;
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ seq_puts(m, "Statistics\tValue\n----------\t-----\n");
-+ seq_printf(m, "tx_packets\t%lld\n", le64_to_cpu(counters->tx_packets));
-+ seq_printf(m, "rx_packets\t%lld\n", le64_to_cpu(counters->rx_packets));
-+ seq_printf(m, "tx_errors\t%lld\n", le64_to_cpu(counters->tx_errors));
-+ seq_printf(m, "rx_missed\t%lld\n", le64_to_cpu(counters->rx_missed));
-+ seq_printf(m, "align_errors\t%lld\n", le64_to_cpu(counters->align_errors));
-+ seq_printf(m, "tx_one_collision\t%lld\n", le64_to_cpu(counters->tx_one_collision));
-+ seq_printf(m, "tx_multi_collision\t%lld\n", le64_to_cpu(counters->tx_multi_collision));
-+ seq_printf(m, "rx_unicast\t%lld\n", le64_to_cpu(counters->rx_unicast));
-+ seq_printf(m, "rx_broadcast\t%lld\n", le64_to_cpu(counters->rx_broadcast));
-+ seq_printf(m, "rx_multicast\t%lld\n", le64_to_cpu(counters->rx_multicast));
-+ seq_printf(m, "tx_aborted\t%lld\n", le64_to_cpu(counters->tx_aborted));
-+ seq_printf(m, "tx_underun\t%lld\n", le64_to_cpu(counters->tx_underun));
-+
-+ seq_putc(m, '\n');
-+ return 0;
-+}
-+
-+static int proc_get_registers(struct seq_file *m, void *v)
-+{
-+ struct net_device *dev = m->private;
-+ int i, n, max = R8168_MAC_REGS_SIZE;
-+ u8 byte_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+
-+ seq_puts(m, "\nDump MAC Registers\n");
-+ seq_puts(m, "Offset\tValue\n------\t-----\n");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ for (n = 0; n < max;) {
-+ seq_printf(m, "\n0x%02x:\t", n);
-+
-+ for (i = 0; i < 16 && n < max; i++, n++) {
-+ byte_rd = readb(ioaddr + n);
-+ seq_printf(m, "%02x ", byte_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ seq_putc(m, '\n');
-+ return 0;
-+}
-+
-+static int proc_get_pcie_phy(struct seq_file *m, void *v)
-+{
-+ struct net_device *dev = m->private;
-+ int i, n, max = R8168_EPHY_REGS_SIZE/2;
-+ u16 word_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+
-+ seq_puts(m, "\nDump PCIE PHY\n");
-+ seq_puts(m, "\nOffset\tValue\n------\t-----\n ");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ for (n = 0; n < max;) {
-+ seq_printf(m, "\n0x%02x:\t", n);
-+
-+ for (i = 0; i < 8 && n < max; i++, n++) {
-+ word_rd = rtl8168_ephy_read(ioaddr, n);
-+ seq_printf(m, "%04x ", word_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ seq_putc(m, '\n');
-+ return 0;
-+}
-+
-+static int proc_get_eth_phy(struct seq_file *m, void *v)
-+{
-+ struct net_device *dev = m->private;
-+ int i, n, max = R8168_PHY_REGS_SIZE/2;
-+ u16 word_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ seq_puts(m, "\nDump Ethernet PHY\n");
-+ seq_puts(m, "\nOffset\tValue\n------\t-----\n ");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ seq_puts(m, "\n####################page 0##################\n ");
-+ mdio_write(tp, 0x1f, 0x0000);
-+ for (n = 0; n < max;) {
-+ seq_printf(m, "\n0x%02x:\t", n);
-+
-+ for (i = 0; i < 8 && n < max; i++, n++) {
-+ word_rd = mdio_read(tp, n);
-+ seq_printf(m, "%04x ", word_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ seq_putc(m, '\n');
-+ return 0;
-+}
-+
-+static int proc_get_extended_registers(struct seq_file *m, void *v)
-+{
-+ struct net_device *dev = m->private;
-+ int i, n, max = R8168_ERI_REGS_SIZE;
-+ u32 dword_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_1:
-+ case CFG_METHOD_2:
-+ case CFG_METHOD_3:
-+ /* RTL8168B does not support Extend GMAC */
-+ seq_puts(m, "\nNot Support Dump Extended Registers\n");
-+ return 0;
-+ }
-+
-+ seq_puts(m, "\nDump Extended Registers\n");
-+ seq_puts(m, "\nOffset\tValue\n------\t-----\n ");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ for (n = 0; n < max;) {
-+ seq_printf(m, "\n0x%02x:\t", n);
-+
-+ for (i = 0; i < 4 && n < max; i++, n+=4) {
-+ dword_rd = rtl8168_eri_read(ioaddr, n, 4, ERIAR_ExGMAC);
-+ seq_printf(m, "%08x ", dword_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ seq_putc(m, '\n');
-+ return 0;
-+}
-+#else
-+
-+static int proc_get_driver_variable(char *page, char **start,
-+ off_t offset, int count,
-+ int *eof, void *data)
-+{
-+ struct net_device *dev = data;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+ int len = 0;
-+
-+ len += snprintf(page + len, count - len,
-+ "\nDump Driver Driver\n");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ len += snprintf(page + len, count - len,
-+ "Variable\tValue\n----------\t-----\n");
-+
-+ len += snprintf(page + len, count - len,
-+ "MODULENAME\t%s\n"
-+ "driver version\t%s\n"
-+ "chipset\t%d\n"
-+ "chipset_name\t%s\n"
-+ "mtu\t%d\n"
-+ "NUM_RX_DESC\t0x%x\n"
-+ "cur_rx\t0x%x\n"
-+ "dirty_rx\t0x%x\n"
-+ "NUM_TX_DESC\t0x%x\n"
-+ "cur_tx\t0x%x\n"
-+ "dirty_tx\t0x%x\n"
-+ "rx_buf_sz\t0x%x\n"
-+ "esd_flag\t0x%x\n"
-+ "pci_cfg_is_read\t0x%x\n"
-+ "rtl8168_rx_config\t0x%x\n"
-+ "cp_cmd\t0x%x\n"
-+ "intr_mask\t0x%x\n"
-+ "timer_intr_mask\t0x%x\n"
-+ "wol_enabled\t0x%x\n"
-+ "wol_opts\t0x%x\n"
-+ "efuse_ver\t0x%x\n"
-+ "eeprom_type\t0x%x\n"
-+ "autoneg\t0x%x\n"
-+ "duplex\t0x%x\n"
-+ "speed\t%d\n"
-+ "eeprom_len\t0x%x\n"
-+ "cur_page\t0x%x\n"
-+ "bios_setting\t0x%x\n"
-+ "features\t0x%x\n"
-+ "org_pci_offset_99\t0x%x\n"
-+ "org_pci_offset_180\t0x%x\n"
-+ "issue_offset_99_event\t0x%x\n"
-+ "org_pci_offset_80\t0x%x\n"
-+ "org_pci_offset_81\t0x%x\n"
-+ "use_timer_interrrupt\t0x%x\n"
-+ "HwIcVerUnknown\t0x%x\n"
-+ "NotWrRamCodeToMicroP\t0x%x\n"
-+ "NotWrMcuPatchCode\t0x%x\n"
-+ "HwHasWrRamCodeToMicroP\t0x%x\n"
-+ "sw_ram_code_ver\t0x%x\n"
-+ "hw_ram_code_ver\t0x%x\n"
-+ "rtk_enable_diag\t0x%x\n"
-+ "ShortPacketSwChecksum\t0x%x\n"
-+ "UseSwPaddingShortPkt\t0x%x\n"
-+ "RequireAdcBiasPatch\t0x%x\n"
-+ "AdcBiasPatchIoffset\t0x%x\n"
-+ "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n"
-+ "SwrCnt1msIni\t0x%x\n"
-+ "HwSuppNowIsOobVer\t0x%x\n"
-+ "RequiredSecLanDonglePatch\t0x%x\n"
-+ "HwSuppDashVer\t0x%x\n"
-+ "DASH\t0x%x\n"
-+ "HwSuppKCPOffloadVer\t0x%x\n",
-+ MODULENAME,
-+ RTL8168_VERSION,
-+ tp->chipset,
-+ rtl_chip_info[tp->chipset].name,
-+ dev->mtu,
-+ NUM_RX_DESC,
-+ tp->cur_rx,
-+ tp->dirty_rx,
-+ NUM_TX_DESC,
-+ tp->cur_tx,
-+ tp->dirty_tx,
-+ tp->rx_buf_sz,
-+ tp->esd_flag,
-+ tp->pci_cfg_is_read,
-+ tp->rtl8168_rx_config,
-+ tp->cp_cmd,
-+ tp->intr_mask,
-+ tp->timer_intr_mask,
-+ tp->wol_enabled,
-+ tp->wol_opts,
-+ tp->efuse_ver,
-+ tp->eeprom_type,
-+ tp->autoneg,
-+ tp->duplex,
-+ tp->speed,
-+ tp->eeprom_len,
-+ tp->cur_page,
-+ tp->bios_setting,
-+ tp->features,
-+ tp->org_pci_offset_99,
-+ tp->org_pci_offset_180,
-+ tp->issue_offset_99_event,
-+ tp->org_pci_offset_80,
-+ tp->org_pci_offset_81,
-+ tp->use_timer_interrrupt,
-+ tp->HwIcVerUnknown,
-+ tp->NotWrRamCodeToMicroP,
-+ tp->NotWrMcuPatchCode,
-+ tp->HwHasWrRamCodeToMicroP,
-+ tp->sw_ram_code_ver,
-+ tp->hw_ram_code_ver,
-+ tp->rtk_enable_diag,
-+ tp->ShortPacketSwChecksum,
-+ tp->UseSwPaddingShortPkt,
-+ tp->RequireAdcBiasPatch,
-+ tp->AdcBiasPatchIoffset,
-+ tp->RequireAdjustUpsTxLinkPulseTiming,
-+ tp->SwrCnt1msIni,
-+ tp->HwSuppNowIsOobVer,
-+ tp->RequiredSecLanDonglePatch,
-+ tp->HwSuppDashVer,
-+ tp->DASH,
-+ tp->HwSuppKCPOffloadVer
-+ );
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ len += snprintf(page + len, count - len, "\n");
-+
-+ *eof = 1;
-+ return len;
-+}
-+
-+static int proc_get_tally_counter(char *page, char **start,
-+ off_t offset, int count,
-+ int *eof, void *data)
-+{
-+ struct net_device *dev = data;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ struct rtl8168_counters *counters;
-+ dma_addr_t paddr;
-+ u32 cmd;
-+ u32 WaitCnt;
-+ unsigned long flags;
-+ int len = 0;
-+
-+ len += snprintf(page + len, count - len,
-+ "\nDump Tally Counter\n");
-+
-+ ASSERT_RTNL();
-+
-+ counters = tp->tally_vaddr;
-+ paddr = tp->tally_paddr;
-+ if (!counters) {
-+ len += snprintf(page + len, count - len,
-+ "\nDump Tally Counter Fail\n");
-+ goto out;
-+ }
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
-+ cmd = (u64)paddr & DMA_BIT_MASK(32);
-+ RTL_W32(CounterAddrLow, cmd);
-+ RTL_W32(CounterAddrLow, cmd | CounterDump);
-+
-+ WaitCnt = 0;
-+ while (RTL_R32(CounterAddrLow) & CounterDump) {
-+ udelay(10);
-+
-+ WaitCnt++;
-+ if (WaitCnt > 20)
-+ break;
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ len += snprintf(page + len, count - len,
-+ "Statistics\tValue\n----------\t-----\n");
-+
-+ len += snprintf(page + len, count - len,
-+ "tx_packets\t%lld\n"
-+ "rx_packets\t%lld\n"
-+ "tx_errors\t%lld\n"
-+ "rx_missed\t%lld\n"
-+ "align_errors\t%lld\n"
-+ "tx_one_collision\t%lld\n"
-+ "tx_multi_collision\t%lld\n"
-+ "rx_unicast\t%lld\n"
-+ "rx_broadcast\t%lld\n"
-+ "rx_multicast\t%lld\n"
-+ "tx_aborted\t%lld\n"
-+ "tx_underun\t%lld\n",
-+ le64_to_cpu(counters->tx_packets),
-+ le64_to_cpu(counters->rx_packets),
-+ le64_to_cpu(counters->tx_errors),
-+ le64_to_cpu(counters->rx_missed),
-+ le64_to_cpu(counters->align_errors),
-+ le64_to_cpu(counters->tx_one_collision),
-+ le64_to_cpu(counters->tx_multi_collision),
-+ le64_to_cpu(counters->rx_unicast),
-+ le64_to_cpu(counters->rx_broadcast),
-+ le64_to_cpu(counters->rx_multicast),
-+ le64_to_cpu(counters->tx_aborted),
-+ le64_to_cpu(counters->tx_underun)
-+ );
-+
-+ len += snprintf(page + len, count - len, "\n");
-+out:
-+ *eof = 1;
-+ return len;
-+}
-+
-+static int proc_get_registers(char *page, char **start,
-+ off_t offset, int count,
-+ int *eof, void *data)
-+{
-+ struct net_device *dev = data;
-+ int i, n, max = R8168_MAC_REGS_SIZE;
-+ u8 byte_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+ int len = 0;
-+
-+ len += snprintf(page + len, count - len,
-+ "\nDump MAC Registers\n"
-+ "Offset\tValue\n------\t-----\n");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ for (n = 0; n < max;) {
-+ len += snprintf(page + len, count - len,
-+ "\n0x%02x:\t",
-+ n);
-+
-+ for (i = 0; i < 16 && n < max; i++, n++) {
-+ byte_rd = readb(ioaddr + n);
-+ len += snprintf(page + len, count - len,
-+ "%02x ",
-+ byte_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ len += snprintf(page + len, count - len, "\n");
-+
-+ *eof = 1;
-+ return len;
-+}
-+
-+static int proc_get_pcie_phy(char *page, char **start,
-+ off_t offset, int count,
-+ int *eof, void *data)
-+{
-+ struct net_device *dev = data;
-+ int i, n, max = R8168_EPHY_REGS_SIZE/2;
-+ u16 word_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+ int len = 0;
-+
-+ len += snprintf(page + len, count - len,
-+ "\nDump PCIE PHY\n"
-+ "Offset\tValue\n------\t-----\n");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ for (n = 0; n < max;) {
-+ len += snprintf(page + len, count - len,
-+ "\n0x%02x:\t",
-+ n);
-+
-+ for (i = 0; i < 8 && n < max; i++, n++) {
-+ word_rd = rtl8168_ephy_read(ioaddr, n);
-+ len += snprintf(page + len, count - len,
-+ "%04x ",
-+ word_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ len += snprintf(page + len, count - len, "\n");
-+
-+ *eof = 1;
-+ return len;
-+}
-+
-+static int proc_get_eth_phy(char *page, char **start,
-+ off_t offset, int count,
-+ int *eof, void *data)
-+{
-+ struct net_device *dev = data;
-+ int i, n, max = R8168_PHY_REGS_SIZE/2;
-+ u16 word_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+ int len = 0;
-+
-+ len += snprintf(page + len, count - len,
-+ "\nDump Ethernet PHY\n"
-+ "Offset\tValue\n------\t-----\n");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ len += snprintf(page + len, count - len,
-+ "\n####################page 0##################\n");
-+ mdio_write(tp, 0x1f, 0x0000);
-+ for (n = 0; n < max;) {
-+ len += snprintf(page + len, count - len,
-+ "\n0x%02x:\t",
-+ n);
-+
-+ for (i = 0; i < 8 && n < max; i++, n++) {
-+ word_rd = mdio_read(tp, n);
-+ len += snprintf(page + len, count - len,
-+ "%04x ",
-+ word_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ len += snprintf(page + len, count - len, "\n");
-+
-+ *eof = 1;
-+ return len;
-+}
-+
-+static int proc_get_extended_registers(char *page, char **start,
-+ off_t offset, int count,
-+ int *eof, void *data)
-+{
-+ struct net_device *dev = data;
-+ int i, n, max = R8168_ERI_REGS_SIZE;
-+ u32 dword_rd;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+ int len = 0;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_1:
-+ case CFG_METHOD_2:
-+ case CFG_METHOD_3:
-+ /* RTL8168B does not support Extend GMAC */
-+ len += snprintf(page + len, count - len,
-+ "\nNot Support Dump Extended Registers\n");
-+
-+ goto out;
-+ }
-+
-+ len += snprintf(page + len, count - len,
-+ "\nDump Extended Registers\n"
-+ "Offset\tValue\n------\t-----\n");
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ for (n = 0; n < max;) {
-+ len += snprintf(page + len, count - len,
-+ "\n0x%02x:\t",
-+ n);
-+
-+ for (i = 0; i < 4 && n < max; i++, n+=4) {
-+ dword_rd = rtl8168_eri_read(ioaddr, n, 4, ERIAR_ExGMAC);
-+ len += snprintf(page + len, count - len,
-+ "%08x ",
-+ dword_rd);
-+ }
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ len += snprintf(page + len, count - len, "\n");
-+out:
-+ *eof = 1;
-+ return len;
-+}
-+
-+#endif
-+static void rtl8168_proc_module_init(void)
-+{
-+ //in case /proc/net/r8168 already exist
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ remove_proc_subtree(MODULENAME, init_net.proc_net);
-+#else
-+ remove_proc_entry(MODULENAME, init_net.proc_net);
-+#endif
-+
-+ //create /proc/net/r8168
-+ rtl8168_proc = proc_mkdir(MODULENAME, init_net.proc_net);
-+}
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+/*
-+ * seq_file wrappers for procfile show routines.
-+ */
-+static int rtl8168_proc_open(struct inode *inode, struct file *file)
-+{
-+ struct net_device *dev = proc_get_parent_data(inode);
-+ int (*show)(struct seq_file *, void *) = PDE_DATA(inode);
-+
-+ return single_open(file, show, dev);
-+}
-+
-+static const struct file_operations rtl8168_proc_fops = {
-+ .open = rtl8168_proc_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+#endif
-+
-+/*
-+ * Table of proc files we need to create.
-+ */
-+struct rtl8168_proc_file {
-+ char name[12];
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ int (*show)(struct seq_file *, void *);
-+#else
-+ int (*show)(char *, char **, off_t, int, int *, void *);
-+#endif
-+};
-+
-+static const struct rtl8168_proc_file rtl8168_proc_files[] = {
-+ { "driver_var", &proc_get_driver_variable },
-+ { "tally", &proc_get_tally_counter },
-+ { "registers", &proc_get_registers },
-+ { "pcie_phy", &proc_get_pcie_phy },
-+ { "eth_phy", &proc_get_eth_phy },
-+ { "ext_regs", &proc_get_extended_registers },
-+ { "" }
-+};
-+
-+static void rtl8168_proc_init(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ const struct rtl8168_proc_file *f;
-+ struct proc_dir_entry *dir;
-+
-+ if (rtl8168_proc && !tp->proc_dir) {
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ dir = proc_mkdir_data(dev->name, 0, rtl8168_proc, dev);
-+ if (!dir) {
-+ printk("Unable to initialize /proc/net/%s/%s\n",
-+ MODULENAME, dev->name);
-+ return;
-+ }
-+
-+ tp->proc_dir = dir;
-+ proc_init_num++;
-+
-+ for (f = rtl8168_proc_files; f->name[0]; f++) {
-+ if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir,
-+ &rtl8168_proc_fops, f->show)) {
-+ printk("Unable to initialize "
-+ "/proc/net/%s/%s/%s\n",
-+ MODULENAME, dev->name, f->name);
-+ return;
-+ }
-+ }
-+#else
-+ dir = proc_mkdir(dev->name, rtl8168_proc);
-+ if (!dir) {
-+ printk("Unable to initialize /proc/net/%s/%s\n",
-+ MODULENAME, dev->name);
-+ return;
-+ }
-+
-+ tp->proc_dir = dir;
-+ proc_init_num++;
-+
-+ for (f = rtl8168_proc_files; f->name[0]; f++) {
-+ if (!create_proc_read_entry(f->name, S_IFREG | S_IRUGO,
-+ dir, f->show, dev)) {
-+ printk("Unable to initialize "
-+ "/proc/net/%s/%s/%s\n",
-+ MODULENAME, dev->name, f->name);
-+ return;
-+ }
-+ }
-+#endif
-+ }
-+}
-+
-+static void rtl8168_proc_remove(struct net_device *dev)
-+{
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
-+ remove_proc_subtree(dev->name, rtl8168_proc);
-+ proc_init_num--;
-+#else
-+ const struct rtl8168_proc_file *f;
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ for (f = rtl8168_proc_files; f->name[0]; f++)
-+ remove_proc_entry(f->name, tp->proc_dir);
-+
-+ remove_proc_entry(dev->name, rtl8168_proc);
-+ proc_init_num--;
-+#endif
-+}
-+
-+#endif //ENABLE_R8168_PROCFS
-+
-+static inline u16 map_phy_ocp_addr(u16 PageNum, u8 RegNum)
-+{
-+ u16 OcpPageNum = 0;
-+ u8 OcpRegNum = 0;
-+ u16 OcpPhyAddress = 0;
-+
-+ if( PageNum == 0 ) {
-+ OcpPageNum = OCP_STD_PHY_BASE_PAGE + ( RegNum / 8 );
-+ OcpRegNum = 0x10 + ( RegNum % 8 );
-+ } else {
-+ OcpPageNum = PageNum;
-+ OcpRegNum = RegNum;
-+ }
-+
-+ OcpPageNum <<= 4;
-+
-+ if( OcpRegNum < 16 ) {
-+ OcpPhyAddress = 0;
-+ } else {
-+ OcpRegNum -= 16;
-+ OcpRegNum <<= 1;
-+
-+ OcpPhyAddress = OcpPageNum + OcpRegNum;
-+ }
-+
-+
-+ return OcpPhyAddress;
-+}
-+
-+static void mdio_write_phy_ocp(struct rtl8168_private *tp,
-+ u16 PageNum,
-+ u32 RegAddr,
-+ u32 value)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 data32;
-+ u16 ocp_addr;
-+ int i;
-+
-+ ocp_addr = map_phy_ocp_addr(PageNum, RegAddr);
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
-+ WARN_ON_ONCE(ocp_addr % 2);
-+#endif
-+ data32 = ocp_addr/2;
-+ data32 <<= OCPR_Addr_Reg_shift;
-+ data32 |= OCPR_Write | value;
-+
-+ RTL_W32(PHYOCP, data32);
-+ for (i = 0; i < 100; i++) {
-+ udelay(1);
-+
-+ if (!(RTL_R32(PHYOCP) & OCPR_Flag))
-+ break;
-+ }
-+}
-+
-+static void mdio_real_write(struct rtl8168_private *tp,
-+ u32 RegAddr,
-+ u32 value)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i;
-+
-+ if (RegAddr == 0x1F) {
-+ tp->cur_page = value;
-+ }
-+
-+ if (tp->mcfg == CFG_METHOD_11) {
-+ RTL_W32(OCPDR, OCPDR_Write |
-+ (RegAddr & OCPDR_Reg_Mask) << OCPDR_GPHY_Reg_shift |
-+ (value & OCPDR_Data_Mask));
-+ RTL_W32(OCPAR, OCPAR_GPHY_Write);
-+ RTL_W32(EPHY_RXER_NUM, 0);
-+
-+ for (i = 0; i < 100; i++) {
-+ mdelay(1);
-+ if (!(RTL_R32(OCPAR) & OCPAR_Flag))
-+ break;
-+ }
-+ } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
-+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
-+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
-+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ if (RegAddr == 0x1F) {
-+ return;
-+ }
-+ mdio_write_phy_ocp(tp, tp->cur_page, RegAddr, value);
-+ } else {
-+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
-+ RTL_W32(0xD0, RTL_R32(0xD0) & ~0x00020000);
-+
-+ RTL_W32(PHYAR, PHYAR_Write |
-+ (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift |
-+ (value & PHYAR_Data_Mask));
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed writing to the specified MII register */
-+ if (!(RTL_R32(PHYAR) & PHYAR_Flag)) {
-+ udelay(20);
-+ break;
-+ }
-+ }
-+
-+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
-+ RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000);
-+ }
-+}
-+
-+void mdio_write(struct rtl8168_private *tp,
-+ u32 RegAddr,
-+ u32 value)
-+{
-+ if (tp->rtk_enable_diag) return;
-+
-+ mdio_real_write(tp, RegAddr, value);
-+}
-+
-+void mdio_prot_write(struct rtl8168_private *tp,
-+ u32 RegAddr,
-+ u32 value)
-+{
-+ mdio_real_write(tp, RegAddr, value);
-+}
-+
-+static u32 mdio_read_phy_ocp(struct rtl8168_private *tp,
-+ u16 PageNum,
-+ u32 RegAddr)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 data32;
-+ u16 ocp_addr;
-+ int i, value = 0;
-+
-+ ocp_addr = map_phy_ocp_addr(PageNum, RegAddr);
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
-+ WARN_ON_ONCE(ocp_addr % 2);
-+#endif
-+ data32 = ocp_addr/2;
-+ data32 <<= OCPR_Addr_Reg_shift;
-+
-+ RTL_W32(PHYOCP, data32);
-+ for (i = 0; i < 100; i++) {
-+ udelay(1);
-+
-+ if (RTL_R32(PHYOCP) & OCPR_Flag)
-+ break;
-+ }
-+ value = RTL_R32(PHYOCP) & OCPDR_Data_Mask;
-+
-+ return value;
-+}
-+
-+u32 mdio_read(struct rtl8168_private *tp,
-+ u32 RegAddr)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i, value = 0;
-+
-+ if (tp->mcfg==CFG_METHOD_11) {
-+ RTL_W32(OCPDR, OCPDR_Read |
-+ (RegAddr & OCPDR_Reg_Mask) << OCPDR_GPHY_Reg_shift);
-+ RTL_W32(OCPAR, OCPAR_GPHY_Write);
-+ RTL_W32(EPHY_RXER_NUM, 0);
-+
-+ for (i = 0; i < 100; i++) {
-+ mdelay(1);
-+ if (!(RTL_R32(OCPAR) & OCPAR_Flag))
-+ break;
-+ }
-+
-+ mdelay(1);
-+ RTL_W32(OCPAR, OCPAR_GPHY_Read);
-+ RTL_W32(EPHY_RXER_NUM, 0);
-+
-+ for (i = 0; i < 100; i++) {
-+ mdelay(1);
-+ if (RTL_R32(OCPAR) & OCPAR_Flag)
-+ break;
-+ }
-+
-+ value = RTL_R32(OCPDR) & OCPDR_Data_Mask;
-+ } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
-+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
-+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
-+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ value = mdio_read_phy_ocp(tp, tp->cur_page, RegAddr);
-+ } else {
-+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
-+ RTL_W32(0xD0, RTL_R32(0xD0) & ~0x00020000);
-+
-+ RTL_W32(PHYAR,
-+ PHYAR_Read | (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift);
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed retrieving data from the specified MII register */
-+ if (RTL_R32(PHYAR) & PHYAR_Flag) {
-+ value = RTL_R32(PHYAR) & PHYAR_Data_Mask;
-+ udelay(20);
-+ break;
-+ }
-+ }
-+
-+ if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
-+ RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000);
-+ }
-+
-+ return value;
-+}
-+
-+static void ClearAndSetEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 clearmask, u16 setmask)
-+{
-+ u16 PhyRegValue;
-+
-+
-+ PhyRegValue = mdio_read( tp, addr );
-+ PhyRegValue &= ~clearmask;
-+ PhyRegValue |= setmask;
-+ mdio_write( tp, addr, PhyRegValue);
-+}
-+
-+void ClearEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask)
-+{
-+ ClearAndSetEthPhyBit( tp,
-+ addr,
-+ mask,
-+ 0
-+ );
-+}
-+
-+void SetEthPhyBit(struct rtl8168_private *tp, u8 addr, u16 mask)
-+{
-+ ClearAndSetEthPhyBit( tp,
-+ addr,
-+ 0,
-+ mask
-+ );
-+}
-+
-+void mac_ocp_write(struct rtl8168_private *tp, u16 reg_addr, u16 value)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 data32;
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
-+ WARN_ON_ONCE(reg_addr % 2);
-+#endif
-+
-+ data32 = reg_addr/2;
-+ data32 <<= OCPR_Addr_Reg_shift;
-+ data32 += value;
-+ data32 |= OCPR_Write;
-+
-+ RTL_W32(MACOCP, data32);
-+}
-+
-+u16 mac_ocp_read(struct rtl8168_private *tp, u16 reg_addr)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 data32;
-+ u16 data16 = 0;
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
-+ WARN_ON_ONCE(reg_addr % 2);
-+#endif
-+
-+ data32 = reg_addr/2;
-+ data32 <<= OCPR_Addr_Reg_shift;
-+
-+ RTL_W32(MACOCP, data32);
-+ data16 = (u16)RTL_R32(MACOCP);
-+
-+ return data16;
-+}
-+
-+static u32 real_ocp_read(struct rtl8168_private *tp, u16 addr, u8 len)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i, val_shift, shift = 0;
-+ u32 value1 = 0, value2 = 0, mask;
-+
-+ if (len > 4 || len <= 0)
-+ return -1;
-+
-+ while (len > 0) {
-+ val_shift = addr % 4;
-+ addr = addr & ~0x3;
-+
-+ RTL_W32(OCPAR, (0x0F<<12) | (addr&0xFFF));
-+
-+ for (i = 0; i < 20; i++) {
-+ udelay(100);
-+ if (RTL_R32(OCPAR) & OCPAR_Flag)
-+ break;
-+ }
-+
-+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+
-+ value1 = RTL_R32(OCPDR) & mask;
-+ value2 |= (value1 >> val_shift * 8) << shift * 8;
-+
-+ if (len <= 4 - val_shift) {
-+ len = 0;
-+ } else {
-+ len -= (4 - val_shift);
-+ shift = 4 - val_shift;
-+ addr += 4;
-+ }
-+ }
-+
-+ udelay(20);
-+
-+ return value2;
-+}
-+
-+u32 OCP_read(struct rtl8168_private *tp, u16 addr, u8 len)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 value = 0;
-+
-+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 ||
-+ tp->mcfg == CFG_METHOD_28) {
-+ value = rtl8168_eri_read(ioaddr, addr, len, ERIAR_OOB);
-+ } else {
-+ value = real_ocp_read(tp, addr, len);
-+ }
-+
-+ return value;
-+}
-+
-+static int real_ocp_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 value)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i, val_shift, shift = 0;
-+ u32 value1 = 0, mask;
-+
-+ if (len > 4 || len <= 0)
-+ return -1;
-+
-+ while (len > 0) {
-+ val_shift = addr % 4;
-+ addr = addr & ~0x3;
-+
-+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+
-+ value1 = OCP_read(tp, addr, 4) & ~mask;
-+ value1 |= ((value << val_shift * 8) >> shift * 8);
-+
-+ RTL_W32(OCPDR, value1);
-+ RTL_W32(OCPAR, OCPAR_Flag | (0x0F<<12) | (addr&0xFFF));
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed ERI write */
-+ if (!(RTL_R32(OCPAR) & OCPAR_Flag))
-+ break;
-+ }
-+
-+ if (len <= 4 - val_shift) {
-+ len = 0;
-+ } else {
-+ len -= (4 - val_shift);
-+ shift = 4 - val_shift;
-+ addr += 4;
-+ }
-+ }
-+
-+ udelay(20);
-+
-+ return 0;
-+}
-+
-+void OCP_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 value)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 ||
-+ tp->mcfg == CFG_METHOD_28) {
-+ rtl8168_eri_write(ioaddr, addr, len, value, ERIAR_OOB);
-+ } else {
-+ real_ocp_write(tp, addr, len, value);
-+ }
-+}
-+
-+void OOB_mutex_lock(struct rtl8168_private *tp)
-+{
-+ u8 reg_16, reg_a0;
-+ u32 wait_cnt_0, wait_Cnt_1;
-+ u16 ocp_reg_mutex_ib;
-+ u16 ocp_reg_mutex_oob;
-+ u16 ocp_reg_mutex_prio;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ ocp_reg_mutex_oob = 0x16;
-+ ocp_reg_mutex_ib = 0x17;
-+ ocp_reg_mutex_prio = 0x9C;
-+ break;
-+ case CFG_METHOD_13:
-+ ocp_reg_mutex_oob = 0x06;
-+ ocp_reg_mutex_ib = 0x07;
-+ ocp_reg_mutex_prio = 0x9C;
-+ break;
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ default:
-+ ocp_reg_mutex_oob = 0x110;
-+ ocp_reg_mutex_ib = 0x114;
-+ ocp_reg_mutex_prio = 0x11C;
-+ break;
-+ }
-+
-+ OCP_write(tp, ocp_reg_mutex_ib, 1, BIT_0);
-+ reg_16 = OCP_read(tp, ocp_reg_mutex_oob, 1);
-+ wait_cnt_0 = 0;
-+ while(reg_16) {
-+ reg_a0 = OCP_read(tp, ocp_reg_mutex_prio, 1);
-+ if(reg_a0) {
-+ OCP_write(tp, ocp_reg_mutex_ib, 1, 0x00);
-+ reg_a0 = OCP_read(tp, ocp_reg_mutex_prio, 1);
-+ wait_Cnt_1 = 0;
-+ while(reg_a0) {
-+ reg_a0 = OCP_read(tp, ocp_reg_mutex_prio, 1);
-+
-+ wait_Cnt_1++;
-+
-+ if(wait_Cnt_1 > 2000)
-+ break;
-+ };
-+ OCP_write(tp, ocp_reg_mutex_ib, 1, BIT_0);
-+
-+ }
-+ reg_16 = OCP_read(tp, ocp_reg_mutex_oob, 1);
-+
-+ wait_cnt_0++;
-+
-+ if(wait_cnt_0 > 2000)
-+ break;
-+ };
-+}
-+
-+void OOB_mutex_unlock(struct rtl8168_private *tp)
-+{
-+ u16 ocp_reg_mutex_ib;
-+ u16 ocp_reg_mutex_oob;
-+ u16 ocp_reg_mutex_prio;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ ocp_reg_mutex_oob = 0x16;
-+ ocp_reg_mutex_ib = 0x17;
-+ ocp_reg_mutex_prio = 0x9C;
-+ break;
-+ case CFG_METHOD_13:
-+ ocp_reg_mutex_oob = 0x06;
-+ ocp_reg_mutex_ib = 0x07;
-+ ocp_reg_mutex_prio = 0x9C;
-+ break;
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ default:
-+ ocp_reg_mutex_oob = 0x110;
-+ ocp_reg_mutex_ib = 0x114;
-+ ocp_reg_mutex_prio = 0x11C;
-+ break;
-+ }
-+
-+ OCP_write(tp, ocp_reg_mutex_prio, 1, BIT_0);
-+ OCP_write(tp, ocp_reg_mutex_ib, 1, 0x00);
-+}
-+
-+void OOB_notify(struct rtl8168_private *tp, u8 cmd)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ rtl8168_eri_write(ioaddr, 0xE8, 1, cmd, ERIAR_ExGMAC);
-+
-+ OCP_write(tp, 0x30, 1, 0x01);
-+}
-+
-+static int rtl8168_check_dash(struct rtl8168_private *tp)
-+{
-+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 ||
-+ tp->mcfg == CFG_METHOD_28) {
-+ if (OCP_read(tp, 0x128, 1) & BIT_0)
-+ return 1;
-+ else
-+ return 0;
-+ } else {
-+ u32 reg;
-+
-+ if (tp->mcfg == CFG_METHOD_13)
-+ reg = 0xb8;
-+ else
-+ reg = 0x10;
-+
-+ if (OCP_read(tp, reg, 2) & 0x00008000)
-+ return 1;
-+ else
-+ return 0;
-+ }
-+}
-+
-+void Dash2DisableTx(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (!tp->DASH) return;
-+
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) {
-+ u16 WaitCnt;
-+ u8 TmpUchar;
-+
-+ //Disable oob Tx
-+ RTL_W8(IBCR2, RTL_R8(IBCR2) & ~( BIT_0 ));
-+ WaitCnt = 0;
-+
-+ //wait oob tx disable
-+ do {
-+ TmpUchar = RTL_R8(IBISR0);
-+
-+ if( TmpUchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE ) {
-+ break;
-+ }
-+
-+ udelay( 50 );
-+ WaitCnt++;
-+ } while(WaitCnt < 2000);
-+
-+ //Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE
-+ RTL_W8(IBISR0, RTL_R8(IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE);
-+ }
-+}
-+
-+void Dash2EnableTx(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (!tp->DASH) return;
-+
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) )
-+ RTL_W8(IBCR2, RTL_R8(IBCR2) | BIT_0);
-+}
-+
-+void Dash2DisableRx(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (!tp->DASH) return;
-+
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) )
-+ RTL_W8(IBCR0, RTL_R8(IBCR0) & ~( BIT_0 ));
-+}
-+
-+void Dash2EnableRx(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (!tp->DASH) return;
-+
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) )
-+ RTL_W8(IBCR0, RTL_R8(IBCR0) | BIT_0);
-+}
-+
-+static void Dash2DisableTxRx(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) {
-+ Dash2DisableTx( tp );
-+ Dash2DisableRx( tp );
-+ }
-+}
-+
-+static void rtl8168_driver_start(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (!tp->DASH)
-+ return;
-+
-+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 ||
-+ tp->mcfg == CFG_METHOD_28) {
-+ int timeout;
-+ u32 tmp_value;
-+
-+ OCP_write(tp, 0x180, 1, OOB_CMD_DRIVER_START);
-+ tmp_value = OCP_read(tp, 0x30, 1);
-+ tmp_value |= BIT_0;
-+ OCP_write(tp, 0x30, 1, tmp_value);
-+
-+ for (timeout = 0; timeout < 10; timeout++) {
-+ mdelay(10);
-+ if (OCP_read(tp, 0x124, 1) & BIT_0)
-+ break;
-+ }
-+ } else {
-+ int timeout;
-+ u32 reg;
-+
-+ if (tp->mcfg == CFG_METHOD_13) {
-+ RTL_W8(TwiCmdReg, RTL_R8(TwiCmdReg) | ( BIT_7 ));
-+ }
-+
-+ OOB_notify(tp, OOB_CMD_DRIVER_START);
-+
-+ if (tp->mcfg == CFG_METHOD_13)
-+ reg = 0xB8;
-+ else
-+ reg = 0x10;
-+
-+ for (timeout = 0; timeout < 10; timeout++) {
-+ mdelay(10);
-+ if (OCP_read(tp, reg, 2) & BIT_11)
-+ break;
-+ }
-+ }
-+}
-+
-+static void rtl8168_driver_stop(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (!tp->DASH)
-+ return;
-+
-+ if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 ||
-+ tp->mcfg == CFG_METHOD_28) {
-+ struct net_device *dev = tp->dev;
-+ int timeout;
-+ u32 tmp_value;
-+
-+ Dash2DisableTxRx(dev);
-+
-+ OCP_write(tp, 0x180, 1, OOB_CMD_DRIVER_STOP);
-+ tmp_value = OCP_read(tp, 0x30, 1);
-+ tmp_value |= BIT_0;
-+ OCP_write(tp, 0x30, 1, tmp_value);
-+
-+ for (timeout = 0; timeout < 10; timeout++) {
-+ mdelay(10);
-+ if (!(OCP_read(tp, 0x124, 1) & BIT_0))
-+ break;
-+ }
-+ } else {
-+ int timeout;
-+ u32 reg;
-+
-+ OOB_notify(tp, OOB_CMD_DRIVER_STOP);
-+
-+ if (tp->mcfg == CFG_METHOD_13)
-+ reg = 0xB8;
-+ else
-+ reg = 0x10;
-+
-+ for (timeout = 0; timeout < 10; timeout++) {
-+ mdelay(10);
-+ if ((OCP_read(tp, reg, 2) & BIT_11) == 0)
-+ break;
-+ }
-+
-+ if (tp->mcfg == CFG_METHOD_13) {
-+ RTL_W8(TwiCmdReg, RTL_R8(TwiCmdReg) & ~( BIT_7 ));
-+ }
-+ }
-+}
-+
-+void rtl8168_ephy_write(void __iomem *ioaddr, int RegAddr, int value)
-+{
-+ int i;
-+
-+ RTL_W32(EPHYAR,
-+ EPHYAR_Write |
-+ (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift |
-+ (value & EPHYAR_Data_Mask));
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed EPHY write */
-+ if (!(RTL_R32(EPHYAR) & EPHYAR_Flag))
-+ break;
-+ }
-+
-+ udelay(20);
-+}
-+
-+u16 rtl8168_ephy_read(void __iomem *ioaddr, int RegAddr)
-+{
-+ int i;
-+ u16 value = 0xffff;
-+
-+ RTL_W32(EPHYAR,
-+ EPHYAR_Read | (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift);
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed EPHY read */
-+ if (RTL_R32(EPHYAR) & EPHYAR_Flag) {
-+ value = (u16) (RTL_R32(EPHYAR) & EPHYAR_Data_Mask);
-+ break;
-+ }
-+ }
-+
-+ udelay(20);
-+
-+ return value;
-+}
-+
-+static void ClearAndSetPCIePhyBit(struct rtl8168_private *tp, u8 addr, u16 clearmask, u16 setmask)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u16 EphyValue;
-+
-+ EphyValue = rtl8168_ephy_read( ioaddr, addr );
-+ EphyValue &= ~clearmask;
-+ EphyValue |= setmask;
-+ rtl8168_ephy_write( ioaddr, addr, EphyValue);
-+}
-+
-+static void ClearPCIePhyBit(struct rtl8168_private *tp, u8 addr, u16 mask)
-+{
-+ ClearAndSetPCIePhyBit( tp,
-+ addr,
-+ mask,
-+ 0
-+ );
-+}
-+
-+static void SetPCIePhyBit( struct rtl8168_private *tp, u8 addr, u16 mask)
-+{
-+ ClearAndSetPCIePhyBit( tp,
-+ addr,
-+ 0,
-+ mask
-+ );
-+}
-+
-+static u32
-+rtl8168_csi_other_fun_read(struct rtl8168_private *tp,
-+ u8 multi_fun_sel_bit,
-+ u32 addr)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 cmd;
-+ int i;
-+ u32 value = 0;
-+
-+ cmd = CSIAR_Read | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask);
-+
-+ if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 &&
-+ tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 &&
-+ tp->mcfg != CFG_METHOD_28) {
-+ multi_fun_sel_bit = 0;
-+ }
-+
-+ if( multi_fun_sel_bit > 7 ) {
-+ return 0xffffffff;
-+ }
-+
-+ cmd |= multi_fun_sel_bit << 16;
-+
-+ RTL_W32(CSIAR, cmd);
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed CSI read */
-+ if (RTL_R32(CSIAR) & CSIAR_Flag) {
-+ value = (u32)RTL_R32(CSIDR);
-+ break;
-+ }
-+ }
-+
-+ udelay(20);
-+
-+ return value;
-+}
-+
-+static void
-+rtl8168_csi_other_fun_write(struct rtl8168_private *tp,
-+ u8 multi_fun_sel_bit,
-+ u32 addr,
-+ u32 value)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 cmd;
-+ int i;
-+
-+ RTL_W32(CSIDR, value);
-+ cmd = CSIAR_Write | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask);
-+ if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 &&
-+ tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 &&
-+ tp->mcfg != CFG_METHOD_28) {
-+ multi_fun_sel_bit = 0;
-+ }
-+
-+ if( multi_fun_sel_bit > 7 ) {
-+ return;
-+ }
-+
-+ cmd |= multi_fun_sel_bit << 16;
-+
-+ RTL_W32(CSIAR, cmd);
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed CSI write */
-+ if (!(RTL_R32(CSIAR) & CSIAR_Flag))
-+ break;
-+ }
-+
-+ udelay(20);
-+}
-+
-+static u32
-+rtl8168_csi_read(struct rtl8168_private *tp,
-+ u32 addr)
-+{
-+ u8 multi_fun_sel_bit;
-+
-+ if (tp->mcfg == CFG_METHOD_20)
-+ multi_fun_sel_bit = 2;
-+ else if (tp->mcfg == CFG_METHOD_26)
-+ multi_fun_sel_bit = 1;
-+ else
-+ multi_fun_sel_bit = 0;
-+
-+
-+ return rtl8168_csi_other_fun_read(tp, multi_fun_sel_bit, addr);
-+}
-+
-+static void
-+rtl8168_csi_write(struct rtl8168_private *tp,
-+ u32 addr,
-+ u32 value)
-+{
-+ u8 multi_fun_sel_bit;
-+
-+ if (tp->mcfg == CFG_METHOD_20)
-+ multi_fun_sel_bit = 2;
-+ else if (tp->mcfg == CFG_METHOD_26)
-+ multi_fun_sel_bit = 1;
-+ else
-+ multi_fun_sel_bit = 0;
-+
-+ rtl8168_csi_other_fun_write(tp, multi_fun_sel_bit, addr, value);
-+}
-+
-+static u8
-+rtl8168_csi_fun0_read_byte(struct rtl8168_private *tp,
-+ u32 addr)
-+{
-+ u8 RetVal = 0;
-+
-+ if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26) {
-+ u32 TmpUlong;
-+ u16 RegAlignAddr;
-+ u8 ShiftByte;
-+
-+ RegAlignAddr = addr & ~(0x3);
-+ ShiftByte = addr & (0x3);
-+ TmpUlong = rtl8168_csi_other_fun_read(tp, 0, addr);
-+ TmpUlong >>= (8*ShiftByte);
-+ RetVal = (u8)TmpUlong;
-+ } else {
-+ struct pci_dev *pdev = tp->pci_dev;
-+
-+ pci_read_config_byte(pdev, addr, &RetVal);
-+ }
-+
-+ udelay(20);
-+
-+ return RetVal;
-+}
-+
-+static void
-+rtl8168_csi_fun0_write_byte(struct rtl8168_private *tp,
-+ u32 addr,
-+ u8 value)
-+{
-+ if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26) {
-+ u32 TmpUlong;
-+ u16 RegAlignAddr;
-+ u8 ShiftByte;
-+
-+ RegAlignAddr = addr & ~(0x3);
-+ ShiftByte = addr & (0x3);
-+ TmpUlong = rtl8168_csi_other_fun_read(tp, 0, RegAlignAddr);
-+ TmpUlong &= ~(0xFF << (8*ShiftByte));
-+ TmpUlong |= (value << (8*ShiftByte));
-+ rtl8168_csi_other_fun_write( tp, 0, RegAlignAddr, TmpUlong );
-+ } else {
-+ struct pci_dev *pdev = tp->pci_dev;
-+
-+ pci_write_config_byte(pdev, addr, value);
-+ }
-+
-+ udelay(20);
-+}
-+
-+u32 rtl8168_eri_read(void __iomem *ioaddr, int addr, int len, int type)
-+{
-+ int i, val_shift, shift = 0;
-+ u32 value1 = 0, value2 = 0, mask;
-+ u32 eri_cmd;
-+
-+ if (len > 4 || len <= 0)
-+ return -1;
-+
-+ while (len > 0) {
-+ val_shift = addr % ERIAR_Addr_Align;
-+ addr = addr & ~0x3;
-+
-+ eri_cmd = ERIAR_Read |
-+ type << ERIAR_Type_shift |
-+ ERIAR_ByteEn << ERIAR_ByteEn_shift |
-+ (addr & 0x0FFF);
-+ if (addr & 0xF000) {
-+ u32 tmp;
-+
-+ tmp = addr & 0xF000;
-+ tmp >>= 12;
-+ eri_cmd |= (tmp << 20) & 0x00F00000;
-+ }
-+
-+ RTL_W32(ERIAR, eri_cmd);
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed ERI read */
-+ if (RTL_R32(ERIAR) & ERIAR_Flag)
-+ break;
-+ }
-+
-+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+
-+ value1 = RTL_R32(ERIDR) & mask;
-+ value2 |= (value1 >> val_shift * 8) << shift * 8;
-+
-+ if (len <= 4 - val_shift) {
-+ len = 0;
-+ } else {
-+ len -= (4 - val_shift);
-+ shift = 4 - val_shift;
-+ addr += 4;
-+ }
-+ }
-+
-+ udelay(20);
-+
-+ return value2;
-+}
-+
-+int rtl8168_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type)
-+{
-+
-+ int i, val_shift, shift = 0;
-+ u32 value1 = 0, mask;
-+ u32 eri_cmd;
-+
-+ if (len > 4 || len <= 0)
-+ return -1;
-+
-+ while (len > 0) {
-+ val_shift = addr % ERIAR_Addr_Align;
-+ addr = addr & ~0x3;
-+
-+ if (len == 1) mask = (0xFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 2) mask = (0xFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else if (len == 3) mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+ else mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
-+
-+ value1 = rtl8168_eri_read(ioaddr, addr, 4, type) & ~mask;
-+ value1 |= ((value << val_shift * 8) >> shift * 8);
-+
-+ RTL_W32(ERIDR, value1);
-+
-+ eri_cmd = ERIAR_Write |
-+ type << ERIAR_Type_shift |
-+ ERIAR_ByteEn << ERIAR_ByteEn_shift |
-+ (addr & 0x0FFF);
-+ if (addr & 0xF000) {
-+ u32 tmp;
-+
-+ tmp = addr & 0xF000;
-+ tmp >>= 12;
-+ eri_cmd |= (tmp << 20) & 0x00F00000;
-+ }
-+
-+ RTL_W32(ERIAR, eri_cmd);
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+
-+ /* Check if the RTL8168 has completed ERI write */
-+ if (!(RTL_R32(ERIAR) & ERIAR_Flag))
-+ break;
-+ }
-+
-+ if (len <= 4 - val_shift) {
-+ len = 0;
-+ } else {
-+ len -= (4 - val_shift);
-+ shift = 4 - val_shift;
-+ addr += 4;
-+ }
-+ }
-+
-+ udelay(20);
-+
-+ return 0;
-+}
-+
-+static void
-+rtl8168_enable_rxdvgate(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W8(0xF2, RTL_R8(0xF2) | BIT_3);
-+ mdelay(2);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_disable_rxdvgate(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_3);
-+ mdelay(2);
-+ break;
-+ }
-+}
-+
-+void
-+rtl8168_wait_txrx_fifo_empty(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+ if (RTL_R32(TxConfig) & BIT_11)
-+ break;
-+ }
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+ if ((RTL_R8(MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty))
-+ break;
-+
-+ }
-+ break;
-+ }
-+}
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+
-+inline void
-+rtl8168_enable_dash2_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ if (!tp->DASH) return;
-+
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) )
-+ RTL_W8(IBIMR0, ( ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE ));
-+}
-+
-+static inline void
-+rtl8168_disable_dash2_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ if (!tp->DASH) return;
-+
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) )
-+ RTL_W8(IBIMR0, 0);
-+}
-+#endif
-+
-+static inline void
-+rtl8168_enable_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ RTL_W16(IntrMask, tp->intr_mask);
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+ if (tp->DASH)
-+ rtl8168_enable_dash2_interrupt(tp, ioaddr);
-+#endif
-+}
-+
-+static inline void
-+rtl8168_disable_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ RTL_W16(IntrMask, 0x0000);
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+ if (tp->DASH)
-+ rtl8168_disable_dash2_interrupt(tp, ioaddr);
-+#endif
-+}
-+
-+
-+static inline void
-+rtl8168_switch_to_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ RTL_W32(TimeInt0, 0x0000);
-+
-+ rtl8168_enable_hw_interrupt(tp, ioaddr);
-+}
-+
-+static inline void
-+rtl8168_switch_to_timer_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ if (tp->use_timer_interrrupt) {
-+ RTL_W32(TCTR, timer_count);
-+ RTL_W32(TimeInt0, timer_count);
-+ RTL_W16(IntrMask, tp->timer_intr_mask);
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+ if (tp->DASH)
-+ rtl8168_enable_dash2_interrupt(tp, ioaddr);
-+#endif
-+ } else {
-+ rtl8168_switch_to_hw_interrupt(tp, ioaddr);
-+ }
-+}
-+
-+static void
-+rtl8168_irq_mask_and_ack(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ rtl8168_disable_hw_interrupt(tp, ioaddr);
-+ RTL_W16(IntrStatus, RTL_R16(IntrStatus));
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+ if ( tp->DASH ) {
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) {
-+ RTL_W8(IBISR0, RTL_R16(IBISR0));
-+ }
-+ }
-+#endif
-+}
-+
-+static void
-+rtl8168_nic_reset(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i;
-+
-+ RTL_W32(RxConfig, (RX_DMA_BURST << RxCfgDMAShift));
-+
-+ rtl8168_enable_rxdvgate(dev);
-+
-+ rtl8168_wait_txrx_fifo_empty(dev);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_1:
-+ case CFG_METHOD_2:
-+ case CFG_METHOD_3:
-+ mdelay(10);
-+ break;
-+ case CFG_METHOD_4:
-+ case CFG_METHOD_5:
-+ case CFG_METHOD_6:
-+ case CFG_METHOD_7:
-+ case CFG_METHOD_8:
-+ case CFG_METHOD_9:
-+ case CFG_METHOD_10:
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ RTL_W8(ChipCmd, StopReq | CmdRxEnb | CmdTxEnb);
-+ udelay(100);
-+ break;
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ case CFG_METHOD_13:
-+ while (RTL_R8(TxPoll) & NPQ)
-+ udelay(20);
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ mdelay(2);
-+ break;
-+ default:
-+ mdelay(10);
-+ break;
-+ }
-+
-+ /* Soft reset the chip. */
-+ RTL_W8(ChipCmd, CmdReset);
-+
-+ /* Check that the chip has finished the reset. */
-+ for (i = 100; i > 0; i--) {
-+ udelay(100);
-+ if ((RTL_R8(ChipCmd) & CmdReset) == 0)
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_11:
-+ OOB_mutex_lock(tp);
-+ OCP_write(tp, 0x10, 2, OCP_read(tp, 0x010, 2)&~0x00004000);
-+ OOB_mutex_unlock(tp);
-+
-+ OOB_notify(tp, OOB_CMD_RESET);
-+
-+ for (i = 0; i < 10; i++) {
-+ mdelay(10);
-+ if (OCP_read(tp, 0x010, 2)&0x00004000)
-+ break;
-+ }
-+
-+ for (i = 0; i < 5; i++) {
-+ if ( OCP_read(tp, 0x034, 1) == 0)
-+ break;
-+ }
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_hw_clear_timer_int(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ RTL_W32(TimeInt0, 0x0000);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_4:
-+ case CFG_METHOD_5:
-+ case CFG_METHOD_6:
-+ case CFG_METHOD_7:
-+ case CFG_METHOD_8:
-+ RTL_W32(TimeInt1, 0x0000);
-+ break;
-+ case CFG_METHOD_9:
-+ case CFG_METHOD_10:
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ case CFG_METHOD_13:
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W32(TimeInt1, 0x0000);
-+ RTL_W32(TimeInt2, 0x0000);
-+ RTL_W32(TimeInt3, 0x0000);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_hw_reset(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ /* Disable interrupts */
-+ rtl8168_irq_mask_and_ack(tp, ioaddr);
-+
-+ rtl8168_hw_clear_timer_int(dev);
-+
-+ rtl8168_nic_reset(dev);
-+}
-+
-+static void rtl8168_mac_loopback_test(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ struct net_device *dev = tp->dev;
-+ struct sk_buff *skb, *rx_skb;
-+ dma_addr_t mapping;
-+ struct TxDesc *txd;
-+ struct RxDesc *rxd;
-+ void *tmpAddr;
-+ u32 len, rx_len, rx_cmd;
-+ u16 type;
-+ u8 pattern;
-+ int i;
-+
-+ if (tp->DASH)
-+ return;
-+
-+ pattern = 0x5A;
-+ len = 60;
-+ type = htons(ETH_P_IP);
-+ txd = tp->TxDescArray;
-+ rxd = tp->RxDescArray;
-+ rx_skb = tp->Rx_skbuff[0];
-+ RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~0x00060000) | 0x00020000);
-+
-+ do {
-+ skb = dev_alloc_skb(len + RTK_RX_ALIGN);
-+ if (unlikely(!skb))
-+ dev_printk(KERN_NOTICE, &tp->pci_dev->dev, "-ENOMEM;\n");
-+ } while (unlikely(skb == NULL));
-+ skb_reserve(skb, RTK_RX_ALIGN);
-+
-+ memcpy(skb_put(skb, dev->addr_len), dev->dev_addr, dev->addr_len);
-+ memcpy(skb_put(skb, dev->addr_len), dev->dev_addr, dev->addr_len);
-+ memcpy(skb_put(skb, sizeof(type)), &type, sizeof(type));
-+ tmpAddr = skb_put(skb, len - 14);
-+
-+ mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
-+ pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(mapping),
-+ len, PCI_DMA_TODEVICE);
-+ txd->addr = cpu_to_le64(mapping);
-+ txd->opts2 = 0;
-+ while (1) {
-+ memset(tmpAddr, pattern++, len - 14);
-+ pci_dma_sync_single_for_device(tp->pci_dev,
-+ le64_to_cpu(mapping),
-+ len, PCI_DMA_TODEVICE);
-+ txd->opts1 = cpu_to_le32(DescOwn | FirstFrag | LastFrag | len);
-+
-+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptMyPhys);
-+
-+ smp_wmb();
-+ RTL_W8(TxPoll, NPQ); /* set polling bit */
-+
-+ for (i = 0; i < 50; i++) {
-+ udelay(200);
-+ rx_cmd = le32_to_cpu(rxd->opts1);
-+ if ((rx_cmd & DescOwn) == 0)
-+ break;
-+ }
-+
-+ RTL_W32(RxConfig, RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys));
-+
-+ rx_len = rx_cmd & 0x3FFF;
-+ rx_len -= 4;
-+ rxd->opts1 = cpu_to_le32(DescOwn | tp->rx_buf_sz);
-+
-+ pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(mapping), len, PCI_DMA_TODEVICE);
-+
-+ if (rx_len == len) {
-+ pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
-+ i = memcmp(skb->data, rx_skb->data, rx_len);
-+ pci_dma_sync_single_for_device(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
-+ if (i == 0) {
-+// dev_printk(KERN_INFO, &tp->pci_dev->dev, "loopback test finished\n",rx_len,len);
-+ break;
-+ }
-+ }
-+
-+ rtl8168_hw_reset(dev);
-+ rtl8168_disable_rxdvgate(dev);
-+ RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
-+ }
-+ tp->dirty_tx++;
-+ tp->dirty_rx++;
-+ tp->cur_tx++;
-+ tp->cur_rx++;
-+ pci_unmap_single(tp->pci_dev, le64_to_cpu(mapping),
-+ len, PCI_DMA_TODEVICE);
-+ RTL_W32(TxConfig, RTL_R32(TxConfig) & ~0x00060000);
-+ dev_kfree_skb_any(skb);
-+ RTL_W16(IntrStatus, 0xFFBF);
-+}
-+
-+static unsigned int
-+rtl8168_xmii_reset_pending(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned int retval;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ retval = mdio_read(tp, MII_BMCR) & BMCR_RESET;
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+
-+ return retval;
-+}
-+
-+static unsigned int
-+rtl8168_xmii_link_ok(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned int retval;
-+
-+ retval = (RTL_R8(PHYstatus) & LinkStatus) ? 1 : 0;
-+
-+ return retval;
-+}
-+
-+static void
-+rtl8168_xmii_reset_enable(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ int i, val = 0;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
-+
-+ for (i = 0; i < 2500; i++) {
-+ val = mdio_read(tp, MII_BMCR) & BMCR_RESET;
-+
-+ if (!val) {
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ return;
-+ }
-+
-+ mdelay(1);
-+ }
-+
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+
-+ if (netif_msg_link(tp))
-+ printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
-+}
-+
-+static void
-+rtl8168dp_10mbps_gphy_para(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u8 status = RTL_R8(PHYstatus);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ if ((status & LinkStatus) && (status & _10bps)) {
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x10, 0x04EE);
-+ } else {
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x10, 0x01EE);
-+ }
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+}
-+
-+void rtl8168_init_ring_indexes(struct rtl8168_private *tp)
-+{
-+ tp->dirty_tx = 0;
-+ tp->dirty_rx = 0;
-+ tp->cur_tx = 0;
-+ tp->cur_rx = 0;
-+}
-+
-+static void
-+rtl8168_issue_offset_99_event(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 csi_tmp;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ if (tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) {
-+ rtl8168_eri_write(ioaddr, 0x3FC, 4, 0x00000000, ERIAR_ExGMAC);
-+ } else {
-+ rtl8168_eri_write(ioaddr, 0x3FC, 4, 0x083C083C, ERIAR_ExGMAC);
-+ }
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F8, 1, ERIAR_ExGMAC);
-+ csi_tmp |= BIT_0;
-+ rtl8168_eri_write(ioaddr, 0x3F8, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1EA, 1, ERIAR_ExGMAC);
-+ csi_tmp |= BIT_0;
-+ rtl8168_eri_write(ioaddr, 0x1EA, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+}
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+static void
-+NICChkTypeEnableDashInterrupt(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (tp->DASH) {
-+ //
-+ // even disconnected, enable 3 dash interrupt mask bits for in-band/out-band communication
-+ //
-+ if( HW_DASH_SUPPORT_TYPE_2( tp ) ) {
-+ rtl8168_enable_dash2_interrupt(tp, ioaddr);
-+ RTL_W16(IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET));
-+ } else {
-+ RTL_W16(IntrMask, (ISRIMR_DP_DASH_OK | ISRIMR_DP_HOST_OK | ISRIMR_DP_REQSYS_OK));
-+ }
-+ }
-+}
-+#endif
-+
-+static void
-+rtl8168_check_link_status(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int link_status_on;
-+ unsigned long flags;
-+
-+ link_status_on = tp->link_ok(dev);
-+
-+ if (tp->mcfg == CFG_METHOD_11)
-+ rtl8168dp_10mbps_gphy_para(dev);
-+
-+ if (netif_carrier_ok(dev) != link_status_on) {
-+ if (link_status_on) {
-+ if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 || tp->mcfg == CFG_METHOD_20) {
-+ if (RTL_R8(PHYstatus) & _1000bpsF) {
-+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC);
-+ } else {
-+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC);
-+ }
-+ } else if ((tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17) && netif_running(dev)) {
-+ if (tp->mcfg == CFG_METHOD_16 && (RTL_R8(PHYstatus) & _10bps)) {
-+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptAllPhys);
-+ } else if (tp->mcfg == CFG_METHOD_17) {
-+ if (RTL_R8(PHYstatus) & _1000bpsF) {
-+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC);
-+ } else if (RTL_R8(PHYstatus) & _100bps) {
-+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC);
-+ } else {
-+ rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC);
-+ }
-+ }
-+ } else if ((tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) && eee_enable ==1) {
-+ /*Full -Duplex mode*/
-+ if (RTL_R8(PHYstatus)&FullDup) {
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0006);
-+ mdio_write(tp, 0x00, 0x5a30);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ if (RTL_R8(PHYstatus) & (_10bps | _100bps))
-+ RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~BIT_19) | BIT_25);
-+
-+ } else {
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0006);
-+ mdio_write(tp, 0x00, 0x5a00);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ if (RTL_R8(PHYstatus) & (_10bps | _100bps))
-+ RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~BIT_19) | (InterFrameGap << TxInterFrameGapShift));
-+ }
-+ } else if ((tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
-+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
-+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
-+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) &&
-+ netif_running(dev)) {
-+ if (RTL_R8(PHYstatus)&FullDup)
-+ RTL_W32(TxConfig, (RTL_R32(TxConfig) | (BIT_24 | BIT_25)) & ~BIT_19);
-+ else
-+ RTL_W32(TxConfig, (RTL_R32(TxConfig) | BIT_25) & ~(BIT_19 | BIT_24));
-+ }
-+
-+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) {
-+ /*half mode*/
-+ if (!(RTL_R8(PHYstatus)&FullDup)) {
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, MII_ADVERTISE, mdio_read(tp, MII_ADVERTISE)&~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM));
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+ }
-+
-+ rtl8168_hw_start(dev);
-+
-+ netif_carrier_on(dev);
-+
-+ netif_wake_queue(dev);
-+
-+ if (netif_msg_ifup(tp))
-+ printk(KERN_INFO PFX "%s: link up\n", dev->name);
-+ } else {
-+ if (netif_msg_ifdown(tp))
-+ printk(KERN_INFO PFX "%s: link down\n", dev->name);
-+
-+ netif_stop_queue(dev);
-+
-+ netif_carrier_off(dev);
-+
-+ rtl8168_hw_reset(dev);
-+
-+ rtl8168_tx_clear(tp);
-+
-+ rtl8168_rx_clear(tp);
-+
-+ rtl8168_init_ring(dev);
-+
-+ rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ if (tp->org_pci_offset_99 & BIT_2)
-+ tp->issue_offset_99_event = TRUE;
-+ break;
-+ }
-+
-+#ifdef ENABLE_DASH_SUPPORT
-+ if (tp->DASH) {
-+ NICChkTypeEnableDashInterrupt(tp);
-+ }
-+#endif
-+ }
-+ }
-+
-+ if (!link_status_on) {
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ if (tp->issue_offset_99_event) {
-+ if (!(RTL_R8(PHYstatus) & PowerSaveStatus)) {
-+ tp->issue_offset_99_event = FALSE;
-+ rtl8168_issue_offset_99_event(tp);
-+ }
-+ }
-+ break;
-+ }
-+ }
-+}
-+
-+static void
-+rtl8168_link_option(u8 *aut,
-+ u16 *spd,
-+ u8 *dup)
-+{
-+ if ((*spd != SPEED_1000) && (*spd != SPEED_100) && (*spd != SPEED_10))
-+ *spd = SPEED_1000;
-+
-+ if ((*dup != DUPLEX_FULL) && (*dup != DUPLEX_HALF))
-+ *dup = DUPLEX_FULL;
-+
-+ if ((*aut != AUTONEG_ENABLE) && (*aut != AUTONEG_DISABLE))
-+ *aut = AUTONEG_ENABLE;
-+}
-+
-+void
-+rtl8168_wait_ll_share_fifo_ready(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i;
-+
-+ for (i = 0; i < 10; i++) {
-+ udelay(100);
-+ if (RTL_R16(0xD2) & BIT_9)
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_disable_pci_offset_99(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 csi_tmp;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC);
-+ csi_tmp &= ~(BIT_0 | BIT_1);
-+ rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ rtl8168_csi_fun0_write_byte(tp, 0x99, 0x00);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_enable_pci_offset_99(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 csi_tmp;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ rtl8168_csi_fun0_write_byte(tp, 0x99, tp->org_pci_offset_99);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC);
-+ csi_tmp &= ~(BIT_0 | BIT_1);
-+ if (!(tp->org_pci_offset_99 & (BIT_5 | BIT_6)))
-+ csi_tmp |= BIT_1;
-+ if (!(tp->org_pci_offset_99 & BIT_2))
-+ csi_tmp |= BIT_0;
-+ rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_init_pci_offset_99(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 csi_tmp;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_26:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C2, 1, ERIAR_ExGMAC);
-+ csi_tmp &= ~BIT_1;
-+ rtl8168_eri_write(ioaddr, 0x5C2, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC);
-+ csi_tmp &= ~( BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 | BIT_13 | BIT_14 | BIT_15 );
-+ csi_tmp |= ( BIT_9 | BIT_10 | BIT_13 | BIT_14 | BIT_15 );
-+ rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3F5, 1, ERIAR_ExGMAC);
-+ csi_tmp |= BIT_6 | BIT_7;
-+ rtl8168_eri_write(ioaddr, 0x3F5, 1, csi_tmp, ERIAR_ExGMAC);
-+ mac_ocp_write(tp, 0xE02C, 0x1880);
-+ mac_ocp_write(tp, 0xE02E, 0x4880);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_26:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC);
-+ csi_tmp |= BIT_0;
-+ rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_23:
-+ rtl8168_eri_write(ioaddr, 0x2E8, 2, 0x883C, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2EA, 2, 0x8C12, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2EC, 2, 0x9003, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2E2, 2, 0x883C, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2E6, 2, 0x9003, ERIAR_ExGMAC);
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ rtl8168_eri_write(ioaddr, 0x2E8, 2, 0x9003, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2EA, 2, 0x9003, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2EC, 2, 0x9003, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2E2, 2, 0x883C, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC);
-+ rtl8168_eri_write(ioaddr, 0x2E6, 2, 0x9003, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W8(0xB6, RTL_R8(0xB6) | BIT_0);
-+
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC);
-+ csi_tmp |= BIT_0;
-+ rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x3FA, 2, ERIAR_ExGMAC);
-+ csi_tmp |= BIT_14;
-+ rtl8168_eri_write(ioaddr, 0x3FA, 2, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ rtl8168_enable_pci_offset_99(tp);
-+}
-+
-+static void
-+rtl8168_disable_pci_offset_180(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 csi_tmp;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E2, 1, ERIAR_ExGMAC);
-+ csi_tmp &= ~BIT_2;
-+ rtl8168_eri_write(ioaddr, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_26:
-+ rtl8168_eri_write(ioaddr, 0x1E9, 1, 0x0A, ERIAR_ExGMAC);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_enable_pci_offset_180(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u32 csi_tmp;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_28:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E8, 4, ERIAR_ExGMAC);
-+ csi_tmp &= ~(0x0000FF00);
-+ csi_tmp |= (0x00006400);
-+ rtl8168_eri_write(ioaddr, 0x1E8, 4, csi_tmp, ERIAR_ExGMAC);
-+
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E4, 4, ERIAR_ExGMAC);
-+ csi_tmp &= ~(0x0000FF00);
-+ rtl8168_eri_write(ioaddr, 0x1E4, 4, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x1E2, 1, ERIAR_ExGMAC);
-+ csi_tmp |= BIT_2;
-+ rtl8168_eri_write(ioaddr, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_26:
-+ rtl8168_eri_write(ioaddr, 0x1E9, 1, 0x64, ERIAR_ExGMAC);
-+ break;
-+ }
-+
-+ mac_ocp_write(tp, 0xE094, 0x0000);
-+}
-+
-+static void
-+rtl8168_init_pci_offset_180(struct rtl8168_private *tp)
-+{
-+ if (tp->org_pci_offset_180 & (BIT_0|BIT_1))
-+ rtl8168_enable_pci_offset_180(tp);
-+ else
-+ rtl8168_disable_pci_offset_180(tp);
-+}
-+
-+static void
-+rtl8168_set_pci_99_180_exit_driver_para(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ rtl8168_issue_offset_99_event(tp);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ rtl8168_disable_pci_offset_99(tp);
-+ break;
-+ }
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ rtl8168_disable_pci_offset_180(tp);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_hw_d3_para(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+
-+ RTL_W16(RxMaxSize, RX_BUF_SIZE);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7);
-+ RTL_W8(Cfg9346, Cfg9346_Unlock);
-+ RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7);
-+ RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0);
-+ RTL_W8(Cfg9346, Cfg9346_Lock);
-+ break;
-+ }
-+
-+ if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
-+ tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
-+ tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) {
-+ rtl8168_eri_write(ioaddr, 0x2F8, 2, 0x0064, ERIAR_ExGMAC);
-+ }
-+
-+ if (tp->bios_setting & BIT_28) {
-+ if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 ||
-+ tp->mcfg == CFG_METHOD_20) {
-+ u32 gphy_val;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, 0x04, 0x0061);
-+ mdio_write(tp, 0x09, 0x0000);
-+ mdio_write(tp, 0x00, 0x9200);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B80);
-+ gphy_val = mdio_read(tp, 0x06);
-+ gphy_val &= ~BIT_7;
-+ mdio_write(tp, 0x06, gphy_val);
-+ mdelay(1);
-+ mdio_write(tp, 0x1F, 0x0007);
-+ mdio_write(tp, 0x1E, 0x002C);
-+ gphy_val = mdio_read(tp, 0x16);
-+ gphy_val &= ~BIT_10;
-+ mdio_write(tp, 0x16, gphy_val);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+ }
-+
-+ rtl8168_set_pci_99_180_exit_driver_para(dev);
-+
-+ /*disable ocp phy power saving*/
-+ if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
-+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0000);
-+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0500);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+
-+ rtl8168_disable_rxdvgate(dev);
-+}
-+
-+#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
-+
-+static void
-+rtl8168_get_hw_wol(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u8 options;
-+ u32 csi_tmp;
-+ unsigned long flags;
-+
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+
-+ tp->wol_opts = 0;
-+ options = RTL_R8(Config1);
-+ if (!(options & PMEnable))
-+ goto out_unlock;
-+
-+ options = RTL_R8(Config3);
-+ if (options & LinkUp)
-+ tp->wol_opts |= WAKE_PHY;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC);
-+ if (csi_tmp & BIT_0)
-+ tp->wol_opts |= WAKE_MAGIC;
-+ break;
-+ default:
-+ if (options & MagicPacket)
-+ tp->wol_opts |= WAKE_MAGIC;
-+ break;
-+ }
-+
-+ options = RTL_R8(Config5);
-+ if (options & UWF)
-+ tp->wol_opts |= WAKE_UCAST;
-+ if (options & BWF)
-+ tp->wol_opts |= WAKE_BCAST;
-+ if (options & MWF)
-+ tp->wol_opts |= WAKE_MCAST;
-+
-+out_unlock:
-+ tp->wol_enabled = (tp->wol_opts) ? WOL_ENABLED : WOL_DISABLED;
-+
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+}
-+
-+static void
-+rtl8168_set_hw_wol(struct net_device *dev, u32 wolopts)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int i,tmp;
-+ u32 csi_tmp;
-+ static struct {
-+ u32 opt;
-+ u16 reg;
-+ u8 mask;
-+ } cfg[] = {
-+ { WAKE_PHY, Config3, LinkUp },
-+ { WAKE_UCAST, Config5, UWF },
-+ { WAKE_BCAST, Config5, BWF },
-+ { WAKE_MCAST, Config5, MWF },
-+ { WAKE_ANY, Config5, LanWake },
-+ { WAKE_MAGIC, Config3, MagicPacket },
-+ };
-+
-+ RTL_W8(Cfg9346, Cfg9346_Unlock);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ tmp = ARRAY_SIZE(cfg) - 1;
-+
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC);
-+ if (wolopts & WAKE_MAGIC)
-+ csi_tmp |= BIT_0;
-+ else
-+ csi_tmp &= ~BIT_0;
-+ rtl8168_eri_write(ioaddr, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
-+ break;
-+ default:
-+ tmp = ARRAY_SIZE(cfg);
-+ break;
-+ }
-+
-+ for (i = 0; i < tmp; i++) {
-+ u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
-+ if (wolopts & cfg[i].opt)
-+ options |= cfg[i].mask;
-+ RTL_W8(cfg[i].reg, options);
-+ }
-+
-+ RTL_W8(Cfg9346, Cfg9346_Lock);
-+}
-+
-+static void
-+rtl8168_powerdown_pll(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (tp->wol_enabled == WOL_ENABLED || tp->DASH || tp->EnableKCPOffload) {
-+ int auto_nego;
-+ int giga_ctrl;
-+ u16 val;
-+ unsigned long flags;
-+
-+ rtl8168_set_hw_wol(dev, tp->wol_opts);
-+
-+ if (tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17 ||
-+ tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
-+ tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 ||
-+ tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_23 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
-+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ RTL_W8(Cfg9346, Cfg9346_Unlock);
-+ RTL_W8(Config2, RTL_R8(Config2) | PMSTS_En);
-+ RTL_W8(Cfg9346, Cfg9346_Lock);
-+ }
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ auto_nego = mdio_read(tp, MII_ADVERTISE);
-+ auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL
-+ | ADVERTISE_100HALF | ADVERTISE_100FULL);
-+
-+ val = mdio_read(tp, MII_LPA);
-+
-+#ifdef CONFIG_DOWN_SPEED_100
-+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL);
-+#else
-+ if (val & (LPA_10HALF | LPA_10FULL))
-+ auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL);
-+ else
-+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL);
-+#endif
-+
-+ if (tp->DASH)
-+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL);
-+
-+ if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(CPlusCmd) & ASF))
-+ auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL);
-+
-+ giga_ctrl = mdio_read(tp, MII_CTRL1000) & ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
-+ mdio_write(tp, MII_ADVERTISE, auto_nego);
-+ mdio_write(tp, MII_CTRL1000, giga_ctrl);
-+ mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+
-+ RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
-+
-+ return;
-+ }
-+
-+ if (tp->DASH)
-+ return;
-+
-+ if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(CPlusCmd) & ASF))
-+ return;
-+
-+ rtl8168_phy_power_down(dev);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_9:
-+ case CFG_METHOD_10:
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ case CFG_METHOD_13:
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W8(PMCH, RTL_R8(PMCH) & ~BIT_7);
-+ break;
-+ }
-+}
-+
-+static void rtl8168_powerup_pll(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_9:
-+ case CFG_METHOD_10:
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ case CFG_METHOD_13:
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W8(PMCH, RTL_R8(PMCH) | BIT_7 | BIT_6);
-+ break;
-+ }
-+
-+ rtl8168_phy_power_up(dev);
-+}
-+
-+static void
-+rtl8168_get_wol(struct net_device *dev,
-+ struct ethtool_wolinfo *wol)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u8 options;
-+ unsigned long flags;
-+
-+ wol->wolopts = 0;
-+
-+ if (tp->mcfg == CFG_METHOD_DEFAULT) {
-+ wol->supported = 0;
-+ return;
-+ } else {
-+ wol->supported = WAKE_ANY;
-+ }
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+
-+ options = RTL_R8(Config1);
-+ if (!(options & PMEnable))
-+ goto out_unlock;
-+
-+ wol->wolopts = tp->wol_opts;
-+
-+out_unlock:
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+}
-+
-+static int
-+rtl8168_set_wol(struct net_device *dev,
-+ struct ethtool_wolinfo *wol)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ if (tp->mcfg == CFG_METHOD_DEFAULT)
-+ return -EOPNOTSUPP;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+
-+ tp->wol_opts = wol->wolopts;
-+
-+ tp->wol_enabled = (tp->wol_opts) ? WOL_ENABLED : WOL_DISABLED;
-+
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return 0;
-+}
-+
-+static void
-+rtl8168_get_drvinfo(struct net_device *dev,
-+ struct ethtool_drvinfo *info)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ strcpy(info->driver, MODULENAME);
-+ strcpy(info->version, RTL8168_VERSION);
-+ strcpy(info->bus_info, pci_name(tp->pci_dev));
-+ info->regdump_len = R8168_REGS_DUMP_SIZE;
-+ info->eedump_len = tp->eeprom_len;
-+}
-+
-+static int
-+rtl8168_get_regs_len(struct net_device *dev)
-+{
-+ return R8168_REGS_DUMP_SIZE;
-+}
-+
-+static int
-+rtl8168_set_speed_xmii(struct net_device *dev,
-+ u8 autoneg,
-+ u16 speed,
-+ u8 duplex)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ int auto_nego = 0;
-+ int giga_ctrl = 0;
-+ int bmcr_true_force = 0;
-+ unsigned long flags;
-+
-+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ //Disable Giga Lite
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ ClearEthPhyBit(tp, 0x14, BIT_9);
-+ mdio_write(tp, 0x1F, 0x0A40);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+
-+ if ((speed != SPEED_1000) &&
-+ (speed != SPEED_100) &&
-+ (speed != SPEED_10)) {
-+ speed = SPEED_1000;
-+ duplex = DUPLEX_FULL;
-+ }
-+
-+ auto_nego = mdio_read(tp, MII_ADVERTISE);
-+ auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
-+
-+ giga_ctrl = mdio_read(tp, MII_CTRL1000);
-+ giga_ctrl &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
-+
-+ if ((autoneg == AUTONEG_ENABLE) || (speed == SPEED_1000)) {
-+ /*n-way force*/
-+ if ((speed == SPEED_10) && (duplex == DUPLEX_HALF)) {
-+ auto_nego |= ADVERTISE_10HALF;
-+ } else if ((speed == SPEED_10) && (duplex == DUPLEX_FULL)) {
-+ auto_nego |= ADVERTISE_10HALF |
-+ ADVERTISE_10FULL;
-+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_HALF)) {
-+ auto_nego |= ADVERTISE_100HALF |
-+ ADVERTISE_10HALF |
-+ ADVERTISE_10FULL;
-+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_FULL)) {
-+ auto_nego |= ADVERTISE_100HALF |
-+ ADVERTISE_100FULL |
-+ ADVERTISE_10HALF |
-+ ADVERTISE_10FULL;
-+ } else if (speed == SPEED_1000) {
-+ giga_ctrl |= ADVERTISE_1000HALF |
-+ ADVERTISE_1000FULL;
-+
-+ auto_nego |= ADVERTISE_100HALF |
-+ ADVERTISE_100FULL |
-+ ADVERTISE_10HALF |
-+ ADVERTISE_10FULL;
-+ }
-+
-+ //flow control
-+ if (dev->mtu <= ETH_DATA_LEN)
-+ auto_nego |= ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM;
-+
-+ tp->phy_auto_nego_reg = auto_nego;
-+ tp->phy_1000_ctrl_reg = giga_ctrl;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, MII_ADVERTISE, auto_nego);
-+ mdio_write(tp, MII_CTRL1000, giga_ctrl);
-+ mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ mdelay(20);
-+ } else {
-+ /*true force*/
-+#ifndef BMCR_SPEED100
-+#define BMCR_SPEED100 0x0040
-+#endif
-+
-+#ifndef BMCR_SPEED10
-+#define BMCR_SPEED10 0x0000
-+#endif
-+ if ((speed == SPEED_10) && (duplex == DUPLEX_HALF)) {
-+ bmcr_true_force = BMCR_SPEED10;
-+ } else if ((speed == SPEED_10) && (duplex == DUPLEX_FULL)) {
-+ bmcr_true_force = BMCR_SPEED10 | BMCR_FULLDPLX;
-+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_HALF)) {
-+ bmcr_true_force = BMCR_SPEED100;
-+ } else if ((speed == SPEED_100) && (duplex == DUPLEX_FULL)) {
-+ bmcr_true_force = BMCR_SPEED100 | BMCR_FULLDPLX;
-+ }
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, MII_BMCR, bmcr_true_force);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+
-+ tp->autoneg = autoneg;
-+ tp->speed = speed;
-+ tp->duplex = duplex;
-+
-+ if (tp->mcfg == CFG_METHOD_11)
-+ rtl8168dp_10mbps_gphy_para(dev);
-+
-+ return 0;
-+}
-+
-+static int
-+rtl8168_set_speed(struct net_device *dev,
-+ u8 autoneg,
-+ u16 speed,
-+ u8 duplex)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ int ret;
-+
-+ ret = tp->set_speed(dev, autoneg, speed, duplex);
-+
-+ return ret;
-+}
-+
-+static int
-+rtl8168_set_settings(struct net_device *dev,
-+ struct ethtool_cmd *cmd)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ int ret;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ ret = rtl8168_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return ret;
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-+static u32
-+rtl8168_get_tx_csum(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ u32 ret;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ ret = ((dev->features & NETIF_F_IP_CSUM) != 0);
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return ret;
-+}
-+
-+static u32
-+rtl8168_get_rx_csum(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ u32 ret;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ ret = tp->cp_cmd & RxChkSum;
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return ret;
-+}
-+
-+static int
-+rtl8168_set_tx_csum(struct net_device *dev,
-+ u32 data)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ if (tp->mcfg == CFG_METHOD_DEFAULT)
-+ return -EOPNOTSUPP;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+
-+ if (data)
-+ dev->features |= NETIF_F_IP_CSUM;
-+ else
-+ dev->features &= ~NETIF_F_IP_CSUM;
-+
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int
-+rtl8168_set_rx_csum(struct net_device *dev,
-+ u32 data)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+
-+ if (tp->mcfg == CFG_METHOD_DEFAULT)
-+ return -EOPNOTSUPP;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+
-+ if (data)
-+ tp->cp_cmd |= RxChkSum;
-+ else
-+ tp->cp_cmd &= ~RxChkSum;
-+
-+ RTL_W16(CPlusCmd, tp->cp_cmd);
-+
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return 0;
-+}
-+#endif
-+
-+#ifdef CONFIG_R8168_VLAN
-+
-+static inline u32
-+rtl8168_tx_vlan_tag(struct rtl8168_private *tp,
-+ struct sk_buff *skb)
-+{
-+ u32 tag;
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
-+ tag = (tp->vlgrp && vlan_tx_tag_present(skb)) ?
-+ TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
-+#elif LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0)
-+ tag = (vlan_tx_tag_present(skb)) ?
-+ TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
-+#else
-+ tag = (skb_vlan_tag_present(skb)) ?
-+ TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
-+#endif
-+
-+ return tag;
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
-+
-+static void
-+rtl8168_vlan_rx_register(struct net_device *dev,
-+ struct vlan_group *grp)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ tp->vlgrp = grp;
-+ if (tp->vlgrp)
-+ tp->cp_cmd |= RxVlan;
-+ else
-+ tp->cp_cmd &= ~RxVlan;
-+ RTL_W16(CPlusCmd, tp->cp_cmd);
-+ RTL_R16(CPlusCmd);
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+}
-+
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
-+static void
-+rtl8168_vlan_rx_kill_vid(struct net_device *dev,
-+ unsigned short vid)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)
-+ if (tp->vlgrp)
-+ tp->vlgrp->vlan_devices[vid] = NULL;
-+#else
-+ vlan_group_set_device(tp->vlgrp, vid, NULL);
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+}
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
-+
-+static int
-+rtl8168_rx_vlan_skb(struct rtl8168_private *tp,
-+ struct RxDesc *desc,
-+ struct sk_buff *skb)
-+{
-+ u32 opts2 = le32_to_cpu(desc->opts2);
-+ int ret = -1;
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
-+ if (tp->vlgrp && (opts2 & RxVlanTag)) {
-+ rtl8168_rx_hwaccel_skb(skb, tp->vlgrp,
-+ swab16(opts2 & 0xffff));
-+ ret = 0;
-+ }
-+#elif LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
-+ if (opts2 & RxVlanTag)
-+ __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
-+#else
-+ if (opts2 & RxVlanTag)
-+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
-+#endif
-+
-+ desc->opts2 = 0;
-+ return ret;
-+}
-+
-+#else /* !CONFIG_R8168_VLAN */
-+
-+static inline u32
-+rtl8168_tx_vlan_tag(struct rtl8168_private *tp,
-+ struct sk_buff *skb)
-+{
-+ return 0;
-+}
-+
-+static int
-+rtl8168_rx_vlan_skb(struct rtl8168_private *tp,
-+ struct RxDesc *desc,
-+ struct sk_buff *skb)
-+{
-+ return -1;
-+}
-+
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-+static u32 rtl8168_fix_features(struct net_device *dev, u32 features)
-+#else
-+static netdev_features_t rtl8168_fix_features(struct net_device *dev,
-+ netdev_features_t features)
-+#endif
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ if (dev->mtu > ETH_DATA_LEN) {
-+ features &= ~NETIF_F_ALL_TSO;
-+ features &= ~NETIF_F_ALL_CSUM;
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return features;
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-+static int rtl8168_hw_set_features(struct net_device *dev, u32 features)
-+#else
-+static int rtl8168_hw_set_features(struct net_device *dev,
-+ netdev_features_t features)
-+#endif
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (features & NETIF_F_RXCSUM)
-+ tp->cp_cmd |= RxChkSum;
-+ else
-+ tp->cp_cmd &= ~RxChkSum;
-+
-+ if (dev->features & NETIF_F_HW_VLAN_RX)
-+ tp->cp_cmd |= RxVlan;
-+ else
-+ tp->cp_cmd &= ~RxVlan;
-+
-+ RTL_W16(CPlusCmd, tp->cp_cmd);
-+ RTL_R16(CPlusCmd);
-+
-+ return 0;
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-+static int rtl8168_set_features(struct net_device *dev, u32 features)
-+#else
-+static int rtl8168_set_features(struct net_device *dev,
-+ netdev_features_t features)
-+#endif
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+
-+ rtl8168_hw_set_features(dev, features);
-+
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ return 0;
-+}
-+
-+#endif
-+
-+static void rtl8168_gset_xmii(struct net_device *dev,
-+ struct ethtool_cmd *cmd)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u8 status;
-+ unsigned long flags;
-+
-+ cmd->supported = SUPPORTED_10baseT_Half |
-+ SUPPORTED_10baseT_Full |
-+ SUPPORTED_100baseT_Half |
-+ SUPPORTED_100baseT_Full |
-+ SUPPORTED_1000baseT_Full |
-+ SUPPORTED_Autoneg |
-+ SUPPORTED_TP;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ cmd->autoneg = (mdio_read(tp, MII_BMCR) & BMCR_ANENABLE) ? 1 : 0;
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
-+
-+ if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
-+ cmd->advertising |= ADVERTISED_10baseT_Half;
-+ if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
-+ cmd->advertising |= ADVERTISED_10baseT_Full;
-+ if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
-+ cmd->advertising |= ADVERTISED_100baseT_Half;
-+ if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
-+ cmd->advertising |= ADVERTISED_100baseT_Full;
-+ if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
-+ cmd->advertising |= ADVERTISED_1000baseT_Full;
-+
-+ status = RTL_R8(PHYstatus);
-+
-+ if (status & _1000bpsF)
-+ cmd->speed = SPEED_1000;
-+ else if (status & _100bps)
-+ cmd->speed = SPEED_100;
-+ else if (status & _10bps)
-+ cmd->speed = SPEED_10;
-+
-+ if (status & TxFlowCtrl)
-+ cmd->advertising |= ADVERTISED_Asym_Pause;
-+
-+ if (status & RxFlowCtrl)
-+ cmd->advertising |= ADVERTISED_Pause;
-+
-+ cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
-+ DUPLEX_FULL : DUPLEX_HALF;
-+
-+
-+}
-+
-+static int
-+rtl8168_get_settings(struct net_device *dev,
-+ struct ethtool_cmd *cmd)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ tp->get_settings(dev, cmd);
-+
-+ return 0;
-+}
-+
-+static void rtl8168_get_regs(struct net_device *dev, struct ethtool_regs *regs,
-+ void *p)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned int i;
-+ u8 *data = p;
-+ unsigned long flags;
-+
-+ if (regs->len < R8168_REGS_DUMP_SIZE)
-+ return /* -EINVAL */;
-+
-+ memset(p, 0, regs->len);
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ for (i = 0; i < R8168_MAC_REGS_SIZE; i++)
-+ *data++ = readb(ioaddr + i);
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+ data = (u8*)p + 256;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ for (i = 0; i < R8168_PHY_REGS_SIZE/2; i++) {
-+ *(u16*)data = mdio_read(tp, i);
-+ data += 2;
-+ }
-+ data = (u8*)p + 256 * 2;
-+
-+ for (i = 0; i < R8168_EPHY_REGS_SIZE/2; i++) {
-+ *(u16*)data = rtl8168_ephy_read(ioaddr, i);
-+ data += 2;
-+ }
-+ data = (u8*)p + 256 * 3;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_1:
-+ case CFG_METHOD_2:
-+ case CFG_METHOD_3:
-+ /* RTL8168B does not support Extend GMAC */
-+ break;
-+ default:
-+ for (i = 0; i < R8168_ERI_REGS_SIZE; i+=4) {
-+ *(u32*)data = rtl8168_eri_read(ioaddr, i , 4, ERIAR_ExGMAC);
-+ data += 4;
-+ }
-+ break;
-+ }
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+}
-+
-+static u32
-+rtl8168_get_msglevel(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ return tp->msg_enable;
-+}
-+
-+static void
-+rtl8168_set_msglevel(struct net_device *dev,
-+ u32 value)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ tp->msg_enable = value;
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)
-+static int rtl8168_get_stats_count(struct net_device *dev)
-+{
-+ return ARRAY_SIZE(rtl8168_gstrings);
-+}
-+#else
-+static int rtl8168_get_sset_count(struct net_device *dev, int sset)
-+{
-+ switch (sset) {
-+ case ETH_SS_STATS:
-+ return ARRAY_SIZE(rtl8168_gstrings);
-+ default:
-+ return -EOPNOTSUPP;
-+ }
-+}
-+#endif
-+static void
-+rtl8168_get_ethtool_stats(struct net_device *dev,
-+ struct ethtool_stats *stats,
-+ u64 *data)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ struct rtl8168_counters *counters;
-+ dma_addr_t paddr;
-+ u32 cmd;
-+ u32 WaitCnt;
-+ unsigned long flags;
-+
-+ ASSERT_RTNL();
-+
-+ counters = tp->tally_vaddr;
-+ paddr = tp->tally_paddr;
-+ if (!counters)
-+ return;
-+
-+ spin_lock_irqsave(&tp->lock, flags);
-+ RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
-+ cmd = (u64)paddr & DMA_BIT_MASK(32);
-+ RTL_W32(CounterAddrLow, cmd);
-+ RTL_W32(CounterAddrLow, cmd | CounterDump);
-+
-+ WaitCnt = 0;
-+ while (RTL_R32(CounterAddrLow) & CounterDump) {
-+ udelay(10);
-+
-+ WaitCnt++;
-+ if (WaitCnt > 20)
-+ break;
-+ }
-+ spin_unlock_irqrestore(&tp->lock, flags);
-+
-+ data[0] = le64_to_cpu(counters->tx_packets);
-+ data[1] = le64_to_cpu(counters->rx_packets);
-+ data[2] = le64_to_cpu(counters->tx_errors);
-+ data[3] = le32_to_cpu(counters->rx_errors);
-+ data[4] = le16_to_cpu(counters->rx_missed);
-+ data[5] = le16_to_cpu(counters->align_errors);
-+ data[6] = le32_to_cpu(counters->tx_one_collision);
-+ data[7] = le32_to_cpu(counters->tx_multi_collision);
-+ data[8] = le64_to_cpu(counters->rx_unicast);
-+ data[9] = le64_to_cpu(counters->rx_broadcast);
-+ data[10] = le32_to_cpu(counters->rx_multicast);
-+ data[11] = le16_to_cpu(counters->tx_aborted);
-+ data[12] = le16_to_cpu(counters->tx_underun);
-+}
-+
-+static void
-+rtl8168_get_strings(struct net_device *dev,
-+ u32 stringset,
-+ u8 *data)
-+{
-+ switch (stringset) {
-+ case ETH_SS_STATS:
-+ memcpy(data, *rtl8168_gstrings, sizeof(rtl8168_gstrings));
-+ break;
-+ }
-+}
-+static int rtl_get_eeprom_len(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ return tp->eeprom_len;
-+}
-+
-+static int rtl_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *buf)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ int i,j,ret;
-+ int start_w, end_w;
-+ int VPD_addr, VPD_data;
-+ u32 *eeprom_buff;
-+ u16 tmp;
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (tp->eeprom_type == EEPROM_TYPE_NONE) {
-+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Detect none EEPROM\n");
-+ return -EOPNOTSUPP;
-+ } else if (eeprom->len == 0 || (eeprom->offset+eeprom->len) > tp->eeprom_len) {
-+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Invalid parameter\n");
-+ return -EINVAL;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_9:
-+ case CFG_METHOD_10:
-+ VPD_addr = 0xCE;
-+ VPD_data = 0xD0;
-+ break;
-+
-+ case CFG_METHOD_1:
-+ case CFG_METHOD_2:
-+ case CFG_METHOD_3:
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ case CFG_METHOD_13:
-+ return -EOPNOTSUPP;
-+ default:
-+ VPD_addr = 0xD2;
-+ VPD_data = 0xD4;
-+ break;
-+ }
-+
-+ start_w = eeprom->offset >> 2;
-+ end_w = (eeprom->offset + eeprom->len - 1) >> 2;
-+
-+ eeprom_buff = kmalloc(sizeof(u32)*(end_w - start_w + 1), GFP_KERNEL);
-+ if (!eeprom_buff)
-+ return -ENOMEM;
-+
-+ RTL_W8(Cfg9346, Cfg9346_Unlock);
-+ ret = -EFAULT;
-+ for (i=start_w; i<=end_w; i++) {
-+ pci_write_config_word(tp->pci_dev, VPD_addr, (u16)i*4);
-+ ret = -EFAULT;
-+ for (j = 0; j < 10; j++) {
-+ udelay(400);
-+ pci_read_config_word(tp->pci_dev, VPD_addr, &tmp);
-+ if (tmp&0x8000) {
-+ ret = 0;
-+ break;
-+ }
-+ }
-+
-+ if (ret)
-+ break;
-+
-+ pci_read_config_dword(tp->pci_dev, VPD_data, &eeprom_buff[i-start_w]);
-+ }
-+ RTL_W8(Cfg9346, Cfg9346_Lock);
-+
-+ if (!ret)
-+ memcpy(buf, (u8 *)eeprom_buff + (eeprom->offset & 3), eeprom->len);
-+
-+ kfree(eeprom_buff);
-+
-+ return ret;
-+}
-+
-+#undef ethtool_op_get_link
-+#define ethtool_op_get_link _kc_ethtool_op_get_link
-+u32 _kc_ethtool_op_get_link(struct net_device *dev)
-+{
-+ return netif_carrier_ok(dev) ? 1 : 0;
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-+#undef ethtool_op_get_sg
-+#define ethtool_op_get_sg _kc_ethtool_op_get_sg
-+u32 _kc_ethtool_op_get_sg(struct net_device *dev)
-+{
-+#ifdef NETIF_F_SG
-+ return (dev->features & NETIF_F_SG) != 0;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+#undef ethtool_op_set_sg
-+#define ethtool_op_set_sg _kc_ethtool_op_set_sg
-+int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ if (tp->mcfg == CFG_METHOD_DEFAULT)
-+ return -EOPNOTSUPP;
-+
-+#ifdef NETIF_F_SG
-+ if (data)
-+ dev->features |= NETIF_F_SG;
-+ else
-+ dev->features &= ~NETIF_F_SG;
-+#endif
-+
-+ return 0;
-+}
-+#endif
-+
-+static const struct ethtool_ops rtl8168_ethtool_ops = {
-+ .get_drvinfo = rtl8168_get_drvinfo,
-+ .get_regs_len = rtl8168_get_regs_len,
-+ .get_link = ethtool_op_get_link,
-+ .get_settings = rtl8168_get_settings,
-+ .set_settings = rtl8168_set_settings,
-+ .get_msglevel = rtl8168_get_msglevel,
-+ .set_msglevel = rtl8168_set_msglevel,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
-+ .get_rx_csum = rtl8168_get_rx_csum,
-+ .set_rx_csum = rtl8168_set_rx_csum,
-+ .get_tx_csum = rtl8168_get_tx_csum,
-+ .set_tx_csum = rtl8168_set_tx_csum,
-+ .get_sg = ethtool_op_get_sg,
-+ .set_sg = ethtool_op_set_sg,
-+#ifdef NETIF_F_TSO
-+ .get_tso = ethtool_op_get_tso,
-+ .set_tso = ethtool_op_set_tso,
-+#endif
-+#endif
-+ .get_regs = rtl8168_get_regs,
-+ .get_wol = rtl8168_get_wol,
-+ .set_wol = rtl8168_set_wol,
-+ .get_strings = rtl8168_get_strings,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)
-+ .get_stats_count = rtl8168_get_stats_count,
-+#else
-+ .get_sset_count = rtl8168_get_sset_count,
-+#endif
-+ .get_ethtool_stats = rtl8168_get_ethtool_stats,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
-+#ifdef ETHTOOL_GPERMADDR
-+ .get_perm_addr = ethtool_op_get_perm_addr,
-+#endif
-+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
-+ .get_eeprom = rtl_get_eeprom,
-+ .get_eeprom_len = rtl_get_eeprom_len,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
-+ .get_ts_info = ethtool_op_get_ts_info,
-+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
-+};
-+
-+
-+static int rtl8168_enable_EEE(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int ret;
-+ u16 data;
-+ u16 PhyRegValue;
-+ u32 WaitCnt;
-+ unsigned long flags;
-+
-+ ret = 0;
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0007);
-+ mdio_write(tp, 0x1E, 0x0020);
-+ data = mdio_read(tp, 0x15) | 0x0100;
-+ mdio_write(tp, 0x15, data);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B85);
-+ data = mdio_read(tp, 0x06) | 0x2000;
-+ mdio_write(tp, 0x06, data);
-+ mdio_write(tp, 0x1F, 0x0006);
-+ mdio_write(tp, 0x00, 0x5A30);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0007);
-+ mdio_write(tp, 0x0E, 0x003C);
-+ mdio_write(tp, 0x0D, 0x4007);
-+ mdio_write(tp, 0x0E, 0x0006);
-+ mdio_write(tp, 0x0D, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ if ((RTL_R8(Config4)&0x40) && (RTL_R8(0x6D) & BIT_7)) {
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8AC8);
-+ mdio_write(tp, 0x06, RTL_R16(CustomLED));
-+ mdio_write(tp, 0x05, 0x8B82);
-+ data = mdio_read(tp, 0x06) | 0x0010;
-+ mdio_write(tp, 0x05, 0x8B82);
-+ mdio_write(tp, 0x06, data);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+ break;
-+
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC) | 0x0003;
-+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC);
-+ mdio_write(tp,0x1F , 0x0004);
-+ mdio_write(tp,0x1F , 0x0007);
-+ mdio_write(tp,0x1E , 0x0020);
-+ data = mdio_read(tp, 0x15)|0x0100;
-+ mdio_write(tp,0x15 , data);
-+ mdio_write(tp,0x1F , 0x0002);
-+ mdio_write(tp,0x1F , 0x0005);
-+ mdio_write(tp,0x05 , 0x8B85);
-+ data = mdio_read(tp, 0x06)|0x2000;
-+ mdio_write(tp,0x06 , data);
-+ mdio_write(tp,0x1F , 0x0000);
-+ mdio_write(tp,0x0D , 0x0007);
-+ mdio_write(tp,0x0E , 0x003C);
-+ mdio_write(tp,0x0D , 0x4007);
-+ mdio_write(tp,0x0E , 0x0006);
-+ mdio_write(tp,0x1D , 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC);
-+ data |= BIT_1 | BIT_0;
-+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC);
-+ mdio_write(tp, 0x1F, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0020);
-+ data = mdio_read(tp, 0x15);
-+ data |= BIT_8;
-+ mdio_write(tp, 0x15, data);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B85);
-+ data = mdio_read(tp, 0x06);
-+ data |= BIT_13;
-+ mdio_write(tp, 0x06, data);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0007);
-+ mdio_write(tp, 0x0E, 0x003C);
-+ mdio_write(tp, 0x0D, 0x4007);
-+ mdio_write(tp, 0x0E, 0x0006);
-+ mdio_write(tp, 0x0D, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ data = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
-+ data |= BIT_1 | BIT_0;
-+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ data = mdio_read(tp, 0x11);
-+ mdio_write(tp, 0x11, data | BIT_4);
-+ mdio_write(tp, 0x1F, 0x0A5D);
-+ mdio_write(tp, 0x10, 0x0006);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ default:
-+// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n");
-+ ret = -EOPNOTSUPP;
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A4A);
-+ SetEthPhyBit(tp, 0x11, BIT_9);
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ SetEthPhyBit(tp, 0x14, BIT_7);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ /*Advanced EEE*/
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp,0x1F, 0x0B82);
-+ SetEthPhyBit(tp, 0x10, BIT_4);
-+ mdio_write(tp, 0x1F, 0x0000);
-+
-+ mdio_write(tp,0x1F, 0x0B80);
-+ WaitCnt = 0;
-+ do {
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= 0x0040;
-+ udelay(100);
-+ WaitCnt++;
-+ } while(PhyRegValue != 0x0040 && WaitCnt <1000);
-+
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_25:
-+ rtl8168_eri_write(ioaddr, 0x1EA, 1, 0xFA, ERIAR_ExGMAC);
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ data = mdio_read(tp, 0x10);
-+ if (data & BIT_10) {
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ data = mdio_read(tp, 0x16);
-+ data &= ~(BIT_1);
-+ mdio_write(tp, 0x16, data);
-+ } else {
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ data = mdio_read(tp, 0x16);
-+ data |= BIT_1;
-+ mdio_write(tp, 0x16, data);
-+ }
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ case CFG_METHOD_26:
-+ data = mac_ocp_read(tp, 0xE052);
-+ data |= BIT_0;
-+ mac_ocp_write(tp, 0xE052, data);
-+ data = mac_ocp_read(tp, 0xE056);
-+ data &= 0xFF0F;
-+ data |= (BIT_4 | BIT_5 | BIT_6);
-+ mac_ocp_write(tp, 0xE056, data);
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ data = mdio_read(tp, 0x10);
-+ if (data & BIT_10) {
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ data = mdio_read(tp, 0x16);
-+ data &= ~(BIT_1);
-+ mdio_write(tp, 0x16, data);
-+ } else {
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ data = mdio_read(tp, 0x16);
-+ data |= BIT_1;
-+ mdio_write(tp, 0x16, data);
-+ }
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ OOB_mutex_lock(tp);
-+ data = mac_ocp_read(tp, 0xE052);
-+ data |= BIT_0;
-+ mac_ocp_write(tp, 0xE052, data);
-+ OOB_mutex_unlock(tp);
-+ data = mac_ocp_read(tp, 0xE056);
-+ data &= 0xFF0F;
-+ data |= (BIT_4 | BIT_5 | BIT_6);
-+ mac_ocp_write(tp, 0xE056, data);
-+ break;
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ data = mac_ocp_read(tp, 0xE052);
-+ data |= BIT_0;
-+ mac_ocp_write(tp, 0xE052, data);
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ data = mdio_read(tp, 0x10) | BIT_15;
-+ mdio_write(tp, 0x10, data);
-+
-+ mdio_write(tp, 0x1F, 0x0A44);
-+ data = mdio_read( tp, 0x11 ) | BIT_12 | BIT_13| BIT_14;
-+ mdio_write(tp, 0x11, data);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0B82);
-+ ClearEthPhyBit(tp, 0x10, BIT_4);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ return ret;
-+}
-+
-+static int rtl8168_disable_EEE(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ int ret;
-+ u16 data;
-+ u16 PhyRegValue;
-+ u32 WaitCnt;
-+ unsigned long flags;
-+
-+ ret = 0;
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B85);
-+ data = mdio_read(tp, 0x06) & ~0x2000;
-+ mdio_write(tp, 0x06, data);
-+ mdio_write(tp, 0x1F, 0x0007);
-+ mdio_write(tp, 0x1E, 0x0020);
-+ data = mdio_read(tp, 0x15) & ~0x0100;
-+ mdio_write(tp, 0x15, data);
-+ mdio_write(tp, 0x1F, 0x0006);
-+ mdio_write(tp, 0x00, 0x5A00);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0007);
-+ mdio_write(tp, 0x0E, 0x003C);
-+ mdio_write(tp, 0x0D, 0x4007);
-+ mdio_write(tp, 0x0E, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0000);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ if (RTL_R8(Config4) & 0x40) {
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B82);
-+ data = mdio_read(tp, 0x06) & ~0x0010;
-+ mdio_write(tp, 0x05, 0x8B82);
-+ mdio_write(tp, 0x06, data);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+ break;
-+
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC)& ~0x0003;
-+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B85);
-+ data = mdio_read(tp, 0x06) & ~0x2000;
-+ mdio_write(tp, 0x06, data);
-+ mdio_write(tp, 0x1F, 0x0004);
-+ mdio_write(tp, 0x1F, 0x0007);
-+ mdio_write(tp, 0x1E, 0x0020);
-+ data = mdio_read(tp, 0x15) & ~0x0100;
-+ mdio_write(tp,0x15 , data);
-+ mdio_write(tp, 0x1F, 0x0002);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0007);
-+ mdio_write(tp, 0x0E, 0x003C);
-+ mdio_write(tp, 0x0D, 0x4007);
-+ mdio_write(tp, 0x0E, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0000);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ data = rtl8168_eri_read(ioaddr,0x1B0 ,4,ERIAR_ExGMAC);
-+ data &= ~(BIT_1 | BIT_0);
-+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B85);
-+ data = mdio_read(tp, 0x06);
-+ data &= ~BIT_13;
-+ mdio_write(tp, 0x06, data);
-+ mdio_write(tp, 0x1F, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0020);
-+ data = mdio_read(tp, 0x15);
-+ data &= ~BIT_8;
-+ mdio_write(tp, 0x15, data);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0007);
-+ mdio_write(tp, 0x0E, 0x003C);
-+ mdio_write(tp, 0x0D, 0x4007);
-+ mdio_write(tp, 0x0E, 0x0000);
-+ mdio_write(tp, 0x0D, 0x0000);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ data = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
-+ data &= ~(BIT_1 | BIT_0);
-+ rtl8168_eri_write(ioaddr, 0x1B0, 4, data, ERIAR_ExGMAC);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ data = mdio_read(tp, 0x11);
-+ mdio_write(tp, 0x11, data & ~BIT_4);
-+ mdio_write(tp, 0x1F, 0x0A5D);
-+ mdio_write(tp, 0x10, 0x0000);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ default:
-+// dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support EEE\n");
-+ ret = -EOPNOTSUPP;
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ ClearEthPhyBit(tp, 0x14, BIT_7);
-+ mdio_write(tp, 0x1F, 0x0A4A);
-+ ClearEthPhyBit(tp, 0x11, BIT_9);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ /*Advanced EEE*/
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp,0x1F, 0x0B82);
-+ SetEthPhyBit(tp, 0x10, BIT_4);
-+ mdio_write(tp, 0x1F, 0x0000);
-+
-+ mdio_write(tp,0x1F, 0x0B80);
-+ WaitCnt = 0;
-+ do {
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= 0x0040;
-+ udelay(100);
-+ WaitCnt++;
-+ } while(PhyRegValue != 0x0040 && WaitCnt <1000);
-+
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_25:
-+ rtl8168_eri_write(ioaddr, 0x1EA, 1, 0x00, ERIAR_ExGMAC);
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ data = mdio_read(tp, 0x16);
-+ data &= ~(BIT_1);
-+ mdio_write(tp, 0x16, data);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ case CFG_METHOD_26:
-+ data = mac_ocp_read(tp, 0xE052);
-+ data &= ~(BIT_0);
-+ mac_ocp_write(tp, 0xE052, data);
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A42);
-+ data = mdio_read(tp, 0x16);
-+ data &= ~(BIT_1);
-+ mdio_write(tp, 0x16, data);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ data = mac_ocp_read(tp, 0xE052);
-+ data &= ~(BIT_0);
-+ mac_ocp_write(tp, 0xE052, data);
-+ break;
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ data = mac_ocp_read(tp, 0xE052);
-+ data &= ~(BIT_0);
-+ mac_ocp_write(tp, 0xE052, data);
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ data = mdio_read(tp, 0x10) & ~(BIT_15);
-+ mdio_write(tp, 0x10, data);
-+
-+ mdio_write(tp, 0x1F, 0x0A44);
-+ data = mdio_read( tp, 0x11 ) & ~(BIT_12 | BIT_13 | BIT_14);
-+ mdio_write(tp, 0x11, data);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0B82);
-+ ClearEthPhyBit(tp, 0x10, BIT_4);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ }
-+
-+ return ret;
-+}
-+
-+#if 0
-+
-+static int rtl8168_enable_green_feature(struct rtl8168_private *tp)
-+{
-+ u16 gphy_val;
-+ unsigned long flags;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0003);
-+ gphy_val = mdio_read(tp, 0x10) | 0x0400;
-+ mdio_write(tp, 0x10, gphy_val);
-+ gphy_val = mdio_read(tp, 0x19) | 0x0001;
-+ mdio_write(tp, 0x19, gphy_val);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ gphy_val = mdio_read(tp, 0x01) & ~0x0100;
-+ mdio_write(tp, 0x01, gphy_val);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ mdio_write(tp, 0x00, 0x9200);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ mdelay(20);
-+ break;
-+
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1f, 0x0003);
-+ gphy_val = mdio_read(tp, 0x10);
-+ gphy_val |= BIT_10;
-+ mdio_write(tp, 0x10, gphy_val);
-+ gphy_val = mdio_read(tp, 0x19);
-+ gphy_val |= BIT_0;
-+ mdio_write(tp, 0x19, gphy_val);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ gphy_val = mdio_read(tp, 0x01);
-+ gphy_val |= BIT_8;
-+ mdio_write(tp, 0x01, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x00, 0x9200);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ mdio_write(tp, 0x13, 0x8011);
-+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ SetEthPhyBit( tp, 0x14, BIT_15 );
-+ } else {
-+ SetEthPhyBit( tp, 0x14, BIT_14 );
-+ }
-+ mdio_write(tp, 0x1F, 0x0A40);
-+ mdio_write(tp, 0x00, 0x9200);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ default:
-+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support Green Feature\n");
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static int rtl8168_disable_green_feature(struct rtl8168_private *tp)
-+{
-+ u16 gphy_val;
-+ unsigned long flags;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0005);
-+ gphy_val = mdio_read(tp, 0x01) | 0x0100;
-+ mdio_write(tp, 0x01, gphy_val);
-+ mdio_write(tp, 0x1F, 0x0003);
-+ gphy_val = mdio_read(tp, 0x10) & ~0x0400;
-+ mdio_write(tp, 0x10, gphy_val);
-+ gphy_val = mdio_read(tp, 0x19) & ~0x0001;
-+ mdio_write(tp, 0x19, gphy_val);
-+ mdio_write(tp, 0x1F, 0x0002);
-+ gphy_val = mdio_read(tp, 0x06) & ~0x7000;
-+ gphy_val |= 0x3000;
-+ mdio_write(tp, 0x06, gphy_val);
-+ gphy_val = mdio_read(tp, 0x0D) & 0x0700;
-+ gphy_val |= 0x0500;
-+ mdio_write(tp, 0x0D, gphy_val);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1f, 0x0003);
-+ gphy_val = mdio_read(tp, 0x19);
-+ gphy_val &= ~BIT_0;
-+ mdio_write(tp, 0x19, gphy_val);
-+ gphy_val = mdio_read(tp, 0x10);
-+ gphy_val &= ~BIT_10;
-+ mdio_write(tp, 0x10, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ mdio_write(tp, 0x13, 0x8011);
-+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ ClearEthPhyBit( tp, 0x14, BIT_15 );
-+ } else {
-+ ClearEthPhyBit( tp, 0x14, BIT_14 );
-+ }
-+ mdio_write(tp, 0x1F, 0x0A40);
-+ mdio_write(tp, 0x00, 0x9200);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ break;
-+
-+ default:
-+ dev_printk(KERN_DEBUG, &tp->pci_dev->dev, "Not Support Green Feature\n");
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+#endif
-+
-+static void rtl8168_get_mac_version(struct rtl8168_private *tp, void __iomem *ioaddr)
-+{
-+ u32 reg,val32;
-+ u32 ICVerID;
-+
-+ val32 = RTL_R32(TxConfig) ;
-+ reg = val32 & 0x7c800000;
-+ ICVerID = val32 & 0x00700000;
-+
-+ switch (reg) {
-+ case 0x30000000:
-+ tp->mcfg = CFG_METHOD_1;
-+ tp->efuse_ver = EFUSE_NOT_SUPPORT;
-+ break;
-+ case 0x38000000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_2;
-+ } else if (ICVerID == 0x00500000) {
-+ tp->mcfg = CFG_METHOD_3;
-+ } else {
-+ tp->mcfg = CFG_METHOD_3;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_NOT_SUPPORT;
-+ break;
-+ case 0x3C000000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_4;
-+ } else if (ICVerID == 0x00200000) {
-+ tp->mcfg = CFG_METHOD_5;
-+ } else if (ICVerID == 0x00400000) {
-+ tp->mcfg = CFG_METHOD_6;
-+ } else {
-+ tp->mcfg = CFG_METHOD_6;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_NOT_SUPPORT;
-+ break;
-+ case 0x3C800000:
-+ if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_7;
-+ } else if (ICVerID == 0x00300000) {
-+ tp->mcfg = CFG_METHOD_8;
-+ } else {
-+ tp->mcfg = CFG_METHOD_8;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_NOT_SUPPORT;
-+ break;
-+ case 0x28000000:
-+ if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_9;
-+ } else if (ICVerID == 0x00300000) {
-+ tp->mcfg = CFG_METHOD_10;
-+ } else {
-+ tp->mcfg = CFG_METHOD_10;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V1;
-+ break;
-+ case 0x28800000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_11;
-+ } else if (ICVerID == 0x00200000) {
-+ tp->mcfg = CFG_METHOD_12;
-+ RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000);
-+ } else if (ICVerID == 0x00300000) {
-+ tp->mcfg = CFG_METHOD_13;
-+ } else {
-+ tp->mcfg = CFG_METHOD_13;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V1;
-+ break;
-+ case 0x2C000000:
-+ if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_14;
-+ } else if (ICVerID == 0x00200000) {
-+ tp->mcfg = CFG_METHOD_15;
-+ } else {
-+ tp->mcfg = CFG_METHOD_15;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V2;
-+ break;
-+ case 0x2C800000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_16;
-+ } else if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_17;
-+ } else {
-+ tp->mcfg = CFG_METHOD_17;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ case 0x48000000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_18;
-+ } else if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_19;
-+ } else {
-+ tp->mcfg = CFG_METHOD_19;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ case 0x48800000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_20;
-+ } else {
-+ tp->mcfg = CFG_METHOD_20;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ case 0x4C000000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_21;
-+ } else if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_22;
-+ } else {
-+ tp->mcfg = CFG_METHOD_22;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ case 0x50000000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_23;
-+ } else if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_27;
-+ } else if (ICVerID == 0x00200000) {
-+ tp->mcfg = CFG_METHOD_28;
-+ } else {
-+ tp->mcfg = CFG_METHOD_28;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ case 0x50800000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_24;
-+ } else if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_25;
-+ } else {
-+ tp->mcfg = CFG_METHOD_25;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ case 0x5C800000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_26;
-+ } else {
-+ tp->mcfg = CFG_METHOD_26;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ case 0x54000000:
-+ if (ICVerID == 0x00000000) {
-+ tp->mcfg = CFG_METHOD_29;
-+ } else if (ICVerID == 0x00100000) {
-+ tp->mcfg = CFG_METHOD_30;
-+ } else {
-+ tp->mcfg = CFG_METHOD_30;
-+ tp->HwIcVerUnknown = TRUE;
-+ }
-+
-+ tp->efuse_ver = EFUSE_SUPPORT_V3;
-+ break;
-+ default:
-+ printk("unknown chip version (%x)\n",reg);
-+ tp->mcfg = CFG_METHOD_DEFAULT;
-+ tp->HwIcVerUnknown = TRUE;
-+ tp->efuse_ver = EFUSE_NOT_SUPPORT;
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_print_mac_version(struct rtl8168_private *tp)
-+{
-+ int i;
-+ for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
-+ if (tp->mcfg == rtl_chip_info[i].mcfg) {
-+ dprintk("Realtek PCIe GBE Family Controller mcfg = %04d\n",
-+ rtl_chip_info[i].mcfg);
-+ return;
-+ }
-+ }
-+
-+ dprintk("mac_version == Unknown\n");
-+}
-+
-+static u8 rtl8168_calc_efuse_dummy_bit(u16 reg)
-+{
-+ int s,a,b;
-+ u8 dummyBitPos = 0;
-+
-+
-+ s=reg% 32;
-+ a=s % 16;
-+ b=s/16;
-+
-+ if (s/16) {
-+ dummyBitPos = (u8)(16-a);
-+ } else {
-+ dummyBitPos = (u8)a;
-+ }
-+
-+ return dummyBitPos;
-+}
-+
-+static u32 rtl8168_decode_efuse_cmd(struct rtl8168_private *tp, u32 DwCmd)
-+{
-+ u16 reg = (u16)((DwCmd & 0x00FE0000) >> 17);
-+ u32 DummyPos = rtl8168_calc_efuse_dummy_bit(reg);
-+ u32 DeCodeDwCmd = DwCmd;
-+ u32 Dw17BitData;
-+
-+
-+ if(tp->efuse_ver < 3) {
-+ DeCodeDwCmd = (DwCmd>>(DummyPos+1))<<DummyPos;
-+ if(DummyPos > 0) {
-+ DeCodeDwCmd |= ((DwCmd<<(32-DummyPos))>>(32-DummyPos));
-+ }
-+ } else {
-+ reg = (u16)((DwCmd & 0x007F0000) >> 16);
-+ DummyPos = rtl8168_calc_efuse_dummy_bit(reg);
-+ Dw17BitData = ((DwCmd & BIT_23) >> 23);
-+ Dw17BitData <<= 16;
-+ Dw17BitData |= (DwCmd & 0x0000FFFF);
-+ DeCodeDwCmd = (Dw17BitData>>(DummyPos+1))<<DummyPos;
-+ if(DummyPos > 0) {
-+ DeCodeDwCmd |= ((Dw17BitData<<(32-DummyPos))>>(32-DummyPos));
-+ }
-+ }
-+
-+ return DeCodeDwCmd;
-+}
-+
-+static u8 rtl8168_efuse_read(struct rtl8168_private *tp, u16 reg)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u8 efuse_data = 0;
-+ u32 temp;
-+ int cnt;
-+
-+ if (tp->efuse_ver == EFUSE_NOT_SUPPORT)
-+ return EFUSE_READ_FAIL;
-+
-+ if (tp->efuse_ver == EFUSE_SUPPORT_V1) {
-+ temp = EFUSE_READ | ((reg & EFUSE_Reg_Mask) << EFUSE_Reg_Shift);
-+ RTL_W32(EFUSEAR, temp);
-+
-+ cnt = 0;
-+ do {
-+ udelay(100);
-+ temp = RTL_R32(EFUSEAR);
-+ cnt++;
-+ } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt));
-+
-+ if (cnt == EFUSE_Check_Cnt)
-+ efuse_data = EFUSE_READ_FAIL;
-+ else
-+ efuse_data = (u8)(RTL_R32(EFUSEAR) & EFUSE_Data_Mask);
-+ } else if (tp->efuse_ver == EFUSE_SUPPORT_V2) {
-+ temp = (reg/2) & 0x03ff;
-+ temp <<= 17;
-+ temp |= EFUSE_READ;
-+ RTL_W32(EFUSEAR, temp);
-+
-+ cnt = 0;
-+ do {
-+ udelay(100);
-+ temp = RTL_R32(EFUSEAR);
-+ cnt++;
-+ } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt));
-+
-+ if (cnt == EFUSE_Check_Cnt) {
-+ efuse_data = EFUSE_READ_FAIL;
-+ } else {
-+ temp = RTL_R32(EFUSEAR);
-+ temp = rtl8168_decode_efuse_cmd(tp, temp);
-+
-+ if(reg%2) {
-+ temp >>= 8;
-+ efuse_data = (u8)temp;
-+ } else {
-+ efuse_data = (u8)temp;
-+ }
-+ }
-+
-+ } else if (tp->efuse_ver == EFUSE_SUPPORT_V3) {
-+ temp = (reg/2) & 0x03ff;
-+ temp <<= 16;
-+ temp |= EFUSE_READ;
-+ RTL_W32(EFUSEAR, temp);
-+
-+ cnt = 0;
-+ do {
-+ udelay(100);
-+ temp = RTL_R32(EFUSEAR);
-+ cnt++;
-+ } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt));
-+
-+ if (cnt == EFUSE_Check_Cnt) {
-+ efuse_data = EFUSE_READ_FAIL;
-+ } else {
-+ temp = RTL_R32(EFUSEAR);
-+ temp = rtl8168_decode_efuse_cmd(tp, temp);
-+
-+ if(reg%2) {
-+ temp >>= 8;
-+ efuse_data = (u8)temp;
-+ } else {
-+ efuse_data = (u8)temp;
-+ }
-+ }
-+ }
-+
-+ udelay(20);
-+
-+ return efuse_data;
-+}
-+
-+static void
-+rtl8168_tally_counter_addr_fill(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (!tp->tally_paddr)
-+ return;
-+
-+ RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32);
-+ RTL_W32(CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32)));
-+}
-+
-+static void
-+rtl8168_tally_counter_clear(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if (tp->mcfg == CFG_METHOD_1 || tp->mcfg == CFG_METHOD_2 ||
-+ tp->mcfg == CFG_METHOD_3 )
-+ return;
-+
-+ if (!tp->tally_paddr)
-+ return;
-+
-+ RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32);
-+ RTL_W32(CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32) | BIT_0));
-+}
-+
-+static int
-+rtl8168_is_ups_resume(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ return (mac_ocp_read(tp, 0xD408) & BIT_0);
-+}
-+
-+static void
-+rtl8168_clear_ups_resume_bit(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ mac_ocp_write(tp, 0xD408, mac_ocp_read(tp, 0xD408) & ~(BIT_0));
-+}
-+
-+static void
-+rtl8168_wait_phy_ups_resume(struct net_device *dev, u16 PhyState)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ u16 TmpPhyState;
-+ int i=0;
-+
-+ do {
-+ TmpPhyState = mdio_read_phy_ocp(tp, 0x0A42, 0x10);
-+ TmpPhyState &= 0x7;
-+ mdelay(1);
-+ i++;
-+ } while ((i < 100) && (TmpPhyState != PhyState));
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
-+ WARN_ON_ONCE(i == 100);
-+#endif
-+}
-+
-+void
-+EnableNowIsOob(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if( tp->HwSuppNowIsOobVer == 1 ) {
-+ RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) | Now_is_oob);
-+ }
-+}
-+
-+void
-+DisableNowIsOob(struct rtl8168_private *tp)
-+{
-+ void __iomem *ioaddr = tp->mmio_addr;
-+
-+ if( tp->HwSuppNowIsOobVer == 1 ) {
-+ RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) & ~Now_is_oob);
-+ }
-+}
-+
-+static void
-+rtl8168_exit_oob(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u16 data16;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ Dash2DisableTxRx(dev);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_11:
-+ case CFG_METHOD_12:
-+ case CFG_METHOD_13:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ if (tp->DASH) {
-+ rtl8168_driver_stop(tp);
-+ rtl8168_driver_start(tp);
-+#ifdef ENABLE_DASH_SUPPORT
-+ DashHwInit(dev);
-+#endif
-+ }
-+ break;
-+ }
-+
-+ //Disable realwow function
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ RTL_W32(MACOCP, 0xE5A90000);
-+ RTL_W32(MACOCP, 0xF2100010);
-+ break;
-+ case CFG_METHOD_20:
-+ RTL_W32(MACOCP, 0xE5A90000);
-+ RTL_W32(MACOCP, 0xE4640000);
-+ RTL_W32(MACOCP, 0xF2100010);
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ RTL_W32(MACOCP, 0x605E0000);
-+ RTL_W32(MACOCP, (0xE05E << 16) | (RTL_R32(MACOCP) & 0xFFFE));
-+ RTL_W32(MACOCP, 0xE9720000);
-+ RTL_W32(MACOCP, 0xF2140010);
-+ break;
-+ case CFG_METHOD_26:
-+ RTL_W32(MACOCP, 0xE05E00FF);
-+ RTL_W32(MACOCP, 0xE9720000);
-+ mac_ocp_write(tp, 0xE428, 0x0010);
-+ break;
-+ }
-+
-+#ifndef ENABLE_REALWOW_SUPPORT
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ rtl8168_eri_write(ioaddr, 0x174, 2, 0x0000, ERIAR_ExGMAC);
-+ mac_ocp_write(tp, 0xE428, 0x0010);
-+ break;
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_28:
-+ rtl8168_eri_write(ioaddr, 0x174, 2, 0x00FF, ERIAR_ExGMAC);
-+ mac_ocp_write(tp, 0xE428, 0x0010);
-+ break;
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30: {
-+ u32 csi_tmp;
-+ csi_tmp = rtl8168_eri_read(ioaddr, 0x174, 2, ERIAR_ExGMAC);
-+ csi_tmp &= ~(BIT_8);
-+ csi_tmp |= (BIT_15);
-+ rtl8168_eri_write(ioaddr, 0x174, 2, csi_tmp, ERIAR_ExGMAC);
-+ mac_ocp_write(tp, 0xE428, 0x0010);
-+ }
-+ break;
-+ }
-+#endif //ENABLE_REALWOW_SUPPORT
-+
-+#ifdef ENABLE_REALWOW_SUPPORT
-+ realwow_hw_init(dev);
-+#endif
-+
-+ rtl8168_nic_reset(dev);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_20:
-+ rtl8168_wait_ll_share_fifo_ready(dev);
-+
-+ data16 = mac_ocp_read(tp, 0xD4DE) | BIT_15;
-+ mac_ocp_write(tp, 0xD4DE, data16);
-+
-+ rtl8168_wait_ll_share_fifo_ready(dev);
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ DisableNowIsOob(tp);
-+
-+ data16 = mac_ocp_read(tp, 0xE8DE) & ~BIT_14;
-+ mac_ocp_write(tp, 0xE8DE, data16);
-+ rtl8168_wait_ll_share_fifo_ready(dev);
-+
-+ data16 = mac_ocp_read(tp, 0xE8DE) | BIT_15;
-+ mac_ocp_write(tp, 0xE8DE, data16);
-+
-+ rtl8168_wait_ll_share_fifo_ready(dev);
-+ break;
-+ }
-+
-+ //wait ups resume (phy state 2)
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ if (rtl8168_is_ups_resume(dev)) {
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+
-+ rtl8168_wait_phy_ups_resume(dev, 2);
-+
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+
-+ rtl8168_clear_ups_resume_bit(dev);
-+ }
-+ break;
-+ };
-+}
-+
-+void
-+rtl8168_hw_disable_mac_mcu_bps(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ mac_ocp_write(tp, 0xFC28, 0x0000);
-+ mac_ocp_write(tp, 0xFC2A, 0x0000);
-+ mac_ocp_write(tp, 0xFC2C, 0x0000);
-+ mac_ocp_write(tp, 0xFC2E, 0x0000);
-+ mac_ocp_write(tp, 0xFC30, 0x0000);
-+ mac_ocp_write(tp, 0xFC32, 0x0000);
-+ mac_ocp_write(tp, 0xFC34, 0x0000);
-+ mac_ocp_write(tp, 0xFC36, 0x0000);
-+ mdelay(3);
-+ mac_ocp_write(tp, 0xFC26, 0x0000);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_hw_mac_mcu_config(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ if (tp->NotWrMcuPatchCode == TRUE) return;
-+
-+ if (tp->mcfg == CFG_METHOD_21) {
-+ mac_ocp_write(tp, 0xE43C, 0x0000);
-+ mac_ocp_write(tp, 0xE43E, 0x0000);
-+
-+ mac_ocp_write(tp, 0xE434, 0x0004);
-+ mac_ocp_write(tp, 0xE43C, 0x0004);
-+
-+ rtl8168_hw_disable_mac_mcu_bps(dev);
-+
-+ mac_ocp_write( tp, 0xF800, 0xE008 );
-+ mac_ocp_write( tp, 0xF802, 0xE01B );
-+ mac_ocp_write( tp, 0xF804, 0xE01D );
-+ mac_ocp_write( tp, 0xF806, 0xE01F );
-+ mac_ocp_write( tp, 0xF808, 0xE022 );
-+ mac_ocp_write( tp, 0xF80A, 0xE025 );
-+ mac_ocp_write( tp, 0xF80C, 0xE031 );
-+ mac_ocp_write( tp, 0xF80E, 0xE04D );
-+ mac_ocp_write( tp, 0xF810, 0x49D2 );
-+ mac_ocp_write( tp, 0xF812, 0xF10D );
-+ mac_ocp_write( tp, 0xF814, 0x766C );
-+ mac_ocp_write( tp, 0xF816, 0x49E2 );
-+ mac_ocp_write( tp, 0xF818, 0xF00A );
-+ mac_ocp_write( tp, 0xF81A, 0x1EC0 );
-+ mac_ocp_write( tp, 0xF81C, 0x8EE1 );
-+ mac_ocp_write( tp, 0xF81E, 0xC60A );
-+ mac_ocp_write( tp, 0xF820, 0x77C0 );
-+ mac_ocp_write( tp, 0xF822, 0x4870 );
-+ mac_ocp_write( tp, 0xF824, 0x9FC0 );
-+ mac_ocp_write( tp, 0xF826, 0x1EA0 );
-+ mac_ocp_write( tp, 0xF828, 0xC707 );
-+ mac_ocp_write( tp, 0xF82A, 0x8EE1 );
-+ mac_ocp_write( tp, 0xF82C, 0x9D6C );
-+ mac_ocp_write( tp, 0xF82E, 0xC603 );
-+ mac_ocp_write( tp, 0xF830, 0xBE00 );
-+ mac_ocp_write( tp, 0xF832, 0xB416 );
-+ mac_ocp_write( tp, 0xF834, 0x0076 );
-+ mac_ocp_write( tp, 0xF836, 0xE86C );
-+ mac_ocp_write( tp, 0xF838, 0xC602 );
-+ mac_ocp_write( tp, 0xF83A, 0xBE00 );
-+ mac_ocp_write( tp, 0xF83C, 0xA000 );
-+ mac_ocp_write( tp, 0xF83E, 0xC602 );
-+ mac_ocp_write( tp, 0xF840, 0xBE00 );
-+ mac_ocp_write( tp, 0xF842, 0x0000 );
-+ mac_ocp_write( tp, 0xF844, 0x1B76 );
-+ mac_ocp_write( tp, 0xF846, 0xC202 );
-+ mac_ocp_write( tp, 0xF848, 0xBA00 );
-+ mac_ocp_write( tp, 0xF84A, 0x059C );
-+ mac_ocp_write( tp, 0xF84C, 0x1B76 );
-+ mac_ocp_write( tp, 0xF84E, 0xC602 );
-+ mac_ocp_write( tp, 0xF850, 0xBE00 );
-+ mac_ocp_write( tp, 0xF852, 0x065A );
-+ mac_ocp_write( tp, 0xF854, 0x74E6 );
-+ mac_ocp_write( tp, 0xF856, 0x1B78 );
-+ mac_ocp_write( tp, 0xF858, 0x46DC );
-+ mac_ocp_write( tp, 0xF85A, 0x1300 );
-+ mac_ocp_write( tp, 0xF85C, 0xF005 );
-+ mac_ocp_write( tp, 0xF85E, 0x74F8 );
-+ mac_ocp_write( tp, 0xF860, 0x48C3 );
-+ mac_ocp_write( tp, 0xF862, 0x48C4 );
-+ mac_ocp_write( tp, 0xF864, 0x8CF8 );
-+ mac_ocp_write( tp, 0xF866, 0x64E7 );
-+ mac_ocp_write( tp, 0xF868, 0xC302 );
-+ mac_ocp_write( tp, 0xF86A, 0xBB00 );
-+ mac_ocp_write( tp, 0xF86C, 0x06A0 );
-+ mac_ocp_write( tp, 0xF86E, 0x74E4 );
-+ mac_ocp_write( tp, 0xF870, 0x49C5 );
-+ mac_ocp_write( tp, 0xF872, 0xF106 );
-+ mac_ocp_write( tp, 0xF874, 0x49C6 );
-+ mac_ocp_write( tp, 0xF876, 0xF107 );
-+ mac_ocp_write( tp, 0xF878, 0x48C8 );
-+ mac_ocp_write( tp, 0xF87A, 0x48C9 );
-+ mac_ocp_write( tp, 0xF87C, 0xE011 );
-+ mac_ocp_write( tp, 0xF87E, 0x48C9 );
-+ mac_ocp_write( tp, 0xF880, 0x4848 );
-+ mac_ocp_write( tp, 0xF882, 0xE00E );
-+ mac_ocp_write( tp, 0xF884, 0x4848 );
-+ mac_ocp_write( tp, 0xF886, 0x49C7 );
-+ mac_ocp_write( tp, 0xF888, 0xF00A );
-+ mac_ocp_write( tp, 0xF88A, 0x48C9 );
-+ mac_ocp_write( tp, 0xF88C, 0xC60D );
-+ mac_ocp_write( tp, 0xF88E, 0x1D1F );
-+ mac_ocp_write( tp, 0xF890, 0x8DC2 );
-+ mac_ocp_write( tp, 0xF892, 0x1D00 );
-+ mac_ocp_write( tp, 0xF894, 0x8DC3 );
-+ mac_ocp_write( tp, 0xF896, 0x1D11 );
-+ mac_ocp_write( tp, 0xF898, 0x8DC0 );
-+ mac_ocp_write( tp, 0xF89A, 0xE002 );
-+ mac_ocp_write( tp, 0xF89C, 0x4849 );
-+ mac_ocp_write( tp, 0xF89E, 0x94E5 );
-+ mac_ocp_write( tp, 0xF8A0, 0xC602 );
-+ mac_ocp_write( tp, 0xF8A2, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8A4, 0x01F0 );
-+ mac_ocp_write( tp, 0xF8A6, 0xE434 );
-+ mac_ocp_write( tp, 0xF8A8, 0x49D9 );
-+ mac_ocp_write( tp, 0xF8AA, 0xF01B );
-+ mac_ocp_write( tp, 0xF8AC, 0xC31E );
-+ mac_ocp_write( tp, 0xF8AE, 0x7464 );
-+ mac_ocp_write( tp, 0xF8B0, 0x49C4 );
-+ mac_ocp_write( tp, 0xF8B2, 0xF114 );
-+ mac_ocp_write( tp, 0xF8B4, 0xC31B );
-+ mac_ocp_write( tp, 0xF8B6, 0x6460 );
-+ mac_ocp_write( tp, 0xF8B8, 0x14FA );
-+ mac_ocp_write( tp, 0xF8BA, 0xFA02 );
-+ mac_ocp_write( tp, 0xF8BC, 0xE00F );
-+ mac_ocp_write( tp, 0xF8BE, 0xC317 );
-+ mac_ocp_write( tp, 0xF8C0, 0x7460 );
-+ mac_ocp_write( tp, 0xF8C2, 0x49C0 );
-+ mac_ocp_write( tp, 0xF8C4, 0xF10B );
-+ mac_ocp_write( tp, 0xF8C6, 0xC311 );
-+ mac_ocp_write( tp, 0xF8C8, 0x7462 );
-+ mac_ocp_write( tp, 0xF8CA, 0x48C1 );
-+ mac_ocp_write( tp, 0xF8CC, 0x9C62 );
-+ mac_ocp_write( tp, 0xF8CE, 0x4841 );
-+ mac_ocp_write( tp, 0xF8D0, 0x9C62 );
-+ mac_ocp_write( tp, 0xF8D2, 0xC30A );
-+ mac_ocp_write( tp, 0xF8D4, 0x1C04 );
-+ mac_ocp_write( tp, 0xF8D6, 0x8C60 );
-+ mac_ocp_write( tp, 0xF8D8, 0xE004 );
-+ mac_ocp_write( tp, 0xF8DA, 0x1C15 );
-+ mac_ocp_write( tp, 0xF8DC, 0xC305 );
-+ mac_ocp_write( tp, 0xF8DE, 0x8C60 );
-+ mac_ocp_write( tp, 0xF8E0, 0xC602 );
-+ mac_ocp_write( tp, 0xF8E2, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8E4, 0x0384 );
-+ mac_ocp_write( tp, 0xF8E6, 0xE434 );
-+ mac_ocp_write( tp, 0xF8E8, 0xE030 );
-+ mac_ocp_write( tp, 0xF8EA, 0xE61C );
-+ mac_ocp_write( tp, 0xF8EC, 0xE906 );
-+
-+ mac_ocp_write( tp, 0xFC26, 0x8000 );
-+
-+ mac_ocp_write( tp, 0xFC28, 0x0075 );
-+ mac_ocp_write( tp, 0xFC2E, 0x059B );
-+ mac_ocp_write( tp, 0xFC30, 0x0659 );
-+ mac_ocp_write( tp, 0xFC32, 0x0000 );
-+ mac_ocp_write( tp, 0xFC34, 0x0000 );
-+ mac_ocp_write( tp, 0xFC36, 0x0000 );
-+ } else if (tp->mcfg == CFG_METHOD_24) {
-+ rtl8168_hw_disable_mac_mcu_bps(dev);
-+
-+ mac_ocp_write( tp, 0xF800, 0xE008 );
-+ mac_ocp_write( tp, 0xF802, 0xE011 );
-+ mac_ocp_write( tp, 0xF804, 0xE015 );
-+ mac_ocp_write( tp, 0xF806, 0xE018 );
-+ mac_ocp_write( tp, 0xF808, 0xE01B );
-+ mac_ocp_write( tp, 0xF80A, 0xE027 );
-+ mac_ocp_write( tp, 0xF80C, 0xE043 );
-+ mac_ocp_write( tp, 0xF80E, 0xE065 );
-+ mac_ocp_write( tp, 0xF810, 0x49E2 );
-+ mac_ocp_write( tp, 0xF812, 0xF005 );
-+ mac_ocp_write( tp, 0xF814, 0x49EA );
-+ mac_ocp_write( tp, 0xF816, 0xF003 );
-+ mac_ocp_write( tp, 0xF818, 0xC404 );
-+ mac_ocp_write( tp, 0xF81A, 0xBC00 );
-+ mac_ocp_write( tp, 0xF81C, 0xC403 );
-+ mac_ocp_write( tp, 0xF81E, 0xBC00 );
-+ mac_ocp_write( tp, 0xF820, 0x0496 );
-+ mac_ocp_write( tp, 0xF822, 0x051A );
-+ mac_ocp_write( tp, 0xF824, 0x1D01 );
-+ mac_ocp_write( tp, 0xF826, 0x8DE8 );
-+ mac_ocp_write( tp, 0xF828, 0xC602 );
-+ mac_ocp_write( tp, 0xF82A, 0xBE00 );
-+ mac_ocp_write( tp, 0xF82C, 0x0206 );
-+ mac_ocp_write( tp, 0xF82E, 0x1B76 );
-+ mac_ocp_write( tp, 0xF830, 0xC202 );
-+ mac_ocp_write( tp, 0xF832, 0xBA00 );
-+ mac_ocp_write( tp, 0xF834, 0x058A );
-+ mac_ocp_write( tp, 0xF836, 0x1B76 );
-+ mac_ocp_write( tp, 0xF838, 0xC602 );
-+ mac_ocp_write( tp, 0xF83A, 0xBE00 );
-+ mac_ocp_write( tp, 0xF83C, 0x0648 );
-+ mac_ocp_write( tp, 0xF83E, 0x74E6 );
-+ mac_ocp_write( tp, 0xF840, 0x1B78 );
-+ mac_ocp_write( tp, 0xF842, 0x46DC );
-+ mac_ocp_write( tp, 0xF844, 0x1300 );
-+ mac_ocp_write( tp, 0xF846, 0xF005 );
-+ mac_ocp_write( tp, 0xF848, 0x74F8 );
-+ mac_ocp_write( tp, 0xF84A, 0x48C3 );
-+ mac_ocp_write( tp, 0xF84C, 0x48C4 );
-+ mac_ocp_write( tp, 0xF84E, 0x8CF8 );
-+ mac_ocp_write( tp, 0xF850, 0x64E7 );
-+ mac_ocp_write( tp, 0xF852, 0xC302 );
-+ mac_ocp_write( tp, 0xF854, 0xBB00 );
-+ mac_ocp_write( tp, 0xF856, 0x068E );
-+ mac_ocp_write( tp, 0xF858, 0x74E4 );
-+ mac_ocp_write( tp, 0xF85A, 0x49C5 );
-+ mac_ocp_write( tp, 0xF85C, 0xF106 );
-+ mac_ocp_write( tp, 0xF85E, 0x49C6 );
-+ mac_ocp_write( tp, 0xF860, 0xF107 );
-+ mac_ocp_write( tp, 0xF862, 0x48C8 );
-+ mac_ocp_write( tp, 0xF864, 0x48C9 );
-+ mac_ocp_write( tp, 0xF866, 0xE011 );
-+ mac_ocp_write( tp, 0xF868, 0x48C9 );
-+ mac_ocp_write( tp, 0xF86A, 0x4848 );
-+ mac_ocp_write( tp, 0xF86C, 0xE00E );
-+ mac_ocp_write( tp, 0xF86E, 0x4848 );
-+ mac_ocp_write( tp, 0xF870, 0x49C7 );
-+ mac_ocp_write( tp, 0xF872, 0xF00A );
-+ mac_ocp_write( tp, 0xF874, 0x48C9 );
-+ mac_ocp_write( tp, 0xF876, 0xC60D );
-+ mac_ocp_write( tp, 0xF878, 0x1D1F );
-+ mac_ocp_write( tp, 0xF87A, 0x8DC2 );
-+ mac_ocp_write( tp, 0xF87C, 0x1D00 );
-+ mac_ocp_write( tp, 0xF87E, 0x8DC3 );
-+ mac_ocp_write( tp, 0xF880, 0x1D11 );
-+ mac_ocp_write( tp, 0xF882, 0x8DC0 );
-+ mac_ocp_write( tp, 0xF884, 0xE002 );
-+ mac_ocp_write( tp, 0xF886, 0x4849 );
-+ mac_ocp_write( tp, 0xF888, 0x94E5 );
-+ mac_ocp_write( tp, 0xF88A, 0xC602 );
-+ mac_ocp_write( tp, 0xF88C, 0xBE00 );
-+ mac_ocp_write( tp, 0xF88E, 0x0238 );
-+ mac_ocp_write( tp, 0xF890, 0xE434 );
-+ mac_ocp_write( tp, 0xF892, 0x49D9 );
-+ mac_ocp_write( tp, 0xF894, 0xF01B );
-+ mac_ocp_write( tp, 0xF896, 0xC31E );
-+ mac_ocp_write( tp, 0xF898, 0x7464 );
-+ mac_ocp_write( tp, 0xF89A, 0x49C4 );
-+ mac_ocp_write( tp, 0xF89C, 0xF114 );
-+ mac_ocp_write( tp, 0xF89E, 0xC31B );
-+ mac_ocp_write( tp, 0xF8A0, 0x6460 );
-+ mac_ocp_write( tp, 0xF8A2, 0x14FA );
-+ mac_ocp_write( tp, 0xF8A4, 0xFA02 );
-+ mac_ocp_write( tp, 0xF8A6, 0xE00F );
-+ mac_ocp_write( tp, 0xF8A8, 0xC317 );
-+ mac_ocp_write( tp, 0xF8AA, 0x7460 );
-+ mac_ocp_write( tp, 0xF8AC, 0x49C0 );
-+ mac_ocp_write( tp, 0xF8AE, 0xF10B );
-+ mac_ocp_write( tp, 0xF8B0, 0xC311 );
-+ mac_ocp_write( tp, 0xF8B2, 0x7462 );
-+ mac_ocp_write( tp, 0xF8B4, 0x48C1 );
-+ mac_ocp_write( tp, 0xF8B6, 0x9C62 );
-+ mac_ocp_write( tp, 0xF8B8, 0x4841 );
-+ mac_ocp_write( tp, 0xF8BA, 0x9C62 );
-+ mac_ocp_write( tp, 0xF8BC, 0xC30A );
-+ mac_ocp_write( tp, 0xF8BE, 0x1C04 );
-+ mac_ocp_write( tp, 0xF8C0, 0x8C60 );
-+ mac_ocp_write( tp, 0xF8C2, 0xE004 );
-+ mac_ocp_write( tp, 0xF8C4, 0x1C15 );
-+ mac_ocp_write( tp, 0xF8C6, 0xC305 );
-+ mac_ocp_write( tp, 0xF8C8, 0x8C60 );
-+ mac_ocp_write( tp, 0xF8CA, 0xC602 );
-+ mac_ocp_write( tp, 0xF8CC, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8CE, 0x0374 );
-+ mac_ocp_write( tp, 0xF8D0, 0xE434 );
-+ mac_ocp_write( tp, 0xF8D2, 0xE030 );
-+ mac_ocp_write( tp, 0xF8D4, 0xE61C );
-+ mac_ocp_write( tp, 0xF8D6, 0xE906 );
-+ mac_ocp_write( tp, 0xF8D8, 0xC602 );
-+ mac_ocp_write( tp, 0xF8DA, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8DC, 0x0000 );
-+
-+ mac_ocp_write( tp, 0xFC26, 0x8000 );
-+
-+ mac_ocp_write( tp, 0xFC28, 0x0493 );
-+ mac_ocp_write( tp, 0xFC2A, 0x0205 );
-+ mac_ocp_write( tp, 0xFC2C, 0x0589 );
-+ mac_ocp_write( tp, 0xFC2E, 0x0647 );
-+ mac_ocp_write( tp, 0xFC30, 0x0000 );
-+ mac_ocp_write( tp, 0xFC32, 0x0215 );
-+ mac_ocp_write( tp, 0xFC34, 0x0285 );
-+ } else if (tp->mcfg == CFG_METHOD_25) {
-+ rtl8168_hw_disable_mac_mcu_bps(dev);
-+
-+ mac_ocp_write( tp, 0xF800, 0xE008 );
-+ mac_ocp_write( tp, 0xF802, 0xE00A );
-+ mac_ocp_write( tp, 0xF804, 0xE01D );
-+ mac_ocp_write( tp, 0xF806, 0xE033 );
-+ mac_ocp_write( tp, 0xF808, 0xE042 );
-+ mac_ocp_write( tp, 0xF80A, 0xE044 );
-+ mac_ocp_write( tp, 0xF80C, 0xE046 );
-+ mac_ocp_write( tp, 0xF80E, 0xE048 );
-+ mac_ocp_write( tp, 0xF810, 0xC602 );
-+ mac_ocp_write( tp, 0xF812, 0xBE00 );
-+ mac_ocp_write( tp, 0xF814, 0x0000 );
-+ mac_ocp_write( tp, 0xF816, 0xC513 );
-+ mac_ocp_write( tp, 0xF818, 0x64A0 );
-+ mac_ocp_write( tp, 0xF81A, 0x49C1 );
-+ mac_ocp_write( tp, 0xF81C, 0xF00A );
-+ mac_ocp_write( tp, 0xF81E, 0x1CEA );
-+ mac_ocp_write( tp, 0xF820, 0x2242 );
-+ mac_ocp_write( tp, 0xF822, 0x0402 );
-+ mac_ocp_write( tp, 0xF824, 0xC50B );
-+ mac_ocp_write( tp, 0xF826, 0x9CA2 );
-+ mac_ocp_write( tp, 0xF828, 0x1C11 );
-+ mac_ocp_write( tp, 0xF82A, 0x9CA0 );
-+ mac_ocp_write( tp, 0xF82C, 0xC506 );
-+ mac_ocp_write( tp, 0xF82E, 0xBD00 );
-+ mac_ocp_write( tp, 0xF830, 0x7444 );
-+ mac_ocp_write( tp, 0xF832, 0xC502 );
-+ mac_ocp_write( tp, 0xF834, 0xBD00 );
-+ mac_ocp_write( tp, 0xF836, 0x0A30 );
-+ mac_ocp_write( tp, 0xF838, 0x0A46 );
-+ mac_ocp_write( tp, 0xF83A, 0xE434 );
-+ mac_ocp_write( tp, 0xF83C, 0xE096 );
-+ mac_ocp_write( tp, 0xF83E, 0x49D9 );
-+ mac_ocp_write( tp, 0xF840, 0xF00F );
-+ mac_ocp_write( tp, 0xF842, 0xC512 );
-+ mac_ocp_write( tp, 0xF844, 0x74A0 );
-+ mac_ocp_write( tp, 0xF846, 0x48C8 );
-+ mac_ocp_write( tp, 0xF848, 0x48CA );
-+ mac_ocp_write( tp, 0xF84A, 0x9CA0 );
-+ mac_ocp_write( tp, 0xF84C, 0xC50F );
-+ mac_ocp_write( tp, 0xF84E, 0x1B00 );
-+ mac_ocp_write( tp, 0xF850, 0x9BA0 );
-+ mac_ocp_write( tp, 0xF852, 0x1B1C );
-+ mac_ocp_write( tp, 0xF854, 0x483F );
-+ mac_ocp_write( tp, 0xF856, 0x9BA2 );
-+ mac_ocp_write( tp, 0xF858, 0x1B04 );
-+ mac_ocp_write( tp, 0xF85A, 0xC5F0 );
-+ mac_ocp_write( tp, 0xF85C, 0x9BA0 );
-+ mac_ocp_write( tp, 0xF85E, 0xC602 );
-+ mac_ocp_write( tp, 0xF860, 0xBE00 );
-+ mac_ocp_write( tp, 0xF862, 0x03DE );
-+ mac_ocp_write( tp, 0xF864, 0xE434 );
-+ mac_ocp_write( tp, 0xF866, 0xE096 );
-+ mac_ocp_write( tp, 0xF868, 0xE860 );
-+ mac_ocp_write( tp, 0xF86A, 0xDE20 );
-+ mac_ocp_write( tp, 0xF86C, 0xC50F );
-+ mac_ocp_write( tp, 0xF86E, 0x76A4 );
-+ mac_ocp_write( tp, 0xF870, 0x49E3 );
-+ mac_ocp_write( tp, 0xF872, 0xF007 );
-+ mac_ocp_write( tp, 0xF874, 0x49C0 );
-+ mac_ocp_write( tp, 0xF876, 0xF103 );
-+ mac_ocp_write( tp, 0xF878, 0xC607 );
-+ mac_ocp_write( tp, 0xF87A, 0xBE00 );
-+ mac_ocp_write( tp, 0xF87C, 0xC606 );
-+ mac_ocp_write( tp, 0xF87E, 0xBE00 );
-+ mac_ocp_write( tp, 0xF880, 0xC602 );
-+ mac_ocp_write( tp, 0xF882, 0xBE00 );
-+ mac_ocp_write( tp, 0xF884, 0x0A88 );
-+ mac_ocp_write( tp, 0xF886, 0x0A64 );
-+ mac_ocp_write( tp, 0xF888, 0x0A68 );
-+ mac_ocp_write( tp, 0xF88A, 0xDC00 );
-+ mac_ocp_write( tp, 0xF88C, 0xC602 );
-+ mac_ocp_write( tp, 0xF88E, 0xBE00 );
-+ mac_ocp_write( tp, 0xF890, 0x0000 );
-+ mac_ocp_write( tp, 0xF892, 0xC602 );
-+ mac_ocp_write( tp, 0xF894, 0xBE00 );
-+ mac_ocp_write( tp, 0xF896, 0x0000 );
-+ mac_ocp_write( tp, 0xF898, 0xC602 );
-+ mac_ocp_write( tp, 0xF89A, 0xBE00 );
-+ mac_ocp_write( tp, 0xF89C, 0x0000 );
-+ mac_ocp_write( tp, 0xF89E, 0xC602 );
-+ mac_ocp_write( tp, 0xF8A0, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8A2, 0x0000 );
-+
-+ mac_ocp_write( tp, 0xFC26, 0x8000 );
-+
-+ mac_ocp_write( tp, 0xFC2A, 0x0A2F );
-+ mac_ocp_write( tp, 0xFC2C, 0x0297 );
-+ mac_ocp_write( tp, 0xFC2E, 0x0A61 );
-+ } else if (tp->mcfg == CFG_METHOD_26) {
-+ rtl8168_hw_disable_mac_mcu_bps(dev);
-+
-+ mac_ocp_write( tp, 0xF800, 0xE008 );
-+ mac_ocp_write( tp, 0xF802, 0xE00A );
-+ mac_ocp_write( tp, 0xF804, 0xE00C );
-+ mac_ocp_write( tp, 0xF806, 0xE00E );
-+ mac_ocp_write( tp, 0xF808, 0xE027 );
-+ mac_ocp_write( tp, 0xF80A, 0xE04F );
-+ mac_ocp_write( tp, 0xF80C, 0xE05E );
-+ mac_ocp_write( tp, 0xF80E, 0xE065 );
-+ mac_ocp_write( tp, 0xF810, 0xC602 );
-+ mac_ocp_write( tp, 0xF812, 0xBE00 );
-+ mac_ocp_write( tp, 0xF814, 0x0000 );
-+ mac_ocp_write( tp, 0xF816, 0xC502 );
-+ mac_ocp_write( tp, 0xF818, 0xBD00 );
-+ mac_ocp_write( tp, 0xF81A, 0x074C );
-+ mac_ocp_write( tp, 0xF81C, 0xC302 );
-+ mac_ocp_write( tp, 0xF81E, 0xBB00 );
-+ mac_ocp_write( tp, 0xF820, 0x080A );
-+ mac_ocp_write( tp, 0xF822, 0x6420 );
-+ mac_ocp_write( tp, 0xF824, 0x48C2 );
-+ mac_ocp_write( tp, 0xF826, 0x8C20 );
-+ mac_ocp_write( tp, 0xF828, 0xC516 );
-+ mac_ocp_write( tp, 0xF82A, 0x64A4 );
-+ mac_ocp_write( tp, 0xF82C, 0x49C0 );
-+ mac_ocp_write( tp, 0xF82E, 0xF009 );
-+ mac_ocp_write( tp, 0xF830, 0x74A2 );
-+ mac_ocp_write( tp, 0xF832, 0x8CA5 );
-+ mac_ocp_write( tp, 0xF834, 0x74A0 );
-+ mac_ocp_write( tp, 0xF836, 0xC50E );
-+ mac_ocp_write( tp, 0xF838, 0x9CA2 );
-+ mac_ocp_write( tp, 0xF83A, 0x1C11 );
-+ mac_ocp_write( tp, 0xF83C, 0x9CA0 );
-+ mac_ocp_write( tp, 0xF83E, 0xE006 );
-+ mac_ocp_write( tp, 0xF840, 0x74F8 );
-+ mac_ocp_write( tp, 0xF842, 0x48C4 );
-+ mac_ocp_write( tp, 0xF844, 0x8CF8 );
-+ mac_ocp_write( tp, 0xF846, 0xC404 );
-+ mac_ocp_write( tp, 0xF848, 0xBC00 );
-+ mac_ocp_write( tp, 0xF84A, 0xC403 );
-+ mac_ocp_write( tp, 0xF84C, 0xBC00 );
-+ mac_ocp_write( tp, 0xF84E, 0x0BF2 );
-+ mac_ocp_write( tp, 0xF850, 0x0C0A );
-+ mac_ocp_write( tp, 0xF852, 0xE434 );
-+ mac_ocp_write( tp, 0xF854, 0xD3C0 );
-+ mac_ocp_write( tp, 0xF856, 0x49D9 );
-+ mac_ocp_write( tp, 0xF858, 0xF01F );
-+ mac_ocp_write( tp, 0xF85A, 0xC526 );
-+ mac_ocp_write( tp, 0xF85C, 0x64A5 );
-+ mac_ocp_write( tp, 0xF85E, 0x1400 );
-+ mac_ocp_write( tp, 0xF860, 0xF007 );
-+ mac_ocp_write( tp, 0xF862, 0x0C01 );
-+ mac_ocp_write( tp, 0xF864, 0x8CA5 );
-+ mac_ocp_write( tp, 0xF866, 0x1C15 );
-+ mac_ocp_write( tp, 0xF868, 0xC51B );
-+ mac_ocp_write( tp, 0xF86A, 0x9CA0 );
-+ mac_ocp_write( tp, 0xF86C, 0xE013 );
-+ mac_ocp_write( tp, 0xF86E, 0xC519 );
-+ mac_ocp_write( tp, 0xF870, 0x74A0 );
-+ mac_ocp_write( tp, 0xF872, 0x48C4 );
-+ mac_ocp_write( tp, 0xF874, 0x8CA0 );
-+ mac_ocp_write( tp, 0xF876, 0xC516 );
-+ mac_ocp_write( tp, 0xF878, 0x74A4 );
-+ mac_ocp_write( tp, 0xF87A, 0x48C8 );
-+ mac_ocp_write( tp, 0xF87C, 0x48CA );
-+ mac_ocp_write( tp, 0xF87E, 0x9CA4 );
-+ mac_ocp_write( tp, 0xF880, 0xC512 );
-+ mac_ocp_write( tp, 0xF882, 0x1B00 );
-+ mac_ocp_write( tp, 0xF884, 0x9BA0 );
-+ mac_ocp_write( tp, 0xF886, 0x1B1C );
-+ mac_ocp_write( tp, 0xF888, 0x483F );
-+ mac_ocp_write( tp, 0xF88A, 0x9BA2 );
-+ mac_ocp_write( tp, 0xF88C, 0x1B04 );
-+ mac_ocp_write( tp, 0xF88E, 0xC508 );
-+ mac_ocp_write( tp, 0xF890, 0x9BA0 );
-+ mac_ocp_write( tp, 0xF892, 0xC505 );
-+ mac_ocp_write( tp, 0xF894, 0xBD00 );
-+ mac_ocp_write( tp, 0xF896, 0xC502 );
-+ mac_ocp_write( tp, 0xF898, 0xBD00 );
-+ mac_ocp_write( tp, 0xF89A, 0x0300 );
-+ mac_ocp_write( tp, 0xF89C, 0x051E );
-+ mac_ocp_write( tp, 0xF89E, 0xE434 );
-+ mac_ocp_write( tp, 0xF8A0, 0xE018 );
-+ mac_ocp_write( tp, 0xF8A2, 0xE092 );
-+ mac_ocp_write( tp, 0xF8A4, 0xDE20 );
-+ mac_ocp_write( tp, 0xF8A6, 0xD3C0 );
-+ mac_ocp_write( tp, 0xF8A8, 0xC50F );
-+ mac_ocp_write( tp, 0xF8AA, 0x76A4 );
-+ mac_ocp_write( tp, 0xF8AC, 0x49E3 );
-+ mac_ocp_write( tp, 0xF8AE, 0xF007 );
-+ mac_ocp_write( tp, 0xF8B0, 0x49C0 );
-+ mac_ocp_write( tp, 0xF8B2, 0xF103 );
-+ mac_ocp_write( tp, 0xF8B4, 0xC607 );
-+ mac_ocp_write( tp, 0xF8B6, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8B8, 0xC606 );
-+ mac_ocp_write( tp, 0xF8BA, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8BC, 0xC602 );
-+ mac_ocp_write( tp, 0xF8BE, 0xBE00 );
-+ mac_ocp_write( tp, 0xF8C0, 0x0C4C );
-+ mac_ocp_write( tp, 0xF8C2, 0x0C28 );
-+ mac_ocp_write( tp, 0xF8C4, 0x0C2C );
-+ mac_ocp_write( tp, 0xF8C6, 0xDC00 );
-+ mac_ocp_write( tp, 0xF8C8, 0xC707 );
-+ mac_ocp_write( tp, 0xF8CA, 0x1D00 );
-+ mac_ocp_write( tp, 0xF8CC, 0x8DE2 );
-+ mac_ocp_write( tp, 0xF8CE, 0x48C1 );
-+ mac_ocp_write( tp, 0xF8D0, 0xC502 );
-+ mac_ocp_write( tp, 0xF8D2, 0xBD00 );
-+ mac_ocp_write( tp, 0xF8D4, 0x00AA );
-+ mac_ocp_write( tp, 0xF8D6, 0xE0C0 );
-+ mac_ocp_write( tp, 0xF8D8, 0xC502 );
-+ mac_ocp_write( tp, 0xF8DA, 0xBD00 );
-+ mac_ocp_write( tp, 0xF8DC, 0x0132 );
-+
-+ mac_ocp_write( tp, 0xFC26, 0x8000 );
-+
-+ mac_ocp_write( tp, 0xFC2A, 0x0743 );
-+ mac_ocp_write( tp, 0xFC2C, 0x0801 );
-+ mac_ocp_write( tp, 0xFC2E, 0x0BE9 );
-+ mac_ocp_write( tp, 0xFC30, 0x02FD );
-+ mac_ocp_write( tp, 0xFC32, 0x0C25 );
-+ mac_ocp_write( tp, 0xFC34, 0x00A9 );
-+ mac_ocp_write( tp, 0xFC36, 0x012D );
-+ } else if (tp->mcfg == CFG_METHOD_27) {
-+ rtl8168_hw_disable_mac_mcu_bps(dev);
-+
-+ mac_ocp_write( tp, 0xF800, 0xE008 );
-+ mac_ocp_write( tp, 0xF802, 0xE0D3 );
-+ mac_ocp_write( tp, 0xF804, 0xE0D6 );
-+ mac_ocp_write( tp, 0xF806, 0xE0D9 );
-+ mac_ocp_write( tp, 0xF808, 0xE0DB );
-+ mac_ocp_write( tp, 0xF80A, 0xE0DD );
-+ mac_ocp_write( tp, 0xF80C, 0xE0DF );
-+ mac_ocp_write( tp, 0xF80E, 0xE0E1 );
-+ mac_ocp_write( tp, 0xF810, 0xC251 );
-+ mac_ocp_write( tp, 0xF812, 0x7340 );
-+ mac_ocp_write( tp, 0xF814, 0x49B1 );
-+ mac_ocp_write( tp, 0xF816, 0xF010 );
-+ mac_ocp_write( tp, 0xF818, 0x1D02 );
-+ mac_ocp_write( tp, 0xF81A, 0x8D40 );
-+ mac_ocp_write( tp, 0xF81C, 0xC202 );
-+ mac_ocp_write( tp, 0xF81E, 0xBA00 );
-+ mac_ocp_write( tp, 0xF820, 0x2C3A );
-+ mac_ocp_write( tp, 0xF822, 0xC0F0 );
-+ mac_ocp_write( tp, 0xF824, 0xE8DE );
-+ mac_ocp_write( tp, 0xF826, 0x2000 );
-+ mac_ocp_write( tp, 0xF828, 0x8000 );
-+ mac_ocp_write( tp, 0xF82A, 0xC0B6 );
-+ mac_ocp_write( tp, 0xF82C, 0x268C );
-+ mac_ocp_write( tp, 0xF82E, 0x752C );
-+ mac_ocp_write( tp, 0xF830, 0x49D4 );
-+ mac_ocp_write( tp, 0xF832, 0xF112 );
-+ mac_ocp_write( tp, 0xF834, 0xE025 );
-+ mac_ocp_write( tp, 0xF836, 0xC2F6 );
-+ mac_ocp_write( tp, 0xF838, 0x7146 );
-+ mac_ocp_write( tp, 0xF83A, 0xC2F5 );
-+ mac_ocp_write( tp, 0xF83C, 0x7340 );
-+ mac_ocp_write( tp, 0xF83E, 0x49BE );
-+ mac_ocp_write( tp, 0xF840, 0xF103 );
-+ mac_ocp_write( tp, 0xF842, 0xC7F2 );
-+ mac_ocp_write( tp, 0xF844, 0xE002 );
-+ mac_ocp_write( tp, 0xF846, 0xC7F1 );
-+ mac_ocp_write( tp, 0xF848, 0x304F );
-+ mac_ocp_write( tp, 0xF84A, 0x6226 );
-+ mac_ocp_write( tp, 0xF84C, 0x49A1 );
-+ mac_ocp_write( tp, 0xF84E, 0xF1F0 );
-+ mac_ocp_write( tp, 0xF850, 0x7222 );
-+ mac_ocp_write( tp, 0xF852, 0x49A0 );
-+ mac_ocp_write( tp, 0xF854, 0xF1ED );
-+ mac_ocp_write( tp, 0xF856, 0x2525 );
-+ mac_ocp_write( tp, 0xF858, 0x1F28 );
-+ mac_ocp_write( tp, 0xF85A, 0x3097 );
-+ mac_ocp_write( tp, 0xF85C, 0x3091 );
-+ mac_ocp_write( tp, 0xF85E, 0x9A36 );
-+ mac_ocp_write( tp, 0xF860, 0x752C );
-+ mac_ocp_write( tp, 0xF862, 0x21DC );
-+ mac_ocp_write( tp, 0xF864, 0x25BC );
-+ mac_ocp_write( tp, 0xF866, 0xC6E2 );
-+ mac_ocp_write( tp, 0xF868, 0x77C0 );
-+ mac_ocp_write( tp, 0xF86A, 0x1304 );
-+ mac_ocp_write( tp, 0xF86C, 0xF014 );
-+ mac_ocp_write( tp, 0xF86E, 0x1303 );
-+ mac_ocp_write( tp, 0xF870, 0xF014 );
-+ mac_ocp_write( tp, 0xF872, 0x1302 );
-+ mac_ocp_write( tp, 0xF874, 0xF014 );
-+ mac_ocp_write( tp, 0xF876, 0x1301 );
-+ mac_ocp_write( tp, 0xF878, 0xF014 );
-+ mac_ocp_write( tp, 0xF87A, 0x49D4 );
-+ mac_ocp_write( tp, 0xF87C, 0xF103 );
-+ mac_ocp_write( tp, 0xF87E, 0xC3D7 );
-+ mac_ocp_write( tp, 0xF880, 0xBB00 );
-+ mac_ocp_write( tp, 0xF882, 0xC618 );
-+ mac_ocp_write( tp, 0xF884, 0x67C6 );
-+ mac_ocp_write( tp, 0xF886, 0x752E );
-+ mac_ocp_write( tp, 0xF888, 0x22D7 );
-+ mac_ocp_write( tp, 0xF88A, 0x26DD );
-+ mac_ocp_write( tp, 0xF88C, 0x1505 );
-+ mac_ocp_write( tp, 0xF88E, 0xF013 );
-+ mac_ocp_write( tp, 0xF890, 0xC60A );
-+ mac_ocp_write( tp, 0xF892, 0xBE00 );
-+ mac_ocp_write( tp, 0xF894, 0xC309 );
-+ mac_ocp_write( tp, 0xF896, 0xBB00 );
-+ mac_ocp_write( tp, 0xF898, 0xC308 );
-+ mac_ocp_write( tp, 0xF89A, 0xBB00 );
-+ mac_ocp_write( tp, 0xF89C, 0xC307 );
-+ mac_ocp_write( tp, 0xF89E, 0xBB00 );
-+ mac_ocp_write( tp, 0xF8A0, 0xC306 );
-+ mac_ocp_write( tp, 0xF8A2, 0xBB00 );
-+ mac_ocp_write( tp, 0xF8A4, 0x25C8 );
-+ mac_ocp_write( tp, 0xF8A6, 0x25A6 );
-+ mac_ocp_write( tp, 0xF8A8, 0x25AC );
-+ mac_ocp_write( tp, 0xF8AA, 0x25B2 );
-+ mac_ocp_write( tp, 0xF8AC, 0x25B8 );
-+ mac_ocp_write( tp, 0xF8AE, 0xCD08 );
-+ mac_ocp_write( tp, 0xF8B0, 0x0000 );
-+ mac_ocp_write( tp, 0xF8B2, 0xC0BC );
-+ mac_ocp_write( tp, 0xF8B4, 0xC2FF );
-+ mac_ocp_write( tp, 0xF8B6, 0x7340 );
-+ mac_ocp_write( tp, 0xF8B8, 0x49B0 );
-+ mac_ocp_write( tp, 0xF8BA, 0xF04E );
-+ mac_ocp_write( tp, 0xF8BC, 0x1F46 );
-+ mac_ocp_write( tp, 0xF8BE, 0x308F );
-+ mac_ocp_write( tp, 0xF8C0, 0xC3F7 );
-+ mac_ocp_write( tp, 0xF8C2, 0x1C04 );
-+ mac_ocp_write( tp, 0xF8C4, 0xE84D );
-+ mac_ocp_write( tp, 0xF8C6, 0x1401 );
-+ mac_ocp_write( tp, 0xF8C8, 0xF147 );
-+ mac_ocp_write( tp, 0xF8CA, 0x7226 );
-+ mac_ocp_write( tp, 0xF8CC, 0x49A7 );
-+ mac_ocp_write( tp, 0xF8CE, 0xF044 );
-+ mac_ocp_write( tp, 0xF8D0, 0x7222 );
-+ mac_ocp_write( tp, 0xF8D2, 0x2525 );
-+ mac_ocp_write( tp, 0xF8D4, 0x1F30 );
-+ mac_ocp_write( tp, 0xF8D6, 0x3097 );
-+ mac_ocp_write( tp, 0xF8D8, 0x3091 );
-+ mac_ocp_write( tp, 0xF8DA, 0x7340 );
-+ mac_ocp_write( tp, 0xF8DC, 0xC4EA );
-+ mac_ocp_write( tp, 0xF8DE, 0x401C );
-+ mac_ocp_write( tp, 0xF8E0, 0xF006 );
-+ mac_ocp_write( tp, 0xF8E2, 0xC6E8 );
-+ mac_ocp_write( tp, 0xF8E4, 0x75C0 );
-+ mac_ocp_write( tp, 0xF8E6, 0x49D7 );
-+ mac_ocp_write( tp, 0xF8E8, 0xF105 );
-+ mac_ocp_write( tp, 0xF8EA, 0xE036 );
-+ mac_ocp_write( tp, 0xF8EC, 0x1D08 );
-+ mac_ocp_write( tp, 0xF8EE, 0x8DC1 );
-+ mac_ocp_write( tp, 0xF8F0, 0x0208 );
-+ mac_ocp_write( tp, 0xF8F2, 0x6640 );
-+ mac_ocp_write( tp, 0xF8F4, 0x2764 );
-+ mac_ocp_write( tp, 0xF8F6, 0x1606 );
-+ mac_ocp_write( tp, 0xF8F8, 0xF12F );
-+ mac_ocp_write( tp, 0xF8FA, 0x6346 );
-+ mac_ocp_write( tp, 0xF8FC, 0x133B );
-+ mac_ocp_write( tp, 0xF8FE, 0xF12C );
-+ mac_ocp_write( tp, 0xF900, 0x9B34 );
-+ mac_ocp_write( tp, 0xF902, 0x1B18 );
-+ mac_ocp_write( tp, 0xF904, 0x3093 );
-+ mac_ocp_write( tp, 0xF906, 0xC32A );
-+ mac_ocp_write( tp, 0xF908, 0x1C10 );
-+ mac_ocp_write( tp, 0xF90A, 0xE82A );
-+ mac_ocp_write( tp, 0xF90C, 0x1401 );
-+ mac_ocp_write( tp, 0xF90E, 0xF124 );
-+ mac_ocp_write( tp, 0xF910, 0x1A36 );
-+ mac_ocp_write( tp, 0xF912, 0x308A );
-+ mac_ocp_write( tp, 0xF914, 0x7322 );
-+ mac_ocp_write( tp, 0xF916, 0x25B5 );
-+ mac_ocp_write( tp, 0xF918, 0x0B0E );
-+ mac_ocp_write( tp, 0xF91A, 0x1C00 );
-+ mac_ocp_write( tp, 0xF91C, 0xE82C );
-+ mac_ocp_write( tp, 0xF91E, 0xC71F );
-+ mac_ocp_write( tp, 0xF920, 0x4027 );
-+ mac_ocp_write( tp, 0xF922, 0xF11A );
-+ mac_ocp_write( tp, 0xF924, 0xE838 );
-+ mac_ocp_write( tp, 0xF926, 0x1F42 );
-+ mac_ocp_write( tp, 0xF928, 0x308F );
-+ mac_ocp_write( tp, 0xF92A, 0x1B08 );
-+ mac_ocp_write( tp, 0xF92C, 0xE824 );
-+ mac_ocp_write( tp, 0xF92E, 0x7236 );
-+ mac_ocp_write( tp, 0xF930, 0x7746 );
-+ mac_ocp_write( tp, 0xF932, 0x1700 );
-+ mac_ocp_write( tp, 0xF934, 0xF00D );
-+ mac_ocp_write( tp, 0xF936, 0xC313 );
-+ mac_ocp_write( tp, 0xF938, 0x401F );
-+ mac_ocp_write( tp, 0xF93A, 0xF103 );
-+ mac_ocp_write( tp, 0xF93C, 0x1F00 );
-+ mac_ocp_write( tp, 0xF93E, 0x9F46 );
-+ mac_ocp_write( tp, 0xF940, 0x7744 );
-+ mac_ocp_write( tp, 0xF942, 0x449F );
-+ mac_ocp_write( tp, 0xF944, 0x445F );
-+ mac_ocp_write( tp, 0xF946, 0xE817 );
-+ mac_ocp_write( tp, 0xF948, 0xC70A );
-+ mac_ocp_write( tp, 0xF94A, 0x4027 );
-+ mac_ocp_write( tp, 0xF94C, 0xF105 );
-+ mac_ocp_write( tp, 0xF94E, 0xC302 );
-+ mac_ocp_write( tp, 0xF950, 0xBB00 );
-+ mac_ocp_write( tp, 0xF952, 0x2E08 );
-+ mac_ocp_write( tp, 0xF954, 0x2DC2 );
-+ mac_ocp_write( tp, 0xF956, 0xC7FF );
-+ mac_ocp_write( tp, 0xF958, 0xBF00 );
-+ mac_ocp_write( tp, 0xF95A, 0xCDB8 );
-+ mac_ocp_write( tp, 0xF95C, 0xFFFF );
-+ mac_ocp_write( tp, 0xF95E, 0x0C02 );
-+ mac_ocp_write( tp, 0xF960, 0xA554 );
-+ mac_ocp_write( tp, 0xF962, 0xA5DC );
-+ mac_ocp_write( tp, 0xF964, 0x402F );
-+ mac_ocp_write( tp, 0xF966, 0xF105 );
-+ mac_ocp_write( tp, 0xF968, 0x1400 );
-+ mac_ocp_write( tp, 0xF96A, 0xF1FA );
-+ mac_ocp_write( tp, 0xF96C, 0x1C01 );
-+ mac_ocp_write( tp, 0xF96E, 0xE002 );
-+ mac_ocp_write( tp, 0xF970, 0x1C00 );
-+ mac_ocp_write( tp, 0xF972, 0xFF80 );
-+ mac_ocp_write( tp, 0xF974, 0x49B0 );
-+ mac_ocp_write( tp, 0xF976, 0xF004 );
-+ mac_ocp_write( tp, 0xF978, 0x0B01 );
-+ mac_ocp_write( tp, 0xF97A, 0xA1D3 );
-+ mac_ocp_write( tp, 0xF97C, 0xE003 );
-+ mac_ocp_write( tp, 0xF97E, 0x0B02 );
-+ mac_ocp_write( tp, 0xF980, 0xA5D3 );
-+ mac_ocp_write( tp, 0xF982, 0x3127 );
-+ mac_ocp_write( tp, 0xF984, 0x3720 );
-+ mac_ocp_write( tp, 0xF986, 0x0B02 );
-+ mac_ocp_write( tp, 0xF988, 0xA5D3 );
-+ mac_ocp_write( tp, 0xF98A, 0x3127 );
-+ mac_ocp_write( tp, 0xF98C, 0x3720 );
-+ mac_ocp_write( tp, 0xF98E, 0x1300 );
-+ mac_ocp_write( tp, 0xF990, 0xF1FB );
-+ mac_ocp_write( tp, 0xF992, 0xFF80 );
-+ mac_ocp_write( tp, 0xF994, 0x7322 );
-+ mac_ocp_write( tp, 0xF996, 0x25B5 );
-+ mac_ocp_write( tp, 0xF998, 0x1E28 );
-+ mac_ocp_write( tp, 0xF99A, 0x30DE );
-+ mac_ocp_write( tp, 0xF99C, 0x30D9 );
-+ mac_ocp_write( tp, 0xF99E, 0x7264 );
-+ mac_ocp_write( tp, 0xF9A0, 0x1E11 );
-+ mac_ocp_write( tp, 0xF9A2, 0x2368 );
-+ mac_ocp_write( tp, 0xF9A4, 0x3116 );
-+ mac_ocp_write( tp, 0xF9A6, 0xFF80 );
-+ mac_ocp_write( tp, 0xF9A8, 0x1B7E );
-+ mac_ocp_write( tp, 0xF9AA, 0xC602 );
-+ mac_ocp_write( tp, 0xF9AC, 0xBE00 );
-+ mac_ocp_write( tp, 0xF9AE, 0x06A6 );
-+ mac_ocp_write( tp, 0xF9B0, 0x1B7E );
-+ mac_ocp_write( tp, 0xF9B2, 0xC602 );
-+ mac_ocp_write( tp, 0xF9B4, 0xBE00 );
-+ mac_ocp_write( tp, 0xF9B6, 0x0764 );
-+ mac_ocp_write( tp, 0xF9B8, 0xC602 );
-+ mac_ocp_write( tp, 0xF9BA, 0xBE00 );
-+ mac_ocp_write( tp, 0xF9BC, 0x0000 );
-+ mac_ocp_write( tp, 0xF9BE, 0xC602 );
-+ mac_ocp_write( tp, 0xF9C0, 0xBE00 );
-+ mac_ocp_write( tp, 0xF9C2, 0x0000 );
-+ mac_ocp_write( tp, 0xF9C4, 0xC602 );
-+ mac_ocp_write( tp, 0xF9C6, 0xBE00 );
-+ mac_ocp_write( tp, 0xF9C8, 0x0000 );
-+ mac_ocp_write( tp, 0xF9CA, 0xC602 );
-+ mac_ocp_write( tp, 0xF9CC, 0xBE00 );
-+ mac_ocp_write( tp, 0xF9CE, 0x0000 );
-+ mac_ocp_write( tp, 0xF9D0, 0xC602 );
-+ mac_ocp_write( tp, 0xF9D2, 0xBE00 );
-+ mac_ocp_write( tp, 0xF9D4, 0x0000 );
-+
-+ mac_ocp_write( tp, 0xFC26, 0x8000 );
-+
-+ mac_ocp_write( tp, 0xFC28, 0x2549 );
-+ mac_ocp_write( tp, 0xFC2A, 0x06A5 );
-+ mac_ocp_write( tp, 0xFC2C, 0x0763 );
-+ } else if (tp->mcfg == CFG_METHOD_28) {
-+ rtl8168_hw_disable_mac_mcu_bps(dev);
-+
-+ mac_ocp_write( tp, 0xF800, 0xE008 );
-+ mac_ocp_write( tp, 0xF802, 0xE017 );
-+ mac_ocp_write( tp, 0xF804, 0xE019 );
-+ mac_ocp_write( tp, 0xF806, 0xE01B );
-+ mac_ocp_write( tp, 0xF808, 0xE01D );
-+ mac_ocp_write( tp, 0xF80A, 0xE01F );
-+ mac_ocp_write( tp, 0xF80C, 0xE021 );
-+ mac_ocp_write( tp, 0xF80E, 0xE023 );
-+ mac_ocp_write( tp, 0xF810, 0xC50F );
-+ mac_ocp_write( tp, 0xF812, 0x76A4 );
-+ mac_ocp_write( tp, 0xF814, 0x49E3 );
-+ mac_ocp_write( tp, 0xF816, 0xF007 );
-+ mac_ocp_write( tp, 0xF818, 0x49C0 );
-+ mac_ocp_write( tp, 0xF81A, 0xF103 );
-+ mac_ocp_write( tp, 0xF81C, 0xC607 );
-+ mac_ocp_write( tp, 0xF81E, 0xBE00 );
-+ mac_ocp_write( tp, 0xF820, 0xC606 );
-+ mac_ocp_write( tp, 0xF822, 0xBE00 );
-+ mac_ocp_write( tp, 0xF824, 0xC602 );
-+ mac_ocp_write( tp, 0xF826, 0xBE00 );
-+ mac_ocp_write( tp, 0xF828, 0x0BDA );
-+ mac_ocp_write( tp, 0xF82A, 0x0BB0 );
-+ mac_ocp_write( tp, 0xF82C, 0x0BBA );
-+ mac_ocp_write( tp, 0xF82E, 0xDC00 );
-+ mac_ocp_write( tp, 0xF830, 0xC602 );
-+ mac_ocp_write( tp, 0xF832, 0xBE00 );
-+ mac_ocp_write( tp, 0xF834, 0x0000 );
-+ mac_ocp_write( tp, 0xF836, 0xC602 );
-+ mac_ocp_write( tp, 0xF838, 0xBE00 );
-+ mac_ocp_write( tp, 0xF83A, 0x0000 );
-+ mac_ocp_write( tp, 0xF83C, 0xC602 );
-+ mac_ocp_write( tp, 0xF83E, 0xBE00 );
-+ mac_ocp_write( tp, 0xF840, 0x0000 );
-+ mac_ocp_write( tp, 0xF842, 0xC602 );
-+ mac_ocp_write( tp, 0xF844, 0xBE00 );
-+ mac_ocp_write( tp, 0xF846, 0x0000 );
-+ mac_ocp_write( tp, 0xF848, 0xC602 );
-+ mac_ocp_write( tp, 0xF84A, 0xBE00 );
-+ mac_ocp_write( tp, 0xF84C, 0x0000 );
-+ mac_ocp_write( tp, 0xF84E, 0xC602 );
-+ mac_ocp_write( tp, 0xF850, 0xBE00 );
-+ mac_ocp_write( tp, 0xF852, 0x0000 );
-+ mac_ocp_write( tp, 0xF854, 0xC602 );
-+ mac_ocp_write( tp, 0xF856, 0xBE00 );
-+ mac_ocp_write( tp, 0xF858, 0x0000 );
-+
-+ mac_ocp_write( tp, 0xFC26, 0x8000 );
-+
-+ mac_ocp_write( tp, 0xFC28, 0x0BB3 );
-+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ rtl8168_hw_disable_mac_mcu_bps(dev);
-+
-+ mac_ocp_write(tp, 0xF800, 0xE008);
-+ mac_ocp_write(tp, 0xF802, 0xE00F);
-+ mac_ocp_write(tp, 0xF804, 0xE011);
-+ mac_ocp_write(tp, 0xF806, 0xE047);
-+ mac_ocp_write(tp, 0xF808, 0xE049);
-+ mac_ocp_write(tp, 0xF80A, 0xE073);
-+ mac_ocp_write(tp, 0xF80C, 0xE075);
-+ mac_ocp_write(tp, 0xF80E, 0xE077);
-+ mac_ocp_write(tp, 0xF810, 0xC707);
-+ mac_ocp_write(tp, 0xF812, 0x1D00);
-+ mac_ocp_write(tp, 0xF814, 0x8DE2);
-+ mac_ocp_write(tp, 0xF816, 0x48C1);
-+ mac_ocp_write(tp, 0xF818, 0xC502);
-+ mac_ocp_write(tp, 0xF81A, 0xBD00);
-+ mac_ocp_write(tp, 0xF81C, 0x00E4);
-+ mac_ocp_write(tp, 0xF81E, 0xE0C0);
-+ mac_ocp_write(tp, 0xF820, 0xC502);
-+ mac_ocp_write(tp, 0xF822, 0xBD00);
-+ mac_ocp_write(tp, 0xF824, 0x0216);
-+ mac_ocp_write(tp, 0xF826, 0xC634);
-+ mac_ocp_write(tp, 0xF828, 0x75C0);
-+ mac_ocp_write(tp, 0xF82A, 0x49D3);
-+ mac_ocp_write(tp, 0xF82C, 0xF027);
-+ mac_ocp_write(tp, 0xF82E, 0xC631);
-+ mac_ocp_write(tp, 0xF830, 0x75C0);
-+ mac_ocp_write(tp, 0xF832, 0x49D3);
-+ mac_ocp_write(tp, 0xF834, 0xF123);
-+ mac_ocp_write(tp, 0xF836, 0xC627);
-+ mac_ocp_write(tp, 0xF838, 0x75C0);
-+ mac_ocp_write(tp, 0xF83A, 0xB405);
-+ mac_ocp_write(tp, 0xF83C, 0xC525);
-+ mac_ocp_write(tp, 0xF83E, 0x9DC0);
-+ mac_ocp_write(tp, 0xF840, 0xC621);
-+ mac_ocp_write(tp, 0xF842, 0x75C8);
-+ mac_ocp_write(tp, 0xF844, 0x49D5);
-+ mac_ocp_write(tp, 0xF846, 0xF00A);
-+ mac_ocp_write(tp, 0xF848, 0x49D6);
-+ mac_ocp_write(tp, 0xF84A, 0xF008);
-+ mac_ocp_write(tp, 0xF84C, 0x49D7);
-+ mac_ocp_write(tp, 0xF84E, 0xF006);
-+ mac_ocp_write(tp, 0xF850, 0x49D8);
-+ mac_ocp_write(tp, 0xF852, 0xF004);
-+ mac_ocp_write(tp, 0xF854, 0x75D2);
-+ mac_ocp_write(tp, 0xF856, 0x49D9);
-+ mac_ocp_write(tp, 0xF858, 0xF111);
-+ mac_ocp_write(tp, 0xF85A, 0xC517);
-+ mac_ocp_write(tp, 0xF85C, 0x9DC8);
-+ mac_ocp_write(tp, 0xF85E, 0xC516);
-+ mac_ocp_write(tp, 0xF860, 0x9DD2);
-+ mac_ocp_write(tp, 0xF862, 0xC618);
-+ mac_ocp_write(tp, 0xF864, 0x75C0);
-+ mac_ocp_write(tp, 0xF866, 0x49D4);
-+ mac_ocp_write(tp, 0xF868, 0xF003);
-+ mac_ocp_write(tp, 0xF86A, 0x49D0);
-+ mac_ocp_write(tp, 0xF86C, 0xF104);
-+ mac_ocp_write(tp, 0xF86E, 0xC60A);
-+ mac_ocp_write(tp, 0xF870, 0xC50E);
-+ mac_ocp_write(tp, 0xF872, 0x9DC0);
-+ mac_ocp_write(tp, 0xF874, 0xB005);
-+ mac_ocp_write(tp, 0xF876, 0xC607);
-+ mac_ocp_write(tp, 0xF878, 0x9DC0);
-+ mac_ocp_write(tp, 0xF87A, 0xB007);
-+ mac_ocp_write(tp, 0xF87C, 0xC602);
-+ mac_ocp_write(tp, 0xF87E, 0xBE00);
-+ mac_ocp_write(tp, 0xF880, 0x1A06);
-+ mac_ocp_write(tp, 0xF882, 0xB400);
-+ mac_ocp_write(tp, 0xF884, 0xE86C);
-+ mac_ocp_write(tp, 0xF886, 0xA000);
-+ mac_ocp_write(tp, 0xF888, 0x01E1);
-+ mac_ocp_write(tp, 0xF88A, 0x0200);
-+ mac_ocp_write(tp, 0xF88C, 0x9200);
-+ mac_ocp_write(tp, 0xF88E, 0xE84C);
-+ mac_ocp_write(tp, 0xF890, 0xE004);
-+ mac_ocp_write(tp, 0xF892, 0xE908);
-+ mac_ocp_write(tp, 0xF894, 0xC502);
-+ mac_ocp_write(tp, 0xF896, 0xBD00);
-+ mac_ocp_write(tp, 0xF898, 0x0B58);
-+ mac_ocp_write(tp, 0xF89A, 0xB407);
-+ mac_ocp_write(tp, 0xF89C, 0xB404);
-+ mac_ocp_write(tp, 0xF89E, 0x2195);
-+ mac_ocp_write(tp, 0xF8A0, 0x25BD);
-+ mac_ocp_write(tp, 0xF8A2, 0x9BE0);
-+ mac_ocp_write(tp, 0xF8A4, 0x1C1C);
-+ mac_ocp_write(tp, 0xF8A6, 0x484F);
-+ mac_ocp_write(tp, 0xF8A8, 0x9CE2);
-+ mac_ocp_write(tp, 0xF8AA, 0x72E2);
-+ mac_ocp_write(tp, 0xF8AC, 0x49AE);
-+ mac_ocp_write(tp, 0xF8AE, 0xF1FE);
-+ mac_ocp_write(tp, 0xF8B0, 0x0B00);
-+ mac_ocp_write(tp, 0xF8B2, 0xF116);
-+ mac_ocp_write(tp, 0xF8B4, 0xC71C);
-+ mac_ocp_write(tp, 0xF8B6, 0xC419);
-+ mac_ocp_write(tp, 0xF8B8, 0x9CE0);
-+ mac_ocp_write(tp, 0xF8BA, 0x1C13);
-+ mac_ocp_write(tp, 0xF8BC, 0x484F);
-+ mac_ocp_write(tp, 0xF8BE, 0x9CE2);
-+ mac_ocp_write(tp, 0xF8C0, 0x74E2);
-+ mac_ocp_write(tp, 0xF8C2, 0x49CE);
-+ mac_ocp_write(tp, 0xF8C4, 0xF1FE);
-+ mac_ocp_write(tp, 0xF8C6, 0xC412);
-+ mac_ocp_write(tp, 0xF8C8, 0x9CE0);
-+ mac_ocp_write(tp, 0xF8CA, 0x1C13);
-+ mac_ocp_write(tp, 0xF8CC, 0x484F);
-+ mac_ocp_write(tp, 0xF8CE, 0x9CE2);
-+ mac_ocp_write(tp, 0xF8D0, 0x74E2);
-+ mac_ocp_write(tp, 0xF8D2, 0x49CE);
-+ mac_ocp_write(tp, 0xF8D4, 0xF1FE);
-+ mac_ocp_write(tp, 0xF8D6, 0xC70C);
-+ mac_ocp_write(tp, 0xF8D8, 0x74F8);
-+ mac_ocp_write(tp, 0xF8DA, 0x48C3);
-+ mac_ocp_write(tp, 0xF8DC, 0x8CF8);
-+ mac_ocp_write(tp, 0xF8DE, 0xB004);
-+ mac_ocp_write(tp, 0xF8E0, 0xB007);
-+ mac_ocp_write(tp, 0xF8E2, 0xC502);
-+ mac_ocp_write(tp, 0xF8E4, 0xBD00);
-+ mac_ocp_write(tp, 0xF8E6, 0x0F24);
-+ mac_ocp_write(tp, 0xF8E8, 0x0481);
-+ mac_ocp_write(tp, 0xF8EA, 0x0C81);
-+ mac_ocp_write(tp, 0xF8EC, 0xDE24);
-+ mac_ocp_write(tp, 0xF8EE, 0xE000);
-+ mac_ocp_write(tp, 0xF8F0, 0xC602);
-+ mac_ocp_write(tp, 0xF8F2, 0xBE00);
-+ mac_ocp_write(tp, 0xF8F4, 0x0CA4);
-+ mac_ocp_write(tp, 0xF8F6, 0xC502);
-+ mac_ocp_write(tp, 0xF8F8, 0xBD00);
-+ mac_ocp_write(tp, 0xF8FA, 0x0000);
-+ mac_ocp_write(tp, 0xF8FC, 0xC602);
-+ mac_ocp_write(tp, 0xF8FE, 0xBE00);
-+ mac_ocp_write(tp, 0xF900, 0x0000);
-+
-+ mac_ocp_write(tp, 0xFC26, 0x8000);
-+
-+ mac_ocp_write(tp, 0xFC28, 0x00E2);
-+ mac_ocp_write(tp, 0xFC2A, 0x0210);
-+ mac_ocp_write(tp, 0xFC2C, 0x1A04);
-+ mac_ocp_write(tp, 0xFC2E, 0x0B26);
-+
-+ mac_ocp_write(tp, 0xFC38, 0x003F);
-+ }
-+}
-+
-+static void
-+rtl8168_hw_init(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ unsigned long flags;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ RTL_W8(Cfg9346, Cfg9346_Unlock);
-+ RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0);
-+ RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7);
-+ RTL_W8(Cfg9346, Cfg9346_Lock);
-+ RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7);
-+ break;
-+ }
-+
-+ //Disable UPS
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ mac_ocp_write(tp, 0xD400, mac_ocp_read( tp, 0xD400) & ~(BIT_0));
-+ break;
-+ }
-+
-+ //Disable DMA Aggregation
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ mac_ocp_write(tp, 0xE63E, mac_ocp_read( tp, 0xE63E) & ~(BIT_3 | BIT_2 | BIT_1));
-+ mac_ocp_write(tp, 0xE63E, mac_ocp_read( tp, 0xE63E) | (BIT_0));
-+ mac_ocp_write(tp, 0xE63E, mac_ocp_read( tp, 0xE63E) & ~(BIT_0));
-+ mac_ocp_write(tp, 0xC094, 0x0);
-+ mac_ocp_write(tp, 0xC09E, 0x0);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_9:
-+ case CFG_METHOD_10:
-+ RTL_W8(DBG_reg, RTL_R8(DBG_reg) | BIT_1 | BIT_7);
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ RTL_W8(0xF2, (RTL_R8(0xF2) & ~(BIT_2 | BIT_1 | BIT_0)));
-+ break;
-+ }
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ if (aspm) {
-+ RTL_W8(0x6E, RTL_R8(0x6E) | BIT_6);
-+ rtl8168_eri_write(ioaddr, 0x1AE, 2, 0x0403, ERIAR_ExGMAC);
-+ }
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ if (aspm) {
-+ if ((mac_ocp_read(tp, 0xDC00) & BIT_3) || (RTL_R8(Config0) & 0x07)) {
-+ RTL_W8(0x6E, RTL_R8(0x6E) | BIT_6);
-+ rtl8168_eri_write(ioaddr, 0x1AE, 2, 0x0403, ERIAR_ExGMAC);
-+ }
-+ }
-+ break;
-+ }
-+
-+ if (tp->mcfg == CFG_METHOD_10 || tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15)
-+ RTL_W8(0xF3, RTL_R8(0xF3) | BIT_2);
-+
-+ rtl8168_hw_mac_mcu_config(dev);
-+
-+ /*disable ocp phy power saving*/
-+ if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
-+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
-+ tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ spin_lock_irqsave(&tp->phy_lock, flags);
-+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0000);
-+ mdio_write_phy_ocp(tp, 0x0C41, 0x13, 0x0500);
-+ spin_unlock_irqrestore(&tp->phy_lock, flags);
-+ }
-+}
-+
-+static void
-+rtl8168_hw_ephy_config(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ void __iomem *ioaddr = tp->mmio_addr;
-+ u16 ephy_data;
-+
-+
-+ if (tp->mcfg == CFG_METHOD_4) {
-+ /*Set EPHY registers begin*/
-+ /*Set EPHY register offset 0x02 bit 11 to 0 and bit 12 to 1*/
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x02);
-+ ephy_data &= ~BIT_11;
-+ ephy_data |= BIT_12;
-+ rtl8168_ephy_write(ioaddr, 0x02, ephy_data);
-+
-+ /*Set EPHY register offset 0x03 bit 1 to 1*/
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x03);
-+ ephy_data |= (1 << 1);
-+ rtl8168_ephy_write(ioaddr, 0x03, ephy_data);
-+
-+ /*Set EPHY register offset 0x06 bit 7 to 0*/
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
-+ ephy_data &= ~(1 << 7);
-+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
-+ /*Set EPHY registers end*/
-+ } else if (tp->mcfg == CFG_METHOD_5) {
-+ /* set EPHY registers */
-+ SetPCIePhyBit(tp, 0x01, BIT_0);
-+
-+ ClearAndSetPCIePhyBit(tp,
-+ 0x03,
-+ BIT_10,
-+ BIT_5
-+ );
-+ } else if (tp->mcfg == CFG_METHOD_9) {
-+ /* set EPHY registers */
-+ rtl8168_ephy_write(ioaddr, 0x01, 0x7C7F);
-+ rtl8168_ephy_write(ioaddr, 0x02, 0x011F);
-+ if(tp->eeprom_type != EEPROM_TYPE_NONE) {
-+ ClearAndSetPCIePhyBit(tp,
-+ 0x03,
-+ 0xFFB0,
-+ 0x05B0
-+ );
-+ } else {
-+ ClearAndSetPCIePhyBit(tp,
-+ 0x03,
-+ 0xFFF0,
-+ 0x05F0
-+ );
-+ }
-+ rtl8168_ephy_write(ioaddr, 0x06, 0xB271);
-+ rtl8168_ephy_write(ioaddr, 0x07, 0xCE00);
-+ } else if (tp->mcfg == CFG_METHOD_10) {
-+ /* set EPHY registers */
-+ rtl8168_ephy_write(ioaddr, 0x01, 0x6C7F);
-+ rtl8168_ephy_write(ioaddr, 0x02, 0x011F);
-+ ClearAndSetPCIePhyBit(tp,
-+ 0x03,
-+ 0xFFF0,
-+ 0x01B0
-+ );
-+ rtl8168_ephy_write(ioaddr, 0x1A, 0x0546);
-+ rtl8168_ephy_write(ioaddr, 0x1C, 0x80C4);
-+ rtl8168_ephy_write(ioaddr, 0x1D, 0x78E5);
-+ rtl8168_ephy_write(ioaddr, 0x0A, 0x8100);
-+ } else if (tp->mcfg == CFG_METHOD_12) {
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0B);
-+ rtl8168_ephy_write(ioaddr, 0x0B, ephy_data|0x48);
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
-+ ephy_data &= ~0x20;
-+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data|0x50);
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
-+ ephy_data &= ~0x100;
-+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data|0x20);
-+ } else if (tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) {
-+ /* set EPHY registers */
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00) & ~0x0200;
-+ ephy_data |= 0x0100;
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
-+ ephy_data |= 0x0004;
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06) & ~0x0002;
-+ ephy_data |= 0x0001;
-+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
-+ ephy_data |= 0x0030;
-+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x07);
-+ ephy_data |= 0x2000;
-+ rtl8168_ephy_write(ioaddr, 0x07, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
-+ ephy_data |= 0x0020;
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x03) & ~0x5800;
-+ ephy_data |= 0x2000;
-+ rtl8168_ephy_write(ioaddr, 0x03, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x03);
-+ ephy_data |= 0x0001;
-+ rtl8168_ephy_write(ioaddr, 0x03, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x01) & ~0x0800;
-+ ephy_data |= 0x1000;
-+ rtl8168_ephy_write(ioaddr, 0x01, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x07);
-+ ephy_data |= 0x4000;
-+ rtl8168_ephy_write(ioaddr, 0x07, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x1E);
-+ ephy_data |= 0x2000;
-+ rtl8168_ephy_write(ioaddr, 0x1E, ephy_data);
-+
-+ rtl8168_ephy_write(ioaddr, 0x19, 0xFE6C);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0A);
-+ ephy_data |= 0x0040;
-+ rtl8168_ephy_write(ioaddr, 0x0A, ephy_data);
-+ } else if (tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17) {
-+ if (tp->mcfg == CFG_METHOD_16) {
-+ rtl8168_ephy_write(ioaddr, 0x06, 0xF020);
-+ rtl8168_ephy_write(ioaddr, 0x07, 0x01FF);
-+ rtl8168_ephy_write(ioaddr, 0x00, 0x5027);
-+ rtl8168_ephy_write(ioaddr, 0x01, 0x0003);
-+ rtl8168_ephy_write(ioaddr, 0x02, 0x2D16);
-+ rtl8168_ephy_write(ioaddr, 0x03, 0x6D49);
-+ rtl8168_ephy_write(ioaddr, 0x08, 0x0006);
-+ rtl8168_ephy_write(ioaddr, 0x0A, 0x00C8);
-+ }
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x09);
-+ ephy_data |= BIT_7;
-+ rtl8168_ephy_write(ioaddr, 0x09, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
-+ ephy_data |= (BIT_2 | BIT_5 | BIT_9);
-+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
-+ ephy_data |= BIT_3;
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
-+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
-+ ephy_data |= BIT_9;
-+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
-+ } else if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19) {
-+ if (tp->mcfg == CFG_METHOD_18) {
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
-+ ephy_data |= BIT_5;
-+ ephy_data &= ~(BIT_7 | BIT_6);
-+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x08);
-+ ephy_data |= BIT_1;
-+ ephy_data &= ~BIT_0;
-+ rtl8168_ephy_write(ioaddr, 0x08, ephy_data);
-+ }
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x09);
-+ ephy_data |= BIT_7;
-+ rtl8168_ephy_write(ioaddr, 0x09, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
-+ ephy_data |= (BIT_2 | BIT_5 | BIT_9);
-+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
-+ ephy_data |= BIT_3;
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
-+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
-+ ephy_data |= BIT_9;
-+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
-+ } else if (tp->mcfg == CFG_METHOD_20) {
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
-+ ephy_data |= BIT_5;
-+ ephy_data &= ~(BIT_7 | BIT_6);
-+ rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
-+
-+ rtl8168_ephy_write(ioaddr, 0x0f, 0x5200);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
-+ ephy_data |= (BIT_2 | BIT_5 | BIT_9);
-+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
-+ ephy_data |= BIT_3;
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
-+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
-+ ephy_data |= BIT_9;
-+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
-+ } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22) {
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
-+ ephy_data &= ~(BIT_3);
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
-+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
-+ ephy_data |= (BIT_5 | BIT_11);
-+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x1E);
-+ ephy_data |= (BIT_0);
-+ rtl8168_ephy_write(ioaddr, 0x1E, ephy_data);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
-+ ephy_data &= ~(BIT_15);
-+ rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
-+ } else if (tp->mcfg == CFG_METHOD_25) {
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
-+ ephy_data &= ~BIT_3;
-+ rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
-+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10| BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
-+ ephy_data |= (BIT_5 | BIT_11);
-+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
-+
-+ rtl8168_ephy_write(ioaddr, 0x19, 0x7C00);
-+ rtl8168_ephy_write(ioaddr, 0x1E, 0x20EB);
-+ rtl8168_ephy_write(ioaddr, 0x0D, 0x1666);
-+ rtl8168_ephy_write(ioaddr, 0x00, 0x10A3);
-+ rtl8168_ephy_write(ioaddr, 0x06, 0xF050);
-+ } else if (tp->mcfg == CFG_METHOD_26) {
-+ ClearPCIePhyBit(tp, 0x00, BIT_3);
-+ ClearAndSetPCIePhyBit( tp,
-+ 0x0C,
-+ (BIT_13 | BIT_12 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_4),
-+ (BIT_5 | BIT_11)
-+ );
-+ ClearPCIePhyBit(tp, 0x1E, BIT_0);
-+ ClearPCIePhyBit(tp, 0x19, BIT_15);
-+
-+ ClearPCIePhyBit(tp, 0x19, (BIT_5 | BIT_0));
-+
-+ SetPCIePhyBit(tp, 0x1E, BIT_13);
-+ ClearPCIePhyBit(tp, 0x0D, BIT_8);
-+ SetPCIePhyBit(tp, 0x0D, BIT_9);
-+ SetPCIePhyBit(tp, 0x00, BIT_7);
-+
-+ SetPCIePhyBit(tp, 0x06, BIT_4);
-+ } else if (tp->mcfg == CFG_METHOD_23) {
-+ rtl8168_ephy_write(ioaddr, 0x00, 0x10AB);
-+ rtl8168_ephy_write(ioaddr, 0x06, 0xf030);
-+ rtl8168_ephy_write(ioaddr, 0x08, 0x2006);
-+ rtl8168_ephy_write(ioaddr, 0x0D, 0x1666);
-+
-+ ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
-+ ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
-+ rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
-+ } else if (tp->mcfg == CFG_METHOD_27) {
-+ rtl8168_ephy_write(ioaddr, 0x00, 0x10A3);
-+ rtl8168_ephy_write(ioaddr, 0x19, 0xFC00);
-+ rtl8168_ephy_write(ioaddr, 0x1E, 0x20EA);
-+ } else if (tp->mcfg == CFG_METHOD_28) {
-+ SetPCIePhyBit(tp, 0x00, BIT_7);
-+ ClearAndSetPCIePhyBit(tp,
-+ 0x0D,
-+ BIT_8,
-+ BIT_9
-+ );
-+ ClearPCIePhyBit(tp, 0x19, (BIT_15 | BIT_5 | BIT_0));
-+ SetPCIePhyBit(tp, 0x1E, BIT_13);
-+
-+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
-+ ClearPCIePhyBit(tp, 0x1E, BIT_11);
-+
-+ SetPCIePhyBit(tp, 0x1E, BIT_0);
-+ SetPCIePhyBit(tp, 0x1D, BIT_11);
-+
-+ rtl8168_ephy_write(ioaddr, 0x05, 0x2089);
-+ rtl8168_ephy_write(ioaddr, 0x06, 0x5881);
-+
-+ rtl8168_ephy_write(ioaddr, 0x04, 0x154A);
-+ rtl8168_ephy_write(ioaddr, 0x01, 0x068B);
-+ }
-+}
-+
-+static int
-+rtl8168_check_hw_phy_mcu_code_ver(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ int ram_code_ver_match = 0;
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B60);
-+ tp->hw_ram_code_ver = mdio_read(tp, 0x06);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ break;
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B30);
-+ tp->hw_ram_code_ver = mdio_read(tp, 0x06);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ mdio_write(tp, 0x13, 0x801E);
-+ tp->hw_ram_code_ver = mdio_read(tp, 0x14);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ break;
-+ default:
-+ tp->hw_ram_code_ver = ~0;
-+ break;
-+ }
-+
-+ if( tp->hw_ram_code_ver == tp->sw_ram_code_ver) {
-+ ram_code_ver_match = 1;
-+ tp->HwHasWrRamCodeToMicroP = TRUE;
-+ }
-+
-+ return ram_code_ver_match;
-+}
-+
-+static void
-+rtl8168_write_hw_phy_mcu_code_ver(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+
-+ switch (tp->mcfg) {
-+ case CFG_METHOD_14:
-+ case CFG_METHOD_15:
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B60);
-+ mdio_write(tp, 0x06, tp->sw_ram_code_ver);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ tp->hw_ram_code_ver = tp->sw_ram_code_ver;
-+ break;
-+ case CFG_METHOD_16:
-+ case CFG_METHOD_17:
-+ case CFG_METHOD_18:
-+ case CFG_METHOD_19:
-+ case CFG_METHOD_20:
-+ mdio_write(tp, 0x1F, 0x0005);
-+ mdio_write(tp, 0x05, 0x8B30);
-+ mdio_write(tp, 0x06, tp->sw_ram_code_ver);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ tp->hw_ram_code_ver = tp->sw_ram_code_ver;
-+ break;
-+ case CFG_METHOD_21:
-+ case CFG_METHOD_22:
-+ case CFG_METHOD_23:
-+ case CFG_METHOD_27:
-+ case CFG_METHOD_28:
-+ case CFG_METHOD_24:
-+ case CFG_METHOD_25:
-+ case CFG_METHOD_26:
-+ case CFG_METHOD_29:
-+ case CFG_METHOD_30:
-+ mdio_write(tp, 0x1F, 0x0A43);
-+ mdio_write(tp, 0x13, 0x801E);
-+ mdio_write(tp, 0x14, tp->sw_ram_code_ver);
-+ mdio_write(tp, 0x1F, 0x0000);
-+ tp->hw_ram_code_ver = tp->sw_ram_code_ver;
-+ break;
-+ }
-+}
-+static int
-+rtl8168_phy_ram_code_check(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ u16 PhyRegValue;
-+ u32 WaitCnt;
-+ int retval = TRUE;
-+
-+ switch(tp->mcfg) {
-+ case CFG_METHOD_21:
-+ mdio_write(tp, 0x1f, 0x0A40);
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= ~(BIT_11);
-+ mdio_write(tp, 0x10, PhyRegValue);
-+
-+
-+ mdio_write(tp, 0x1f, 0x0A00);
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= ~(BIT_12 | BIT_13 | BIT_14 | BIT_15);
-+ mdio_write(tp, 0x10, PhyRegValue);
-+
-+ mdio_write(tp, 0x1f, 0x0A43);
-+ mdio_write(tp, 0x13, 0x8010);
-+ PhyRegValue = mdio_read(tp, 0x14);
-+ PhyRegValue &= ~(BIT_11);
-+ mdio_write(tp, 0x14, PhyRegValue);
-+
-+ mdio_write(tp,0x1f, 0x0B82);
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue |= BIT_4;
-+ mdio_write(tp,0x10, PhyRegValue);
-+
-+ mdio_write(tp,0x1f, 0x0B80);
-+ WaitCnt = 0;
-+ do {
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= 0x0040;
-+ udelay(100);
-+ WaitCnt++;
-+ } while(PhyRegValue != 0x0040 && WaitCnt <1000);
-+
-+ if(WaitCnt == 1000) {
-+ retval = FALSE ;
-+ }
-+
-+ mdio_write(tp, 0x1f, 0x0A40);
-+ mdio_write(tp, 0x10, 0x0140);
-+
-+ mdio_write(tp, 0x1f, 0x0A4A);
-+ PhyRegValue = mdio_read(tp, 0x13);
-+ PhyRegValue &= ~(BIT_6);
-+ PhyRegValue |= (BIT_7);
-+ mdio_write(tp, 0x13, PhyRegValue);
-+
-+ mdio_write(tp, 0x1f, 0x0A44);
-+ PhyRegValue = mdio_read(tp, 0x14);
-+ PhyRegValue |= (BIT_2);
-+ mdio_write(tp, 0x14, PhyRegValue);
-+
-+ mdio_write(tp, 0x1f, 0x0A50);
-+ PhyRegValue = mdio_read(tp, 0x11);
-+ PhyRegValue |= (BIT_11|BIT_12);
-+ mdio_write(tp, 0x11, PhyRegValue);
-+
-+ mdio_write(tp, 0x1f, 0x0B82);
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= ~(BIT_4);
-+ mdio_write(tp, 0x10, PhyRegValue);
-+
-+ mdio_write(tp,0x1f, 0x0A22);
-+ WaitCnt = 0;
-+ do {
-+ PhyRegValue = mdio_read(tp, 0x12);
-+ PhyRegValue &= 0x0010;
-+ udelay(100);
-+ WaitCnt++;
-+ } while(PhyRegValue != 0x0010 && WaitCnt <1000);
-+
-+ if(WaitCnt == 1000) {
-+ retval = FALSE;
-+ }
-+
-+ mdio_write(tp, 0x1f, 0x0A40);
-+ mdio_write(tp, 0x10, 0x1040);
-+
-+ mdio_write(tp, 0x1f, 0x0A4A);
-+ PhyRegValue = mdio_read(tp, 0x13);
-+ PhyRegValue &= ~(BIT_6|BIT_7);
-+ mdio_write(tp, 0x13, PhyRegValue);
-+
-+ mdio_write(tp, 0x1f, 0x0A44);
-+ PhyRegValue = mdio_read(tp, 0x14);
-+ PhyRegValue &= ~(BIT_2);
-+ mdio_write(tp, 0x14, PhyRegValue);
-+
-+ mdio_write(tp, 0x1f, 0x0A50);
-+ PhyRegValue = mdio_read(tp, 0x11);
-+ PhyRegValue &= ~(BIT_11|BIT_12);
-+ mdio_write(tp, 0x11, PhyRegValue);
-+
-+ mdio_write(tp, 0x1f, 0x0A43);
-+ mdio_write(tp, 0x13, 0x8010);
-+ PhyRegValue = mdio_read(tp, 0x14);
-+ PhyRegValue |= (BIT_11);
-+ mdio_write(tp, 0x14, PhyRegValue);
-+
-+ mdio_write(tp,0x1f, 0x0B82);
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue |= BIT_4;
-+ mdio_write(tp,0x10, PhyRegValue);
-+
-+ mdio_write(tp,0x1f, 0x0B80);
-+ WaitCnt = 0;
-+ do {
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= 0x0040;
-+ udelay(100);
-+ WaitCnt++;
-+ } while(PhyRegValue != 0x0040 && WaitCnt <1000);
-+
-+ if( WaitCnt == 1000) {
-+ retval = FALSE;
-+ }
-+
-+ mdio_write(tp, 0x1f, 0x0A20);
-+ PhyRegValue = mdio_read(tp, 0x13);
-+ if(PhyRegValue & BIT_11) {
-+ if(PhyRegValue & BIT_10) {
-+ retval = FALSE;
-+ }
-+ }
-+
-+ mdio_write(tp, 0x1f, 0x0B82);
-+ PhyRegValue = mdio_read(tp, 0x10);
-+ PhyRegValue &= ~(BIT_4);
-+ mdio_write(tp, 0x10, PhyRegValue);
-+
-+ mdelay(2);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ mdio_write(tp, 0x1F, 0x0000);
-+
-+ return retval;
-+}
-+
-+static void
-+rtl8168_set_phy_ram_code_check_fail_flag(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ u16 TmpUshort;
-+
-+ switch(tp->mcfg) {
-+ case CFG_METHOD_21:
-+ TmpUshort = mac_ocp_read(tp, 0xD3C0);
-+ TmpUshort |= BIT_0;
-+ mac_ocp_write(tp, 0xD3C0, TmpUshort);
-+ break;
-+ }
-+}
-+
-+static void
-+rtl8168_set_phy_mcu_8168e_1(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned int gphy_val,i;
-+
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x00, 0x1800);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0023);
-+ mdio_write(tp, 0x17, 0x0117);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1E, 0x002C);
-+ mdio_write(tp, 0x1B, 0x5000);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x16, 0x4104);
-+ for (i = 0; i < 200; i++) {
-+ udelay(100);
-+ gphy_val = mdio_read(tp, 0x1E);
-+ gphy_val &= 0x03FF;
-+ if (gphy_val == 0x000C)
-+ break;
-+ }
-+ mdio_write(tp, 0x1f, 0x0005);
-+ for (i = 0; i < 200; i++) {
-+ udelay(100);
-+ gphy_val = mdio_read(tp, 0x07);
-+ if ((gphy_val & BIT_5) == 0)
-+ break;
-+ }
-+ gphy_val = mdio_read(tp, 0x07);
-+ if (gphy_val & BIT_5) {
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x00a1);
-+ mdio_write(tp, 0x17, 0x1000);
-+ mdio_write(tp, 0x17, 0x0000);
-+ mdio_write(tp, 0x17, 0x2000);
-+ mdio_write(tp, 0x1e, 0x002f);
-+ mdio_write(tp, 0x18, 0x9bfb);
-+ mdio_write(tp, 0x1f, 0x0005);
-+ mdio_write(tp, 0x07, 0x0000);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ }
-+ mdio_write(tp, 0x1f, 0x0005);
-+ mdio_write(tp, 0x05, 0xfff6);
-+ mdio_write(tp, 0x06, 0x0080);
-+ gphy_val = mdio_read(tp, 0x00);
-+ gphy_val &= ~(BIT_7);
-+ mdio_write(tp, 0x00, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0002);
-+ gphy_val = mdio_read(tp, 0x08);
-+ gphy_val &= ~(BIT_7);
-+ mdio_write(tp, 0x08, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0023);
-+ mdio_write(tp, 0x16, 0x0306);
-+ mdio_write(tp, 0x16, 0x0307);
-+ mdio_write(tp, 0x15, 0x000e);
-+ mdio_write(tp, 0x19, 0x000a);
-+ mdio_write(tp, 0x15, 0x0010);
-+ mdio_write(tp, 0x19, 0x0008);
-+ mdio_write(tp, 0x15, 0x0018);
-+ mdio_write(tp, 0x19, 0x4801);
-+ mdio_write(tp, 0x15, 0x0019);
-+ mdio_write(tp, 0x19, 0x6801);
-+ mdio_write(tp, 0x15, 0x001a);
-+ mdio_write(tp, 0x19, 0x66a1);
-+ mdio_write(tp, 0x15, 0x001f);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0020);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0021);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0022);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0023);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0024);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0025);
-+ mdio_write(tp, 0x19, 0x64a1);
-+ mdio_write(tp, 0x15, 0x0026);
-+ mdio_write(tp, 0x19, 0x40ea);
-+ mdio_write(tp, 0x15, 0x0027);
-+ mdio_write(tp, 0x19, 0x4503);
-+ mdio_write(tp, 0x15, 0x0028);
-+ mdio_write(tp, 0x19, 0x9f00);
-+ mdio_write(tp, 0x15, 0x0029);
-+ mdio_write(tp, 0x19, 0xa631);
-+ mdio_write(tp, 0x15, 0x002a);
-+ mdio_write(tp, 0x19, 0x9717);
-+ mdio_write(tp, 0x15, 0x002b);
-+ mdio_write(tp, 0x19, 0x302c);
-+ mdio_write(tp, 0x15, 0x002c);
-+ mdio_write(tp, 0x19, 0x4802);
-+ mdio_write(tp, 0x15, 0x002d);
-+ mdio_write(tp, 0x19, 0x58da);
-+ mdio_write(tp, 0x15, 0x002e);
-+ mdio_write(tp, 0x19, 0x400d);
-+ mdio_write(tp, 0x15, 0x002f);
-+ mdio_write(tp, 0x19, 0x4488);
-+ mdio_write(tp, 0x15, 0x0030);
-+ mdio_write(tp, 0x19, 0x9e00);
-+ mdio_write(tp, 0x15, 0x0031);
-+ mdio_write(tp, 0x19, 0x63c8);
-+ mdio_write(tp, 0x15, 0x0032);
-+ mdio_write(tp, 0x19, 0x6481);
-+ mdio_write(tp, 0x15, 0x0033);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0034);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0035);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0036);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0037);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0038);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0039);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x003a);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x003b);
-+ mdio_write(tp, 0x19, 0x63e8);
-+ mdio_write(tp, 0x15, 0x003c);
-+ mdio_write(tp, 0x19, 0x7d00);
-+ mdio_write(tp, 0x15, 0x003d);
-+ mdio_write(tp, 0x19, 0x59d4);
-+ mdio_write(tp, 0x15, 0x003e);
-+ mdio_write(tp, 0x19, 0x63f8);
-+ mdio_write(tp, 0x15, 0x0040);
-+ mdio_write(tp, 0x19, 0x64a1);
-+ mdio_write(tp, 0x15, 0x0041);
-+ mdio_write(tp, 0x19, 0x30de);
-+ mdio_write(tp, 0x15, 0x0044);
-+ mdio_write(tp, 0x19, 0x480f);
-+ mdio_write(tp, 0x15, 0x0045);
-+ mdio_write(tp, 0x19, 0x6800);
-+ mdio_write(tp, 0x15, 0x0046);
-+ mdio_write(tp, 0x19, 0x6680);
-+ mdio_write(tp, 0x15, 0x0047);
-+ mdio_write(tp, 0x19, 0x7c10);
-+ mdio_write(tp, 0x15, 0x0048);
-+ mdio_write(tp, 0x19, 0x63c8);
-+ mdio_write(tp, 0x15, 0x0049);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004a);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004b);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004c);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004d);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004e);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004f);
-+ mdio_write(tp, 0x19, 0x40ea);
-+ mdio_write(tp, 0x15, 0x0050);
-+ mdio_write(tp, 0x19, 0x4503);
-+ mdio_write(tp, 0x15, 0x0051);
-+ mdio_write(tp, 0x19, 0x58ca);
-+ mdio_write(tp, 0x15, 0x0052);
-+ mdio_write(tp, 0x19, 0x63c8);
-+ mdio_write(tp, 0x15, 0x0053);
-+ mdio_write(tp, 0x19, 0x63d8);
-+ mdio_write(tp, 0x15, 0x0054);
-+ mdio_write(tp, 0x19, 0x66a0);
-+ mdio_write(tp, 0x15, 0x0055);
-+ mdio_write(tp, 0x19, 0x9f00);
-+ mdio_write(tp, 0x15, 0x0056);
-+ mdio_write(tp, 0x19, 0x3000);
-+ mdio_write(tp, 0x15, 0x006E);
-+ mdio_write(tp, 0x19, 0x9afa);
-+ mdio_write(tp, 0x15, 0x00a1);
-+ mdio_write(tp, 0x19, 0x3044);
-+ mdio_write(tp, 0x15, 0x00ab);
-+ mdio_write(tp, 0x19, 0x5820);
-+ mdio_write(tp, 0x15, 0x00ac);
-+ mdio_write(tp, 0x19, 0x5e04);
-+ mdio_write(tp, 0x15, 0x00ad);
-+ mdio_write(tp, 0x19, 0xb60c);
-+ mdio_write(tp, 0x15, 0x00af);
-+ mdio_write(tp, 0x19, 0x000a);
-+ mdio_write(tp, 0x15, 0x00b2);
-+ mdio_write(tp, 0x19, 0x30b9);
-+ mdio_write(tp, 0x15, 0x00b9);
-+ mdio_write(tp, 0x19, 0x4408);
-+ mdio_write(tp, 0x15, 0x00ba);
-+ mdio_write(tp, 0x19, 0x480b);
-+ mdio_write(tp, 0x15, 0x00bb);
-+ mdio_write(tp, 0x19, 0x5e00);
-+ mdio_write(tp, 0x15, 0x00bc);
-+ mdio_write(tp, 0x19, 0x405f);
-+ mdio_write(tp, 0x15, 0x00bd);
-+ mdio_write(tp, 0x19, 0x4448);
-+ mdio_write(tp, 0x15, 0x00be);
-+ mdio_write(tp, 0x19, 0x4020);
-+ mdio_write(tp, 0x15, 0x00bf);
-+ mdio_write(tp, 0x19, 0x4468);
-+ mdio_write(tp, 0x15, 0x00c0);
-+ mdio_write(tp, 0x19, 0x9c02);
-+ mdio_write(tp, 0x15, 0x00c1);
-+ mdio_write(tp, 0x19, 0x58a0);
-+ mdio_write(tp, 0x15, 0x00c2);
-+ mdio_write(tp, 0x19, 0xb605);
-+ mdio_write(tp, 0x15, 0x00c3);
-+ mdio_write(tp, 0x19, 0xc0d3);
-+ mdio_write(tp, 0x15, 0x00c4);
-+ mdio_write(tp, 0x19, 0x00e6);
-+ mdio_write(tp, 0x15, 0x00c5);
-+ mdio_write(tp, 0x19, 0xdaec);
-+ mdio_write(tp, 0x15, 0x00c6);
-+ mdio_write(tp, 0x19, 0x00fa);
-+ mdio_write(tp, 0x15, 0x00c7);
-+ mdio_write(tp, 0x19, 0x9df9);
-+ mdio_write(tp, 0x15, 0x00c8);
-+ mdio_write(tp, 0x19, 0x307a);
-+ mdio_write(tp, 0x15, 0x0112);
-+ mdio_write(tp, 0x19, 0x6421);
-+ mdio_write(tp, 0x15, 0x0113);
-+ mdio_write(tp, 0x19, 0x7c08);
-+ mdio_write(tp, 0x15, 0x0114);
-+ mdio_write(tp, 0x19, 0x63f0);
-+ mdio_write(tp, 0x15, 0x0115);
-+ mdio_write(tp, 0x19, 0x4003);
-+ mdio_write(tp, 0x15, 0x0116);
-+ mdio_write(tp, 0x19, 0x4418);
-+ mdio_write(tp, 0x15, 0x0117);
-+ mdio_write(tp, 0x19, 0x9b00);
-+ mdio_write(tp, 0x15, 0x0118);
-+ mdio_write(tp, 0x19, 0x6461);
-+ mdio_write(tp, 0x15, 0x0119);
-+ mdio_write(tp, 0x19, 0x64e1);
-+ mdio_write(tp, 0x15, 0x011a);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0150);
-+ mdio_write(tp, 0x19, 0x7c80);
-+ mdio_write(tp, 0x15, 0x0151);
-+ mdio_write(tp, 0x19, 0x6461);
-+ mdio_write(tp, 0x15, 0x0152);
-+ mdio_write(tp, 0x19, 0x4003);
-+ mdio_write(tp, 0x15, 0x0153);
-+ mdio_write(tp, 0x19, 0x4540);
-+ mdio_write(tp, 0x15, 0x0154);
-+ mdio_write(tp, 0x19, 0x9f00);
-+ mdio_write(tp, 0x15, 0x0155);
-+ mdio_write(tp, 0x19, 0x9d00);
-+ mdio_write(tp, 0x15, 0x0156);
-+ mdio_write(tp, 0x19, 0x7c40);
-+ mdio_write(tp, 0x15, 0x0157);
-+ mdio_write(tp, 0x19, 0x6421);
-+ mdio_write(tp, 0x15, 0x0158);
-+ mdio_write(tp, 0x19, 0x7c80);
-+ mdio_write(tp, 0x15, 0x0159);
-+ mdio_write(tp, 0x19, 0x64a1);
-+ mdio_write(tp, 0x15, 0x015a);
-+ mdio_write(tp, 0x19, 0x30fe);
-+ mdio_write(tp, 0x15, 0x021e);
-+ mdio_write(tp, 0x19, 0x5410);
-+ mdio_write(tp, 0x15, 0x0225);
-+ mdio_write(tp, 0x19, 0x5400);
-+ mdio_write(tp, 0x15, 0x023D);
-+ mdio_write(tp, 0x19, 0x4050);
-+ mdio_write(tp, 0x15, 0x0295);
-+ mdio_write(tp, 0x19, 0x6c08);
-+ mdio_write(tp, 0x15, 0x02bd);
-+ mdio_write(tp, 0x19, 0xa523);
-+ mdio_write(tp, 0x15, 0x02be);
-+ mdio_write(tp, 0x19, 0x32ca);
-+ mdio_write(tp, 0x15, 0x02ca);
-+ mdio_write(tp, 0x19, 0x48b3);
-+ mdio_write(tp, 0x15, 0x02cb);
-+ mdio_write(tp, 0x19, 0x4020);
-+ mdio_write(tp, 0x15, 0x02cc);
-+ mdio_write(tp, 0x19, 0x4823);
-+ mdio_write(tp, 0x15, 0x02cd);
-+ mdio_write(tp, 0x19, 0x4510);
-+ mdio_write(tp, 0x15, 0x02ce);
-+ mdio_write(tp, 0x19, 0xb63a);
-+ mdio_write(tp, 0x15, 0x02cf);
-+ mdio_write(tp, 0x19, 0x7dc8);
-+ mdio_write(tp, 0x15, 0x02d6);
-+ mdio_write(tp, 0x19, 0x9bf8);
-+ mdio_write(tp, 0x15, 0x02d8);
-+ mdio_write(tp, 0x19, 0x85f6);
-+ mdio_write(tp, 0x15, 0x02d9);
-+ mdio_write(tp, 0x19, 0x32e0);
-+ mdio_write(tp, 0x15, 0x02e0);
-+ mdio_write(tp, 0x19, 0x4834);
-+ mdio_write(tp, 0x15, 0x02e1);
-+ mdio_write(tp, 0x19, 0x6c08);
-+ mdio_write(tp, 0x15, 0x02e2);
-+ mdio_write(tp, 0x19, 0x4020);
-+ mdio_write(tp, 0x15, 0x02e3);
-+ mdio_write(tp, 0x19, 0x4824);
-+ mdio_write(tp, 0x15, 0x02e4);
-+ mdio_write(tp, 0x19, 0x4520);
-+ mdio_write(tp, 0x15, 0x02e5);
-+ mdio_write(tp, 0x19, 0x4008);
-+ mdio_write(tp, 0x15, 0x02e6);
-+ mdio_write(tp, 0x19, 0x4560);
-+ mdio_write(tp, 0x15, 0x02e7);
-+ mdio_write(tp, 0x19, 0x9d04);
-+ mdio_write(tp, 0x15, 0x02e8);
-+ mdio_write(tp, 0x19, 0x48c4);
-+ mdio_write(tp, 0x15, 0x02e9);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x02ea);
-+ mdio_write(tp, 0x19, 0x4844);
-+ mdio_write(tp, 0x15, 0x02eb);
-+ mdio_write(tp, 0x19, 0x7dc8);
-+ mdio_write(tp, 0x15, 0x02f0);
-+ mdio_write(tp, 0x19, 0x9cf7);
-+ mdio_write(tp, 0x15, 0x02f1);
-+ mdio_write(tp, 0x19, 0xdf94);
-+ mdio_write(tp, 0x15, 0x02f2);
-+ mdio_write(tp, 0x19, 0x0002);
-+ mdio_write(tp, 0x15, 0x02f3);
-+ mdio_write(tp, 0x19, 0x6810);
-+ mdio_write(tp, 0x15, 0x02f4);
-+ mdio_write(tp, 0x19, 0xb614);
-+ mdio_write(tp, 0x15, 0x02f5);
-+ mdio_write(tp, 0x19, 0xc42b);
-+ mdio_write(tp, 0x15, 0x02f6);
-+ mdio_write(tp, 0x19, 0x00d4);
-+ mdio_write(tp, 0x15, 0x02f7);
-+ mdio_write(tp, 0x19, 0xc455);
-+ mdio_write(tp, 0x15, 0x02f8);
-+ mdio_write(tp, 0x19, 0x0093);
-+ mdio_write(tp, 0x15, 0x02f9);
-+ mdio_write(tp, 0x19, 0x92ee);
-+ mdio_write(tp, 0x15, 0x02fa);
-+ mdio_write(tp, 0x19, 0xefed);
-+ mdio_write(tp, 0x15, 0x02fb);
-+ mdio_write(tp, 0x19, 0x3312);
-+ mdio_write(tp, 0x15, 0x0312);
-+ mdio_write(tp, 0x19, 0x49b5);
-+ mdio_write(tp, 0x15, 0x0313);
-+ mdio_write(tp, 0x19, 0x7d00);
-+ mdio_write(tp, 0x15, 0x0314);
-+ mdio_write(tp, 0x19, 0x4d00);
-+ mdio_write(tp, 0x15, 0x0315);
-+ mdio_write(tp, 0x19, 0x6810);
-+ mdio_write(tp, 0x15, 0x031e);
-+ mdio_write(tp, 0x19, 0x404f);
-+ mdio_write(tp, 0x15, 0x031f);
-+ mdio_write(tp, 0x19, 0x44c8);
-+ mdio_write(tp, 0x15, 0x0320);
-+ mdio_write(tp, 0x19, 0xd64f);
-+ mdio_write(tp, 0x15, 0x0321);
-+ mdio_write(tp, 0x19, 0x00e7);
-+ mdio_write(tp, 0x15, 0x0322);
-+ mdio_write(tp, 0x19, 0x7c08);
-+ mdio_write(tp, 0x15, 0x0323);
-+ mdio_write(tp, 0x19, 0x8203);
-+ mdio_write(tp, 0x15, 0x0324);
-+ mdio_write(tp, 0x19, 0x4d48);
-+ mdio_write(tp, 0x15, 0x0325);
-+ mdio_write(tp, 0x19, 0x3327);
-+ mdio_write(tp, 0x15, 0x0326);
-+ mdio_write(tp, 0x19, 0x4d40);
-+ mdio_write(tp, 0x15, 0x0327);
-+ mdio_write(tp, 0x19, 0xc8d7);
-+ mdio_write(tp, 0x15, 0x0328);
-+ mdio_write(tp, 0x19, 0x0003);
-+ mdio_write(tp, 0x15, 0x0329);
-+ mdio_write(tp, 0x19, 0x7c20);
-+ mdio_write(tp, 0x15, 0x032a);
-+ mdio_write(tp, 0x19, 0x4c20);
-+ mdio_write(tp, 0x15, 0x032b);
-+ mdio_write(tp, 0x19, 0xc8ed);
-+ mdio_write(tp, 0x15, 0x032c);
-+ mdio_write(tp, 0x19, 0x00f4);
-+ mdio_write(tp, 0x15, 0x032d);
-+ mdio_write(tp, 0x19, 0x82b3);
-+ mdio_write(tp, 0x15, 0x032e);
-+ mdio_write(tp, 0x19, 0xd11d);
-+ mdio_write(tp, 0x15, 0x032f);
-+ mdio_write(tp, 0x19, 0x00b1);
-+ mdio_write(tp, 0x15, 0x0330);
-+ mdio_write(tp, 0x19, 0xde18);
-+ mdio_write(tp, 0x15, 0x0331);
-+ mdio_write(tp, 0x19, 0x0008);
-+ mdio_write(tp, 0x15, 0x0332);
-+ mdio_write(tp, 0x19, 0x91ee);
-+ mdio_write(tp, 0x15, 0x0333);
-+ mdio_write(tp, 0x19, 0x3339);
-+ mdio_write(tp, 0x15, 0x033a);
-+ mdio_write(tp, 0x19, 0x4064);
-+ mdio_write(tp, 0x15, 0x0340);
-+ mdio_write(tp, 0x19, 0x9e06);
-+ mdio_write(tp, 0x15, 0x0341);
-+ mdio_write(tp, 0x19, 0x7c08);
-+ mdio_write(tp, 0x15, 0x0342);
-+ mdio_write(tp, 0x19, 0x8203);
-+ mdio_write(tp, 0x15, 0x0343);
-+ mdio_write(tp, 0x19, 0x4d48);
-+ mdio_write(tp, 0x15, 0x0344);
-+ mdio_write(tp, 0x19, 0x3346);
-+ mdio_write(tp, 0x15, 0x0345);
-+ mdio_write(tp, 0x19, 0x4d40);
-+ mdio_write(tp, 0x15, 0x0346);
-+ mdio_write(tp, 0x19, 0xd11d);
-+ mdio_write(tp, 0x15, 0x0347);
-+ mdio_write(tp, 0x19, 0x0099);
-+ mdio_write(tp, 0x15, 0x0348);
-+ mdio_write(tp, 0x19, 0xbb17);
-+ mdio_write(tp, 0x15, 0x0349);
-+ mdio_write(tp, 0x19, 0x8102);
-+ mdio_write(tp, 0x15, 0x034a);
-+ mdio_write(tp, 0x19, 0x334d);
-+ mdio_write(tp, 0x15, 0x034b);
-+ mdio_write(tp, 0x19, 0xa22c);
-+ mdio_write(tp, 0x15, 0x034c);
-+ mdio_write(tp, 0x19, 0x3397);
-+ mdio_write(tp, 0x15, 0x034d);
-+ mdio_write(tp, 0x19, 0x91f2);
-+ mdio_write(tp, 0x15, 0x034e);
-+ mdio_write(tp, 0x19, 0xc218);
-+ mdio_write(tp, 0x15, 0x034f);
-+ mdio_write(tp, 0x19, 0x00f0);
-+ mdio_write(tp, 0x15, 0x0350);
-+ mdio_write(tp, 0x19, 0x3397);
-+ mdio_write(tp, 0x15, 0x0351);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0364);
-+ mdio_write(tp, 0x19, 0xbc05);
-+ mdio_write(tp, 0x15, 0x0367);
-+ mdio_write(tp, 0x19, 0xa1fc);
-+ mdio_write(tp, 0x15, 0x0368);
-+ mdio_write(tp, 0x19, 0x3377);
-+ mdio_write(tp, 0x15, 0x0369);
-+ mdio_write(tp, 0x19, 0x328b);
-+ mdio_write(tp, 0x15, 0x036a);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0377);
-+ mdio_write(tp, 0x19, 0x4b97);
-+ mdio_write(tp, 0x15, 0x0378);
-+ mdio_write(tp, 0x19, 0x6818);
-+ mdio_write(tp, 0x15, 0x0379);
-+ mdio_write(tp, 0x19, 0x4b07);
-+ mdio_write(tp, 0x15, 0x037a);
-+ mdio_write(tp, 0x19, 0x40ac);
-+ mdio_write(tp, 0x15, 0x037b);
-+ mdio_write(tp, 0x19, 0x4445);
-+ mdio_write(tp, 0x15, 0x037c);
-+ mdio_write(tp, 0x19, 0x404e);
-+ mdio_write(tp, 0x15, 0x037d);
-+ mdio_write(tp, 0x19, 0x4461);
-+ mdio_write(tp, 0x15, 0x037e);
-+ mdio_write(tp, 0x19, 0x9c09);
-+ mdio_write(tp, 0x15, 0x037f);
-+ mdio_write(tp, 0x19, 0x63da);
-+ mdio_write(tp, 0x15, 0x0380);
-+ mdio_write(tp, 0x19, 0x5440);
-+ mdio_write(tp, 0x15, 0x0381);
-+ mdio_write(tp, 0x19, 0x4b98);
-+ mdio_write(tp, 0x15, 0x0382);
-+ mdio_write(tp, 0x19, 0x7c60);
-+ mdio_write(tp, 0x15, 0x0383);
-+ mdio_write(tp, 0x19, 0x4c00);
-+ mdio_write(tp, 0x15, 0x0384);
-+ mdio_write(tp, 0x19, 0x4b08);
-+ mdio_write(tp, 0x15, 0x0385);
-+ mdio_write(tp, 0x19, 0x63d8);
-+ mdio_write(tp, 0x15, 0x0386);
-+ mdio_write(tp, 0x19, 0x338d);
-+ mdio_write(tp, 0x15, 0x0387);
-+ mdio_write(tp, 0x19, 0xd64f);
-+ mdio_write(tp, 0x15, 0x0388);
-+ mdio_write(tp, 0x19, 0x0080);
-+ mdio_write(tp, 0x15, 0x0389);
-+ mdio_write(tp, 0x19, 0x820c);
-+ mdio_write(tp, 0x15, 0x038a);
-+ mdio_write(tp, 0x19, 0xa10b);
-+ mdio_write(tp, 0x15, 0x038b);
-+ mdio_write(tp, 0x19, 0x9df3);
-+ mdio_write(tp, 0x15, 0x038c);
-+ mdio_write(tp, 0x19, 0x3395);
-+ mdio_write(tp, 0x15, 0x038d);
-+ mdio_write(tp, 0x19, 0xd64f);
-+ mdio_write(tp, 0x15, 0x038e);
-+ mdio_write(tp, 0x19, 0x00f9);
-+ mdio_write(tp, 0x15, 0x038f);
-+ mdio_write(tp, 0x19, 0xc017);
-+ mdio_write(tp, 0x15, 0x0390);
-+ mdio_write(tp, 0x19, 0x0005);
-+ mdio_write(tp, 0x15, 0x0391);
-+ mdio_write(tp, 0x19, 0x6c0b);
-+ mdio_write(tp, 0x15, 0x0392);
-+ mdio_write(tp, 0x19, 0xa103);
-+ mdio_write(tp, 0x15, 0x0393);
-+ mdio_write(tp, 0x19, 0x6c08);
-+ mdio_write(tp, 0x15, 0x0394);
-+ mdio_write(tp, 0x19, 0x9df9);
-+ mdio_write(tp, 0x15, 0x0395);
-+ mdio_write(tp, 0x19, 0x6c08);
-+ mdio_write(tp, 0x15, 0x0396);
-+ mdio_write(tp, 0x19, 0x3397);
-+ mdio_write(tp, 0x15, 0x0399);
-+ mdio_write(tp, 0x19, 0x6810);
-+ mdio_write(tp, 0x15, 0x03a4);
-+ mdio_write(tp, 0x19, 0x7c08);
-+ mdio_write(tp, 0x15, 0x03a5);
-+ mdio_write(tp, 0x19, 0x8203);
-+ mdio_write(tp, 0x15, 0x03a6);
-+ mdio_write(tp, 0x19, 0x4d08);
-+ mdio_write(tp, 0x15, 0x03a7);
-+ mdio_write(tp, 0x19, 0x33a9);
-+ mdio_write(tp, 0x15, 0x03a8);
-+ mdio_write(tp, 0x19, 0x4d00);
-+ mdio_write(tp, 0x15, 0x03a9);
-+ mdio_write(tp, 0x19, 0x9bfa);
-+ mdio_write(tp, 0x15, 0x03aa);
-+ mdio_write(tp, 0x19, 0x33b6);
-+ mdio_write(tp, 0x15, 0x03bb);
-+ mdio_write(tp, 0x19, 0x4056);
-+ mdio_write(tp, 0x15, 0x03bc);
-+ mdio_write(tp, 0x19, 0x44e9);
-+ mdio_write(tp, 0x15, 0x03bd);
-+ mdio_write(tp, 0x19, 0x405e);
-+ mdio_write(tp, 0x15, 0x03be);
-+ mdio_write(tp, 0x19, 0x44f8);
-+ mdio_write(tp, 0x15, 0x03bf);
-+ mdio_write(tp, 0x19, 0xd64f);
-+ mdio_write(tp, 0x15, 0x03c0);
-+ mdio_write(tp, 0x19, 0x0037);
-+ mdio_write(tp, 0x15, 0x03c1);
-+ mdio_write(tp, 0x19, 0xbd37);
-+ mdio_write(tp, 0x15, 0x03c2);
-+ mdio_write(tp, 0x19, 0x9cfd);
-+ mdio_write(tp, 0x15, 0x03c3);
-+ mdio_write(tp, 0x19, 0xc639);
-+ mdio_write(tp, 0x15, 0x03c4);
-+ mdio_write(tp, 0x19, 0x0011);
-+ mdio_write(tp, 0x15, 0x03c5);
-+ mdio_write(tp, 0x19, 0x9b03);
-+ mdio_write(tp, 0x15, 0x03c6);
-+ mdio_write(tp, 0x19, 0x7c01);
-+ mdio_write(tp, 0x15, 0x03c7);
-+ mdio_write(tp, 0x19, 0x4c01);
-+ mdio_write(tp, 0x15, 0x03c8);
-+ mdio_write(tp, 0x19, 0x9e03);
-+ mdio_write(tp, 0x15, 0x03c9);
-+ mdio_write(tp, 0x19, 0x7c20);
-+ mdio_write(tp, 0x15, 0x03ca);
-+ mdio_write(tp, 0x19, 0x4c20);
-+ mdio_write(tp, 0x15, 0x03cb);
-+ mdio_write(tp, 0x19, 0x9af4);
-+ mdio_write(tp, 0x15, 0x03cc);
-+ mdio_write(tp, 0x19, 0x7c12);
-+ mdio_write(tp, 0x15, 0x03cd);
-+ mdio_write(tp, 0x19, 0x4c52);
-+ mdio_write(tp, 0x15, 0x03ce);
-+ mdio_write(tp, 0x19, 0x4470);
-+ mdio_write(tp, 0x15, 0x03cf);
-+ mdio_write(tp, 0x19, 0x7c12);
-+ mdio_write(tp, 0x15, 0x03d0);
-+ mdio_write(tp, 0x19, 0x4c40);
-+ mdio_write(tp, 0x15, 0x03d1);
-+ mdio_write(tp, 0x19, 0x33bf);
-+ mdio_write(tp, 0x15, 0x03d6);
-+ mdio_write(tp, 0x19, 0x4047);
-+ mdio_write(tp, 0x15, 0x03d7);
-+ mdio_write(tp, 0x19, 0x4469);
-+ mdio_write(tp, 0x15, 0x03d8);
-+ mdio_write(tp, 0x19, 0x492b);
-+ mdio_write(tp, 0x15, 0x03d9);
-+ mdio_write(tp, 0x19, 0x4479);
-+ mdio_write(tp, 0x15, 0x03da);
-+ mdio_write(tp, 0x19, 0x7c09);
-+ mdio_write(tp, 0x15, 0x03db);
-+ mdio_write(tp, 0x19, 0x8203);
-+ mdio_write(tp, 0x15, 0x03dc);
-+ mdio_write(tp, 0x19, 0x4d48);
-+ mdio_write(tp, 0x15, 0x03dd);
-+ mdio_write(tp, 0x19, 0x33df);
-+ mdio_write(tp, 0x15, 0x03de);
-+ mdio_write(tp, 0x19, 0x4d40);
-+ mdio_write(tp, 0x15, 0x03df);
-+ mdio_write(tp, 0x19, 0xd64f);
-+ mdio_write(tp, 0x15, 0x03e0);
-+ mdio_write(tp, 0x19, 0x0017);
-+ mdio_write(tp, 0x15, 0x03e1);
-+ mdio_write(tp, 0x19, 0xbd17);
-+ mdio_write(tp, 0x15, 0x03e2);
-+ mdio_write(tp, 0x19, 0x9b03);
-+ mdio_write(tp, 0x15, 0x03e3);
-+ mdio_write(tp, 0x19, 0x7c20);
-+ mdio_write(tp, 0x15, 0x03e4);
-+ mdio_write(tp, 0x19, 0x4c20);
-+ mdio_write(tp, 0x15, 0x03e5);
-+ mdio_write(tp, 0x19, 0x88f5);
-+ mdio_write(tp, 0x15, 0x03e6);
-+ mdio_write(tp, 0x19, 0xc428);
-+ mdio_write(tp, 0x15, 0x03e7);
-+ mdio_write(tp, 0x19, 0x0008);
-+ mdio_write(tp, 0x15, 0x03e8);
-+ mdio_write(tp, 0x19, 0x9af2);
-+ mdio_write(tp, 0x15, 0x03e9);
-+ mdio_write(tp, 0x19, 0x7c12);
-+ mdio_write(tp, 0x15, 0x03ea);
-+ mdio_write(tp, 0x19, 0x4c52);
-+ mdio_write(tp, 0x15, 0x03eb);
-+ mdio_write(tp, 0x19, 0x4470);
-+ mdio_write(tp, 0x15, 0x03ec);
-+ mdio_write(tp, 0x19, 0x7c12);
-+ mdio_write(tp, 0x15, 0x03ed);
-+ mdio_write(tp, 0x19, 0x4c40);
-+ mdio_write(tp, 0x15, 0x03ee);
-+ mdio_write(tp, 0x19, 0x33da);
-+ mdio_write(tp, 0x15, 0x03ef);
-+ mdio_write(tp, 0x19, 0x3312);
-+ mdio_write(tp, 0x16, 0x0306);
-+ mdio_write(tp, 0x16, 0x0300);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x17, 0x2179);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0040);
-+ mdio_write(tp, 0x18, 0x0645);
-+ mdio_write(tp, 0x19, 0xe200);
-+ mdio_write(tp, 0x18, 0x0655);
-+ mdio_write(tp, 0x19, 0x9000);
-+ mdio_write(tp, 0x18, 0x0d05);
-+ mdio_write(tp, 0x19, 0xbe00);
-+ mdio_write(tp, 0x18, 0x0d15);
-+ mdio_write(tp, 0x19, 0xd300);
-+ mdio_write(tp, 0x18, 0x0d25);
-+ mdio_write(tp, 0x19, 0xfe00);
-+ mdio_write(tp, 0x18, 0x0d35);
-+ mdio_write(tp, 0x19, 0x4000);
-+ mdio_write(tp, 0x18, 0x0d45);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x0d55);
-+ mdio_write(tp, 0x19, 0x1000);
-+ mdio_write(tp, 0x18, 0x0d65);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x0d75);
-+ mdio_write(tp, 0x19, 0x8200);
-+ mdio_write(tp, 0x18, 0x0d85);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x0d95);
-+ mdio_write(tp, 0x19, 0x7000);
-+ mdio_write(tp, 0x18, 0x0da5);
-+ mdio_write(tp, 0x19, 0x0f00);
-+ mdio_write(tp, 0x18, 0x0db5);
-+ mdio_write(tp, 0x19, 0x0100);
-+ mdio_write(tp, 0x18, 0x0dc5);
-+ mdio_write(tp, 0x19, 0x9b00);
-+ mdio_write(tp, 0x18, 0x0dd5);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x0de5);
-+ mdio_write(tp, 0x19, 0xe000);
-+ mdio_write(tp, 0x18, 0x0df5);
-+ mdio_write(tp, 0x19, 0xef00);
-+ mdio_write(tp, 0x18, 0x16d5);
-+ mdio_write(tp, 0x19, 0xe200);
-+ mdio_write(tp, 0x18, 0x16e5);
-+ mdio_write(tp, 0x19, 0xab00);
-+ mdio_write(tp, 0x18, 0x2904);
-+ mdio_write(tp, 0x19, 0x4000);
-+ mdio_write(tp, 0x18, 0x2914);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x2924);
-+ mdio_write(tp, 0x19, 0x0100);
-+ mdio_write(tp, 0x18, 0x2934);
-+ mdio_write(tp, 0x19, 0x2000);
-+ mdio_write(tp, 0x18, 0x2944);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2954);
-+ mdio_write(tp, 0x19, 0x4600);
-+ mdio_write(tp, 0x18, 0x2964);
-+ mdio_write(tp, 0x19, 0xfc00);
-+ mdio_write(tp, 0x18, 0x2974);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2984);
-+ mdio_write(tp, 0x19, 0x5000);
-+ mdio_write(tp, 0x18, 0x2994);
-+ mdio_write(tp, 0x19, 0x9d00);
-+ mdio_write(tp, 0x18, 0x29a4);
-+ mdio_write(tp, 0x19, 0xff00);
-+ mdio_write(tp, 0x18, 0x29b4);
-+ mdio_write(tp, 0x19, 0x4000);
-+ mdio_write(tp, 0x18, 0x29c4);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x29d4);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x29e4);
-+ mdio_write(tp, 0x19, 0x2000);
-+ mdio_write(tp, 0x18, 0x29f4);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2a04);
-+ mdio_write(tp, 0x19, 0xe600);
-+ mdio_write(tp, 0x18, 0x2a14);
-+ mdio_write(tp, 0x19, 0xff00);
-+ mdio_write(tp, 0x18, 0x2a24);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2a34);
-+ mdio_write(tp, 0x19, 0x5000);
-+ mdio_write(tp, 0x18, 0x2a44);
-+ mdio_write(tp, 0x19, 0x8500);
-+ mdio_write(tp, 0x18, 0x2a54);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x2a64);
-+ mdio_write(tp, 0x19, 0xac00);
-+ mdio_write(tp, 0x18, 0x2a74);
-+ mdio_write(tp, 0x19, 0x0800);
-+ mdio_write(tp, 0x18, 0x2a84);
-+ mdio_write(tp, 0x19, 0xfc00);
-+ mdio_write(tp, 0x18, 0x2a94);
-+ mdio_write(tp, 0x19, 0xe000);
-+ mdio_write(tp, 0x18, 0x2aa4);
-+ mdio_write(tp, 0x19, 0x7400);
-+ mdio_write(tp, 0x18, 0x2ab4);
-+ mdio_write(tp, 0x19, 0x4000);
-+ mdio_write(tp, 0x18, 0x2ac4);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x2ad4);
-+ mdio_write(tp, 0x19, 0x0100);
-+ mdio_write(tp, 0x18, 0x2ae4);
-+ mdio_write(tp, 0x19, 0xff00);
-+ mdio_write(tp, 0x18, 0x2af4);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2b04);
-+ mdio_write(tp, 0x19, 0x4400);
-+ mdio_write(tp, 0x18, 0x2b14);
-+ mdio_write(tp, 0x19, 0xfc00);
-+ mdio_write(tp, 0x18, 0x2b24);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2b34);
-+ mdio_write(tp, 0x19, 0x4000);
-+ mdio_write(tp, 0x18, 0x2b44);
-+ mdio_write(tp, 0x19, 0x9d00);
-+ mdio_write(tp, 0x18, 0x2b54);
-+ mdio_write(tp, 0x19, 0xff00);
-+ mdio_write(tp, 0x18, 0x2b64);
-+ mdio_write(tp, 0x19, 0x4000);
-+ mdio_write(tp, 0x18, 0x2b74);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x2b84);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2b94);
-+ mdio_write(tp, 0x19, 0xff00);
-+ mdio_write(tp, 0x18, 0x2ba4);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2bb4);
-+ mdio_write(tp, 0x19, 0xfc00);
-+ mdio_write(tp, 0x18, 0x2bc4);
-+ mdio_write(tp, 0x19, 0xff00);
-+ mdio_write(tp, 0x18, 0x2bd4);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2be4);
-+ mdio_write(tp, 0x19, 0x4000);
-+ mdio_write(tp, 0x18, 0x2bf4);
-+ mdio_write(tp, 0x19, 0x8900);
-+ mdio_write(tp, 0x18, 0x2c04);
-+ mdio_write(tp, 0x19, 0x8300);
-+ mdio_write(tp, 0x18, 0x2c14);
-+ mdio_write(tp, 0x19, 0xe000);
-+ mdio_write(tp, 0x18, 0x2c24);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x18, 0x2c34);
-+ mdio_write(tp, 0x19, 0xac00);
-+ mdio_write(tp, 0x18, 0x2c44);
-+ mdio_write(tp, 0x19, 0x0800);
-+ mdio_write(tp, 0x18, 0x2c54);
-+ mdio_write(tp, 0x19, 0xfa00);
-+ mdio_write(tp, 0x18, 0x2c64);
-+ mdio_write(tp, 0x19, 0xe100);
-+ mdio_write(tp, 0x18, 0x2c74);
-+ mdio_write(tp, 0x19, 0x7f00);
-+ mdio_write(tp, 0x18, 0x0001);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x17, 0x2100);
-+ mdio_write(tp, 0x1f, 0x0005);
-+ mdio_write(tp, 0x05, 0xfff6);
-+ mdio_write(tp, 0x06, 0x0080);
-+ mdio_write(tp, 0x05, 0x8b88);
-+ mdio_write(tp, 0x06, 0x0000);
-+ mdio_write(tp, 0x06, 0x0000);
-+ mdio_write(tp, 0x06, 0x0000);
-+ mdio_write(tp, 0x06, 0x0000);
-+ mdio_write(tp, 0x05, 0x8000);
-+ mdio_write(tp, 0x06, 0xd480);
-+ mdio_write(tp, 0x06, 0xc1e4);
-+ mdio_write(tp, 0x06, 0x8b9a);
-+ mdio_write(tp, 0x06, 0xe58b);
-+ mdio_write(tp, 0x06, 0x9bee);
-+ mdio_write(tp, 0x06, 0x8b83);
-+ mdio_write(tp, 0x06, 0x41bf);
-+ mdio_write(tp, 0x06, 0x8b88);
-+ mdio_write(tp, 0x06, 0xec00);
-+ mdio_write(tp, 0x06, 0x19a9);
-+ mdio_write(tp, 0x06, 0x8b90);
-+ mdio_write(tp, 0x06, 0xf9ee);
-+ mdio_write(tp, 0x06, 0xfff6);
-+ mdio_write(tp, 0x06, 0x00ee);
-+ mdio_write(tp, 0x06, 0xfff7);
-+ mdio_write(tp, 0x06, 0xffe0);
-+ mdio_write(tp, 0x06, 0xe140);
-+ mdio_write(tp, 0x06, 0xe1e1);
-+ mdio_write(tp, 0x06, 0x41f7);
-+ mdio_write(tp, 0x06, 0x2ff6);
-+ mdio_write(tp, 0x06, 0x28e4);
-+ mdio_write(tp, 0x06, 0xe140);
-+ mdio_write(tp, 0x06, 0xe5e1);
-+ mdio_write(tp, 0x06, 0x41f7);
-+ mdio_write(tp, 0x06, 0x0002);
-+ mdio_write(tp, 0x06, 0x020c);
-+ mdio_write(tp, 0x06, 0x0202);
-+ mdio_write(tp, 0x06, 0x1d02);
-+ mdio_write(tp, 0x06, 0x0230);
-+ mdio_write(tp, 0x06, 0x0202);
-+ mdio_write(tp, 0x06, 0x4002);
-+ mdio_write(tp, 0x06, 0x028b);
-+ mdio_write(tp, 0x06, 0x0280);
-+ mdio_write(tp, 0x06, 0x6c02);
-+ mdio_write(tp, 0x06, 0x8085);
-+ mdio_write(tp, 0x06, 0xe08b);
-+ mdio_write(tp, 0x06, 0x88e1);
-+ mdio_write(tp, 0x06, 0x8b89);
-+ mdio_write(tp, 0x06, 0x1e01);
-+ mdio_write(tp, 0x06, 0xe18b);
-+ mdio_write(tp, 0x06, 0x8a1e);
-+ mdio_write(tp, 0x06, 0x01e1);
-+ mdio_write(tp, 0x06, 0x8b8b);
-+ mdio_write(tp, 0x06, 0x1e01);
-+ mdio_write(tp, 0x06, 0xe18b);
-+ mdio_write(tp, 0x06, 0x8c1e);
-+ mdio_write(tp, 0x06, 0x01e1);
-+ mdio_write(tp, 0x06, 0x8b8d);
-+ mdio_write(tp, 0x06, 0x1e01);
-+ mdio_write(tp, 0x06, 0xe18b);
-+ mdio_write(tp, 0x06, 0x8e1e);
-+ mdio_write(tp, 0x06, 0x01a0);
-+ mdio_write(tp, 0x06, 0x00c7);
-+ mdio_write(tp, 0x06, 0xaec3);
-+ mdio_write(tp, 0x06, 0xf8e0);
-+ mdio_write(tp, 0x06, 0x8b8d);
-+ mdio_write(tp, 0x06, 0xad20);
-+ mdio_write(tp, 0x06, 0x10ee);
-+ mdio_write(tp, 0x06, 0x8b8d);
-+ mdio_write(tp, 0x06, 0x0002);
-+ mdio_write(tp, 0x06, 0x1310);
-+ mdio_write(tp, 0x06, 0x021f);
-+ mdio_write(tp, 0x06, 0x9d02);
-+ mdio_write(tp, 0x06, 0x1f0c);
-+ mdio_write(tp, 0x06, 0x0227);
-+ mdio_write(tp, 0x06, 0x49fc);
-+ mdio_write(tp, 0x06, 0x04f8);
-+ mdio_write(tp, 0x06, 0xe08b);
-+ mdio_write(tp, 0x06, 0x8ead);
-+ mdio_write(tp, 0x06, 0x200b);
-+ mdio_write(tp, 0x06, 0xf620);
-+ mdio_write(tp, 0x06, 0xe48b);
-+ mdio_write(tp, 0x06, 0x8e02);
-+ mdio_write(tp, 0x06, 0x830e);
-+ mdio_write(tp, 0x06, 0x021b);
-+ mdio_write(tp, 0x06, 0x67ad);
-+ mdio_write(tp, 0x06, 0x2211);
-+ mdio_write(tp, 0x06, 0xf622);
-+ mdio_write(tp, 0x06, 0xe48b);
-+ mdio_write(tp, 0x06, 0x8e02);
-+ mdio_write(tp, 0x06, 0x2ba5);
-+ mdio_write(tp, 0x06, 0x022a);
-+ mdio_write(tp, 0x06, 0x2402);
-+ mdio_write(tp, 0x06, 0x80c6);
-+ mdio_write(tp, 0x06, 0x022a);
-+ mdio_write(tp, 0x06, 0xf0ad);
-+ mdio_write(tp, 0x06, 0x2511);
-+ mdio_write(tp, 0x06, 0xf625);
-+ mdio_write(tp, 0x06, 0xe48b);
-+ mdio_write(tp, 0x06, 0x8e02);
-+ mdio_write(tp, 0x06, 0x8226);
-+ mdio_write(tp, 0x06, 0x0204);
-+ mdio_write(tp, 0x06, 0x0302);
-+ mdio_write(tp, 0x06, 0x19cc);
-+ mdio_write(tp, 0x06, 0x022b);
-+ mdio_write(tp, 0x06, 0x5bfc);
-+ mdio_write(tp, 0x06, 0x04ee);
-+ mdio_write(tp, 0x06, 0x8b8d);
-+ mdio_write(tp, 0x06, 0x0105);
-+ mdio_write(tp, 0x06, 0xf8e0);
-+ mdio_write(tp, 0x06, 0x8b83);
-+ mdio_write(tp, 0x06, 0xad24);
-+ mdio_write(tp, 0x06, 0x44e0);
-+ mdio_write(tp, 0x06, 0xe022);
-+ mdio_write(tp, 0x06, 0xe1e0);
-+ mdio_write(tp, 0x06, 0x23ad);
-+ mdio_write(tp, 0x06, 0x223b);
-+ mdio_write(tp, 0x06, 0xe08a);
-+ mdio_write(tp, 0x06, 0xbea0);
-+ mdio_write(tp, 0x06, 0x0005);
-+ mdio_write(tp, 0x06, 0x0228);
-+ mdio_write(tp, 0x06, 0xdeae);
-+ mdio_write(tp, 0x06, 0x42a0);
-+ mdio_write(tp, 0x06, 0x0105);
-+ mdio_write(tp, 0x06, 0x0228);
-+ mdio_write(tp, 0x06, 0xf1ae);
-+ mdio_write(tp, 0x06, 0x3aa0);
-+ mdio_write(tp, 0x06, 0x0205);
-+ mdio_write(tp, 0x06, 0x0281);
-+ mdio_write(tp, 0x06, 0x25ae);
-+ mdio_write(tp, 0x06, 0x32a0);
-+ mdio_write(tp, 0x06, 0x0305);
-+ mdio_write(tp, 0x06, 0x0229);
-+ mdio_write(tp, 0x06, 0x9aae);
-+ mdio_write(tp, 0x06, 0x2aa0);
-+ mdio_write(tp, 0x06, 0x0405);
-+ mdio_write(tp, 0x06, 0x0229);
-+ mdio_write(tp, 0x06, 0xaeae);
-+ mdio_write(tp, 0x06, 0x22a0);
-+ mdio_write(tp, 0x06, 0x0505);
-+ mdio_write(tp, 0x06, 0x0229);
-+ mdio_write(tp, 0x06, 0xd7ae);
-+ mdio_write(tp, 0x06, 0x1aa0);
-+ mdio_write(tp, 0x06, 0x0605);
-+ mdio_write(tp, 0x06, 0x0229);
-+ mdio_write(tp, 0x06, 0xfeae);
-+ mdio_write(tp, 0x06, 0x12ee);
-+ mdio_write(tp, 0x06, 0x8ac0);
-+ mdio_write(tp, 0x06, 0x00ee);
-+ mdio_write(tp, 0x06, 0x8ac1);
-+ mdio_write(tp, 0x06, 0x00ee);
-+ mdio_write(tp, 0x06, 0x8ac6);
-+ mdio_write(tp, 0x06, 0x00ee);
-+ mdio_write(tp, 0x06, 0x8abe);
-+ mdio_write(tp, 0x06, 0x00ae);
-+ mdio_write(tp, 0x06, 0x00fc);
-+ mdio_write(tp, 0x06, 0x04f8);
-+ mdio_write(tp, 0x06, 0x022a);
-+ mdio_write(tp, 0x06, 0x67e0);
-+ mdio_write(tp, 0x06, 0xe022);
-+ mdio_write(tp, 0x06, 0xe1e0);
-+ mdio_write(tp, 0x06, 0x230d);
-+ mdio_write(tp, 0x06, 0x0658);
-+ mdio_write(tp, 0x06, 0x03a0);
-+ mdio_write(tp, 0x06, 0x0202);
-+ mdio_write(tp, 0x06, 0xae2d);
-+ mdio_write(tp, 0x06, 0xa001);
-+ mdio_write(tp, 0x06, 0x02ae);
-+ mdio_write(tp, 0x06, 0x2da0);
-+ mdio_write(tp, 0x06, 0x004d);
-+ mdio_write(tp, 0x06, 0xe0e2);
-+ mdio_write(tp, 0x06, 0x00e1);
-+ mdio_write(tp, 0x06, 0xe201);
-+ mdio_write(tp, 0x06, 0xad24);
-+ mdio_write(tp, 0x06, 0x44e0);
-+ mdio_write(tp, 0x06, 0x8ac2);
-+ mdio_write(tp, 0x06, 0xe48a);
-+ mdio_write(tp, 0x06, 0xc4e0);
-+ mdio_write(tp, 0x06, 0x8ac3);
-+ mdio_write(tp, 0x06, 0xe48a);
-+ mdio_write(tp, 0x06, 0xc5ee);
-+ mdio_write(tp, 0x06, 0x8abe);
-+ mdio_write(tp, 0x06, 0x03e0);
-+ mdio_write(tp, 0x06, 0x8b83);
-+ mdio_write(tp, 0x06, 0xad25);
-+ mdio_write(tp, 0x06, 0x3aee);
-+ mdio_write(tp, 0x06, 0x8abe);
-+ mdio_write(tp, 0x06, 0x05ae);
-+ mdio_write(tp, 0x06, 0x34e0);
-+ mdio_write(tp, 0x06, 0x8ace);
-+ mdio_write(tp, 0x06, 0xae03);
-+ mdio_write(tp, 0x06, 0xe08a);
-+ mdio_write(tp, 0x06, 0xcfe1);
-+ mdio_write(tp, 0x06, 0x8ac2);
-+ mdio_write(tp, 0x06, 0x4905);
-+ mdio_write(tp, 0x06, 0xe58a);
-+ mdio_write(tp, 0x06, 0xc4e1);
-+ mdio_write(tp, 0x06, 0x8ac3);
-+ mdio_write(tp, 0x06, 0x4905);
-+ mdio_write(tp, 0x06, 0xe58a);
-+ mdio_write(tp, 0x06, 0xc5ee);
-+ mdio_write(tp, 0x06, 0x8abe);
-+ mdio_write(tp, 0x06, 0x0502);
-+ mdio_write(tp, 0x06, 0x2ab6);
-+ mdio_write(tp, 0x06, 0xac20);
-+ mdio_write(tp, 0x06, 0x1202);
-+ mdio_write(tp, 0x06, 0x819b);
-+ mdio_write(tp, 0x06, 0xac20);
-+ mdio_write(tp, 0x06, 0x0cee);
-+ mdio_write(tp, 0x06, 0x8ac1);
-+ mdio_write(tp, 0x06, 0x00ee);
-+ mdio_write(tp, 0x06, 0x8ac6);
-+ mdio_write(tp, 0x06, 0x00ee);
-+ mdio_write(tp, 0x06, 0x8abe);
-+ mdio_write(tp, 0x06, 0x02fc);
-+ mdio_write(tp, 0x06, 0x04d0);
-+ mdio_write(tp, 0x06, 0x0002);
-+ mdio_write(tp, 0x06, 0x81ad);
-+ mdio_write(tp, 0x06, 0x590f);
-+ mdio_write(tp, 0x06, 0x3902);
-+ mdio_write(tp, 0x06, 0xaa04);
-+ mdio_write(tp, 0x06, 0xd001);
-+ mdio_write(tp, 0x06, 0xae02);
-+ mdio_write(tp, 0x06, 0xd000);
-+ mdio_write(tp, 0x06, 0x04f9);
-+ mdio_write(tp, 0x06, 0xfae2);
-+ mdio_write(tp, 0x06, 0xe2d2);
-+ mdio_write(tp, 0x06, 0xe3e2);
-+ mdio_write(tp, 0x06, 0xd3f9);
-+ mdio_write(tp, 0x06, 0x5af7);
-+ mdio_write(tp, 0x06, 0xe6e2);
-+ mdio_write(tp, 0x06, 0xd2e7);
-+ mdio_write(tp, 0x06, 0xe2d3);
-+ mdio_write(tp, 0x06, 0xe2e0);
-+ mdio_write(tp, 0x06, 0x2ce3);
-+ mdio_write(tp, 0x06, 0xe02d);
-+ mdio_write(tp, 0x06, 0xf95b);
-+ mdio_write(tp, 0x06, 0xe01e);
-+ mdio_write(tp, 0x06, 0x30e6);
-+ mdio_write(tp, 0x06, 0xe02c);
-+ mdio_write(tp, 0x06, 0xe7e0);
-+ mdio_write(tp, 0x06, 0x2de2);
-+ mdio_write(tp, 0x06, 0xe2cc);
-+ mdio_write(tp, 0x06, 0xe3e2);
-+ mdio_write(tp, 0x06, 0xcdf9);
-+ mdio_write(tp, 0x06, 0x5a0f);
-+ mdio_write(tp, 0x06, 0x6a50);
-+ mdio_write(tp, 0x06, 0xe6e2);
-+ mdio_write(tp, 0x06, 0xcce7);
-+ mdio_write(tp, 0x06, 0xe2cd);
-+ mdio_write(tp, 0x06, 0xe0e0);
-+ mdio_write(tp, 0x06, 0x3ce1);
-+ mdio_write(tp, 0x06, 0xe03d);
-+ mdio_write(tp, 0x06, 0xef64);
-+ mdio_write(tp, 0x06, 0xfde0);
-+ mdio_write(tp, 0x06, 0xe2cc);
-+ mdio_write(tp, 0x06, 0xe1e2);
-+ mdio_write(tp, 0x06, 0xcd58);
-+ mdio_write(tp, 0x06, 0x0f5a);
-+ mdio_write(tp, 0x06, 0xf01e);
-+ mdio_write(tp, 0x06, 0x02e4);
-+ mdio_write(tp, 0x06, 0xe2cc);
-+ mdio_write(tp, 0x06, 0xe5e2);
-+ mdio_write(tp, 0x06, 0xcdfd);
-+ mdio_write(tp, 0x06, 0xe0e0);
-+ mdio_write(tp, 0x06, 0x2ce1);
-+ mdio_write(tp, 0x06, 0xe02d);
-+ mdio_write(tp, 0x06, 0x59e0);
-+ mdio_write(tp, 0x06, 0x5b1f);
-+ mdio_write(tp, 0x06, 0x1e13);
-+ mdio_write(tp, 0x06, 0xe4e0);
-+ mdio_write(tp, 0x06, 0x2ce5);
-+ mdio_write(tp, 0x06, 0xe02d);
-+ mdio_write(tp, 0x06, 0xfde0);
-+ mdio_write(tp, 0x06, 0xe2d2);
-+ mdio_write(tp, 0x06, 0xe1e2);
-+ mdio_write(tp, 0x06, 0xd358);
-+ mdio_write(tp, 0x06, 0xf75a);
-+ mdio_write(tp, 0x06, 0x081e);
-+ mdio_write(tp, 0x06, 0x02e4);
-+ mdio_write(tp, 0x06, 0xe2d2);
-+ mdio_write(tp, 0x06, 0xe5e2);
-+ mdio_write(tp, 0x06, 0xd3ef);
-+ mdio_write(tp, 0x06, 0x46fe);
-+ mdio_write(tp, 0x06, 0xfd04);
-+ mdio_write(tp, 0x06, 0xf8f9);
-+ mdio_write(tp, 0x06, 0xfaef);
-+ mdio_write(tp, 0x06, 0x69e0);
-+ mdio_write(tp, 0x06, 0xe022);
-+ mdio_write(tp, 0x06, 0xe1e0);
-+ mdio_write(tp, 0x06, 0x2358);
-+ mdio_write(tp, 0x06, 0xc4e1);
-+ mdio_write(tp, 0x06, 0x8b6e);
-+ mdio_write(tp, 0x06, 0x1f10);
-+ mdio_write(tp, 0x06, 0x9e58);
-+ mdio_write(tp, 0x06, 0xe48b);
-+ mdio_write(tp, 0x06, 0x6ead);
-+ mdio_write(tp, 0x06, 0x2222);
-+ mdio_write(tp, 0x06, 0xac27);
-+ mdio_write(tp, 0x06, 0x55ac);
-+ mdio_write(tp, 0x06, 0x2602);
-+ mdio_write(tp, 0x06, 0xae1a);
-+ mdio_write(tp, 0x06, 0xd106);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xba02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd107);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xbd02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd107);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xc002);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xae30);
-+ mdio_write(tp, 0x06, 0xd103);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xc302);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd100);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xc602);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd100);
-+ mdio_write(tp, 0x06, 0xbf82);
-+ mdio_write(tp, 0x06, 0xca02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd10f);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xba02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd101);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xbd02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd101);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xc002);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xef96);
-+ mdio_write(tp, 0x06, 0xfefd);
-+ mdio_write(tp, 0x06, 0xfc04);
-+ mdio_write(tp, 0x06, 0xd100);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xc302);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd011);
-+ mdio_write(tp, 0x06, 0x022b);
-+ mdio_write(tp, 0x06, 0xfb59);
-+ mdio_write(tp, 0x06, 0x03ef);
-+ mdio_write(tp, 0x06, 0x01d1);
-+ mdio_write(tp, 0x06, 0x00a0);
-+ mdio_write(tp, 0x06, 0x0002);
-+ mdio_write(tp, 0x06, 0xd101);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0xc602);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xd111);
-+ mdio_write(tp, 0x06, 0xad20);
-+ mdio_write(tp, 0x06, 0x020c);
-+ mdio_write(tp, 0x06, 0x11ad);
-+ mdio_write(tp, 0x06, 0x2102);
-+ mdio_write(tp, 0x06, 0x0c12);
-+ mdio_write(tp, 0x06, 0xbf82);
-+ mdio_write(tp, 0x06, 0xca02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xaec8);
-+ mdio_write(tp, 0x06, 0x70e4);
-+ mdio_write(tp, 0x06, 0x2602);
-+ mdio_write(tp, 0x06, 0x82d1);
-+ mdio_write(tp, 0x06, 0x05f8);
-+ mdio_write(tp, 0x06, 0xfaef);
-+ mdio_write(tp, 0x06, 0x69e0);
-+ mdio_write(tp, 0x06, 0xe2fe);
-+ mdio_write(tp, 0x06, 0xe1e2);
-+ mdio_write(tp, 0x06, 0xffad);
-+ mdio_write(tp, 0x06, 0x2d1a);
-+ mdio_write(tp, 0x06, 0xe0e1);
-+ mdio_write(tp, 0x06, 0x4ee1);
-+ mdio_write(tp, 0x06, 0xe14f);
-+ mdio_write(tp, 0x06, 0xac2d);
-+ mdio_write(tp, 0x06, 0x22f6);
-+ mdio_write(tp, 0x06, 0x0302);
-+ mdio_write(tp, 0x06, 0x033b);
-+ mdio_write(tp, 0x06, 0xf703);
-+ mdio_write(tp, 0x06, 0xf706);
-+ mdio_write(tp, 0x06, 0xbf84);
-+ mdio_write(tp, 0x06, 0x4402);
-+ mdio_write(tp, 0x06, 0x2d21);
-+ mdio_write(tp, 0x06, 0xae11);
-+ mdio_write(tp, 0x06, 0xe0e1);
-+ mdio_write(tp, 0x06, 0x4ee1);
-+ mdio_write(tp, 0x06, 0xe14f);
-+ mdio_write(tp, 0x06, 0xad2d);
-+ mdio_write(tp, 0x06, 0x08bf);
-+ mdio_write(tp, 0x06, 0x844f);
-+ mdio_write(tp, 0x06, 0x022d);
-+ mdio_write(tp, 0x06, 0x21f6);
-+ mdio_write(tp, 0x06, 0x06ef);
-+ mdio_write(tp, 0x06, 0x96fe);
-+ mdio_write(tp, 0x06, 0xfc04);
-+ mdio_write(tp, 0x06, 0xf8fa);
-+ mdio_write(tp, 0x06, 0xef69);
-+ mdio_write(tp, 0x06, 0x0283);
-+ mdio_write(tp, 0x06, 0x4502);
-+ mdio_write(tp, 0x06, 0x83a2);
-+ mdio_write(tp, 0x06, 0xe0e0);
-+ mdio_write(tp, 0x06, 0x00e1);
-+ mdio_write(tp, 0x06, 0xe001);
-+ mdio_write(tp, 0x06, 0xad27);
-+ mdio_write(tp, 0x06, 0x1fd1);
-+ mdio_write(tp, 0x06, 0x01bf);
-+ mdio_write(tp, 0x06, 0x843b);
-+ mdio_write(tp, 0x06, 0x022d);
-+ mdio_write(tp, 0x06, 0xc1e0);
-+ mdio_write(tp, 0x06, 0xe020);
-+ mdio_write(tp, 0x06, 0xe1e0);
-+ mdio_write(tp, 0x06, 0x21ad);
-+ mdio_write(tp, 0x06, 0x200e);
-+ mdio_write(tp, 0x06, 0xd100);
-+ mdio_write(tp, 0x06, 0xbf84);
-+ mdio_write(tp, 0x06, 0x3b02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xbf3b);
-+ mdio_write(tp, 0x06, 0x9602);
-+ mdio_write(tp, 0x06, 0x2d21);
-+ mdio_write(tp, 0x06, 0xef96);
-+ mdio_write(tp, 0x06, 0xfefc);
-+ mdio_write(tp, 0x06, 0x04f8);
-+ mdio_write(tp, 0x06, 0xf9fa);
-+ mdio_write(tp, 0x06, 0xef69);
-+ mdio_write(tp, 0x06, 0xe08b);
-+ mdio_write(tp, 0x06, 0x87ad);
-+ mdio_write(tp, 0x06, 0x204c);
-+ mdio_write(tp, 0x06, 0xd200);
-+ mdio_write(tp, 0x06, 0xe0e2);
-+ mdio_write(tp, 0x06, 0x0058);
-+ mdio_write(tp, 0x06, 0x010c);
-+ mdio_write(tp, 0x06, 0x021e);
-+ mdio_write(tp, 0x06, 0x20e0);
-+ mdio_write(tp, 0x06, 0xe000);
-+ mdio_write(tp, 0x06, 0x5810);
-+ mdio_write(tp, 0x06, 0x1e20);
-+ mdio_write(tp, 0x06, 0xe0e0);
-+ mdio_write(tp, 0x06, 0x3658);
-+ mdio_write(tp, 0x06, 0x031e);
-+ mdio_write(tp, 0x06, 0x20e0);
-+ mdio_write(tp, 0x06, 0xe022);
-+ mdio_write(tp, 0x06, 0xe1e0);
-+ mdio_write(tp, 0x06, 0x2358);
-+ mdio_write(tp, 0x06, 0xe01e);
-+ mdio_write(tp, 0x06, 0x20e0);
-+ mdio_write(tp, 0x06, 0x8b64);
-+ mdio_write(tp, 0x06, 0x1f02);
-+ mdio_write(tp, 0x06, 0x9e22);
-+ mdio_write(tp, 0x06, 0xe68b);
-+ mdio_write(tp, 0x06, 0x64ad);
-+ mdio_write(tp, 0x06, 0x3214);
-+ mdio_write(tp, 0x06, 0xad34);
-+ mdio_write(tp, 0x06, 0x11ef);
-+ mdio_write(tp, 0x06, 0x0258);
-+ mdio_write(tp, 0x06, 0x039e);
-+ mdio_write(tp, 0x06, 0x07ad);
-+ mdio_write(tp, 0x06, 0x3508);
-+ mdio_write(tp, 0x06, 0x5ac0);
-+ mdio_write(tp, 0x06, 0x9f04);
-+ mdio_write(tp, 0x06, 0xd101);
-+ mdio_write(tp, 0x06, 0xae02);
-+ mdio_write(tp, 0x06, 0xd100);
-+ mdio_write(tp, 0x06, 0xbf84);
-+ mdio_write(tp, 0x06, 0x3e02);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xef96);
-+ mdio_write(tp, 0x06, 0xfefd);
-+ mdio_write(tp, 0x06, 0xfc04);
-+ mdio_write(tp, 0x06, 0xf8f9);
-+ mdio_write(tp, 0x06, 0xfbe0);
-+ mdio_write(tp, 0x06, 0x8b85);
-+ mdio_write(tp, 0x06, 0xad25);
-+ mdio_write(tp, 0x06, 0x22e0);
-+ mdio_write(tp, 0x06, 0xe022);
-+ mdio_write(tp, 0x06, 0xe1e0);
-+ mdio_write(tp, 0x06, 0x23e2);
-+ mdio_write(tp, 0x06, 0xe036);
-+ mdio_write(tp, 0x06, 0xe3e0);
-+ mdio_write(tp, 0x06, 0x375a);
-+ mdio_write(tp, 0x06, 0xc40d);
-+ mdio_write(tp, 0x06, 0x0158);
-+ mdio_write(tp, 0x06, 0x021e);
-+ mdio_write(tp, 0x06, 0x20e3);
-+ mdio_write(tp, 0x06, 0x8ae7);
-+ mdio_write(tp, 0x06, 0xac31);
-+ mdio_write(tp, 0x06, 0x60ac);
-+ mdio_write(tp, 0x06, 0x3a08);
-+ mdio_write(tp, 0x06, 0xac3e);
-+ mdio_write(tp, 0x06, 0x26ae);
-+ mdio_write(tp, 0x06, 0x67af);
-+ mdio_write(tp, 0x06, 0x8437);
-+ mdio_write(tp, 0x06, 0xad37);
-+ mdio_write(tp, 0x06, 0x61e0);
-+ mdio_write(tp, 0x06, 0x8ae8);
-+ mdio_write(tp, 0x06, 0x10e4);
-+ mdio_write(tp, 0x06, 0x8ae8);
-+ mdio_write(tp, 0x06, 0xe18a);
-+ mdio_write(tp, 0x06, 0xe91b);
-+ mdio_write(tp, 0x06, 0x109e);
-+ mdio_write(tp, 0x06, 0x02ae);
-+ mdio_write(tp, 0x06, 0x51d1);
-+ mdio_write(tp, 0x06, 0x00bf);
-+ mdio_write(tp, 0x06, 0x8441);
-+ mdio_write(tp, 0x06, 0x022d);
-+ mdio_write(tp, 0x06, 0xc1ee);
-+ mdio_write(tp, 0x06, 0x8ae8);
-+ mdio_write(tp, 0x06, 0x00ae);
-+ mdio_write(tp, 0x06, 0x43ad);
-+ mdio_write(tp, 0x06, 0x3627);
-+ mdio_write(tp, 0x06, 0xe08a);
-+ mdio_write(tp, 0x06, 0xeee1);
-+ mdio_write(tp, 0x06, 0x8aef);
-+ mdio_write(tp, 0x06, 0xef74);
-+ mdio_write(tp, 0x06, 0xe08a);
-+ mdio_write(tp, 0x06, 0xeae1);
-+ mdio_write(tp, 0x06, 0x8aeb);
-+ mdio_write(tp, 0x06, 0x1b74);
-+ mdio_write(tp, 0x06, 0x9e2e);
-+ mdio_write(tp, 0x06, 0x14e4);
-+ mdio_write(tp, 0x06, 0x8aea);
-+ mdio_write(tp, 0x06, 0xe58a);
-+ mdio_write(tp, 0x06, 0xebef);
-+ mdio_write(tp, 0x06, 0x74e0);
-+ mdio_write(tp, 0x06, 0x8aee);
-+ mdio_write(tp, 0x06, 0xe18a);
-+ mdio_write(tp, 0x06, 0xef1b);
-+ mdio_write(tp, 0x06, 0x479e);
-+ mdio_write(tp, 0x06, 0x0fae);
-+ mdio_write(tp, 0x06, 0x19ee);
-+ mdio_write(tp, 0x06, 0x8aea);
-+ mdio_write(tp, 0x06, 0x00ee);
-+ mdio_write(tp, 0x06, 0x8aeb);
-+ mdio_write(tp, 0x06, 0x00ae);
-+ mdio_write(tp, 0x06, 0x0fac);
-+ mdio_write(tp, 0x06, 0x390c);
-+ mdio_write(tp, 0x06, 0xd101);
-+ mdio_write(tp, 0x06, 0xbf84);
-+ mdio_write(tp, 0x06, 0x4102);
-+ mdio_write(tp, 0x06, 0x2dc1);
-+ mdio_write(tp, 0x06, 0xee8a);
-+ mdio_write(tp, 0x06, 0xe800);
-+ mdio_write(tp, 0x06, 0xe68a);
-+ mdio_write(tp, 0x06, 0xe7ff);
-+ mdio_write(tp, 0x06, 0xfdfc);
-+ mdio_write(tp, 0x06, 0x0400);
-+ mdio_write(tp, 0x06, 0xe234);
-+ mdio_write(tp, 0x06, 0xcce2);
-+ mdio_write(tp, 0x06, 0x0088);
-+ mdio_write(tp, 0x06, 0xe200);
-+ mdio_write(tp, 0x06, 0xa725);
-+ mdio_write(tp, 0x06, 0xe50a);
-+ mdio_write(tp, 0x06, 0x1de5);
-+ mdio_write(tp, 0x06, 0x0a2c);
-+ mdio_write(tp, 0x06, 0xe50a);
-+ mdio_write(tp, 0x06, 0x6de5);
-+ mdio_write(tp, 0x06, 0x0a1d);
-+ mdio_write(tp, 0x06, 0xe50a);
-+ mdio_write(tp, 0x06, 0x1ce5);
-+ mdio_write(tp, 0x06, 0x0a2d);
-+ mdio_write(tp, 0x06, 0xa755);
-+ mdio_write(tp, 0x05, 0x8b64);
-+ mdio_write(tp, 0x06, 0x0000);
-+ mdio_write(tp, 0x05, 0x8b94);
-+ mdio_write(tp, 0x06, 0x82cd);
-+ mdio_write(tp, 0x05, 0x8b85);
-+ mdio_write(tp, 0x06, 0x2000);
-+ mdio_write(tp, 0x05, 0x8aee);
-+ mdio_write(tp, 0x06, 0x03b8);
-+ mdio_write(tp, 0x05, 0x8ae8);
-+ mdio_write(tp, 0x06, 0x0002);
-+ gphy_val = mdio_read(tp, 0x01);
-+ gphy_val |= BIT_0;
-+ mdio_write(tp, 0x01, gphy_val);
-+ gphy_val = mdio_read(tp, 0x00);
-+ gphy_val |= BIT_0;
-+ mdio_write(tp, 0x00, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x1f, 0x0005);
-+ for (i = 0; i < 200; i++) {
-+ udelay(100);
-+ gphy_val = mdio_read(tp, 0x00);
-+ if (gphy_val & BIT_7)
-+ break;
-+ }
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0023);
-+ gphy_val = mdio_read(tp, 0x17);
-+ gphy_val &= ~(BIT_0);
-+ if (tp->RequiredSecLanDonglePatch)
-+ gphy_val &= ~(BIT_2);
-+ mdio_write(tp, 0x17, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0028);
-+ mdio_write(tp, 0x15, 0x0010);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0041);
-+ mdio_write(tp, 0x15, 0x0802);
-+ mdio_write(tp, 0x16, 0x2185);
-+ mdio_write(tp, 0x1f, 0x0000);
-+}
-+
-+static void
-+rtl8168_set_phy_mcu_8168e_2(struct net_device *dev)
-+{
-+ struct rtl8168_private *tp = netdev_priv(dev);
-+ unsigned int gphy_val,i;
-+
-+ if (rtl8168_efuse_read(tp, 0x22) == 0x0c) {
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x00, 0x1800);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0023);
-+ mdio_write(tp, 0x17, 0x0117);
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1E, 0x002C);
-+ mdio_write(tp, 0x1B, 0x5000);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ mdio_write(tp, 0x16, 0x4104);
-+ for (i = 0; i < 200; i++) {
-+ udelay(100);
-+ gphy_val = mdio_read(tp, 0x1E);
-+ gphy_val &= 0x03FF;
-+ if (gphy_val==0x000C)
-+ break;
-+ }
-+ mdio_write(tp, 0x1f, 0x0005);
-+ for (i = 0; i < 200; i++) {
-+ udelay(100);
-+ gphy_val = mdio_read(tp, 0x07);
-+ if ((gphy_val & BIT_5) == 0)
-+ break;
-+ }
-+ gphy_val = mdio_read(tp, 0x07);
-+ if (gphy_val & BIT_5) {
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x00a1);
-+ mdio_write(tp, 0x17, 0x1000);
-+ mdio_write(tp, 0x17, 0x0000);
-+ mdio_write(tp, 0x17, 0x2000);
-+ mdio_write(tp, 0x1e, 0x002f);
-+ mdio_write(tp, 0x18, 0x9bfb);
-+ mdio_write(tp, 0x1f, 0x0005);
-+ mdio_write(tp, 0x07, 0x0000);
-+ mdio_write(tp, 0x1f, 0x0000);
-+ }
-+ mdio_write(tp, 0x1f, 0x0005);
-+ mdio_write(tp, 0x05, 0xfff6);
-+ mdio_write(tp, 0x06, 0x0080);
-+ gphy_val = mdio_read(tp, 0x00);
-+ gphy_val &= ~(BIT_7);
-+ mdio_write(tp, 0x00, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0002);
-+ gphy_val = mdio_read(tp, 0x08);
-+ gphy_val &= ~(BIT_7);
-+ mdio_write(tp, 0x08, gphy_val);
-+ mdio_write(tp, 0x1f, 0x0000);
-+
-+ mdio_write(tp, 0x1f, 0x0007);
-+ mdio_write(tp, 0x1e, 0x0023);
-+ mdio_write(tp, 0x16, 0x0306);
-+ mdio_write(tp, 0x16, 0x0307);
-+ mdio_write(tp, 0x15, 0x000e);
-+ mdio_write(tp, 0x19, 0x000a);
-+ mdio_write(tp, 0x15, 0x0010);
-+ mdio_write(tp, 0x19, 0x0008);
-+ mdio_write(tp, 0x15, 0x0018);
-+ mdio_write(tp, 0x19, 0x4801);
-+ mdio_write(tp, 0x15, 0x0019);
-+ mdio_write(tp, 0x19, 0x6801);
-+ mdio_write(tp, 0x15, 0x001a);
-+ mdio_write(tp, 0x19, 0x66a1);
-+ mdio_write(tp, 0x15, 0x001f);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0020);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0021);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0022);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0023);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0024);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0025);
-+ mdio_write(tp, 0x19, 0x64a1);
-+ mdio_write(tp, 0x15, 0x0026);
-+ mdio_write(tp, 0x19, 0x40ea);
-+ mdio_write(tp, 0x15, 0x0027);
-+ mdio_write(tp, 0x19, 0x4503);
-+ mdio_write(tp, 0x15, 0x0028);
-+ mdio_write(tp, 0x19, 0x9f00);
-+ mdio_write(tp, 0x15, 0x0029);
-+ mdio_write(tp, 0x19, 0xa631);
-+ mdio_write(tp, 0x15, 0x002a);
-+ mdio_write(tp, 0x19, 0x9717);
-+ mdio_write(tp, 0x15, 0x002b);
-+ mdio_write(tp, 0x19, 0x302c);
-+ mdio_write(tp, 0x15, 0x002c);
-+ mdio_write(tp, 0x19, 0x4802);
-+ mdio_write(tp, 0x15, 0x002d);
-+ mdio_write(tp, 0x19, 0x58da);
-+ mdio_write(tp, 0x15, 0x002e);
-+ mdio_write(tp, 0x19, 0x400d);
-+ mdio_write(tp, 0x15, 0x002f);
-+ mdio_write(tp, 0x19, 0x4488);
-+ mdio_write(tp, 0x15, 0x0030);
-+ mdio_write(tp, 0x19, 0x9e00);
-+ mdio_write(tp, 0x15, 0x0031);
-+ mdio_write(tp, 0x19, 0x63c8);
-+ mdio_write(tp, 0x15, 0x0032);
-+ mdio_write(tp, 0x19, 0x6481);
-+ mdio_write(tp, 0x15, 0x0033);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0034);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0035);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0036);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0037);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0038);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0039);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x003a);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x003b);
-+ mdio_write(tp, 0x19, 0x63e8);
-+ mdio_write(tp, 0x15, 0x003c);
-+ mdio_write(tp, 0x19, 0x7d00);
-+ mdio_write(tp, 0x15, 0x003d);
-+ mdio_write(tp, 0x19, 0x59d4);
-+ mdio_write(tp, 0x15, 0x003e);
-+ mdio_write(tp, 0x19, 0x63f8);
-+ mdio_write(tp, 0x15, 0x0040);
-+ mdio_write(tp, 0x19, 0x64a1);
-+ mdio_write(tp, 0x15, 0x0041);
-+ mdio_write(tp, 0x19, 0x30de);
-+ mdio_write(tp, 0x15, 0x0044);
-+ mdio_write(tp, 0x19, 0x480f);
-+ mdio_write(tp, 0x15, 0x0045);
-+ mdio_write(tp, 0x19, 0x6800);
-+ mdio_write(tp, 0x15, 0x0046);
-+ mdio_write(tp, 0x19, 0x6680);
-+ mdio_write(tp, 0x15, 0x0047);
-+ mdio_write(tp, 0x19, 0x7c10);
-+ mdio_write(tp, 0x15, 0x0048);
-+ mdio_write(tp, 0x19, 0x63c8);
-+ mdio_write(tp, 0x15, 0x0049);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004a);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004b);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004c);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004d);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004e);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x004f);
-+ mdio_write(tp, 0x19, 0x40ea);
-+ mdio_write(tp, 0x15, 0x0050);
-+ mdio_write(tp, 0x19, 0x4503);
-+ mdio_write(tp, 0x15, 0x0051);
-+ mdio_write(tp, 0x19, 0x58ca);
-+ mdio_write(tp, 0x15, 0x0052);
-+ mdio_write(tp, 0x19, 0x63c8);
-+ mdio_write(tp, 0x15, 0x0053);
-+ mdio_write(tp, 0x19, 0x63d8);
-+ mdio_write(tp, 0x15, 0x0054);
-+ mdio_write(tp, 0x19, 0x66a0);
-+ mdio_write(tp, 0x15, 0x0055);
-+ mdio_write(tp, 0x19, 0x9f00);
-+ mdio_write(tp, 0x15, 0x0056);
-+ mdio_write(tp, 0x19, 0x3000);
-+ mdio_write(tp, 0x15, 0x00a1);
-+ mdio_write(tp, 0x19, 0x3044);
-+ mdio_write(tp, 0x15, 0x00ab);
-+ mdio_write(tp, 0x19, 0x5820);
-+ mdio_write(tp, 0x15, 0x00ac);
-+ mdio_write(tp, 0x19, 0x5e04);
-+ mdio_write(tp, 0x15, 0x00ad);
-+ mdio_write(tp, 0x19, 0xb60c);
-+ mdio_write(tp, 0x15, 0x00af);
-+ mdio_write(tp, 0x19, 0x000a);
-+ mdio_write(tp, 0x15, 0x00b2);
-+ mdio_write(tp, 0x19, 0x30b9);
-+ mdio_write(tp, 0x15, 0x00b9);
-+ mdio_write(tp, 0x19, 0x4408);
-+ mdio_write(tp, 0x15, 0x00ba);
-+ mdio_write(tp, 0x19, 0x480b);
-+ mdio_write(tp, 0x15, 0x00bb);
-+ mdio_write(tp, 0x19, 0x5e00);
-+ mdio_write(tp, 0x15, 0x00bc);
-+ mdio_write(tp, 0x19, 0x405f);
-+ mdio_write(tp, 0x15, 0x00bd);
-+ mdio_write(tp, 0x19, 0x4448);
-+ mdio_write(tp, 0x15, 0x00be);
-+ mdio_write(tp, 0x19, 0x4020);
-+ mdio_write(tp, 0x15, 0x00bf);
-+ mdio_write(tp, 0x19, 0x4468);
-+ mdio_write(tp, 0x15, 0x00c0);
-+ mdio_write(tp, 0x19, 0x9c02);
-+ mdio_write(tp, 0x15, 0x00c1);
-+ mdio_write(tp, 0x19, 0x58a0);
-+ mdio_write(tp, 0x15, 0x00c2);
-+ mdio_write(tp, 0x19, 0xb605);
-+ mdio_write(tp, 0x15, 0x00c3);
-+ mdio_write(tp, 0x19, 0xc0d3);
-+ mdio_write(tp, 0x15, 0x00c4);
-+ mdio_write(tp, 0x19, 0x00e6);
-+ mdio_write(tp, 0x15, 0x00c5);
-+ mdio_write(tp, 0x19, 0xdaec);
-+ mdio_write(tp, 0x15, 0x00c6);
-+ mdio_write(tp, 0x19, 0x00fa);
-+ mdio_write(tp, 0x15, 0x00c7);
-+ mdio_write(tp, 0x19, 0x9df9);
-+ mdio_write(tp, 0x15, 0x0112);
-+ mdio_write(tp, 0x19, 0x6421);
-+ mdio_write(tp, 0x15, 0x0113);
-+ mdio_write(tp, 0x19, 0x7c08);
-+ mdio_write(tp, 0x15, 0x0114);
-+ mdio_write(tp, 0x19, 0x63f0);
-+ mdio_write(tp, 0x15, 0x0115);
-+ mdio_write(tp, 0x19, 0x4003);
-+ mdio_write(tp, 0x15, 0x0116);
-+ mdio_write(tp, 0x19, 0x4418);
-+ mdio_write(tp, 0x15, 0x0117);
-+ mdio_write(tp, 0x19, 0x9b00);
-+ mdio_write(tp, 0x15, 0x0118);
-+ mdio_write(tp, 0x19, 0x6461);
-+ mdio_write(tp, 0x15, 0x0119);
-+ mdio_write(tp, 0x19, 0x64e1);
-+ mdio_write(tp, 0x15, 0x011a);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0150);
-+ mdio_write(tp, 0x19, 0x7c80);
-+ mdio_write(tp, 0x15, 0x0151);
-+ mdio_write(tp, 0x19, 0x6461);
-+ mdio_write(tp, 0x15, 0x0152);
-+ mdio_write(tp, 0x19, 0x4003);
-+ mdio_write(tp, 0x15, 0x0153);
-+ mdio_write(tp, 0x19, 0x4540);
-+ mdio_write(tp, 0x15, 0x0154);
-+ mdio_write(tp, 0x19, 0x9f00);
-+ mdio_write(tp, 0x15, 0x0155);
-+ mdio_write(tp, 0x19, 0x9d00);
-+ mdio_write(tp, 0x15, 0x0156);
-+ mdio_write(tp, 0x19, 0x7c40);
-+ mdio_write(tp, 0x15, 0x0157);
-+ mdio_write(tp, 0x19, 0x6421);
-+ mdio_write(tp, 0x15, 0x0158);
-+ mdio_write(tp, 0x19, 0x7c80);
-+ mdio_write(tp, 0x15, 0x0159);
-+ mdio_write(tp, 0x19, 0x64a1);
-+ mdio_write(tp, 0x15, 0x015a);
-+ mdio_write(tp, 0x19, 0x30fe);
-+ mdio_write(tp, 0x15, 0x029c);
-+ mdio_write(tp, 0x19, 0x0070);
-+ mdio_write(tp, 0x15, 0x02b2);
-+ mdio_write(tp, 0x19, 0x005a);
-+ mdio_write(tp, 0x15, 0x02bd);
-+ mdio_write(tp, 0x19, 0xa522);
-+ mdio_write(tp, 0x15, 0x02ce);
-+ mdio_write(tp, 0x19, 0xb63e);
-+ mdio_write(tp, 0x15, 0x02d9);
-+ mdio_write(tp, 0x19, 0x32df);
-+ mdio_write(tp, 0x15, 0x02df);
-+ mdio_write(tp, 0x19, 0x4500);
-+ mdio_write(tp, 0x15, 0x02e7);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x02f4);
-+ mdio_write(tp, 0x19, 0xb618);
-+ mdio_write(tp, 0x15, 0x02fb);
-+ mdio_write(tp, 0x19, 0xb900);
-+ mdio_write(tp, 0x15, 0x02fc);
-+ mdio_write(tp, 0x19, 0x49b5);
-+ mdio_write(tp, 0x15, 0x02fd);
-+ mdio_write(tp, 0x19, 0x6812);
-+ mdio_write(tp, 0x15, 0x02fe);
-+ mdio_write(tp, 0x19, 0x66a0);
-+ mdio_write(tp, 0x15, 0x02ff);
-+ mdio_write(tp, 0x19, 0x9900);
-+ mdio_write(tp, 0x15, 0x0300);
-+ mdio_write(tp, 0x19, 0x64a0);
-+ mdio_write(tp, 0x15, 0x0301);
-+ mdio_write(tp, 0x19, 0x3316);
-+ mdio_write(tp, 0x15, 0x0308);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x030c);
-+ mdio_write(tp, 0x19, 0x3000);
-+ mdio_write(tp, 0x15, 0x0312);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0313);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0314);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0315);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0316);
-+ mdio_write(tp, 0x19, 0x49b5);
-+ mdio_write(tp, 0x15, 0x0317);
-+ mdio_write(tp, 0x19, 0x7d00);
-+ mdio_write(tp, 0x15, 0x0318);
-+ mdio_write(tp, 0x19, 0x4d00);
-+ mdio_write(tp, 0x15, 0x0319);
-+ mdio_write(tp, 0x19, 0x6810);
-+ mdio_write(tp, 0x15, 0x031a);
-+ mdio_write(tp, 0x19, 0x6c08);
-+ mdio_write(tp, 0x15, 0x031b);
-+ mdio_write(tp, 0x19, 0x4925);
-+ mdio_write(tp, 0x15, 0x031c);
-+ mdio_write(tp, 0x19, 0x403b);
-+ mdio_write(tp, 0x15, 0x031d);
-+ mdio_write(tp, 0x19, 0xa602);
-+ mdio_write(tp, 0x15, 0x031e);
-+ mdio_write(tp, 0x19, 0x402f);
-+ mdio_write(tp, 0x15, 0x031f);
-+ mdio_write(tp, 0x19, 0x4484);
-+ mdio_write(tp, 0x15, 0x0320);
-+ mdio_write(tp, 0x19, 0x40c8);
-+ mdio_write(tp, 0x15, 0x0321);
-+ mdio_write(tp, 0x19, 0x44c4);
-+ mdio_write(tp, 0x15, 0x0322);
-+ mdio_write(tp, 0x19, 0x404f);
-+ mdio_write(tp, 0x15, 0x0323);
-+ mdio_write(tp, 0x19, 0x44c8);
-+ mdio_write(tp, 0x15, 0x0324);
-+ mdio_write(tp, 0x19, 0xd64f);
-+ mdio_write(tp, 0x15, 0x0325);
-+ mdio_write(tp, 0x19, 0x00e7);
-+ mdio_write(tp, 0x15, 0x0326);
-+ mdio_write(tp, 0x19, 0x7c08);
-+ mdio_write(tp, 0x15, 0x0327);
-+ mdio_write(tp, 0x19, 0x8203);
-+ mdio_write(tp, 0x15, 0x0328);
-+ mdio_write(tp, 0x19, 0x4d48);
-+ mdio_write(tp, 0x15, 0x0329);
-+ mdio_write(tp, 0x19, 0x332b);
-+ mdio_write(tp, 0x15, 0x032a);
-+ mdio_write(tp, 0x19, 0x4d40);
-+ mdio_write(tp, 0x15, 0x032c);
-+ mdio_write(tp, 0x19, 0x00f8);
-+ mdio_write(tp, 0x15, 0x032d);
-+ mdio_write(tp, 0x19, 0x82b2);
-+ mdio_write(tp, 0x15, 0x032f);
-+ mdio_write(tp, 0x19, 0x00b0);
-+ mdio_write(tp, 0x15, 0x0332);
-+ mdio_write(tp, 0x19, 0x91f2);
-+ mdio_write(tp, 0x15, 0x033f);
-+ mdio_write(tp, 0x19, 0xb6cd);
-+ mdio_write(tp, 0x15, 0x0340);
-+ mdio_write(tp, 0x19, 0x9e01);
-+ mdio_write(tp, 0x15, 0x0341);
-+ mdio_write(tp, 0x19, 0xd11d);
-+ mdio_write(tp, 0x15, 0x0342);
-+ mdio_write(tp, 0x19, 0x009d);
-+ mdio_write(tp, 0x15, 0x0343);
-+ mdio_write(tp, 0x19, 0xbb1c);
-+ mdio_write(tp, 0x15, 0x0344);
-+ mdio_write(tp, 0x19, 0x8102);
-+ mdio_write(tp, 0x15, 0x0345);
-+ mdio_write(tp, 0x19, 0x3348);
-+ mdio_write(tp, 0x15, 0x0346);
-+ mdio_write(tp, 0x19, 0xa231);
-+ mdio_write(tp, 0x15, 0x0347);
-+ mdio_write(tp, 0x19, 0x335b);
-+ mdio_write(tp, 0x15, 0x0348);
-+ mdio_write(tp, 0x19, 0x91f7);
-+ mdio_write(tp, 0x15, 0x0349);
-+ mdio_write(tp, 0x19, 0xc218);
-+ mdio_write(tp, 0x15, 0x034a);
-+ mdio_write(tp, 0x19, 0x00f5);
-+ mdio_write(tp, 0x15, 0x034b);
-+ mdio_write(tp, 0x19, 0x335b);
-+ mdio_write(tp, 0x15, 0x034c);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x034d);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x034e);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x034f);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x0350);
-+ mdio_write(tp, 0x19, 0x0000);
-+ mdio_write(tp, 0x15, 0x035b);
-+ mdio_write(tp, 0x19, 0xa23c);
-+ mdio_write(tp, 0x15, 0x035c);
-+ mdio_write(tp, 0x19, 0x7c08);
-+ mdio_write(tp, 0x15, 0x035d);
-+ mdio_write(tp, 0x19, 0x4c00);
-+ mdio_write(tp, 0x15, 0x035e);
-+ mdio_write(tp, 0x19, 0x3397);
-+ mdio_write(tp, 0x15, 0x0363);
-+ mdio_write(tp, 0x19, 0xb6a9);
-+ mdio_write(tp, 0x15, 0x0366);
-+ mdio_write(tp, 0x19, 0x00f5);
-+ mdio_write(tp, 0x15, 0x0382);
-+ mdio_write(tp, 0x19, 0x7c40);
-+ mdio_write(tp, 0x15, 0x0388);
-+ mdio_write(tp, 0x19, 0x0084);
-+ mdio_write(tp, 0x15, 0x0389);
-+ mdio_write(tp, 0x19, 0xdd17);
-+ mdio_write(tp, 0x15, 0x038a);
-+ mdio_write(tp, 0x19, 0x000b);
-+ mdio_write(tp, 0x15, 0x038b);
-+ mdio_write(tp, 0x19, 0xa10a);
-+ mdio_write(tp, 0x15, 0x038c);
-+ mdio_write(tp, 0x19, 0x337e);
-+ mdio_write(tp, 0x15, 0x038d);
-+ mdio_write(tp, 0x19, 0x6c0b);
-+ mdio_write(tp, 0x15, 0x038e);
-+ mdio_write(tp, 0x19, 0xa107);
-+ mdio_write(tp, 0x15, 0x038f);
-+ mdio_write(tp, 0x19, 0x6c08);
-+ mdio_write(tp, 0x15, 0x0390);
-+ mdio_write(tp, 0x19, 0xc017);
-+ mdio_write(tp, 0x15, 0x0391);
-+ mdio_write(tp, 0x19, 0x0004);
-+ mdio_write(tp, 0x15,