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authorWade Farnsworth <wfarnsworth@users.noreply.github.com>2019-10-22 08:08:07 -0700
committerGitHub <noreply@github.com>2019-10-22 08:08:07 -0700
commit8e0cf9ee43840bd7ee004412129ba4aa055f5fc8 (patch)
treeb13804093e413307097cd6788ccdc8b062084013 /meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0571-drm-amd-display-Rename-DCN-opp-specific-function-pre.patch
parent9e1e1da00d8ef569d83a7a742a734dbbf5e0bd13 (diff)
parent3f8062a03dc1d1d5fa386e1f1ca59d56b86a85d1 (diff)
downloadmeta-amd-master.tar.gz
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Merge pull request #661 from ArsalanHAwan/master-merge-warriorHEADmaster
master: merge warrior
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0571-drm-amd-display-Rename-DCN-opp-specific-function-pre.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0571-drm-amd-display-Rename-DCN-opp-specific-function-pre.patch453
1 files changed, 453 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0571-drm-amd-display-Rename-DCN-opp-specific-function-pre.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0571-drm-amd-display-Rename-DCN-opp-specific-function-pre.patch
new file mode 100644
index 00000000..5a2baef3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0571-drm-amd-display-Rename-DCN-opp-specific-function-pre.patch
@@ -0,0 +1,453 @@
+From d4a845fa320c3434328bd5515b9a43ebf15eb4b9 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 28 Jun 2017 18:41:22 -0400
+Subject: [PATCH 0571/4131] drm/amd/display: Rename DCN opp specific function
+ prefixes to oppn10
+
+Also update relevant registers.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 189 ++++++++++-----------
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 79 ++++-----
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +-
+ 3 files changed, 138 insertions(+), 136 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index a074010..e6f2220 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -37,7 +37,7 @@
+ #define CTX \
+ oppn10->base.ctx
+
+-static void opp_set_regamma_mode(
++static void oppn10_set_regamma_mode(
+ struct output_pixel_processor *opp,
+ enum opp_regamma mode)
+ {
+@@ -167,7 +167,7 @@ static void set_spatial_dither(
+ FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
+ }
+
+-static void opp_program_bit_depth_reduction(
++static void oppn10_program_bit_depth_reduction(
+ struct output_pixel_processor *opp,
+ const struct bit_depth_reduction_params *params)
+ {
+@@ -255,7 +255,7 @@ static void opp_set_clamping(
+
+ }
+
+-static void opp_set_dyn_expansion(
++static void oppn10_set_dyn_expansion(
+ struct output_pixel_processor *opp,
+ enum dc_color_space color_sp,
+ enum dc_color_depth color_dpth,
+@@ -304,7 +304,7 @@ static void opp_program_clamping_and_pixel_encoding(
+ set_pixel_encoding(oppn10, params);
+ }
+
+-static void opp_program_fmt(
++static void oppn10_program_fmt(
+ struct output_pixel_processor *opp,
+ struct bit_depth_reduction_params *fmt_bit_depth,
+ struct clamping_and_pixel_encoding_params *clamping)
+@@ -316,7 +316,7 @@ static void opp_program_fmt(
+
+ /* dithering is affected by <CrtcSourceSelect>, hence should be
+ * programmed afterwards */
+- opp_program_bit_depth_reduction(
++ oppn10_program_bit_depth_reduction(
+ opp,
+ fmt_bit_depth);
+
+@@ -327,7 +327,7 @@ static void opp_program_fmt(
+ return;
+ }
+
+-static void opp_set_output_csc_default(
++static void oppn10_set_output_csc_default(
+ struct output_pixel_processor *opp,
+ const struct default_adjustment *default_adjust)
+ {
+@@ -703,7 +703,7 @@ static void opp_configure_regamma_lut(
+ REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
+ }
+
+-static void opp_power_on_regamma_lut(
++static void oppn10_power_on_regamma_lut(
+ struct output_pixel_processor *opp,
+ bool power_on)
+ {
+@@ -713,7 +713,78 @@ static void opp_power_on_regamma_lut(
+
+ }
+
+-void opp_set_output_csc_adjustment(
++
++static void oppn10_program_color_matrix(struct dcn10_opp *oppn10,
++ const struct out_csc_color_matrix *tbl_entry)
++{
++ uint32_t mode;
++
++ REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
++
++ if (tbl_entry == NULL) {
++ BREAK_TO_DEBUGGER();
++ return;
++ }
++
++
++ if (mode == 4) {
++ /*R*/
++ REG_SET_2(CM_OCSC_C11_C12, 0,
++ CM_OCSC_C11, tbl_entry->regval[0],
++ CM_OCSC_C12, tbl_entry->regval[1]);
++
++ REG_SET_2(CM_OCSC_C13_C14, 0,
++ CM_OCSC_C13, tbl_entry->regval[2],
++ CM_OCSC_C14, tbl_entry->regval[3]);
++
++ /*G*/
++ REG_SET_2(CM_OCSC_C21_C22, 0,
++ CM_OCSC_C21, tbl_entry->regval[4],
++ CM_OCSC_C22, tbl_entry->regval[5]);
++
++ REG_SET_2(CM_OCSC_C23_C24, 0,
++ CM_OCSC_C23, tbl_entry->regval[6],
++ CM_OCSC_C24, tbl_entry->regval[7]);
++
++ /*B*/
++ REG_SET_2(CM_OCSC_C31_C32, 0,
++ CM_OCSC_C31, tbl_entry->regval[8],
++ CM_OCSC_C32, tbl_entry->regval[9]);
++
++ REG_SET_2(CM_OCSC_C33_C34, 0,
++ CM_OCSC_C33, tbl_entry->regval[10],
++ CM_OCSC_C34, tbl_entry->regval[11]);
++ } else {
++ /*R*/
++ REG_SET_2(CM_COMB_C11_C12, 0,
++ CM_COMB_C11, tbl_entry->regval[0],
++ CM_COMB_C12, tbl_entry->regval[1]);
++
++ REG_SET_2(CM_COMB_C13_C14, 0,
++ CM_COMB_C13, tbl_entry->regval[2],
++ CM_COMB_C14, tbl_entry->regval[3]);
++
++ /*G*/
++ REG_SET_2(CM_COMB_C21_C22, 0,
++ CM_COMB_C21, tbl_entry->regval[4],
++ CM_COMB_C22, tbl_entry->regval[5]);
++
++ REG_SET_2(CM_COMB_C23_C24, 0,
++ CM_COMB_C23, tbl_entry->regval[6],
++ CM_COMB_C24, tbl_entry->regval[7]);
++
++ /*B*/
++ REG_SET_2(CM_COMB_C31_C32, 0,
++ CM_COMB_C31, tbl_entry->regval[8],
++ CM_COMB_C32, tbl_entry->regval[9]);
++
++ REG_SET_2(CM_COMB_C33_C34, 0,
++ CM_COMB_C33, tbl_entry->regval[10],
++ CM_COMB_C34, tbl_entry->regval[11]);
++ }
++}
++
++void oppn10_set_output_csc_adjustment(
+ struct output_pixel_processor *opp,
+ const struct out_csc_color_matrix *tbl_entry)
+ {
+@@ -752,7 +823,7 @@ void opp_set_output_csc_adjustment(
+ */
+
+ REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
+- program_color_matrix(oppn10, tbl_entry);
++ oppn10_program_color_matrix(oppn10, tbl_entry);
+ }
+
+ static void opp_program_regamma_lut(
+@@ -778,20 +849,18 @@ static void opp_program_regamma_lut(
+
+ }
+
+-
+-
+-static bool opp_set_regamma_pwl(
++static bool oppn10_set_regamma_pwl(
+ struct output_pixel_processor *opp, const struct pwl_params *params)
+ {
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+- opp_power_on_regamma_lut(opp, true);
++ oppn10_power_on_regamma_lut(opp, true);
+ opp_configure_regamma_lut(opp, oppn10->is_write_to_ram_a_safe);
+
+ if (oppn10->is_write_to_ram_a_safe)
+- opp_program_regamma_luta_settings(opp, params);
++ opp_program_regamma_luta_settings(opp, params);
+ else
+- opp_program_regamma_lutb_settings(opp, params);
++ opp_program_regamma_lutb_settings(opp, params);
+
+ opp_program_regamma_lut(
+ opp, params->rgb_resulted, params->hw_points_num);
+@@ -799,7 +868,7 @@ static bool opp_set_regamma_pwl(
+ return true;
+ }
+
+-static void opp_set_stereo_polarity(
++static void oppn10_set_stereo_polarity(
+ struct output_pixel_processor *opp,
+ bool enable, bool rightEyePolarity)
+ {
+@@ -819,15 +888,15 @@ static void dcn10_opp_destroy(struct output_pixel_processor **opp)
+ }
+
+ static struct opp_funcs dcn10_opp_funcs = {
+- .opp_power_on_regamma_lut = opp_power_on_regamma_lut,
+- .opp_set_csc_adjustment = opp_set_output_csc_adjustment,
+- .opp_set_csc_default = opp_set_output_csc_default,
+- .opp_set_dyn_expansion = opp_set_dyn_expansion,
+- .opp_program_regamma_pwl = opp_set_regamma_pwl,
+- .opp_set_regamma_mode = opp_set_regamma_mode,
+- .opp_program_fmt = opp_program_fmt,
+- .opp_program_bit_depth_reduction = opp_program_bit_depth_reduction,
+- .opp_set_stereo_polarity = opp_set_stereo_polarity,
++ .opp_power_on_regamma_lut = oppn10_power_on_regamma_lut,
++ .opp_set_csc_adjustment = oppn10_set_output_csc_adjustment,
++ .opp_set_csc_default = oppn10_set_output_csc_default,
++ .opp_set_dyn_expansion = oppn10_set_dyn_expansion,
++ .opp_program_regamma_pwl = oppn10_set_regamma_pwl,
++ .opp_set_regamma_mode = oppn10_set_regamma_mode,
++ .opp_program_fmt = oppn10_program_fmt,
++ .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction,
++ .opp_set_stereo_polarity = oppn10_set_stereo_polarity,
+ .opp_destroy = dcn10_opp_destroy
+ };
+
+@@ -847,73 +916,3 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
+ oppn10->opp_mask = opp_mask;
+ }
+
+-
+-void program_color_matrix(struct dcn10_opp *oppn10,
+- const struct out_csc_color_matrix *tbl_entry)
+-{
+- uint32_t mode;
+-
+- REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
+-
+- if (tbl_entry == NULL) {
+- BREAK_TO_DEBUGGER();
+- return;
+- }
+-
+-
+- if (mode == 4) {
+- /*R*/
+- REG_SET_2(CM_OCSC_C11_C12, 0,
+- CM_OCSC_C11, tbl_entry->regval[0],
+- CM_OCSC_C12, tbl_entry->regval[1]);
+-
+- REG_SET_2(CM_OCSC_C13_C14, 0,
+- CM_OCSC_C13, tbl_entry->regval[2],
+- CM_OCSC_C14, tbl_entry->regval[3]);
+-
+- /*G*/
+- REG_SET_2(CM_OCSC_C21_C22, 0,
+- CM_OCSC_C21, tbl_entry->regval[4],
+- CM_OCSC_C22, tbl_entry->regval[5]);
+-
+- REG_SET_2(CM_OCSC_C23_C24, 0,
+- CM_OCSC_C23, tbl_entry->regval[6],
+- CM_OCSC_C24, tbl_entry->regval[7]);
+-
+- /*B*/
+- REG_SET_2(CM_OCSC_C31_C32, 0,
+- CM_OCSC_C31, tbl_entry->regval[8],
+- CM_OCSC_C32, tbl_entry->regval[9]);
+-
+- REG_SET_2(CM_OCSC_C33_C34, 0,
+- CM_OCSC_C33, tbl_entry->regval[10],
+- CM_OCSC_C34, tbl_entry->regval[11]);
+- } else {
+- /*R*/
+- REG_SET_2(CM_COMB_C11_C12, 0,
+- CM_COMB_C11, tbl_entry->regval[0],
+- CM_COMB_C12, tbl_entry->regval[1]);
+-
+- REG_SET_2(CM_COMB_C13_C14, 0,
+- CM_COMB_C13, tbl_entry->regval[2],
+- CM_COMB_C14, tbl_entry->regval[3]);
+-
+- /*G*/
+- REG_SET_2(CM_COMB_C21_C22, 0,
+- CM_COMB_C21, tbl_entry->regval[4],
+- CM_COMB_C22, tbl_entry->regval[5]);
+-
+- REG_SET_2(CM_COMB_C23_C24, 0,
+- CM_COMB_C23, tbl_entry->regval[6],
+- CM_COMB_C24, tbl_entry->regval[7]);
+-
+- /*B*/
+- REG_SET_2(CM_COMB_C31_C32, 0,
+- CM_COMB_C31, tbl_entry->regval[8],
+- CM_COMB_C32, tbl_entry->regval[9]);
+-
+- REG_SET_2(CM_COMB_C33_C34, 0,
+- CM_COMB_C33, tbl_entry->regval[10],
+- CM_COMB_C34, tbl_entry->regval[11]);
+- }
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+index 9cc4c5f..eb99c31 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+@@ -33,7 +33,19 @@
+ #define OPP_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+-#define OPP_DCN10_REG_LIST(id) \
++#define OPP_REG_LIST_DCN(id) \
++ SRI(OBUF_CONTROL, DSCL, id), \
++ SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
++ SRI(FMT_CONTROL, FMT, id), \
++ SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
++ SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
++ SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
++ SRI(FMT_CLAMP_CNTL, FMT, id), \
++ SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
++ SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id)
++
++#define OPP_REG_LIST_DCN10(id) \
++ OPP_REG_LIST_DCN(id), \
+ SRI(CM_OCSC_C11_C12, CM, id), \
+ SRI(CM_OCSC_C13_C14, CM, id), \
+ SRI(CM_OCSC_C21_C22, CM, id), \
+@@ -48,15 +60,6 @@
+ SRI(CM_COMB_C33_C34, CM, id), \
+ SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \
+ SRI(CM_RGAM_CONTROL, CM, id), \
+- SRI(OBUF_CONTROL, DSCL, id), \
+- SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
+- SRI(FMT_CONTROL, FMT, id), \
+- SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
+- SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
+- SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
+- SRI(FMT_CLAMP_CNTL, FMT, id), \
+- SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
+- SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
+ SRI(CM_OCSC_CONTROL, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
+@@ -120,7 +123,34 @@
+ SRI(CM_MEM_PWR_CTRL, CM, id), \
+ SRI(CM_RGAM_LUT_DATA, CM, id)
+
+-#define OPP_DCN10_MASK_SH_LIST(mask_sh) \
++
++#define OPP_MASK_SH_LIST_DCN(mask_sh) \
++ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
++ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
++ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
++ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
++ OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
++ OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
++ OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
++ OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
++ OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
++ OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
++ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
++ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
++ OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh)
++
++#define OPP_MASK_SH_LIST_DCN10(mask_sh) \
++ OPP_MASK_SH_LIST_DCN(mask_sh), \
++ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
+ OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
+ OPP_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
+ OPP_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \
+@@ -146,29 +176,6 @@
+ OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh), \
+ OPP_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
+- OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
+- OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
+- OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
+- OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
+- OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
+- OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
+- OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
+- OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
+- OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
+- OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
+- OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
+- OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
+- OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
+- OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \
+ OPP_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
+@@ -691,8 +698,4 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
+ const struct dcn10_opp_shift *opp_shift,
+ const struct dcn10_opp_mask *opp_mask);
+
+-void program_color_matrix(
+- struct dcn10_opp *oppn10,
+- const struct out_csc_color_matrix *tbl_entry);
+-
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index b0888a8..898b618 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -286,7 +286,7 @@ static const struct dcn10_ipp_mask ipp_mask = {
+
+ #define opp_regs(id)\
+ [id] = {\
+- OPP_DCN10_REG_LIST(id),\
++ OPP_REG_LIST_DCN10(id),\
+ }
+
+ static const struct dcn10_opp_registers opp_regs[] = {
+@@ -297,11 +297,11 @@ static const struct dcn10_opp_registers opp_regs[] = {
+ };
+
+ static const struct dcn10_opp_shift opp_shift = {
+- OPP_DCN10_MASK_SH_LIST(__SHIFT)
++ OPP_MASK_SH_LIST_DCN10(__SHIFT)
+ };
+
+ static const struct dcn10_opp_mask opp_mask = {
+- OPP_DCN10_MASK_SH_LIST(_MASK),
++ OPP_MASK_SH_LIST_DCN10(_MASK),
+ };
+
+ #define tf_regs(id)\
+--
+2.7.4
+