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authorAwais Belal <awais_belal@mentor.com>2018-11-14 14:44:19 +0500
committerAwais Belal <awais_belal@mentor.com>2018-11-14 14:44:22 +0500
commitbc139f16bfe8bc885b1505706faa9a4564c77ff2 (patch)
tree71fc44d89877e81f7b77f13db4b08980a32df2a7 /common/recipes-kernel/linux/linux-yocto-4.9.21/0064-x86-cpufeatures-Disentangle-MSR_SPEC_CTRL-enumeratio.patch
parent972275e4accf161f73fab3bbc7eb24fa95356e95 (diff)
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common: drop all the 4.9 kernel metadata
None of the BSPs are currently based on the 4.9 kernel so drop the common metadata as well. Signed-off-by: Awais Belal <awais_belal@mentor.com>
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.9.21/0064-x86-cpufeatures-Disentangle-MSR_SPEC_CTRL-enumeratio.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.9.21/0064-x86-cpufeatures-Disentangle-MSR_SPEC_CTRL-enumeratio.patch155
1 files changed, 0 insertions, 155 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.9.21/0064-x86-cpufeatures-Disentangle-MSR_SPEC_CTRL-enumeratio.patch b/common/recipes-kernel/linux/linux-yocto-4.9.21/0064-x86-cpufeatures-Disentangle-MSR_SPEC_CTRL-enumeratio.patch
deleted file mode 100644
index b84bc768..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.9.21/0064-x86-cpufeatures-Disentangle-MSR_SPEC_CTRL-enumeratio.patch
+++ /dev/null
@@ -1,155 +0,0 @@
-From 7731d9040d16874cb3fe11f52c4a238ab3fd658d Mon Sep 17 00:00:00 2001
-From: Thomas Gleixner <tglx@linutronix.de>
-Date: Thu, 10 May 2018 19:13:18 +0200
-Subject: [PATCH 64/93] x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration
- from IBRS
-
-commit 7eb8956a7fec3c1f0abc2a5517dada99ccc8a961 upstream
-
-The availability of the SPEC_CTRL MSR is enumerated by a CPUID bit on
-Intel and implied by IBRS or STIBP support on AMD. That's just confusing
-and in case an AMD CPU has IBRS not supported because the underlying
-problem has been fixed but has another bit valid in the SPEC_CTRL MSR,
-the thing falls apart.
-
-Add a synthetic feature bit X86_FEATURE_MSR_SPEC_CTRL to denote the
-availability on both Intel and AMD.
-
-While at it replace the boot_cpu_has() checks with static_cpu_has() where
-possible. This prevents late microcode loading from exposing SPEC_CTRL, but
-late loading is already very limited as it does not reevaluate the
-mitigation options and other bits and pieces. Having static_cpu_has() is
-the simplest and least fragile solution.
-
-Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-Reviewed-by: Borislav Petkov <bp@suse.de>
-Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
-Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/cpufeatures.h | 2 ++
- arch/x86/kernel/cpu/bugs.c | 18 +++++++++++-------
- arch/x86/kernel/cpu/common.c | 9 +++++++--
- arch/x86/kernel/cpu/intel.c | 1 +
- 4 files changed, 21 insertions(+), 9 deletions(-)
-
-diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
-index 059437a..ca0f33f 100644
---- a/arch/x86/include/asm/cpufeatures.h
-+++ b/arch/x86/include/asm/cpufeatures.h
-@@ -197,6 +197,8 @@
- #define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
- #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
-
-+#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
-+
- #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
-
- /* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */
-diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
-index 4f8c88e..59649310 100644
---- a/arch/x86/kernel/cpu/bugs.c
-+++ b/arch/x86/kernel/cpu/bugs.c
-@@ -63,7 +63,7 @@ void __init check_bugs(void)
- * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
- * init code as it is not enumerated and depends on the family.
- */
-- if (boot_cpu_has(X86_FEATURE_IBRS))
-+ if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
- rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
-
- /* Select the proper spectre mitigation before patching alternatives */
-@@ -144,7 +144,7 @@ u64 x86_spec_ctrl_get_default(void)
- {
- u64 msrval = x86_spec_ctrl_base;
-
-- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
- msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
- return msrval;
- }
-@@ -154,10 +154,12 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
- {
- u64 host = x86_spec_ctrl_base;
-
-- if (!boot_cpu_has(X86_FEATURE_IBRS))
-+ /* Is MSR_SPEC_CTRL implemented ? */
-+ if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
- return;
-
-- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-+ /* Intel controls SSB in MSR_SPEC_CTRL */
-+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
- host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
-
- if (host != guest_spec_ctrl)
-@@ -169,10 +171,12 @@ void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
- {
- u64 host = x86_spec_ctrl_base;
-
-- if (!boot_cpu_has(X86_FEATURE_IBRS))
-+ /* Is MSR_SPEC_CTRL implemented ? */
-+ if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
- return;
-
-- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-+ /* Intel controls SSB in MSR_SPEC_CTRL */
-+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
- host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
-
- if (host != guest_spec_ctrl)
-@@ -630,7 +634,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
-
- void x86_spec_ctrl_setup_ap(void)
- {
-- if (boot_cpu_has(X86_FEATURE_IBRS))
-+ if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
- x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
-
- if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
-diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
-index 67bfa3c..04362282 100644
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -729,19 +729,24 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
- if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
- set_cpu_cap(c, X86_FEATURE_IBRS);
- set_cpu_cap(c, X86_FEATURE_IBPB);
-+ set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
- }
-
- if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
- set_cpu_cap(c, X86_FEATURE_STIBP);
-
-- if (cpu_has(c, X86_FEATURE_AMD_IBRS))
-+ if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
- set_cpu_cap(c, X86_FEATURE_IBRS);
-+ set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
-+ }
-
- if (cpu_has(c, X86_FEATURE_AMD_IBPB))
- set_cpu_cap(c, X86_FEATURE_IBPB);
-
-- if (cpu_has(c, X86_FEATURE_AMD_STIBP))
-+ if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
- set_cpu_cap(c, X86_FEATURE_STIBP);
-+ set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
-+ }
- }
-
- void get_cpu_cap(struct cpuinfo_x86 *c)
-diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
-index 047adaa..7f495e8 100644
---- a/arch/x86/kernel/cpu/intel.c
-+++ b/arch/x86/kernel/cpu/intel.c
-@@ -153,6 +153,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
- setup_clear_cpu_cap(X86_FEATURE_IBPB);
- setup_clear_cpu_cap(X86_FEATURE_STIBP);
- setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
-+ setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
- setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
- setup_clear_cpu_cap(X86_FEATURE_SSBD);
- }
---
-2.7.4
-