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authorAwais Belal <awais_belal@mentor.com>2018-11-14 14:44:19 +0500
committerAwais Belal <awais_belal@mentor.com>2018-11-14 14:44:22 +0500
commitbc139f16bfe8bc885b1505706faa9a4564c77ff2 (patch)
tree71fc44d89877e81f7b77f13db4b08980a32df2a7 /common/recipes-kernel/linux/linux-yocto-4.9.21/0057-x86-bugs-Rename-_RDS-to-_SSBD.patch
parent972275e4accf161f73fab3bbc7eb24fa95356e95 (diff)
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common: drop all the 4.9 kernel metadata
None of the BSPs are currently based on the 4.9 kernel so drop the common metadata as well. Signed-off-by: Awais Belal <awais_belal@mentor.com>
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.9.21/0057-x86-bugs-Rename-_RDS-to-_SSBD.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.9.21/0057-x86-bugs-Rename-_RDS-to-_SSBD.patch405
1 files changed, 0 insertions, 405 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.9.21/0057-x86-bugs-Rename-_RDS-to-_SSBD.patch b/common/recipes-kernel/linux/linux-yocto-4.9.21/0057-x86-bugs-Rename-_RDS-to-_SSBD.patch
deleted file mode 100644
index 189588aa..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.9.21/0057-x86-bugs-Rename-_RDS-to-_SSBD.patch
+++ /dev/null
@@ -1,405 +0,0 @@
-From 4bb9a717246aa3019a3d97904e29c4da0bfc37f9 Mon Sep 17 00:00:00 2001
-From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
-Date: Wed, 9 May 2018 21:41:38 +0200
-Subject: [PATCH 57/93] x86/bugs: Rename _RDS to _SSBD
-
-commit 9f65fb29374ee37856dbad847b4e121aab72b510 upstream
-
-Intel collateral will reference the SSB mitigation bit in IA32_SPEC_CTL[2]
-as SSBD (Speculative Store Bypass Disable).
-
-Hence changing it.
-
-It is unclear yet what the MSR_IA32_ARCH_CAPABILITIES (0x10a) Bit(4) name
-is going to be. Following the rename it would be SSBD_NO but that rolls out
-to Speculative Store Bypass Disable No.
-
-Also fixed the missing space in X86_FEATURE_AMD_SSBD.
-
-[ tglx: Fixup x86_amd_rds_enable() and rds_tif_to_amd_ls_cfg() as well ]
-
-Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
-Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-
-Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/cpufeatures.h | 4 ++--
- arch/x86/include/asm/msr-index.h | 10 +++++-----
- arch/x86/include/asm/spec-ctrl.h | 12 ++++++------
- arch/x86/include/asm/thread_info.h | 6 +++---
- arch/x86/kernel/cpu/amd.c | 14 +++++++-------
- arch/x86/kernel/cpu/bugs.c | 36 ++++++++++++++++++------------------
- arch/x86/kernel/cpu/common.c | 2 +-
- arch/x86/kernel/cpu/intel.c | 2 +-
- arch/x86/kernel/process.c | 8 ++++----
- arch/x86/kvm/cpuid.c | 2 +-
- arch/x86/kvm/cpuid.h | 2 +-
- arch/x86/kvm/vmx.c | 2 +-
- 12 files changed, 50 insertions(+), 50 deletions(-)
-
-diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
-index 8797069..0ed8ea5 100644
---- a/arch/x86/include/asm/cpufeatures.h
-+++ b/arch/x86/include/asm/cpufeatures.h
-@@ -205,7 +205,7 @@
- #define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
- #define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
- #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
--#define X86_FEATURE_AMD_RDS (7*32+24) /* "" AMD RDS implementation */
-+#define X86_FEATURE_AMD_SSBD (7*32+24) /* "" AMD SSBD implementation */
-
- /* Virtualization flags: Linux defined, word 8 */
- #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
-@@ -308,7 +308,7 @@
- #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
- #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
- #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
--#define X86_FEATURE_RDS (18*32+31) /* Reduced Data Speculation */
-+#define X86_FEATURE_SSBD (18*32+31) /* Speculative Store Bypass Disable */
-
- /*
- * BUG word(s)
-diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
-index 7ad3ed9..0145a0b 100644
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -40,8 +40,8 @@
- #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
- #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */
- #define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */
--#define SPEC_CTRL_RDS_SHIFT 2 /* Reduced Data Speculation bit */
--#define SPEC_CTRL_RDS (1 << SPEC_CTRL_RDS_SHIFT) /* Reduced Data Speculation */
-+#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
-+#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
-
- #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
- #define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */
-@@ -63,10 +63,10 @@
- #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
- #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
- #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
--#define ARCH_CAP_RDS_NO (1 << 4) /*
-+#define ARCH_CAP_SSBD_NO (1 << 4) /*
- * Not susceptible to Speculative Store Bypass
-- * attack, so no Reduced Data Speculation control
-- * required.
-+ * attack, so no Speculative Store Bypass
-+ * control required.
- */
-
- #define MSR_IA32_BBL_CR_CTL 0x00000119
-diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h
-index 45ef00a..dc21209 100644
---- a/arch/x86/include/asm/spec-ctrl.h
-+++ b/arch/x86/include/asm/spec-ctrl.h
-@@ -17,20 +17,20 @@ extern void x86_spec_ctrl_restore_host(u64);
-
- /* AMD specific Speculative Store Bypass MSR data */
- extern u64 x86_amd_ls_cfg_base;
--extern u64 x86_amd_ls_cfg_rds_mask;
-+extern u64 x86_amd_ls_cfg_ssbd_mask;
-
- /* The Intel SPEC CTRL MSR base value cache */
- extern u64 x86_spec_ctrl_base;
-
--static inline u64 rds_tif_to_spec_ctrl(u64 tifn)
-+static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
- {
-- BUILD_BUG_ON(TIF_RDS < SPEC_CTRL_RDS_SHIFT);
-- return (tifn & _TIF_RDS) >> (TIF_RDS - SPEC_CTRL_RDS_SHIFT);
-+ BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
-+ return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
- }
-
--static inline u64 rds_tif_to_amd_ls_cfg(u64 tifn)
-+static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
- {
-- return (tifn & _TIF_RDS) ? x86_amd_ls_cfg_rds_mask : 0ULL;
-+ return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
- }
-
- extern void speculative_store_bypass_update(void);
-diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
-index 661afac..2d8788a 100644
---- a/arch/x86/include/asm/thread_info.h
-+++ b/arch/x86/include/asm/thread_info.h
-@@ -83,7 +83,7 @@ struct thread_info {
- #define TIF_SIGPENDING 2 /* signal pending */
- #define TIF_NEED_RESCHED 3 /* rescheduling necessary */
- #define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/
--#define TIF_RDS 5 /* Reduced data speculation */
-+#define TIF_SSBD 5 /* Reduced data speculation */
- #define TIF_SYSCALL_EMU 6 /* syscall emulation active */
- #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
- #define TIF_SECCOMP 8 /* secure computing */
-@@ -107,7 +107,7 @@ struct thread_info {
- #define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
- #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
- #define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
--#define _TIF_RDS (1 << TIF_RDS)
-+#define _TIF_SSBD (1 << TIF_SSBD)
- #define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
- #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
- #define _TIF_SECCOMP (1 << TIF_SECCOMP)
-@@ -141,7 +141,7 @@ struct thread_info {
-
- /* flags to check in __switch_to() */
- #define _TIF_WORK_CTXSW \
-- (_TIF_IO_BITMAP|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_RDS)
-+ (_TIF_IO_BITMAP|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_SSBD)
-
- #define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
- #define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)
-diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
-index a176c81..acb2fcc 100644
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -555,12 +555,12 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
- }
- /*
- * Try to cache the base value so further operations can
-- * avoid RMW. If that faults, do not enable RDS.
-+ * avoid RMW. If that faults, do not enable SSBD.
- */
- if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
-- setup_force_cpu_cap(X86_FEATURE_RDS);
-- setup_force_cpu_cap(X86_FEATURE_AMD_RDS);
-- x86_amd_ls_cfg_rds_mask = 1ULL << bit;
-+ setup_force_cpu_cap(X86_FEATURE_SSBD);
-+ setup_force_cpu_cap(X86_FEATURE_AMD_SSBD);
-+ x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
- }
- }
- }
-@@ -849,9 +849,9 @@ static void init_amd(struct cpuinfo_x86 *c)
- if (!cpu_has(c, X86_FEATURE_XENPV))
- set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
-
-- if (boot_cpu_has(X86_FEATURE_AMD_RDS)) {
-- set_cpu_cap(c, X86_FEATURE_RDS);
-- set_cpu_cap(c, X86_FEATURE_AMD_RDS);
-+ if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) {
-+ set_cpu_cap(c, X86_FEATURE_SSBD);
-+ set_cpu_cap(c, X86_FEATURE_AMD_SSBD);
- }
- }
-
-diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
-index 9a3bb65..ae6f9ba 100644
---- a/arch/x86/kernel/cpu/bugs.c
-+++ b/arch/x86/kernel/cpu/bugs.c
-@@ -44,10 +44,10 @@ static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
-
- /*
- * AMD specific MSR info for Speculative Store Bypass control.
-- * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
-+ * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
- */
- u64 __ro_after_init x86_amd_ls_cfg_base;
--u64 __ro_after_init x86_amd_ls_cfg_rds_mask;
-+u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
-
- void __init check_bugs(void)
- {
-@@ -145,7 +145,7 @@ u64 x86_spec_ctrl_get_default(void)
- u64 msrval = x86_spec_ctrl_base;
-
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-- msrval |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
-+ msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
- return msrval;
- }
- EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
-@@ -158,7 +158,7 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
- return;
-
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-- host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
-+ host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
-
- if (host != guest_spec_ctrl)
- wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
-@@ -173,18 +173,18 @@ void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
- return;
-
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-- host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
-+ host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
-
- if (host != guest_spec_ctrl)
- wrmsrl(MSR_IA32_SPEC_CTRL, host);
- }
- EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
-
--static void x86_amd_rds_enable(void)
-+static void x86_amd_ssb_disable(void)
- {
-- u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_mask;
-+ u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
-
-- if (boot_cpu_has(X86_FEATURE_AMD_RDS))
-+ if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
- wrmsrl(MSR_AMD64_LS_CFG, msrval);
- }
-
-@@ -472,7 +472,7 @@ static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void)
- enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
- enum ssb_mitigation_cmd cmd;
-
-- if (!boot_cpu_has(X86_FEATURE_RDS))
-+ if (!boot_cpu_has(X86_FEATURE_SSBD))
- return mode;
-
- cmd = ssb_parse_cmdline();
-@@ -506,7 +506,7 @@ static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void)
- /*
- * We have three CPU feature flags that are in play here:
- * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
-- * - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
-+ * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
- * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
- */
- if (mode == SPEC_STORE_BYPASS_DISABLE) {
-@@ -517,12 +517,12 @@ static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void)
- */
- switch (boot_cpu_data.x86_vendor) {
- case X86_VENDOR_INTEL:
-- x86_spec_ctrl_base |= SPEC_CTRL_RDS;
-- x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS;
-- x86_spec_ctrl_set(SPEC_CTRL_RDS);
-+ x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
-+ x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
-+ x86_spec_ctrl_set(SPEC_CTRL_SSBD);
- break;
- case X86_VENDOR_AMD:
-- x86_amd_rds_enable();
-+ x86_amd_ssb_disable();
- break;
- }
- }
-@@ -555,16 +555,16 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
- if (task_spec_ssb_force_disable(task))
- return -EPERM;
- task_clear_spec_ssb_disable(task);
-- update = test_and_clear_tsk_thread_flag(task, TIF_RDS);
-+ update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
- break;
- case PR_SPEC_DISABLE:
- task_set_spec_ssb_disable(task);
-- update = !test_and_set_tsk_thread_flag(task, TIF_RDS);
-+ update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
- break;
- case PR_SPEC_FORCE_DISABLE:
- task_set_spec_ssb_disable(task);
- task_set_spec_ssb_force_disable(task);
-- update = !test_and_set_tsk_thread_flag(task, TIF_RDS);
-+ update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
- break;
- default:
- return -ERANGE;
-@@ -634,7 +634,7 @@ void x86_spec_ctrl_setup_ap(void)
- x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
-
- if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
-- x86_amd_rds_enable();
-+ x86_amd_ssb_disable();
- }
-
- #ifdef CONFIG_SYSFS
-diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
-index beb1da8..d0dd736 100644
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -911,7 +911,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
- rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
-
- if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
-- !(ia32_cap & ARCH_CAP_RDS_NO))
-+ !(ia32_cap & ARCH_CAP_SSBD_NO))
- setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
-
- if (x86_match_cpu(cpu_no_speculation))
-diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
-index f15aea6..047adaa 100644
---- a/arch/x86/kernel/cpu/intel.c
-+++ b/arch/x86/kernel/cpu/intel.c
-@@ -154,7 +154,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
- setup_clear_cpu_cap(X86_FEATURE_STIBP);
- setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
- setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
-- setup_clear_cpu_cap(X86_FEATURE_RDS);
-+ setup_clear_cpu_cap(X86_FEATURE_SSBD);
- }
-
- /*
-diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
-index 9c48e18..c344230 100644
---- a/arch/x86/kernel/process.c
-+++ b/arch/x86/kernel/process.c
-@@ -207,11 +207,11 @@ static __always_inline void __speculative_store_bypass_update(unsigned long tifn
- {
- u64 msr;
-
-- if (static_cpu_has(X86_FEATURE_AMD_RDS)) {
-- msr = x86_amd_ls_cfg_base | rds_tif_to_amd_ls_cfg(tifn);
-+ if (static_cpu_has(X86_FEATURE_AMD_SSBD)) {
-+ msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
- wrmsrl(MSR_AMD64_LS_CFG, msr);
- } else {
-- msr = x86_spec_ctrl_base | rds_tif_to_spec_ctrl(tifn);
-+ msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
- wrmsrl(MSR_IA32_SPEC_CTRL, msr);
- }
- }
-@@ -250,7 +250,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
- if ((tifp ^ tifn) & _TIF_NOTSC)
- cr4_toggle_bits(X86_CR4_TSD);
-
-- if ((tifp ^ tifn) & _TIF_RDS)
-+ if ((tifp ^ tifn) & _TIF_SSBD)
- __speculative_store_bypass_update(tifn);
- }
-
-diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
-index 237e926..db95637 100644
---- a/arch/x86/kvm/cpuid.c
-+++ b/arch/x86/kvm/cpuid.c
-@@ -382,7 +382,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
-
- /* cpuid 7.0.edx*/
- const u32 kvm_cpuid_7_0_edx_x86_features =
-- F(SPEC_CTRL) | F(RDS) | F(ARCH_CAPABILITIES);
-+ F(SPEC_CTRL) | F(SSBD) | F(ARCH_CAPABILITIES);
-
- /* all calls to cpuid_count() should be made on the same cpu */
- get_cpu();
-diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
-index 39dd457..72551c5 100644
---- a/arch/x86/kvm/cpuid.h
-+++ b/arch/x86/kvm/cpuid.h
-@@ -171,7 +171,7 @@ static inline bool guest_cpuid_has_spec_ctrl(struct kvm_vcpu *vcpu)
- if (best && (best->ebx & bit(X86_FEATURE_IBRS)))
- return true;
- best = kvm_find_cpuid_entry(vcpu, 7, 0);
-- return best && (best->edx & (bit(X86_FEATURE_SPEC_CTRL) | bit(X86_FEATURE_RDS)));
-+ return best && (best->edx & (bit(X86_FEATURE_SPEC_CTRL) | bit(X86_FEATURE_SSBD)));
- }
-
- static inline bool guest_cpuid_has_arch_capabilities(struct kvm_vcpu *vcpu)
-diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
-index 17199dc..c7df5c4 100644
---- a/arch/x86/kvm/vmx.c
-+++ b/arch/x86/kvm/vmx.c
-@@ -3133,7 +3133,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
- return 1;
-
- /* The STIBP bit doesn't fault even if it's not advertised */
-- if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_RDS))
-+ if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
- return 1;
-
- vmx->spec_ctrl = data;
---
-2.7.4
-