aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch
diff options
context:
space:
mode:
authorWade Farnsworth <wfarnsworth@users.noreply.github.com>2019-10-22 08:08:07 -0700
committerGitHub <noreply@github.com>2019-10-22 08:08:07 -0700
commit8e0cf9ee43840bd7ee004412129ba4aa055f5fc8 (patch)
treeb13804093e413307097cd6788ccdc8b062084013 /common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch
parent9e1e1da00d8ef569d83a7a742a734dbbf5e0bd13 (diff)
parent3f8062a03dc1d1d5fa386e1f1ca59d56b86a85d1 (diff)
downloadmeta-amd-master.tar.gz
meta-amd-master.tar.bz2
meta-amd-master.zip
Merge pull request #661 from ArsalanHAwan/master-merge-warriorHEADmaster
master: merge warrior
Diffstat (limited to 'common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch')
-rw-r--r--common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch124
1 files changed, 0 insertions, 124 deletions
diff --git a/common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch b/common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch
deleted file mode 100644
index b2c91d3f..00000000
--- a/common/recipes-kernel/linux/files/0285-drm-amd-Adding-IVSRC-register-headers.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From c580f8426eb04e18ed9373ab4f420b5e05e6b63e Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Tue, 24 Nov 2015 10:51:51 -0500
-Subject: [PATCH 0285/1110] drm/amd: Adding IVSRC register headers
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../drm/amd/include/ivsrcid/ivsrcid_vislands30.h | 102 +++++++++++++++++++++
- 1 file changed, 102 insertions(+)
- create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
-
-diff --git a/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h b/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
-new file mode 100644
-index 0000000..d21c6b1
---- /dev/null
-+++ b/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
-@@ -0,0 +1,102 @@
-+/*
-+ * Volcanic Islands IV SRC Register documentation
-+ *
-+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef _IVSRCID_VISLANDS30_H_
-+#define _IVSRCID_VISLANDS30_H_
-+
-+
-+// IV Source IDs
-+
-+#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07
-+#define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0
-+
-+#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08
-+#define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0
-+
-+#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09
-+#define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0
-+
-+#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a
-+#define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0
-+
-+#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b
-+#define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0
-+
-+#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c
-+#define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP 0
-+
-+#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d
-+#define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT 0
-+
-+#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e
-+#define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP 0
-+
-+#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f
-+#define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT 0
-+
-+#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10
-+#define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP 0
-+
-+#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11
-+#define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT 0
-+
-+#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12
-+#define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP 0
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A 0
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B 1
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C 2
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D 3
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E 4
-+
-+#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F 5
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HPD_RX_A 6
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HPD_RX_B 7
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HPD_RX_C 8
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HPD_RX_D 9
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HPD_RX_E 10
-+
-+#define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a
-+#define VISLANDS30_IV_EXTID_HPD_RX_F 11
-+
-+#endif // _IVSRCID_VISLANDS30_H_
---
-2.7.4
-