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authorArsalan H. Awan <Arsalan_Awan@mentor.com>2019-08-28 13:44:37 +0500
committerArsalan H. Awan <Arsalan_Awan@mentor.com>2019-08-28 13:44:37 +0500
commit4149413febf799293758015e230e0ce865ed9cb5 (patch)
tree454771ead3a7e7ab134480b2356dea6dc6befa0b
parenta20d58805a858b6cea00f1c163ec93e6db04facf (diff)
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common: remove unused linux-yocto_4.4 & linux-yocto-rt_4.4 recipes
This removes the linux-yocto_4.4 & linux-yocto-rt_4.4 kernel recipes as we don't need them anymore. This also sets the PREFERRED_VERSION_linux-yocto ?= "4.14%" as default kernel for all bsps. We still have snowyowl and v1000 using the 4.14 kernel. r1000 has moved to 4.19 kernel. Signed-off-by: Arsalan H. Awan <Arsalan_Awan@mentor.com>
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-rw-r--r--common/recipes-kernel/linux/files/1051-drm-amd-dal-fixed-one-issue-found-by-static-analyzer.patch35
-rw-r--r--common/recipes-kernel/linux/files/1052-drm-amd-dal-Fix-audio-endpoints-incorrect-during-unp.patch420
-rw-r--r--common/recipes-kernel/linux/files/1053-drm-amd-dal-Change-reset-pipe_ctx-check-conditon.patch153
-rw-r--r--common/recipes-kernel/linux/files/1054-drm-amd-dal-increase-link-training-retry-delay-to-fi.patch103
-rw-r--r--common/recipes-kernel/linux/files/1055-drm-amd-dal-Move-gamma-program-DPP-after-DCHUB-follo.patch40
-rw-r--r--common/recipes-kernel/linux/files/1056-drm-amd-dal-On-resume-rewrite-the-MSTM-control-bits-.patch76
-rw-r--r--common/recipes-kernel/linux/files/1057-drm-amd-dal-Fix-wrong-audio-clock-after-resume.patch638
-rw-r--r--common/recipes-kernel/linux/files/1058-drm-amd-dal-Run-full-validate-for-virtual-connector.patch30
-rw-r--r--common/recipes-kernel/linux/files/1059-drm-amd-dal-Use-dce110-audio-for-dce112.patch620
-rw-r--r--common/recipes-kernel/linux/files/1060-drm-amd-dal-Add-mininum-display-clock-check-fixed-80.patch49
-rw-r--r--common/recipes-kernel/linux/files/1061-drm-amd-dal-Remove-empty-audio-base-class-functions.patch387
-rw-r--r--common/recipes-kernel/linux/files/1062-Revert-drm-amd-dal-dm-remove-LINUX_VERSION_CODE-chec.patch204
-rw-r--r--common/recipes-kernel/linux/files/1063-drm-amdgpu-add-pipeline-sync-for-compute-job.patch38
-rw-r--r--common/recipes-kernel/linux/files/1064-drm-amdgpu-fiji-set-UVD-CG-state-when-enabling-UVD-D.patch43
-rw-r--r--common/recipes-kernel/linux/files/1065-drm-amdgpu-uvd6-add-bypass-support-for-fiji-v2.patch63
-rw-r--r--common/recipes-kernel/linux/files/1066-drm-amdgpu-check-if-ring-emit_vm_flush-exists-in-vm-.patch35
-rw-r--r--common/recipes-kernel/linux/files/1067-drm-powerplay-add-missing-clockgating-callback-for-t.patch29
-rw-r--r--common/recipes-kernel/linux/files/1068-drm-amd-amdgpu-Convert-ring-debugfs-entries-to-binar.patch181
-rw-r--r--common/recipes-kernel/linux/files/1069-drm-amd-amdgpu-ring-debugfs-is-read-in-increments-of.patch35
-rw-r--r--common/recipes-kernel/linux/files/1070-drm-amd-amdgpu-Enable-CG-for-UVD6-on-Carrizo.patch30
-rw-r--r--common/recipes-kernel/linux/files/1071-drm-amd-dal-change-default-to-use-SW-i2c.patch50
-rw-r--r--common/recipes-kernel/linux/files/1072-drm-amdgpu-hdp-flush-inval-should-always-do.patch43
-rw-r--r--common/recipes-kernel/linux/files/1073-drm-amdgpu-two-minor-80-char-fixes.patch81
-rw-r--r--common/recipes-kernel/linux/files/1074-drm-amdgpu-make-the-VMID-owner-always-64bit.patch56
-rw-r--r--common/recipes-kernel/linux/files/1075-drm-amdgpu-remove-owner-cleanup-v2.patch52
-rw-r--r--common/recipes-kernel/linux/files/1076-drm-amdgpu-remove-define-for-reserved-client-ID.patch33
-rw-r--r--common/recipes-kernel/linux/files/1077-drm-amd-cleanup-DAL-spaces-and-tabs-v2.patch86
-rw-r--r--common/recipes-kernel/linux/files/1078-drm-amd-cleanup-remaining-spaces-and-tabs-v2.patch462
-rw-r--r--common/recipes-kernel/linux/files/1079-drm-amdgpu-fix-compilation-errors-during-backport.patch1247
-rw-r--r--common/recipes-kernel/linux/files/1080-drm-amdgpu-fix-num_rbs-exposed-to-userspace.patch31
-rw-r--r--common/recipes-kernel/linux/files/1081-drm-amd-amdgpu-make-sure-VCE-is-disabled-by-default.patch40
-rw-r--r--common/recipes-kernel/linux/files/1082-drm-amd-powerplay-make-sure-VCE-is-disabled-by-defau.patch45
-rw-r--r--common/recipes-kernel/linux/files/1083-1083-drm-amd-dal-remove-common-modes.patch.patch116
-rw-r--r--common/recipes-kernel/linux/files/1084-drm-amdgpu-gfx8-add-state-setup-for-CZ-ST-GFX-power-.patch240
-rw-r--r--common/recipes-kernel/linux/files/1085-drm-amdgpu-gfx8-add-powergating-support-for-CZ-ST.patch357
-rw-r--r--common/recipes-kernel/linux/files/1086-drm-amdgpu-gfx8-Add-serdes-wait-for-idle-in-CGCG-en-.patch31
-rw-r--r--common/recipes-kernel/linux/files/1087-drm-amdgpu-gfx8-fix-CP-jump-table-size.patch36
-rw-r--r--common/recipes-kernel/linux/files/1088-drm-amdgpu-gfx8-Enable-GFX-PG-on-CZ.patch42
-rw-r--r--common/recipes-kernel/linux/files/1089-drm-amd-amdgpu-Add-name-field-to-amd_ip_funcs.patch448
-rw-r--r--common/recipes-kernel/linux/files/1090-drm-amd-amdgpu-Added-more-named-DRM-info-messages-fo.patch105
-rw-r--r--common/recipes-kernel/linux/files/1091-drm-amdgpu-fix-staging-4.5-merge-error-for-pipeline-.patch60
-rw-r--r--common/recipes-kernel/linux/files/1092-drm-amd-dal-Properly-handle-vblank-on-S3-suspend-and.patch66
-rw-r--r--common/recipes-kernel/linux/files/1093-drm-amd-dal-S3-Move-vblank_off-to-before-CRTCs-are-d.patch103
-rw-r--r--common/recipes-kernel/linux/files/1094-drm-amd-dal-Not-releasing-target-during-suspend.patch55
-rw-r--r--common/recipes-kernel/linux/files/1095-drm-amdgpu-add-late_fini-for-ip_funcs.patch32
-rw-r--r--common/recipes-kernel/linux/files/1096-drm-amdgpu-impl-late_fini-for-amdgpu_pp_ip.patch55
-rw-r--r--common/recipes-kernel/linux/files/1097-drm-amdgpu-modify-sdma-start-sequence.patch122
-rw-r--r--common/recipes-kernel/linux/files/1098-drm-amd-dal-Revert-to-generic-list-iteration.patch39
-rw-r--r--common/recipes-kernel/linux/files/1099-drm-amdgpu-free-sync-ioctl-declaration.patch129
-rw-r--r--common/recipes-kernel/linux/files/1100-drm-amdgpu-drm_helper_resume_force_mode-is-only-work.patch34
-rw-r--r--common/recipes-kernel/linux/files/1101-drm-amdgpu-mode-restore-for-atomic-modesetting.patch310
-rw-r--r--common/recipes-kernel/linux/files/1103-drm-amdgpu-use-PCI_D3hot-for-PX-systems-without-dGPU.patch84
-rw-r--r--common/recipes-kernel/linux/files/1104-drm-amdgpu-add-amdgpu_irq_gpu_reset_resume_helper.patch71
-rw-r--r--common/recipes-kernel/linux/files/1105-drm-amdgpu-add-dm_display_resume-to-balance-dm_suspe.patch34
-rw-r--r--common/recipes-kernel/linux/files/1106-drm-amdgpu-dce8-fix-flash-with-white-screen-on-monit.patch123
-rw-r--r--common/recipes-kernel/linux/files/1107-drm-amdgpu-fix-UVD-enabled-display-after-system-resu.patch45
-rw-r--r--common/recipes-kernel/linux/files/1108-drm-amdgpu-fix-uvd-fini-mem-leak.patch79
-rw-r--r--common/recipes-kernel/linux/files/1109-drm-amdgpu-fix-system-randomly-reboots-after-login.patch26
-rw-r--r--common/recipes-kernel/linux/files/1110-drm-amdgpu-free-handles-after-fini-the-context.patch49
-rw-r--r--common/recipes-kernel/linux/files/1111-drm-amd-dal-return-page-flip-status-to-userspace.patch69
-rw-r--r--common/recipes-kernel/linux/files/1112-drm-amd-Indentation-of-the-code.patch4870
-rw-r--r--common/recipes-kernel/linux/files/1141-Fix-a-deadlock-affecting-ww_mutexes.patch121
-rw-r--r--common/recipes-kernel/linux/files/CVE-2016-5195.patch91
-rw-r--r--common/recipes-kernel/linux/files/console.cfg7
-rw-r--r--common/recipes-kernel/linux/files/disable-bluetooth.cfg1
-rw-r--r--common/recipes-kernel/linux/files/disable-intel-graphics.cfg2
-rw-r--r--common/recipes-kernel/linux/files/disable-kgdb.cfg1
-rw-r--r--common/recipes-kernel/linux/files/drm.cfg6
-rw-r--r--common/recipes-kernel/linux/files/efi-partition.cfg1
-rw-r--r--common/recipes-kernel/linux/files/enable-bluetooth.cfg13
-rw-r--r--common/recipes-kernel/linux/files/enable-imc.cfg2
-rw-r--r--common/recipes-kernel/linux/files/enable-kgdb.cfg3
-rw-r--r--common/recipes-kernel/linux/files/hid.cfg5
-rw-r--r--common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc1116
-rw-r--r--common/recipes-kernel/linux/files/logo.cfg1
-rw-r--r--common/recipes-kernel/linux/files/radeon-console.cfg3
-rw-r--r--common/recipes-kernel/linux/files/radeon-gpu-config.cfg2
-rw-r--r--common/recipes-kernel/linux/files/radeon-microcode.cfg2
-rw-r--r--common/recipes-kernel/linux/files/sound.cfg30
-rw-r--r--common/recipes-kernel/linux/files/usb-serial.cfg1
-rw-r--r--common/recipes-kernel/linux/files/wifi-drivers.cfg9
-rw-r--r--common/recipes-kernel/linux/linux-yocto-common_4.4.inc30
-rw-r--r--common/recipes-kernel/linux/linux-yocto-rt_4.4.bb36
-rw-r--r--common/recipes-kernel/linux/linux-yocto-rt_4.4.bbappend4
-rw-r--r--common/recipes-kernel/linux/linux-yocto_4.4.bb42
-rw-r--r--common/recipes-kernel/linux/linux-yocto_4.4.bbappend11
1140 files changed, 1 insertions, 527532 deletions
diff --git a/common/conf/machine/include/amd-common-configurations.inc b/common/conf/machine/include/amd-common-configurations.inc
index f1d39b7c..8134bad3 100644
--- a/common/conf/machine/include/amd-common-configurations.inc
+++ b/common/conf/machine/include/amd-common-configurations.inc
@@ -5,7 +5,7 @@ POKY_DEFAULT_DISTRO_FEATURES_remove = "wayland"
PREFERRED_PROVIDER_jpeg ?= "jpeg"
PREFERRED_PROVIDER_jpeg-native ?= "jpeg-native"
-PREFERRED_VERSION_linux-yocto ?= "4.4%"
+PREFERRED_VERSION_linux-yocto ?= "4.14%"
PREFERRED_VERSION_libav ?= "9.18"
PREFERRED_PROVIDER_llvm ?= "llvm9.0.0"
diff --git a/common/recipes-kernel/linux/files/0001-drm-Remove-unused-fbdev_list-members.patch b/common/recipes-kernel/linux/files/0001-drm-Remove-unused-fbdev_list-members.patch
deleted file mode 100644
index ac621aaf..00000000
--- a/common/recipes-kernel/linux/files/0001-drm-Remove-unused-fbdev_list-members.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 327138e09ccd825e24563b7fa787a3c50bb2c39f Mon Sep 17 00:00:00 2001
-From: Lukas Wunner <lukas@wunner.de>
-Date: Sun, 1 Nov 2015 14:22:00 +0100
-Subject: [PATCH 0001/1110] drm: Remove unused fbdev_list members
-
-I noticed that intel_fbdev->our_mode is unused. Introduced by
-79e539453b34 ("DRM: i915: add mode setting support").
-
-Then I noticed that intel_fbdev->fbdev_list is unused as well.
-Introduced by 386516744ba4 ("drm/fb: fix fbdev object model +
-cleanup properly.") in i915, nouveau and radeon.
-
-Subsequently cargo culted to amdgpu, ast, cirrus, qxl, udl,
-virtio and mgag200.
-
-Already removed from the latter with cc59487a05b1 ("drm/mgag200:
-'fbdev_list' in 'struct mga_fbdev' is not used").
-
-Remove it from the others.
-
-Signed-off-by: Lukas Wunner <lukas@wunner.de>
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-index 093a8c6..6fcbbcc 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-@@ -45,7 +45,6 @@
- struct amdgpu_fbdev {
- struct drm_fb_helper helper;
- struct amdgpu_framebuffer rfb;
-- struct list_head fbdev_list;
- struct amdgpu_device *adev;
- };
-
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0001-random-replace-non-blocking-pool-with-a-Chacha20-bas.patch b/common/recipes-kernel/linux/files/0001-random-replace-non-blocking-pool-with-a-Chacha20-bas.patch
deleted file mode 100644
index a1094e76..00000000
--- a/common/recipes-kernel/linux/files/0001-random-replace-non-blocking-pool-with-a-Chacha20-bas.patch
+++ /dev/null
@@ -1,801 +0,0 @@
-From 82abea15da5d7483c84071c43ad223d14f0a6cdd Mon Sep 17 00:00:00 2001
-From: Awais Belal <awais_belal@mentor.com>
-Date: Tue, 22 Nov 2016 17:54:08 +0500
-Subject: [PATCH] random: replace non-blocking pool with a Chacha20-based CRNG
-
-The CRNG is faster, and we don't pretend to track entropy usage in the
-CRNG any more.
-
-Signed-off-by: Theodore Ts'o <tytso@mit.edu>
-Backport-by: Awais Belal <awais_belal@mentor.com>
----
- crypto/chacha20_generic.c | 61 --------
- drivers/char/random.c | 378 +++++++++++++++++++++++++++++++++-------------
- include/crypto/chacha20.h | 1 +
- lib/Makefile | 2 +-
- lib/chacha20.c | 79 ++++++++++
- 5 files changed, 357 insertions(+), 164 deletions(-)
- create mode 100644 lib/chacha20.c
-
-diff --git a/crypto/chacha20_generic.c b/crypto/chacha20_generic.c
-index da9c899..1cab831 100644
---- a/crypto/chacha20_generic.c
-+++ b/crypto/chacha20_generic.c
-@@ -15,72 +15,11 @@
- #include <linux/module.h>
- #include <crypto/chacha20.h>
-
--static inline u32 rotl32(u32 v, u8 n)
--{
-- return (v << n) | (v >> (sizeof(v) * 8 - n));
--}
--
- static inline u32 le32_to_cpuvp(const void *p)
- {
- return le32_to_cpup(p);
- }
-
--static void chacha20_block(u32 *state, void *stream)
--{
-- u32 x[16], *out = stream;
-- int i;
--
-- for (i = 0; i < ARRAY_SIZE(x); i++)
-- x[i] = state[i];
--
-- for (i = 0; i < 20; i += 2) {
-- x[0] += x[4]; x[12] = rotl32(x[12] ^ x[0], 16);
-- x[1] += x[5]; x[13] = rotl32(x[13] ^ x[1], 16);
-- x[2] += x[6]; x[14] = rotl32(x[14] ^ x[2], 16);
-- x[3] += x[7]; x[15] = rotl32(x[15] ^ x[3], 16);
--
-- x[8] += x[12]; x[4] = rotl32(x[4] ^ x[8], 12);
-- x[9] += x[13]; x[5] = rotl32(x[5] ^ x[9], 12);
-- x[10] += x[14]; x[6] = rotl32(x[6] ^ x[10], 12);
-- x[11] += x[15]; x[7] = rotl32(x[7] ^ x[11], 12);
--
-- x[0] += x[4]; x[12] = rotl32(x[12] ^ x[0], 8);
-- x[1] += x[5]; x[13] = rotl32(x[13] ^ x[1], 8);
-- x[2] += x[6]; x[14] = rotl32(x[14] ^ x[2], 8);
-- x[3] += x[7]; x[15] = rotl32(x[15] ^ x[3], 8);
--
-- x[8] += x[12]; x[4] = rotl32(x[4] ^ x[8], 7);
-- x[9] += x[13]; x[5] = rotl32(x[5] ^ x[9], 7);
-- x[10] += x[14]; x[6] = rotl32(x[6] ^ x[10], 7);
-- x[11] += x[15]; x[7] = rotl32(x[7] ^ x[11], 7);
--
-- x[0] += x[5]; x[15] = rotl32(x[15] ^ x[0], 16);
-- x[1] += x[6]; x[12] = rotl32(x[12] ^ x[1], 16);
-- x[2] += x[7]; x[13] = rotl32(x[13] ^ x[2], 16);
-- x[3] += x[4]; x[14] = rotl32(x[14] ^ x[3], 16);
--
-- x[10] += x[15]; x[5] = rotl32(x[5] ^ x[10], 12);
-- x[11] += x[12]; x[6] = rotl32(x[6] ^ x[11], 12);
-- x[8] += x[13]; x[7] = rotl32(x[7] ^ x[8], 12);
-- x[9] += x[14]; x[4] = rotl32(x[4] ^ x[9], 12);
--
-- x[0] += x[5]; x[15] = rotl32(x[15] ^ x[0], 8);
-- x[1] += x[6]; x[12] = rotl32(x[12] ^ x[1], 8);
-- x[2] += x[7]; x[13] = rotl32(x[13] ^ x[2], 8);
-- x[3] += x[4]; x[14] = rotl32(x[14] ^ x[3], 8);
--
-- x[10] += x[15]; x[5] = rotl32(x[5] ^ x[10], 7);
-- x[11] += x[12]; x[6] = rotl32(x[6] ^ x[11], 7);
-- x[8] += x[13]; x[7] = rotl32(x[7] ^ x[8], 7);
-- x[9] += x[14]; x[4] = rotl32(x[4] ^ x[9], 7);
-- }
--
-- for (i = 0; i < ARRAY_SIZE(x); i++)
-- out[i] = cpu_to_le32(x[i] + state[i]);
--
-- state[12]++;
--}
--
- static void chacha20_docrypt(u32 *state, u8 *dst, const u8 *src,
- unsigned int bytes)
- {
-diff --git a/drivers/char/random.c b/drivers/char/random.c
-index 491a4dc..9088000 100644
---- a/drivers/char/random.c
-+++ b/drivers/char/random.c
-@@ -260,6 +260,7 @@
- #include <linux/irq.h>
- #include <linux/syscalls.h>
- #include <linux/completion.h>
-+#include <crypto/chacha20.h>
-
- #include <asm/processor.h>
- #include <asm/uaccess.h>
-@@ -412,6 +413,31 @@ static struct fasync_struct *fasync;
- static DEFINE_SPINLOCK(random_ready_list_lock);
- static LIST_HEAD(random_ready_list);
-
-+struct crng_state {
-+ __u32 state[16];
-+ unsigned long init_time;
-+ spinlock_t lock;
-+};
-+
-+struct crng_state primary_crng = {
-+ .lock = __SPIN_LOCK_UNLOCKED(primary_crng.lock),
-+};
-+
-+/*
-+ * crng_init = 0 --> Uninitialized
-+ * 1 --> Initialized
-+ * 2 --> Initialized from input_pool
-+ *
-+ * crng_init is protected by primary_crng->lock, and only increases
-+ * its value (from 0->1->2).
-+ */
-+static int crng_init = 0;
-+#define crng_ready() (likely(crng_init > 0))
-+static int crng_init_cnt = 0;
-+#define CRNG_INIT_CNT_THRESH (2*CHACHA20_KEY_SIZE)
-+static void extract_crng(__u8 out[CHACHA20_BLOCK_SIZE]);
-+static void process_random_ready_list(void);
-+
- /**********************************************************************
- *
- * OS independent entropy store. Here are the functions which handle
-@@ -441,10 +467,15 @@ struct entropy_store {
- __u8 last_data[EXTRACT_SIZE];
- };
-
-+static ssize_t extract_entropy(struct entropy_store *r, void *buf,
-+ size_t nbytes, int min, int rsvd);
-+static ssize_t _extract_entropy(struct entropy_store *r, void *buf,
-+ size_t nbytes, int fips);
-+
-+static void crng_reseed(struct crng_state *crng, struct entropy_store *r);
- static void push_to_pool(struct work_struct *work);
- static __u32 input_pool_data[INPUT_POOL_WORDS];
- static __u32 blocking_pool_data[OUTPUT_POOL_WORDS];
--static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS];
-
- static struct entropy_store input_pool = {
- .poolinfo = &poolinfo_table[0],
-@@ -465,16 +496,6 @@ static struct entropy_store blocking_pool = {
- push_to_pool),
- };
-
--static struct entropy_store nonblocking_pool = {
-- .poolinfo = &poolinfo_table[1],
-- .name = "nonblocking",
-- .pull = &input_pool,
-- .lock = __SPIN_LOCK_UNLOCKED(nonblocking_pool.lock),
-- .pool = nonblocking_pool_data,
-- .push_work = __WORK_INITIALIZER(nonblocking_pool.push_work,
-- push_to_pool),
--};
--
- static __u32 const twist_table[8] = {
- 0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158,
- 0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 };
-@@ -677,12 +698,6 @@ retry:
- if (!r->initialized && r->entropy_total > 128) {
- r->initialized = 1;
- r->entropy_total = 0;
-- if (r == &nonblocking_pool) {
-- prandom_reseed_late();
-- process_random_ready_list();
-- wake_up_all(&urandom_init_wait);
-- pr_notice("random: %s pool is initialized\n", r->name);
-- }
- }
-
- trace_credit_entropy_bits(r->name, nbits,
-@@ -692,30 +707,27 @@ retry:
- if (r == &input_pool) {
- int entropy_bits = entropy_count >> ENTROPY_SHIFT;
-
-+ if (crng_init < 2 && entropy_bits >= 128) {
-+ crng_reseed(&primary_crng, r);
-+ entropy_bits = r->entropy_count >> ENTROPY_SHIFT;
-+ }
-+
- /* should we wake readers? */
- if (entropy_bits >= random_read_wakeup_bits) {
- wake_up_interruptible(&random_read_wait);
- kill_fasync(&fasync, SIGIO, POLL_IN);
- }
- /* If the input pool is getting full, send some
-- * entropy to the two output pools, flipping back and
-- * forth between them, until the output pools are 75%
-- * full.
-+ * entropy to the blocking pool until it is 75% full.
- */
- if (entropy_bits > random_write_wakeup_bits &&
- r->initialized &&
- r->entropy_total >= 2*random_read_wakeup_bits) {
-- static struct entropy_store *last = &blocking_pool;
- struct entropy_store *other = &blocking_pool;
-
-- if (last == &blocking_pool)
-- other = &nonblocking_pool;
- if (other->entropy_count <=
-- 3 * other->poolinfo->poolfracbits / 4)
-- last = other;
-- if (last->entropy_count <=
-- 3 * last->poolinfo->poolfracbits / 4) {
-- schedule_work(&last->push_work);
-+ 3 * other->poolinfo->poolfracbits / 4) {
-+ schedule_work(&other->push_work);
- r->entropy_total = 0;
- }
- }
-@@ -738,6 +750,152 @@ static int credit_entropy_bits_safe(struct entropy_store *r, int nbits)
-
- /*********************************************************************
- *
-+ * CRNG using CHACHA20
-+ *
-+ *********************************************************************/
-+
-+#define CRNG_RESEED_INTERVAL (300*HZ)
-+
-+static DECLARE_WAIT_QUEUE_HEAD(crng_init_wait);
-+
-+static void crng_initialize(struct crng_state *crng)
-+{
-+ int i;
-+ unsigned long rv;
-+
-+ memcpy(&crng->state[0], "expand 32-byte k", 16);
-+ if (crng == &primary_crng)
-+ _extract_entropy(&input_pool, &crng->state[4],
-+ sizeof(__u32) * 12, 0);
-+ else
-+ get_random_bytes(&crng->state[4], sizeof(__u32) * 12);
-+ for (i = 4; i < 16; i++) {
-+ if (!arch_get_random_seed_long(&rv) &&
-+ !arch_get_random_long(&rv))
-+ rv = random_get_entropy();
-+ crng->state[i] ^= rv;
-+ }
-+ crng->init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
-+}
-+
-+static int crng_fast_load(const char *cp, size_t len)
-+{
-+ unsigned long flags;
-+ char *p;
-+
-+ if (!spin_trylock_irqsave(&primary_crng.lock, flags))
-+ return 0;
-+ if (crng_ready()) {
-+ spin_unlock_irqrestore(&primary_crng.lock, flags);
-+ return 0;
-+ }
-+ p = (unsigned char *) &primary_crng.state[4];
-+ while (len > 0 && crng_init_cnt < CRNG_INIT_CNT_THRESH) {
-+ p[crng_init_cnt % CHACHA20_KEY_SIZE] ^= *cp;
-+ cp++; crng_init_cnt++; len--;
-+ }
-+ if (crng_init_cnt >= CRNG_INIT_CNT_THRESH) {
-+ crng_init = 1;
-+ wake_up_interruptible(&crng_init_wait);
-+ pr_notice("random: fast init done\n");
-+ }
-+ spin_unlock_irqrestore(&primary_crng.lock, flags);
-+ return 1;
-+}
-+
-+static void crng_reseed(struct crng_state *crng, struct entropy_store *r)
-+{
-+ unsigned long flags;
-+ int i, num;
-+ union {
-+ __u8 block[CHACHA20_BLOCK_SIZE];
-+ __u32 key[8];
-+ } buf;
-+
-+ if (r) {
-+ num = extract_entropy(r, &buf, 32, 16, 0);
-+ if (num == 0)
-+ return;
-+ } else
-+ extract_crng(buf.block);
-+ spin_lock_irqsave(&primary_crng.lock, flags);
-+ for (i = 0; i < 8; i++) {
-+ unsigned long rv;
-+ if (!arch_get_random_seed_long(&rv) &&
-+ !arch_get_random_long(&rv))
-+ rv = random_get_entropy();
-+ crng->state[i+4] ^= buf.key[i] ^ rv;
-+ }
-+ memzero_explicit(&buf, sizeof(buf));
-+ crng->init_time = jiffies;
-+ if (crng == &primary_crng && crng_init < 2) {
-+ crng_init = 2;
-+ process_random_ready_list();
-+ wake_up_interruptible(&crng_init_wait);
-+ pr_notice("random: crng init done\n");
-+ }
-+ spin_unlock_irqrestore(&primary_crng.lock, flags);
-+}
-+
-+static inline void crng_wait_ready(void)
-+{
-+ wait_event_interruptible(crng_init_wait, crng_ready());
-+}
-+
-+static void extract_crng(__u8 out[CHACHA20_BLOCK_SIZE])
-+{
-+ unsigned long v, flags;
-+ struct crng_state *crng = &primary_crng;
-+
-+ if (crng_init > 1 &&
-+ time_after(jiffies, crng->init_time + CRNG_RESEED_INTERVAL))
-+ crng_reseed(crng, &input_pool);
-+ spin_lock_irqsave(&crng->lock, flags);
-+ if (arch_get_random_long(&v))
-+ crng->state[14] ^= v;
-+ chacha20_block(&crng->state[0], out);
-+ if (crng->state[12] == 0)
-+ crng->state[13]++;
-+ spin_unlock_irqrestore(&crng->lock, flags);
-+}
-+
-+static ssize_t extract_crng_user(void __user *buf, size_t nbytes)
-+{
-+ ssize_t ret = 0, i;
-+ __u8 tmp[CHACHA20_BLOCK_SIZE];
-+ int large_request = (nbytes > 256);
-+
-+ while (nbytes) {
-+ if (large_request && need_resched()) {
-+ if (signal_pending(current)) {
-+ if (ret == 0)
-+ ret = -ERESTARTSYS;
-+ break;
-+ }
-+ schedule();
-+ }
-+
-+ extract_crng(tmp);
-+ i = min_t(int, nbytes, CHACHA20_BLOCK_SIZE);
-+ if (copy_to_user(buf, tmp, i)) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ nbytes -= i;
-+ buf += i;
-+ ret += i;
-+ }
-+
-+ /* Wipe data just written to memory */
-+ memzero_explicit(tmp, sizeof(tmp));
-+
-+ return ret;
-+}
-+
-+
-+/*********************************************************************
-+ *
- * Entropy input management
- *
- *********************************************************************/
-@@ -752,12 +910,12 @@ struct timer_rand_state {
- #define INIT_TIMER_RAND_STATE { INITIAL_JIFFIES, };
-
- /*
-- * Add device- or boot-specific data to the input and nonblocking
-- * pools to help initialize them to unique values.
-+ * Add device- or boot-specific data to the input pool to help
-+ * initialize it.
- *
-- * None of this adds any entropy, it is meant to avoid the
-- * problem of the nonblocking pool having similar initial state
-- * across largely identical devices.
-+ * None of this adds any entropy; it is meant to avoid the problem of
-+ * the entropy pool having similar initial state across largely
-+ * identical devices.
- */
- void add_device_randomness(const void *buf, unsigned int size)
- {
-@@ -769,11 +927,6 @@ void add_device_randomness(const void *buf, unsigned int size)
- _mix_pool_bytes(&input_pool, buf, size);
- _mix_pool_bytes(&input_pool, &time, sizeof(time));
- spin_unlock_irqrestore(&input_pool.lock, flags);
--
-- spin_lock_irqsave(&nonblocking_pool.lock, flags);
-- _mix_pool_bytes(&nonblocking_pool, buf, size);
-- _mix_pool_bytes(&nonblocking_pool, &time, sizeof(time));
-- spin_unlock_irqrestore(&nonblocking_pool.lock, flags);
- }
- EXPORT_SYMBOL(add_device_randomness);
-
-@@ -804,7 +957,7 @@ static void add_timer_randomness(struct timer_rand_state *state, unsigned num)
- sample.jiffies = jiffies;
- sample.cycles = random_get_entropy();
- sample.num = num;
-- r = nonblocking_pool.initialized ? &input_pool : &nonblocking_pool;
-+ r = &input_pool;
- mix_pool_bytes(r, &sample, sizeof(sample));
-
- /*
-@@ -920,11 +1073,21 @@ void add_interrupt_randomness(int irq, int irq_flags)
- fast_mix(fast_pool);
- add_interrupt_bench(cycles);
-
-+ if (!crng_ready()) {
-+ if ((fast_pool->count >= 64) &&
-+ crng_fast_load((char *) fast_pool->pool,
-+ sizeof(fast_pool->pool))) {
-+ fast_pool->count = 0;
-+ fast_pool->last = now;
-+ }
-+ return;
-+ }
-+
- if ((fast_pool->count < 64) &&
- !time_after(now, fast_pool->last + HZ))
- return;
-
-- r = nonblocking_pool.initialized ? &input_pool : &nonblocking_pool;
-+ r = &input_pool;
- if (!spin_trylock(&r->lock))
- return;
-
-@@ -968,9 +1131,6 @@ EXPORT_SYMBOL_GPL(add_disk_randomness);
- *
- *********************************************************************/
-
--static ssize_t extract_entropy(struct entropy_store *r, void *buf,
-- size_t nbytes, int min, int rsvd);
--
- /*
- * This utility inline function is responsible for transferring entropy
- * from the primary pool to the secondary extraction pool. We make
-@@ -1145,6 +1305,36 @@ static void extract_buf(struct entropy_store *r, __u8 *out)
- memzero_explicit(&hash, sizeof(hash));
- }
-
-+static ssize_t _extract_entropy(struct entropy_store *r, void *buf,
-+ size_t nbytes, int fips)
-+{
-+ ssize_t ret = 0, i;
-+ __u8 tmp[EXTRACT_SIZE];
-+ unsigned long flags;
-+
-+ while (nbytes) {
-+ extract_buf(r, tmp);
-+
-+ if (fips) {
-+ spin_lock_irqsave(&r->lock, flags);
-+ if (!memcmp(tmp, r->last_data, EXTRACT_SIZE))
-+ panic("Hardware RNG duplicated output!\n");
-+ memcpy(r->last_data, tmp, EXTRACT_SIZE);
-+ spin_unlock_irqrestore(&r->lock, flags);
-+ }
-+ i = min_t(int, nbytes, EXTRACT_SIZE);
-+ memcpy(buf, tmp, i);
-+ nbytes -= i;
-+ buf += i;
-+ ret += i;
-+ }
-+
-+ /* Wipe data just returned from memory */
-+ memzero_explicit(tmp, sizeof(tmp));
-+
-+ return ret;
-+}
-+
- /*
- * This function extracts randomness from the "entropy pool", and
- * returns it in a buffer.
-@@ -1157,7 +1347,6 @@ static void extract_buf(struct entropy_store *r, __u8 *out)
- static ssize_t extract_entropy(struct entropy_store *r, void *buf,
- size_t nbytes, int min, int reserved)
- {
-- ssize_t ret = 0, i;
- __u8 tmp[EXTRACT_SIZE];
- unsigned long flags;
-
-@@ -1181,27 +1370,7 @@ static ssize_t extract_entropy(struct entropy_store *r, void *buf,
- xfer_secondary_pool(r, nbytes);
- nbytes = account(r, nbytes, min, reserved);
-
-- while (nbytes) {
-- extract_buf(r, tmp);
--
-- if (fips_enabled) {
-- spin_lock_irqsave(&r->lock, flags);
-- if (!memcmp(tmp, r->last_data, EXTRACT_SIZE))
-- panic("Hardware RNG duplicated output!\n");
-- memcpy(r->last_data, tmp, EXTRACT_SIZE);
-- spin_unlock_irqrestore(&r->lock, flags);
-- }
-- i = min_t(int, nbytes, EXTRACT_SIZE);
-- memcpy(buf, tmp, i);
-- nbytes -= i;
-- buf += i;
-- ret += i;
-- }
--
-- /* Wipe data just returned from memory */
-- memzero_explicit(tmp, sizeof(tmp));
--
-- return ret;
-+ return _extract_entropy(r, buf, nbytes, fips_enabled);
- }
-
- /*
-@@ -1256,15 +1425,26 @@ static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf,
- */
- void get_random_bytes(void *buf, int nbytes)
- {
-+ __u8 tmp[CHACHA20_BLOCK_SIZE];
-+
- #if DEBUG_RANDOM_BOOT > 0
-- if (unlikely(nonblocking_pool.initialized == 0))
-+ if (!crng_ready())
- printk(KERN_NOTICE "random: %pF get_random_bytes called "
-- "with %d bits of entropy available\n",
-- (void *) _RET_IP_,
-- nonblocking_pool.entropy_total);
-+ "with crng_init = %d\n", (void *) _RET_IP_, crng_init);
- #endif
- trace_get_random_bytes(nbytes, _RET_IP_);
-- extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0);
-+
-+ while (nbytes >= CHACHA20_BLOCK_SIZE) {
-+ extract_crng(buf);
-+ buf += CHACHA20_BLOCK_SIZE;
-+ nbytes -= CHACHA20_BLOCK_SIZE;
-+ }
-+
-+ if (nbytes > 0) {
-+ extract_crng(tmp);
-+ memcpy(buf, tmp, nbytes);
-+ memzero_explicit(tmp, nbytes);
-+ }
- }
- EXPORT_SYMBOL(get_random_bytes);
-
-@@ -1282,7 +1462,7 @@ int add_random_ready_callback(struct random_ready_callback *rdy)
- unsigned long flags;
- int err = -EALREADY;
-
-- if (likely(nonblocking_pool.initialized))
-+ if (crng_ready())
- return err;
-
- owner = rdy->owner;
-@@ -1290,7 +1470,7 @@ int add_random_ready_callback(struct random_ready_callback *rdy)
- return -ENOENT;
-
- spin_lock_irqsave(&random_ready_list_lock, flags);
-- if (nonblocking_pool.initialized)
-+ if (crng_ready())
- goto out;
-
- owner = NULL;
-@@ -1354,7 +1534,7 @@ void get_random_bytes_arch(void *buf, int nbytes)
- }
-
- if (nbytes)
-- extract_entropy(&nonblocking_pool, p, nbytes, 0, 0);
-+ get_random_bytes(p, nbytes);
- }
- EXPORT_SYMBOL(get_random_bytes_arch);
-
-@@ -1399,7 +1579,7 @@ static int rand_initialize(void)
- {
- init_std_data(&input_pool);
- init_std_data(&blocking_pool);
-- init_std_data(&nonblocking_pool);
-+ crng_initialize(&primary_crng);
- return 0;
- }
- early_initcall(rand_initialize);
-@@ -1461,22 +1641,22 @@ random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
- static ssize_t
- urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
- {
-+ unsigned long flags;
- static int maxwarn = 10;
- int ret;
-
-- if (unlikely(nonblocking_pool.initialized == 0) &&
-- maxwarn > 0) {
-+ if (!crng_ready() && maxwarn > 0) {
- maxwarn--;
- printk(KERN_NOTICE "random: %s: uninitialized urandom read "
-- "(%zd bytes read, %d bits of entropy available)\n",
-- current->comm, nbytes, nonblocking_pool.entropy_total);
-+ "(%zd bytes read)\n",
-+ current->comm, nbytes);
-+ spin_lock_irqsave(&primary_crng.lock, flags);
-+ crng_init_cnt = 0;
-+ spin_unlock_irqrestore(&primary_crng.lock, flags);
- }
--
- nbytes = min_t(size_t, nbytes, INT_MAX >> (ENTROPY_SHIFT + 3));
-- ret = extract_entropy_user(&nonblocking_pool, buf, nbytes);
--
-- trace_urandom_read(8 * nbytes, ENTROPY_BITS(&nonblocking_pool),
-- ENTROPY_BITS(&input_pool));
-+ ret = extract_crng_user(buf, nbytes);
-+ trace_urandom_read(8 * nbytes, 0, ENTROPY_BITS(&input_pool));
- return ret;
- }
-
-@@ -1522,10 +1702,7 @@ static ssize_t random_write(struct file *file, const char __user *buffer,
- {
- size_t ret;
-
-- ret = write_pool(&blocking_pool, buffer, count);
-- if (ret)
-- return ret;
-- ret = write_pool(&nonblocking_pool, buffer, count);
-+ ret = write_pool(&input_pool, buffer, count);
- if (ret)
- return ret;
-
-@@ -1574,7 +1751,6 @@ static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
- if (!capable(CAP_SYS_ADMIN))
- return -EPERM;
- input_pool.entropy_count = 0;
-- nonblocking_pool.entropy_count = 0;
- blocking_pool.entropy_count = 0;
- return 0;
- default:
-@@ -1616,11 +1792,10 @@ SYSCALL_DEFINE3(getrandom, char __user *, buf, size_t, count,
- if (flags & GRND_RANDOM)
- return _random_read(flags & GRND_NONBLOCK, buf, count);
-
-- if (unlikely(nonblocking_pool.initialized == 0)) {
-+ if (!crng_ready()) {
- if (flags & GRND_NONBLOCK)
- return -EAGAIN;
-- wait_event_interruptible(urandom_init_wait,
-- nonblocking_pool.initialized);
-+ crng_wait_ready();
- if (signal_pending(current))
- return -ERESTARTSYS;
- }
-@@ -1852,18 +2027,17 @@ void add_hwgenerator_randomness(const char *buffer, size_t count,
- {
- struct entropy_store *poolp = &input_pool;
-
-- if (unlikely(nonblocking_pool.initialized == 0))
-- poolp = &nonblocking_pool;
-- else {
-- /* Suspend writing if we're above the trickle
-- * threshold. We'll be woken up again once below
-- * random_write_wakeup_thresh, or when the calling
-- * thread is about to terminate.
-- */
-- wait_event_interruptible(random_write_wait,
-- kthread_should_stop() ||
-- ENTROPY_BITS(&input_pool) <= random_write_wakeup_bits);
-+ if (!crng_ready()) {
-+ crng_fast_load(buffer, count);
-+ return;
- }
-+
-+ /* Suspend writing if we're above the trickle threshold.
-+ * We'll be woken up again once below random_write_wakeup_thresh,
-+ * or when the calling thread is about to terminate.
-+ */
-+ wait_event_interruptible(random_write_wait, kthread_should_stop() ||
-+ ENTROPY_BITS(&input_pool) <= random_write_wakeup_bits);
- mix_pool_bytes(poolp, buffer, count);
- credit_entropy_bits(poolp, entropy);
- }
-diff --git a/include/crypto/chacha20.h b/include/crypto/chacha20.h
-index 274bbae..20d20f6 100644
---- a/include/crypto/chacha20.h
-+++ b/include/crypto/chacha20.h
-@@ -16,6 +16,7 @@ struct chacha20_ctx {
- u32 key[8];
- };
-
-+void chacha20_block(u32 *state, void *stream);
- void crypto_chacha20_init(u32 *state, struct chacha20_ctx *ctx, u8 *iv);
- int crypto_chacha20_setkey(struct crypto_tfm *tfm, const u8 *key,
- unsigned int keysize);
-diff --git a/lib/Makefile b/lib/Makefile
-index 7f1de26..0f465dc 100644
---- a/lib/Makefile
-+++ b/lib/Makefile
-@@ -10,7 +10,7 @@ endif
- lib-y := ctype.o string.o vsprintf.o cmdline.o \
- rbtree.o radix-tree.o dump_stack.o timerqueue.o\
- idr.o int_sqrt.o extable.o \
-- sha1.o md5.o irq_regs.o argv_split.o \
-+ sha1.o chacha20.o md5.o irq_regs.o argv_split.o \
- proportions.o flex_proportions.o ratelimit.o show_mem.o \
- is_single_threaded.o plist.o decompress.o kobject_uevent.o \
- earlycpio.o seq_buf.o nmi_backtrace.o
-diff --git a/lib/chacha20.c b/lib/chacha20.c
-new file mode 100644
-index 0000000..250ceed
---- /dev/null
-+++ b/lib/chacha20.c
-@@ -0,0 +1,79 @@
-+/*
-+ * ChaCha20 256-bit cipher algorithm, RFC7539
-+ *
-+ * Copyright (C) 2015 Martin Willi
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/export.h>
-+#include <linux/bitops.h>
-+#include <linux/cryptohash.h>
-+#include <asm/unaligned.h>
-+#include <crypto/chacha20.h>
-+
-+static inline u32 rotl32(u32 v, u8 n)
-+{
-+ return (v << n) | (v >> (sizeof(v) * 8 - n));
-+}
-+
-+extern void chacha20_block(u32 *state, void *stream)
-+{
-+ u32 x[16], *out = stream;
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(x); i++)
-+ x[i] = state[i];
-+
-+ for (i = 0; i < 20; i += 2) {
-+ x[0] += x[4]; x[12] = rotl32(x[12] ^ x[0], 16);
-+ x[1] += x[5]; x[13] = rotl32(x[13] ^ x[1], 16);
-+ x[2] += x[6]; x[14] = rotl32(x[14] ^ x[2], 16);
-+ x[3] += x[7]; x[15] = rotl32(x[15] ^ x[3], 16);
-+
-+ x[8] += x[12]; x[4] = rotl32(x[4] ^ x[8], 12);
-+ x[9] += x[13]; x[5] = rotl32(x[5] ^ x[9], 12);
-+ x[10] += x[14]; x[6] = rotl32(x[6] ^ x[10], 12);
-+ x[11] += x[15]; x[7] = rotl32(x[7] ^ x[11], 12);
-+
-+ x[0] += x[4]; x[12] = rotl32(x[12] ^ x[0], 8);
-+ x[1] += x[5]; x[13] = rotl32(x[13] ^ x[1], 8);
-+ x[2] += x[6]; x[14] = rotl32(x[14] ^ x[2], 8);
-+ x[3] += x[7]; x[15] = rotl32(x[15] ^ x[3], 8);
-+
-+ x[8] += x[12]; x[4] = rotl32(x[4] ^ x[8], 7);
-+ x[9] += x[13]; x[5] = rotl32(x[5] ^ x[9], 7);
-+ x[10] += x[14]; x[6] = rotl32(x[6] ^ x[10], 7);
-+ x[11] += x[15]; x[7] = rotl32(x[7] ^ x[11], 7);
-+
-+ x[0] += x[5]; x[15] = rotl32(x[15] ^ x[0], 16);
-+ x[1] += x[6]; x[12] = rotl32(x[12] ^ x[1], 16);
-+ x[2] += x[7]; x[13] = rotl32(x[13] ^ x[2], 16);
-+ x[3] += x[4]; x[14] = rotl32(x[14] ^ x[3], 16);
-+
-+ x[10] += x[15]; x[5] = rotl32(x[5] ^ x[10], 12);
-+ x[11] += x[12]; x[6] = rotl32(x[6] ^ x[11], 12);
-+ x[8] += x[13]; x[7] = rotl32(x[7] ^ x[8], 12);
-+ x[9] += x[14]; x[4] = rotl32(x[4] ^ x[9], 12);
-+
-+ x[0] += x[5]; x[15] = rotl32(x[15] ^ x[0], 8);
-+ x[1] += x[6]; x[12] = rotl32(x[12] ^ x[1], 8);
-+ x[2] += x[7]; x[13] = rotl32(x[13] ^ x[2], 8);
-+ x[3] += x[4]; x[14] = rotl32(x[14] ^ x[3], 8);
-+
-+ x[10] += x[15]; x[5] = rotl32(x[5] ^ x[10], 7);
-+ x[11] += x[12]; x[6] = rotl32(x[6] ^ x[11], 7);
-+ x[8] += x[13]; x[7] = rotl32(x[7] ^ x[8], 7);
-+ x[9] += x[14]; x[4] = rotl32(x[4] ^ x[9], 7);
-+ }
-+
-+ for (i = 0; i < ARRAY_SIZE(x); i++)
-+ out[i] = cpu_to_le32(x[i] + state[i]);
-+
-+ state[12]++;
-+}
-+EXPORT_SYMBOL(chacha20_block);
---
-1.9.1
-
diff --git a/common/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-.patch b/common/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-.patch
deleted file mode 100644
index 570e7b85..00000000
--- a/common/recipes-kernel/linux/files/0001-yocto-amd-staging-add-support-to-enable-and-disable-.patch
+++ /dev/null
@@ -1,432 +0,0 @@
-From 31f1e845c0d5d9fd243a6cf8d07fec822c335f88 Mon Sep 17 00:00:00 2001
-From: Sanjay R Mehta <sanju.mehta@amd.com>
-Date: Tue, 27 Sep 2016 16:13:05 +0530
-Subject: [PATCH 1/2] yocto amd staging add support to enable and disable IMC
- to fetch BIOS code
-
-Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
----
- drivers/staging/Kconfig | 2 +
- drivers/staging/Makefile | 1 +
- drivers/staging/amd_imc/Kconfig | 9 ++
- drivers/staging/amd_imc/Makefile | 1 +
- drivers/staging/amd_imc/amd_imc.c | 286 ++++++++++++++++++++++++++++++++++++++
- include/linux/amd_imc.h | 69 +++++++++
- 6 files changed, 368 insertions(+)
- create mode 100644 drivers/staging/amd_imc/Kconfig
- create mode 100644 drivers/staging/amd_imc/Makefile
- create mode 100644 drivers/staging/amd_imc/amd_imc.c
- create mode 100644 include/linux/amd_imc.h
-
-diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
-index 5d3b86a..a6ee082 100644
---- a/drivers/staging/Kconfig
-+++ b/drivers/staging/Kconfig
-@@ -110,4 +110,6 @@ source "drivers/staging/wilc1000/Kconfig"
-
- source "drivers/staging/most/Kconfig"
-
-+source "drivers/staging/amd_imc/Kconfig"
-+
- endif # STAGING
-diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
-index 30918ed..4f31852 100644
---- a/drivers/staging/Makefile
-+++ b/drivers/staging/Makefile
-@@ -47,3 +47,4 @@ obj-$(CONFIG_FB_TFT) += fbtft/
- obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/
- obj-$(CONFIG_WILC1000) += wilc1000/
- obj-$(CONFIG_MOST) += most/
-+obj-$(CONFIG_AMD_IMC) += amd_imc/
-diff --git a/drivers/staging/amd_imc/Kconfig b/drivers/staging/amd_imc/Kconfig
-new file mode 100644
-index 0000000..abfb724
---- /dev/null
-+++ b/drivers/staging/amd_imc/Kconfig
-@@ -0,0 +1,9 @@
-+config AMD_IMC
-+ bool "AMD Intergrated Micro Controller support"
-+ depends on PCI && X86_64
-+ default y
-+ ---help---
-+ This driver supports AMD Intergrated Micro Controller.
-+
-+ To compile this driver as a module, choose M here. The module
-+ will be called amd_imc.
-diff --git a/drivers/staging/amd_imc/Makefile b/drivers/staging/amd_imc/Makefile
-new file mode 100644
-index 0000000..c4837f8
---- /dev/null
-+++ b/drivers/staging/amd_imc/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_AMD_IMC) += amd_imc.o
-diff --git a/drivers/staging/amd_imc/amd_imc.c b/drivers/staging/amd_imc/amd_imc.c
-new file mode 100644
-index 0000000..1551bdb
---- /dev/null
-+++ b/drivers/staging/amd_imc/amd_imc.c
-@@ -0,0 +1,286 @@
-+/*****************************************************************************
-+*
-+* Copyright (c) 2014, Advanced Micro Devices, Inc.
-+* All rights reserved.
-+*
-+* Redistribution and use in source and binary forms, with or without
-+* modification, are permitted provided that the following conditions are met:
-+* * Redistributions of source code must retain the above copyright
-+* notice, this list of conditions and the following disclaimer.
-+* * Redistributions in binary form must reproduce the above copyright
-+* notice, this list of conditions and the following disclaimer in the
-+* documentation and/or other materials provided with the distribution.
-+* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-+* its contributors may be used to endorse or promote products derived
-+* from this software without specific prior written permission.
-+*
-+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*
-+*
-+***************************************************************************/
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/pci.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+#include <linux/io.h>
-+#include <linux/delay.h>
-+#include <linux/amd_imc.h>
-+
-+static int imc_enabled;
-+static u16 imc_port_addr;
-+static u8 msg_reg_base_hi;
-+static u8 msg_reg_base_lo;
-+static u16 msg_reg_base;
-+
-+static struct pci_dev *amd_imc_pci;
-+static struct platform_device *amd_imc_platform_device;
-+
-+static DEFINE_PCI_DEVICE_TABLE(amd_lpc_pci_tbl) = {
-+ {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LPC_BRIDGE, PCI_ANY_ID,
-+ PCI_ANY_ID,},
-+ {}
-+};
-+
-+void amd_imc_enter_scratch_ram(void)
-+{
-+ u8 byte;
-+
-+ if (!imc_enabled)
-+ return;
-+
-+ /* Instruct IMC to enter scratch RAM */
-+ outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ outb(0, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+ outb(AMD_MSG_REG1, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ outb(AMD_IMC_ENTER_SCRATCH_RAM, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+ outb(AMD_MSG_SYS_TO_IMC, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ outb(AMD_IMC_ROM_OWNERSHIP_SEM, msg_reg_base +
-+ AMD_MSG_DATA_REG_OFFSET);
-+
-+ /* As per the spec, the firmware may take up to 50ms */
-+ msleep(50);
-+
-+ /* read message registger 0 to confirm function completion */
-+ outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ byte = inb(msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+ if (byte == AMD_IMC_FUNC_NOT_SUPP)
-+ pr_info("amd_imc: %s not supported\n", __func__);
-+ else if (byte == AMD_IMC_FUNC_COMPLETED)
-+ pr_info("amd_imc: %s completed\n", __func__);
-+}
-+EXPORT_SYMBOL_GPL(amd_imc_enter_scratch_ram);
-+
-+void amd_imc_exit_scratch_ram(void)
-+{
-+ u8 byte;
-+
-+ if (!imc_enabled)
-+ return;
-+
-+ /* Instruct IMC to exit scratch RAM */
-+ outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ outb(0, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+ outb(AMD_MSG_REG1, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ outb(AMD_IMC_ENTER_SCRATCH_RAM, msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+ outb(AMD_MSG_SYS_TO_IMC, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ outb(AMD_IMC_ROM_OWNERSHIP_SEM, msg_reg_base +
-+ AMD_MSG_DATA_REG_OFFSET);
-+
-+ /* As per the spec, the firmware may take up to 50ms */
-+ msleep(50);
-+
-+ /* read message registger 0 to confirm function completion */
-+ outb(AMD_MSG_REG0, msg_reg_base + AMD_MSG_INDEX_REG_OFFSET);
-+ byte = inb(msg_reg_base + AMD_MSG_DATA_REG_OFFSET);
-+
-+ if (byte == AMD_IMC_FUNC_NOT_SUPP)
-+ pr_info("amd_imc: %s not supported\n", __func__);
-+ else if (byte == AMD_IMC_FUNC_COMPLETED)
-+ pr_info("amd_imc: %s completed\n", __func__);
-+}
-+EXPORT_SYMBOL_GPL(amd_imc_exit_scratch_ram);
-+
-+/*
-+* The PCI Device ID table below is used to identify the platform
-+* the driver is supposed to work for. Since this is a platform
-+* driver, we need a way for us to be able to find the correct
-+* platform when the driver gets loaded, otherwise we should
-+* bail out.
-+*/
-+static DEFINE_PCI_DEVICE_TABLE(amd_imc_pci_tbl) = {
-+ { PCI_VENDOR_ID_AMD, 0x790B, PCI_ANY_ID,
-+ PCI_ANY_ID, },
-+ { 0, },
-+};
-+
-+static int amd_imc_init(struct platform_device *pdev)
-+{
-+ struct pci_dev *dev = NULL;
-+ static u32 imc_strap_status_phys;
-+ void __iomem *imcstrapstatus;
-+ u32 val;
-+
-+ /* Match the PCI device */
-+ for_each_pci_dev(dev) {
-+ if (pci_match_id(amd_imc_pci_tbl, dev) != NULL) {
-+ amd_imc_pci = dev;
-+ break;
-+ }
-+ }
-+
-+ if (!amd_imc_pci)
-+ return -ENODEV;
-+
-+
-+ /* ACPI MMIO Base Address */
-+ val = AMD_GPIO_ACPIMMIO_BASE;
-+
-+ /* IMCStrapStatus is located at ACPI MMIO Base Address + 0xE80 */
-+ if (!request_mem_region_exclusive(val + AMD_IMC_STRAP_STATUS_OFFSET,
-+ AMD_IMC_STRAP_STATUS_SIZE, "IMC Strap Status")) {
-+ pr_err("amd_imc: MMIO address 0x%04x already in use\n",
-+ val + AMD_IMC_STRAP_STATUS_OFFSET);
-+ goto exit;
-+ }
-+
-+ imc_strap_status_phys = val + AMD_IMC_STRAP_STATUS_OFFSET;
-+
-+ imcstrapstatus = ioremap(imc_strap_status_phys,
-+ AMD_IMC_STRAP_STATUS_SIZE);
-+ if (!imcstrapstatus) {
-+ pr_err("amd_imc: failed to get IMC Strap Status address\n");
-+ goto unreg_imc_region;
-+ }
-+
-+ /* Check if IMC is enabled */
-+ val = ioread32(imcstrapstatus);
-+ if ((val & AMD_IMC_ENABLED) == AMD_IMC_ENABLED) {
-+ struct pci_dev *pdev = NULL;
-+
-+ pr_info("amd_imc: IMC is enabled\n");
-+ imc_enabled = 1;
-+
-+ /*
-+ * In case IMC is enabled, we need to find the IMC port address
-+ * which will be used to send messages to the IMC. The IMC port
-+ * address is stored in bits 1:15 of PCI device 20, function 3,
-+ * offset 0xA4. PCI device 20, function 3 is actually the LPC
-+ * ISA bridge.
-+ */
-+ for_each_pci_dev(pdev) {
-+ if (pci_match_id(amd_lpc_pci_tbl, pdev) != NULL)
-+ break;
-+ }
-+
-+ /* Match found. Get the IMC port address */
-+ if (pdev) {
-+ pci_read_config_word(pdev, AMD_PCI_IMC_PORT_ADDR_REG,
-+ &imc_port_addr);
-+
-+ /* The actual IMC port address has bit 0 masked out */
-+ imc_port_addr &= ~AMD_IMC_PORT_ACTIVE;
-+ }
-+
-+ /* Put device into configuration state */
-+ outb(AMD_DEVICE_ENTER_CONFIG_STATE, imc_port_addr +
-+ AMD_IMC_INDEX_REG_OFFSET);
-+
-+ /* Select logical device number 9 */
-+ outb(AMD_SET_LOGICAL_DEVICE, imc_port_addr +
-+ AMD_IMC_INDEX_REG_OFFSET);
-+ outb(AMD_SET_DEVICE_9, imc_port_addr +
-+ AMD_IMC_DATA_REG_OFFSET);
-+
-+ /* read high byte of message register base address */
-+ outb(AMD_MSG_REG_HIGH, imc_port_addr +
-+ AMD_IMC_INDEX_REG_OFFSET);
-+ msg_reg_base_hi = inb(imc_port_addr + AMD_IMC_DATA_REG_OFFSET);
-+
-+ /* read low byte of message register base address */
-+ outb(AMD_MSG_REG_LOW, imc_port_addr +
-+ AMD_IMC_INDEX_REG_OFFSET);
-+ msg_reg_base_lo = inb(imc_port_addr + AMD_IMC_DATA_REG_OFFSET);
-+
-+ msg_reg_base = msg_reg_base_lo | (msg_reg_base_hi << 8);
-+
-+ /* Get device out of configuration state */
-+ outb(AMD_DEVICE_EXIT_CONFIG_STATE, imc_port_addr +
-+ AMD_IMC_INDEX_REG_OFFSET);
-+ } else {
-+ pr_info("amd_imc: IMC is disabled\n");
-+ imc_enabled = 0;
-+ }
-+
-+ /* Release the region occupied by IMC Strap Status register */
-+ iounmap(imcstrapstatus);
-+ release_mem_region(imc_strap_status_phys, AMD_IMC_STRAP_STATUS_SIZE);
-+
-+ return 0;
-+
-+unreg_imc_region:
-+ release_mem_region(imc_strap_status_phys, AMD_IMC_STRAP_STATUS_SIZE);
-+exit:
-+ return -ENODEV;
-+}
-+
-+static struct platform_driver amd_imc_driver = {
-+ .probe = amd_imc_init,
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = IMC_MODULE_NAME,
-+ },
-+};
-+
-+static int __init amd_imc_init_module(void)
-+{
-+ int err;
-+
-+ pr_info("AMD IMC Driver v%s\n", IMC_VERSION);
-+
-+ err = platform_driver_register(&amd_imc_driver);
-+ if (err)
-+ return err;
-+
-+ amd_imc_platform_device = platform_device_register_simple(
-+ IMC_MODULE_NAME, -1, NULL, 0);
-+ if (IS_ERR(amd_imc_platform_device)) {
-+ err = PTR_ERR(amd_imc_platform_device);
-+ goto unreg_platform_driver;
-+ }
-+
-+ return 0;
-+
-+unreg_platform_driver:
-+ platform_driver_unregister(&amd_imc_driver);
-+ return err;
-+}
-+
-+static void __exit amd_imc_cleanup_module(void)
-+{
-+ platform_device_unregister(amd_imc_platform_device);
-+ platform_driver_unregister(&amd_imc_driver);
-+ pr_info("AMD IMC Module Unloaded\n");
-+}
-+
-+module_init(amd_imc_init_module);
-+module_exit(amd_imc_cleanup_module);
-+
-+MODULE_AUTHOR("Arindam Nath <arindam.nath@amd.com>");
-+MODULE_DESCRIPTION("AMD IMC driver");
-+MODULE_LICENSE("Dual BSD/GPL");
-diff --git a/include/linux/amd_imc.h b/include/linux/amd_imc.h
-new file mode 100644
-index 0000000..b1c03bf
---- /dev/null
-+++ b/include/linux/amd_imc.h
-@@ -0,0 +1,69 @@
-+#ifndef _AMD_IMC_H_
-+#define _AMD_IMC_H_
-+
-+/* Module and version information */
-+#define IMC_VERSION "0.1"
-+#define IMC_MODULE_NAME "AMD IMC"
-+#define IMC_DRIVER_NAME IMC_MODULE_NAME ", v" IMC_VERSION
-+
-+#define DRV_NAME "amd_imc"
-+
-+/* IO port address for indirect access using the ACPI PM registers */
-+#define AMD_IO_PM_INDEX_REG 0xCD6
-+#define AMD_IO_PM_DATA_REG 0xCD7
-+
-+#define AMD_GPIO_ACPIMMIO_BASE 0xFED80000
-+#define AMD_PM_ACPI_MMIO_BASE0 0x24
-+#define AMD_PM_ACPI_MMIO_BASE1 0x25
-+#define AMD_PM_ACPI_MMIO_BASE2 0x26
-+#define AMD_PM_ACPI_MMIO_BASE3 0x27
-+
-+#define AMD_ACPI_MMIO_ADDR_MASK ~0x1FFF
-+
-+/* Offset of IMC Strap Status register in the ACPI MMIO region */
-+#define AMD_IMC_STRAP_STATUS_OFFSET 0xE80
-+ #define AMD_IMC_ENABLED 0x4
-+#define AMD_IMC_STRAP_STATUS_SIZE 4
-+
-+#define PCI_DEVICE_ID_AMD_LPC_BRIDGE 0x790E
-+ #define AMD_PCI_IMC_PORT_ADDR_REG 0xA4
-+ #define AMD_IMC_PORT_ACTIVE 0x0001
-+
-+/* Device configuration state fields */
-+#define AMD_DEVICE_ENTER_CONFIG_STATE 0x5A
-+#define AMD_DEVICE_EXIT_CONFIG_STATE 0xA5
-+
-+/* Global configuration registers */
-+#define AMD_SET_LOGICAL_DEVICE 0x07
-+ #define AMD_SET_DEVICE_9 0x09
-+#define AMD_MSG_REG_HIGH 0x60
-+#define AMD_MSG_REG_LOW 0x61
-+
-+/* IMC index and data port offsets for indirect access */
-+#define AMD_IMC_INDEX_REG_OFFSET 0x00
-+#define AMD_IMC_DATA_REG_OFFSET 0x01
-+
-+/* Message register index and data port offsets for indirect access */
-+#define AMD_MSG_INDEX_REG_OFFSET 0x00
-+#define AMD_MSG_DATA_REG_OFFSET 0x01
-+
-+/* IMC message registers */
-+#define AMD_MSG_SYS_TO_IMC 0x80
-+ #define AMD_IMC_ROM_OWNERSHIP_SEM 0x96
-+#define AMD_MSG_REG0 0x82
-+ #define AMD_IMC_FUNC_NOT_SUPP 0x00
-+ #define AMD_IMC_FUNC_COMPLETED 0xFA
-+#define AMD_MSG_REG1 0x83
-+ #define AMD_IMC_ENTER_SCRATCH_RAM 0xB4
-+ #define AMD_IMC_EXIT_SCRATCH_RAM 0xB5
-+
-+/* Extern functions */
-+#ifdef CONFIG_AMD_IMC
-+extern void amd_imc_enter_scratch_ram(void);
-+extern void amd_imc_exit_scratch_ram(void);
-+#else
-+void amd_imc_enter_scratch_ram(void) {}
-+void amd_imc_exit_scratch_ram(void) {}
-+#endif
-+
-+#endif /* _AMD_IMC_H_ */
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0002-drm-Pass-the-user-drm_mode_fb_cmd2-as-const-to-.fb_c.patch b/common/recipes-kernel/linux/files/0002-drm-Pass-the-user-drm_mode_fb_cmd2-as-const-to-.fb_c.patch
deleted file mode 100644
index 609e2d0f..00000000
--- a/common/recipes-kernel/linux/files/0002-drm-Pass-the-user-drm_mode_fb_cmd2-as-const-to-.fb_c.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From e915ae9d87955964538402e0c5510d0161d0072f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
-Date: Wed, 11 Nov 2015 19:11:29 +0200
-Subject: [PATCH 0002/1110] drm: Pass the user drm_mode_fb_cmd2 as const to
- .fb_create()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Drivers shouldn't clobber the passed in addfb ioctl parameters.
-i915 was doing just that. To prevent it from happening again,
-pass the struct around as const, starting all the way from
-internal_framebuffer_create().
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-index 82903ca..1846d65 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
-@@ -530,7 +530,7 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
- int
- amdgpu_framebuffer_init(struct drm_device *dev,
- struct amdgpu_framebuffer *rfb,
-- struct drm_mode_fb_cmd2 *mode_cmd,
-+ const struct drm_mode_fb_cmd2 *mode_cmd,
- struct drm_gem_object *obj)
- {
- int ret;
-@@ -547,7 +547,7 @@ amdgpu_framebuffer_init(struct drm_device *dev,
- static struct drm_framebuffer *
- amdgpu_user_framebuffer_create(struct drm_device *dev,
- struct drm_file *file_priv,
-- struct drm_mode_fb_cmd2 *mode_cmd)
-+ const struct drm_mode_fb_cmd2 *mode_cmd)
- {
- struct drm_gem_object *obj;
- struct amdgpu_framebuffer *amdgpu_fb;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 89df787..cfb48e3 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -556,7 +556,7 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
-
- int amdgpu_framebuffer_init(struct drm_device *dev,
- struct amdgpu_framebuffer *rfb,
-- struct drm_mode_fb_cmd2 *mode_cmd,
-+ const struct drm_mode_fb_cmd2 *mode_cmd,
- struct drm_gem_object *obj);
-
- int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IM.patch b/common/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IM.patch
deleted file mode 100644
index c4aa7915..00000000
--- a/common/recipes-kernel/linux/files/0002-yocto-amd-i2c-dev-add-calls-to-enable-and-disable-IM.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 6d365974c73b25976a5c5b7572af2dab13ad39d0 Mon Sep 17 00:00:00 2001
-From: Sanjay R Mehta <sanju.mehta@amd.com>
-Date: Tue, 27 Sep 2016 16:14:53 +0530
-Subject: [PATCH 2/2] yocto amd i2c dev add calls to enable and disable IMC
- from fetching BIOS code
-
----
- drivers/i2c/i2c-dev.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
-index 2413ec9..6a3419d 100644
---- a/drivers/i2c/i2c-dev.c
-+++ b/drivers/i2c/i2c-dev.c
-@@ -34,6 +34,7 @@
- #include <linux/i2c-dev.h>
- #include <linux/jiffies.h>
- #include <linux/uaccess.h>
-+#include <linux/amd_imc.h>
-
- /*
- * An i2c_dev represents an i2c_adapter ... an I2C or SMBus master, not a
-@@ -510,6 +511,8 @@ static int i2cdev_open(struct inode *inode, struct file *file)
- client->adapter = adap;
- file->private_data = client;
-
-+ amd_imc_enter_scratch_ram();
-+
- return 0;
- }
-
-@@ -521,6 +524,8 @@ static int i2cdev_release(struct inode *inode, struct file *file)
- kfree(client);
- file->private_data = NULL;
-
-+ amd_imc_exit_scratch_ram();
-+
- return 0;
- }
-
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0003-drm-amdgpu-use-src-in-Makefile-v2.patch b/common/recipes-kernel/linux/files/0003-drm-amdgpu-use-src-in-Makefile-v2.patch
deleted file mode 100644
index 57182375..00000000
--- a/common/recipes-kernel/linux/files/0003-drm-amdgpu-use-src-in-Makefile-v2.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 5275bdcecdd42926a65d16ad29b48414af476b46 Mon Sep 17 00:00:00 2001
-From: Jammy Zhou <Jammy.Zhou@amd.com>
-Date: Tue, 24 Nov 2015 16:55:20 +0800
-Subject: [PATCH 0003/1110] drm/amdgpu: use $(src) in Makefile (v2)
-
-This can solve the path problem when compile amdgpu with DKMS.
-
-v2: agd: rebase on current drm-next
-
-Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Acked-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/Makefile | 10 ++++++----
- 1 file changed, 6 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
-index ca06601..178fa15 100644
---- a/drivers/gpu/drm/amd/amdgpu/Makefile
-+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
-@@ -2,10 +2,12 @@
- # Makefile for the drm device driver. This driver provides support for the
- # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-
--ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg \
-- -Idrivers/gpu/drm/amd/include \
-- -Idrivers/gpu/drm/amd/amdgpu \
-- -Idrivers/gpu/drm/amd/scheduler
-+FULL_AMD_PATH=$(src)/..
-+
-+ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
-+ -I$(FULL_AMD_PATH)/include \
-+ -I$(FULL_AMD_PATH)/amdgpu \
-+ -I$(FULL_AMD_PATH)/scheduler
-
- amdgpu-y := amdgpu_drv.o
-
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0004-drm-amdgpu-add-a-callback-for-reading-the-bios-from-.patch b/common/recipes-kernel/linux/files/0004-drm-amdgpu-add-a-callback-for-reading-the-bios-from-.patch
deleted file mode 100644
index 141a0235..00000000
--- a/common/recipes-kernel/linux/files/0004-drm-amdgpu-add-a-callback-for-reading-the-bios-from-.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From a0a9b0026f51444eaf05073bc0b1c223adbb07bd Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 10:14:28 -0500
-Subject: [PATCH 0004/1110] drm/amdgpu: add a callback for reading the bios
- from the rom directly
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is necessary when the vbios image is not directly accessible via
-the rom BAR or legacy vga location.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 053fc2f..d313225 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1829,6 +1829,8 @@ struct amdgpu_cu_info {
- */
- struct amdgpu_asic_funcs {
- bool (*read_disabled_bios)(struct amdgpu_device *adev);
-+ bool (*read_bios_from_rom)(struct amdgpu_device *adev,
-+ u8 *bios, u32 length_bytes);
- int (*read_register)(struct amdgpu_device *adev, u32 se_num,
- u32 sh_num, u32 reg_offset, u32 *value);
- void (*set_vga_state)(struct amdgpu_device *adev, bool state);
-@@ -2235,6 +2237,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
- #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
- #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
- #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
-+#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
- #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
- #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
- #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0005-drm-amdgpu-add-read_bios_from_rom-callback-for-CI-pa.patch b/common/recipes-kernel/linux/files/0005-drm-amdgpu-add-read_bios_from_rom-callback-for-CI-pa.patch
deleted file mode 100644
index f6e6f934..00000000
--- a/common/recipes-kernel/linux/files/0005-drm-amdgpu-add-read_bios_from_rom-callback-for-CI-pa.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From b24e766a5d73da9f5a4b51b31171a445298d6b1f Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 10:34:45 -0500
-Subject: [PATCH 0005/1110] drm/amdgpu: add read_bios_from_rom callback for CI
- parts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Read the vbios image directly from the rom.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/cik.c | 32 ++++++++++++++++++++++++++++++++
- 1 file changed, 32 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
-index 484710c..61689f0 100644
---- a/drivers/gpu/drm/amd/amdgpu/cik.c
-+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
-@@ -929,6 +929,37 @@ static bool cik_read_disabled_bios(struct amdgpu_device *adev)
- return r;
- }
-
-+static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
-+ u8 *bios, u32 length_bytes)
-+{
-+ u32 *dw_ptr;
-+ unsigned long flags;
-+ u32 i, length_dw;
-+
-+ if (bios == NULL)
-+ return false;
-+ if (length_bytes == 0)
-+ return false;
-+ /* APU vbios image is part of sbios image */
-+ if (adev->flags & AMD_IS_APU)
-+ return false;
-+
-+ dw_ptr = (u32 *)bios;
-+ length_dw = ALIGN(length_bytes, 4) / 4;
-+ /* take the smc lock since we are using the smc index */
-+ spin_lock_irqsave(&adev->smc_idx_lock, flags);
-+ /* set rom index to 0 */
-+ WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
-+ WREG32(mmSMC_IND_DATA_0, 0);
-+ /* set index to data for continous read */
-+ WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
-+ for (i = 0; i < length_dw; i++)
-+ dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
-+ spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-+
-+ return true;
-+}
-+
- static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
- {mmGRBM_STATUS, false},
- {mmGB_ADDR_CONFIG, false},
-@@ -2267,6 +2298,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
- static const struct amdgpu_asic_funcs cik_asic_funcs =
- {
- .read_disabled_bios = &cik_read_disabled_bios,
-+ .read_bios_from_rom = &cik_read_bios_from_rom,
- .read_register = &cik_read_register,
- .reset = &cik_asic_reset,
- .set_vga_state = &cik_vga_set_state,
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0006-drm-amdgpu-add-read_bios_from_rom-callback-for-VI-pa.patch b/common/recipes-kernel/linux/files/0006-drm-amdgpu-add-read_bios_from_rom-callback-for-VI-pa.patch
deleted file mode 100644
index 9d6a83de..00000000
--- a/common/recipes-kernel/linux/files/0006-drm-amdgpu-add-read_bios_from_rom-callback-for-VI-pa.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From b526555fa7a53776ff1925bd0bf9cef664134750 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 10:37:54 -0500
-Subject: [PATCH 0006/1110] drm/amdgpu: add read_bios_from_rom callback for VI
- parts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Read the vbios image directly from the rom.
-
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Monk Liu <monk.liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 3e9cbe3..0cb6f31 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -377,6 +377,38 @@ static bool vi_read_disabled_bios(struct amdgpu_device *adev)
- WREG32_SMC(ixROM_CNTL, rom_cntl);
- return r;
- }
-+
-+static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
-+ u8 *bios, u32 length_bytes)
-+{
-+ u32 *dw_ptr;
-+ unsigned long flags;
-+ u32 i, length_dw;
-+
-+ if (bios == NULL)
-+ return false;
-+ if (length_bytes == 0)
-+ return false;
-+ /* APU vbios image is part of sbios image */
-+ if (adev->flags & AMD_IS_APU)
-+ return false;
-+
-+ dw_ptr = (u32 *)bios;
-+ length_dw = ALIGN(length_bytes, 4) / 4;
-+ /* take the smc lock since we are using the smc index */
-+ spin_lock_irqsave(&adev->smc_idx_lock, flags);
-+ /* set rom index to 0 */
-+ WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
-+ WREG32(mmSMC_IND_DATA_0, 0);
-+ /* set index to data for continous read */
-+ WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
-+ for (i = 0; i < length_dw; i++)
-+ dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
-+ spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-+
-+ return true;
-+}
-+
- static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
- {mmGB_MACROTILE_MODE7, true},
- };
-@@ -1369,6 +1401,7 @@ static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
- static const struct amdgpu_asic_funcs vi_asic_funcs =
- {
- .read_disabled_bios = &vi_read_disabled_bios,
-+ .read_bios_from_rom = &vi_read_bios_from_rom,
- .read_register = &vi_read_register,
- .reset = &vi_asic_reset,
- .set_vga_state = &vi_vga_set_state,
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0007-drm-amdgpu-Use-new-read-bios-from-rom-callback.patch b/common/recipes-kernel/linux/files/0007-drm-amdgpu-Use-new-read-bios-from-rom-callback.patch
deleted file mode 100644
index 43ed61bb..00000000
--- a/common/recipes-kernel/linux/files/0007-drm-amdgpu-Use-new-read-bios-from-rom-callback.patch
+++ /dev/null
@@ -1,153 +0,0 @@
-From 4886ec68e93f0151fc681cf6f792fe1acba03814 Mon Sep 17 00:00:00 2001
-From: "monk.liu" <Monk.Liu@amd.com>
-Date: Thu, 29 Oct 2015 15:33:06 +0800
-Subject: [PATCH 0007/1110] drm/amdgpu: Use new read bios from rom callback
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Read the vbios directly from the rom. In some cases,
-e.g., virtualization, the rom is not available via
-the BAR or other means. Access it directly.
-
-This is an updated version of Monks original patch which
-uses family specific callbacks and unifies some of the
-validation checking.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Signed-off-by: Monk Liu <Monk.Liu@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 58 +++++++++++++++++++++++++++-----
- 1 file changed, 50 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-index c44c0c6..80add22 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
-@@ -35,6 +35,13 @@
- * BIOS.
- */
-
-+#define AMD_VBIOS_SIGNATURE " 761295520"
-+#define AMD_VBIOS_SIGNATURE_OFFSET 0x30
-+#define AMD_VBIOS_SIGNATURE_SIZE sizeof(AMD_VBIOS_SIGNATURE)
-+#define AMD_VBIOS_SIGNATURE_END (AMD_VBIOS_SIGNATURE_OFFSET + AMD_VBIOS_SIGNATURE_SIZE)
-+#define AMD_IS_VALID_VBIOS(p) ((p)[0] == 0x55 && (p)[1] == 0xAA)
-+#define AMD_VBIOS_LENGTH(p) ((p)[2] << 9)
-+
- /* If you boot an IGP board with a discrete card as the primary,
- * the IGP rom is not accessible via the rom bar as the IGP rom is
- * part of the system bios. On boot, the system bios puts a
-@@ -58,7 +65,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
- return false;
- }
-
-- if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
-+ if (size == 0 || !AMD_IS_VALID_VBIOS(bios)) {
- iounmap(bios);
- return false;
- }
-@@ -74,7 +81,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
-
- bool amdgpu_read_bios(struct amdgpu_device *adev)
- {
-- uint8_t __iomem *bios, val1, val2;
-+ uint8_t __iomem *bios, val[2];
- size_t size;
-
- adev->bios = NULL;
-@@ -84,10 +91,10 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)
- return false;
- }
-
-- val1 = readb(&bios[0]);
-- val2 = readb(&bios[1]);
-+ val[0] = readb(&bios[0]);
-+ val[1] = readb(&bios[1]);
-
-- if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
-+ if (size == 0 || !AMD_IS_VALID_VBIOS(val)) {
- pci_unmap_rom(adev->pdev, bios);
- return false;
- }
-@@ -101,6 +108,38 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)
- return true;
- }
-
-+static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)
-+{
-+ u8 header[AMD_VBIOS_SIGNATURE_END+1] = {0};
-+ int len;
-+
-+ if (!adev->asic_funcs->read_bios_from_rom)
-+ return false;
-+
-+ /* validate VBIOS signature */
-+ if (amdgpu_asic_read_bios_from_rom(adev, &header[0], sizeof(header)) == false)
-+ return false;
-+ header[AMD_VBIOS_SIGNATURE_END] = 0;
-+
-+ if ((!AMD_IS_VALID_VBIOS(header)) ||
-+ 0 != memcmp((char *)&header[AMD_VBIOS_SIGNATURE_OFFSET],
-+ AMD_VBIOS_SIGNATURE,
-+ strlen(AMD_VBIOS_SIGNATURE)))
-+ return false;
-+
-+ /* valid vbios, go on */
-+ len = AMD_VBIOS_LENGTH(header);
-+ len = ALIGN(len, 4);
-+ adev->bios = kmalloc(len, GFP_KERNEL);
-+ if (!adev->bios) {
-+ DRM_ERROR("no memory to allocate for BIOS\n");
-+ return false;
-+ }
-+
-+ /* read complete BIOS */
-+ return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);
-+}
-+
- static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
- {
- uint8_t __iomem *bios;
-@@ -113,7 +152,7 @@ static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
- return false;
- }
-
-- if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
-+ if (size == 0 || !AMD_IS_VALID_VBIOS(bios)) {
- return false;
- }
- adev->bios = kmemdup(bios, size, GFP_KERNEL);
-@@ -230,7 +269,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
- break;
- }
-
-- if (i == 0 || adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) {
-+ if (i == 0 || !AMD_IS_VALID_VBIOS(adev->bios)) {
- kfree(adev->bios);
- return false;
- }
-@@ -320,6 +359,9 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
- if (r == false)
- r = amdgpu_read_bios(adev);
- if (r == false) {
-+ r = amdgpu_read_bios_from_rom(adev);
-+ }
-+ if (r == false) {
- r = amdgpu_read_disabled_bios(adev);
- }
- if (r == false) {
-@@ -330,7 +372,7 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
- adev->bios = NULL;
- return false;
- }
-- if (adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) {
-+ if (!AMD_IS_VALID_VBIOS(adev->bios)) {
- printk("BIOS signature incorrect %x %x\n", adev->bios[0], adev->bios[1]);
- goto free_bios;
- }
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0008-drm-amdgpu-Use-unlocked-gem-unreferencing.patch b/common/recipes-kernel/linux/files/0008-drm-amdgpu-Use-unlocked-gem-unreferencing.patch
deleted file mode 100644
index b576ea36..00000000
--- a/common/recipes-kernel/linux/files/0008-drm-amdgpu-Use-unlocked-gem-unreferencing.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From e898d15a84f811ba9b0947af65fb57696c100fbc Mon Sep 17 00:00:00 2001
-From: Daniel Vetter <daniel.vetter@ffwll.ch>
-Date: Mon, 23 Nov 2015 10:32:37 +0100
-Subject: [PATCH 0008/1110] drm/amdgpu: Use unlocked gem unreferencing
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-For drm_gem_object_unreference callers are required to hold
-dev->struct_mutex, which these paths don't. Enforcing this requirement
-has become a bit more strict with
-
-commit ef4c6270bf2867e2f8032e9614d1a8cfc6c71663
-Author: Daniel Vetter <daniel.vetter@ffwll.ch>
-Date: Thu Oct 15 09:36:25 2015 +0200
-
- drm/gem: Check locking in drm_gem_object_unreference
-
-Cc: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-index 6fcbbcc..cfb6caa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
-@@ -263,7 +263,7 @@ out_unref:
-
- }
- if (fb && ret) {
-- drm_gem_object_unreference(gobj);
-+ drm_gem_object_unreference_unlocked(gobj);
- drm_framebuffer_unregister_private(fb);
- drm_framebuffer_cleanup(fb);
- kfree(fb);
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0009-drm-amdgpu-add-err-check-for-pin-userptr.patch b/common/recipes-kernel/linux/files/0009-drm-amdgpu-add-err-check-for-pin-userptr.patch
deleted file mode 100644
index f7f77fc5..00000000
--- a/common/recipes-kernel/linux/files/0009-drm-amdgpu-add-err-check-for-pin-userptr.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From de1d487e1722791013ba3b384fc679a16d6070c5 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 26 Nov 2015 16:33:58 +0800
-Subject: [PATCH 0009/1110] drm/amdgpu: add err check for pin userptr
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Missing error check if the operation failed.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-index 1cbb16e..e8fe0b7 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
-@@ -587,13 +587,13 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
- uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
- int r;
-
-- if (gtt->userptr) {
-- r = amdgpu_ttm_tt_pin_userptr(ttm);
-- if (r) {
-- DRM_ERROR("failed to pin userptr\n");
-- return r;
-- }
-- }
-+ if (gtt->userptr) {
-+ r = amdgpu_ttm_tt_pin_userptr(ttm);
-+ if (r) {
-+ DRM_ERROR("failed to pin userptr\n");
-+ return r;
-+ }
-+ }
- gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
- if (!ttm->num_pages) {
- WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0010-drm-amd-add-new-gfx8-register-definitions-for-EDC.patch b/common/recipes-kernel/linux/files/0010-drm-amd-add-new-gfx8-register-definitions-for-EDC.patch
deleted file mode 100644
index 08e1c034..00000000
--- a/common/recipes-kernel/linux/files/0010-drm-amd-add-new-gfx8-register-definitions-for-EDC.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From c8fb90402ca0bec0886137b3bbd0d4b646d9f00b Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 17:42:02 -0500
-Subject: [PATCH 0010/1110] drm/amd: add new gfx8 register definitions for EDC
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-EDC is a RAS feature for on chip memory.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-index daf763b..a9b6923 100644
---- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
-@@ -2807,5 +2807,18 @@
- #define ixDIDT_DBR_WEIGHT0_3 0x90
- #define ixDIDT_DBR_WEIGHT4_7 0x91
- #define ixDIDT_DBR_WEIGHT8_11 0x92
-+#define mmTD_EDC_CNT 0x252e
-+#define mmCPF_EDC_TAG_CNT 0x3188
-+#define mmCPF_EDC_ROQ_CNT 0x3189
-+#define mmCPF_EDC_ATC_CNT 0x318a
-+#define mmCPG_EDC_TAG_CNT 0x318b
-+#define mmCPG_EDC_ATC_CNT 0x318c
-+#define mmCPG_EDC_DMA_CNT 0x318d
-+#define mmCPC_EDC_SCRATCH_CNT 0x318e
-+#define mmCPC_EDC_UCODE_CNT 0x318f
-+#define mmCPC_EDC_ATC_CNT 0x3190
-+#define mmDC_EDC_STATE_CNT 0x3191
-+#define mmDC_EDC_CSINVOC_CNT 0x3192
-+#define mmDC_EDC_RESTORE_CNT 0x3193
-
- #endif /* GFX_8_0_D_H */
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0011-drm-amdgpu-add-EDC-support-for-CZ-v3.patch b/common/recipes-kernel/linux/files/0011-drm-amdgpu-add-EDC-support-for-CZ-v3.patch
deleted file mode 100644
index 1f5b247a..00000000
--- a/common/recipes-kernel/linux/files/0011-drm-amdgpu-add-EDC-support-for-CZ-v3.patch
+++ /dev/null
@@ -1,384 +0,0 @@
-From 2096458a304a38ca3f983174fba7a82946c0e5dd Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Tue, 24 Nov 2015 17:43:42 -0500
-Subject: [PATCH 0011/1110] drm/amdgpu: add EDC support for CZ (v3)
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This adds EDC support for CZ.
-EDC = Error Correction and Detection
-This code properly initializes the EDC hardware and
-resets the error counts. This is done in late_init
-since it requires the IB pool which is not initialized
-during hw_init.
-
-v2: fix the IB size as noted by Felix, fix shader pgm
-register programming
-v3: use the IB for the shaders as suggested by Christian
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 331 +++++++++++++++++++++++++++++++++-
- 1 file changed, 330 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index d105403..bc72883 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -964,6 +964,322 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
- return 0;
- }
-
-+static const u32 vgpr_init_compute_shader[] =
-+{
-+ 0x7e000209, 0x7e020208,
-+ 0x7e040207, 0x7e060206,
-+ 0x7e080205, 0x7e0a0204,
-+ 0x7e0c0203, 0x7e0e0202,
-+ 0x7e100201, 0x7e120200,
-+ 0x7e140209, 0x7e160208,
-+ 0x7e180207, 0x7e1a0206,
-+ 0x7e1c0205, 0x7e1e0204,
-+ 0x7e200203, 0x7e220202,
-+ 0x7e240201, 0x7e260200,
-+ 0x7e280209, 0x7e2a0208,
-+ 0x7e2c0207, 0x7e2e0206,
-+ 0x7e300205, 0x7e320204,
-+ 0x7e340203, 0x7e360202,
-+ 0x7e380201, 0x7e3a0200,
-+ 0x7e3c0209, 0x7e3e0208,
-+ 0x7e400207, 0x7e420206,
-+ 0x7e440205, 0x7e460204,
-+ 0x7e480203, 0x7e4a0202,
-+ 0x7e4c0201, 0x7e4e0200,
-+ 0x7e500209, 0x7e520208,
-+ 0x7e540207, 0x7e560206,
-+ 0x7e580205, 0x7e5a0204,
-+ 0x7e5c0203, 0x7e5e0202,
-+ 0x7e600201, 0x7e620200,
-+ 0x7e640209, 0x7e660208,
-+ 0x7e680207, 0x7e6a0206,
-+ 0x7e6c0205, 0x7e6e0204,
-+ 0x7e700203, 0x7e720202,
-+ 0x7e740201, 0x7e760200,
-+ 0x7e780209, 0x7e7a0208,
-+ 0x7e7c0207, 0x7e7e0206,
-+ 0xbf8a0000, 0xbf810000,
-+};
-+
-+static const u32 sgpr_init_compute_shader[] =
-+{
-+ 0xbe8a0100, 0xbe8c0102,
-+ 0xbe8e0104, 0xbe900106,
-+ 0xbe920108, 0xbe940100,
-+ 0xbe960102, 0xbe980104,
-+ 0xbe9a0106, 0xbe9c0108,
-+ 0xbe9e0100, 0xbea00102,
-+ 0xbea20104, 0xbea40106,
-+ 0xbea60108, 0xbea80100,
-+ 0xbeaa0102, 0xbeac0104,
-+ 0xbeae0106, 0xbeb00108,
-+ 0xbeb20100, 0xbeb40102,
-+ 0xbeb60104, 0xbeb80106,
-+ 0xbeba0108, 0xbebc0100,
-+ 0xbebe0102, 0xbec00104,
-+ 0xbec20106, 0xbec40108,
-+ 0xbec60100, 0xbec80102,
-+ 0xbee60004, 0xbee70005,
-+ 0xbeea0006, 0xbeeb0007,
-+ 0xbee80008, 0xbee90009,
-+ 0xbefc0000, 0xbf8a0000,
-+ 0xbf810000, 0x00000000,
-+};
-+
-+static const u32 vgpr_init_regs[] =
-+{
-+ mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
-+ mmCOMPUTE_RESOURCE_LIMITS, 0,
-+ mmCOMPUTE_NUM_THREAD_X, 256*4,
-+ mmCOMPUTE_NUM_THREAD_Y, 1,
-+ mmCOMPUTE_NUM_THREAD_Z, 1,
-+ mmCOMPUTE_PGM_RSRC2, 20,
-+ mmCOMPUTE_USER_DATA_0, 0xedcedc00,
-+ mmCOMPUTE_USER_DATA_1, 0xedcedc01,
-+ mmCOMPUTE_USER_DATA_2, 0xedcedc02,
-+ mmCOMPUTE_USER_DATA_3, 0xedcedc03,
-+ mmCOMPUTE_USER_DATA_4, 0xedcedc04,
-+ mmCOMPUTE_USER_DATA_5, 0xedcedc05,
-+ mmCOMPUTE_USER_DATA_6, 0xedcedc06,
-+ mmCOMPUTE_USER_DATA_7, 0xedcedc07,
-+ mmCOMPUTE_USER_DATA_8, 0xedcedc08,
-+ mmCOMPUTE_USER_DATA_9, 0xedcedc09,
-+};
-+
-+static const u32 sgpr1_init_regs[] =
-+{
-+ mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
-+ mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
-+ mmCOMPUTE_NUM_THREAD_X, 256*5,
-+ mmCOMPUTE_NUM_THREAD_Y, 1,
-+ mmCOMPUTE_NUM_THREAD_Z, 1,
-+ mmCOMPUTE_PGM_RSRC2, 20,
-+ mmCOMPUTE_USER_DATA_0, 0xedcedc00,
-+ mmCOMPUTE_USER_DATA_1, 0xedcedc01,
-+ mmCOMPUTE_USER_DATA_2, 0xedcedc02,
-+ mmCOMPUTE_USER_DATA_3, 0xedcedc03,
-+ mmCOMPUTE_USER_DATA_4, 0xedcedc04,
-+ mmCOMPUTE_USER_DATA_5, 0xedcedc05,
-+ mmCOMPUTE_USER_DATA_6, 0xedcedc06,
-+ mmCOMPUTE_USER_DATA_7, 0xedcedc07,
-+ mmCOMPUTE_USER_DATA_8, 0xedcedc08,
-+ mmCOMPUTE_USER_DATA_9, 0xedcedc09,
-+};
-+
-+static const u32 sgpr2_init_regs[] =
-+{
-+ mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
-+ mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
-+ mmCOMPUTE_NUM_THREAD_X, 256*5,
-+ mmCOMPUTE_NUM_THREAD_Y, 1,
-+ mmCOMPUTE_NUM_THREAD_Z, 1,
-+ mmCOMPUTE_PGM_RSRC2, 20,
-+ mmCOMPUTE_USER_DATA_0, 0xedcedc00,
-+ mmCOMPUTE_USER_DATA_1, 0xedcedc01,
-+ mmCOMPUTE_USER_DATA_2, 0xedcedc02,
-+ mmCOMPUTE_USER_DATA_3, 0xedcedc03,
-+ mmCOMPUTE_USER_DATA_4, 0xedcedc04,
-+ mmCOMPUTE_USER_DATA_5, 0xedcedc05,
-+ mmCOMPUTE_USER_DATA_6, 0xedcedc06,
-+ mmCOMPUTE_USER_DATA_7, 0xedcedc07,
-+ mmCOMPUTE_USER_DATA_8, 0xedcedc08,
-+ mmCOMPUTE_USER_DATA_9, 0xedcedc09,
-+};
-+
-+static const u32 sec_ded_counter_registers[] =
-+{
-+ mmCPC_EDC_ATC_CNT,
-+ mmCPC_EDC_SCRATCH_CNT,
-+ mmCPC_EDC_UCODE_CNT,
-+ mmCPF_EDC_ATC_CNT,
-+ mmCPF_EDC_ROQ_CNT,
-+ mmCPF_EDC_TAG_CNT,
-+ mmCPG_EDC_ATC_CNT,
-+ mmCPG_EDC_DMA_CNT,
-+ mmCPG_EDC_TAG_CNT,
-+ mmDC_EDC_CSINVOC_CNT,
-+ mmDC_EDC_RESTORE_CNT,
-+ mmDC_EDC_STATE_CNT,
-+ mmGDS_EDC_CNT,
-+ mmGDS_EDC_GRBM_CNT,
-+ mmGDS_EDC_OA_DED,
-+ mmSPI_EDC_CNT,
-+ mmSQC_ATC_EDC_GATCL1_CNT,
-+ mmSQC_EDC_CNT,
-+ mmSQ_EDC_DED_CNT,
-+ mmSQ_EDC_INFO,
-+ mmSQ_EDC_SEC_CNT,
-+ mmTCC_EDC_CNT,
-+ mmTCP_ATC_EDC_GATCL1_CNT,
-+ mmTCP_EDC_CNT,
-+ mmTD_EDC_CNT
-+};
-+
-+static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
-+{
-+ struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
-+ struct amdgpu_ib ib;
-+ struct fence *f = NULL;
-+ int r, i;
-+ u32 tmp;
-+ unsigned total_size, vgpr_offset, sgpr_offset;
-+ u64 gpu_addr;
-+
-+ /* only supported on CZ */
-+ if (adev->asic_type != CHIP_CARRIZO)
-+ return 0;
-+
-+ /* bail if the compute ring is not ready */
-+ if (!ring->ready)
-+ return 0;
-+
-+ tmp = RREG32(mmGB_EDC_MODE);
-+ WREG32(mmGB_EDC_MODE, 0);
-+
-+ total_size =
-+ (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
-+ total_size +=
-+ (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
-+ total_size +=
-+ (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
-+ total_size = ALIGN(total_size, 256);
-+ vgpr_offset = total_size;
-+ total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
-+ sgpr_offset = total_size;
-+ total_size += sizeof(sgpr_init_compute_shader);
-+
-+ /* allocate an indirect buffer to put the commands in */
-+ memset(&ib, 0, sizeof(ib));
-+ r = amdgpu_ib_get(ring, NULL, total_size, &ib);
-+ if (r) {
-+ DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
-+ return r;
-+ }
-+
-+ /* load the compute shaders */
-+ for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
-+ ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
-+
-+ for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
-+ ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
-+
-+ /* init the ib length to 0 */
-+ ib.length_dw = 0;
-+
-+ /* VGPR */
-+ /* write the register state for the compute dispatch */
-+ for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
-+ ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
-+ ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
-+ }
-+ /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
-+ gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
-+ ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
-+ ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
-+ ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
-+
-+ /* write dispatch packet */
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-+ ib.ptr[ib.length_dw++] = 8; /* x */
-+ ib.ptr[ib.length_dw++] = 1; /* y */
-+ ib.ptr[ib.length_dw++] = 1; /* z */
-+ ib.ptr[ib.length_dw++] =
-+ REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
-+
-+ /* write CS partial flush packet */
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
-+ ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
-+
-+ /* SGPR1 */
-+ /* write the register state for the compute dispatch */
-+ for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
-+ ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
-+ ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
-+ }
-+ /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
-+ gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
-+ ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
-+ ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
-+ ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
-+
-+ /* write dispatch packet */
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-+ ib.ptr[ib.length_dw++] = 8; /* x */
-+ ib.ptr[ib.length_dw++] = 1; /* y */
-+ ib.ptr[ib.length_dw++] = 1; /* z */
-+ ib.ptr[ib.length_dw++] =
-+ REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
-+
-+ /* write CS partial flush packet */
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
-+ ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
-+
-+ /* SGPR2 */
-+ /* write the register state for the compute dispatch */
-+ for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
-+ ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
-+ ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
-+ }
-+ /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
-+ gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
-+ ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
-+ ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
-+ ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
-+
-+ /* write dispatch packet */
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
-+ ib.ptr[ib.length_dw++] = 8; /* x */
-+ ib.ptr[ib.length_dw++] = 1; /* y */
-+ ib.ptr[ib.length_dw++] = 1; /* z */
-+ ib.ptr[ib.length_dw++] =
-+ REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
-+
-+ /* write CS partial flush packet */
-+ ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
-+ ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
-+
-+ /* shedule the ib on the ring */
-+ r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
-+ AMDGPU_FENCE_OWNER_UNDEFINED,
-+ &f);
-+ if (r) {
-+ DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
-+ goto fail;
-+ }
-+
-+ /* wait for the GPU to finish processing the IB */
-+ r = fence_wait(f, false);
-+ if (r) {
-+ DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
-+ goto fail;
-+ }
-+
-+ tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
-+ tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
-+ WREG32(mmGB_EDC_MODE, tmp);
-+
-+ tmp = RREG32(mmCC_GC_EDC_CONFIG);
-+ tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
-+ WREG32(mmCC_GC_EDC_CONFIG, tmp);
-+
-+
-+ /* read back registers to clear the counters */
-+ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
-+ RREG32(sec_ded_counter_registers[i]);
-+
-+fail:
-+ fence_put(f);
-+ amdgpu_ib_free(adev, &ib);
-+
-+ return r;
-+}
-+
- static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
- {
- u32 gb_addr_config;
-@@ -4458,6 +4774,19 @@ static int gfx_v8_0_early_init(void *handle)
- return 0;
- }
-
-+static int gfx_v8_0_late_init(void *handle)
-+{
-+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+ int r;
-+
-+ /* requires IBs so do in late init after IB pool is initialized */
-+ r = gfx_v8_0_do_edc_gpr_workarounds(adev);
-+ if (r)
-+ return r;
-+
-+ return 0;
-+}
-+
- static int gfx_v8_0_set_powergating_state(void *handle,
- enum amd_powergating_state state)
- {
-@@ -4996,7 +5325,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
-
- const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
- .early_init = gfx_v8_0_early_init,
-- .late_init = NULL,
-+ .late_init = gfx_v8_0_late_init,
- .sw_init = gfx_v8_0_sw_init,
- .sw_fini = gfx_v8_0_sw_fini,
- .hw_init = gfx_v8_0_hw_init,
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0012-drm-amd-abstract-kernel-rq-and-normal-rq-to-priority.patch b/common/recipes-kernel/linux/files/0012-drm-amd-abstract-kernel-rq-and-normal-rq-to-priority.patch
deleted file mode 100644
index 2366e803..00000000
--- a/common/recipes-kernel/linux/files/0012-drm-amd-abstract-kernel-rq-and-normal-rq-to-priority.patch
+++ /dev/null
@@ -1,155 +0,0 @@
-From b0d5d1dd7c190c9a20369c4ef0880a1ffdfa95f9 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 5 Nov 2015 15:23:09 +0800
-Subject: [PATCH 0012/1110] drm/amd: abstract kernel rq and normal rq to
- priority of run queue
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Allows us to set priorities in the scheduler.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 11 +++++------
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 14 +++++++++-----
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 9 +++++++--
- 5 files changed, 23 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index d313225..e85ed1b 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1045,7 +1045,7 @@ struct amdgpu_ctx_mgr {
- struct idr ctx_handles;
- };
-
--int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
-+int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- struct amdgpu_ctx *ctx);
- void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index fec65f0..c1f2308 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -25,7 +25,7 @@
- #include <drm/drmP.h>
- #include "amdgpu.h"
-
--int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
-+int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- struct amdgpu_ctx *ctx)
- {
- unsigned i, j;
-@@ -42,10 +42,9 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
- /* create context entity for each ring */
- for (i = 0; i < adev->num_rings; i++) {
- struct amd_sched_rq *rq;
-- if (kernel)
-- rq = &adev->rings[i]->sched.kernel_rq;
-- else
-- rq = &adev->rings[i]->sched.sched_rq;
-+ if (pri >= AMD_SCHED_MAX_PRIORITY)
-+ return -EINVAL;
-+ rq = &adev->rings[i]->sched.sched_rq[pri];
- r = amd_sched_entity_init(&adev->rings[i]->sched,
- &ctx->rings[i].entity,
- rq, amdgpu_sched_jobs);
-@@ -103,7 +102,7 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
- return r;
- }
- *id = (uint32_t)r;
-- r = amdgpu_ctx_init(adev, false, ctx);
-+ r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_NORMAL, ctx);
- mutex_unlock(&mgr->lock);
-
- return r;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index c961fe0..c5206fd 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1528,7 +1528,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- return r;
- }
-
-- r = amdgpu_ctx_init(adev, true, &adev->kernel_ctx);
-+ r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_KERNEL, &adev->kernel_ctx);
- if (r) {
- dev_err(adev->dev, "failed to create kernel context (%d).\n", r);
- return r;
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 3a4820e..5ace1a7 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -349,14 +349,17 @@ static struct amd_sched_entity *
- amd_sched_select_entity(struct amd_gpu_scheduler *sched)
- {
- struct amd_sched_entity *entity;
-+ int i;
-
- if (!amd_sched_ready(sched))
- return NULL;
-
- /* Kernel run queue has higher priority than normal run queue*/
-- entity = amd_sched_rq_select_entity(&sched->kernel_rq);
-- if (entity == NULL)
-- entity = amd_sched_rq_select_entity(&sched->sched_rq);
-+ for (i = 0; i < AMD_SCHED_MAX_PRIORITY; i++) {
-+ entity = amd_sched_rq_select_entity(&sched->sched_rq[i]);
-+ if (entity)
-+ break;
-+ }
-
- return entity;
- }
-@@ -478,12 +481,13 @@ int amd_sched_init(struct amd_gpu_scheduler *sched,
- struct amd_sched_backend_ops *ops,
- unsigned hw_submission, long timeout, const char *name)
- {
-+ int i;
- sched->ops = ops;
- sched->hw_submission_limit = hw_submission;
- sched->name = name;
- sched->timeout = timeout;
-- amd_sched_rq_init(&sched->sched_rq);
-- amd_sched_rq_init(&sched->kernel_rq);
-+ for (i = 0; i < AMD_SCHED_MAX_PRIORITY; i++)
-+ amd_sched_rq_init(&sched->sched_rq[i]);
-
- init_waitqueue_head(&sched->wake_up_worker);
- init_waitqueue_head(&sched->job_scheduled);
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-index a0f0ae5..9403145 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
-@@ -104,6 +104,12 @@ struct amd_sched_backend_ops {
- struct fence *(*run_job)(struct amd_sched_job *sched_job);
- };
-
-+enum amd_sched_priority {
-+ AMD_SCHED_PRIORITY_KERNEL = 0,
-+ AMD_SCHED_PRIORITY_NORMAL,
-+ AMD_SCHED_MAX_PRIORITY
-+};
-+
- /**
- * One scheduler is implemented for each hardware ring
- */
-@@ -112,8 +118,7 @@ struct amd_gpu_scheduler {
- uint32_t hw_submission_limit;
- long timeout;
- const char *name;
-- struct amd_sched_rq sched_rq;
-- struct amd_sched_rq kernel_rq;
-+ struct amd_sched_rq sched_rq[AMD_SCHED_MAX_PRIORITY];
- wait_queue_head_t wake_up_worker;
- wait_queue_head_t job_scheduled;
- atomic_t hw_rq_count;
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0013-amdgpu-gfxv8-Add-missing-break-to-switch-statement-f.patch b/common/recipes-kernel/linux/files/0013-amdgpu-gfxv8-Add-missing-break-to-switch-statement-f.patch
deleted file mode 100644
index 5ecc4989..00000000
--- a/common/recipes-kernel/linux/files/0013-amdgpu-gfxv8-Add-missing-break-to-switch-statement-f.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 4a99da7413e28c0a9ffe7e258981e57ba0b6dfeb Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Mon, 30 Nov 2015 14:13:11 -0500
-Subject: [PATCH 0013/1110] amdgpu/gfxv8: Add missing break to switch statement
- from states init code
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index bc72883..2dd0583 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1923,6 +1923,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
- }
-+ break;
- case CHIP_FIJI:
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch b/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch
deleted file mode 100644
index 84fa3f14..00000000
--- a/common/recipes-kernel/linux/files/0014-amdgpu-gfxv8-Cleanup-of-gfx_v8_0_tiling_mode_table_i.patch
+++ /dev/null
@@ -1,2338 +0,0 @@
-From a420ce17e2154d83fa3c3f6c8ad91393cc49cdd6 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 1 Dec 2015 11:47:21 -0500
-Subject: [PATCH 0014/1110] amdgpu/gfxv8: Cleanup of
- gfx_v8_0_tiling_mode_table_init() (v2)
-
-Simplification and LOC reduction of function gfx_v8_0_tiling_mode_table_init()
-
-v2: remove spurious break
-bug: https://bugs.freedesktop.org/show_bug.cgi?id=93236
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2286 +++++++++++++--------------------
- 1 file changed, 898 insertions(+), 1388 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 2dd0583..f85de15 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1639,1407 +1639,917 @@ static int gfx_v8_0_sw_fini(void *handle)
-
- static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- {
-+ uint32_t *modearray, *mod2array;
- const u32 num_tile_mode_states = 32;
- const u32 num_secondary_tile_mode_states = 16;
-- u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
-+ u32 reg_offset;
-
-- switch (adev->gfx.config.mem_row_size_in_kb) {
-- case 1:
-- split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
-- break;
-- case 2:
-- default:
-- split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
-- break;
-- case 4:
-- split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
-- break;
-- }
-+ modearray = adev->gfx.config.tile_mode_array;
-+ mod2array = adev->gfx.config.macrotile_mode_array;
-+
-+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+ modearray[reg_offset] = 0;
-+
-+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+ mod2array[reg_offset] = 0;
-
- switch (adev->asic_type) {
- case CHIP_TOPAZ:
-- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 1:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 2:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 3:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 4:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 5:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 6:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 8:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-- PIPE_CONFIG(ADDR_SURF_P2));
-- break;
-- case 9:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 10:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 11:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 13:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 14:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 15:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 16:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 18:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 19:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 20:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 21:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 22:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 24:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 25:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 26:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 27:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 28:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 29:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 7:
-- case 12:
-- case 17:
-- case 23:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 1:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 2:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 3:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 4:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 5:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 6:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 8:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 9:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 10:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 11:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 12:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 13:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 14:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 7:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-+ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+ PIPE_CONFIG(ADDR_SURF_P2));
-+ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
-+ reg_offset != 23)
-+ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7)
-+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- break;
- case CHIP_FIJI:
-- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 1:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 2:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 3:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 4:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 5:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 6:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 7:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 8:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
-- break;
-- case 9:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 10:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 11:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 12:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 13:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 14:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 15:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 16:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 17:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 18:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 19:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 20:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 21:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 22:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 23:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 24:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 25:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 26:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 27:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 28:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 29:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 30:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- default:
-- gb_tile_moden = 0;
-- break;
-- }
-- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 1:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 2:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 3:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 4:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 5:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 6:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 8:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 9:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 10:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 11:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 12:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 13:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 14:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 7:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- }
-- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-+ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
-+ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7)
-+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- break;
- case CHIP_TONGA:
-- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 1:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 2:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 3:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 4:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 5:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 6:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 7:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 8:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
-- break;
-- case 9:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 10:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 11:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 12:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 13:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 14:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 15:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 16:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 17:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 18:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 19:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 20:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 21:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 22:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 23:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 24:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 25:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 26:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 27:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 28:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 29:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 30:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 1:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 2:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 3:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 4:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 5:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 6:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 8:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 9:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 10:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 11:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 12:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 13:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 14:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-- NUM_BANKS(ADDR_SURF_4_BANK));
-- break;
-- case 7:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-+ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
-+ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_4_BANK));
-+ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-+ NUM_BANKS(ADDR_SURF_4_BANK));
-+
-+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7)
-+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- break;
- case CHIP_STONEY:
-- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 1:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 2:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 3:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 4:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 5:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 6:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 8:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-- PIPE_CONFIG(ADDR_SURF_P2));
-- break;
-- case 9:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 10:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 11:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 13:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 14:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 15:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 16:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 18:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 19:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 20:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 21:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 22:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 24:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 25:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 26:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 27:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 28:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 29:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 7:
-- case 12:
-- case 17:
-- case 23:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 1:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 2:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 3:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 4:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 5:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 6:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 8:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 9:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 10:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 11:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 12:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 13:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 14:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 7:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-+ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+ PIPE_CONFIG(ADDR_SURF_P2));
-+ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
-+ reg_offset != 23)
-+ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7)
-+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
- break;
-- case CHIP_CARRIZO:
- default:
-- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 1:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 2:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 3:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 4:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 5:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 6:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-- break;
-- case 8:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-- PIPE_CONFIG(ADDR_SURF_P2));
-- break;
-- case 9:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 10:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 11:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 13:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 14:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 15:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 16:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 18:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 19:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 20:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 21:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 22:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 24:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 25:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 26:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-- break;
-- case 27:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 28:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-- break;
-- case 29:
-- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-- PIPE_CONFIG(ADDR_SURF_P2) |
-- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-- break;
-- case 7:
-- case 12:
-- case 17:
-- case 23:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
-- switch (reg_offset) {
-- case 0:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 1:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 2:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 3:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 4:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 5:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 6:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 8:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 9:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 10:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 11:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 12:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 13:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-- NUM_BANKS(ADDR_SURF_16_BANK));
-- break;
-- case 14:
-- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-- NUM_BANKS(ADDR_SURF_8_BANK));
-- break;
-- case 7:
-- /* unused idx */
-- continue;
-- default:
-- gb_tile_moden = 0;
-- break;
-- };
-- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
-- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
-- }
-+ dev_warn(adev->dev,
-+ "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
-+ adev->asic_type);
-+
-+ case CHIP_CARRIZO:
-+ modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-+ modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-+ PIPE_CONFIG(ADDR_SURF_P2));
-+ modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+ modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
-+ modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-+ modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-+ PIPE_CONFIG(ADDR_SURF_P2) |
-+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
-+
-+ mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+ mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-+ NUM_BANKS(ADDR_SURF_16_BANK));
-+ mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-+ NUM_BANKS(ADDR_SURF_8_BANK));
-+
-+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
-+ reg_offset != 23)
-+ WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
-+
-+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
-+ if (reg_offset != 7)
-+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
-+
-+ break;
- }
- }
-
-@@ -4957,7 +4467,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
- EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
- EVENT_INDEX(5)));
- amdgpu_ring_write(ring, addr & 0xfffffffc);
-- amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
-+ amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
- DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
- amdgpu_ring_write(ring, lower_32_bits(seq));
- amdgpu_ring_write(ring, upper_32_bits(seq));
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0015-amdgpu-gfxv8-Simplification-of-gfx_v8_0_create_bitma.patch b/common/recipes-kernel/linux/files/0015-amdgpu-gfxv8-Simplification-of-gfx_v8_0_create_bitma.patch
deleted file mode 100644
index 8efc17c3..00000000
--- a/common/recipes-kernel/linux/files/0015-amdgpu-gfxv8-Simplification-of-gfx_v8_0_create_bitma.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 1e6e1ab728900b26bec4de25fc5d851133137c0b Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 1 Dec 2015 11:48:32 -0500
-Subject: [PATCH 0015/1110] amdgpu/gfxv8: Simplification of
- gfx_v8_0_create_bitmask()
-
-Simplification of the function gfx_v8_0_create_bitmask().
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 +-------
- 1 file changed, 1 insertion(+), 7 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index f85de15..38f960c 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2555,13 +2555,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
-
- static u32 gfx_v8_0_create_bitmask(u32 bit_width)
- {
-- u32 i, mask = 0;
--
-- for (i = 0; i < bit_width; i++) {
-- mask <<= 1;
-- mask |= 1;
-- }
-- return mask;
-+ return (u32)((1ULL << bit_width) - 1);
- }
-
- void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0016-amdgpu-gfxv8-Simplification-in-gfx_v8_0_enable_gui_i.patch b/common/recipes-kernel/linux/files/0016-amdgpu-gfxv8-Simplification-in-gfx_v8_0_enable_gui_i.patch
deleted file mode 100644
index b6e77ef4..00000000
--- a/common/recipes-kernel/linux/files/0016-amdgpu-gfxv8-Simplification-in-gfx_v8_0_enable_gui_i.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 8b58a7e84ac160e687c8a184833c4d6210125dd2 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Tue, 1 Dec 2015 10:42:28 -0500
-Subject: [PATCH 0016/1110] amdgpu/gfxv8: Simplification in
- gfx_v8_0_enable_gui_idle_interrupt()
-
-Simplified the function by folding the two paths into one.
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 16 +++++-----------
- 1 file changed, 5 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 38f960c..0446565 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2818,17 +2818,11 @@ static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
- {
- u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
-
-- if (enable) {
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
-- } else {
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
-- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
-- }
-+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
-+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
-+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
-+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
-+
- WREG32(mmCP_INT_CNTL_RING0, tmp);
- }
-
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0017-amdgpu-gfxv8-Remove-magic-numbers-from-function-gfx_.patch b/common/recipes-kernel/linux/files/0017-amdgpu-gfxv8-Remove-magic-numbers-from-function-gfx_.patch
deleted file mode 100644
index 8b3a2684..00000000
--- a/common/recipes-kernel/linux/files/0017-amdgpu-gfxv8-Remove-magic-numbers-from-function-gfx_.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From a238e5cbb433f5a0df5ca1c4125f20fa61bc4914 Mon Sep 17 00:00:00 2001
-From: Tom St Denis <tom.stdenis@amd.com>
-Date: Thu, 3 Dec 2015 12:23:28 -0500
-Subject: [PATCH 0017/1110] amdgpu/gfxv8: Remove magic numbers from function
- gfx_v8_0_tiling_mode_table_init()
-
-Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 0446565..15db401 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -1640,8 +1640,8 @@ static int gfx_v8_0_sw_fini(void *handle)
- static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
- {
- uint32_t *modearray, *mod2array;
-- const u32 num_tile_mode_states = 32;
-- const u32 num_secondary_tile_mode_states = 16;
-+ const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-+ const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
- u32 reg_offset;
-
- modearray = adev->gfx.config.tile_mode_array;
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0018-drm-Move-LEAVE-ENTER_ATOMIC_MODESET-to-fbdev-helpers.patch b/common/recipes-kernel/linux/files/0018-drm-Move-LEAVE-ENTER_ATOMIC_MODESET-to-fbdev-helpers.patch
deleted file mode 100644
index f8d04042..00000000
--- a/common/recipes-kernel/linux/files/0018-drm-Move-LEAVE-ENTER_ATOMIC_MODESET-to-fbdev-helpers.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 0dd3eb7611d2cb97a1ad7c02ea7d504bf0e5a086 Mon Sep 17 00:00:00 2001
-From: Daniel Vetter <daniel.vetter@ffwll.ch>
-Date: Fri, 4 Dec 2015 09:45:43 +0100
-Subject: [PATCH 0018/1110] drm: Move LEAVE/ENTER_ATOMIC_MODESET to fbdev
- helpers
-
-This is only used for kgdb (and previously panic) handlers in
-the fbdev emulation, so belongs there.
-
-Note that this means we'll leave behind a forward declaration, but
-once all the helper vtables are consolidated (in the next patch) that
-will make more sense.
-
-v2: fixup radone/amdgpu.
-
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Link: http://patchwork.freedesktop.org/patch/msgid/1449218769-16577-3-git-send-email-daniel.vetter@ffwll.ch
-Reviewed-by: Thierry Reding <treding@nvidia.com> (v2)
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index cfb48e3..3b2d75d 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-@@ -35,6 +35,7 @@
- #include <drm/drm_dp_helper.h>
- #include <drm/drm_fixed.h>
- #include <drm/drm_crtc_helper.h>
-+#include <drm/drm_fb_helper.h>
- #include <drm/drm_plane_helper.h>
- #include <linux/i2c.h>
- #include <linux/i2c-algo-bit.h>
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0019-drm-Pass-name-to-drm_encoder_init.patch b/common/recipes-kernel/linux/files/0019-drm-Pass-name-to-drm_encoder_init.patch
deleted file mode 100644
index b687b44e..00000000
--- a/common/recipes-kernel/linux/files/0019-drm-Pass-name-to-drm_encoder_init.patch
+++ /dev/null
@@ -1,202 +0,0 @@
-From 374964ea1da0a7d2a78d715cb6cf886b751ce16c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
-Date: Wed, 9 Dec 2015 16:20:18 +0200
-Subject: [PATCH 0019/1110] drm: Pass 'name' to drm_encoder_init()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Done with coccinelle for the most part. However, it thinks '...' is
-part of the semantic patch, so I put an 'int DOTDOTDOT' placeholder
-in its place and got rid of it with sed afterwards.
-
-@@
-identifier dev, encoder, funcs;
-@@
- int drm_encoder_init(struct drm_device *dev,
- struct drm_encoder *encoder,
- const struct drm_encoder_funcs *funcs,
- int encoder_type
-+ ,const char *name, int DOTDOTDOT
- )
-{ ... }
-
-@@
-identifier dev, encoder, funcs;
-@@
- int drm_encoder_init(struct drm_device *dev,
- struct drm_encoder *encoder,
- const struct drm_encoder_funcs *funcs,
- int encoder_type
-+ ,const char *name, int DOTDOTDOT
- );
-
-@@
-expression E1, E2, E3, E4;
-@@
- drm_encoder_init(E1, E2, E3, E4
-+ ,NULL
- )
-
-v2: Add ', or NULL...' to @name kernel doc (Jani)
- Annotate the function with __printf() attribute (Jani)
-
-Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Link: http://patchwork.freedesktop.org/patch/msgid/1449670818-2966-1-git-send-email-ville.syrjala@linux.intel.com
----
- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 14 +++++++-------
- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 14 +++++++-------
- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 14 +++++++-------
- 3 files changed, 21 insertions(+), 21 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-index 4dcc8fb..093599a 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
-@@ -3729,7 +3729,7 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
- break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3740,15 +3740,15 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- amdgpu_encoder->rmx_type = RMX_FULL;
- drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
-- DRM_MODE_ENCODER_LVDS);
-+ DRM_MODE_ENCODER_LVDS, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- } else {
- drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
-- DRM_MODE_ENCODER_TMDS);
-+ DRM_MODE_ENCODER_TMDS, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- }
- drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
-@@ -3766,13 +3766,13 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- amdgpu_encoder->is_ext_encoder = true;
- if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
-- DRM_MODE_ENCODER_LVDS);
-+ DRM_MODE_ENCODER_LVDS, NULL);
- else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- else
- drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
-- DRM_MODE_ENCODER_TMDS);
-+ DRM_MODE_ENCODER_TMDS, NULL);
- drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
- break;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-index 8f1e511..8701661 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
-@@ -3722,7 +3722,7 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
- break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3733,15 +3733,15 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- amdgpu_encoder->rmx_type = RMX_FULL;
- drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
-- DRM_MODE_ENCODER_LVDS);
-+ DRM_MODE_ENCODER_LVDS, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- } else {
- drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
-- DRM_MODE_ENCODER_TMDS);
-+ DRM_MODE_ENCODER_TMDS, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- }
- drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
-@@ -3759,13 +3759,13 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- amdgpu_encoder->is_ext_encoder = true;
- if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
-- DRM_MODE_ENCODER_LVDS);
-+ DRM_MODE_ENCODER_LVDS, NULL);
- else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- else
- drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
-- DRM_MODE_ENCODER_TMDS);
-+ DRM_MODE_ENCODER_TMDS, NULL);
- drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
- break;
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-index 42d954d..d0e128c 100644
---- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
-@@ -3659,7 +3659,7 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
- drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
- break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
-@@ -3670,15 +3670,15 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
- if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
- amdgpu_encoder->rmx_type = RMX_FULL;
- drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
-- DRM_MODE_ENCODER_LVDS);
-+ DRM_MODE_ENCODER_LVDS, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
- } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
- drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- } else {
- drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
-- DRM_MODE_ENCODER_TMDS);
-+ DRM_MODE_ENCODER_TMDS, NULL);
- amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
- }
- drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
-@@ -3696,13 +3696,13 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
- amdgpu_encoder->is_ext_encoder = true;
- if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
- drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
-- DRM_MODE_ENCODER_LVDS);
-+ DRM_MODE_ENCODER_LVDS, NULL);
- else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
- drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
-- DRM_MODE_ENCODER_DAC);
-+ DRM_MODE_ENCODER_DAC, NULL);
- else
- drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
-- DRM_MODE_ENCODER_TMDS);
-+ DRM_MODE_ENCODER_TMDS, NULL);
- drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
- break;
- }
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0020-drm-amdgpu-gfx8-Enable-interrupt-on-ME1_PIPE3.patch b/common/recipes-kernel/linux/files/0020-drm-amdgpu-gfx8-Enable-interrupt-on-ME1_PIPE3.patch
deleted file mode 100644
index 18eb9f33..00000000
--- a/common/recipes-kernel/linux/files/0020-drm-amdgpu-gfx8-Enable-interrupt-on-ME1_PIPE3.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 1d6c3c343ad0b1162aae90758b2de30d8aab64a1 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Wed, 2 Dec 2015 09:56:06 +0800
-Subject: [PATCH 0020/1110] drm/amdgpu/gfx8: Enable interrupt on ME1_PIPE3
-
-Otherwise FW cannot see the RLC ACK for the memory clean request
-It's for Stoney.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 15db401..5a6bb34 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -3756,6 +3756,11 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
- tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
- WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
- mqd->cp_hqd_persistent_state = tmp;
-+ if (adev->asic_type == CHIP_STONEY) {
-+ tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
-+ tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
-+ WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
-+ }
-
- /* activate the queue */
- mqd->cp_hqd_active = 1;
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0021-drm-amdgpu-gfx8-update-PA_SC_RASTER_CONFIG-PKR_MAP-o.patch b/common/recipes-kernel/linux/files/0021-drm-amdgpu-gfx8-update-PA_SC_RASTER_CONFIG-PKR_MAP-o.patch
deleted file mode 100644
index eff58cd1..00000000
--- a/common/recipes-kernel/linux/files/0021-drm-amdgpu-gfx8-update-PA_SC_RASTER_CONFIG-PKR_MAP-o.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f933ed7d6bfd0ba56541536b54648e8ed80f959f Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Tue, 8 Dec 2015 11:23:29 +0800
-Subject: [PATCH 0021/1110] drm/amdgpu/gfx8: update PA_SC_RASTER_CONFIG:PKR_MAP
- only
-
-Use default value as a base.
-
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-index 5a6bb34..16420b9 100644
---- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
-@@ -2630,7 +2630,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
- mutex_lock(&adev->grbm_idx_mutex);
- for (i = 0; i < se_num; i++) {
- gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
-- data = 0;
-+ data = RREG32(mmPA_SC_RASTER_CONFIG);
- for (j = 0; j < sh_per_se; j++) {
- switch (enabled_rbs & 3) {
- case 0:
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0022-drm-amdgpu-update-rev-id-register-for-VI.patch b/common/recipes-kernel/linux/files/0022-drm-amdgpu-update-rev-id-register-for-VI.patch
deleted file mode 100644
index 8056f349..00000000
--- a/common/recipes-kernel/linux/files/0022-drm-amdgpu-update-rev-id-register-for-VI.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 05158425917db24bd4310339d1433895135c5ae8 Mon Sep 17 00:00:00 2001
-From: Flora Cui <Flora.Cui@amd.com>
-Date: Fri, 20 Nov 2015 11:40:53 +0800
-Subject: [PATCH 0022/1110] drm/amdgpu: update rev id register for VI
-
-Change-Id: I2ae9bb4a929f7c0c8783e0be563ae04be77596e2
-Signed-off-by: Flora Cui <Flora.Cui@amd.com>
-Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/vi.c | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
-index 0cb6f31..2f1c118 100644
---- a/drivers/gpu/drm/amd/amdgpu/vi.c
-+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
-@@ -1387,15 +1387,12 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
-
- static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
- {
-- if (adev->asic_type == CHIP_TOPAZ)
-- return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
-- >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
-- else if (adev->flags & AMD_IS_APU)
-+ if (adev->flags & AMD_IS_APU)
- return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
- >> ATI_REV_ID_FUSE_MACRO__SHIFT;
- else
-- return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
-- >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
-+ return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
-+ >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
- }
-
- static const struct amdgpu_asic_funcs vi_asic_funcs =
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0023-drm-amdgpu-add-more-debugging-output-for-driver-fail.patch b/common/recipes-kernel/linux/files/0023-drm-amdgpu-add-more-debugging-output-for-driver-fail.patch
deleted file mode 100644
index 50c39836..00000000
--- a/common/recipes-kernel/linux/files/0023-drm-amdgpu-add-more-debugging-output-for-driver-fail.patch
+++ /dev/null
@@ -1,211 +0,0 @@
-From 0273b5fac28b3b13111b978c7c27c908ba9d28c2 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Mon, 7 Dec 2015 17:02:53 -0500
-Subject: [PATCH 0023/1110] drm/amdgpu: add more debugging output for driver
- failures
-
-Add more fine grained debugging output for init/fini/suspend/
-resume failures.
-
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +++++++++++++++++++++++-------
- 1 file changed, 57 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index c5206fd..991884a 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -1214,12 +1214,14 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
- } else {
- if (adev->ip_blocks[i].funcs->early_init) {
- r = adev->ip_blocks[i].funcs->early_init((void *)adev);
-- if (r == -ENOENT)
-+ if (r == -ENOENT) {
- adev->ip_block_status[i].valid = false;
-- else if (r)
-+ } else if (r) {
-+ DRM_ERROR("early_init %d failed %d\n", i, r);
- return r;
-- else
-+ } else {
- adev->ip_block_status[i].valid = true;
-+ }
- } else {
- adev->ip_block_status[i].valid = true;
- }
-@@ -1237,20 +1239,28 @@ static int amdgpu_init(struct amdgpu_device *adev)
- if (!adev->ip_block_status[i].valid)
- continue;
- r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("sw_init %d failed %d\n", i, r);
- return r;
-+ }
- adev->ip_block_status[i].sw = true;
- /* need to do gmc hw init early so we can allocate gpu mem */
- if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
- r = amdgpu_vram_scratch_init(adev);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
- return r;
-+ }
- r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("hw_init %d failed %d\n", i, r);
- return r;
-+ }
- r = amdgpu_wb_init(adev);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("amdgpu_wb_init failed %d\n", r);
- return r;
-+ }
- adev->ip_block_status[i].hw = true;
- }
- }
-@@ -1262,8 +1272,10 @@ static int amdgpu_init(struct amdgpu_device *adev)
- if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
- continue;
- r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("hw_init %d failed %d\n", i, r);
- return r;
-+ }
- adev->ip_block_status[i].hw = true;
- }
-
-@@ -1280,12 +1292,16 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
- /* enable clockgating to save power */
- r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- AMD_CG_STATE_GATE);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
- return r;
-+ }
- if (adev->ip_blocks[i].funcs->late_init) {
- r = adev->ip_blocks[i].funcs->late_init((void *)adev);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("late_init %d failed %d\n", i, r);
- return r;
-+ }
- }
- }
-
-@@ -1306,10 +1322,15 @@ static int amdgpu_fini(struct amdgpu_device *adev)
- /* ungate blocks before hw fini so that we can shutdown the blocks safely */
- r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- AMD_CG_STATE_UNGATE);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
- return r;
-+ }
- r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
- /* XXX handle errors */
-+ if (r) {
-+ DRM_DEBUG("hw_fini %d failed %d\n", i, r);
-+ }
- adev->ip_block_status[i].hw = false;
- }
-
-@@ -1318,6 +1339,9 @@ static int amdgpu_fini(struct amdgpu_device *adev)
- continue;
- r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
- /* XXX handle errors */
-+ if (r) {
-+ DRM_DEBUG("sw_fini %d failed %d\n", i, r);
-+ }
- adev->ip_block_status[i].sw = false;
- adev->ip_block_status[i].valid = false;
- }
-@@ -1335,9 +1359,15 @@ static int amdgpu_suspend(struct amdgpu_device *adev)
- /* ungate blocks so that suspend can properly shut them down */
- r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
- AMD_CG_STATE_UNGATE);
-+ if (r) {
-+ DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
-+ }
- /* XXX handle errors */
- r = adev->ip_blocks[i].funcs->suspend(adev);
- /* XXX handle errors */
-+ if (r) {
-+ DRM_ERROR("suspend %d failed %d\n", i, r);
-+ }
- }
-
- return 0;
-@@ -1351,8 +1381,10 @@ static int amdgpu_resume(struct amdgpu_device *adev)
- if (!adev->ip_block_status[i].valid)
- continue;
- r = adev->ip_blocks[i].funcs->resume(adev);
-- if (r)
-+ if (r) {
-+ DRM_ERROR("resume %d failed %d\n", i, r);
- return r;
-+ }
- }
-
- return 0;
-@@ -1484,8 +1516,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- return -EINVAL;
- }
- r = amdgpu_atombios_init(adev);
-- if (r)
-+ if (r) {
-+ dev_err(adev->dev, "amdgpu_atombios_init failed\n");
- return r;
-+ }
-
- /* Post card if necessary */
- if (!amdgpu_card_posted(adev)) {
-@@ -1499,21 +1533,26 @@ int amdgpu_device_init(struct amdgpu_device *adev,
-
- /* Initialize clocks */
- r = amdgpu_atombios_get_clock_info(adev);
-- if (r)
-+ if (r) {
-+ dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
- return r;
-+ }
- /* init i2c buses */
- amdgpu_atombios_i2c_init(adev);
-
- /* Fence driver */
- r = amdgpu_fence_driver_init(adev);
-- if (r)
-+ if (r) {
-+ dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
- return r;
-+ }
-
- /* init the mode config */
- drm_mode_config_init(adev->ddev);
-
- r = amdgpu_init(adev);
- if (r) {
-+ dev_err(adev->dev, "amdgpu_init failed\n");
- amdgpu_fini(adev);
- return r;
- }
-@@ -1570,8 +1609,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
- * explicit gating rather than handling it automatically.
- */
- r = amdgpu_late_init(adev);
-- if (r)
-+ if (r) {
-+ dev_err(adev->dev, "amdgpu_late_init failed\n");
- return r;
-+ }
-
- return 0;
- }
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0024-drm-amdgpu-add-entity-only-when-first-job-come.patch b/common/recipes-kernel/linux/files/0024-drm-amdgpu-add-entity-only-when-first-job-come.patch
deleted file mode 100644
index 659bbaf0..00000000
--- a/common/recipes-kernel/linux/files/0024-drm-amdgpu-add-entity-only-when-first-job-come.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 090a50215bda6e62ddd9514d6f1ab0ba972b87bd Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Fri, 11 Dec 2015 18:22:52 +0800
-Subject: [PATCH 0024/1110] drm/amdgpu: add entity only when first job come
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-umd somtimes will create a context for every ring,
-that means some entities wouldn't be used at all.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 13 ++++++++-----
- 1 file changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-index 5ace1a7..8b2becd 100644
---- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
-@@ -47,6 +47,8 @@ static void amd_sched_rq_init(struct amd_sched_rq *rq)
- static void amd_sched_rq_add_entity(struct amd_sched_rq *rq,
- struct amd_sched_entity *entity)
- {
-+ if (!list_empty(&entity->list))
-+ return;
- spin_lock(&rq->lock);
- list_add_tail(&entity->list, &rq->entities);
- spin_unlock(&rq->lock);
-@@ -55,6 +57,8 @@ static void amd_sched_rq_add_entity(struct amd_sched_rq *rq,
- static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq,
- struct amd_sched_entity *entity)
- {
-+ if (list_empty(&entity->list))
-+ return;
- spin_lock(&rq->lock);
- list_del_init(&entity->list);
- if (rq->current_entity == entity)
-@@ -138,9 +142,6 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
- atomic_set(&entity->fence_seq, 0);
- entity->fence_context = fence_context_alloc(1);
-
-- /* Add the entity to the run queue */
-- amd_sched_rq_add_entity(rq, entity);
--
- return 0;
- }
-
-@@ -302,9 +303,11 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
- spin_unlock(&entity->queue_lock);
-
- /* first job wakes up scheduler */
-- if (first)
-+ if (first) {
-+ /* Add the entity to the run queue */
-+ amd_sched_rq_add_entity(entity->rq, entity);
- amd_sched_wakeup(sched);
--
-+ }
- return added;
- }
-
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0025-drm-amdgpu-handle-error-case-for-ctx.patch b/common/recipes-kernel/linux/files/0025-drm-amdgpu-handle-error-case-for-ctx.patch
deleted file mode 100644
index 55da8d0f..00000000
--- a/common/recipes-kernel/linux/files/0025-drm-amdgpu-handle-error-case-for-ctx.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From b94cbc431148d3dc4b5bf20303412ed3b6e60f53 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 15:50:02 +0800
-Subject: [PATCH 0025/1110] drm/amdgpu: handle error case for ctx
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Properly handle ctx init failure.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index c1f2308..15e3416 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -56,7 +56,6 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- for (j = 0; j < i; j++)
- amd_sched_entity_fini(&adev->rings[j]->sched,
- &ctx->rings[j].entity);
-- kfree(ctx);
- return r;
- }
- }
-@@ -103,8 +102,12 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
- }
- *id = (uint32_t)r;
- r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_NORMAL, ctx);
-+ if (r) {
-+ idr_remove(&mgr->ctx_handles, *id);
-+ *id = 0;
-+ kfree(ctx);
-+ }
- mutex_unlock(&mgr->lock);
--
- return r;
- }
-
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0026-drm-amdgpu-unify-AMDGPU_CTX_MAX_CS_PENDING-and-amdgp.patch b/common/recipes-kernel/linux/files/0026-drm-amdgpu-unify-AMDGPU_CTX_MAX_CS_PENDING-and-amdgp.patch
deleted file mode 100644
index da130896..00000000
--- a/common/recipes-kernel/linux/files/0026-drm-amdgpu-unify-AMDGPU_CTX_MAX_CS_PENDING-and-amdgp.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 12db7286ff75575c9cac9afc5309c26e8ae21527 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 15:45:11 +0800
-Subject: [PATCH 0026/1110] drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and
- amdgpu_sched_jobs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 ++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 25 ++++++++++++++++++-------
- 2 files changed, 20 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index e85ed1b..f6563fa 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -1022,11 +1022,9 @@ int amdgpu_vm_free_job(struct amdgpu_job *job);
- * context related structures
- */
-
--#define AMDGPU_CTX_MAX_CS_PENDING 16
--
- struct amdgpu_ctx_ring {
- uint64_t sequence;
-- struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
-+ struct fence **fences;
- struct amd_sched_entity entity;
- };
-
-@@ -1035,6 +1033,7 @@ struct amdgpu_ctx {
- struct amdgpu_device *adev;
- unsigned reset_counter;
- spinlock_t ring_lock;
-+ struct fence **fences;
- struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
- };
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index 15e3416..ee121ec 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -35,15 +35,24 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- ctx->adev = adev;
- kref_init(&ctx->refcount);
- spin_lock_init(&ctx->ring_lock);
-- for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
-- ctx->rings[i].sequence = 1;
-+ ctx->fences = kzalloc(sizeof(struct fence *) * amdgpu_sched_jobs *
-+ AMDGPU_MAX_RINGS, GFP_KERNEL);
-+ if (!ctx->fences)
-+ return -ENOMEM;
-
-+ for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-+ ctx->rings[i].sequence = 1;
-+ ctx->rings[i].fences = (void *)ctx->fences + sizeof(struct fence *) *
-+ amdgpu_sched_jobs * i;
-+ }
- if (amdgpu_enable_scheduler) {
- /* create context entity for each ring */
- for (i = 0; i < adev->num_rings; i++) {
- struct amd_sched_rq *rq;
-- if (pri >= AMD_SCHED_MAX_PRIORITY)
-+ if (pri >= AMD_SCHED_MAX_PRIORITY) {
-+ kfree(ctx->fences);
- return -EINVAL;
-+ }
- rq = &adev->rings[i]->sched.sched_rq[pri];
- r = amd_sched_entity_init(&adev->rings[i]->sched,
- &ctx->rings[i].entity,
-@@ -56,6 +65,7 @@ int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
- for (j = 0; j < i; j++)
- amd_sched_entity_fini(&adev->rings[j]->sched,
- &ctx->rings[j].entity);
-+ kfree(ctx->fences);
- return r;
- }
- }
-@@ -71,8 +81,9 @@ void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
- return;
-
- for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
-- for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
-+ for (j = 0; j < amdgpu_sched_jobs; ++j)
- fence_put(ctx->rings[i].fences[j]);
-+ kfree(ctx->fences);
-
- if (amdgpu_enable_scheduler) {
- for (i = 0; i < adev->num_rings; i++)
-@@ -241,7 +252,7 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
- unsigned idx = 0;
- struct fence *other = NULL;
-
-- idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
-+ idx = seq % amdgpu_sched_jobs;
- other = cring->fences[idx];
- if (other) {
- signed long r;
-@@ -276,12 +287,12 @@ struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
- }
-
-
-- if (seq + AMDGPU_CTX_MAX_CS_PENDING < cring->sequence) {
-+ if (seq + amdgpu_sched_jobs < cring->sequence) {
- spin_unlock(&ctx->ring_lock);
- return NULL;
- }
-
-- fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
-+ fence = fence_get(cring->fences[seq % amdgpu_sched_jobs]);
- spin_unlock(&ctx->ring_lock);
-
- return fence;
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0027-drm-amdgpu-change-default-sched-jobs-to-32.patch b/common/recipes-kernel/linux/files/0027-drm-amdgpu-change-default-sched-jobs-to-32.patch
deleted file mode 100644
index c1bedd3f..00000000
--- a/common/recipes-kernel/linux/files/0027-drm-amdgpu-change-default-sched-jobs-to-32.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From df7c1b76f73d1969ff8b8001e351b9b2d1454595 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 15:46:50 +0800
-Subject: [PATCH 0027/1110] drm/amdgpu: change default sched jobs to 32
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Change the default scheduler queue size from 16 to 32.
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-index 8d6668c..659300c 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -79,7 +79,7 @@ int amdgpu_vm_fault_stop = 0;
- int amdgpu_vm_debug = 0;
- int amdgpu_exp_hw_support = 0;
- int amdgpu_enable_scheduler = 1;
--int amdgpu_sched_jobs = 16;
-+int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_enable_semaphores = 0;
-
-@@ -155,7 +155,7 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
- MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)");
- module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);
-
--MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)");
-+MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
- module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
-
- MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0028-drm-amdgpu-limit-visible-vram-if-it-s-smaller-than-t.patch b/common/recipes-kernel/linux/files/0028-drm-amdgpu-limit-visible-vram-if-it-s-smaller-than-t.patch
deleted file mode 100644
index 3f09b488..00000000
--- a/common/recipes-kernel/linux/files/0028-drm-amdgpu-limit-visible-vram-if-it-s-smaller-than-t.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 59751bbb53fb875b45a1f6a389e70a62923a58e3 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 9 Dec 2015 15:36:40 -0500
-Subject: [PATCH 0028/1110] drm/amdgpu: limit visible vram if it's smaller than
- the BAR
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In some cases the amount of vram may be less than the BAR size,
-if so, limit visible vram to the amount of actual vram, not the
-BAR size.
-
-Reviewed-by: Christian König <christian.koenig@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++++
- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++++
- 2 files changed, 8 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-index ea87033..538af44 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
-@@ -407,6 +407,10 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
- adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- adev->mc.visible_vram_size = adev->mc.aper_size;
-
-+ /* In case the PCI BAR is larger than the actual amount of vram */
-+ if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
-+ adev->mc.visible_vram_size = adev->mc.real_vram_size;
-+
- /* unless the user had overridden it, set the gart
- * size equal to the 1024 or vram, whichever is larger.
- */
-diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-index 0842308..3d4a923 100644
---- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
-@@ -448,6 +448,10 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
- adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- adev->mc.visible_vram_size = adev->mc.aper_size;
-
-+ /* In case the PCI BAR is larger than the actual amount of vram */
-+ if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
-+ adev->mc.visible_vram_size = adev->mc.real_vram_size;
-+
- /* unless the user had overridden it, set the gart
- * size equal to the 1024 or vram, whichever is larger.
- */
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0029-drm-amdgpu-restrict-the-sched-jobs-number-to-power-o.patch b/common/recipes-kernel/linux/files/0029-drm-amdgpu-restrict-the-sched-jobs-number-to-power-o.patch
deleted file mode 100644
index 889b82a1..00000000
--- a/common/recipes-kernel/linux/files/0029-drm-amdgpu-restrict-the-sched-jobs-number-to-power-o.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 0cb97db6c8809cf2127421383a668cbf912660e3 Mon Sep 17 00:00:00 2001
-From: Chunming Zhou <David1.Zhou@amd.com>
-Date: Thu, 10 Dec 2015 17:34:33 +0800
-Subject: [PATCH 0029/1110] drm/amdgpu: restrict the sched jobs number to power
- of two
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
-Reviewed-by: Christian König <christian.koenig@amd.com>
-CC: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +++++++++
- 2 files changed, 11 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-index ee121ec..17d1fb1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
-@@ -252,7 +252,7 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
- unsigned idx = 0;
- struct fence *other = NULL;
-
-- idx = seq % amdgpu_sched_jobs;
-+ idx = seq & (amdgpu_sched_jobs - 1);
- other = cring->fences[idx];
- if (other) {
- signed long r;
-@@ -292,7 +292,7 @@ struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
- return NULL;
- }
-
-- fence = fence_get(cring->fences[seq % amdgpu_sched_jobs]);
-+ fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
- spin_unlock(&ctx->ring_lock);
-
- return fence;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-index 991884a..a138f69 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -949,6 +949,15 @@ static bool amdgpu_check_pot_argument(int arg)
- */
- static void amdgpu_check_arguments(struct amdgpu_device *adev)
- {
-+ if (amdgpu_sched_jobs < 4) {
-+ dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
-+ amdgpu_sched_jobs);
-+ amdgpu_sched_jobs = 4;
-+ } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
-+ dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
-+ amdgpu_sched_jobs);
-+ amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
-+ }
- /* vramlimit must be a power of two */
- if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
- dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0030-drm-amdgpu-put-VM-page-tables-directly-into-duplicat.patch b/common/recipes-kernel/linux/files/0030-drm-amdgpu-put-VM-page-tables-directly-into-duplicat.patch
deleted file mode 100644
index 39072112..00000000
--- a/common/recipes-kernel/linux/files/0030-drm-amdgpu-put-VM-page-tables-directly-into-duplicat.patch
+++ /dev/null
@@ -1,119 +0,0 @@
-From 78fe04e337d615028fcbee472d8a3dc30a4177ea Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Dec 2015 14:39:05 +0100
-Subject: [PATCH 0030/1110] drm/amdgpu: put VM page tables directly into
- duplicates list
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-They share the reservation object with the page directory anyway.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 ++++++++-----
- 4 files changed, 15 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index f6563fa..1447a5e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -982,6 +982,10 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
- struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct list_head *head);
-+struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
-+ struct amdgpu_vm *vm,
-+ struct list_head *validated,
-+ struct list_head *duplicates);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- struct amdgpu_sync *sync);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 25a3e24..1d52144 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -406,8 +406,9 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- amdgpu_cs_buckets_get_list(&buckets, &p->validated);
- }
-
-+ INIT_LIST_HEAD(&duplicates);
- p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
-- &p->validated);
-+ &p->validated, &duplicates);
-
- if (p->uf.bo)
- list_add(&p->uf_entry.tv.head, &p->validated);
-@@ -415,7 +416,6 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- if (need_mmap_lock)
- down_read(&current->mm->mmap_sem);
-
-- INIT_LIST_HEAD(&duplicates);
- r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
- if (unlikely(r != 0))
- goto error_reserve;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index 9c253c5..df0444f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -461,7 +461,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- tv.shared = true;
- list_add(&tv.head, &list);
-
-- vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
-+ vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list, &duplicates);
- if (!vm_bos)
- return;
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 8c5ec15..3c3404f 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -78,14 +78,17 @@ static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
- * amdgpu_vm_get_bos - add the vm BOs to a validation list
- *
- * @vm: vm providing the BOs
-- * @head: head of validation list
-+ * @validated: head of validation list
-+ * @duplicates: head of duplicates list
-+
- *
- * Add the page directory to the list of BOs to
- * validate for command submission (cayman+).
- */
- struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
-- struct amdgpu_vm *vm,
-- struct list_head *head)
-+ struct amdgpu_vm *vm,
-+ struct list_head *validated,
-+ struct list_head *duplicates)
- {
- struct amdgpu_bo_list_entry *list;
- unsigned i, idx;
-@@ -103,7 +106,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- list[0].priority = 0;
- list[0].tv.bo = &vm->page_directory->tbo;
- list[0].tv.shared = true;
-- list_add(&list[0].tv.head, head);
-+ list_add(&list[0].tv.head, validated);
-
- for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
- if (!vm->page_tables[i].bo)
-@@ -115,7 +118,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- list[idx].priority = 0;
- list[idx].tv.bo = &list[idx].robj->tbo;
- list[idx].tv.shared = true;
-- list_add(&list[idx++].tv.head, head);
-+ list_add(&list[idx++].tv.head, duplicates);
- }
-
- return list;
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0031-drm-amdgpu-split-VM-PD-and-PT-handling-during-CS.patch b/common/recipes-kernel/linux/files/0031-drm-amdgpu-split-VM-PD-and-PT-handling-during-CS.patch
deleted file mode 100644
index 4f646fee..00000000
--- a/common/recipes-kernel/linux/files/0031-drm-amdgpu-split-VM-PD-and-PT-handling-during-CS.patch
+++ /dev/null
@@ -1,190 +0,0 @@
-From e80b9ea2005233764ff7bac3ed1ef49732bdaa05 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Dec 2015 15:16:32 +0100
-Subject: [PATCH 0031/1110] drm/amdgpu: split VM PD and PT handling during CS
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This way we avoid the extra allocation for the page directory entry.
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +++++
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 ++++++--
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 16 +++++++++-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 39 ++++++++++++++++++++++++---------
- 4 files changed, 52 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 1447a5e..638b089 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -986,6 +986,11 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
- struct list_head *validated,
- struct list_head *duplicates);
-+void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-+ struct list_head *validated,
-+ struct amdgpu_bo_list_entry *entry);
-+struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
-+ struct list_head *duplicates);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- struct amdgpu_sync *sync);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
-@@ -1255,6 +1260,7 @@ struct amdgpu_cs_parser {
- unsigned nchunks;
- struct amdgpu_cs_chunk *chunks;
- /* relocations */
-+ struct amdgpu_bo_list_entry vm_pd;
- struct amdgpu_bo_list_entry *vm_bos;
- struct list_head validated;
- struct fence *fence;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 1d52144..1ff138e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -407,8 +407,7 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- }
-
- INIT_LIST_HEAD(&duplicates);
-- p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
-- &p->validated, &duplicates);
-+ amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
-
- if (p->uf.bo)
- list_add(&p->uf_entry.tv.head, &p->validated);
-@@ -420,6 +419,12 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- if (unlikely(r != 0))
- goto error_reserve;
-
-+ p->vm_bos = amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
-+ if (!p->vm_bos) {
-+ r = -ENOMEM;
-+ goto error_validate;
-+ }
-+
- r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
- if (r)
- goto error_validate;
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index df0444f..b1d44ce 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -449,6 +449,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- {
- struct ttm_validate_buffer tv, *entry;
- struct amdgpu_bo_list_entry *vm_bos;
-+ struct amdgpu_bo_list_entry vm_pd;
- struct ww_acquire_ctx ticket;
- struct list_head list, duplicates;
- unsigned domain;
-@@ -461,14 +462,18 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- tv.shared = true;
- list_add(&tv.head, &list);
-
-- vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list, &duplicates);
-- if (!vm_bos)
-- return;
-+ amdgpu_vm_get_pd_bo(bo_va->vm, &list, &vm_pd);
-
- /* Provide duplicates to avoid -EALREADY */
- r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
- if (r)
-- goto error_free;
-+ goto error_print;
-+
-+ vm_bos = amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
-+ if (!vm_bos) {
-+ r = -ENOMEM;
-+ goto error_unreserve;
-+ }
-
- list_for_each_entry(entry, &list, head) {
- domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
-@@ -498,10 +503,9 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
-
- error_unreserve:
- ttm_eu_backoff_reservation(&ticket, &list);
--
--error_free:
- drm_free_large(vm_bos);
-
-+error_print:
- if (r && r != -ERESTARTSYS)
- DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
- }
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 3c3404f..396ab85 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -75,27 +75,46 @@ static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
- }
-
- /**
-- * amdgpu_vm_get_bos - add the vm BOs to a validation list
-- *
-+ * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
- * @vm: vm providing the BOs
- * @validated: head of validation list
-+ * @entry: entry to add
-+ *
-+ * Add the page directory to the list of BOs to
-+ * validate for command submission.
-+ */
-+void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
-+ struct list_head *validated,
-+ struct amdgpu_bo_list_entry *entry)
-+{
-+ entry->robj = vm->page_directory;
-+ entry->prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
-+ entry->allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
-+ entry->priority = 0;
-+ entry->tv.bo = &vm->page_directory->tbo;
-+ entry->tv.shared = true;
-+ list_add(&entry->tv.head, validated);
-+}
-+
-+/**
-++ * amdgpu_vm_get_bos - add the vm BOs to a validation list
-++ *
-++ * @vm: vm providing the BOs
- * @duplicates: head of duplicates list
-
-- *
- * Add the page directory to the list of BOs to
- * validate for command submission (cayman+).
- */
--struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
-- struct amdgpu_vm *vm,
-- struct list_head *validated,
-- struct list_head *duplicates)
-+struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
-+ struct list_head *duplicates)
-+
- {
- struct amdgpu_bo_list_entry *list;
- unsigned i, idx;
-
-- list = drm_malloc_ab(vm->max_pde_used + 2,
-+ list = drm_malloc_ab(vm->max_pde_used + 1,
- sizeof(struct amdgpu_bo_list_entry));
-- if (!list) {
-+ if (!list)
- return NULL;
- }
-
-@@ -108,7 +127,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- list[0].tv.shared = true;
- list_add(&list[0].tv.head, validated);
-
-- for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
-+ for (i = 0, idx = 0; i <= vm->max_pde_used; i++) {
- if (!vm->page_tables[i].bo)
- continue;
-
---
-2.7.4
-
diff --git a/common/recipes-kernel/linux/files/0032-drm-amdgpu-keep-the-PTs-validation-list-in-the-VM-v2.patch b/common/recipes-kernel/linux/files/0032-drm-amdgpu-keep-the-PTs-validation-list-in-the-VM-v2.patch
deleted file mode 100644
index e7f774f3..00000000
--- a/common/recipes-kernel/linux/files/0032-drm-amdgpu-keep-the-PTs-validation-list-in-the-VM-v2.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From 7e593951bf930179ca0d28269536c58361f5fa34 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 11 Dec 2015 21:01:23 +0100
-Subject: [PATCH 0032/1110] drm/amdgpu: keep the PTs validation list in the VM
- v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This avoids allocating it on the fly.
-
-v2: fix grammar in comment
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
-Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
-Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
----
- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 9 +++---
- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +---
- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 9 +-----
- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 57 +++++++++++++++------------------
- 4 files changed, 31 insertions(+), 51 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-index 638b089..41bee9e 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
-@@ -916,8 +916,9 @@ struct amdgpu_ring {
- #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
-
- struct amdgpu_vm_pt {
-- struct amdgpu_bo *bo;
-- uint64_t addr;
-+ struct amdgpu_bo_list_entry entry;
-+ uint64_t addr;
-+
- };
-
- struct amdgpu_vm_id {
-@@ -989,8 +990,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
- void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
- struct list_head *validated,
- struct amdgpu_bo_list_entry *entry);
--struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
-- struct list_head *duplicates);
-+void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
- int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
- struct amdgpu_sync *sync);
- void amdgpu_vm_flush(struct amdgpu_ring *ring,
-@@ -1261,7 +1261,6 @@ struct amdgpu_cs_parser {
- struct amdgpu_cs_chunk *chunks;
- /* relocations */
- struct amdgpu_bo_list_entry vm_pd;
-- struct amdgpu_bo_list_entry *vm_bos;
- struct list_head validated;
- struct fence *fence;
-
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-index 1ff138e..850f2ab 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
-@@ -419,11 +419,7 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
- if (unlikely(r != 0))
- goto error_reserve;
-
-- p->vm_bos = amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
-- if (!p->vm_bos) {
-- r = -ENOMEM;
-- goto error_validate;
-- }
-+ amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates);
-
- r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated);
- if (r)
-@@ -506,7 +502,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo
- if (parser->bo_list)
- amdgpu_bo_list_put(parser->bo_list);
-
-- drm_free_large(parser->vm_bos);
- for (i = 0; i < parser->nchunks; i++)
- drm_free_large(parser->chunks[i].kdata);
- kfree(parser->chunks);
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-index b1d44ce..8eb4b68 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-@@ -448,7 +448,6 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- struct amdgpu_bo_va *bo_va, uint32_t operation)
- {
- struct ttm_validate_buffer tv, *entry;
-- struct amdgpu_bo_list_entry *vm_bos;
- struct amdgpu_bo_list_entry vm_pd;
- struct ww_acquire_ctx ticket;
- struct list_head list, duplicates;
-@@ -469,12 +468,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
- if (r)
- goto error_print;
-
-- vm_bos = amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
-- if (!vm_bos) {
-- r = -ENOMEM;
-- goto error_unreserve;
-- }
--
-+ amdgpu_vm_get_pt_bos(bo_va->vm, &duplicates);
- list_for_each_entry(entry, &list, head) {
- domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
- /* if anything is swapped out don't swap it in here,
-@@ -503,7 +497,6 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
-
- error_unreserve:
- ttm_eu_backoff_reservation(&ticket, &list);
-- drm_free_large(vm_bos);
-
- error_print:
- if (r && r != -ERESTARTSYS)
-diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-index 396ab85..e83d4f1 100644
---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
-@@ -97,26 +97,18 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
- }
-
- /**
--+ * amdgpu_vm_get_bos - add the vm BOs to a validation list
--+ *
--+ * @vm: vm providing the BOs
-+ * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
-+ *
-+ * @vm: vm providing the BOs
- * @duplicates: head of duplicates list
-
-- * Add the page directory to the list of BOs to
-- * validate for command submission (cayman+).
-- */
--struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
-- struct list_head *duplicates)
-+ * Add the page directory to the BO duplicates list
-+ * for command submission.
-
-+ */
-+void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
- {
-- struct amdgpu_bo_list_entry *list;
-- unsigned i, idx;
--
-- list = drm_malloc_ab(vm->max_pde_used + 1,
-- sizeof(struct amdgpu_bo_list_entry));
-- if (!list)
-- return NULL;
-- }
-+ unsigned i;
-
- /* add the vm page table to the list */
- list[0].robj = vm->page_directory;
-@@ -127,20 +119,14 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm,
- list[0].tv.shared = true;
- list_add(&list[0].tv.head, validated);
-
-- for (i = 0, idx = 0; i <= vm->max_pde_used; i++) {
-- if (!vm->page_tables[i].bo)
-+ for (i = 0; i <= vm->max_pde_used; ++i) {
-+ struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
-+
-+ if (!entry->robj)
- continue;
-
-- list[idx].robj = vm->page_tables[i].bo;
-- list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
-- list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
-- list[idx].priority = 0;
-- list[idx].tv.bo = &list[idx].robj->tbo;
-- list[idx].tv.shared = true;
-- list_add(&list[idx++].tv.head, duplicates);
-+ list_add(&entry->tv.head, duplicates);
- }
--
-- return list;
- }
-
- /**
-@@ -483,7 +469,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-
- /* walk over the address space and update the page directory */
- for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
-- struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
-+ struct amdgp