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authorDrew Moseley <drew@moseleynet.net>2016-09-09 15:28:25 -0400
committerGitHub <noreply@github.com>2016-09-09 15:28:25 -0400
commit373d83e1095f789a52151a8bcf5d2678b376cb72 (patch)
treec7072d338ee5ea3390958be1756d8ff6366507c7
parentf14024fff6b2706f40430c09b243cbb527aab795 (diff)
parent0be4998dad775ff6e90f475638f3b583e3eca16e (diff)
downloadmeta-amd-jethro.tar.gz
meta-amd-jethro.tar.bz2
meta-amd-jethro.zip
Merge pull request #344 from drewmoseley/jethrojethro
Merge Cedar to Jethro
-rw-r--r--common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb4
-rw-r--r--common/recipes-kernel/linux/files/1574-add-support-of-SW-clock-gating-for-UVD6.patch482
-rw-r--r--common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc1
3 files changed, 485 insertions, 2 deletions
diff --git a/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb b/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb
index b8bde23e..53e59856 100644
--- a/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb
+++ b/common/recipes-graphics/xorg-driver/xf86-video-amd_git.bb
@@ -17,12 +17,12 @@ PACKAGECONFIG[udev] = "--enable-udev,--disable-udev,udev"
PACKAGECONFIG[glamor] = "--enable-glamor,--disable-glamor"
SRC_URI_radeon = "git://anongit.freedesktop.org/git/xorg/driver/xf86-video-ati"
-SRCREV_radeon = "xf86-video-ati-7.6.1"
+SRCREV_radeon = "99cb8c3faf1a4ce368b7500f17a2a7868c15e8e8"
PV_radeon = "radeon-7.6.1"
PACKAGECONFIG_append_radeon = " udev glamor"
SRC_URI_amdgpu = "git://anongit.freedesktop.org/xorg/driver/xf86-video-amdgpu;branch=1.0"
-SRCREV_amdgpu = "xf86-video-amdgpu-1.0.1"
+SRCREV_amdgpu = "d68b3073a9627a81b047e9bdd4b5569359df898d"
PV_amdgpu = "amdgpu-1.0.1"
PACKAGECONFIG_append_amdgpu = " udev glamor"
diff --git a/common/recipes-kernel/linux/files/1574-add-support-of-SW-clock-gating-for-UVD6.patch b/common/recipes-kernel/linux/files/1574-add-support-of-SW-clock-gating-for-UVD6.patch
new file mode 100644
index 00000000..732096cb
--- /dev/null
+++ b/common/recipes-kernel/linux/files/1574-add-support-of-SW-clock-gating-for-UVD6.patch
@@ -0,0 +1,482 @@
+From 9c9a07080af6d3418ab0b1c0ab0f47ff8f69833d Mon Sep 17 00:00:00 2001
+From: Sanjay R Mehta <sanju.mehta@amd.com>
+Date: Wed, 24 Aug 2016 16:52:14 +0530
+Subject: [PATCH] add support of SW clock gating for UVD6
+
+Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 371 +++++++++-------------------------
+ 1 file changed, 96 insertions(+), 275 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+index 4befb62..46dbdcf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+@@ -31,11 +31,15 @@
+ #include "uvd/uvd_6_0_sh_mask.h"
+ #include "oss/oss_2_0_d.h"
+ #include "oss/oss_2_0_sh_mask.h"
++#include "smu/smu_7_1_3_d.h"
++#include "smu/smu_7_1_3_sh_mask.h"
++#include "vi.h"
+
+ static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
+ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
+ static int uvd_v6_0_start(struct amdgpu_device *adev);
+ static void uvd_v6_0_stop(struct amdgpu_device *adev);
++static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
+
+ /**
+ * uvd_v6_0_ring_get_rptr - get read pointer
+@@ -110,7 +114,7 @@ static int uvd_v6_0_sw_init(void *handle)
+
+ ring = &adev->uvd.ring;
+ sprintf(ring->name, "uvd");
+- r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,
++ r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
+ &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
+
+ return r;
+@@ -214,15 +218,16 @@ static int uvd_v6_0_suspend(void *handle)
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
++ r = uvd_v6_0_hw_fini(adev);
++ if (r)
++ return r;
++
+ /* Skip this for APU for now */
+ if (!(adev->flags & AMD_IS_APU)) {
+ r = amdgpu_uvd_suspend(adev);
+ if (r)
+ return r;
+ }
+- r = uvd_v6_0_hw_fini(adev);
+- if (r)
+- return r;
+
+ return r;
+ }
+@@ -286,6 +291,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
+ WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
+ }
+
++#if 0
+ static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
+ bool enable)
+ {
+@@ -362,157 +368,7 @@ static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
+ WREG32(mmUVD_CGC_GATE, data);
+ WREG32(mmUVD_SUVD_CGC_GATE, data1);
+ }
+-
+-static void tonga_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
+- bool enable)
+-{
+- u32 data, data1;
+-
+- data = RREG32(mmUVD_CGC_GATE);
+- data1 = RREG32(mmUVD_SUVD_CGC_GATE);
+- if (enable) {
+- data |= UVD_CGC_GATE__SYS_MASK |
+- UVD_CGC_GATE__UDEC_MASK |
+- UVD_CGC_GATE__MPEG2_MASK |
+- UVD_CGC_GATE__RBC_MASK |
+- UVD_CGC_GATE__LMI_MC_MASK |
+- UVD_CGC_GATE__IDCT_MASK |
+- UVD_CGC_GATE__MPRD_MASK |
+- UVD_CGC_GATE__MPC_MASK |
+- UVD_CGC_GATE__LBSI_MASK |
+- UVD_CGC_GATE__LRBBM_MASK |
+- UVD_CGC_GATE__UDEC_RE_MASK |
+- UVD_CGC_GATE__UDEC_CM_MASK |
+- UVD_CGC_GATE__UDEC_IT_MASK |
+- UVD_CGC_GATE__UDEC_DB_MASK |
+- UVD_CGC_GATE__UDEC_MP_MASK |
+- UVD_CGC_GATE__WCB_MASK |
+- UVD_CGC_GATE__VCPU_MASK |
+- UVD_CGC_GATE__SCPU_MASK;
+- data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
+- UVD_SUVD_CGC_GATE__SIT_MASK |
+- UVD_SUVD_CGC_GATE__SMP_MASK |
+- UVD_SUVD_CGC_GATE__SCM_MASK |
+- UVD_SUVD_CGC_GATE__SDB_MASK;
+- } else {
+- data &= ~(UVD_CGC_GATE__SYS_MASK |
+- UVD_CGC_GATE__UDEC_MASK |
+- UVD_CGC_GATE__MPEG2_MASK |
+- UVD_CGC_GATE__RBC_MASK |
+- UVD_CGC_GATE__LMI_MC_MASK |
+- UVD_CGC_GATE__LMI_UMC_MASK |
+- UVD_CGC_GATE__IDCT_MASK |
+- UVD_CGC_GATE__MPRD_MASK |
+- UVD_CGC_GATE__MPC_MASK |
+- UVD_CGC_GATE__LBSI_MASK |
+- UVD_CGC_GATE__LRBBM_MASK |
+- UVD_CGC_GATE__UDEC_RE_MASK |
+- UVD_CGC_GATE__UDEC_CM_MASK |
+- UVD_CGC_GATE__UDEC_IT_MASK |
+- UVD_CGC_GATE__UDEC_DB_MASK |
+- UVD_CGC_GATE__UDEC_MP_MASK |
+- UVD_CGC_GATE__WCB_MASK |
+- UVD_CGC_GATE__VCPU_MASK |
+- UVD_CGC_GATE__SCPU_MASK);
+- data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
+- UVD_SUVD_CGC_GATE__SIT_MASK |
+- UVD_SUVD_CGC_GATE__SMP_MASK |
+- UVD_SUVD_CGC_GATE__SCM_MASK |
+- UVD_SUVD_CGC_GATE__SDB_MASK);
+- }
+- WREG32(mmUVD_CGC_GATE, data);
+- WREG32(mmUVD_SUVD_CGC_GATE, data1);
+-}
+-
+-static void uvd_v6_0_set_uvd_dynamic_clock_mode(struct amdgpu_device *adev,
+- bool swmode)
+-{
+- u32 data, data1 = 0, data2;
+-
+- /* Always un-gate UVD REGS bit */
+- data = RREG32(mmUVD_CGC_GATE);
+- data &= ~(UVD_CGC_GATE__REGS_MASK);
+- WREG32(mmUVD_CGC_GATE, data);
+-
+- data = RREG32(mmUVD_CGC_CTRL);
+- data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
+- UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
+- data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
+- 1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER) |
+- 4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY);
+-
+- data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
+- if (swmode) {
+- data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
+- UVD_CGC_CTRL__SYS_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_MODE_MASK |
+- UVD_CGC_CTRL__MPEG2_MODE_MASK |
+- UVD_CGC_CTRL__REGS_MODE_MASK |
+- UVD_CGC_CTRL__RBC_MODE_MASK |
+- UVD_CGC_CTRL__LMI_MC_MODE_MASK |
+- UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
+- UVD_CGC_CTRL__IDCT_MODE_MASK |
+- UVD_CGC_CTRL__MPRD_MODE_MASK |
+- UVD_CGC_CTRL__MPC_MODE_MASK |
+- UVD_CGC_CTRL__LBSI_MODE_MASK |
+- UVD_CGC_CTRL__LRBBM_MODE_MASK |
+- UVD_CGC_CTRL__WCB_MODE_MASK |
+- UVD_CGC_CTRL__VCPU_MODE_MASK |
+- UVD_CGC_CTRL__JPEG_MODE_MASK |
+- UVD_CGC_CTRL__SCPU_MODE_MASK);
+- data1 |= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
+- UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK;
+- data1 &= ~UVD_CGC_CTRL2__GATER_DIV_ID_MASK;
+- data1 |= 7 << REG_FIELD_SHIFT(UVD_CGC_CTRL2, GATER_DIV_ID);
+- data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
+- } else {
+- data |= UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
+- UVD_CGC_CTRL__SYS_MODE_MASK |
+- UVD_CGC_CTRL__UDEC_MODE_MASK |
+- UVD_CGC_CTRL__MPEG2_MODE_MASK |
+- UVD_CGC_CTRL__REGS_MODE_MASK |
+- UVD_CGC_CTRL__RBC_MODE_MASK |
+- UVD_CGC_CTRL__LMI_MC_MODE_MASK |
+- UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
+- UVD_CGC_CTRL__IDCT_MODE_MASK |
+- UVD_CGC_CTRL__MPRD_MODE_MASK |
+- UVD_CGC_CTRL__MPC_MODE_MASK |
+- UVD_CGC_CTRL__LBSI_MODE_MASK |
+- UVD_CGC_CTRL__LRBBM_MODE_MASK |
+- UVD_CGC_CTRL__WCB_MODE_MASK |
+- UVD_CGC_CTRL__VCPU_MODE_MASK |
+- UVD_CGC_CTRL__SCPU_MODE_MASK;
+- data2 |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
+- UVD_SUVD_CGC_CTRL__SDB_MODE_MASK;
+- }
+- WREG32(mmUVD_CGC_CTRL, data);
+- WREG32(mmUVD_SUVD_CGC_CTRL, data2);
+-
+- data = RREG32_UVD_CTX(ixUVD_CGC_CTRL2);
+- data &= ~(REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
+- REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
+- REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
+- data1 &= (REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
+- REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
+- REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
+- data |= data1;
+- WREG32_UVD_CTX(ixUVD_CGC_CTRL2, data);
+-}
++#endif
+
+ /**
+ * uvd_v6_0_start - start UVD block
+@@ -540,11 +396,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
+
+ /* Set dynamic clock gating in S/W control mode */
+ if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
+- if (adev->flags & AMD_IS_APU)
+- cz_set_uvd_clock_gating_branches(adev, false);
+- else
+- tonga_set_uvd_clock_gating_branches(adev, false);
+- uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
++ uvd_v6_0_set_sw_clock_gating(adev);
+ } else {
+ /* disable clock gating */
+ uint32_t data = RREG32(mmUVD_CGC_CTRL);
+@@ -857,112 +709,6 @@ static int uvd_v6_0_soft_reset(void *handle)
+ return uvd_v6_0_start(adev);
+ }
+
+-static void uvd_v6_0_print_status(void *handle)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+- dev_info(adev->dev, "UVD 6.0 registers\n");
+- dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
+- RREG32(mmUVD_SEMA_ADDR_LOW));
+- dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
+- RREG32(mmUVD_SEMA_ADDR_HIGH));
+- dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
+- RREG32(mmUVD_SEMA_CMD));
+- dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
+- RREG32(mmUVD_GPCOM_VCPU_CMD));
+- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
+- RREG32(mmUVD_GPCOM_VCPU_DATA0));
+- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
+- RREG32(mmUVD_GPCOM_VCPU_DATA1));
+- dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
+- RREG32(mmUVD_ENGINE_CNTL));
+- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
+- RREG32(mmUVD_UDEC_ADDR_CONFIG));
+- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
+- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
+- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
+- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
+- dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
+- RREG32(mmUVD_SEMA_CNTL));
+- dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
+- RREG32(mmUVD_LMI_EXT40_ADDR));
+- dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
+- RREG32(mmUVD_CTX_INDEX));
+- dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
+- RREG32(mmUVD_CTX_DATA));
+- dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
+- RREG32(mmUVD_CGC_GATE));
+- dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
+- RREG32(mmUVD_CGC_CTRL));
+- dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
+- RREG32(mmUVD_LMI_CTRL2));
+- dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
+- RREG32(mmUVD_MASTINT_EN));
+- dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
+- RREG32(mmUVD_LMI_ADDR_EXT));
+- dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
+- RREG32(mmUVD_LMI_CTRL));
+- dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
+- RREG32(mmUVD_LMI_SWAP_CNTL));
+- dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
+- RREG32(mmUVD_MP_SWAP_CNTL));
+- dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
+- RREG32(mmUVD_MPC_SET_MUXA0));
+- dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
+- RREG32(mmUVD_MPC_SET_MUXA1));
+- dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
+- RREG32(mmUVD_MPC_SET_MUXB0));
+- dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
+- RREG32(mmUVD_MPC_SET_MUXB1));
+- dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
+- RREG32(mmUVD_MPC_SET_MUX));
+- dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
+- RREG32(mmUVD_MPC_SET_ALU));
+- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
+- RREG32(mmUVD_VCPU_CACHE_OFFSET0));
+- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
+- RREG32(mmUVD_VCPU_CACHE_SIZE0));
+- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
+- RREG32(mmUVD_VCPU_CACHE_OFFSET1));
+- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
+- RREG32(mmUVD_VCPU_CACHE_SIZE1));
+- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
+- RREG32(mmUVD_VCPU_CACHE_OFFSET2));
+- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
+- RREG32(mmUVD_VCPU_CACHE_SIZE2));
+- dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
+- RREG32(mmUVD_VCPU_CNTL));
+- dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
+- RREG32(mmUVD_SOFT_RESET));
+- dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
+- RREG32(mmUVD_RBC_IB_SIZE));
+- dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
+- RREG32(mmUVD_RBC_RB_RPTR));
+- dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
+- RREG32(mmUVD_RBC_RB_WPTR));
+- dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
+- RREG32(mmUVD_RBC_RB_WPTR_CNTL));
+- dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
+- RREG32(mmUVD_RBC_RB_CNTL));
+- dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
+- RREG32(mmUVD_STATUS));
+- dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
+- RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
+- dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
+- RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
+- dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
+- RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
+- dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
+- RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
+- dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
+- RREG32(mmUVD_CONTEXT_ID));
+- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
+- RREG32(mmUVD_UDEC_ADDR_CONFIG));
+- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
+- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
+- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
+- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
+-}
+-
+ static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned type,
+@@ -981,25 +727,100 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
+ return 0;
+ }
+
++static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
++{
++ uint32_t data, data1, data2, suvd_flags;
++
++ data = RREG32(mmUVD_CGC_CTRL);
++ data1 = RREG32(mmUVD_SUVD_CGC_GATE);
++ data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
++
++ data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
++ UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
++
++ suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
++ UVD_SUVD_CGC_GATE__SIT_MASK |
++ UVD_SUVD_CGC_GATE__SMP_MASK |
++ UVD_SUVD_CGC_GATE__SCM_MASK |
++ UVD_SUVD_CGC_GATE__SDB_MASK;
++
++ data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
++ (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
++ (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
++
++ data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
++ UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
++ UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
++ UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
++ UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
++ UVD_CGC_CTRL__SYS_MODE_MASK |
++ UVD_CGC_CTRL__UDEC_MODE_MASK |
++ UVD_CGC_CTRL__MPEG2_MODE_MASK |
++ UVD_CGC_CTRL__REGS_MODE_MASK |
++ UVD_CGC_CTRL__RBC_MODE_MASK |
++ UVD_CGC_CTRL__LMI_MC_MODE_MASK |
++ UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
++ UVD_CGC_CTRL__IDCT_MODE_MASK |
++ UVD_CGC_CTRL__MPRD_MODE_MASK |
++ UVD_CGC_CTRL__MPC_MODE_MASK |
++ UVD_CGC_CTRL__LBSI_MODE_MASK |
++ UVD_CGC_CTRL__LRBBM_MODE_MASK |
++ UVD_CGC_CTRL__WCB_MODE_MASK |
++ UVD_CGC_CTRL__VCPU_MODE_MASK |
++ UVD_CGC_CTRL__JPEG_MODE_MASK |
++ UVD_CGC_CTRL__SCPU_MODE_MASK |
++ UVD_CGC_CTRL__JPEG2_MODE_MASK);
++ data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
++ UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
++ UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
++ UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
++ UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
++ data1 |= suvd_flags;
++
++ WREG32(mmUVD_CGC_CTRL, data);
++ WREG32(mmUVD_CGC_GATE, 0);
++ WREG32(mmUVD_SUVD_CGC_GATE, data1);
++ WREG32(mmUVD_SUVD_CGC_CTRL, data2);
++}
++
++static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)
++{
++ u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
++
++ if (enable)
++ tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
++ GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
++ else
++ tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
++ GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
++
++ WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
++}
++
+ static int uvd_v6_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
++ static int curstate = -1;
++
++ if (adev->asic_type == CHIP_FIJI)
++ uvd_v6_set_bypass_mode(adev, enable);
+
+ if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
+ return 0;
+
++ if (curstate == state)
++ return 0;
++
++ curstate = state;
+ if (enable) {
+- if (adev->flags & AMD_IS_APU)
+- cz_set_uvd_clock_gating_branches(adev, enable);
+- else
+- tonga_set_uvd_clock_gating_branches(adev, enable);
+- uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
++ /* disable HW gating and enable Sw gating */
++ uvd_v6_0_set_sw_clock_gating(adev);
+ } else {
+- uint32_t data = RREG32(mmUVD_CGC_CTRL);
+- data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+- WREG32(mmUVD_CGC_CTRL, data);
++ /* wait for STATUS to clear */
++ if (uvd_v6_0_wait_for_idle(handle))
++ return -EBUSY;
+ }
+
+ return 0;
+@@ -1029,6 +850,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
+ }
+
+ const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
++ .name = "uvd_v6_0",
+ .early_init = uvd_v6_0_early_init,
+ .late_init = NULL,
+ .sw_init = uvd_v6_0_sw_init,
+@@ -1040,7 +862,6 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
+ .is_idle = uvd_v6_0_is_idle,
+ .wait_for_idle = uvd_v6_0_wait_for_idle,
+ .soft_reset = uvd_v6_0_soft_reset,
+- .print_status = uvd_v6_0_print_status,
+ .set_clockgating_state = uvd_v6_0_set_clockgating_state,
+ .set_powergating_state = uvd_v6_0_set_powergating_state,
+ };
+--
+1.9.1
+
diff --git a/common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc b/common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc
index fbbd52af..ffbcf476 100644
--- a/common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc
+++ b/common/recipes-kernel/linux/files/linux-yocto-amd-patches.scc
@@ -1462,6 +1462,7 @@ patch 1570-4-1-0-kernel-s-drivers-I2C-directory.patch
patch 1571-Add-support-for-amd-gnb-bus.patch
patch 1572-drm-amdgpu-fix-num_rbs-exposed-to-userspace.patch
patch 1573-Add-power-gating-initialization-support-for-GFX8.0.patch
+patch 1574-add-support-of-SW-clock-gating-for-UVD6.patch
patch 0300-amd-powerplay-handle-power-management-state-based-on.patch
patch 0001-ALSA-hda-add-AMD-Stoney-PCI-ID-with-proper-driver-ca.patch
patch 0001-fs-prioritize-ext4-rootfs-type.patch