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authorWade Farnsworth <wfarnsworth@users.noreply.github.com>2020-05-29 08:53:21 -0700
committerGitHub <noreply@github.com>2020-05-29 08:53:21 -0700
commite56e1c0a3905ae7c9d570c6b7fde2e31a694276b (patch)
treed1fb9fa54669b6ad7b293e74b1f721e9f332a7f8
parent15872577ba289e5fc23d7a4e5c16eab5c454634d (diff)
parent1c77d6ed794b2257f27c060581aaab14fc9b54bc (diff)
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Merge pull request #679 from choubeyrahul/dunfelldunfell
amdgpu patches on 5.4.2 Linux kernel
-rw-r--r--meta-amd-bsp/conf/machine/include/amd-common-configurations.inc5
-rw-r--r--meta-amd-bsp/recipes-kernel/amd-spi/files/spirom.c6
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0001-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch111
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0002-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch955
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0003-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch82
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0004-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch66
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0005-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch49
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0006-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch226
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0007-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch43
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0008-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch129
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0009-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch145
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0010-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch145
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0011-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch206
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0012-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch141
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0013-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch111
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0014-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch57
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0015-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch38
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0016-drm-amdgpu-Support-new-arcturus-mtype.patch49
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0017-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch121
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0018-drm-amdgpu-Use-optimal-mtypes-and-PTE-bits-for-Arctu.patch79
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0019-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch76
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0020-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch30
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0021-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch75
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0022-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch32
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0023-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch92
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0024-drm-amd-powerplay-update-cached-feature-enablement-s.patch170
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0025-drm-amd-powerplay-do-proper-cleanups-on-hw_fini.patch103
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0026-drm-amdgpu-use-moving-fence-instead-of-exclusive-for.patch36
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0027-drm-amdgpu-reserve-at-least-4MB-of-VRAM-for-page-tab.patch117
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0028-drm-amdgpu-remove-amdgpu_cs_try_evict.patch137
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0029-drm-amdgpu-Fix-bugs-in-amdgpu_device_gpu_recover-in-.patch95
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0030-dmr-amdgpu-Avoid-HW-GPU-reset-for-RAS.patch514
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0031-dmr-amdgpu-Add-system-auto-reboot-to-RAS.patch101
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0032-drm-amdgpu-set-ip-specific-ras-interface-pointer-to-.patch134
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0033-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch157
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0034-drm-amdgpu-gfx-switch-to-amdgpu_gfx_ras_late_init-he.patch155
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0035-drm-amdgpu-sdma-switch-to-amdgpu_sdma_ras_late_init-.patch154
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0036-drm-amdgpu-mmhub-switch-to-amdgpu_mmhub_ras_late_ini.patch154
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0037-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch189
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0038-drm-amdgpu-init-UMC-RSMU-register-base-address.patch29
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0039-drm-amd-amdgpu-add-sw_fini-interface-for-df_funcs.patch101
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0040-drm-amd-powerplay-replace-smu-table_count-with-SMU_T.patch186
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0041-drm-amdgpu-change-r-type-to-int-in-gmc_v9_0_late_ini.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0042-drm-amdgpu-enable-TA-load-support-in-Arcturus.patch45
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0043-drm-amdgpu-clean-up-load-TMR-sequence.patch37
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0044-drm-amdgpu-disable-stutter-mode-for-renoir.patch31
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0045-drm-amdgpu-Disable-page-faults-while-reading-user-wp.patch50
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0046-drm-amdkfd-Query-kfd-device-info-by-CHIP-id-instead-.patch291
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0047-drm-madgpu-Fix-EEPROM-Checksum-calculation.patch32
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0048-drm-amdgpu-change-ras-bps-type-to-eeprom-table-recor.patch186
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0049-drm-amdgpu-Hook-EEPROM-table-to-RAS.patch181
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0050-drm-amdgpu-save-umc-error-records.patch163
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0051-drm-amdgpu-move-the-call-of-ras-recovery_init-and-ba.patch193
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0052-drm-amd-powerplay-fix-unused-variable-compile-warnin.patch67
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0053-drm-amdkfd-Fix-a-building-error-when-KFD_SUPPORT_IOM.patch46
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0054-drm-amd-display-Fix-DML-tests.patch34
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0055-drm-amd-display-refine-i2c-over-aux.patch158
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0056-drm-amd-display-Subsample-mode-suboptimal-for-YCbCr4.patch55
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0057-drm-amd-display-Don-t-allocate-payloads-if-link-lost.patch184
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0058-drm-amd-display-Add-back-support-for-DSC-4-2-2-Simpl.patch33
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0059-drm-amd-display-config-to-override-DSC-start-slice-h.patch83
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0060-drm-amd-display-3.2.49.patch28
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0061-drm-amd-display-Add-missing-surface-address-register.patch80
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0062-drm-amd-display-update-navi-to-use-new-surface-progr.patch980
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0063-drm-amd-display-remove-temporary-transition-code.patch65
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0064-drm-amd-display-Reuse-dcn2-registers.patch270
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0065-drm-amd-display-remove-hw-access-from-dc_destroy.patch204
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0066-drm-amd-display-OTC-underflow-fix.patch36
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0067-drm-amd-display-Isolate-DSC-module-from-driver-depen.patch399
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0068-drm-amd-display-verify-stream-link-before-link-test.patch37
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-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0072-drm-amdgpu-Disable-retry-faults-in-VMID0.patch86
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-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1352-drm-amdgpu-fix-the-instance-loop-and-build-warning.patch33
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1353-drm-amdgpu-added-support-to-get-mGPU-DRAM-base.patch184
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1354-drm-amd-display-Clear-state-after-exiting-fixed-acti.patch44
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1355-drm-amd-display-3.2.65.patch29
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1356-drm-amd-display-fix-chroma-vp-wa-corner-case.patch52
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1357-drm-amd-display-Fix-300Hz-Freesync-bug.patch79
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1358-drm-amd-display-Disable-secondary-link-for-certain-m.patch83
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1359-drm-amd-display-Adding-forgotten-hubbub-func.patch39
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1360-drm-amd-display-Flush-framebuffer-data-before-passin.patch145
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1361-drm-amd-display-Read-inst_fb-data-back-during-DMUB-l.patch74
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1362-drm-amd-display-Soft-reset-DMUIF-during-DMUB-reset.patch66
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1363-drm-amd-display-Add-double-buffering-to-dcn20-OCSC.patch220
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1364-drm-amd-display-store-lttpr-mode-with-dpcd.patch58
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1365-drm-amd-display-Don-t-always-set-pstate-true-if-dumm.patch37
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1366-drm-amd-display-Update-HDMI-hang-w-a-to-apply-to-all.patch57
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1367-drm-amd-display-wait-for-update-when-setting-dpg-tes.patch58
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1368-drm-amd-display-stop-doing-unnecessary-detection-whe.patch57
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1369-drm-amd-display-expand-dml-structs.patch2145
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1370-drm-amd-display-3.2.66.patch29
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1371-drm-amd-display-Fix-double-buffering-in-dcn2-ICSC.patch450
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1372-drm-amd-display-Driverside-changes-to-support-PSR-in.patch483
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1373-drm-amd-display-Double-buffer-dcn2-Gamut-Remap.patch218
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1374-drm-amd-display-programing-surface-flip-by-dmcub.patch293
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1375-drm-amd-display-DMCUB-FW-Changes-to-support-PSR.patch81
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1376-drm-amd-display-Indirect-reg-read-macro-with-shift-a.patch312
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1377-drm-amd-display-Refactor-surface-flip-programming.patch434
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1378-drm-amd-display-Fix-DMUB-PSR-command-IDs.patch51
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1379-drm-amd-display-Add-w-a-to-reset-PHY-before-link-tra.patch74
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1380-drm-amd-display-rename-_lvp-to-l_vp.patch98
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1381-drm-amd-display-Use-SMU-ClockTable-Values-for-DML-Ca.patch40
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1382-drm-amd-display-Add-default-switch-case-for-DCC.patch46
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1383-drm-amd-display-implement-fw-driver-interface-for-ab.patch46
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1384-drm-amd-display-remove-psr-state-condition-when-psr-.patch39
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1385-drm-amd-display-3.2.67.patch29
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1386-drm-amd-display-make-PSR-static-screen-entry-within-.patch530
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1387-drm-amd-display-wait-for-test-pattern-after-when-all.patch43
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1388-drm-amd-display-Add-monitor-patch-for-AUO-dpcd-issue.patch143
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1389-drm-amd-display-Enable-double-buffer-for-OTG_BLANK.patch45
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1390-drm-amd-display-Only-program-surface-flip-for-video-.patch380
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1391-drm-amd-display-Use-mdelay-to-avoid-context-switch.patch41
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1392-drm-amd-display-fixup-DML-dependencies.patch56
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1393-drm-amd-display-reallocate-MST-payload-when-link-los.patch103
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1394-drm-amd-display-3.2.68.patch29
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1395-drm-amd-display-skip-opp-blank-or-unblank-if-test-pa.patch40
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1396-drm-amdgpu-pm-clean-up-return-types.patch97
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1397-drm-amdkfd-Add-a-message-when-SW-scheduler-is-used.patch30
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1398-drm-amdgpu-only-set-cp-active-field-for-kiq-queue.patch73
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1399-drm-amdgpu-check-if-driver-should-try-recovery-in-ra.patch32
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1400-drm-amdgpu-add-arcturus-to-gpu-recovery-check-code-p.patch30
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1401-drm-amdgpu-modify-packet-size-for-pm4-flush-tlbs.patch81
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1402-drm-amd-powerplay-a-quick-fix-for-the-deadlock-issue.patch123
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1403-drm-amdgpu-provide-a-generic-function-interface-for-.patch378
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1404-drm-amdgpu-add-kiq-version-interface-for-RREG32-WREG.patch65
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1405-drm-amdgpu-read-gfx-register-using-RREG32_KIQ-macro.patch64
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1406-drm-amdgpu-remove-the-alignment-placeholder-for-secu.patch38
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1407-drm-amdkfd-Enable-GWS-based-on-FW-Support.patch191
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1408-drm-amdgpu-fix-modprobe-failure-of-the-secondary-GPU.patch99
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1409-drm-amdgpu-sriov-skip-the-update-of-SMU_TABLE_ACTIVI.patch58
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1410-drm-amdgpu-update-mmhub-9.4.1-header-files-for-Acrtu.patch264
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1411-drm-amdgpu-enable-RAS-feature-for-more-mmhub-sub-blo.patch749
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1412-drm-amdgpu-refine-the-security-check-for-RAS-functio.patch47
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1413-drm-amdgpu-abstract-EDC-counter-clear-to-a-separated.patch243
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1414-drm-amdgpu-add-EDC-counter-registers-of-gc-for-Arctu.patch1052
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1415-drm-amdgpu-add-RAS-support-for-the-gfx-block-of-Arct.patch1121
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1416-amd-xgbe-Fix-to-avoid-RX-loss-issue-with-BEL-sfp.patch61
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1417-Revert-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0.patch3138
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1418-drm-amd-display-Fixes-MST-failure-issue-on-RV2-Add-M.patch117
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1419-drm-amdgpu-vcn-Share-vcn_v2_0_dec_ring_test_ring-to-.patch58
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1420-drm-amdgpu-vcn2.5-fix-a-bug-for-the-2nd-vcn-instance.patch56
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1421-drm-amdgpu-vcn-fix-vcn2.5-instance-issue.patch241
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1422-drm-amdgpu-vcn-fix-typo-error.patch29
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1423-drm-amdgpu-vcn-use-inst_idx-relacing-inst.patch66
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1424-drm-amdgpu-remove-unnecessary-conversion-to-bool.patch460
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1425-drm-amdgpu-fix-VRAM-partially-encroached-issue-in-GD.patch109
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1426-Revert-drm-amdgpu-fix-modprobe-failure-of-the-second.patch92
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1427-drm-amdgpu-individualize-fence-allocation-per-entity.patch116
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1428-drm-amd-display-update-MSA-and-VSC-SDP-on-video-test.patch73
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1429-drm-amd-display-Do-not-send-training-pattern-if-VS-D.patch40
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1430-drm-amd-display-Add-debug-option-to-disable-DSC-supp.patch46
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1431-drm-amd-display-Get-fb-base-and-fb-offset-for-DMUB-f.patch114
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1432-drm-amd-display-Fallback-to-DMCUB-when-command-table.patch186
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1433-drm-amd-display-check-pipe_ctx-is-split-pipe-or-not.patch59
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1434-drm-amd-display-Fixed-comment-styling.patch30
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1435-drm-amd-display-Do-DMCUB-hw_init-before-DC.patch47
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1436-drm-amd-display-Fix-DML-dummyinteger-types-mismatch.patch37
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1437-drm-amd-display-Refactor-to-remove-diags-specific-rg.patch405
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1438-drm-amd-display-Refine-i2c-frequency-calculating-seq.patch181
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1439-drm-amd-display-3.2.69.patch28
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1440-drm-amd-display-fix-rotation_angle-to-use-enum-value.patch69
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1441-drm-amd-display-Fix-update-type-for-multiple-planes.patch174
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1442-drm-amd-display-Add-hardware-reset-interface-for-DMU.patch77
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1443-drm-amd-display-Call-ATOM_INIT-instead-of-ATOM_ENABL.patch38
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1444-drm-amd-display-Reset-inbox-rptr-wptr-when-resetting.patch45
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1445-drm-amd-display-Check-hw_init-state-when-determining.patch39
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1446-drm-amd-display-support-VSC-SDP-update-on-video-test.patch53
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1447-drm-amd-display-changed-max_downscale_src_width-to-4.patch36
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1448-drm-amd-display-init-hw-i2c-speed.patch77
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1449-drm-amd-display-use-odm-combine-for-YCbCr420-timing-.patch148
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1450-drm-amdgpu-Fix-TLB-invalidation-request-when-using-s.patch86
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1451-drm-amdgpu-Use-the-correct-flush_type-in-flush_gpu_t.patch58
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1452-i2s-audio-codec-driver-for-raven-Bilby.patch302
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/1453-amd-i2s-Bilby-specific-changes.patch148
-rw-r--r--meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/amdgpu-patches.scc1453
1456 files changed, 225924 insertions, 7 deletions
diff --git a/meta-amd-bsp/conf/machine/include/amd-common-configurations.inc b/meta-amd-bsp/conf/machine/include/amd-common-configurations.inc
index e4c36676..9beec0f0 100644
--- a/meta-amd-bsp/conf/machine/include/amd-common-configurations.inc
+++ b/meta-amd-bsp/conf/machine/include/amd-common-configurations.inc
@@ -27,9 +27,8 @@ MACHINE_FEATURES_remove = "qemu-usermode"
MACHINE_EXTRA_RRECOMMENDS += "kernel-modules alsa-utils"
MACHINE_EXTRA_RRECOMMENDS += "grub parted util-linux-blkid"
-MACHINE_EXTRA_RRECOMMENDS += "rtc-test smbus-test gpio-test"
-MACHINE_EXTRA_RRECOMMENDS += "amd-wdt watchdog-test"
-#MACHINE_EXTRA_RRECOMMENDS += "amd-spi spi-test"
+MACHINE_EXTRA_RRECOMMENDS += "rtc-test watchdog-test spi-test smbus-test gpio-test"
+MACHINE_EXTRA_RRECOMMENDS += "amd-wdt amd-spi"
# Add serial consoles to kernel commandline, these should occur before the tty0
KERNEL_SERIAL_CONSOLE ??= ""
diff --git a/meta-amd-bsp/recipes-kernel/amd-spi/files/spirom.c b/meta-amd-bsp/recipes-kernel/amd-spi/files/spirom.c
index cb5970ba..8547afd1 100644
--- a/meta-amd-bsp/recipes-kernel/amd-spi/files/spirom.c
+++ b/meta-amd-bsp/recipes-kernel/amd-spi/files/spirom.c
@@ -223,11 +223,9 @@ spirom_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
* from the kernel perspective; so they look reversed.
*/
if (_IOC_DIR(cmd) & _IOC_READ)
- err = !access_ok(VERIFY_WRITE,
- (void __user *)arg, _IOC_SIZE(cmd));
+ err = !access_ok((void __user *)arg, _IOC_SIZE(cmd));
if (err == 0 && _IOC_DIR(cmd) & _IOC_WRITE)
- err = !access_ok(VERIFY_READ,
- (void __user *)arg, _IOC_SIZE(cmd));
+ err = !access_ok((void __user *)arg, _IOC_SIZE(cmd));
if (err)
return -EFAULT;
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0001-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0001-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch
new file mode 100644
index 00000000..837723fc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0001-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch
@@ -0,0 +1,111 @@
+From 1c37543acdf46930de0bf174d06d8eaecf3a1e56 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 23 Aug 2019 19:02:14 +0800
+Subject: [PATCH 0001/1453] drm/amdgpu: add new amdgpu nbio header file
+
+More nbio funcitonalities will be added and nbio could
+be treated as an ip block like gfx/sdma.etc
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 87 ++++++++++++++++++++++++
+ 1 file changed, 87 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+new file mode 100644
+index 000000000000..0563476b1242
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -0,0 +1,87 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __AMDGPU_NBIO_H__
++#define __AMDGPU_NBIO_H__
++
++/*
++ * amdgpu nbio functions
++ */
++struct nbio_hdp_flush_reg {
++ u32 ref_and_mask_cp0;
++ u32 ref_and_mask_cp1;
++ u32 ref_and_mask_cp2;
++ u32 ref_and_mask_cp3;
++ u32 ref_and_mask_cp4;
++ u32 ref_and_mask_cp5;
++ u32 ref_and_mask_cp6;
++ u32 ref_and_mask_cp7;
++ u32 ref_and_mask_cp8;
++ u32 ref_and_mask_cp9;
++ u32 ref_and_mask_sdma0;
++ u32 ref_and_mask_sdma1;
++ u32 ref_and_mask_sdma2;
++ u32 ref_and_mask_sdma3;
++ u32 ref_and_mask_sdma4;
++ u32 ref_and_mask_sdma5;
++ u32 ref_and_mask_sdma6;
++ u32 ref_and_mask_sdma7;
++};
++
++struct amdgpu_nbio_funcs {
++ const struct nbio_hdp_flush_reg *hdp_flush_reg;
++ u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
++ u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
++ u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
++ u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
++ u32 (*get_rev_id)(struct amdgpu_device *adev);
++ void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
++ void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
++ u32 (*get_memsize)(struct amdgpu_device *adev);
++ void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
++ bool use_doorbell, int doorbell_index, int doorbell_size);
++ void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
++ int doorbell_index, int instance);
++ void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
++ bool enable);
++ void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
++ bool enable);
++ void (*ih_doorbell_range)(struct amdgpu_device *adev,
++ bool use_doorbell, int doorbell_index);
++ void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
++ bool enable);
++ void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
++ bool enable);
++ void (*get_clockgating_state)(struct amdgpu_device *adev,
++ u32 *flags);
++ void (*ih_control)(struct amdgpu_device *adev);
++ void (*init_registers)(struct amdgpu_device *adev);
++ void (*detect_hw_virt)(struct amdgpu_device *adev);
++ void (*remap_hdp_registers)(struct amdgpu_device *adev);
++};
++
++struct amdgpu_nbio {
++ const struct nbio_hdp_flush_reg *hdp_flush_reg;
++ const struct amdgpu_nbio_funcs *funcs;
++};
++
++#endif
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0002-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0002-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch
new file mode 100644
index 00000000..2aa42b49
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0002-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch
@@ -0,0 +1,955 @@
+From ecadecef4f0d28ec8228dd3895bcffc4598b7a1a Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 23 Aug 2019 19:39:18 +0800
+Subject: [PATCH 0002/1453] drm/amdgpu: switch to new amdgpu_nbio structure
+
+no functional change, just switch to new structures
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 63 ++--------------
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 16 ++---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++--
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +-
+ drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 1 -
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 3 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 1 -
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/nv.c | 34 ++++-----
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +--
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 71 ++++++++++---------
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
+ .../drm/amd/powerplay/smumgr/smu10_smumgr.c | 2 +-
+ .../drm/amd/powerplay/smumgr/vega10_smumgr.c | 2 +-
+ .../drm/amd/powerplay/smumgr/vega12_smumgr.c | 2 +-
+ .../drm/amd/powerplay/smumgr/vega20_smumgr.c | 4 +-
+ 27 files changed, 108 insertions(+), 154 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index bd37df5dd6d0..ca963ed6049c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -73,6 +73,7 @@
+ #include "amdgpu_gmc.h"
+ #include "amdgpu_gfx.h"
+ #include "amdgpu_sdma.h"
++#include "amdgpu_nbio.h"
+ #include "amdgpu_dm.h"
+ #include "amdgpu_virt.h"
+ #include "amdgpu_csa.h"
+@@ -644,69 +645,11 @@ typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
+ typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
+ typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
+
+-
+-/*
+- * amdgpu nbio functions
+- *
+- */
+-struct nbio_hdp_flush_reg {
+- u32 ref_and_mask_cp0;
+- u32 ref_and_mask_cp1;
+- u32 ref_and_mask_cp2;
+- u32 ref_and_mask_cp3;
+- u32 ref_and_mask_cp4;
+- u32 ref_and_mask_cp5;
+- u32 ref_and_mask_cp6;
+- u32 ref_and_mask_cp7;
+- u32 ref_and_mask_cp8;
+- u32 ref_and_mask_cp9;
+- u32 ref_and_mask_sdma0;
+- u32 ref_and_mask_sdma1;
+- u32 ref_and_mask_sdma2;
+- u32 ref_and_mask_sdma3;
+- u32 ref_and_mask_sdma4;
+- u32 ref_and_mask_sdma5;
+- u32 ref_and_mask_sdma6;
+- u32 ref_and_mask_sdma7;
+-};
+-
+ struct amdgpu_mmio_remap {
+ u32 reg_offset;
+ resource_size_t bus_addr;
+ };
+
+-struct amdgpu_nbio_funcs {
+- const struct nbio_hdp_flush_reg *hdp_flush_reg;
+- u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
+- u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
+- u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
+- u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+- u32 (*get_rev_id)(struct amdgpu_device *adev);
+- void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
+- void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
+- u32 (*get_memsize)(struct amdgpu_device *adev);
+- void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
+- bool use_doorbell, int doorbell_index, int doorbell_size);
+- void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
+- int doorbell_index, int instance);
+- void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
+- bool enable);
+- void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
+- bool enable);
+- void (*ih_doorbell_range)(struct amdgpu_device *adev,
+- bool use_doorbell, int doorbell_index);
+- void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
+- bool enable);
+- void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
+- bool enable);
+- void (*get_clockgating_state)(struct amdgpu_device *adev,
+- u32 *flags);
+- void (*ih_control)(struct amdgpu_device *adev);
+- void (*init_registers)(struct amdgpu_device *adev);
+- void (*detect_hw_virt)(struct amdgpu_device *adev);
+- void (*remap_hdp_registers)(struct amdgpu_device *adev);
+-};
+-
+ struct amdgpu_df_funcs {
+ void (*sw_init)(struct amdgpu_device *adev);
+ void (*enable_broadcast_mode)(struct amdgpu_device *adev,
+@@ -921,6 +864,9 @@ struct amdgpu_device {
+ u32 cg_flags;
+ u32 pg_flags;
+
++ /* nbio */
++ struct amdgpu_nbio nbio;
++
+ /* gfx */
+ struct amdgpu_gfx gfx;
+
+@@ -974,7 +920,6 @@ struct amdgpu_device {
+ /* soc15 register offset based on ip, instance and segment */
+ uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+
+- const struct amdgpu_nbio_funcs *nbio_funcs;
+ const struct amdgpu_df_funcs *df_funcs;
+ const struct amdgpu_mmhub_funcs *mmhub_funcs;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 5850c8e34caa..deee4f40423d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -99,8 +99,8 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ unsigned long flags, address, data;
+ uint32_t ficadl_val, ficadh_val;
+
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+@@ -122,8 +122,8 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ {
+ unsigned long flags, address, data;
+
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+@@ -150,8 +150,8 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+ {
+ unsigned long flags, address, data;
+
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, lo_addr);
+@@ -172,8 +172,8 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+ {
+ unsigned long flags, address, data;
+
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, lo_addr);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 53090eae0082..700dd0a1ddcc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -2470,7 +2470,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
+ }
+
+ if (amdgpu_emu_mode == 1)
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
+ tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
+@@ -2540,7 +2540,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
+ }
+
+ if (amdgpu_emu_mode == 1)
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
+ tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
+@@ -2609,7 +2609,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
+ }
+
+ if (amdgpu_emu_mode == 1)
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
+ tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
+@@ -2930,7 +2930,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
+ }
+
+ if (amdgpu_emu_mode == 1)
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
+ tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
+@@ -4384,7 +4384,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ struct amdgpu_device *adev = ring->adev;
+ u32 ref_and_mask, reg_mem_engine;
+- const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++ const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+
+ if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ switch (ring->me) {
+@@ -4404,8 +4404,8 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ }
+
+ gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
+- adev->nbio_funcs->get_hdp_flush_req_offset(adev),
+- adev->nbio_funcs->get_hdp_flush_done_offset(adev),
++ adev->nbio.funcs->get_hdp_flush_req_offset(adev),
++ adev->nbio.funcs->get_hdp_flush_done_offset(adev),
+ ref_and_mask, ref_and_mask, 0x20);
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 97cf0b536873..a48d58ac0d5c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4988,7 +4988,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ struct amdgpu_device *adev = ring->adev;
+ u32 ref_and_mask, reg_mem_engine;
+- const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++ const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+
+ if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ switch (ring->me) {
+@@ -5008,8 +5008,8 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ }
+
+ gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
+- adev->nbio_funcs->get_hdp_flush_req_offset(adev),
+- adev->nbio_funcs->get_hdp_flush_done_offset(adev),
++ adev->nbio.funcs->get_hdp_flush_req_offset(adev),
++ adev->nbio.funcs->get_hdp_flush_done_offset(adev),
+ ref_and_mask, ref_and_mask, 0x20);
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 5c7d5f73f54f..583b4c5200de 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -278,7 +278,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+ int r;
+
+ /* flush hdp cache */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ mutex_lock(&adev->mman.gtt_window_lock);
+
+@@ -556,7 +556,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
+
+ /* size in MB on si */
+ adev->gmc.mc_vram_size =
+- adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
++ adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+ adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
+ adev->gmc.visible_vram_size = adev->gmc.aper_size;
+
+@@ -793,7 +793,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
+ WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
+
+ /* Flush HDP after it is initialized */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
+ false : true;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index f91337030dc0..0a26107b423d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -996,7 +996,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
+
+ /* size in MB on si */
+ adev->gmc.mc_vram_size =
+- adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
++ adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+ adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
+
+ if (!(adev->flags & AMD_IS_APU)) {
+@@ -1361,7 +1361,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
+
+ /* After HDP is initialized, flush HDP.*/
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
+ value = false;
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+index 9fe08408db58..9af73567e716 100644
+--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+@@ -117,7 +117,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
+ /* disable irqs */
+ navi10_ih_disable_interrupts(adev);
+
+- adev->nbio_funcs->ih_control(adev);
++ adev->nbio.funcs->ih_control(adev);
+
+ /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
+@@ -162,7 +162,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
+ }
+ WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
+
+- adev->nbio_funcs->ih_doorbell_range(adev, ih->use_doorbell,
++ adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell,
+ ih->doorbell_index);
+
+ tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+index c05d78d4efc6..e7e36fb6113d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+@@ -311,7 +311,6 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
+ }
+
+ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
+- .hdp_flush_reg = &nbio_v2_3_hdp_flush_reg,
+ .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
+index 5ae52085f6b7..a43b60acf7f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
+@@ -26,6 +26,7 @@
+
+ #include "soc15_common.h"
+
++extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v2_3_funcs;
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+index 6590143c3f75..635d9e1fc0a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+@@ -226,7 +226,7 @@ static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
+ }
+
+-static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
++const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
+ .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
+ .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
+ .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
+@@ -277,7 +277,6 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
+ }
+
+ const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
+- .hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
+ .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+index 0743a6f016f3..6dc743b73218 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+@@ -26,6 +26,7 @@
+
+ #include "soc15_common.h"
+
++extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+index 74eecb768a82..d6cbf26074bc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+@@ -292,7 +292,6 @@ static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
+ }
+
+ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
+- .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
+ .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+index 508d549c5029..e7aefb252550 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+@@ -26,6 +26,7 @@
+
+ #include "soc15_common.h"
+
++extern const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 910fffced43b..c416ab8ab1c3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -266,7 +266,7 @@ static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
+ }
+
+-static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
++const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
+ .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
+ .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
+ .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
+@@ -316,7 +316,6 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
+ }
+
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+- .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
+ .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+index c442865bac4f..b1ac82872752 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+@@ -26,6 +26,7 @@
+
+ #include "soc15_common.h"
+
++extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index de9b995b65b1..81f1d360bc0b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -46,6 +46,7 @@
+ #include "gmc_v10_0.h"
+ #include "gfxhub_v2_0.h"
+ #include "mmhub_v2_0.h"
++#include "nbio_v2_3.h"
+ #include "nv.h"
+ #include "navi10_ih.h"
+ #include "gfx_v10_0.h"
+@@ -63,8 +64,8 @@ static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
+ {
+ unsigned long flags, address, data;
+ u32 r;
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, reg);
+@@ -78,8 +79,8 @@ static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ {
+ unsigned long flags, address, data;
+
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, reg);
+@@ -119,7 +120,7 @@ static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+
+ static u32 nv_get_config_memsize(struct amdgpu_device *adev)
+ {
+- return adev->nbio_funcs->get_memsize(adev);
++ return adev->nbio.funcs->get_memsize(adev);
+ }
+
+ static u32 nv_get_xclk(struct amdgpu_device *adev)
+@@ -279,7 +280,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
+
+ /* wait for asic to come out of reset */
+ for (i = 0; i < adev->usec_timeout; i++) {
+- u32 memsize = adev->nbio_funcs->get_memsize(adev);
++ u32 memsize = adev->nbio.funcs->get_memsize(adev);
+
+ if (memsize != 0xffffffff)
+ break;
+@@ -368,8 +369,8 @@ static void nv_program_aspm(struct amdgpu_device *adev)
+ static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable)
+ {
+- adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
+- adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
++ adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
++ adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
+ }
+
+ static const struct amdgpu_ip_block_version nv_common_ip_block =
+@@ -423,9 +424,10 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ if (r)
+ return r;
+
+- adev->nbio_funcs = &nbio_v2_3_funcs;
++ adev->nbio.funcs = &nbio_v2_3_funcs;
++ adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+
+- adev->nbio_funcs->detect_hw_virt(adev);
++ adev->nbio.funcs->detect_hw_virt(adev);
+
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+@@ -482,12 +484,12 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+
+ static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
+ {
+- return adev->nbio_funcs->get_rev_id(adev);
++ return adev->nbio.funcs->get_rev_id(adev);
+ }
+
+ static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+- adev->nbio_funcs->hdp_flush(adev, ring);
++ adev->nbio.funcs->hdp_flush(adev, ring);
+ }
+
+ static void nv_invalidate_hdp(struct amdgpu_device *adev,
+@@ -694,7 +696,7 @@ static int nv_common_hw_init(void *handle)
+ /* enable aspm */
+ nv_program_aspm(adev);
+ /* setup nbio registers */
+- adev->nbio_funcs->init_registers(adev);
++ adev->nbio.funcs->init_registers(adev);
+ /* enable the doorbell aperture */
+ nv_enable_doorbell_aperture(adev, true);
+
+@@ -856,9 +858,9 @@ static int nv_common_set_clockgating_state(void *handle,
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
+ case CHIP_NAVI12:
+- adev->nbio_funcs->update_medium_grain_clock_gating(adev,
++ adev->nbio.funcs->update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+- adev->nbio_funcs->update_medium_grain_light_sleep(adev,
++ adev->nbio.funcs->update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ nv_update_hdp_mem_power_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+@@ -886,7 +888,7 @@ static void nv_common_get_clockgating_state(void *handle, u32 *flags)
+ if (amdgpu_sriov_vf(adev))
+ *flags = 0;
+
+- adev->nbio_funcs->get_clockgating_state(adev, flags);
++ adev->nbio.funcs->get_clockgating_state(adev, flags);
+
+ /* AMD_CG_SUPPORT_HDP_MGCG */
+ tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 4554e72c8378..9d536822b0fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -747,13 +747,13 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ struct amdgpu_device *adev = ring->adev;
+ u32 ref_and_mask = 0;
+- const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++ const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+
+ ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
+
+ sdma_v4_0_wait_reg_mem(ring, 0, 1,
+- adev->nbio_funcs->get_hdp_flush_done_offset(adev),
+- adev->nbio_funcs->get_hdp_flush_req_offset(adev),
++ adev->nbio.funcs->get_hdp_flush_done_offset(adev),
++ adev->nbio.funcs->get_hdp_flush_req_offset(adev),
+ ref_and_mask, ref_and_mask, 10);
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 8493bfbbc148..f4ad2990f973 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -406,7 +406,7 @@ static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ struct amdgpu_device *adev = ring->adev;
+ u32 ref_and_mask = 0;
+- const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++ const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+
+ if (ring->me == 0)
+ ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
+@@ -416,8 +416,8 @@ static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+ SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
+ SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
+- amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
+- amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
++ amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
++ amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
+ amdgpu_ring_write(ring, ref_and_mask); /* reference */
+ amdgpu_ring_write(ring, ref_and_mask); /* mask */
+ amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+@@ -683,7 +683,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
+ WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+ WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+
+- adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
++ adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
+ ring->doorbell_index, 20);
+
+ if (amdgpu_sriov_vf(adev))
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 4ccfcdf8f16a..7f6c73493939 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -58,6 +58,9 @@
+ #include "mmhub_v1_0.h"
+ #include "df_v1_7.h"
+ #include "df_v3_6.h"
++#include "nbio_v6_1.h"
++#include "nbio_v7_0.h"
++#include "nbio_v7_4.h"
+ #include "vega10_ih.h"
+ #include "sdma_v4_0.h"
+ #include "uvd_v7_0.h"
+@@ -91,8 +94,8 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
+ {
+ unsigned long flags, address, data;
+ u32 r;
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, reg);
+@@ -106,8 +109,8 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ {
+ unsigned long flags, address, data;
+
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ WREG32(address, reg);
+@@ -121,8 +124,8 @@ static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
+ {
+ unsigned long flags, address, data;
+ u64 r;
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ /* read low 32 bit */
+@@ -142,8 +145,8 @@ static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
+ {
+ unsigned long flags, address, data;
+
+- address = adev->nbio_funcs->get_pcie_index_offset(adev);
+- data = adev->nbio_funcs->get_pcie_data_offset(adev);
++ address = adev->nbio.funcs->get_pcie_index_offset(adev);
++ data = adev->nbio.funcs->get_pcie_data_offset(adev);
+
+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ /* write low 32 bit */
+@@ -262,7 +265,7 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+
+ static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
+ {
+- return adev->nbio_funcs->get_memsize(adev);
++ return adev->nbio.funcs->get_memsize(adev);
+ }
+
+ static u32 soc15_get_xclk(struct amdgpu_device *adev)
+@@ -461,7 +464,7 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
+
+ /* wait for asic to come out of reset */
+ for (i = 0; i < adev->usec_timeout; i++) {
+- u32 memsize = adev->nbio_funcs->get_memsize(adev);
++ u32 memsize = adev->nbio.funcs->get_memsize(adev);
+
+ if (memsize != 0xffffffff)
+ break;
+@@ -626,8 +629,8 @@ static void soc15_program_aspm(struct amdgpu_device *adev)
+ static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable)
+ {
+- adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
+- adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
++ adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
++ adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
+ }
+
+ static const struct amdgpu_ip_block_version vega10_common_ip_block =
+@@ -641,7 +644,7 @@ static const struct amdgpu_ip_block_version vega10_common_ip_block =
+
+ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
+ {
+- return adev->nbio_funcs->get_rev_id(adev);
++ return adev->nbio.funcs->get_rev_id(adev);
+ }
+
+ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+@@ -667,13 +670,17 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
+ adev->gmc.xgmi.supported = true;
+
+- if (adev->flags & AMD_IS_APU)
+- adev->nbio_funcs = &nbio_v7_0_funcs;
+- else if (adev->asic_type == CHIP_VEGA20 ||
+- adev->asic_type == CHIP_ARCTURUS)
+- adev->nbio_funcs = &nbio_v7_4_funcs;
+- else
+- adev->nbio_funcs = &nbio_v6_1_funcs;
++ if (adev->flags & AMD_IS_APU) {
++ adev->nbio.funcs = &nbio_v7_0_funcs;
++ adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
++ } else if (adev->asic_type == CHIP_VEGA20 ||
++ adev->asic_type == CHIP_ARCTURUS) {
++ adev->nbio.funcs = &nbio_v7_4_funcs;
++ adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
++ } else {
++ adev->nbio.funcs = &nbio_v6_1_funcs;
++ adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
++ }
+
+ if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
+ adev->df_funcs = &df_v3_6_funcs;
+@@ -681,7 +688,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ adev->df_funcs = &df_v1_7_funcs;
+
+ adev->rev_id = soc15_get_rev_id(adev);
+- adev->nbio_funcs->detect_hw_virt(adev);
++ adev->nbio.funcs->detect_hw_virt(adev);
+
+ if (amdgpu_sriov_vf(adev))
+ adev->virt.ops = &xgpu_ai_virt_ops;
+@@ -785,7 +792,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+
+ static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+- adev->nbio_funcs->hdp_flush(adev, ring);
++ adev->nbio.funcs->hdp_flush(adev, ring);
+ }
+
+ static void soc15_invalidate_hdp(struct amdgpu_device *adev,
+@@ -1236,12 +1243,12 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev)
+ if (!amdgpu_sriov_vf(adev)) {
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ ring = &adev->sdma.instance[i].ring;
+- adev->nbio_funcs->sdma_doorbell_range(adev, i,
++ adev->nbio.funcs->sdma_doorbell_range(adev, i,
+ ring->use_doorbell, ring->doorbell_index,
+ adev->doorbell_index.sdma_doorbell_range);
+ }
+
+- adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
++ adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
+ adev->irq.ih.doorbell_index);
+ }
+ }
+@@ -1255,13 +1262,13 @@ static int soc15_common_hw_init(void *handle)
+ /* enable aspm */
+ soc15_program_aspm(adev);
+ /* setup nbio registers */
+- adev->nbio_funcs->init_registers(adev);
++ adev->nbio.funcs->init_registers(adev);
+ /* remap HDP registers to a hole in mmio space,
+ * for the purpose of expose those registers
+ * to process space
+ */
+- if (adev->nbio_funcs->remap_hdp_registers)
+- adev->nbio_funcs->remap_hdp_registers(adev);
++ if (adev->nbio.funcs->remap_hdp_registers)
++ adev->nbio.funcs->remap_hdp_registers(adev);
+
+ /* enable the doorbell aperture */
+ soc15_enable_doorbell_aperture(adev, true);
+@@ -1424,9 +1431,9 @@ static int soc15_common_set_clockgating_state(void *handle,
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+- adev->nbio_funcs->update_medium_grain_clock_gating(adev,
++ adev->nbio.funcs->update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+- adev->nbio_funcs->update_medium_grain_light_sleep(adev,
++ adev->nbio.funcs->update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ soc15_update_hdp_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+@@ -1441,9 +1448,9 @@ static int soc15_common_set_clockgating_state(void *handle,
+ break;
+ case CHIP_RAVEN:
+ case CHIP_RENOIR:
+- adev->nbio_funcs->update_medium_grain_clock_gating(adev,
++ adev->nbio.funcs->update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+- adev->nbio_funcs->update_medium_grain_light_sleep(adev,
++ adev->nbio.funcs->update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ soc15_update_hdp_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+@@ -1472,7 +1479,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
+ if (amdgpu_sriov_vf(adev))
+ *flags = 0;
+
+- adev->nbio_funcs->get_clockgating_state(adev, flags);
++ adev->nbio.funcs->get_clockgating_state(adev, flags);
+
+ /* AMD_CG_SUPPORT_HDP_LS */
+ data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 36ad0c0e8efb..4628fd10a9ec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -244,7 +244,7 @@ static int vcn_v2_0_hw_init(void *handle)
+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ int i, r;
+
+- adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ring->doorbell_index, 0);
+
+ ring->sched.ready = true;
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 395c2259f979..2d7109d443c4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -255,7 +255,7 @@ static int vcn_v2_5_hw_init(void *handle)
+ continue;
+ ring = &adev->vcn.inst[j].ring_dec;
+
+- adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ring->doorbell_index, j);
+
+ r = amdgpu_ring_test_ring(ring);
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+index 9eae3536ddad..14e0b0438d09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+@@ -226,7 +226,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ /* disable irqs */
+ vega10_ih_disable_interrupts(adev);
+
+- adev->nbio_funcs->ih_control(adev);
++ adev->nbio.funcs->ih_control(adev);
+
+ ih = &adev->irq.ih;
+ /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 4acf139ea014..146f6b53d89b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -463,7 +463,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
+ return ret;
+
+ /* flush hdp cache */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ if (!drv2smu)
+ memcpy(table_data, table->cpu_addr, table->size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+index 3f12cf341511..aa0ee2b46135 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+@@ -137,7 +137,7 @@ static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ priv->smu_tables.entry[table_id].table_id);
+
+ /* flush hdp cache */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
+ priv->smu_tables.entry[table_id].size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+index 0dbdde69f2d9..0f3836fd9666 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+@@ -58,7 +58,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ priv->smu_tables.entry[table_id].table_id);
+
+ /* flush hdp cache */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ memcpy(table, priv->smu_tables.entry[table_id].table,
+ priv->smu_tables.entry[table_id].size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+index f9589806bf83..90c782c132d2 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+@@ -66,7 +66,7 @@ static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ return -EINVAL);
+
+ /* flush hdp cache */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ memcpy(table, priv->smu_tables.entry[table_id].table,
+ priv->smu_tables.entry[table_id].size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+index b9089c6bea85..f604612f411f 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+@@ -189,7 +189,7 @@ static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ return ret);
+
+ /* flush hdp cache */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ memcpy(table, priv->smu_tables.entry[table_id].table,
+ priv->smu_tables.entry[table_id].size);
+@@ -290,7 +290,7 @@ int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
+ return ret);
+
+ /* flush hdp cache */
+- adev->nbio_funcs->hdp_flush(adev, NULL);
++ adev->nbio.funcs->hdp_flush(adev, NULL);
+
+ memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,
+ priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0003-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0003-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch
new file mode 100644
index 00000000..d7c1561f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0003-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch
@@ -0,0 +1,82 @@
+From 1ceedda04eed96f689f1dd1b0e8f8cfc4d8da52f Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 30 May 2019 11:57:20 +0800
+Subject: [PATCH 0003/1453] drm/amdgpu/nbio: add functions to query ras
+ specific interrupt status
+
+ras_controller_interrupt and err_event_interrupt are ras specific interrupts.
+add functions to check their status and ack them if they are generated. both
+funcitons should only be invoked in ISR when BIF ring is disabled or even not
+initialized.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 32 ++++++++++++++++++++++++
+ 2 files changed, 34 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 0563476b1242..28417e485c58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -77,6 +77,8 @@ struct amdgpu_nbio_funcs {
+ void (*init_registers)(struct amdgpu_device *adev);
+ void (*detect_hw_virt)(struct amdgpu_device *adev);
+ void (*remap_hdp_registers)(struct amdgpu_device *adev);
++ void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
++ void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
+ };
+
+ struct amdgpu_nbio {
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index c416ab8ab1c3..6ecdd5e3ca3f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -315,6 +315,36 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
+ WREG32_PCIE(smnPCIE_CI_CNTL, data);
+ }
+
++static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
++{
++ uint32_t bif_doorbell_intr_cntl;
++
++ bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
++ if (REG_GET_FIELD(bif_doorbell_intr_cntl,
++ BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
++ /* driver has to clear the interrupt status when bif ring is disabled */
++ bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++ BIF_DOORBELL_INT_CNTL,
++ RAS_CNTLR_INTERRUPT_CLEAR, 1);
++ WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++ }
++}
++
++static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
++{
++ uint32_t bif_doorbell_intr_cntl;
++
++ bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
++ if (REG_GET_FIELD(bif_doorbell_intr_cntl,
++ BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
++ /* driver has to clear the interrupt status when bif ring is disabled */
++ bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++ BIF_DOORBELL_INT_CNTL,
++ RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
++ WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++ }
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -336,4 +366,6 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .init_registers = nbio_v7_4_init_registers,
+ .detect_hw_virt = nbio_v7_4_detect_hw_virt,
+ .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
++ .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
++ .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0004-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0004-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch
new file mode 100644
index 00000000..3c712873
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0004-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch
@@ -0,0 +1,66 @@
+From 655e30cd1b62731566d10b2daa26b2d2fdfc397e Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 29 May 2019 14:00:19 +0800
+Subject: [PATCH 0004/1453] drm/amdgpu: add nbif v7_4 irq source header for
+ vega20
+
+nbif v7_4 interrupt source definition
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/ivsrcid/nbio/irqsrcs_nbif_7_4.h | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h
+
+diff --git a/drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h b/drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h
+new file mode 100644
+index 000000000000..79af4258f259
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __IRQSRCS_NBIF_7_4_H__
++#define __IRQSRCS_NBIF_7_4_H__
++
++#define NBIF_7_4__SRCID__CHIP_ERR_INT_EVENT 0x5E // Error generated
++#define NBIF_7_4__SRCID__DOORBELL_INTERRUPT 0x5F // Interrupt for doorbell event during VDDGFX off
++#define NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT 0x60 // Interrupt for ras_intr_valid from RAS controller
++#define NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT 0x61 // Interrupt for SDP ErrEvent received from ATHUB
++#define NBIF_7_4__SRCID__PF_VF_MSGBUF_VALID 0x87 // Valid message in PF->VF mailbox message buffer (The interrupt is sent on behalf of PF)
++#define NBIF_7_4__SRCID__PF_VF_MSGBUF_ACK 0x88 // Acknowledge message in PF->VF mailbox message buffer (The interrupt is sent on behalf of VF)
++#define NBIF_7_4__SRCID__VF_PF_MSGBUF_VALID 0x89 // Valid message in VF->PF mailbox message buffer (The interrupt is sent on behalf of VF)
++#define NBIF_7_4__SRCID__VF_PF_MSGBUF_ACK 0x8A // Acknowledge message in VF->PF mailbox message buffer (The interrupt is sent on behalf of PF)
++#define NBIF_7_4__SRCID__CHIP_DPA_INT_EVENT 0xA0 // BIF_CHIP_DPA_INT_EVENT
++#define NBIF_7_4__SRCID__CHIP_SLOT_POWER_CHG_INT_EVENT 0xA1 // BIF_CHIP_SLOT_POWER_CHG_INT_EVENT
++#define NBIF_7_4__SRCID__ATOMIC_UR_OPCODE 0xCE // BIF receives unsupported atomic opcode from MC
++#define NBIF_7_4__SRCID__ATOMIC_REQESTEREN_LOW 0xCF // BIF receive atomic request from MC while AtomicOp Requester is not enabled in PCIE config space
++
++#endif // __IRQSRCS_NBIF_7_4_H__
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0005-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0005-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch
new file mode 100644
index 00000000..835b0d43
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0005-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch
@@ -0,0 +1,49 @@
+From 09576ff43c18df6347ca049366f496fc294aae89 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 5 Jun 2019 14:20:38 +0800
+Subject: [PATCH 0005/1453] drm/amdgpu: update nbio v7_4 ip header files
+
+Add mmBIF_INTR_CNTL and its shift mask.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h | 4 ++--
+ .../gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h | 6 +++---
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
+index 994e796a28d7..ce5830ebe095 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
+@@ -2793,8 +2793,8 @@
+ #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2
+ #define mmBIF_FB_EN 0x00ff
+ #define mmBIF_FB_EN_BASE_IDX 2
+-#define mmBIF_BUSY_DELAY_CNTR 0x0100
+-#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2
++#define mmBIF_INTR_CNTL 0x0100
++#define mmBIF_INTR_CNTL_BASE_IDX 2
+ #define mmBIF_MST_TRANS_PENDING_VF 0x0109
+ #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2
+ #define mmBIF_SLV_TRANS_PENDING_VF 0x010a
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
+index d467b939c971..f9829f577364 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
+@@ -20420,9 +20420,9 @@
+ #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+ #define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+ #define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+-//BIF_BUSY_DELAY_CNTR
+-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003FL
++//BIF_INTR_CNTL
++#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
++#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
+ //BIF_MST_TRANS_PENDING_VF
+ #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+ #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0006-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0006-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch
new file mode 100644
index 00000000..f1cf8620
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0006-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch
@@ -0,0 +1,226 @@
+From a120b1b0298837f1b1f19393f2f85f282e4e2c84 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 5 Jun 2019 14:57:00 +0800
+Subject: [PATCH 0006/1453] drm/amdgpu: add ras_controller and err_event_athub
+ interrupt support
+
+Ras controller interrupt and Ras err event athub interrupt are two dedicated
+interrupts for RAS support.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 4 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 +++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 125 +++++++++++++++++++++++
+ 3 files changed, 143 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 28417e485c58..a04c5ea03418 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -79,10 +79,14 @@ struct amdgpu_nbio_funcs {
+ void (*remap_hdp_registers)(struct amdgpu_device *adev);
+ void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
+ void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
++ int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
++ int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
+ };
+
+ struct amdgpu_nbio {
+ const struct nbio_hdp_flush_reg *hdp_flush_reg;
++ struct amdgpu_irq_src ras_controller_irq;
++ struct amdgpu_irq_src ras_err_event_athub_irq;
+ const struct amdgpu_nbio_funcs *funcs;
+ };
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 016ea274b955..f7180109bef4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -29,6 +29,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_ras.h"
+ #include "amdgpu_atomfirmware.h"
++#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
+
+ const char *ras_error_string[] = {
+ "none",
+@@ -1500,6 +1501,7 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
+ int amdgpu_ras_init(struct amdgpu_device *adev)
+ {
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
++ int r;
+
+ if (con)
+ return 0;
+@@ -1527,6 +1529,18 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ /* Might need get this flag from vbios. */
+ con->flags = RAS_DEFAULT_FLAGS;
+
++ if (adev->nbio.funcs->init_ras_controller_interrupt) {
++ r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
++ if (r)
++ return r;
++ }
++
++ if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
++ r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
++ if (r)
++ return r;
++ }
++
+ if (amdgpu_ras_recovery_init(adev))
+ goto recovery_out;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 6ecdd5e3ca3f..faf9300630a5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -27,6 +27,7 @@
+ #include "nbio/nbio_7_4_offset.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
+ #include "nbio/nbio_7_4_0_smn.h"
++#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
+ #include <uapi/linux/kfd_ioctl.h>
+
+ #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
+@@ -345,6 +346,128 @@ static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_d
+ }
+ }
+
++
++static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *src,
++ unsigned type,
++ enum amdgpu_interrupt_state state)
++{
++ /* The ras_controller_irq enablement should be done in psp bl when it
++ * tries to enable ras feature. Driver only need to set the correct interrupt
++ * vector for bare-metal and sriov use case respectively
++ */
++ uint32_t bif_intr_cntl;
++
++ bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
++ if (state == AMDGPU_IRQ_STATE_ENABLE) {
++ /* set interrupt vector select bit to 0 to select
++ * vetcor 1 for bare metal case */
++ bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
++ BIF_INTR_CNTL,
++ RAS_INTR_VEC_SEL, 0);
++ WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
++ }
++
++ return 0;
++}
++
++static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ struct amdgpu_iv_entry *entry)
++{
++ /* By design, the ih cookie for ras_controller_irq should be written
++ * to BIFring instead of general iv ring. However, due to known bif ring
++ * hw bug, it has to be disabled. There is no chance the process function
++ * will be involked. Just left it as a dummy one.
++ */
++ return 0;
++}
++
++static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *src,
++ unsigned type,
++ enum amdgpu_interrupt_state state)
++{
++ /* The ras_controller_irq enablement should be done in psp bl when it
++ * tries to enable ras feature. Driver only need to set the correct interrupt
++ * vector for bare-metal and sriov use case respectively
++ */
++ uint32_t bif_intr_cntl;
++
++ bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
++ if (state == AMDGPU_IRQ_STATE_ENABLE) {
++ /* set interrupt vector select bit to 0 to select
++ * vetcor 1 for bare metal case */
++ bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
++ BIF_INTR_CNTL,
++ RAS_INTR_VEC_SEL, 0);
++ WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
++ }
++
++ return 0;
++}
++
++static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
++ struct amdgpu_irq_src *source,
++ struct amdgpu_iv_entry *entry)
++{
++ /* By design, the ih cookie for err_event_athub_irq should be written
++ * to BIFring instead of general iv ring. However, due to known bif ring
++ * hw bug, it has to be disabled. There is no chance the process function
++ * will be involked. Just left it as a dummy one.
++ */
++ return 0;
++}
++
++static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
++ .set = nbio_v7_4_set_ras_controller_irq_state,
++ .process = nbio_v7_4_process_ras_controller_irq,
++};
++
++static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
++ .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
++ .process = nbio_v7_4_process_err_event_athub_irq,
++};
++
++static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
++{
++ int r;
++
++ /* init the irq funcs */
++ adev->nbio.ras_controller_irq.funcs =
++ &nbio_v7_4_ras_controller_irq_funcs;
++ adev->nbio.ras_controller_irq.num_types = 1;
++
++ /* register ras controller interrupt */
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
++ NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
++ &adev->nbio.ras_controller_irq);
++ if (r)
++ return r;
++
++ return 0;
++}
++
++static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
++{
++
++ int r;
++
++ /* init the irq funcs */
++ adev->nbio.ras_err_event_athub_irq.funcs =
++ &nbio_v7_4_ras_err_event_athub_irq_funcs;
++ adev->nbio.ras_err_event_athub_irq.num_types = 1;
++
++ /* register ras err event athub interrupt */
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
++ NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
++ &adev->nbio.ras_err_event_athub_irq);
++ if (r)
++ return r;
++
++ return 0;
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -368,4 +491,6 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
+ .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
+ .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
++ .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
++ .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0007-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0007-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch
new file mode 100644
index 00000000..ab116a86
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0007-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch
@@ -0,0 +1,43 @@
+From bb364e76f1ed71ff22d58c7b9fa08c04a2b7e056 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 5 Jun 2019 14:40:57 +0800
+Subject: [PATCH 0007/1453] drm/amdgpu: poll ras_controller_irq and
+ err_event_athub_irq status
+
+For the hardware that can not enable BIF ring for IH cookies for both
+ras_controller_irq and err_event_athub_irq, the driver has to poll the
+status register in irq handling and ack the hardware properly when there
+is interrupt triggered
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 2a3f5ec298db..4ed6a4d0d7db 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -153,6 +153,18 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
+ ret = amdgpu_ih_process(adev, &adev->irq.ih);
+ if (ret == IRQ_HANDLED)
+ pm_runtime_mark_last_busy(dev->dev);
++
++ /* For the hardware that cannot enable bif ring for both ras_controller_irq
++ * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
++ * register to check whether the interrupt is triggered or not, and properly
++ * ack the interrupt if it is there
++ */
++ if (adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
++ adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
++
++ if (adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
++ adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
++
+ return ret;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0008-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0008-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch
new file mode 100644
index 00000000..6288b4eb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0008-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch
@@ -0,0 +1,129 @@
+From 08013d0255595dd89566a7b5769e296e7e022c00 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 30 Aug 2019 13:29:18 +0800
+Subject: [PATCH 0008/1453] drm/amdgpu: add helper function to do common
+ ras_late_init/fini (v3)
+
+In late_init for ras, the helper function will be used to
+1). disable ras feature if the IP block is masked as disabled
+2). send enable feature command if the ip block was masked as enabled
+3). create debugfs/sysfs node per IP block
+4). register interrupt handler
+
+v2: check ih_info.cb to decide add interrupt handler or not
+
+v3: add ras_late_fini for cleanup all the ras fs node and remove
+interrupt handler
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 72 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 7 +++
+ 2 files changed, 79 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index f7180109bef4..0b466d101f53 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1566,6 +1566,78 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ return -EINVAL;
+ }
+
++/* helper function to handle common stuff in ip late init phase */
++int amdgpu_ras_late_init(struct amdgpu_device *adev,
++ struct ras_common_if *ras_block,
++ struct ras_fs_if *fs_info,
++ struct ras_ih_if *ih_info)
++{
++ int r;
++
++ /* disable RAS feature per IP block if it is not supported */
++ if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
++ amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
++ return 0;
++ }
++
++ r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
++ if (r) {
++ if (r == -EAGAIN) {
++ /* request gpu reset. will run again */
++ amdgpu_ras_request_reset_on_boot(adev,
++ ras_block->block);
++ return 0;
++ } else if (adev->in_suspend || adev->in_gpu_reset) {
++ /* in resume phase, if fail to enable ras,
++ * clean up all ras fs nodes, and disable ras */
++ goto cleanup;
++ } else
++ return r;
++ }
++
++ /* in resume phase, no need to create ras fs node */
++ if (adev->in_suspend || adev->in_gpu_reset)
++ return 0;
++
++ if (ih_info->cb) {
++ r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
++ if (r)
++ goto interrupt;
++ }
++
++ amdgpu_ras_debugfs_create(adev, fs_info);
++
++ r = amdgpu_ras_sysfs_create(adev, fs_info);
++ if (r)
++ goto sysfs;
++
++ return 0;
++cleanup:
++ amdgpu_ras_sysfs_remove(adev, ras_block);
++sysfs:
++ amdgpu_ras_debugfs_remove(adev, ras_block);
++ if (ih_info->cb)
++ amdgpu_ras_interrupt_remove_handler(adev, ih_info);
++interrupt:
++ amdgpu_ras_feature_enable(adev, ras_block, 0);
++ return r;
++}
++
++/* helper function to remove ras fs node and interrupt handler */
++void amdgpu_ras_late_fini(struct amdgpu_device *adev,
++ struct ras_common_if *ras_block,
++ struct ras_ih_if *ih_info)
++{
++ if (!ras_block || !ih_info)
++ return;
++
++ amdgpu_ras_sysfs_remove(adev, ras_block);
++ amdgpu_ras_debugfs_remove(adev, ras_block);
++ if (ih_info->cb)
++ amdgpu_ras_interrupt_remove_handler(adev, ih_info);
++ amdgpu_ras_feature_enable(adev, ras_block, 0);
++}
++
+ /* do some init work after IP late init as dependence.
+ * and it runs in resume/gpu reset/booting up cases.
+ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 6c76bb2a6843..66b71525446e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -566,6 +566,13 @@ amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
+ int amdgpu_ras_init(struct amdgpu_device *adev);
+ int amdgpu_ras_fini(struct amdgpu_device *adev);
+ int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
++int amdgpu_ras_late_init(struct amdgpu_device *adev,
++ struct ras_common_if *ras_block,
++ struct ras_fs_if *fs_info,
++ struct ras_ih_if *ih_info);
++void amdgpu_ras_late_fini(struct amdgpu_device *adev,
++ struct ras_common_if *ras_block,
++ struct ras_ih_if *ih_info);
+
+ int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
+ struct ras_common_if *head, bool enable);
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0009-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0009-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch
new file mode 100644
index 00000000..f0afbff4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0009-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch
@@ -0,0 +1,145 @@
+From e3a7b792d827ebf2bc47a2d434cd820d2fac7331 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:15:16 +0800
+Subject: [PATCH 0009/1453] drm/amdgpu: switch to amdgpu_ras_late_init for gfx
+ v9 block (v2)
+
+call helper function in late init phase to handle ras init
+for gfx ip block
+
+v2: call ras_late_fini to do clean up when fail to enable interrupt
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 92 ++++++---------------------
+ 1 file changed, 21 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index a48d58ac0d5c..633a70815576 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4418,7 +4418,6 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ static int gfx_v9_0_ecc_late_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+- struct ras_common_if **ras_if = &adev->gfx.ras_if;
+ struct ras_ih_if ih_info = {
+ .cb = gfx_v9_0_process_ras_data_cb,
+ };
+@@ -4426,18 +4425,18 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ .sysfs_name = "gfx_err_count",
+ .debugfs_name = "gfx_err_inject",
+ };
+- struct ras_common_if ras_block = {
+- .block = AMDGPU_RAS_BLOCK__GFX,
+- .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+- .sub_block_index = 0,
+- .name = "gfx",
+- };
+ int r;
+
+- if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
+- amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
+- return 0;
++ if (!adev->gfx.ras_if) {
++ adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++ if (!adev->gfx.ras_if)
++ return -ENOMEM;
++ adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
++ adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++ adev->gfx.ras_if->sub_block_index = 0;
++ strcpy(adev->gfx.ras_if->name, "gfx");
+ }
++ fs_info.head = ih_info.head = *adev->gfx.ras_if;
+
+ r = gfx_v9_0_do_edc_gds_workarounds(adev);
+ if (r)
+@@ -4448,71 +4447,22 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ if (r)
+ return r;
+
+- /* handle resume path. */
+- if (*ras_if) {
+- /* resend ras TA enable cmd during resume.
+- * prepare to handle failure.
+- */
+- ih_info.head = **ras_if;
+- r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+- if (r) {
+- if (r == -EAGAIN) {
+- /* request a gpu reset. will run again. */
+- amdgpu_ras_request_reset_on_boot(adev,
+- AMDGPU_RAS_BLOCK__GFX);
+- return 0;
+- }
+- /* fail to enable ras, cleanup all. */
+- goto irq;
+- }
+- /* enable successfully. continue. */
+- goto resume;
+- }
+-
+- *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
+- if (!*ras_if)
+- return -ENOMEM;
+-
+- **ras_if = ras_block;
+-
+- r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+- if (r) {
+- if (r == -EAGAIN) {
+- amdgpu_ras_request_reset_on_boot(adev,
+- AMDGPU_RAS_BLOCK__GFX);
+- r = 0;
+- }
+- goto feature;
+- }
+-
+- ih_info.head = **ras_if;
+- fs_info.head = **ras_if;
+-
+- r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
++ r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
++ &fs_info, &ih_info);
+ if (r)
+- goto interrupt;
++ goto free;
+
+- amdgpu_ras_debugfs_create(adev, &fs_info);
+-
+- r = amdgpu_ras_sysfs_create(adev, &fs_info);
+- if (r)
+- goto sysfs;
+-resume:
+- r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+- if (r)
+- goto irq;
++ if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
++ r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
++ if (r)
++ goto late_fini;
++ }
+
+ return 0;
+-irq:
+- amdgpu_ras_sysfs_remove(adev, *ras_if);
+-sysfs:
+- amdgpu_ras_debugfs_remove(adev, *ras_if);
+- amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-interrupt:
+- amdgpu_ras_feature_enable(adev, *ras_if, 0);
+-feature:
+- kfree(*ras_if);
+- *ras_if = NULL;
++late_fini:
++ amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
++free:
++ kfree(adev->gfx.ras_if);
+ return r;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0010-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0010-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch
new file mode 100644
index 00000000..4bd20559
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0010-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch
@@ -0,0 +1,145 @@
+From da5d3393d0c55adb3fb84569bbcfab0e896ae6bb Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:30:02 +0800
+Subject: [PATCH 0010/1453] drm/amdgpu: switch to amdgpu_ras_late_init for sdma
+ v4 block (v2)
+
+call helper function in late init phase to handle ras init
+for sdma ip block
+
+v2: call ras_late_fini to do clean up when fail to enable interrupt
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 98 +++++++-------------------
+ 1 file changed, 24 insertions(+), 74 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 9d536822b0fc..dbd99e8e5045 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1697,7 +1697,6 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ static int sdma_v4_0_late_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+- struct ras_common_if **ras_if = &adev->sdma.ras_if;
+ struct ras_ih_if ih_info = {
+ .cb = sdma_v4_0_process_ras_data_cb,
+ };
+@@ -1705,87 +1704,38 @@ static int sdma_v4_0_late_init(void *handle)
+ .sysfs_name = "sdma_err_count",
+ .debugfs_name = "sdma_err_inject",
+ };
+- struct ras_common_if ras_block = {
+- .block = AMDGPU_RAS_BLOCK__SDMA,
+- .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+- .sub_block_index = 0,
+- .name = "sdma",
+- };
+ int r, i;
+
+- if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
+- amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
+- return 0;
+- }
+-
+- /* handle resume path. */
+- if (*ras_if) {
+- /* resend ras TA enable cmd during resume.
+- * prepare to handle failure.
+- */
+- ih_info.head = **ras_if;
+- r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+- if (r) {
+- if (r == -EAGAIN) {
+- /* request a gpu reset. will run again. */
+- amdgpu_ras_request_reset_on_boot(adev,
+- AMDGPU_RAS_BLOCK__SDMA);
+- return 0;
+- }
+- /* fail to enable ras, cleanup all. */
+- goto irq;
+- }
+- /* enable successfully. continue. */
+- goto resume;
+- }
+-
+- *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
+- if (!*ras_if)
+- return -ENOMEM;
+-
+- **ras_if = ras_block;
+-
+- r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+- if (r) {
+- if (r == -EAGAIN) {
+- amdgpu_ras_request_reset_on_boot(adev,
+- AMDGPU_RAS_BLOCK__SDMA);
+- r = 0;
+- }
+- goto feature;
++ if (!adev->sdma.ras_if) {
++ adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++ if (!adev->sdma.ras_if)
++ return -ENOMEM;
++ adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
++ adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++ adev->sdma.ras_if->sub_block_index = 0;
++ strcpy(adev->sdma.ras_if->name, "sdma");
+ }
++ fs_info.head = ih_info.head = *adev->sdma.ras_if;
+
+- ih_info.head = **ras_if;
+- fs_info.head = **ras_if;
+-
+- r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
++ r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
++ &fs_info, &ih_info);
+ if (r)
+- goto interrupt;
+-
+- amdgpu_ras_debugfs_create(adev, &fs_info);
++ goto free;
+
+- r = amdgpu_ras_sysfs_create(adev, &fs_info);
+- if (r)
+- goto sysfs;
+-resume:
+- for (i = 0; i < adev->sdma.num_instances; i++) {
+- r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
+- AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+- if (r)
+- goto irq;
++ if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
++ for (i = 0; i < adev->sdma.num_instances; i++) {
++ r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
++ AMDGPU_SDMA_IRQ_INSTANCE0 + i);
++ if (r)
++ goto late_fini;
++ }
+ }
+
+- return 0;
+-irq:
+- amdgpu_ras_sysfs_remove(adev, *ras_if);
+-sysfs:
+- amdgpu_ras_debugfs_remove(adev, *ras_if);
+- amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-interrupt:
+- amdgpu_ras_feature_enable(adev, *ras_if, 0);
+-feature:
+- kfree(*ras_if);
+- *ras_if = NULL;
++ return 0;
++late_fini:
++ amdgpu_ras_late_fini(adev, adev->sdma.ras_if, &ih_info);
++free:
++ kfree(adev->sdma.ras_if);
+ return r;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0011-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0011-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch
new file mode 100644
index 00000000..7f1bb9b1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0011-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch
@@ -0,0 +1,206 @@
+From 20fd0fa1fd9b1ebd67a9266ebc0640f63dead6e4 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:35:50 +0800
+Subject: [PATCH 0011/1453] drm/amdgpu: switch to amdgpu_ras_late_init for gmc
+ v9 block (v2)
+
+call helper function in late init phase to handle ras init
+for gmc ip block
+
+v2: call ras_late_fini to do clean up when fail to enable interrupt
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 159 ++++++++------------------
+ 1 file changed, 47 insertions(+), 112 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 0a26107b423d..007c2ba75ac1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -762,133 +762,68 @@ static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
+ return 0;
+ }
+
+-static int gmc_v9_0_ecc_ras_block_late_init(void *handle,
+- struct ras_fs_if *fs_info, struct ras_common_if *ras_block)
+-{
+- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+- struct ras_common_if **ras_if = NULL;
+- struct ras_ih_if ih_info = {
+- .cb = gmc_v9_0_process_ras_data_cb,
+- };
+- int r;
+-
+- if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
+- ras_if = &adev->gmc.umc_ras_if;
+- else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB)
+- ras_if = &adev->gmc.mmhub_ras_if;
+- else
+- BUG();
+-
+- if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
+- amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
+- return 0;
+- }
+-
+- /* handle resume path. */
+- if (*ras_if) {
+- /* resend ras TA enable cmd during resume.
+- * prepare to handle failure.
+- */
+- ih_info.head = **ras_if;
+- r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+- if (r) {
+- if (r == -EAGAIN) {
+- /* request a gpu reset. will run again. */
+- amdgpu_ras_request_reset_on_boot(adev,
+- ras_block->block);
+- return 0;
+- }
+- /* fail to enable ras, cleanup all. */
+- goto irq;
+- }
+- /* enable successfully. continue. */
+- goto resume;
+- }
+-
+- *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
+- if (!*ras_if)
+- return -ENOMEM;
+-
+- **ras_if = *ras_block;
+-
+- r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+- if (r) {
+- if (r == -EAGAIN) {
+- amdgpu_ras_request_reset_on_boot(adev,
+- ras_block->block);
+- r = 0;
+- }
+- goto feature;
+- }
+-
+- ih_info.head = **ras_if;
+- fs_info->head = **ras_if;
+-
+- if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
+- r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
+- if (r)
+- goto interrupt;
+- }
+-
+- amdgpu_ras_debugfs_create(adev, fs_info);
+-
+- r = amdgpu_ras_sysfs_create(adev, fs_info);
+- if (r)
+- goto sysfs;
+-resume:
+- if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
+- r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+- if (r)
+- goto irq;
+- }
+-
+- return 0;
+-irq:
+- amdgpu_ras_sysfs_remove(adev, *ras_if);
+-sysfs:
+- amdgpu_ras_debugfs_remove(adev, *ras_if);
+- if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
+- amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-interrupt:
+- amdgpu_ras_feature_enable(adev, *ras_if, 0);
+-feature:
+- kfree(*ras_if);
+- *ras_if = NULL;
+- return r;
+-}
+-
+ static int gmc_v9_0_ecc_late_init(void *handle)
+ {
+ int r;
+-
++ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ struct ras_ih_if mmhub_ih_info;
+ struct ras_fs_if umc_fs_info = {
+ .sysfs_name = "umc_err_count",
+ .debugfs_name = "umc_err_inject",
+ };
+- struct ras_common_if umc_ras_block = {
+- .block = AMDGPU_RAS_BLOCK__UMC,
+- .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+- .sub_block_index = 0,
+- .name = "umc",
++ struct ras_ih_if umc_ih_info = {
++ .cb = gmc_v9_0_process_ras_data_cb,
+ };
+ struct ras_fs_if mmhub_fs_info = {
+ .sysfs_name = "mmhub_err_count",
+ .debugfs_name = "mmhub_err_inject",
+ };
+- struct ras_common_if mmhub_ras_block = {
+- .block = AMDGPU_RAS_BLOCK__MMHUB,
+- .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+- .sub_block_index = 0,
+- .name = "mmhub",
+- };
+
+- r = gmc_v9_0_ecc_ras_block_late_init(handle,
+- &umc_fs_info, &umc_ras_block);
++ if (!adev->gmc.umc_ras_if) {
++ adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++ if (!adev->gmc.umc_ras_if)
++ return -ENOMEM;
++ adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
++ adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++ adev->gmc.umc_ras_if->sub_block_index = 0;
++ strcpy(adev->gmc.umc_ras_if->name, "umc");
++ }
++ umc_ih_info.head = umc_fs_info.head = *adev->gmc.umc_ras_if;
++
++ r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
++ &umc_fs_info, &umc_ih_info);
+ if (r)
+- return r;
++ goto free;
+
+- r = gmc_v9_0_ecc_ras_block_late_init(handle,
+- &mmhub_fs_info, &mmhub_ras_block);
++ if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
++ r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
++ if (r)
++ goto umc_late_fini;
++ }
++
++ if (!adev->gmc.mmhub_ras_if) {
++ adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++ if (!adev->gmc.mmhub_ras_if)
++ return -ENOMEM;
++ adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
++ adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++ adev->gmc.mmhub_ras_if->sub_block_index = 0;
++ strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++ }
++ mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
++ r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
++ &mmhub_fs_info, &mmhub_ih_info);
++ if (r)
++ goto mmhub_late_fini;
++
++ return 0;
++mmhub_late_fini:
++ amdgpu_ras_late_fini(adev, adev->gmc.mmhub_ras_if, &mmhub_ih_info);
++umc_late_fini:
++ amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info);
++free:
++ kfree(adev->gmc.umc_ras_if);
++ kfree(adev->gmc.mmhub_ras_if);
+ return r;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0012-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0012-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch
new file mode 100644
index 00000000..36ab9762
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0012-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch
@@ -0,0 +1,141 @@
+From 2bef766ffb48049a7e9df75a55524ef9c29673ef Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 30 Aug 2019 13:34:38 +0800
+Subject: [PATCH 0012/1453] drm/amdgpu: add mmhub ras_late_init callback
+ function (v2)
+
+The function will be called in late init phase to do mmhub
+ras init
+
+v2: check ras_late_init function pointer before invoking the
+function
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 +++-----------------
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 30 +++++++++++++++++++++++
+ 3 files changed, 35 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+index 2d75ecfa199b..df04c718dfab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+@@ -23,6 +23,7 @@
+
+ struct amdgpu_mmhub_funcs {
+ void (*ras_init)(struct amdgpu_device *adev);
++ int (*ras_late_init)(struct amdgpu_device *adev);
+ void (*query_ras_error_count)(struct amdgpu_device *adev,
+ void *ras_error_status);
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 007c2ba75ac1..b4eead9a0f6b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -766,7 +766,6 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ {
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+- struct ras_ih_if mmhub_ih_info;
+ struct ras_fs_if umc_fs_info = {
+ .sysfs_name = "umc_err_count",
+ .debugfs_name = "umc_err_inject",
+@@ -774,10 +773,6 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ struct ras_ih_if umc_ih_info = {
+ .cb = gmc_v9_0_process_ras_data_cb,
+ };
+- struct ras_fs_if mmhub_fs_info = {
+- .sysfs_name = "mmhub_err_count",
+- .debugfs_name = "mmhub_err_inject",
+- };
+
+ if (!adev->gmc.umc_ras_if) {
+ adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+@@ -801,29 +796,16 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ goto umc_late_fini;
+ }
+
+- if (!adev->gmc.mmhub_ras_if) {
+- adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+- if (!adev->gmc.mmhub_ras_if)
+- return -ENOMEM;
+- adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
+- adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+- adev->gmc.mmhub_ras_if->sub_block_index = 0;
+- strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++ if (adev->mmhub_funcs->ras_late_init) {
++ r = adev->mmhub_funcs->ras_late_init(adev);
++ if (r)
++ return r;
+ }
+- mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
+- r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
+- &mmhub_fs_info, &mmhub_ih_info);
+- if (r)
+- goto mmhub_late_fini;
+-
+ return 0;
+-mmhub_late_fini:
+- amdgpu_ras_late_fini(adev, adev->gmc.mmhub_ras_if, &mmhub_ih_info);
+ umc_late_fini:
+ amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info);
+ free:
+ kfree(adev->gmc.umc_ras_if);
+- kfree(adev->gmc.mmhub_ras_if);
+ return r;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 04cd4b6f95d4..af15f4b8e3ad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -31,6 +31,7 @@
+ #include "vega10_enum.h"
+
+ #include "soc15_common.h"
++#include "amdgpu_ras.h"
+
+ #define mmDAGB0_CNTL_MISC2_RV 0x008f
+ #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
+@@ -615,6 +616,35 @@ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
+ }
+ }
+
++static int mmhub_v1_0_ras_late_init(struct amdgpu_device *adev)
++{
++ int r;
++ struct ras_ih_if mmhub_ih_info = {
++ .cb = NULL,
++ };
++ struct ras_fs_if mmhub_fs_info = {
++ .sysfs_name = "mmhub_err_count",
++ .debugfs_name = "mmhub_err_inject",
++ };
++
++ if (!adev->gmc.mmhub_ras_if) {
++ adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++ if (!adev->gmc.mmhub_ras_if)
++ return -ENOMEM;
++ adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
++ adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++ adev->gmc.mmhub_ras_if->sub_block_index = 0;
++ strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++ }
++ mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
++ r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
++ &mmhub_fs_info, &mmhub_ih_info);
++ if (r)
++ kfree(adev->gmc.mmhub_ras_if);
++ return r;
++}
++
+ const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
++ .ras_late_init = mmhub_v1_0_ras_late_init,
+ .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0013-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0013-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch
new file mode 100644
index 00000000..6c236037
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0013-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch
@@ -0,0 +1,111 @@
+From 7dd7db7e478b54b367088fd25b2c2a5c0e8241a7 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 20:57:32 +0800
+Subject: [PATCH 0013/1453] drm/amdgpu: add ras_late_init callback function for
+ nbio v7_4 (v3)
+
+ras_late_init callback function will be used to do common ras
+init in late init phase.
+
+v2: call ras_late_fini to do cleanup when fails to enable interrupt
+
+v3: rename sysfs/debugfs node name to pcie_bif_xxx
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 45 ++++++++++++++++++++++++
+ 2 files changed, 47 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index a04c5ea03418..51078da6188f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -81,12 +81,14 @@ struct amdgpu_nbio_funcs {
+ void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
+ int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
+ int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
++ int (*ras_late_init)(struct amdgpu_device *adev);
+ };
+
+ struct amdgpu_nbio {
+ const struct nbio_hdp_flush_reg *hdp_flush_reg;
+ struct amdgpu_irq_src ras_controller_irq;
+ struct amdgpu_irq_src ras_err_event_athub_irq;
++ struct ras_common_if *ras_if;
+ const struct amdgpu_nbio_funcs *funcs;
+ };
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index faf9300630a5..5e784bbd2d7f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -23,6 +23,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_atombios.h"
+ #include "nbio_v7_4.h"
++#include "amdgpu_ras.h"
+
+ #include "nbio/nbio_7_4_offset.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
+@@ -468,6 +469,49 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
+ return 0;
+ }
+
++static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev)
++{
++ int r;
++ struct ras_ih_if ih_info = {
++ .cb = NULL,
++ };
++ struct ras_fs_if fs_info = {
++ .sysfs_name = "pcie_bif_err_count",
++ .debugfs_name = "pcie_bif_err_inject",
++ };
++
++ if (!adev->nbio.ras_if) {
++ adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++ if (!adev->nbio.ras_if)
++ return -ENOMEM;
++ adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
++ adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++ adev->nbio.ras_if->sub_block_index = 0;
++ strcpy(adev->nbio.ras_if->name, "pcie_bif");
++ }
++ ih_info.head = fs_info.head = *adev->nbio.ras_if;
++ r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
++ &fs_info, &ih_info);
++ if (r)
++ goto free;
++
++ if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
++ r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
++ if (r)
++ goto late_fini;
++ r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
++ if (r)
++ goto late_fini;
++ }
++
++ return 0;
++late_fini:
++ amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
++free:
++ kfree(adev->nbio.ras_if);
++ return r;
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -493,4 +537,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
+ .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
+ .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
++ .ras_late_init = nbio_v7_4_ras_late_init,
+ };
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0014-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0014-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch
new file mode 100644
index 00000000..484e42c5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0014-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch
@@ -0,0 +1,57 @@
+From 800caee4230c35f5b7be5c155310e646a468f132 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:56:44 +0800
+Subject: [PATCH 0014/1453] drm/amdgpu: switch to amdgpu_ras_late_init for nbio
+ v7_4 (v2)
+
+call helper function in late init phase to handle ras init
+for nbio ip block
+
+v2: init local var r to 0 in case the function return failure
+on asics that don't have ras_late_init implementation
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 7f6c73493939..c6a63b2fedd5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1210,11 +1210,15 @@ static int soc15_common_early_init(void *handle)
+ static int soc15_common_late_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++ int r = 0;
+
+ if (amdgpu_sriov_vf(adev))
+ xgpu_ai_mailbox_get_irq(adev);
+
+- return 0;
++ if (adev->nbio.funcs->ras_late_init)
++ r = adev->nbio.funcs->ras_late_init(adev);
++
++ return r;
+ }
+
+ static int soc15_common_sw_init(void *handle)
+@@ -1291,6 +1295,13 @@ static int soc15_common_hw_fini(void *handle)
+ if (amdgpu_sriov_vf(adev))
+ xgpu_ai_mailbox_put_irq(adev);
+
++ if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
++ if (adev->nbio.funcs->init_ras_controller_interrupt)
++ amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
++ if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
++ amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
++ }
++
+ return 0;
+ }
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0015-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0015-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch
new file mode 100644
index 00000000..b144fc79
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0015-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch
@@ -0,0 +1,38 @@
+From 44ba17e3af7347571faaa06f34f605429c530700 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 26 Jul 2019 15:57:50 -0500
+Subject: [PATCH 0015/1453] drm/amdgpu: Extends amdgpu vm definitions (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add RW mtype introduced for arcturus.
+
+v2:
+* Don't add probe-invalidation bit from UAPI
+* Don't add unused AMDGPU_MTYPE_ definitions
+
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
+---
+ include/uapi/drm/amdgpu_drm.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 4fe35d600ab8..bbdad866e3fe 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -500,6 +500,8 @@ struct drm_amdgpu_gem_op {
+ #define AMDGPU_VM_MTYPE_CC (3 << 5)
+ /* Use UC MTYPE instead of default MTYPE */
+ #define AMDGPU_VM_MTYPE_UC (4 << 5)
++/* Use RW MTYPE instead of default MTYPE */
++#define AMDGPU_VM_MTYPE_RW (5 << 5)
+
+ struct drm_amdgpu_gem_va {
+ /** GEM object handle */
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0016-drm-amdgpu-Support-new-arcturus-mtype.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0016-drm-amdgpu-Support-new-arcturus-mtype.patch
new file mode 100644
index 00000000..7aabd199
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0016-drm-amdgpu-Support-new-arcturus-mtype.patch
@@ -0,0 +1,49 @@
+From bd6c56c6757128760adb39fa2af6da2ad86cea2c Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 26 Jul 2019 16:03:11 -0500
+Subject: [PATCH 0016/1453] drm/amdgpu: Support new arcturus mtype
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Arcturus repurposed mtype WC to RW. Modify gmc functions
+to support the new mtype
+
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
+ drivers/gpu/drm/amd/include/vega10_enum.h | 1 +
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index b4eead9a0f6b..420dcdd769ff 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -607,6 +607,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
+ case AMDGPU_VM_MTYPE_WC:
+ pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
+ break;
++ case AMDGPU_VM_MTYPE_RW:
++ pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
++ break;
+ case AMDGPU_VM_MTYPE_CC:
+ pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
+ break;
+diff --git a/drivers/gpu/drm/amd/include/vega10_enum.h b/drivers/gpu/drm/amd/include/vega10_enum.h
+index c14ba65a2415..adf1b754666e 100644
+--- a/drivers/gpu/drm/amd/include/vega10_enum.h
++++ b/drivers/gpu/drm/amd/include/vega10_enum.h
+@@ -1037,6 +1037,7 @@ TCC_CACHE_POLICY_STREAM = 0x00000001,
+ typedef enum MTYPE {
+ MTYPE_NC = 0x00000000,
+ MTYPE_WC = 0x00000001,
++MTYPE_RW = 0x00000001,
+ MTYPE_CC = 0x00000002,
+ MTYPE_UC = 0x00000003,
+ } MTYPE;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0017-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0017-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch
new file mode 100644
index 00000000..e8139798
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0017-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch
@@ -0,0 +1,121 @@
+From d1d2b216d5a46f2da102e5704980076a4f7eafe9 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 26 Aug 2019 18:39:11 -0400
+Subject: [PATCH 0017/1453] drm/amdgpu: Determing PTE flags separately for each
+ mapping (v3)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The same BO can be mapped with different PTE flags by different GPUs.
+Therefore determine the PTE flags separately for each mapping instead
+of storing them in the KFD buffer object.
+
+Add a helper function to determine the PTE flags to be extended with
+ASIC and memory-type-specific logic in subsequent commits.
+
+v2: Split Arcturus-specific MTYPE changes into separate commit
+v3: Fix return type of get_pte_flags to uint64_t
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 39 +++++++++++--------
+ 2 files changed, 24 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+index e519df3fd2b6..1af8f83f7e02 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+@@ -57,7 +57,7 @@ struct kgd_mem {
+ unsigned int mapped_to_gpu_memory;
+ uint64_t va;
+
+- uint32_t mapping_flags;
++ uint32_t alloc_flags;
+
+ atomic_t invalid;
+ struct amdkfd_process_info *process_info;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 6d021ecc8d59..f0ebe0012f52 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -356,6 +356,23 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
+ return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
+ }
+
++static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
++{
++ bool coherent = mem->alloc_flags & ALLOC_MEM_FLAGS_COHERENT;
++ uint32_t mapping_flags;
++
++ mapping_flags = AMDGPU_VM_PAGE_READABLE;
++ if (mem->alloc_flags & ALLOC_MEM_FLAGS_WRITABLE)
++ mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
++ if (mem->alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
++ mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
++
++ mapping_flags |= coherent ?
++ AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++
++ return amdgpu_gmc_get_pte_flags(adev, mapping_flags);
++}
++
+ /* add_bo_to_vm - Add a BO to a VM
+ *
+ * Everything that needs to bo done only once when a BO is first added
+@@ -404,8 +421,7 @@ static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem,
+ }
+
+ bo_va_entry->va = va;
+- bo_va_entry->pte_flags = amdgpu_gmc_get_pte_flags(adev,
+- mem->mapping_flags);
++ bo_va_entry->pte_flags = get_pte_flags(adev, mem);
+ bo_va_entry->kgd_dev = (void *)adev;
+ list_add(&bo_va_entry->bo_list, list_bo_va);
+
+@@ -1082,7 +1098,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ int byte_align;
+ u32 domain, alloc_domain;
+ u64 alloc_flags;
+- uint32_t mapping_flags;
+ int ret;
+
+ /*
+@@ -1144,16 +1159,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ adev->asic_type != CHIP_VEGAM) ?
+ VI_BO_SIZE_ALIGN : 1;
+
+- mapping_flags = AMDGPU_VM_PAGE_READABLE;
+- if (flags & ALLOC_MEM_FLAGS_WRITABLE)
+- mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
+- if (flags & ALLOC_MEM_FLAGS_EXECUTABLE)
+- mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
+- if (flags & ALLOC_MEM_FLAGS_COHERENT)
+- mapping_flags |= AMDGPU_VM_MTYPE_UC;
+- else
+- mapping_flags |= AMDGPU_VM_MTYPE_NC;
+- (*mem)->mapping_flags = mapping_flags;
++ (*mem)->alloc_flags = flags;
+
+ amdgpu_sync_create(&(*mem)->sync);
+
+@@ -1626,9 +1632,10 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
+
+ INIT_LIST_HEAD(&(*mem)->bo_va_list);
+ mutex_init(&(*mem)->lock);
+- (*mem)->mapping_flags =
+- AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
+- AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_NC;
++ (*mem)->alloc_flags =
++ ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
++ ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT) |
++ ALLOC_MEM_FLAGS_WRITABLE | ALLOC_MEM_FLAGS_EXECUTABLE;
+
+ (*mem)->bo = amdgpu_bo_ref(bo);
+ (*mem)->va = va;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0018-drm-amdgpu-Use-optimal-mtypes-and-PTE-bits-for-Arctu.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0018-drm-amdgpu-Use-optimal-mtypes-and-PTE-bits-for-Arctu.patch
new file mode 100644
index 00000000..b4ac8ad4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0018-drm-amdgpu-Use-optimal-mtypes-and-PTE-bits-for-Arctu.patch
@@ -0,0 +1,79 @@
+From 52ba813350cb57d716b6d8fb5c65ba2ba97e0651 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 26 Aug 2019 18:46:28 -0400
+Subject: [PATCH 0018/1453] drm/amdgpu: Use optimal mtypes and PTE bits for
+ Arcturus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For compute VRAM allocations on Arturus use the new RW mtype
+for non-coherent local memory, CC mtype for coherent local
+memory and PTE_SNOOPED bit for invalidating non-dirty cache
+lines on remote XGMI mappings.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Tested-by: Amber Lin <Amber.Lin@amd.com>
+Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 20 +++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++++
+ 2 files changed, 22 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index f0ebe0012f52..3e0e099d3b9b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -358,6 +358,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
+
+ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
+ {
++ struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
+ bool coherent = mem->alloc_flags & ALLOC_MEM_FLAGS_COHERENT;
+ uint32_t mapping_flags;
+
+@@ -367,8 +368,23 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
+ if (mem->alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
+ mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
+
+- mapping_flags |= coherent ?
+- AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++ switch (adev->asic_type) {
++ case CHIP_ARCTURUS:
++ if (mem->alloc_flags & ALLOC_MEM_FLAGS_VRAM) {
++ if (bo_adev == adev)
++ mapping_flags |= coherent ?
++ AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
++ else
++ mapping_flags |= AMDGPU_VM_MTYPE_UC;
++ } else {
++ mapping_flags |= coherent ?
++ AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++ }
++ break;
++ default:
++ mapping_flags |= coherent ?
++ AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++ }
+
+ return amdgpu_gmc_get_pte_flags(adev, mapping_flags);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 5251352f5922..860ab798d43a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1590,6 +1590,10 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
+ }
+ flags &= ~AMDGPU_PTE_VALID;
+ }
++ if (adev->asic_type == CHIP_ARCTURUS &&
++ !(flags & AMDGPU_PTE_SYSTEM) &&
++ mapping->bo_va->is_xgmi)
++ flags |= AMDGPU_PTE_SNOOPED;
+
+ trace_amdgpu_vm_bo_update(mapping);
+
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0019-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0019-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch
new file mode 100644
index 00000000..a189e974
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0019-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch
@@ -0,0 +1,76 @@
+From 472f84fe5027a2ee4bfbdbe1471ab0db24b5772d Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Thu, 29 Aug 2019 21:18:43 -0400
+Subject: [PATCH 0019/1453] drm/amdgpu: Remove unnecessary TLB workaround (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This workaround is better handled in user mode in a way that doesn't
+require allocating extra memory and breaking userptr BOs.
+
+The TLB bug is a performance bug, not a functional or security bug.
+Hence it is safe to remove this kernel part of the workaround to
+allow a better workaround using only virtual address alignments in
+user mode.
+
+v2: Removed VI_BO_SIZE_ALIGN definition
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 17 +----------------
+ 1 file changed, 1 insertion(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 3e0e099d3b9b..23237fa63ad6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -33,11 +33,6 @@
+ #include "amdgpu_amdkfd.h"
+ #include "amdgpu_dma_buf.h"
+
+-/* Special VM and GART address alignment needed for VI pre-Fiji due to
+- * a HW bug.
+- */
+-#define VI_BO_SIZE_ALIGN (0x8000)
+-
+ /* BO flag to indicate a KFD userptr BO */
+ #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
+
+@@ -1111,7 +1106,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ uint64_t user_addr = 0;
+ struct amdgpu_bo *bo;
+ struct amdgpu_bo_param bp;
+- int byte_align;
+ u32 domain, alloc_domain;
+ u64 alloc_flags;
+ int ret;
+@@ -1166,15 +1160,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ if ((*mem)->aql_queue)
+ size = size >> 1;
+
+- /* Workaround for TLB bug on older VI chips */
+- byte_align = (adev->family == AMDGPU_FAMILY_VI &&
+- adev->asic_type != CHIP_FIJI &&
+- adev->asic_type != CHIP_POLARIS10 &&
+- adev->asic_type != CHIP_POLARIS11 &&
+- adev->asic_type != CHIP_POLARIS12 &&
+- adev->asic_type != CHIP_VEGAM) ?
+- VI_BO_SIZE_ALIGN : 1;
+-
+ (*mem)->alloc_flags = flags;
+
+ amdgpu_sync_create(&(*mem)->sync);
+@@ -1190,7 +1175,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+
+ memset(&bp, 0, sizeof(bp));
+ bp.size = size;
+- bp.byte_align = byte_align;
++ bp.byte_align = 1;
+ bp.domain = alloc_domain;
+ bp.flags = alloc_flags;
+ bp.type = bo_type;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0020-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0020-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch
new file mode 100644
index 00000000..e88fc4bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0020-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch
@@ -0,0 +1,30 @@
+From 31b9da0e90995a28091544ea5f6e9d885a389eee Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sat, 31 Aug 2019 13:18:40 +0800
+Subject: [PATCH 0020/1453] drm/amdgpu: check mmhub_funcs pointer before
+ refering to it
+
+mmhub callback functions are not initialized for all the ASICs
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 420dcdd769ff..08a47a5785cd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -799,7 +799,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ goto umc_late_fini;
+ }
+
+- if (adev->mmhub_funcs->ras_late_init) {
++ if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+ r = adev->mmhub_funcs->ras_late_init(adev);
+ if (r)
+ return r;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0021-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0021-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch
new file mode 100644
index 00000000..b1ddce4d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0021-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch
@@ -0,0 +1,75 @@
+From e3b286656bdc64fb935d7ac14d8e1f887701f42e Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sat, 31 Aug 2019 14:20:38 +0800
+Subject: [PATCH 0021/1453] drm/amdgpu: fix memory leak when ras is not
+ supported on specific ip block
+
+free ras_if if ras is not supported
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
+ 4 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 633a70815576..4b68d213ed1e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4456,7 +4456,8 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+ if (r)
+ goto late_fini;
+- }
++ } else
++ kfree(adev->gfx.ras_if);
+
+ return 0;
+ late_fini:
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 08a47a5785cd..6a61e5c5b2ce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -797,7 +797,8 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+ if (r)
+ goto umc_late_fini;
+- }
++ } else
++ kfree(adev->gmc.umc_ras_if);
+
+ if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+ r = adev->mmhub_funcs->ras_late_init(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index af15f4b8e3ad..ab6559a2d5e8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -639,7 +639,7 @@ static int mmhub_v1_0_ras_late_init(struct amdgpu_device *adev)
+ mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
+ r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
+ &mmhub_fs_info, &mmhub_ih_info);
+- if (r)
++ if (r || !amdgpu_ras_is_supported(adev, adev->gmc.mmhub_ras_if->block))
+ kfree(adev->gmc.mmhub_ras_if);
+ return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index dbd99e8e5045..dd6e37a3c7ee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1729,7 +1729,8 @@ static int sdma_v4_0_late_init(void *handle)
+ if (r)
+ goto late_fini;
+ }
+- }
++ } else
++ kfree(adev->sdma.ras_if);
+
+ return 0;
+ late_fini:
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0022-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0022-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch
new file mode 100644
index 00000000..62dac205
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0022-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch
@@ -0,0 +1,32 @@
+From f3ed44a3dd092ff0c40de43e2d8b1bc0a7c1e058 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sat, 31 Aug 2019 14:27:13 +0800
+Subject: [PATCH 0022/1453] drm/amdgpu: only apply gds clearing workaround when
+ ras is supported
+
+gds clearing workaround should only be applied on asics that support gfx ras
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 4b68d213ed1e..f5b99dbf01b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4221,6 +4221,10 @@ static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
+ struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
+ int i, r;
+
++ /* only support when RAS is enabled */
++ if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
++ return 0;
++
+ r = amdgpu_ring_alloc(ring, 7);
+ if (r) {
+ DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0023-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0023-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch
new file mode 100644
index 00000000..bf1b81f2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0023-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch
@@ -0,0 +1,92 @@
+From 6a7d6adb05a4d13a8fba388d58a867f7a64cf5bd Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 30 Aug 2019 17:30:46 +0800
+Subject: [PATCH 0023/1453] drm/amd/powerplay: guard manual mode prerequisite
+ for clock level force
+
+Force clock level is for dpm manual mode only.
+
+Change-Id: I3b4caf3fafc72197d65e2b9255c68e40e673e25e
+Reported-by: Candice Li <candice.li@amd.com>
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Jack Gui <Jack.Gui@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++--
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 ------
+ 3 files changed, 21 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 146f6b53d89b..9aedced0ad18 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1766,6 +1766,24 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
+ return ret;
+ }
+
++int smu_force_clk_levels(struct smu_context *smu,
++ enum smu_clk_type clk_type,
++ uint32_t mask)
++{
++ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
++ int ret = 0;
++
++ if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
++ pr_debug("force clock level is for dpm manual mode only.\n");
++ return -EINVAL;
++ }
++
++ if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
++ ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
++
++ return ret;
++}
++
+ const struct amd_ip_funcs smu_ip_funcs = {
+ .name = "smu",
+ .early_init = smu_early_init,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 23171a4d9a31..aec0f099052a 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -636,8 +636,6 @@ struct smu_funcs
+ ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+ #define smu_print_clk_levels(smu, clk_type, buf) \
+ ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
+-#define smu_force_clk_levels(smu, clk_type, level) \
+- ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
+ #define smu_get_od_percentage(smu, type) \
+ ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
+ #define smu_set_od_percentage(smu, type, value) \
+@@ -833,5 +831,8 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
+ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
++int smu_force_clk_levels(struct smu_context *smu,
++ enum smu_clk_type clk_type,
++ uint32_t mask);
+
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 92c393f613d3..ed8e13c6f2fa 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -1274,14 +1274,8 @@ static int vega20_force_clk_levels(struct smu_context *smu,
+ struct vega20_dpm_table *dpm_table;
+ struct vega20_single_dpm_table *single_dpm_table;
+ uint32_t soft_min_level, soft_max_level, hard_min_level;
+- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ int ret = 0;
+
+- if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+- pr_info("force clock level is for dpm manual mode only.\n");
+- return -EINVAL;
+- }
+-
+ mutex_lock(&(smu->mutex));
+
+ soft_min_level = mask ? (ffs(mask) - 1) : 0;
+--
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0024-drm-amd-powerplay-update-cached-feature-enablement-s.patch b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0024-drm-amd-powerplay-update-cached-feature-enablement-s.patch
new file mode 100644
index 00000000..1f57773f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-5.4/linux-yocto-5.4.2/0024-drm-amd-powerplay-update-cached-feature-enablement-s.patch
@@ -0,0 +1,170 @@
+From d83f9589b37fd3fca8bf64aa4c1a6dfaa0d14b22 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 21 Aug 2019 17:19:52 +0800
+Subject: [PATCH 0024/1453] drm/amd/powerplay: update cached feature enablement
+ status V3
+
+Need to update in cache feature enablement status after pp_feature
+settings. Another fix for the commit below:
+drm/amd/powerplay: implment sysfs feature status function in smu
+
+V2: update smu_feature_update_enable_state() and relates
+V3: use bitmap_or and bitmap_andnot
+
+Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Jack Gui <Jack.Gui@amd.com>
+---