aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/dra76x.dtsi
blob: b69c7d40f5d828305bb917a0fc3c2f72d94c8bf0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "dra74x.dtsi"

/ {
	compatible = "ti,dra762", "ti,dra7";

	ocp {
		target-module@42c01900 {
			compatible = "ti,sysc-dra7-mcan", "ti,sysc";
			ranges = <0x0 0x42c00000 0x2000>;
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x42c01900 0x4>,
			      <0x42c01904 0x4>,
			      <0x42c01908 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
					 SYSC_DRA7_MCAN_ENAWAKEUP)>;
			ti,syss-mask = <1>;
			clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
			clock-names = "fck";

			m_can0: mcan@1a00 {
				compatible = "bosch,m_can";
				reg = <0x1a00 0x4000>, <0x0 0x18FC>;
				reg-names = "m_can", "message_ram";
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "int0", "int1";
				clocks = <&mcan_clk>, <&l3_iclk_div>;
				clock-names = "cclk", "hclk";
				bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
			};
		};
	};

};

&l4_per3 {
	target-module@1b0000 {			/* 0x489b0000, ap 25 34.0 */
		compatible = "ti,sysc-omap4", "ti,sysc";
		reg = <0x1b0000 0x4>,
		      <0x1b0010 0x4>;
		reg-names = "rev", "sysc";
		ti,sysc-midle = <SYSC_IDLE_FORCE>,
				<SYSC_IDLE_NO>;
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
				<SYSC_IDLE_NO>;
		clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
		clock-names = "fck";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x1b0000 0x10000>;

		cal: cal@0 {
			compatible = "ti,dra76-cal";
			reg = <0x0000 0x400>,
			      <0x0800 0x40>,
			      <0x0900 0x40>;
			reg-names = "cal_top",
				    "cal_rx_core0",
				    "cal_rx_core1";
			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
			ti,camerrx-control = <&scm_conf 0x6dc>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi2_0: port@0 {
					reg = <0>;
				};
				csi2_1: port@1 {
					reg = <1>;
				};
			};
		};
	};
};

/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
	ti,irqs-skip = <10 67 68 133 139 140>;
};

&scm_conf_clocks {
	dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_gmac_x2_ck>;
		ti,max-div = <63>;
		reg = <0x03fc>;
		ti,bit-shift=<20>;
		ti,latch-bit=<26>;
		assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
		assigned-clock-rates = <80000000>;
	};

	dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
		reg = <0x3fc>;
		ti,bit-shift = <29>;
		ti,latch-bit=<26>;
		assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
		assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
	};

	mcan_clk: mcan_clk@3fc {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
		ti,bit-shift = <27>;
		reg = <0x3fc>;
	};
};

&rtctarget {
	status = "disabled";
};

&usb4_tm {
	status = "disabled";
};

&mmc3 {
	/* dra76x is not affected by i887 */
	max-frequency = <96000000>;
};