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-rw-r--r--arch/arm64/Kconfig49
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index cf5f1dafcf74..5a785e62d882 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -539,6 +539,22 @@ config ARM64_ERRATUM_1463225
If unsure, say Y.
+config ARM64_ERRATUM_1542419
+ bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
+ default y
+ help
+ This option adds a workaround for ARM Neoverse-N1 erratum
+ 1542419.
+
+ Affected Neoverse-N1 cores could execute a stale instruction when
+ modified by another CPU. The workaround depends on a firmware
+ counterpart.
+
+ Workaround the issue by hiding the DIC feature from EL0. This
+ forces user-space to perform cache maintenance.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y
@@ -597,6 +613,31 @@ config CAVIUM_ERRATUM_30115
If unsure, say Y.
+config CAVIUM_ERRATUM_36890
+ bool "Cavium erratum 36890"
+ default y
+ help
+ Enable workaround for erratum 36890. On all ThunderX T88xx and
+ OcteonTX1 T81/T83 and some OcteonTX2 chips, the "dc zva" instruction
+ does not work all the time. This happens when there are two VAs
+ that match up with one PA; including when the two VAs match but have
+ different asids. The fix is to disable "dc zva" in userspace.
+
+ If unsure, say Y.
+
+config MRVL_ERRATUM_37119
+ bool "Marvell erratum 37119"
+ default y
+ help
+ Enable workaround for erratum 37119. On some OcteonTX2 chips,
+ while using the SSO workslots in userspace can cause problems
+ as the cache are not invalidated correctly. To workaround
+ this erratum, a local tlbi is placed before the eret.
+ This TLBI does not need to invalidate anything so a tlbi against
+ asid 0 is used.
+
+ If unsure, say Y.
+
config QCOM_FALKOR_ERRATUM_1003
bool "Falkor E1003: Incorrect translation due to ASID change"
default y
@@ -682,6 +723,14 @@ config FUJITSU_ERRATUM_010001
endmenu
+config MRVL_OCTEONTX_EL0_INTR
+ bool "Handle interrupts in EL0 via EL3"
+ default y
+ help
+ Handle certain interrupts in EL0 with the help of EL3 firmware to achieve
+ low latency and also not break task isolation.
+ Generally implemented and tested on OcteonTx and its successive
+ generation CPUs.
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