diff options
Diffstat (limited to 'arch/arm/boot/dts/mt8135.dtsi')
-rw-r--r-- | arch/arm/boot/dts/mt8135.dtsi | 259 |
1 files changed, 0 insertions, 259 deletions
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi deleted file mode 100644 index 0f291ad22d3a..000000000000 --- a/arch/arm/boot/dts/mt8135.dtsi +++ /dev/null @@ -1,259 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Joe.C <yingjoe.chen@mediatek.com> - * - */ - -#include <dt-bindings/clock/mt8135-clk.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/mt8135-resets.h> -#include <dt-bindings/pinctrl/mt8135-pinfunc.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "mediatek,mt8135"; - interrupt-parent = <&sysirq>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "mediatek,mt81xx-tz-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x001>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x100>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x101>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - trustzone-bootinfo@80002000 { - compatible = "mediatek,trustzone-bootinfo"; - reg = <0 0x80002000 0 0x1000>; - }; - }; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - clk26m: clk26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - topckgen: topckgen@10000000 { - compatible = "mediatek,mt8135-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: infracfg@10001000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - }; - - pericfg: pericfg@10003000 { - #reset-cells = <1>; - #clock-cells = <1>; - compatible = "mediatek,mt8135-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - }; - - /* - * Pinctrl access register at 0x10005000 and 0x1020c000 through - * regmap. Register 0x1000b000 is used by EINT. - */ - pio: pinctrl@10005000 { - compatible = "mediatek,mt8135-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt8135-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x80>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; - - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; - reg = <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names = "pwrap", "pwrap-bridge"; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names = "pwrap", "pwrap-bridge"; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "wrap"; - }; - - sysirq: interrupt-controller@10200030 { - compatible = "mediatek,mt8135-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200030 0 0x1c>; - }; - - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt8135-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - syscfg_pctl_b: syscfg_pctl_b@1020c000 { - compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; - reg = <0 0x1020c000 0 0x1000>; - }; - - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; - - uart0: serial@11006000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11006000 0 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11007000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11007000 0 0x400>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11008000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11008000 0 0x400>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11009000 { - compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; - reg = <0 0x11009000 0 0x400>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - }; -}; |