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-rw-r--r--arch/arm/boot/dts/armada-39x.dtsi594
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diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
deleted file mode 100644
index 9d1cac49c022..000000000000
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ /dev/null
@@ -1,594 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree Include file for Marvell Armada 39x family of SoCs.
- *
- * Copyright (C) 2015 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "Marvell Armada 39x family SoC";
- compatible = "marvell,armada390";
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "marvell,armada-390-smp";
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts-extended = <&mpic 3>;
- };
-
- soc {
- compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
- "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- controller = <&mbusc>;
- interrupt-parent = <&gic>;
- pcie-mem-aperture = <0xe0000000 0x8000000>;
- pcie-io-aperture = <0xe8000000 0x100000>;
-
- bootrom {
- compatible = "marvell,bootrom";
- reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
- };
-
- internal-regs {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
-
- L2: cache-controller@8000 {
- compatible = "arm,pl310-cache";
- reg = <0x8000 0x1000>;
- cache-unified;
- cache-level = <2>;
- arm,double-linefill-incr = <0>;
- arm,double-linefill-wrap = <0>;
- arm,double-linefill = <0>;
- prefetch-data = <1>;
- };
-
- scu@c000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0xc000 0x100>;
- };
-
- timer@c600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0xc600 0x20>;
- interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
- clocks = <&coreclk 2>;
- };
-
- gic: interrupt-controller@d000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #size-cells = <0>;
- interrupt-controller;
- reg = <0xd000 0x1000>,
- <0xc100 0x100>;
- };
-
- i2c0: i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- i2c1: i2c@11100 {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- i2c2: i2c@11200 {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11200 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- i2c3: i2c@11300 {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11300 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- uart0: serial@12000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x12000 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- uart1: serial@12100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x12100 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- uart2: serial@12200 {
- compatible = "snps,dw-apb-uart";
- reg = <0x12200 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- uart3: serial@12300 {
- compatible = "snps,dw-apb-uart";
- reg = <0x12300 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- pinctrl@18000 {
- i2c0_pins: i2c0-pins {
- marvell,pins = "mpp2", "mpp3";
- marvell,function = "i2c0";
- };
-
- uart0_pins: uart0-pins {
- marvell,pins = "mpp0", "mpp1";
- marvell,function = "ua0";
- };
-
- uart1_pins: uart1-pins {
- marvell,pins = "mpp19", "mpp20";
- marvell,function = "ua1";
- };
-
- spi1_pins: spi1-pins {
- marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
- marvell,function = "spi1";
- };
-
- nand_pins: nand-pins {
- marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
- "mpp38", "mpp28", "mpp40", "mpp42",
- "mpp35", "mpp36", "mpp25", "mpp30",
- "mpp32";
- marvell,function = "dev";
- };
- };
-
- gpio0: gpio@18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpio1: gpio@18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
- ngpios = <28>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- system-controller@18200 {
- compatible = "marvell,armada-390-system-controller",
- "marvell,armada-370-xp-system-controller";
- reg = <0x18200 0x100>;
- };
-
- gateclk: clock-gating-control@18220 {
- compatible = "marvell,armada-390-gating-clock";
- reg = <0x18220 0x4>;
- clocks = <&coreclk 0>;
- #clock-cells = <1>;
- };
-
- coreclk: mvebu-sar@18600 {
- compatible = "marvell,armada-390-core-clock";
- reg = <0x18600 0x04>;
- #clock-cells = <1>;
- };
-
- mbusc: mbus-controller@20000 {
- compatible = "marvell,mbus-controller";
- reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
- };
-
- mpic: interrupt-controller@20a00 {
- compatible = "marvell,mpic";
- reg = <0x20a00 0x2d0>, <0x21070 0x58>;
- #interrupt-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
- msi-controller;
- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- timer@20300 {
- compatible = "marvell,armada-380-timer",
- "marvell,armada-xp-timer";
- reg = <0x20300 0x30>, <0x21040 0x30>;
- interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <&mpic 5>,
- <&mpic 6>;
- clocks = <&coreclk 2>, <&coreclk 5>;
- clock-names = "nbclk", "fixed";
- };
-
- watchdog@20300 {
- compatible = "marvell,armada-380-wdt";
- reg = <0x20300 0x34>, <0x20704 0x4>,
- <0x18260 0x4>;
- clocks = <&coreclk 2>, <&refclk>;
- clock-names = "nbclk", "fixed";
- };
-
- cpurst@20800 {
- compatible = "marvell,armada-370-cpu-reset";
- reg = <0x20800 0x10>;
- };
-
- mpcore-soc-ctrl@20d20 {
- compatible = "marvell,armada-380-mpcore-soc-ctrl";
- reg = <0x20d20 0x6c>;
- };
-
- coherency-fabric@21010 {
- compatible = "marvell,armada-380-coherency-fabric";
- reg = <0x21010 0x1c>;
- };
-
- pmsu@22000 {
- compatible = "marvell,armada-390-pmsu",
- "marvell,armada-380-pmsu";
- reg = <0x22000 0x1000>;
- };
-
- xor@60800 {
- compatible = "marvell,armada-380-xor", "marvell,orion-xor";
- reg = <0x60800 0x100
- 0x60a00 0x100>;
- clocks = <&gateclk 22>;
- status = "okay";
-
- xor00 {
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- dmacap,memcpy;
- dmacap,xor;
- };
- xor01 {
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
- };
- };
-
- xor@60900 {
- compatible = "marvell,armada-380-xor", "marvell,orion-xor";
- reg = <0x60900 0x100
- 0x60b00 0x100>;
- clocks = <&gateclk 28>;
- status = "okay";
-
- xor10 {
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- dmacap,memcpy;
- dmacap,xor;
- };
- xor11 {
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
- };
- };
-
- rtc@a3800 {
- compatible = "marvell,armada-380-rtc";
- reg = <0xa3800 0x20>, <0x184a0 0x0c>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- nand_controller: nand-controller@d0000 {
- compatible = "marvell,armada370-nand-controller";
- reg = <0xd0000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coredivclk 0>;
- status = "disabled";
- };
-
- sdhci@d8000 {
- compatible = "marvell,armada-380-sdhci";
- reg-names = "sdhci", "mbus", "conf-sdio3";
- reg = <0xd8000 0x1000>,
- <0xdc000 0x100>,
- <0x18454 0x4>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gateclk 17>;
- mrvl,clk-delay-cycles = <0x1F>;
- status = "disabled";
- };
-
- coredivclk: clock@e4250 {
- compatible = "marvell,armada-390-corediv-clock",
- "marvell,armada-380-corediv-clock";
- reg = <0xe4250 0xc>;
- #clock-cells = <1>;
- clocks = <&mainpll>;
- clock-output-names = "nand";
- };
-
- thermal@e8078 {
- compatible = "marvell,armada380-thermal";
- reg = <0xe4078 0x4>, <0xe4074 0x4>;
- status = "okay";
- };
- };
-
- pcie {
- compatible = "marvell,armada-370-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- msi-parent = <&mpic>;
- bus-range = <0x00 0xff>;
-
- ranges =
- <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
- 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
- 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
- 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
- 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
- 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
- 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
- 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
- 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
- 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
-
- /*
- * This port can be either x4 or x1. When
- * configured in x4 by the bootloader, then
- * pcie@4,0 is not available.
- */
- pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
- 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie1_intc 0>,
- <0 0 0 2 &pcie1_intc 1>,
- <0 0 0 3 &pcie1_intc 2>,
- <0 0 0 4 &pcie1_intc 3>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 8>;
- status = "disabled";
-
- pcie1_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- /* x1 port */
- pcie@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
- 0x81000000 0 0 0x81000000 0x2 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2_intc 0>,
- <0 0 0 2 &pcie2_intc 1>,
- <0 0 0 3 &pcie2_intc 2>,
- <0 0 0 4 &pcie2_intc 3>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 5>;
- status = "disabled";
-
- pcie2_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- /* x1 port */
- pcie@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
- reg = <0x1800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
- 0x81000000 0 0 0x81000000 0x3 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie3_intc 0>,
- <0 0 0 2 &pcie3_intc 1>,
- <0 0 0 3 &pcie3_intc 2>,
- <0 0 0 4 &pcie3_intc 3>;
- marvell,pcie-port = <2>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 6>;
- status = "disabled";
-
- pcie3_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- /*
- * x1 port only available when pcie@1,0 is
- * configured as a x1 port
- */
- pcie@4,0 {
- device_type = "pci";
- assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
- reg = <0x2000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- interrupt-names = "intx";
- interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
- 0x81000000 0 0 0x81000000 0x4 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie4_intc 0>,
- <0 0 0 2 &pcie4_intc 1>,
- <0 0 0 3 &pcie4_intc 2>,
- <0 0 0 4 &pcie4_intc 3>;
- marvell,pcie-port = <3>;
- marvell,pcie-lane = <0>;
- clocks = <&gateclk 7>;
- status = "disabled";
-
- pcie4_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
- };
-
- spi0: spi@10600 {
- compatible = "marvell,armada-390-spi",
- "marvell,orion-spi";
- reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- spi1: spi@10680 {
- compatible = "marvell,armada-390-spi",
- "marvell,orion-spi";
- reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
- };
-
- clocks {
- /* 1 GHz fixed main PLL */
- mainpll: mainpll {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000000>;
- };
-
- /* 25 MHz reference crystal */
- refclk: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
- };
-};
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-23 05:29:20 +0000