diff options
Diffstat (limited to 'Documentation/devicetree/bindings/riscv/cpus.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 105 |
1 files changed, 77 insertions, 28 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 04819ad379c2..38c0b5213736 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -4,11 +4,12 @@ $id: http://devicetree.org/schemas/riscv/cpus.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: RISC-V bindings for 'cpus' DT nodes +title: RISC-V CPUs maintainers: - Paul Walmsley <paul.walmsley@sifive.com> - Palmer Dabbelt <palmer@sifive.com> + - Conor Dooley <conor@kernel.org> description: | This document uses some terminology common to the RISC-V community @@ -22,17 +23,36 @@ description: | two cores, each of which has two hyperthreads, could be described as having four harts. +allOf: + - $ref: /schemas/cpu.yaml# + - $ref: extensions.yaml + properties: compatible: oneOf: - items: - enum: - - sifive,rocket0 + - andestech,ax45mp + - canaan,k210 + - sifive,bullet0 - sifive,e5 + - sifive,e7 + - sifive,e71 + - sifive,rocket0 + - sifive,s7 + - sifive,u5 + - sifive,u54 + - sifive,u7 + - sifive,u74 + - sifive,u74-mc + - thead,c906 + - thead,c910 + - const: riscv + - items: + - enum: - sifive,e51 - sifive,u54-mc - - sifive,u54 - - sifive,u5 + - const: sifive,rocket0 - const: riscv - const: riscv # Simulator only description: @@ -40,34 +60,32 @@ properties: and identifies the type of the hart. mmu-type: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: - - riscv,sv32 - - riscv,sv39 - - riscv,sv48 description: Identifies the MMU address translation mode used on this hart. These values originate from the RISC-V Privileged Specification document, available from https://riscv.org/specifications/ - - riscv,isa: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: - - rv64imac - - rv64imafdc + $ref: /schemas/types.yaml#/definitions/string + enum: + - riscv,sv32 + - riscv,sv39 + - riscv,sv48 + - riscv,sv57 + - riscv,none + + riscv,cbom-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 description: - Identifies the specific RISC-V instruction set architecture - supported by the hart. These are documented in the RISC-V - User-Level ISA document, available from - https://riscv.org/specifications/ + The blocksize in bytes for the Zicbom cache operations. - While the isa strings in ISA specification are case - insensitive, letters in the riscv,isa string must be all - lowercase to simplify parsing. + riscv,cboz-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicboz cache operations. + # RISC-V has multiple properties for cache op block sizes as the sizes + # differ between individual CBO extensions + cache-op-block-size: false # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false @@ -89,10 +107,35 @@ properties: - compatible - interrupt-controller + cpu-idle-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + description: | + List of phandles to idle state nodes supported + by this hart (see ./idle-states.yaml). + + capacity-dmips-mhz: + description: + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + +anyOf: + - required: + - riscv,isa + - required: + - riscv,isa-base + +dependencies: + riscv,isa-base: [ "riscv,isa-extensions" ] + riscv,isa-extensions: [ "riscv,isa-base" ] + required: - - riscv,isa - interrupt-controller +unevaluatedProperties: false + examples: - | // Example 1: SiFive Freedom U540G Development Kit @@ -108,7 +151,9 @@ examples: i-cache-sets = <128>; i-cache-size = <16384>; reg = <0>; - riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c"; + cpu_intc0: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -131,8 +176,10 @@ examples: i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <1>; - riscv,isa = "rv64imafdc"; tlb-split; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + cpu_intc1: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -150,8 +197,10 @@ examples: device_type = "cpu"; reg = <0>; compatible = "riscv"; - riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + interrupt-controller { #interrupt-cells = <1>; interrupt-controller; |