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Diffstat (limited to 'Documentation/devicetree/bindings/arm/coresight.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/coresight.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 8a88ddebc1a2..248acd840d11 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -99,6 +99,10 @@ its hardware characteristcs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. + * cache-lock: Enables cache locking for the allocated trace buffer. + As of now, this is supported only for secure buffer allocations + on Marvell OcteonTx2 platform. + * Optional property for CATU : * interrupts : Exactly one SPI may be listed for reporting the address error |