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authorBruce Ashfield <bruce.ashfield@windriver.com>2013-04-05 00:11:33 -0400
committerBruce Ashfield <bruce.ashfield@windriver.com>2016-08-30 12:12:25 -0400
commitc9c8f1ef8a5acc293e6fadf6d192bd333748b17a (patch)
treefa31c5e9c82344768fd65edef49b159d79b53f7b
parentee5d1631fd60f07837f34e18066f7e7bb34cef7b (diff)
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oprofile/mips: do not set perf_irq for qemu mips 64v4.8/standard/mti-malta64
In a similar manner to the following commit: oprofile/mips: override register writes for qemu mips 64 Even when oprofile timer mode is enabled, during oprofile arch init there are writes to registers that do not exist in the qemu malta 64 bit pseudo machine. To allow initialization to continue and the fallback to oprofile timer mode to take effect, we stub the register writes. These two defines are only appropriate for qemu-system-mips. This should not merge to a common location, and only be applied to emulated boards. We also cannot set perf_irq to mipsxx_perfcount_handler during oprofile arch init, or unsupported register reads will be triggered before the fallback to timer mode occurs. This commit is also only appropriate for qemu mips based boards, and should not be applied to any general branch. Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index c0c278fc0470..d953bb96150c 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -449,7 +449,9 @@ static int __init mipsxx_init(void)
}
save_perf_irq = perf_irq;
+#if 0
perf_irq = mipsxx_perfcount_handler;
+#endif
if (get_c0_perfcount_int)
perfcount_irq = get_c0_perfcount_int();