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Add Valley Island Platform (Bayley Bay and Bakersport CRB)
platform-specific I/Os scc and config files.
By default, enable PCI mode enumeration.
Signed-off-by: Ong, Boon Leong <boon.leong.ong@intel.com>
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Allow PCI SPI-PXA2XX controller to enable DMA capapability
by providing channel id and slave id.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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This is enable the PCI mode support for Intel BYT SPI controller.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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SD Card v3.01 in the market is not compatible with BYT SDHC IP
in SoC because this IP only support SD v3.0 only. So, we are
forcing DDR50 mode to always step down to SDR25.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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A host controller for a SD card may need a GPIO
for card detect in order to wake up from runtime
suspend when a card is inserted. If that GPIO is
not configured, then the host controller will not
wake up. Fix that for the affected devices by not
enabling runtime PM unless the GPIO is successfully
set up.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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add PCI ID of Intel BayTrail SMBus controller.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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this commit enables the following:
- setup clock tree for PCI mode SPI, DMA and PWM host
as the controller drivers require clock information during
device/driver probe
- register SPI slave
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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allow CONFIG_X86_INTEL_LPSS to be set when ACPI
or PCI is set.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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Instead of always depending on formula to calculate the HCNT and LCNT set
the HCNT, LCNT and SDA if the target values are known beforehand.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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For Intel BayTrail, enable i2c-designware-pci host controller
to support 10-bit addressing mode functionality.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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This is to enable PCI mode of Intel BayTrail LPSS I2C.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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This is the PCI part of the DesignWare DMAC driver.
The controller is usually used in the Intel hardware such as Medfield.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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Intel BayTrail LPSS includes two PWM controllers which can be
enumerated from ACPI namespace.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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This improves the accuracy of base_unit calculation
so that the resulting PWM frequency will be more optimal.
The change in the patch is meant for Intel BayTrail only
because pwm-lpss.c is only used for this platform.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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The Intel BayTrail PWM driver is extended to support PCI mode
along with the ACPI mode. A new file pwm-lpss-pci.c is added
to support the LPSS PWM PCI functionality.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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Add support for Intel Low Power I/O subsystem PWM controllers found
on some newer intel chipsets.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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This is to enable 1M, 2M, 3M & 4M baud-rate support for BYT ACPI mode
HSUART.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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BayTrail ACPI mode SPI is not read/writing correctly at low speeds
using DMA mode. Changing DMA SRC_MSIZE and
DEST_MSIZE of SPI FIFO side from 16 to 32 fixes the issue.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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Rename the functions from ce4100_xxx to pxa2xx_spi_pci_xxx
to clarify that this is a generic PCI glue layer.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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Due to power saving purpose, BIOS disabled ulpi phy refclk by default.
Hence, the refclk will only be enabled during device/driver probing.
and disabled during driver removal.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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To remove features/valleyisland-io/valleyisland-io.scc
includes from valleyisland.scc and valleyisland32.scc.
Instead, this feature should be added to KERNEL_FEATURES in
linux-yocto_3.8.bbappend of meta-valleyisland.
Signed-off-by: Ong, Boon Leong <boon.leong.ong@intel.com>
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Update valleyisland bsp config file to enable SMBus,
PWM, USB Device and ICH lineage SATA host controller.
Signed-off-by: Chew Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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clk/x86: Add clock framework support for Baytrail ACPI mode LPIO devices.
The ACPI mode LPIO devices inclusive of SPI, HSUART, I2C and DMA.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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x86: add support for Intel Low Power Subsystem
We are starting to see traditional SoC peripherals also in the x86 world in
chips like Intel Lynxpoint. Typically we already have a Linux driver for
the peripheral but it takes advantage of the common clk framework to
control and retrieve information about the peripheral clock.
So far there hasn't been a standard way on x86 to pass information such as
clock rate from whatever the configuration system is used to the driver,
but instead different variations have emerged, like adding this information
to the platform data.
Solve this by adding a new config option X86_INTEL_LPSS. If this is
selected we enable common clk framework (and everything else) that is
needed to support the Intel LPSS drivers.
Enabling common clk framework on x86 was originally proposed by Mark Brown.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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ata_piix: added IDE mode PCI device IDs for Baytrail.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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mmc: Baytrail has three SDHC controllers, namely eMMC controller,
SDIO controller and SDCARD controller. The controllers can be PCI or
ACPI enumerated.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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sysfs: Functions for adding/removing symlinks to/from attribute groups
The most convenient way to expose ACPI power resources lists of a
device is to put symbolic links to sysfs directories representing
those resources into special attribute groups in the device's sysfs
directory. For this purpose, it is necessary to be able to add
symbolic links to attribute groups.
For this reason, add sysfs helper functions for adding/removing
symbolic links to/from attribute groups, sysfs_add_link_to_group()
and sysfs_remove_link_from_group(), respectively.
This change set includes a build fix from David Rientjes.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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x86/PCI: setup data may be in highmem
pcibios_add_device() assumes that the physical addresses stored in
setup_data are accessible via the direct kernel mapping, and that
calling phys_to_virt() is valid. This isn't guaranteed to be true on x86
where the direct mapping range is much smaller than on x86-64.
Calling phys_to_virt() on a highmem address results in the following,
BUG: unable to handle kernel paging request at 39a3c198
IP: [<c262be0f>] pcibios_add_device+0x2f/0x90
*pde = 00000000
Oops: 0000 [#1] SMP
Modules linked in:
Pid: 1, comm: swapper/0 Tainted: G W I 3.9.0-rc2+ #280
EIP: 0060:[<c262be0f>] EFLAGS: 00010206 CPU: 1
EIP is at pcibios_add_device+0x2f/0x90
EAX: f6258800 EBX: f6258800 ECX: 79a3c190 EDX: 39a3c190
ESI: f62d9814 EDI: f6258864 EBP: f60add38 ESP: f60add2c
DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
CR0: 8005003b CR2: 39a3c198 CR3: 02b91000 CR4: 001007d0
DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000
DR6: ffff0ff0 DR7: 00000400
Process swapper/0 (pid: 1, ti=f60ac000 task=f60b0000 task.ti=f60ac000)
Stack:
f6258800 f62d9814 f6258864 f60add4c c2370c73 00000000 f62d9800 00000000
f60add6c c274640b 0000ea60 f6258800 0f008086 f62d9800 f62d9800 00000000
f60add84 c2370d08 00000000 00000008 f62d9800 00000000 f60adda4 c2371904
Call Trace:
[<c2370c73>] pci_device_add+0xe3/0x130
[<c274640b>] pci_scan_single_device+0x8b/0xb0
[<c2370d08>] pci_scan_slot+0x48/0x100
[<c2371904>] pci_scan_child_bus+0x24/0xc0
[<c262a7b0>] pci_acpi_scan_root+0x2c0/0x490
[<c23b7203>] acpi_pci_root_add+0x312/0x42f
[<c23b29d7>] ? acpi_device_notify_fixed+0x1d/0x1d
[<c23b36a8>] acpi_bus_device_attach+0x77/0xdd
[<c23cb6be>] acpi_ns_walk_namespace+0xb1/0x163
[<c23b3631>] ? acpi_bus_type_and_status+0x82/0x82
[<c23cbd4e>] acpi_walk_namespace+0x7e/0xa8
[<c23b3631>] ? acpi_bus_type_and_status+0x82/0x82
[<c23b46e0>] acpi_bus_scan+0x9a/0xa6
[<c23b3631>] ? acpi_bus_type_and_status+0x82/0x82
[<c2b17ec9>] acpi_scan_init+0x51/0x144
[<c2b252a2>] ? pci_mmcfg_late_init+0x49/0x4b
[<c2b17cdc>] acpi_init+0x224/0x28c
[<c2001144>] do_one_initcall+0x34/0x170
[<c2b17ab8>] ? acpi_sleep_proc_init+0x2e/0x2e
[<c2aeeb83>] kernel_init_freeable+0x119/0x1b6
[<c2aee4da>] ? do_early_param+0x74/0x74
[<c2743f10>] kernel_init+0x10/0xd0
[<c2765697>] ret_from_kernel_thread+0x1b/0x28
[<c2743f00>] ? rest_init+0x60/0x60
The most reliable way to trigger this crash seems to be booting a 32-bit
kernel via the EFI boot stub.
The solution is to use ioremap() instead of phys_to_virt() to map the
setup data into the kernel address space.
Tested-by: Jani Nikula <jani.nikula@intel.com>
Cc: Matthew Garrett <mjg59@srcf.ucam.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Seth Forshee <seth.forshee@canonical.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Matt Fleming <matt.fleming@intel.com>
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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hda: Add HDA controller PCI ID with CPT parameters.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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Baytrail has 2 USB controllers, namely, EHCI controller and XHCI
controller. This patch will add PCI device ID for Baytrail to have
USB EHCI and XHCI controller support.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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x86: This is to resolve the compile error if the kernel is built for
platform with no ACPI support. It is expected the PCI mode LPSS
devices will still work on system with no ACPI support.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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x86/platform: This board file includes clock tree setup and
register SPI devices.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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spidev: Enable SPI support in ACPI mode.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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[backport of commit 6f3e186bc7721c5b24ad90d4a751cccfccd445e6]
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Add Valley Island Platform (Bayley Bay and Bakersport CRB)
platform-specific I/Os scc and config files.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Bakersport CRB) scc and config files
To create Valley Island Platform (Bayley Bay and Bakersport CRB) cfg
and scc files under meta branch.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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This commit will turn on some legacy block drivers configuration,
e.g. SMBus, LPC-ICH, and Watchdog timer.
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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standard/common-pc-64/base branch
Remove "branch haswell-wc" from haswell-wc-standard.scc
so that "haswell-wc" BSP uses standard/common-pc-64/base branch
on linux-yocto-3.8 repo.
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
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Include the input.scc to get the CONFIG_INPUT_EVDEV enabled.
The evdev kernel driver is needed to create /dev/input/event* devices.
These devices are used by Xserver to connect to keyboard & mouse kind
of input devices. Without this change some of the BSPs need
AutoAddDevices = false
in their xorg.conf, which is considered as an undesired hack around
the issue.
Fixes Bug:
[YOCTO #5279]
Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
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Right now the CONFIG_INPUT_* options are scattered at various
places in config fragments. The plan is to get them in one place
for cleanliness.
To begin with a new feature is created with name input.scc.
And it is populated with the needed CONFIG_INPUT_EVDEV .
Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
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and config files
To create Haswell Platform (Walnut Canyon CRB) cfg & scc files under meta branch
Signed-off-by Ong Boon Leong <boon.leong.ong@intel.com>
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Enable GMA3600 (as used in the Cedar Trail platform), and merge in the GMA600
fragment.
Signed-off-by: Ross Burton <ross.burton@intel.com>
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These are fairly ubiquitous among modern Intel platforms, so add them to
common-pc.
Signed-off-by: Ross Burton <ross.burton@intel.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Add standalone CONFIG_RFKILL feature for cross-BSP/driver use.
Signed-off-by: Ross Burton <ross.burton@intel.com>
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iwlagn doesn't exist in recent kernels, instead the "next gen AGN" driver is
called iwlwifi (was iwlagn) and the 3945/4965 driver is called iwlegacy.
Signed-off-by: Ross Burton <ross.burton@intel.com>
Acked-by: Darren Hart <dvhart@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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This gives control on including these modules in the final image.
Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Disable USB autosuspend configuration. This is causing unusable
keyboards & mice issues for many Intel BSPs.
Also by default this config is disabled in the kernel.
Fixes bug:
[YOCTO #4992]
Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Ong, Boon Leong
Bruce Ashfield
Chang, Rebecca Swee Fun
Nitin A Kamble
Ross Burton